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456 Commits

Author SHA1 Message Date
Dario Nieuwenhuis
0f04776eaa rcc: l0, l1, l4: add missing enums. 2022-01-04 23:56:52 +01:00
Dario Nieuwenhuis
7061d52abd pwr f4, f7: cleanup a bit 2022-01-04 21:10:54 +01:00
Dominik Boehi
bb6321bc87 Extract flash information for STM32WB by looking for FLASH_REG_BASE define 2022-01-04 19:38:05 +01:00
Dominik Boehi
d8189255fa Add Flash, RTC, PWR for STM32WB55, fix IPCC CPU registers 2022-01-04 18:52:34 +01:00
Sjoerd Simons
8ed35ce95b Add registers for F1 ADC block 2021-12-29 15:51:27 +01:00
Dario Nieuwenhuis
0e9fa2f438 Merge pull request #109 from VasanthakumarV/f3-registers 
Add `SYSCFG`, `PWR`, `FLASH` and `SPI` registers for `STM32F3`
 2021-12-16 08:12:07 +01:00
VasanthakumarV
b9193128ed [manual] Make EXTICRx in SYSCFG register an array 
The four variants of EXTICRx has been manually edited into
an array of size and stride four.
The corresponding fieldset was also manually changed.
 2021-12-09 13:47:55 +05:30
VasanthakumarV
fdf0cc95b9 [manual] Deduplicate PLLSRC entry of RCC_CFGR register 
I have manually removed the single bit PLLSRC under RCC_CFGR register,
and I have manually updated the `enum/PLLSRC` to have 3 variants to match
the bit_size of PLLSRC.
 2021-12-09 13:24:25 +05:30
Matous Hybl
8402040d17 Fix generation of FMC peripheral in chip yamls. Add FMC registers. 2021-12-08 20:01:57 +01:00
VasanthakumarV
ef950a6feb [generate] Create SYSCFG, PWR, FLASH register files 2021-12-08 15:43:23 +05:30
Dario Nieuwenhuis
f6c9772cf4 usart: make v1 and v2 more consistent. 2021-12-08 04:48:21 +01:00
Dario Nieuwenhuis
df6b1a13b0 rcc_f3: add lots of missing stuff. 2021-11-28 23:25:16 +01:00
Dario Nieuwenhuis
3780dbab57 rcc_l5: fix typo 2021-11-28 22:45:06 +01:00
Dario Nieuwenhuis
2e8c0bc791 Fix stm32u5 accidentally removed fieldset/PRIVCFGR 2021-11-27 02:32:51 +01:00
Dario Nieuwenhuis
353411841c stm32g4 support. 2021-11-27 02:20:17 +01:00
Dario Nieuwenhuis
6af084d858 SYSCFG_H7: random typo fix 2021-11-27 02:19:55 +01:00
Dario Nieuwenhuis
b630a96365 PWR: arrayify PUCRx, PDCRx 2021-11-27 02:19:38 +01:00
Dario Nieuwenhuis
0dcaaa07fe cleanup spi v1/f1, add missing i2s stuff 2021-11-17 21:30:52 +01:00
Dario Nieuwenhuis
c6c5c099bb fmt all register yamls 2021-11-17 21:23:26 +01:00
Bob McWhirter
e501a9746f Complete enum cleanup. 2021-11-11 14:52:45 -05:00
Bob McWhirter
91c77958bd Remove some useless enums. 
Apply better variant names to some enums.
 2021-11-11 14:09:49 -05:00
Bob McWhirter
117e3f3f4b Clean up some enum variants, reduce some enums that duplicate. 2021-11-11 10:25:04 -05:00
Matous Hybl
bfc7856d75 Fix DCMI reset. 2021-11-10 17:31:06 +01:00
Bob McWhirter
d2e9ef3622 U5 FLASH and RCC. 2021-11-08 13:48:03 -05:00
Matous Hybl
6ef7659b9d Add support for H723 RCC differences. 2021-11-04 15:26:52 +01:00
Matous Hybl
3d7e46e6c9 Fix v1c ethernet definition. 2021-11-03 10:13:15 +01:00
Bob McWhirter
21f31372a6 Adjust the d script. 
Extract some peripherals for U5.
Update parse.py for some U5 perculiarities.
 2021-11-02 12:02:38 -04:00
Ben Gamari
2f42ebcd2c Add support for LPTIM peripherals 2021-10-26 17:55:48 +02:00
Matous Hybl
2e1302c4e8 Support for STM32F767ZI and basic support for the rest of the family. 2021-10-25 10:38:28 +02:00
Tobias Pisani
b8de47fa04 feat: Add F1 SPI registers 2021-10-06 20:51:27 +02:00
Dario Nieuwenhuis
f6ce6dc36b CRC register cleanup 2021-09-27 00:26:24 +02:00
Joshua Salzedo
24dabf68e5 Add three distinct versions of CRC 
- remove F4 specific version
 2021-09-26 14:58:47 -07:00
Joshua Salzedo
a8a8b88661 add CRC32 peripheral for the F4 family 2021-09-24 16:59:18 -07:00
Vincent Stakenburg
97fd020941 add l4 flash register 2021-09-24 16:45:59 +02:00
Mariusz Ryndzionek
8dde100c15 Updated register mapping for STM32 F1 AFIO 2021-09-23 18:54:22 +02:00
Dario Nieuwenhuis
5dec590202 Merge pull request #85 from mryndzionek/stm32f1_support 
Add initial register mapping for STM32 F1 AFIO and FLASH
 2021-09-23 17:36:38 +02:00
Ulf Lilleengen
a302947e87 Add PWR register block and fix RCC register block 2021-09-23 14:40:59 +02:00
Mariusz Ryndzionek
fbea23bd00 Added missing FLASH registers (generated automatically) 2021-09-23 07:09:11 +02:00
Mariusz Ryndzionek
c0938c9102 Add initial register mapping for STM32 F1 AFIO and FLASH 2021-09-22 18:22:36 +02:00
Ulf Lilleengen
9f1bd7d0d0 Update chip yaml 2021-09-15 14:47:33 +02:00
Dario Nieuwenhuis
616a2779d0 Merge pull request #82 from bgamari/stm32g0 
Fix ADC register layout on STM32G0
 2021-08-31 22:21:51 +02:00
Ulf Lilleengen
902b9a6986 Add PWR peripheral for STM32WL5 2021-08-31 14:34:54 +02:00
Ben Gamari
3a88360dc6 Add PWR registers for STM32G0 2021-08-31 01:46:26 -04:00
Ben Gamari
5366833cbd Introduce ADC register set for STM32G0 2021-08-31 01:46:02 -04:00
Dario Nieuwenhuis
deb37365d7 exti: g0 and l5 are 8 bits per line... 2021-08-20 01:26:33 +02:00
Dario Nieuwenhuis
8534ae884d rcc: make GPIO EN/RST regs naming consistent. 2021-08-19 23:50:42 +02:00
Dario Nieuwenhuis
3b6363dffb wl rcc: rename SPI2S2 -> SPI2 2021-08-19 22:37:07 +02:00
Dario Nieuwenhuis
49e579e97f Add F2 RCC 2021-08-19 22:12:39 +02:00
Dario Nieuwenhuis
e289dd883f Cleanup EXTI 2021-08-19 21:54:22 +02:00
Dario Nieuwenhuis
701ab04c2a Cleanup SYSCFG naming 2021-08-19 21:28:32 +02:00