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Merge pull request #82 from bgamari/stm32g0

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Fix ADC register layout on STM32G0
This commit is contained in:
Dario Nieuwenhuis 2021-08-31 22:21:51 +02:00 committed by GitHub
commit 616a2779d0
3 changed files with 1443 additions and 1 deletions
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data/registers/adc_g0.yaml Normal file
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---
block/ADC:
description: Analog to Digital Converter
items:
- name: ISR
description: ADC interrupt and status register
byte_offset: 0
fieldset: ISR
- name: IER
description: ADC interrupt enable register
byte_offset: 4
fieldset: IER
- name: CR
description: ADC control register
byte_offset: 8
fieldset: CR
- name: CFGR1
description: ADC configuration register 1
byte_offset: 12
fieldset: CFGR1
- name: CFGR2
description: ADC configuration register 2
byte_offset: 16
fieldset: CFGR2
- name: SMPR
description: ADC sampling time register
byte_offset: 20
fieldset: SMPR
- name: AWD1TR
description: watchdog threshold register
byte_offset: 32
fieldset: AWD1TR
- name: AWD2TR
description: watchdog threshold register
byte_offset: 36
fieldset: AWD2TR
- name: CHSELR
description: channel selection register
byte_offset: 40
fieldset: CHSELR
- name: CHSELR_1
description: channel selection register CHSELRMOD = 1 in ADC_CFGR1
byte_offset: 40
fieldset: CHSELR_1
- name: AWD3TR
description: watchdog threshold register
byte_offset: 44
fieldset: AWD3TR
- name: DR
description: ADC group regular conversion data register
byte_offset: 64
access: Read
fieldset: DR
- name: AWD2CR
description: ADC analog watchdog 2 configuration register
byte_offset: 160
fieldset: AWD2CR
- name: AWD3CR
description: ADC analog watchdog 3 configuration register
byte_offset: 164
fieldset: AWD3CR
- name: CALFACT
description: ADC calibration factors register
byte_offset: 180
fieldset: CALFACT
- name: CCR
description: ADC common control register
byte_offset: 776
fieldset: CCR
- name: HWCFGR6
description: Hardware Configuration Register
byte_offset: 984
fieldset: HWCFGR6
- name: HWCFGR5
description: Hardware Configuration Register
byte_offset: 988
fieldset: HWCFGR5
- name: HWCFGR4
description: Hardware Configuration Register
byte_offset: 992
fieldset: HWCFGR4
- name: HWCFGR3
description: Hardware Configuration Register
byte_offset: 996
fieldset: HWCFGR3
- name: HWCFGR2
description: Hardware Configuration Register
byte_offset: 1000
fieldset: HWCFGR2
- name: HWCFGR1
description: Hardware Configuration Register
byte_offset: 1004
fieldset: HWCFGR1
- name: HWCFGR0
description: Hardware Configuration Register
byte_offset: 1008
access: Read
fieldset: HWCFGR0
- name: VERR
description: EXTI IP Version register
byte_offset: 1012
access: Read
fieldset: VERR
- name: IPIDR
description: EXTI Identification register
byte_offset: 1016
access: Read
fieldset: IPIDR
- name: SIDR
description: EXTI Size ID register
byte_offset: 1020
access: Read
fieldset: SIDR
fieldset/AWD1TR:
description: watchdog threshold register
fields:
- name: LT1
description: ADC analog watchdog 1 threshold low
bit_offset: 0
bit_size: 12
- name: HT1
description: ADC analog watchdog 1 threshold high
bit_offset: 16
bit_size: 12
fieldset/AWD2CR:
description: ADC analog watchdog 2 configuration register
fields:
- name: AWD2CH
description: ADC analog watchdog 2 monitored channel selection
bit_offset: 0
bit_size: 19
fieldset/AWD2TR:
description: watchdog threshold register
fields:
- name: LT2
description: ADC analog watchdog 2 threshold low
bit_offset: 0
bit_size: 12
- name: HT2
description: ADC analog watchdog 2 threshold high
bit_offset: 16
bit_size: 12
fieldset/AWD3CR:
description: ADC analog watchdog 3 configuration register
fields:
- name: AWD3CH
description: ADC analog watchdog 3 monitored channel selection
bit_offset: 0
bit_size: 19
fieldset/AWD3TR:
description: watchdog threshold register
fields:
- name: LT3
description: ADC analog watchdog 3 threshold high
bit_offset: 0
bit_size: 12
- name: HT3
description: ADC analog watchdog 3 threshold high
bit_offset: 16
bit_size: 12
fieldset/CALFACT:
description: ADC calibration factors register
fields:
- name: CALFACT
description: ADC calibration factor in single-ended mode
bit_offset: 0
bit_size: 7
fieldset/CCR:
description: ADC common control register
fields:
- name: PRESC
description: ADC prescaler
bit_offset: 18
bit_size: 4
- name: VREFEN
description: VREFINT enable
bit_offset: 22
bit_size: 1
- name: TSEN
description: Temperature sensor enable
bit_offset: 23
bit_size: 1
- name: VBATEN
description: VBAT enable
bit_offset: 24
bit_size: 1
fieldset/CFGR1:
description: ADC configuration register 1
fields:
- name: DMAEN
description: ADC DMA transfer enable
bit_offset: 0
bit_size: 1
- name: DMACFG
description: ADC DMA transfer configuration
bit_offset: 1
bit_size: 1
- name: SCANDIR
description: Scan sequence direction
bit_offset: 2
bit_size: 1
- name: RES
description: ADC data resolution
bit_offset: 3
bit_size: 2
enum: RES
- name: ALIGN
description: ADC data alignement
bit_offset: 5
bit_size: 1
- name: EXTSEL
description: ADC group regular external trigger source
bit_offset: 6
bit_size: 3
- name: EXTEN
description: ADC group regular external trigger polarity
bit_offset: 10
bit_size: 2
- name: OVRMOD
description: ADC group regular overrun configuration
bit_offset: 12
bit_size: 1
- name: CONT
description: ADC group regular continuous conversion mode
bit_offset: 13
bit_size: 1
- name: WAIT
description: Wait conversion mode
bit_offset: 14
bit_size: 1
- name: AUTOFF
description: Auto-off mode
bit_offset: 15
bit_size: 1
- name: DISCEN
description: ADC group regular sequencer discontinuous mode
bit_offset: 16
bit_size: 1
- name: CHSELRMOD
description: Mode selection of the ADC_CHSELR register
bit_offset: 21
bit_size: 1
- name: AWD1SGL
description: ADC analog watchdog 1 monitoring a single channel or all channels
bit_offset: 22
bit_size: 1
- name: AWD1EN
description: ADC analog watchdog 1 enable on scope ADC group regular
bit_offset: 23
bit_size: 1
- name: AWDCH1CH
description: ADC analog watchdog 1 monitored channel selection
bit_offset: 26
bit_size: 5
fieldset/CFGR2:
description: ADC configuration register 2
fields:
- name: OVSE
description: ADC oversampler enable on scope ADC group regular
bit_offset: 0
bit_size: 1
- name: OVSR
description: ADC oversampling ratio
bit_offset: 2
bit_size: 3
- name: OVSS
description: ADC oversampling shift
bit_offset: 5
bit_size: 4
- name: TOVS
description: ADC oversampling discontinuous mode (triggered mode) for ADC group regular
bit_offset: 9
bit_size: 1
- name: LFTRIG
description: Low frequency trigger mode enable
bit_offset: 29
bit_size: 1
- name: CKMODE
description: ADC clock mode
bit_offset: 30
bit_size: 2
fieldset/CHSELR:
description: channel selection register
fields:
- name: CHSEL
description: Channel-x selection
bit_offset: 0
bit_size: 19
fieldset/CHSELR_1:
description: channel selection register CHSELRMOD = 1 in ADC_CFGR1
fields:
- name: SQ1
description: conversion of the sequence
bit_offset: 0
bit_size: 4
- name: SQ2
description: conversion of the sequence
bit_offset: 4
bit_size: 4
- name: SQ3
description: conversion of the sequence
bit_offset: 8
bit_size: 4
- name: SQ4
description: conversion of the sequence
bit_offset: 12
bit_size: 4
- name: SQ5
description: conversion of the sequence
bit_offset: 16
bit_size: 4
- name: SQ6
description: conversion of the sequence
bit_offset: 20
bit_size: 4
- name: SQ7
description: conversion of the sequence
bit_offset: 24
bit_size: 4
- name: SQ8
description: conversion of the sequence
bit_offset: 28
bit_size: 4
fieldset/CR:
description: ADC control register
fields:
- name: ADEN
description: ADC enable
bit_offset: 0
bit_size: 1
- name: ADDIS
description: ADC disable
bit_offset: 1
bit_size: 1
- name: ADSTART
description: ADC group regular conversion start
bit_offset: 2
bit_size: 1
- name: ADSTP
description: ADC group regular conversion stop
bit_offset: 4
bit_size: 1
- name: ADVREGEN
description: ADC voltage regulator enable
bit_offset: 28
bit_size: 1
- name: ADCAL
description: ADC calibration
bit_offset: 31
bit_size: 1
fieldset/DR:
description: ADC group regular conversion data register
fields:
- name: regularDATA
description: ADC group regular conversion data
bit_offset: 0
bit_size: 16
fieldset/HWCFGR0:
description: Hardware Configuration Register
fields:
- name: NUM_CHAN_24
description: NUM_CHAN_24
bit_offset: 0
bit_size: 4
- name: EXTRA_AWDS
description: Extra analog watchdog
bit_offset: 4
bit_size: 4
- name: OVS
description: Oversampling
bit_offset: 8
bit_size: 4
fieldset/HWCFGR1:
description: Hardware Configuration Register
fields:
- name: CHMAP3
description: Input channel mapping
bit_offset: 0
bit_size: 5
- name: CHMAP2
description: Input channel mapping
bit_offset: 8
bit_size: 5
- name: CHMAP1
description: Input channel mapping
bit_offset: 16
bit_size: 5
- name: CHMAP0
description: Input channel mapping
bit_offset: 24
bit_size: 5
fieldset/HWCFGR2:
description: Hardware Configuration Register
fields:
- name: CHMAP7
description: Input channel mapping
bit_offset: 0
bit_size: 5
- name: CHMAP6
description: Input channel mapping
bit_offset: 8
bit_size: 5
- name: CHMAP5
description: Input channel mapping
bit_offset: 16
bit_size: 5
- name: CHMAP4
description: Input channel mapping
bit_offset: 24
bit_size: 5
fieldset/HWCFGR3:
description: Hardware Configuration Register
fields:
- name: CHMAP11
description: Input channel mapping
bit_offset: 0
bit_size: 5
- name: CHMAP10
description: Input channel mapping
bit_offset: 8
bit_size: 5
- name: CHMAP9
description: Input channel mapping
bit_offset: 16
bit_size: 5
- name: CHMAP8
description: Input channel mapping
bit_offset: 24
bit_size: 5
fieldset/HWCFGR4:
description: Hardware Configuration Register
fields:
- name: CHMAP15
description: Input channel mapping
bit_offset: 0
bit_size: 5
- name: CHMAP14
description: Input channel mapping
bit_offset: 8
bit_size: 5
- name: CHMAP13
description: Input channel mapping
bit_offset: 16
bit_size: 5
- name: CHMAP12
description: Input channel mapping
bit_offset: 24
bit_size: 5
fieldset/HWCFGR5:
description: Hardware Configuration Register
fields:
- name: CHMAP19
description: Input channel mapping
bit_offset: 0
bit_size: 5
- name: CHMAP18
description: Input channel mapping
bit_offset: 8
bit_size: 5
- name: CHMAP17
description: Input channel mapping
bit_offset: 16
bit_size: 5
- name: CHMAP16
description: Input channel mapping
bit_offset: 24
bit_size: 5
fieldset/HWCFGR6:
description: Hardware Configuration Register
fields:
- name: CHMAP20
description: Input channel mapping
bit_offset: 0
bit_size: 5
- name: CHMAP21
description: Input channel mapping
bit_offset: 8
bit_size: 5
- name: CHMAP22
description: Input channel mapping
bit_offset: 16
bit_size: 5
- name: CHMAP23
description: Input channel mapping
bit_offset: 24
bit_size: 5
fieldset/IER:
description: ADC interrupt enable register
fields:
- name: ADRDYIE
description: ADC ready interrupt
bit_offset: 0
bit_size: 1
- name: EOSMPIE
description: ADC group regular end of sampling interrupt
bit_offset: 1
bit_size: 1
- name: EOCIE
description: ADC group regular end of unitary conversion interrupt
bit_offset: 2
bit_size: 1
- name: EOSIE
description: ADC group regular end of sequence conversions interrupt
bit_offset: 3
bit_size: 1
- name: OVRIE
description: ADC group regular overrun interrupt
bit_offset: 4
bit_size: 1
- name: AWD1IE
description: ADC analog watchdog 1 interrupt
bit_offset: 7
bit_size: 1
- name: AWD2IE
description: ADC analog watchdog 2 interrupt
bit_offset: 8
bit_size: 1
- name: AWD3IE
description: ADC analog watchdog 3 interrupt
bit_offset: 9
bit_size: 1
- name: EOCALIE
description: End of calibration interrupt enable
bit_offset: 11
bit_size: 1
- name: CCRDYIE
description: Channel Configuration Ready Interrupt enable
bit_offset: 13
bit_size: 1
fieldset/IPIDR:
description: EXTI Identification register
fields:
- name: IPID
description: IP Identification
bit_offset: 0
bit_size: 32
fieldset/ISR:
description: ADC interrupt and status register
fields:
- name: ADRDY
description: ADC ready flag
bit_offset: 0
bit_size: 1
- name: EOSMP
description: ADC group regular end of sampling flag
bit_offset: 1
bit_size: 1
- name: EOC
description: ADC group regular end of unitary conversion flag
bit_offset: 2
bit_size: 1
- name: EOS
description: ADC group regular end of sequence conversions flag
bit_offset: 3
bit_size: 1
- name: OVR
description: ADC group regular overrun flag
bit_offset: 4
bit_size: 1
- name: AWD1
description: ADC analog watchdog 1 flag
bit_offset: 7
bit_size: 1
- name: AWD2
description: ADC analog watchdog 2 flag
bit_offset: 8
bit_size: 1
- name: AWD3
description: ADC analog watchdog 3 flag
bit_offset: 9
bit_size: 1
- name: EOCAL
description: End Of Calibration flag
bit_offset: 11
bit_size: 1
- name: CCRDY
description: Channel Configuration Ready flag
bit_offset: 13
bit_size: 1
fieldset/SIDR:
description: EXTI Size ID register
fields:
- name: SID
description: Size Identification
bit_offset: 0
bit_size: 32
fieldset/SMPR:
description: ADC sampling time register
fields:
- name: SMP1
description: Sampling time selection
bit_offset: 0
bit_size: 3
enum: SAMPLE_TIME
- name: SMP2
description: Sampling time selection
bit_offset: 4
bit_size: 3
enum: SAMPLE_TIME
- name: SMPSEL
description: Channel sampling time selection
bit_offset: 8
bit_size: 1
array:
len: 19
stride: 0
fieldset/VERR:
description: EXTI IP Version register
fields:
- name: MINREV
description: Minor Revision number
bit_offset: 0
bit_size: 4
- name: MAJREV
description: Major Revision number
bit_offset: 4
bit_size: 4
enum/SAMPLE_TIME:
bit_size: 3
variants:
- name: Cycles1_5
description: 1.5 ADC cycles
value: 0
- name: Cycles3_5
description: 3.5 ADC cycles
value: 1
- name: Cycles7_5
description: 7.5 ADC cycles
value: 2
- name: Cycles12_5
description: 12.5 ADC cycles
value: 3
- name: Cycles19_5
description: 19.5 ADC cycles
value: 4
- name: Cycles39_5
description: 39.5 ADC cycles
value: 5
- name: Cycles79_5
description: 79.5 ADC cycles
value: 6
- name: Cycles160_5
description: 160.5 ADC cycles
value: 7
enum/RES:
bit_size: 2
variants:
- name: TwelveBit
description: 12-bit resolution
value: 0
- name: TenBit
description: 10-bit resolution
value: 1
- name: EightBit
description: 8-bit resolution
value: 2
- name: SixBit
description: 6-bit resolution
value: 3

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data/registers/pwr_g0.yaml Normal file
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---
block/PWR:
description: Power control
items:
- name: CR1
description: Power control register 1
byte_offset: 0
fieldset: CR1
- name: CR2
description: Power control register 2
byte_offset: 4
fieldset: CR2
- name: CR3
description: Power control register 3
byte_offset: 8
fieldset: CR3
- name: CR4
description: Power control register 4
byte_offset: 12
fieldset: CR4
- name: SR1
description: Power status register 1
byte_offset: 16
access: Read
fieldset: SR1
- name: SR2
description: Power status register 2
byte_offset: 20
access: Read
fieldset: SR2
- name: SCR
description: Power status clear register
byte_offset: 24
access: Write
fieldset: SCR
- name: PUCRA
description: Power Port A pull-up control register
byte_offset: 32
fieldset: PUCRA
- name: PDCRA
description: Power Port A pull-down control register
byte_offset: 36
fieldset: PDCRA
- name: PUCRB
description: Power Port B pull-up control register
byte_offset: 40
fieldset: PUCRB
- name: PDCRB
description: Power Port B pull-down control register
byte_offset: 44
fieldset: PDCRB
- name: PUCRC
description: Power Port C pull-up control register
byte_offset: 48
fieldset: PUCRC
- name: PDCRC
description: Power Port C pull-down control register
byte_offset: 52
fieldset: PDCRC
- name: PUCRD
description: Power Port D pull-up control register
byte_offset: 56
fieldset: PUCRD
- name: PDCRD
description: Power Port D pull-down control register
byte_offset: 60
fieldset: PDCRD
- name: PUCRF
description: Power Port F pull-up control register
byte_offset: 72
fieldset: PUCRF
- name: PDCRF
description: Power Port F pull-down control register
byte_offset: 76
fieldset: PDCRF
fieldset/CR1:
description: Power control register 1
fields:
- name: LPMS
description: Low-power mode selection
bit_offset: 0
bit_size: 3
- name: FPD_STOP
description: Flash memory powered down during Stop mode
bit_offset: 3
bit_size: 1
- name: FPD_LPRUN
description: Flash memory powered down during Low-power run mode
bit_offset: 4
bit_size: 1
- name: FPD_LPSLP
description: Flash memory powered down during Low-power sleep mode
bit_offset: 5
bit_size: 1
- name: DBP
description: Disable backup domain write protection
bit_offset: 8
bit_size: 1
- name: VOS
description: Voltage scaling range selection
bit_offset: 9
bit_size: 2
- name: LPR
description: Low-power run
bit_offset: 14
bit_size: 1
fieldset/CR2:
description: Power control register 2
fields:
- name: PVDE
description: Power voltage detector enable
bit_offset: 0
bit_size: 1
- name: PVDFT
description: Power voltage detector falling threshold selection
bit_offset: 1
bit_size: 3
- name: PVDRT
description: Power voltage detector rising threshold selection
bit_offset: 4
bit_size: 3
fieldset/CR3:
description: Power control register 3
fields:
- name: EWUP1
description: Enable Wakeup pin WKUP1
bit_offset: 0
bit_size: 1
- name: EWUP2
description: Enable Wakeup pin WKUP2
bit_offset: 1
bit_size: 1
- name: EWUP4
description: Enable Wakeup pin WKUP4
bit_offset: 3
bit_size: 1
- name: EWUP5
description: Enable WKUP5 wakeup pin
bit_offset: 4
bit_size: 1
- name: EWUP6
description: Enable WKUP6 wakeup pin
bit_offset: 5
bit_size: 1
- name: RRS
description: SRAM retention in Standby mode
bit_offset: 8
bit_size: 1
- name: ULPEN
description: Enable the periodical sampling mode for PDR detection
bit_offset: 9
bit_size: 1
- name: APC
description: Apply pull-up and pull-down configuration
bit_offset: 10
bit_size: 1
- name: EIWUL
description: Enable internal wakeup line
bit_offset: 15
bit_size: 1
fieldset/CR4:
description: Power control register 4
fields:
- name: WP1
description: Wakeup pin WKUP1 polarity
bit_offset: 0
bit_size: 1
- name: WP2
description: Wakeup pin WKUP2 polarity
bit_offset: 1
bit_size: 1
- name: WP4
description: Wakeup pin WKUP4 polarity
bit_offset: 3
bit_size: 1
- name: WP5
description: Wakeup pin WKUP5 polarity
bit_offset: 4
bit_size: 1
- name: WP6
description: WKUP6 wakeup pin polarity
bit_offset: 5
bit_size: 1
- name: VBE
description: VBAT battery charging enable
bit_offset: 8
bit_size: 1
- name: VBRS
description: VBAT battery charging resistor selection
bit_offset: 9
bit_size: 1
fieldset/PDCRA:
description: Power Port A pull-down control register
fields:
- name: PD0
description: Port A pull-down bit y (y=0..15)
bit_offset: 0
bit_size: 1
- name: PD1
description: Port A pull-down bit y (y=0..15)
bit_offset: 1
bit_size: 1
- name: PD2
description: Port A pull-down bit y (y=0..15)
bit_offset: 2
bit_size: 1
- name: PD3
description: Port A pull-down bit y (y=0..15)
bit_offset: 3
bit_size: 1
- name: PD4
description: Port A pull-down bit y (y=0..15)
bit_offset: 4
bit_size: 1
- name: PD5
description: Port A pull-down bit y (y=0..15)
bit_offset: 5
bit_size: 1
- name: PD6
description: Port A pull-down bit y (y=0..15)
bit_offset: 6
bit_size: 1
- name: PD7
description: Port A pull-down bit y (y=0..15)
bit_offset: 7
bit_size: 1
- name: PD8
description: Port A pull-down bit y (y=0..15)
bit_offset: 8
bit_size: 1
- name: PD9
description: Port A pull-down bit y (y=0..15)
bit_offset: 9
bit_size: 1
- name: PD10
description: Port A pull-down bit y (y=0..15)
bit_offset: 10
bit_size: 1
- name: PD11
description: Port A pull-down bit y (y=0..15)
bit_offset: 11
bit_size: 1
- name: PD12
description: Port A pull-down bit y (y=0..15)
bit_offset: 12
bit_size: 1
- name: PD13
description: Port A pull-down bit y (y=0..15)
bit_offset: 13
bit_size: 1
- name: PD14
description: Port A pull-down bit y (y=0..15)
bit_offset: 14
bit_size: 1
- name: PD15
description: Port A pull-down bit y (y=0..15)
bit_offset: 15
bit_size: 1
fieldset/PDCRB:
description: Power Port B pull-down control register
fields:
- name: PD0
description: Port B pull-down bit y (y=0..15)
bit_offset: 0
bit_size: 1
- name: PD1
description: Port B pull-down bit y (y=0..15)
bit_offset: 1
bit_size: 1
- name: PD2
description: Port B pull-down bit y (y=0..15)
bit_offset: 2
bit_size: 1
- name: PD3
description: Port B pull-down bit y (y=0..15)
bit_offset: 3
bit_size: 1
- name: PD4
description: Port B pull-down bit y (y=0..15)
bit_offset: 4
bit_size: 1
- name: PD5
description: Port B pull-down bit y (y=0..15)
bit_offset: 5
bit_size: 1
- name: PD6
description: Port B pull-down bit y (y=0..15)
bit_offset: 6
bit_size: 1
- name: PD7
description: Port B pull-down bit y (y=0..15)
bit_offset: 7
bit_size: 1
- name: PD8
description: Port B pull-down bit y (y=0..15)
bit_offset: 8
bit_size: 1
- name: PD9
description: Port B pull-down bit y (y=0..15)
bit_offset: 9
bit_size: 1
- name: PD10
description: Port B pull-down bit y (y=0..15)
bit_offset: 10
bit_size: 1
- name: PD11
description: Port B pull-down bit y (y=0..15)
bit_offset: 11
bit_size: 1
- name: PD12
description: Port B pull-down bit y (y=0..15)
bit_offset: 12
bit_size: 1
- name: PD13
description: Port B pull-down bit y (y=0..15)
bit_offset: 13
bit_size: 1
- name: PD14
description: Port B pull-down bit y (y=0..15)
bit_offset: 14
bit_size: 1
- name: PD15
description: Port B pull-down bit y (y=0..15)
bit_offset: 15
bit_size: 1
fieldset/PDCRC:
description: Power Port C pull-down control register
fields:
- name: PD0
description: Port C pull-down bit y (y=0..15)
bit_offset: 0
bit_size: 1
- name: PD1
description: Port C pull-down bit y (y=0..15)
bit_offset: 1
bit_size: 1
- name: PD2
description: Port C pull-down bit y (y=0..15)
bit_offset: 2
bit_size: 1
- name: PD3
description: Port C pull-down bit y (y=0..15)
bit_offset: 3
bit_size: 1
- name: PD4
description: Port C pull-down bit y (y=0..15)
bit_offset: 4
bit_size: 1
- name: PD5
description: Port C pull-down bit y (y=0..15)
bit_offset: 5
bit_size: 1
- name: PD6
description: Port C pull-down bit y (y=0..15)
bit_offset: 6
bit_size: 1
- name: PD7
description: Port C pull-down bit y (y=0..15)
bit_offset: 7
bit_size: 1
- name: PD8
description: Port C pull-down bit y (y=0..15)
bit_offset: 8
bit_size: 1
- name: PD9
description: Port C pull-down bit y (y=0..15)
bit_offset: 9
bit_size: 1
- name: PD10
description: Port C pull-down bit y (y=0..15)
bit_offset: 10
bit_size: 1
- name: PD11
description: Port C pull-down bit y (y=0..15)
bit_offset: 11
bit_size: 1
- name: PD12
description: Port C pull-down bit y (y=0..15)
bit_offset: 12
bit_size: 1
- name: PD13
description: Port C pull-down bit y (y=0..15)
bit_offset: 13
bit_size: 1
- name: PD14
description: Port C pull-down bit y (y=0..15)
bit_offset: 14
bit_size: 1
- name: PD15
description: Port C pull-down bit y (y=0..15)
bit_offset: 15
bit_size: 1
fieldset/PDCRD:
description: Power Port D pull-down control register
fields:
- name: PD0
description: Port D pull-down bit y (y=0..15)
bit_offset: 0
bit_size: 1
- name: PD1
description: Port D pull-down bit y (y=0..15)
bit_offset: 1
bit_size: 1
- name: PD2
description: Port D pull-down bit y (y=0..15)
bit_offset: 2
bit_size: 1
- name: PD3
description: Port D pull-down bit y (y=0..15)
bit_offset: 3
bit_size: 1
- name: PD4
description: Port D pull-down bit y (y=0..15)
bit_offset: 4
bit_size: 1
- name: PD5
description: Port D pull-down bit y (y=0..15)
bit_offset: 5
bit_size: 1
- name: PD6
description: Port D pull-down bit y (y=0..15)
bit_offset: 6
bit_size: 1
- name: PD8
description: Port D pull-down bit y (y=0..15)
bit_offset: 8
bit_size: 1
- name: PD9
description: Port D pull-down bit y (y=0..15)
bit_offset: 9
bit_size: 1
fieldset/PDCRF:
description: Power Port F pull-down control register
fields:
- name: PD0
description: Port F pull-down bit y (y=0..15)
bit_offset: 0
bit_size: 1
- name: PD1
description: Port F pull-down bit y (y=0..15)
bit_offset: 1
bit_size: 1
- name: PD2
description: Port F pull-down bit y (y=0..15)
bit_offset: 2
bit_size: 1
fieldset/PUCRA:
description: Power Port A pull-up control register
fields:
- name: PU0
description: Port A pull-up bit y (y=0..15)
bit_offset: 0
bit_size: 1
- name: PU1
description: Port A pull-up bit y (y=0..15)
bit_offset: 1
bit_size: 1
- name: PU2
description: Port A pull-up bit y (y=0..15)
bit_offset: 2
bit_size: 1
- name: PU3
description: Port A pull-up bit y (y=0..15)
bit_offset: 3
bit_size: 1
- name: PU4
description: Port A pull-up bit y (y=0..15)
bit_offset: 4
bit_size: 1
- name: PU5
description: Port A pull-up bit y (y=0..15)
bit_offset: 5
bit_size: 1
- name: PU6
description: Port A pull-up bit y (y=0..15)
bit_offset: 6
bit_size: 1
- name: PU7
description: Port A pull-up bit y (y=0..15)
bit_offset: 7
bit_size: 1
- name: PU8
description: Port A pull-up bit y (y=0..15)
bit_offset: 8
bit_size: 1
- name: PU9
description: Port A pull-up bit y (y=0..15)
bit_offset: 9
bit_size: 1
- name: PU10
description: Port A pull-up bit y (y=0..15)
bit_offset: 10
bit_size: 1
- name: PU11
description: Port A pull-up bit y (y=0..15)
bit_offset: 11
bit_size: 1
- name: PU12
description: Port A pull-up bit y (y=0..15)
bit_offset: 12
bit_size: 1
- name: PU13
description: Port A pull-up bit y (y=0..15)
bit_offset: 13
bit_size: 1
- name: PU14
description: Port A pull-up bit y (y=0..15)
bit_offset: 14
bit_size: 1
- name: PU15
description: Port A pull-up bit y (y=0..15)
bit_offset: 15
bit_size: 1
fieldset/PUCRB:
description: Power Port B pull-up control register
fields:
- name: PU0
description: Port B pull-up bit y (y=0..15)
bit_offset: 0
bit_size: 1
- name: PU1
description: Port B pull-up bit y (y=0..15)
bit_offset: 1
bit_size: 1
- name: PU2
description: Port B pull-up bit y (y=0..15)
bit_offset: 2
bit_size: 1
- name: PU3
description: Port B pull-up bit y (y=0..15)
bit_offset: 3
bit_size: 1
- name: PU4
description: Port B pull-up bit y (y=0..15)
bit_offset: 4
bit_size: 1
- name: PU5
description: Port B pull-up bit y (y=0..15)
bit_offset: 5
bit_size: 1
- name: PU6
description: Port B pull-up bit y (y=0..15)
bit_offset: 6
bit_size: 1
- name: PU7
description: Port B pull-up bit y (y=0..15)
bit_offset: 7
bit_size: 1
- name: PU8
description: Port B pull-up bit y (y=0..15)
bit_offset: 8
bit_size: 1
- name: PU9
description: Port B pull-up bit y (y=0..15)
bit_offset: 9
bit_size: 1
- name: PU10
description: Port B pull-up bit y (y=0..15)
bit_offset: 10
bit_size: 1
- name: PU11
description: Port B pull-up bit y (y=0..15)
bit_offset: 11
bit_size: 1
- name: PU12
description: Port B pull-up bit y (y=0..15)
bit_offset: 12
bit_size: 1
- name: PU13
description: Port B pull-up bit y (y=0..15)
bit_offset: 13
bit_size: 1
- name: PU14
description: Port B pull-up bit y (y=0..15)
bit_offset: 14
bit_size: 1
- name: PU15
description: Port B pull-up bit y (y=0..15)
bit_offset: 15
bit_size: 1
fieldset/PUCRC:
description: Power Port C pull-up control register
fields:
- name: PU0
description: Port C pull-up bit y (y=0..15)
bit_offset: 0
bit_size: 1
- name: PU1
description: Port C pull-up bit y (y=0..15)
bit_offset: 1
bit_size: 1
- name: PU2
description: Port C pull-up bit y (y=0..15)
bit_offset: 2
bit_size: 1
- name: PU3
description: Port C pull-up bit y (y=0..15)
bit_offset: 3
bit_size: 1
- name: PU4
description: Port C pull-up bit y (y=0..15)
bit_offset: 4
bit_size: 1
- name: PU5
description: Port C pull-up bit y (y=0..15)
bit_offset: 5
bit_size: 1
- name: PU6
description: Port C pull-up bit y (y=0..15)
bit_offset: 6
bit_size: 1
- name: PU7
description: Port C pull-up bit y (y=0..15)
bit_offset: 7
bit_size: 1
- name: PU8
description: Port C pull-up bit y (y=0..15)
bit_offset: 8
bit_size: 1
- name: PU9
description: Port C pull-up bit y (y=0..15)
bit_offset: 9
bit_size: 1
- name: PU10
description: Port C pull-up bit y (y=0..15)
bit_offset: 10
bit_size: 1
- name: PU11
description: Port C pull-up bit y (y=0..15)
bit_offset: 11
bit_size: 1
- name: PU12
description: Port C pull-up bit y (y=0..15)
bit_offset: 12
bit_size: 1
- name: PU13
description: Port C pull-up bit y (y=0..15)
bit_offset: 13
bit_size: 1
- name: PU14
description: Port C pull-up bit y (y=0..15)
bit_offset: 14
bit_size: 1
- name: PU15
description: Port C pull-up bit y (y=0..15)
bit_offset: 15
bit_size: 1
fieldset/PUCRD:
description: Power Port D pull-up control register
fields:
- name: PU0
description: Port D pull-up bit y (y=0..15)
bit_offset: 0
bit_size: 1
- name: PU1
description: Port D pull-up bit y (y=0..15)
bit_offset: 1
bit_size: 1
- name: PU2
description: Port D pull-up bit y (y=0..15)
bit_offset: 2
bit_size: 1
- name: PU3
description: Port D pull-up bit y (y=0..15)
bit_offset: 3
bit_size: 1
- name: PU4
description: Port D pull-up bit y (y=0..15)
bit_offset: 4
bit_size: 1
- name: PU5
description: Port D pull-up bit y (y=0..15)
bit_offset: 5
bit_size: 1
- name: PU6
description: Port D pull-up bit y (y=0..15)
bit_offset: 6
bit_size: 1
- name: PU8
description: Port D pull-up bit y (y=0..15)
bit_offset: 8
bit_size: 1
- name: PU9
description: Port D pull-up bit y (y=0..15)
bit_offset: 9
bit_size: 1
fieldset/PUCRF:
description: Power Port F pull-up control register
fields:
- name: PU0
description: Port F pull-up bit y (y=0..15)
bit_offset: 0
bit_size: 1
- name: PU1
description: Port F pull-up bit y (y=0..15)
bit_offset: 1
bit_size: 1
- name: PU2
description: Port F pull-up bit y (y=0..15)
bit_offset: 2
bit_size: 1
fieldset/SCR:
description: Power status clear register
fields:
- name: CWUF1
description: Clear wakeup flag 1
bit_offset: 0
bit_size: 1
- name: CWUF2
description: Clear wakeup flag 2
bit_offset: 1
bit_size: 1
- name: CWUF4
description: Clear wakeup flag 4
bit_offset: 3
bit_size: 1
- name: CWUF5
description: Clear wakeup flag 5
bit_offset: 4
bit_size: 1
- name: CWUF6
description: Clear wakeup flag 6
bit_offset: 5
bit_size: 1
- name: CSBF
description: Clear standby flag
bit_offset: 8
bit_size: 1
fieldset/SR1:
description: Power status register 1
fields:
- name: WUF1
description: Wakeup flag 1
bit_offset: 0
bit_size: 1
- name: WUF2
description: Wakeup flag 2
bit_offset: 1
bit_size: 1
- name: WUF4
description: Wakeup flag 4
bit_offset: 3
bit_size: 1
- name: WUF5
description: Wakeup flag 5
bit_offset: 4
bit_size: 1
- name: WUF6
description: Wakeup flag 6
bit_offset: 5
bit_size: 1
- name: SBF
description: Standby flag
bit_offset: 8
bit_size: 1
- name: WUFI
description: Wakeup flag internal
bit_offset: 15
bit_size: 1
fieldset/SR2:
description: Power status register 2
fields:
- name: FLASH_RDY
description: Flash ready flag
bit_offset: 7
bit_size: 1
- name: REGLPS
description: Low-power regulator started
bit_offset: 8
bit_size: 1
- name: REGLPF
description: Low-power regulator flag
bit_offset: 9
bit_size: 1
- name: VOSF
description: Voltage scaling flag
bit_offset: 10
bit_size: 1
- name: PVDO
description: Power voltage detector output
bit_offset: 11
bit_size: 1

3
parse.py
View File

@ -340,7 +340,7 @@ perimap = [
('.*:DAC:dacif_v2_0', 'dac_v2/DAC'),
('.*:DAC:dacif_v3_0', 'dac_v2/DAC'),
('.*:ADC:aditf5_v2_0', 'adc_v3/ADC'),
('STM32G0.*:ADC:.*', 'adc_v3/ADC'),
('STM32G0.*:ADC:.*', 'adc_g0/ADC'),
('STM32G0.*:ADC_COMMON:.*', 'adccommon_v3/ADC_COMMON'),
('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'),
('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'),
@ -384,6 +384,7 @@ perimap = [
('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'),
('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
('.*:STM32G0_pwr_v1_0', 'pwr_g0/PWR'),
('STM32H7(42|43|53|50).*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'),
('.*:STM32H7_pwr_v1_0', 'pwr_h7smps/PWR'),
('.*:STM32F4_pwr_v1_0', 'pwr_f4/PWR'),