stm32g4 support.

2021-11-27 02:20:17 +01:00 · 2021-11-27 02:20:17 +01:00 · 353411841c
commit 353411841c
parent 6af084d858
3 changed files with 441 additions and 0 deletions
--- a/data/registers/pwr_g4.yaml
+++ b/data/registers/pwr_g4.yaml
@ -0,0 +1,283 @@
+---
+block/PWR:
+  description: Power control
+  items:
+    - name: CR1
+      description: Power control register 1
+      byte_offset: 0
+      fieldset: CR1
+    - name: CR2
+      description: Power control register 2
+      byte_offset: 4
+      fieldset: CR2
+    - name: CR3
+      description: Power control register 3
+      byte_offset: 8
+      fieldset: CR3
+    - name: CR4
+      description: Power control register 4
+      byte_offset: 12
+      fieldset: CR4
+    - name: SR1
+      description: Power status register 1
+      byte_offset: 16
+      access: Read
+      fieldset: SR1
+    - name: SR2
+      description: Power status register 2
+      byte_offset: 20
+      access: Read
+      fieldset: SR2
+    - name: SCR
+      description: Power status clear register
+      byte_offset: 24
+      access: Write
+      fieldset: SCR
+    - name: PUCR
+      description: Power Port pull-up control register
+      byte_offset: 32
+      fieldset: PCR
+      array:
+        len: 7
+        stride: 8
+    - name: PDCR
+      description: Power Port pull-down control register
+      byte_offset: 36
+      fieldset: PCR
+      array:
+        len: 7
+        stride: 8
+    - name: CR5
+      description: Power control register 5
+      byte_offset: 128
+      fieldset: CR5
+fieldset/CR1:
+  description: Power control register 1
+  fields:
+    - name: LPMS
+      description: Low-power mode selection
+      bit_offset: 0
+      bit_size: 3
+    - name: DBP
+      description: Disable backup domain write protection
+      bit_offset: 8
+      bit_size: 1
+    - name: VOS
+      description: Voltage scaling range selection
+      bit_offset: 9
+      bit_size: 2
+    - name: LPR
+      description: Low-power run
+      bit_offset: 14
+      bit_size: 1
+fieldset/CR2:
+  description: Power control register 2
+  fields:
+    - name: PVDE
+      description: Power voltage detector enable
+      bit_offset: 0
+      bit_size: 1
+    - name: PLS
+      description: Power voltage detector level selection
+      bit_offset: 1
+      bit_size: 3
+    - name: PVMEN1
+      description: "Peripheral voltage monitoring 1 enable: VDDA vs. COMP min voltage"
+      bit_offset: 4
+      bit_size: 1
+    - name: PVMEN2
+      description: "Peripheral voltage monitoring 2 enable: VDDA vs. Fast DAC min voltage"
+      bit_offset: 5
+      bit_size: 1
+    - name: PVMEN3
+      description: "Peripheral voltage monitoring 3 enable: VDDA vs. ADC min voltage 1.62V"
+      bit_offset: 6
+      bit_size: 1
+    - name: PVMEN4
+      description: "Peripheral voltage monitoring 4 enable: VDDA vs. OPAMP/DAC min voltage"
+      bit_offset: 7
+      bit_size: 1
+fieldset/CR3:
+  description: Power control register 3
+  fields:
+    - name: EWUP1
+      description: Enable Wakeup pin WKUP1
+      bit_offset: 0
+      bit_size: 1
+    - name: EWUP2
+      description: Enable Wakeup pin WKUP2
+      bit_offset: 1
+      bit_size: 1
+    - name: EWUP3
+      description: Enable Wakeup pin WKUP3
+      bit_offset: 2
+      bit_size: 1
+    - name: EWUP4
+      description: Enable Wakeup pin WKUP4
+      bit_offset: 3
+      bit_size: 1
+    - name: EWUP5
+      description: Enable Wakeup pin WKUP5
+      bit_offset: 4
+      bit_size: 1
+    - name: RRS
+      description: SRAM2 retention in Standby mode
+      bit_offset: 8
+      bit_size: 1
+    - name: APC
+      description: Apply pull-up and pull-down configuration
+      bit_offset: 10
+      bit_size: 1
+    - name: UCPD1_STDBY
+      description: STDBY
+      bit_offset: 13
+      bit_size: 1
+    - name: UCPD1_DBDIS
+      description: DBDIS
+      bit_offset: 14
+      bit_size: 1
+    - name: EIWUL
+      description: Enable external WakeUp line
+      bit_offset: 15
+      bit_size: 1
+fieldset/CR4:
+  description: Power control register 4
+  fields:
+    - name: WP1
+      description: Wakeup pin WKUP1 polarity
+      bit_offset: 0
+      bit_size: 1
+    - name: WP2
+      description: Wakeup pin WKUP2 polarity
+      bit_offset: 1
+      bit_size: 1
+    - name: WP3
+      description: Wakeup pin WKUP3 polarity
+      bit_offset: 2
+      bit_size: 1
+    - name: WP4
+      description: Wakeup pin WKUP4 polarity
+      bit_offset: 3
+      bit_size: 1
+    - name: WP5
+      description: Wakeup pin WKUP5 polarity
+      bit_offset: 4
+      bit_size: 1
+    - name: VBE
+      description: VBAT battery charging enable
+      bit_offset: 8
+      bit_size: 1
+    - name: VBRS
+      description: VBAT battery charging resistor selection
+      bit_offset: 9
+      bit_size: 1
+fieldset/CR5:
+  description: Power control register 5
+  fields:
+    - name: R1MODE
+      description: Main regular range 1 mode
+      bit_offset: 0
+      bit_size: 1
+fieldset/PCR:
+  description: Power Port pull control register
+  fields:
+    - name: P
+      description: Port pull bit y (y=0..15)
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+fieldset/SCR:
+  description: Power status clear register
+  fields:
+    - name: CWUF1
+      description: Clear wakeup flag 1
+      bit_offset: 0
+      bit_size: 1
+    - name: CWUF2
+      description: Clear wakeup flag 2
+      bit_offset: 1
+      bit_size: 1
+    - name: CWUF3
+      description: Clear wakeup flag 3
+      bit_offset: 2
+      bit_size: 1
+    - name: CWUF4
+      description: Clear wakeup flag 4
+      bit_offset: 3
+      bit_size: 1
+    - name: CWUF5
+      description: Clear wakeup flag 5
+      bit_offset: 4
+      bit_size: 1
+    - name: CSBF
+      description: Clear standby flag
+      bit_offset: 8
+      bit_size: 1
+fieldset/SR1:
+  description: Power status register 1
+  fields:
+    - name: WUF1
+      description: Wakeup flag 1
+      bit_offset: 0
+      bit_size: 1
+    - name: WUF2
+      description: Wakeup flag 2
+      bit_offset: 1
+      bit_size: 1
+    - name: WUF3
+      description: Wakeup flag 3
+      bit_offset: 2
+      bit_size: 1
+    - name: WUF4
+      description: Wakeup flag 4
+      bit_offset: 3
+      bit_size: 1
+    - name: WUF5
+      description: Wakeup flag 5
+      bit_offset: 4
+      bit_size: 1
+    - name: SBF
+      description: Standby flag
+      bit_offset: 8
+      bit_size: 1
+    - name: WUFI
+      description: Wakeup flag internal
+      bit_offset: 15
+      bit_size: 1
+fieldset/SR2:
+  description: Power status register 2
+  fields:
+    - name: REGLPS
+      description: Low-power regulator started
+      bit_offset: 8
+      bit_size: 1
+    - name: REGLPF
+      description: Low-power regulator flag
+      bit_offset: 9
+      bit_size: 1
+    - name: VOSF
+      description: Voltage scaling flag
+      bit_offset: 10
+      bit_size: 1
+    - name: PVDO
+      description: Power voltage detector output
+      bit_offset: 11
+      bit_size: 1
+    - name: PVMO1
+      description: "Peripheral voltage monitoring output: VDDUSB vs. 1.2 V"
+      bit_offset: 12
+      bit_size: 1
+    - name: PVMO2
+      description: "Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V"
+      bit_offset: 13
+      bit_size: 1
+    - name: PVMO3
+      description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V"
+      bit_offset: 14
+      bit_size: 1
+    - name: PVMO4
+      description: "Peripheral voltage monitoring output: VDDA vs. 2.2 V"
+      bit_offset: 15
+      bit_size: 1
--- a/data/registers/syscfg_g4.yaml
+++ b/data/registers/syscfg_g4.yaml
@ -0,0 +1,155 @@
+---
+block/SYSCFG:
+  description: System configuration controller
+  items:
+    - name: MEMRMP
+      description: Remap Memory register
+      byte_offset: 0
+      fieldset: MEMRMP
+    - name: CFGR1
+      description: peripheral mode configuration register
+      byte_offset: 4
+      fieldset: CFGR1
+    - name: EXTICR
+      description: external interrupt configuration register 1
+      array:
+        len: 4
+        stride: 4
+      byte_offset: 8
+      fieldset: EXTICR
+    - name: SCSR
+      description: CCM SRAM control and status register
+      byte_offset: 24
+      fieldset: SCSR
+    - name: CFGR2
+      description: configuration register 2
+      byte_offset: 28
+      fieldset: CFGR2
+    - name: SWPR
+      description: SRAM Write protection register 1
+      byte_offset: 32
+      fieldset: SWPR
+    - name: SKR
+      description: SRAM2 Key Register
+      byte_offset: 36
+      access: Write
+      fieldset: SKR
+fieldset/CFGR1:
+  description: peripheral mode configuration register
+  fields:
+    - name: BOOSTEN
+      description: BOOSTEN
+      bit_offset: 8
+      bit_size: 1
+    - name: ANASWVDD
+      description: GPIO analog switch control voltage selection
+      bit_offset: 9
+      bit_size: 1
+    - name: I2C_PB6_FMP
+      description: FM+ drive capability on PB6
+      bit_offset: 16
+      bit_size: 1
+    - name: I2C_PB7_FMP
+      description: FM+ drive capability on PB6
+      bit_offset: 17
+      bit_size: 1
+    - name: I2C_PB8_FMP
+      description: FM+ drive capability on PB6
+      bit_offset: 18
+      bit_size: 1
+    - name: I2C_PB9_FMP
+      description: FM+ drive capability on PB6
+      bit_offset: 19
+      bit_size: 1
+    - name: I2C1_FMP
+      description: I2C1 FM+ drive capability enable
+      bit_offset: 20
+      bit_size: 1
+    - name: I2C2_FMP
+      description: I2C1 FM+ drive capability enable
+      bit_offset: 21
+      bit_size: 1
+    - name: I2C3_FMP
+      description: I2C1 FM+ drive capability enable
+      bit_offset: 22
+      bit_size: 1
+    - name: I2C4_FMP
+      description: I2C1 FM+ drive capability enable
+      bit_offset: 23
+      bit_size: 1
+    - name: FPU_IE
+      description: FPU Interrupts Enable
+      bit_offset: 26
+      bit_size: 6
+fieldset/CFGR2:
+  description: configuration register 2
+  fields:
+    - name: CLL
+      description: Core Lockup Lock
+      bit_offset: 0
+      bit_size: 1
+    - name: SPL
+      description: SRAM Parity Lock
+      bit_offset: 1
+      bit_size: 1
+    - name: PVDL
+      description: PVD Lock
+      bit_offset: 2
+      bit_size: 1
+    - name: ECCL
+      description: ECC Lock
+      bit_offset: 3
+      bit_size: 1
+    - name: SPF
+      description: SRAM Parity Flag
+      bit_offset: 8
+      bit_size: 1
+fieldset/EXTICR:
+  description: external interrupt configuration register
+  fields:
+    - name: EXTI
+      description: EXTI x configuration
+      bit_offset: 0
+      bit_size: 4
+      array:
+        len: 4
+        stride: 4
+fieldset/MEMRMP:
+  description: Remap Memory register
+  fields:
+    - name: MEM_MODE
+      description: Memory mapping selection
+      bit_offset: 0
+      bit_size: 3
+    - name: FB_mode
+      description: User Flash Bank mode
+      bit_offset: 8
+      bit_size: 1
+fieldset/SCSR:
+  description: CCM SRAM control and status register
+  fields:
+    - name: CCMER
+      description: CCM SRAM Erase
+      bit_offset: 0
+      bit_size: 1
+    - name: CCMBSY
+      description: CCM SRAM busy by erase operation
+      bit_offset: 1
+      bit_size: 1
+fieldset/SKR:
+  description: SRAM2 Key Register
+  fields:
+    - name: KEY
+      description: SRAM2 Key for software erase
+      bit_offset: 0
+      bit_size: 8
+fieldset/SWPR:
+  description: SRAM Write protection register
+  fields:
+    - name: Page_WP
+      description: Write protection
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 32
+        stride: 1
--- a/stm32data/main.py
+++ b/stm32data/main.py
@ -125,6 +125,7 @@ perimap = [
    ('STM32L0.*:SYS:.*',  'syscfg_l0/SYSCFG'),
    ('STM32L1.*:SYS:.*',  'syscfg_l1/SYSCFG'),
    ('STM32G0.*:SYS:.*',  'syscfg_g0/SYSCFG'),
+    ('STM32G4.*:SYS:.*',  'syscfg_g4/SYSCFG'),
    ('STM32H7.*:SYS:.*',  'syscfg_h7/SYSCFG'),
    ('STM32U5.*:SYS:.*',  'syscfg_u5/SYSCFG'),
    ('STM32WB.*:SYS:.*',  'syscfg_wb/SYSCFG'),
@ -180,6 +181,7 @@ perimap = [
    ('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'),
    ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
    ('.*:STM32G0_pwr_v1_0', 'pwr_g0/PWR'),
+    ('.*:STM32G4_pwr_v1_0', 'pwr_g4/PWR'),
    ('STM32H7(42|43|53|50).*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'),
    ('.*:STM32H7_pwr_v1_0', 'pwr_h7smps/PWR'),
    ('.*:STM32F4_pwr_v1_0', 'pwr_f4/PWR'),
@ -1152,6 +1154,7 @@ def parse_rcc_regs():
        with open(f, 'r') as yaml_file:
            y = yaml.load(yaml_file)
            for (key, body) in y.items():
+                if 'SMENR' in key: continue
                if key.startswith("fieldset/A") and key.endswith("ENR"):
                    clock = removesuffix(key, "ENR")
                    clock = removeprefix(clock, "fieldset/")