fmt all register yamls

data/registers/adc_g0.yaml

@@ -615,6 +615,21 @@ fieldset/VERR:
       description: Major Revision number
       bit_offset: 4
       bit_size: 4
+enum/RES:
+  bit_size: 2
+  variants:
+    - name: TwelveBit
+      description: 12-bit resolution
+      value: 0
+    - name: TenBit
+      description: 10-bit resolution
+      value: 1
+    - name: EightBit
+      description: 8-bit resolution
+      value: 2
+    - name: SixBit
+      description: 6-bit resolution
+      value: 3
 enum/SAMPLE_TIME:
   bit_size: 3
   variants:
@@ -642,18 +657,3 @@ enum/SAMPLE_TIME:
     - name: Cycles160_5
       description: 160.5 ADC cycles
       value: 7
-enum/RES:
-  bit_size: 2
-  variants:
-    - name: TwelveBit
-      description: 12-bit resolution
-      value: 0
-    - name: TenBit
-      description: 10-bit resolution
-      value: 1
-    - name: EightBit
-      description: 8-bit resolution
-      value: 2
-    - name: SixBit
-      description: 6-bit resolution
-      value: 3

data/registers/adc_v3.yaml

@@ -521,10 +521,10 @@ fieldset/SMPR1:
       description: Channel 0 sampling time selection
       bit_offset: 0
       bit_size: 3
-      enum: SAMPLE_TIME
       array:
         len: 10
         stride: 3
+      enum: SAMPLE_TIME
 fieldset/SMPR2:
   description: sample time register 2
   fields:
@@ -532,10 +532,10 @@ fieldset/SMPR2:
       description: Channel 10 sampling time selection
       bit_offset: 0
       bit_size: 3
-      enum: SAMPLE_TIME
       array:
         len: 9
         stride: 3
+      enum: SAMPLE_TIME
 fieldset/SQR1:
   description: regular sequence register 1
   fields:
@@ -631,6 +631,21 @@ fieldset/TR3:
       array:
         len: 1
         stride: 0
+enum/RES:
+  bit_size: 2
+  variants:
+    - name: TwelveBit
+      description: 12-bit resolution
+      value: 0
+    - name: TenBit
+      description: 10-bit resolution
+      value: 1
+    - name: EightBit
+      description: 8-bit resolution
+      value: 2
+    - name: SixBit
+      description: 6-bit resolution
+      value: 3
 enum/SAMPLE_TIME:
   bit_size: 3
   variants:
@@ -658,18 +673,3 @@ enum/SAMPLE_TIME:
     - name: Cycles640_5
       description: 640.5 ADC cycles
       value: 7
-enum/RES:
-  bit_size: 2
-  variants:
-    - name: TwelveBit
-      description: 12-bit resolution
-      value: 0
-    - name: TenBit
-      description: 10-bit resolution
-      value: 1
-    - name: EightBit
-      description: 8-bit resolution
-      value: 2
-    - name: SixBit
-      description: 6-bit resolution
-      value: 3

data/registers/adccommon_v2.yaml

@@ -2,271 +2,268 @@
 block/ADC_COMMON:
   description: ADC common registers
   items:
-  - access: Read
-    byte_offset: 0
-    description: ADC Common status register
-    fieldset: CSR
-    name: CSR
-  - byte_offset: 4
-    description: ADC common control register
-    fieldset: CCR
-    name: CCR
-  - access: Read
-    byte_offset: 8
-    description: ADC common regular data register for dual and triple modes
-    fieldset: CDR
-    name: CDR
-enum/ADCPRE:
-  bit_size: 2
-  variants:
-  - description: PCLK2 divided by 2
-    name: Div2
-    value: 0
-  - description: PCLK2 divided by 4
-    name: Div4
-    value: 1
-  - description: PCLK2 divided by 6
-    name: Div6
-    value: 2
-  - description: PCLK2 divided by 8
-    name: Div8
-    value: 3
-enum/AWD:
-  bit_size: 1
-  variants:
-  - description: No analog watchdog event occurred
-    name: NoEvent
-    value: 0
-  - description: Analog watchdog event occurred
-    name: Event
-    value: 1
-enum/DDS:
-  bit_size: 1
-  variants:
-  - description: No new DMA request is issued after the last transfer
-    name: Single
-    value: 0
-  - description: DMA requests are issued as long as data are converted and DMA=01,
-      10 or 11
-    name: Continuous
-    value: 1
-enum/DMA:
-  bit_size: 2
-  variants:
-  - description: DMA mode disabled
-    name: Disabled
-    value: 0
-  - description: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
-    name: Mode1
-    value: 1
-  - description: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then
-      3&2)
-    name: Mode2
-    value: 2
-  - description: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then
-      3&2)
-    name: Mode3
-    value: 3
-enum/EOC:
-  bit_size: 1
-  variants:
-  - description: Conversion is not complete
-    name: NotComplete
-    value: 0
-  - description: Conversion complete
-    name: Complete
-    value: 1
-enum/JEOC:
-  bit_size: 1
-  variants:
-  - description: Conversion is not complete
-    name: NotComplete
-    value: 0
-  - description: Conversion complete
-    name: Complete
-    value: 1
-enum/JSTRT:
-  bit_size: 1
-  variants:
-  - description: No injected channel conversion started
-    name: NotStarted
-    value: 0
-  - description: Injected channel conversion has started
-    name: Started
-    value: 1
-enum/MULTI:
-  bit_size: 5
-  variants:
-  - description: 'All the ADCs independent: independent mode'
-    name: Independent
-    value: 0
-  - description: Dual ADC1 and ADC2, combined regular and injected simultaneous mode
-    name: DualRJ
-    value: 1
-  - description: Dual ADC1 and ADC2, combined regular and alternate trigger mode
-    name: DualRA
-    value: 2
-  - description: Dual ADC1 and ADC2, injected simultaneous mode only
-    name: DualJ
-    value: 5
-  - description: Dual ADC1 and ADC2, regular simultaneous mode only
-    name: DualR
-    value: 6
-  - description: Dual ADC1 and ADC2, interleaved mode only
-    name: DualI
-    value: 7
-  - description: Dual ADC1 and ADC2, alternate trigger mode only
-    name: DualA
-    value: 9
-  - description: Triple ADC, regular and injected simultaneous mode
-    name: TripleRJ
-    value: 17
-  - description: Triple ADC, regular and alternate trigger mode
-    name: TripleRA
-    value: 18
-  - description: Triple ADC, injected simultaneous mode only
-    name: TripleJ
-    value: 21
-  - description: Triple ADC, regular simultaneous mode only
-    name: TripleR
-    value: 22
-  - description: Triple ADC, interleaved mode only
-    name: TripleI
-    value: 23
-  - description: Triple ADC, alternate trigger mode only
-    name: TripleA
-    value: 24
-enum/OVR:
-  bit_size: 1
-  variants:
-  - description: No overrun occurred
-    name: NoOverrun
-    value: 0
-  - description: Overrun occurred
-    name: Overrun
-    value: 1
-enum/STRT:
-  bit_size: 1
-  variants:
-  - description: No regular channel conversion started
-    name: NotStarted
-    value: 0
-  - description: Regular channel conversion has started
-    name: Started
-    value: 1
-enum/TSVREFE:
-  bit_size: 1
-  variants:
-  - description: Temperature sensor and V_REFINT channel disabled
-    name: Disabled
-    value: 0
-  - description: Temperature sensor and V_REFINT channel enabled
-    name: Enabled
-    value: 1
-enum/VBATE:
-  bit_size: 1
-  variants:
-  - description: V_BAT channel disabled
-    name: Disabled
-    value: 0
-  - description: V_BAT channel enabled
-    name: Enabled
-    value: 1
+    - name: CSR
+      description: ADC Common status register
+      byte_offset: 0
+      access: Read
+      fieldset: CSR
+    - name: CCR
+      description: ADC common control register
+      byte_offset: 4
+      fieldset: CCR
+    - name: CDR
+      description: ADC common regular data register for dual and triple modes
+      byte_offset: 8
+      access: Read
+      fieldset: CDR
 fieldset/CCR:
   description: ADC common control register
   fields:
-  - bit_offset: 0
-    bit_size: 5
-    description: Multi ADC mode selection
-    enum: MULTI
-    name: MULTI
-  - bit_offset: 8
-    bit_size: 4
-    description: Delay between 2 sampling phases
-    name: DELAY
-  - bit_offset: 13
-    bit_size: 1
-    description: DMA disable selection for multi-ADC mode
-    enum: DDS
-    name: DDS
-  - bit_offset: 14
-    bit_size: 2
-    description: Direct memory access mode for multi ADC mode
-    enum: DMA
-    name: DMA
-  - bit_offset: 16
-    bit_size: 2
-    description: ADC prescaler
-    enum: ADCPRE
-    name: ADCPRE
-  - bit_offset: 22
-    bit_size: 1
-    description: VBAT enable
-    enum: VBATE
-    name: VBATE
-  - bit_offset: 23
-    bit_size: 1
-    description: Temperature sensor and VREFINT enable
-    enum: TSVREFE
-    name: TSVREFE
+    - name: MULTI
+      description: Multi ADC mode selection
+      bit_offset: 0
+      bit_size: 5
+      enum: MULTI
+    - name: DELAY
+      description: Delay between 2 sampling phases
+      bit_offset: 8
+      bit_size: 4
+    - name: DDS
+      description: DMA disable selection for multi-ADC mode
+      bit_offset: 13
+      bit_size: 1
+      enum: DDS
+    - name: DMA
+      description: Direct memory access mode for multi ADC mode
+      bit_offset: 14
+      bit_size: 2
+      enum: DMA
+    - name: ADCPRE
+      description: ADC prescaler
+      bit_offset: 16
+      bit_size: 2
+      enum: ADCPRE
+    - name: VBATE
+      description: VBAT enable
+      bit_offset: 22
+      bit_size: 1
+      enum: VBATE
+    - name: TSVREFE
+      description: Temperature sensor and VREFINT enable
+      bit_offset: 23
+      bit_size: 1
+      enum: TSVREFE
 fieldset/CDR:
   description: ADC common regular data register for dual and triple modes
   fields:
-  - array:
-      len: 2
-      stride: 16
-    bit_offset: 0
-    bit_size: 16
-    description: 1st data item of a pair of regular conversions
-    name: DATA
+    - name: DATA
+      description: 1st data item of a pair of regular conversions
+      bit_offset: 0
+      bit_size: 16
+      array:
+        len: 2
+        stride: 16
 fieldset/CSR:
   description: ADC common status register
   fields:
-  - array:
-      len: 3
-      stride: 8
-    bit_offset: 0
-    bit_size: 1
-    description: Analog watchdog flag of ADC 1
-    enum: AWD
-    name: AWD
-  - array:
-      len: 3
-      stride: 8
-    bit_offset: 1
-    bit_size: 1
-    description: End of conversion of ADC 1
-    enum: EOC
-    name: EOC
-  - array:
-      len: 3
-      stride: 8
-    bit_offset: 2
-    bit_size: 1
-    description: Injected channel end of conversion of ADC 1
-    enum: JEOC
-    name: JEOC
-  - array:
-      len: 3
-      stride: 8
-    bit_offset: 3
-    bit_size: 1
-    description: Injected channel Start flag of ADC 1
-    enum: JSTRT
-    name: JSTRT
-  - array:
-      len: 3
-      stride: 8
-    bit_offset: 4
-    bit_size: 1
-    description: Regular channel Start flag of ADC 1
-    enum: STRT
-    name: STRT
-  - array:
-      len: 3
-      stride: 8
-    bit_offset: 5
-    bit_size: 1
-    description: Overrun flag of ADC 1
-    enum: OVR
-    name: OVR
+    - name: AWD
+      description: Analog watchdog flag of ADC 1
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 3
+        stride: 8
+      enum: AWD
+    - name: EOC
+      description: End of conversion of ADC 1
+      bit_offset: 1
+      bit_size: 1
+      array:
+        len: 3
+        stride: 8
+      enum: EOC
+    - name: JEOC
+      description: Injected channel end of conversion of ADC 1
+      bit_offset: 2
+      bit_size: 1
+      array:
+        len: 3
+        stride: 8
+      enum: JEOC
+    - name: JSTRT
+      description: Injected channel Start flag of ADC 1
+      bit_offset: 3
+      bit_size: 1
+      array:
+        len: 3
+        stride: 8
+      enum: JSTRT
+    - name: STRT
+      description: Regular channel Start flag of ADC 1
+      bit_offset: 4
+      bit_size: 1
+      array:
+        len: 3
+        stride: 8
+      enum: STRT
+    - name: OVR
+      description: Overrun flag of ADC 1
+      bit_offset: 5
+      bit_size: 1
+      array:
+        len: 3
+        stride: 8
+      enum: OVR
+enum/ADCPRE:
+  bit_size: 2
+  variants:
+    - name: Div2
+      description: PCLK2 divided by 2
+      value: 0
+    - name: Div4
+      description: PCLK2 divided by 4
+      value: 1
+    - name: Div6
+      description: PCLK2 divided by 6
+      value: 2
+    - name: Div8
+      description: PCLK2 divided by 8
+      value: 3
+enum/AWD:
+  bit_size: 1
+  variants:
+    - name: NoEvent
+      description: No analog watchdog event occurred
+      value: 0
+    - name: Event
+      description: Analog watchdog event occurred
+      value: 1
+enum/DDS:
+  bit_size: 1
+  variants:
+    - name: Single
+      description: No new DMA request is issued after the last transfer
+      value: 0
+    - name: Continuous
+      description: "DMA requests are issued as long as data are converted and DMA=01, 10 or 11"
+      value: 1
+enum/DMA:
+  bit_size: 2
+  variants:
+    - name: Disabled
+      description: DMA mode disabled
+      value: 0
+    - name: Mode1
+      description: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
+      value: 1
+    - name: Mode2
+      description: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
+      value: 2
+    - name: Mode3
+      description: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
+      value: 3
+enum/EOC:
+  bit_size: 1
+  variants:
+    - name: NotComplete
+      description: Conversion is not complete
+      value: 0
+    - name: Complete
+      description: Conversion complete
+      value: 1
+enum/JEOC:
+  bit_size: 1
+  variants:
+    - name: NotComplete
+      description: Conversion is not complete
+      value: 0
+    - name: Complete
+      description: Conversion complete
+      value: 1
+enum/JSTRT:
+  bit_size: 1
+  variants:
+    - name: NotStarted
+      description: No injected channel conversion started
+      value: 0
+    - name: Started
+      description: Injected channel conversion has started
+      value: 1
+enum/MULTI:
+  bit_size: 5
+  variants:
+    - name: Independent
+      description: "All the ADCs independent: independent mode"
+      value: 0
+    - name: DualRJ
+      description: "Dual ADC1 and ADC2, combined regular and injected simultaneous mode"
+      value: 1
+    - name: DualRA
+      description: "Dual ADC1 and ADC2, combined regular and alternate trigger mode"
+      value: 2
+    - name: DualJ
+      description: "Dual ADC1 and ADC2, injected simultaneous mode only"
+      value: 5
+    - name: DualR
+      description: "Dual ADC1 and ADC2, regular simultaneous mode only"
+      value: 6
+    - name: DualI
+      description: "Dual ADC1 and ADC2, interleaved mode only"
+      value: 7
+    - name: DualA
+      description: "Dual ADC1 and ADC2, alternate trigger mode only"
+      value: 9
+    - name: TripleRJ
+      description: "Triple ADC, regular and injected simultaneous mode"
+      value: 17
+    - name: TripleRA
+      description: "Triple ADC, regular and alternate trigger mode"
+      value: 18
+    - name: TripleJ
+      description: "Triple ADC, injected simultaneous mode only"
+      value: 21
+    - name: TripleR
+      description: "Triple ADC, regular simultaneous mode only"
+      value: 22
+    - name: TripleI
+      description: "Triple ADC, interleaved mode only"
+      value: 23
+    - name: TripleA
+      description: "Triple ADC, alternate trigger mode only"
+      value: 24
+enum/OVR:
+  bit_size: 1
+  variants:
+    - name: NoOverrun
+      description: No overrun occurred
+      value: 0
+    - name: Overrun
+      description: Overrun occurred
+      value: 1
+enum/STRT:
+  bit_size: 1
+  variants:
+    - name: NotStarted
+      description: No regular channel conversion started
+      value: 0
+    - name: Started
+      description: Regular channel conversion has started
+      value: 1
+enum/TSVREFE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Temperature sensor and V_REFINT channel disabled
+      value: 0
+    - name: Enabled
+      description: Temperature sensor and V_REFINT channel enabled
+      value: 1
+enum/VBATE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: V_BAT channel disabled
+      value: 0
+    - name: Enabled
+      description: V_BAT channel enabled
+      value: 1

data/registers/afio_f1.yaml

@@ -1,205 +1,206 @@
+---
 block/AFIO:
   description: Alternate function I/O
   items:
-  - byte_offset: 0
-    description: Event Control Register (AFIO_EVCR)
-    fieldset: EVCR
-    name: EVCR
-  - byte_offset: 4
-    description: AF remap and debug I/O configuration register (AFIO_MAPR)
-    fieldset: MAPR
-    name: MAPR
-  - array:
-      len: 4
-      stride: 4
-    byte_offset: 8
-    description: External interrupt configuration register 1 (AFIO_EXTICR1)
-    fieldset: EXTICR
-    name: EXTICR
-  - byte_offset: 28
-    description: AF remap and debug I/O configuration register
-    fieldset: MAPR2
-    name: MAPR2
+    - name: EVCR
+      description: Event Control Register (AFIO_EVCR)
+      byte_offset: 0
+      fieldset: EVCR
+    - name: MAPR
+      description: AF remap and debug I/O configuration register (AFIO_MAPR)
+      byte_offset: 4
+      fieldset: MAPR
+    - name: EXTICR
+      description: External interrupt configuration register 1 (AFIO_EXTICR1)
+      array:
+        len: 4
+        stride: 4
+      byte_offset: 8
+      fieldset: EXTICR
+    - name: MAPR2
+      description: AF remap and debug I/O configuration register
+      byte_offset: 28
+      fieldset: MAPR2
 fieldset/EVCR:
   description: Event Control Register (AFIO_EVCR)
   fields:
-  - bit_offset: 0
-    bit_size: 4
-    description: Pin selection
-    name: PIN
-  - bit_offset: 4
-    bit_size: 3
-    description: Port selection
-    name: PORT
-  - bit_offset: 7
-    bit_size: 1
-    description: Event Output Enable
-    name: EVOE
+    - name: PIN
+      description: Pin selection
+      bit_offset: 0
+      bit_size: 4
+    - name: PORT
+      description: Port selection
+      bit_offset: 4
+      bit_size: 3
+    - name: EVOE
+      description: Event Output Enable
+      bit_offset: 7
+      bit_size: 1
 fieldset/EXTICR:
   description: External interrupt configuration register 3 (AFIO_EXTICR3)
   fields:
-  - array:
-      len: 4
-      stride: 4
-    bit_offset: 0
-    bit_size: 4
-    description: EXTI12 configuration
-    name: EXTI
+    - name: EXTI
+      description: EXTI12 configuration
+      bit_offset: 0
+      bit_size: 4
+      array:
+        len: 4
+        stride: 4
 fieldset/MAPR:
   description: AF remap and debug I/O configuration register (AFIO_MAPR)
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: SPI1 remapping
-    name: SPI1_REMAP
-  - bit_offset: 1
-    bit_size: 1
-    description: I2C1 remapping
-    name: I2C1_REMAP
-  - bit_offset: 2
-    bit_size: 1
-    description: USART1 remapping
-    name: USART1_REMAP
-  - bit_offset: 3
-    bit_size: 1
-    description: USART2 remapping
-    name: USART2_REMAP
-  - bit_offset: 4
-    bit_size: 2
-    description: USART3 remapping
-    name: USART3_REMAP
-  - bit_offset: 6
-    bit_size: 2
-    description: TIM1 remapping
-    name: TIM1_REMAP
-  - bit_offset: 8
-    bit_size: 2
-    description: TIM2 remapping
-    name: TIM2_REMAP
-  - bit_offset: 10
-    bit_size: 2
-    description: TIM3 remapping
-    name: TIM3_REMAP
-  - bit_offset: 12
-    bit_size: 1
-    description: TIM4 remapping
-    name: TIM4_REMAP
-  - bit_offset: 13
-    bit_size: 2
-    description: CAN1 remapping
-    name: CAN_REMAP
-  - bit_offset: 13
-    bit_size: 2
-    description: CAN1 remapping
-    name: CAN1_REMAP
-  - bit_offset: 15
-    bit_size: 1
-    description: Port D0/Port D1 mapping on OSCIN/OSCOUT
-    name: PD01_REMAP
-  - bit_offset: 16
-    bit_size: 1
-    description: Set and cleared by software
-    name: TIM5CH4_IREMAP
-  - bit_offset: 17
-    bit_size: 1
-    description: ADC 1 External trigger injected conversion remapping
-    name: ADC1_ETRGINJ_REMAP
-  - bit_offset: 18
-    bit_size: 1
-    description: ADC 1 external trigger regular conversion remapping
-    name: ADC1_ETRGREG_REMAP
-  - bit_offset: 19
-    bit_size: 1
-    description: ADC 2 external trigger injected conversion remapping
-    name: ADC2_ETRGINJ_REMAP
-  - bit_offset: 20
-    bit_size: 1
-    description: ADC 2 external trigger regular conversion remapping
-    name: ADC2_ETRGREG_REMAP
-  - bit_offset: 21
-    bit_size: 1
-    description: Ethernet MAC I/O remapping
-    name: ETH_REMAP
-  - bit_offset: 22
-    bit_size: 1
-    description: CAN2 I/O remapping
-    name: CAN2_REMAP
-  - bit_offset: 23
-    bit_size: 1
-    description: MII or RMII selection
-    name: MII_RMII_SEL
-  - bit_offset: 24
-    bit_size: 3
-    description: Serial wire JTAG configuration
-    name: SWJ_CFG
-  - bit_offset: 28
-    bit_size: 1
-    description: SPI3/I2S3 remapping
-    name: SPI3_REMAP
-  - bit_offset: 29
-    bit_size: 1
-    description: TIM2 internal trigger 1 remapping
-    name: TIM2ITR1_IREMAP
-  - bit_offset: 30
-    bit_size: 1
-    description: Ethernet PTP PPS remapping
-    name: PTP_PPS_REMAP
+    - name: SPI1_REMAP
+      description: SPI1 remapping
+      bit_offset: 0
+      bit_size: 1
+    - name: I2C1_REMAP
+      description: I2C1 remapping
+      bit_offset: 1
+      bit_size: 1
+    - name: USART1_REMAP
+      description: USART1 remapping
+      bit_offset: 2
+      bit_size: 1
+    - name: USART2_REMAP
+      description: USART2 remapping
+      bit_offset: 3
+      bit_size: 1
+    - name: USART3_REMAP
+      description: USART3 remapping
+      bit_offset: 4
+      bit_size: 2
+    - name: TIM1_REMAP
+      description: TIM1 remapping
+      bit_offset: 6
+      bit_size: 2
+    - name: TIM2_REMAP
+      description: TIM2 remapping
+      bit_offset: 8
+      bit_size: 2
+    - name: TIM3_REMAP
+      description: TIM3 remapping
+      bit_offset: 10
+      bit_size: 2
+    - name: TIM4_REMAP
+      description: TIM4 remapping
+      bit_offset: 12
+      bit_size: 1
+    - name: CAN_REMAP
+      description: CAN1 remapping
+      bit_offset: 13
+      bit_size: 2
+    - name: CAN1_REMAP
+      description: CAN1 remapping
+      bit_offset: 13
+      bit_size: 2
+    - name: PD01_REMAP
+      description: Port D0/Port D1 mapping on OSCIN/OSCOUT
+      bit_offset: 15
+      bit_size: 1
+    - name: TIM5CH4_IREMAP
+      description: Set and cleared by software
+      bit_offset: 16
+      bit_size: 1
+    - name: ADC1_ETRGINJ_REMAP
+      description: ADC 1 External trigger injected conversion remapping
+      bit_offset: 17
+      bit_size: 1
+    - name: ADC1_ETRGREG_REMAP
+      description: ADC 1 external trigger regular conversion remapping
+      bit_offset: 18
+      bit_size: 1
+    - name: ADC2_ETRGINJ_REMAP
+      description: ADC 2 external trigger injected conversion remapping
+      bit_offset: 19
+      bit_size: 1
+    - name: ADC2_ETRGREG_REMAP
+      description: ADC 2 external trigger regular conversion remapping
+      bit_offset: 20
+      bit_size: 1
+    - name: ETH_REMAP
+      description: Ethernet MAC I/O remapping
+      bit_offset: 21
+      bit_size: 1
+    - name: CAN2_REMAP
+      description: CAN2 I/O remapping
+      bit_offset: 22
+      bit_size: 1
+    - name: MII_RMII_SEL
+      description: MII or RMII selection
+      bit_offset: 23
+      bit_size: 1
+    - name: SWJ_CFG
+      description: Serial wire JTAG configuration
+      bit_offset: 24
+      bit_size: 3
+    - name: SPI3_REMAP
+      description: SPI3/I2S3 remapping
+      bit_offset: 28
+      bit_size: 1
+    - name: TIM2ITR1_IREMAP
+      description: TIM2 internal trigger 1 remapping
+      bit_offset: 29
+      bit_size: 1
+    - name: PTP_PPS_REMAP
+      description: Ethernet PTP PPS remapping
+      bit_offset: 30
+      bit_size: 1
 fieldset/MAPR2:
   description: AF remap and debug I/O configuration register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: TIM15 remapping
-    name: TIM15_REMAP
-  - bit_offset: 1
-    bit_size: 1
-    description: TIM16 remapping
-    name: TIM16_REMAP
-  - bit_offset: 2
-    bit_size: 1
-    description: TIM17 remapping
-    name: TIM17_REMAP
-  - bit_offset: 3
-    bit_size: 1
-    description: CEC remapping
-    name: CEC_REMAP
-  - bit_offset: 4
-    bit_size: 1
-    description: TIM1 DMA remapping
-    name: TIM1_DMA_REMAP
-  - bit_offset: 5
-    bit_size: 1
-    description: TIM9 remapping
-    name: TIM9_REMAP
-  - bit_offset: 6
-    bit_size: 1
-    description: TIM10 remapping
-    name: TIM10_REMAP
-  - bit_offset: 7
-    bit_size: 1
-    description: TIM11 remapping
-    name: TIM11_REMAP
-  - bit_offset: 8
-    bit_size: 1
-    description: TIM13 remapping
-    name: TIM13_REMAP
-  - bit_offset: 9
-    bit_size: 1
-    description: TIM14 remapping
-    name: TIM14_REMAP
-  - bit_offset: 10
-    bit_size: 1
-    description: NADV connect/disconnect
-    name: FSMC_NADV
-  - bit_offset: 11
-    bit_size: 1
-    description: TIM67_DAC DMA remapping
-    name: TIM67_DAC_DMA_REMAP
-  - bit_offset: 12
-    bit_size: 1
-    description: TIM12 remapping
-    name: TIM12_REMAP
-  - bit_offset: 13
-    bit_size: 1
-    description: Miscellaneous features remapping
-    name: MISC_REMAP
+    - name: TIM15_REMAP
+      description: TIM15 remapping
+      bit_offset: 0
+      bit_size: 1
+    - name: TIM16_REMAP
+      description: TIM16 remapping
+      bit_offset: 1
+      bit_size: 1
+    - name: TIM17_REMAP
+      description: TIM17 remapping
+      bit_offset: 2
+      bit_size: 1
+    - name: CEC_REMAP
+      description: CEC remapping
+      bit_offset: 3
+      bit_size: 1
+    - name: TIM1_DMA_REMAP
+      description: TIM1 DMA remapping
+      bit_offset: 4
+      bit_size: 1
+    - name: TIM9_REMAP
+      description: TIM9 remapping
+      bit_offset: 5
+      bit_size: 1
+    - name: TIM10_REMAP
+      description: TIM10 remapping
+      bit_offset: 6
+      bit_size: 1
+    - name: TIM11_REMAP
+      description: TIM11 remapping
+      bit_offset: 7
+      bit_size: 1
+    - name: TIM13_REMAP
+      description: TIM13 remapping
+      bit_offset: 8
+      bit_size: 1
+    - name: TIM14_REMAP
+      description: TIM14 remapping
+      bit_offset: 9
+      bit_size: 1
+    - name: FSMC_NADV
+      description: NADV connect/disconnect
+      bit_offset: 10
+      bit_size: 1
+    - name: TIM67_DAC_DMA_REMAP
+      description: TIM67_DAC DMA remapping
+      bit_offset: 11
+      bit_size: 1
+    - name: TIM12_REMAP
+      description: TIM12 remapping
+      bit_offset: 12
+      bit_size: 1
+    - name: MISC_REMAP
+      description: Miscellaneous features remapping
+      bit_offset: 13
+      bit_size: 1

data/registers/bdma_v1.yaml

@@ -1,17 +1,32 @@
 ---
+block/CH:
+  description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
+  items:
+    - name: CR
+      description: DMA channel configuration register (DMA_CCR)
+      byte_offset: 0
+      fieldset: CR
+    - name: NDTR
+      description: DMA channel 1 number of data register
+      byte_offset: 4
+      fieldset: NDTR
+    - name: PAR
+      description: DMA channel 1 peripheral address register
+      byte_offset: 8
+    - name: MAR
+      description: DMA channel 1 memory address register
+      byte_offset: 12
 block/DMA:
   description: DMA controller
   items:
     - name: ISR
       description: DMA interrupt status register (DMA_ISR)
       byte_offset: 0
-      reset_value: 0
       access: Read
       fieldset: ISR
     - name: IFCR
       description: DMA interrupt flag clear register (DMA_IFCR)
       byte_offset: 4
-      reset_value: 0
       access: Write
       fieldset: ISR
     - name: CH
@@ -21,27 +36,6 @@ block/DMA:
         stride: 20
       byte_offset: 8
       block: CH
-block/CH:
-  description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
-  items:
-    - name: CR
-      description: DMA channel configuration register (DMA_CCR)
-      byte_offset: 0
-      reset_value: 0
-      fieldset: CR
-    - name: NDTR
-      description: DMA channel 1 number of data register
-      byte_offset: 4
-      reset_value: 0
-      fieldset: NDTR
-    - name: PAR
-      description: DMA channel 1 peripheral address register
-      byte_offset: 8
-      reset_value: 0
-    - name: MAR
-      description: DMA channel 1 memory address register
-      byte_offset: 12
-      reset_value: 0
 fieldset/CR:
   description: DMA channel configuration register (DMA_CCR)
   fields:
@@ -157,15 +151,6 @@ enum/DIR:
     - name: FromMemory
       description: Read from memory
       value: 1
-enum/MEMMEM:
-  bit_size: 1
-  variants:
-    - name: Disabled
-      description: Memory to memory mode disabled
-      value: 0
-    - name: Enabled
-      description: Memory to memory mode enabled
-      value: 1
 enum/INC:
   bit_size: 1
   variants:
@@ -175,6 +160,15 @@ enum/INC:
     - name: Enabled
       description: Increment mode enabled
       value: 1
+enum/MEMMEM:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Memory to memory mode disabled
+      value: 0
+    - name: Enabled
+      description: Memory to memory mode enabled
+      value: 1
 enum/PL:
   bit_size: 2
   variants:

data/registers/bdma_v2.yaml

@@ -1,17 +1,32 @@
 ---
+block/CH:
+  description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
+  items:
+    - name: CR
+      description: DMA channel configuration register (DMA_CCR)
+      byte_offset: 0
+      fieldset: CR
+    - name: NDTR
+      description: DMA channel 1 number of data register
+      byte_offset: 4
+      fieldset: NDTR
+    - name: PAR
+      description: DMA channel 1 peripheral address register
+      byte_offset: 8
+    - name: MAR
+      description: DMA channel 1 memory address register
+      byte_offset: 12
 block/DMA:
   description: DMA controller
   items:
     - name: ISR
       description: DMA interrupt status register (DMA_ISR)
       byte_offset: 0
-      reset_value: 0
       access: Read
       fieldset: ISR
     - name: IFCR
       description: DMA interrupt flag clear register (DMA_IFCR)
       byte_offset: 4
-      reset_value: 0
       access: Write
       fieldset: ISR
     - name: CH
@@ -25,27 +40,6 @@ block/DMA:
       description: channel selection register
       byte_offset: 168
       fieldset: CSELR
-block/CH:
-  description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
-  items:
-    - name: CR
-      description: DMA channel configuration register (DMA_CCR)
-      byte_offset: 0
-      reset_value: 0
-      fieldset: CR
-    - name: NDTR
-      description: DMA channel 1 number of data register
-      byte_offset: 4
-      reset_value: 0
-      fieldset: NDTR
-    - name: PAR
-      description: DMA channel 1 peripheral address register
-      byte_offset: 8
-      reset_value: 0
-    - name: MAR
-      description: DMA channel 1 memory address register
-      byte_offset: 12
-      reset_value: 0
 fieldset/CR:
   description: DMA channel configuration register (DMA_CCR)
   fields:
@@ -171,15 +165,6 @@ enum/DIR:
     - name: FromMemory
       description: Read from memory
       value: 1
-enum/MEMMEM:
-  bit_size: 1
-  variants:
-    - name: Disabled
-      description: Memory to memory mode disabled
-      value: 0
-    - name: Enabled
-      description: Memory to memory mode enabled
-      value: 1
 enum/INC:
   bit_size: 1
   variants:
@@ -189,6 +174,15 @@ enum/INC:
     - name: Enabled
       description: Increment mode enabled
       value: 1
+enum/MEMMEM:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Memory to memory mode disabled
+      value: 0
+    - name: Enabled
+      description: Memory to memory mode enabled
+      value: 1
 enum/PL:
   bit_size: 2
   variants:

data/registers/dac_v1.yaml

@@ -2,365 +2,365 @@
 block/DAC:
   description: Digital-to-analog converter
   items:
-  - byte_offset: 0
-    description: control register
-    fieldset: CR
-    name: CR
-  - access: Write
-    byte_offset: 4
-    description: software trigger register
-    fieldset: SWTRIGR
-    name: SWTRIGR
-  - byte_offset: 8
-    description: channel1 12-bit right-aligned data holding register
-    fieldset: DHR12R1
-    name: DHR12R1
-  - byte_offset: 12
-    description: channel1 12-bit left aligned data holding register
-    fieldset: DHR12L1
-    name: DHR12L1
-  - byte_offset: 16
-    description: channel1 8-bit right aligned data holding register
-    fieldset: DHR8R1
-    name: DHR8R1
-  - byte_offset: 20
-    description: channel2 12-bit right aligned data holding register
-    fieldset: DHR12R2
-    name: DHR12R2
-  - byte_offset: 24
-    description: channel2 12-bit left aligned data holding register
-    fieldset: DHR12L2
-    name: DHR12L2
-  - byte_offset: 28
-    description: channel2 8-bit right-aligned data holding register
-    fieldset: DHR8R2
-    name: DHR8R2
-  - byte_offset: 32
-    description: Dual DAC 12-bit right-aligned data holding register
-    fieldset: DHR12RD
-    name: DHR12RD
-  - byte_offset: 36
-    description: DUAL DAC 12-bit left aligned data holding register
-    fieldset: DHR12LD
-    name: DHR12LD
-  - byte_offset: 40
-    description: DUAL DAC 8-bit right aligned data holding register
-    fieldset: DHR8RD
-    name: DHR8RD
-  - access: Read
-    byte_offset: 44
-    description: channel1 data output register
-    fieldset: DOR1
-    name: DOR1
-  - access: Read
-    byte_offset: 48
-    description: channel2 data output register
-    fieldset: DOR2
-    name: DOR2
-  - byte_offset: 52
-    description: status register
-    fieldset: SR
-    name: SR
-enum/BOFF:
-  bit_size: 1
-  variants:
-  - description: DAC channel X output buffer enabled
-    name: Enabled
-    value: 0
-  - description: DAC channel X output buffer disabled
-    name: Disabled
-    value: 1
-enum/DMAEN:
-  bit_size: 1
-  variants:
-  - description: DAC channel X DMA mode disabled
-    name: Disabled
-    value: 0
-  - description: DAC channel X DMA mode enabled
-    name: Enabled
-    value: 1
-enum/DMAUDR:
-  bit_size: 1
-  variants:
-  - description: No DMA underrun error condition occurred for DAC channel X
-    name: NoUnderrun
-    value: 0
-  - description: DMA underrun error condition occurred for DAC channel X
-    name: Underrun
-    value: 1
-enum/DMAUDRIE:
-  bit_size: 1
-  variants:
-  - description: DAC channel X DMA Underrun Interrupt disabled
-    name: Disabled
-    value: 0
-  - description: DAC channel X DMA Underrun Interrupt enabled
-    name: Enabled
-    value: 1
-enum/EN:
-  bit_size: 1
-  variants:
-  - description: DAC channel X disabled
-    name: Disabled
-    value: 0
-  - description: DAC channel X enabled
-    name: Enabled
-    value: 1
-enum/SWTRIG:
-  bit_size: 1
-  variants:
-  - description: DAC channel X software trigger disabled
-    name: Disabled
-    value: 0
-  - description: DAC channel X software trigger enabled
-    name: Enabled
-    value: 1
-enum/TEN:
-  bit_size: 1
-  variants:
-  - description: DAC channel X trigger disabled
-    name: Disabled
-    value: 0
-  - description: DAC channel X trigger enabled
-    name: Enabled
-    value: 1
-enum/TSEL1:
-  bit_size: 3
-  variants:
-  - description: Timer 6 TRGO event
-    name: TIM6_TRGO
-    value: 0
-  - description: Timer 3 TRGO event
-    name: TIM3_TRGO
-    value: 1
-  - description: Timer 7 TRGO event
-    name: TIM7_TRGO
-    value: 2
-  - description: Timer 15 TRGO event
-    name: TIM15_TRGO
-    value: 3
-  - description: Timer 2 TRGO event
-    name: TIM2_TRGO
-    value: 4
-  - description: EXTI line9
-    name: EXTI9
-    value: 6
-  - description: Software trigger
-    name: SOFTWARE
-    value: 7
-enum/TSEL2:
-  bit_size: 3
-  variants:
-  - description: Timer 6 TRGO event
-    name: TIM6_TRGO
-    value: 0
-  - description: Timer 8 TRGO event
-    name: TIM8_TRGO
-    value: 1
-  - description: Timer 7 TRGO event
-    name: TIM7_TRGO
-    value: 2
-  - description: Timer 5 TRGO event
-    name: TIM5_TRGO
-    value: 3
-  - description: Timer 2 TRGO event
-    name: TIM2_TRGO
-    value: 4
-  - description: Timer 4 TRGO event
-    name: TIM4_TRGO
-    value: 5
-  - description: EXTI line9
-    name: EXTI9
-    value: 6
-  - description: Software trigger
-    name: SOFTWARE
-    value: 7
-enum/WAVE:
-  bit_size: 2
-  variants:
-  - description: Wave generation disabled
-    name: Disabled
-    value: 0
-  - description: Noise wave generation enabled
-    name: Noise
-    value: 1
-  - description: Triangle wave generation enabled
-    name: Triangle
-    value: 2
+    - name: CR
+      description: control register
+      byte_offset: 0
+      fieldset: CR
+    - name: SWTRIGR
+      description: software trigger register
+      byte_offset: 4
+      access: Write
+      fieldset: SWTRIGR
+    - name: DHR12R1
+      description: channel1 12-bit right-aligned data holding register
+      byte_offset: 8
+      fieldset: DHR12R1
+    - name: DHR12L1
+      description: channel1 12-bit left aligned data holding register
+      byte_offset: 12
+      fieldset: DHR12L1
+    - name: DHR8R1
+      description: channel1 8-bit right aligned data holding register
+      byte_offset: 16
+      fieldset: DHR8R1
+    - name: DHR12R2
+      description: channel2 12-bit right aligned data holding register
+      byte_offset: 20
+      fieldset: DHR12R2
+    - name: DHR12L2
+      description: channel2 12-bit left aligned data holding register
+      byte_offset: 24
+      fieldset: DHR12L2
+    - name: DHR8R2
+      description: channel2 8-bit right-aligned data holding register
+      byte_offset: 28
+      fieldset: DHR8R2
+    - name: DHR12RD
+      description: Dual DAC 12-bit right-aligned data holding register
+      byte_offset: 32
+      fieldset: DHR12RD
+    - name: DHR12LD
+      description: DUAL DAC 12-bit left aligned data holding register
+      byte_offset: 36
+      fieldset: DHR12LD
+    - name: DHR8RD
+      description: DUAL DAC 8-bit right aligned data holding register
+      byte_offset: 40
+      fieldset: DHR8RD
+    - name: DOR1
+      description: channel1 data output register
+      byte_offset: 44
+      access: Read
+      fieldset: DOR1
+    - name: DOR2
+      description: channel2 data output register
+      byte_offset: 48
+      access: Read
+      fieldset: DOR2
+    - name: SR
+      description: status register
+      byte_offset: 52
+      fieldset: SR
 fieldset/CR:
   description: control register
   fields:
-  - array:
-      len: 2
-      stride: 16
-    bit_offset: 0
-    bit_size: 1
-    description: DAC channel1 enable
-    enum: EN
-    name: EN
-  - array:
-      len: 2
-      stride: 16
-    bit_offset: 1
-    bit_size: 1
-    description: DAC channel1 output buffer disable
-    enum: BOFF
-    name: BOFF
-  - array:
-      len: 2
-      stride: 16
-    bit_offset: 2
-    bit_size: 1
-    description: DAC channel1 trigger enable
-    enum: TEN
-    name: TEN
-  - array:
-      len: 2
-      stride: 16
-    bit_offset: 3
-    bit_size: 3
-    description: DAC channel1 trigger selection
-    enum: TSEL1
-    name: TSEL
-  - array:
-      len: 2
-      stride: 16
-    bit_offset: 6
-    bit_size: 2
-    description: DAC channel1 noise/triangle wave generation enable
-    enum: WAVE
-    name: WAVE
-  - array:
-      len: 2
-      stride: 16
-    bit_offset: 8
-    bit_size: 4
-    description: DAC channel1 mask/amplitude selector
-    name: MAMP
-  - array:
-      len: 2
-      stride: 16
-    bit_offset: 12
-    bit_size: 1
-    description: DAC channel1 DMA enable
-    enum: DMAEN
-    name: DMAEN
-  - array:
-      len: 2
-      stride: 16
-    bit_offset: 13
-    bit_size: 1
-    description: DAC channel1 DMA Underrun Interrupt enable
-    enum: DMAUDRIE
-    name: DMAUDRIE
+    - name: EN
+      description: DAC channel1 enable
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 2
+        stride: 16
+      enum: EN
+    - name: BOFF
+      description: DAC channel1 output buffer disable
+      bit_offset: 1
+      bit_size: 1
+      array:
+        len: 2
+        stride: 16
+      enum: BOFF
+    - name: TEN
+      description: DAC channel1 trigger enable
+      bit_offset: 2
+      bit_size: 1
+      array:
+        len: 2
+        stride: 16
+      enum: TEN
+    - name: TSEL
+      description: DAC channel1 trigger selection
+      bit_offset: 3
+      bit_size: 3
+      array:
+        len: 2
+        stride: 16
+      enum: TSEL1
+    - name: WAVE
+      description: DAC channel1 noise/triangle wave generation enable
+      bit_offset: 6
+      bit_size: 2
+      array:
+        len: 2
+        stride: 16
+      enum: WAVE
+    - name: MAMP
+      description: DAC channel1 mask/amplitude selector
+      bit_offset: 8
+      bit_size: 4
+      array:
+        len: 2
+        stride: 16
+    - name: DMAEN
+      description: DAC channel1 DMA enable
+      bit_offset: 12
+      bit_size: 1
+      array:
+        len: 2
+        stride: 16
+      enum: DMAEN
+    - name: DMAUDRIE
+      description: DAC channel1 DMA Underrun Interrupt enable
+      bit_offset: 13
+      bit_size: 1
+      array:
+        len: 2
+        stride: 16
+      enum: DMAUDRIE
 fieldset/DHR12L1:
   description: channel1 12-bit left aligned data holding register
   fields:
-  - bit_offset: 4
-    bit_size: 12
-    description: DAC channel1 12-bit left-aligned data
-    name: DACC1DHR
+    - name: DACC1DHR
+      description: DAC channel1 12-bit left-aligned data
+      bit_offset: 4
+      bit_size: 12
 fieldset/DHR12L2:
   description: channel2 12-bit left aligned data holding register
   fields:
-  - bit_offset: 4
-    bit_size: 12
-    description: DAC channel2 12-bit left-aligned data
-    name: DACC2DHR
+    - name: DACC2DHR
+      description: DAC channel2 12-bit left-aligned data
+      bit_offset: 4
+      bit_size: 12
 fieldset/DHR12LD:
   description: DUAL DAC 12-bit left aligned data holding register
   fields:
-  - bit_offset: 4
-    bit_size: 12
-    description: DAC channel1 12-bit left-aligned data
-    name: DACC1DHR
-  - bit_offset: 20
-    bit_size: 12
-    description: DAC channel2 12-bit left-aligned data
-    name: DACC2DHR
+    - name: DACC1DHR
+      description: DAC channel1 12-bit left-aligned data
+      bit_offset: 4
+      bit_size: 12
+    - name: DACC2DHR
+      description: DAC channel2 12-bit left-aligned data
+      bit_offset: 20
+      bit_size: 12
 fieldset/DHR12R1:
   description: channel1 12-bit right-aligned data holding register
   fields:
-  - bit_offset: 0
-    bit_size: 12
-    description: DAC channel1 12-bit right-aligned data
-    name: DACC1DHR
+    - name: DACC1DHR
+      description: DAC channel1 12-bit right-aligned data
+      bit_offset: 0
+      bit_size: 12
 fieldset/DHR12R2:
   description: channel2 12-bit right aligned data holding register
   fields:
-  - bit_offset: 0
-    bit_size: 12
-    description: DAC channel2 12-bit right-aligned data
-    name: DACC2DHR
+    - name: DACC2DHR
+      description: DAC channel2 12-bit right-aligned data
+      bit_offset: 0
+      bit_size: 12
 fieldset/DHR12RD:
   description: Dual DAC 12-bit right-aligned data holding register
   fields:
-  - bit_offset: 0
-    bit_size: 12
-    description: DAC channel1 12-bit right-aligned data
-    name: DACC1DHR
-  - bit_offset: 16
-    bit_size: 12
-    description: DAC channel2 12-bit right-aligned data
-    name: DACC2DHR
+    - name: DACC1DHR
+      description: DAC channel1 12-bit right-aligned data
+      bit_offset: 0
+      bit_size: 12
+    - name: DACC2DHR
+      description: DAC channel2 12-bit right-aligned data
+      bit_offset: 16
+      bit_size: 12
 fieldset/DHR8R1:
   description: channel1 8-bit right aligned data holding register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: DAC channel1 8-bit right-aligned data
-    name: DACC1DHR
+    - name: DACC1DHR
+      description: DAC channel1 8-bit right-aligned data
+      bit_offset: 0
+      bit_size: 8
 fieldset/DHR8R2:
   description: channel2 8-bit right-aligned data holding register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: DAC channel2 8-bit right-aligned data
-    name: DACC2DHR
+    - name: DACC2DHR
+      description: DAC channel2 8-bit right-aligned data
+      bit_offset: 0
+      bit_size: 8
 fieldset/DHR8RD:
   description: DUAL DAC 8-bit right aligned data holding register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: DAC channel1 8-bit right-aligned data
-    name: DACC1DHR
-  - bit_offset: 8
-    bit_size: 8
-    description: DAC channel2 8-bit right-aligned data
-    name: DACC2DHR
+    - name: DACC1DHR
+      description: DAC channel1 8-bit right-aligned data
+      bit_offset: 0
+      bit_size: 8
+    - name: DACC2DHR
+      description: DAC channel2 8-bit right-aligned data
+      bit_offset: 8
+      bit_size: 8
 fieldset/DOR1:
   description: channel1 data output register
   fields:
-  - bit_offset: 0
-    bit_size: 12
-    description: DAC channel1 data output
-    name: DACC1DOR
+    - name: DACC1DOR
+      description: DAC channel1 data output
+      bit_offset: 0
+      bit_size: 12
 fieldset/DOR2:
   description: channel2 data output register
   fields:
-  - bit_offset: 0
-    bit_size: 12
-    description: DAC channel2 data output
-    name: DACC2DOR
+    - name: DACC2DOR
+      description: DAC channel2 data output
+      bit_offset: 0
+      bit_size: 12
 fieldset/SR:
   description: status register
   fields:
-  - array:
-      len: 2
-      stride: 16
-    bit_offset: 13
-    bit_size: 1
-    description: DAC channel1 DMA underrun flag
-    enum: DMAUDR
-    name: DMAUDR
+    - name: DMAUDR
+      description: DAC channel1 DMA underrun flag
+      bit_offset: 13
+      bit_size: 1
+      array:
+        len: 2
+        stride: 16
+      enum: DMAUDR
 fieldset/SWTRIGR:
   description: software trigger register
   fields:
-  - array:
-      len: 2
-      stride: 1
-    bit_offset: 0
-    bit_size: 1
-    description: DAC channel1 software trigger
-    enum: SWTRIG
-    name: SWTRIG
+    - name: SWTRIG
+      description: DAC channel1 software trigger
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 2
+        stride: 1
+      enum: SWTRIG
+enum/BOFF:
+  bit_size: 1
+  variants:
+    - name: Enabled
+      description: DAC channel X output buffer enabled
+      value: 0
+    - name: Disabled
+      description: DAC channel X output buffer disabled
+      value: 1
+enum/DMAEN:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: DAC channel X DMA mode disabled
+      value: 0
+    - name: Enabled
+      description: DAC channel X DMA mode enabled
+      value: 1
+enum/DMAUDR:
+  bit_size: 1
+  variants:
+    - name: NoUnderrun
+      description: No DMA underrun error condition occurred for DAC channel X
+      value: 0
+    - name: Underrun
+      description: DMA underrun error condition occurred for DAC channel X
+      value: 1
+enum/DMAUDRIE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: DAC channel X DMA Underrun Interrupt disabled
+      value: 0
+    - name: Enabled
+      description: DAC channel X DMA Underrun Interrupt enabled
+      value: 1
+enum/EN:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: DAC channel X disabled
+      value: 0
+    - name: Enabled
+      description: DAC channel X enabled
+      value: 1
+enum/SWTRIG:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: DAC channel X software trigger disabled
+      value: 0
+    - name: Enabled
+      description: DAC channel X software trigger enabled
+      value: 1
+enum/TEN:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: DAC channel X trigger disabled
+      value: 0
+    - name: Enabled
+      description: DAC channel X trigger enabled
+      value: 1
+enum/TSEL1:
+  bit_size: 3
+  variants:
+    - name: TIM6_TRGO
+      description: Timer 6 TRGO event
+      value: 0
+    - name: TIM3_TRGO
+      description: Timer 3 TRGO event
+      value: 1
+    - name: TIM7_TRGO
+      description: Timer 7 TRGO event
+      value: 2
+    - name: TIM15_TRGO
+      description: Timer 15 TRGO event
+      value: 3
+    - name: TIM2_TRGO
+      description: Timer 2 TRGO event
+      value: 4
+    - name: EXTI9
+      description: EXTI line9
+      value: 6
+    - name: SOFTWARE
+      description: Software trigger
+      value: 7
+enum/TSEL2:
+  bit_size: 3
+  variants:
+    - name: TIM6_TRGO
+      description: Timer 6 TRGO event
+      value: 0
+    - name: TIM8_TRGO
+      description: Timer 8 TRGO event
+      value: 1
+    - name: TIM7_TRGO
+      description: Timer 7 TRGO event
+      value: 2
+    - name: TIM5_TRGO
+      description: Timer 5 TRGO event
+      value: 3
+    - name: TIM2_TRGO
+      description: Timer 2 TRGO event
+      value: 4
+    - name: TIM4_TRGO
+      description: Timer 4 TRGO event
+      value: 5
+    - name: EXTI9
+      description: EXTI line9
+      value: 6
+    - name: SOFTWARE
+      description: Software trigger
+      value: 7
+enum/WAVE:
+  bit_size: 2
+  variants:
+    - name: Disabled
+      description: Wave generation disabled
+      value: 0
+    - name: Noise
+      description: Noise wave generation enabled
+      value: 1
+    - name: Triangle
+      description: Triangle wave generation enabled
+      value: 2

data/registers/dcmi_v1.yaml

@@ -2,285 +2,285 @@
 block/DCMI:
   description: Digital camera interface
   items:
-  - byte_offset: 0
-    description: control register 1
-    fieldset: CR
-    name: CR
-  - access: Read
-    byte_offset: 4
-    description: status register
-    fieldset: SR
-    name: SR
-  - access: Read
-    byte_offset: 8
-    description: raw interrupt status register
-    fieldset: RIS
-    name: RIS
-  - byte_offset: 12
-    description: interrupt enable register
-    fieldset: IER
-    name: IER
-  - access: Read
-    byte_offset: 16
-    description: masked interrupt status register
-    fieldset: MIS
-    name: MIS
-  - access: Write
-    byte_offset: 20
-    description: interrupt clear register
-    fieldset: ICR
-    name: ICR
-  - byte_offset: 24
-    description: embedded synchronization code register
-    fieldset: ESCR
-    name: ESCR
-  - byte_offset: 28
-    description: embedded synchronization unmask register
-    fieldset: ESUR
-    name: ESUR
-  - byte_offset: 32
-    description: crop window start
-    fieldset: CWSTRT
-    name: CWSTRT
-  - byte_offset: 36
-    description: crop window size
-    fieldset: CWSIZE
-    name: CWSIZE
-  - access: Read
-    byte_offset: 40
-    description: data register
-    fieldset: DR
-    name: DR
+    - name: CR
+      description: control register 1
+      byte_offset: 0
+      fieldset: CR
+    - name: SR
+      description: status register
+      byte_offset: 4
+      access: Read
+      fieldset: SR
+    - name: RIS
+      description: raw interrupt status register
+      byte_offset: 8
+      access: Read
+      fieldset: RIS
+    - name: IER
+      description: interrupt enable register
+      byte_offset: 12
+      fieldset: IER
+    - name: MIS
+      description: masked interrupt status register
+      byte_offset: 16
+      access: Read
+      fieldset: MIS
+    - name: ICR
+      description: interrupt clear register
+      byte_offset: 20
+      access: Write
+      fieldset: ICR
+    - name: ESCR
+      description: embedded synchronization code register
+      byte_offset: 24
+      fieldset: ESCR
+    - name: ESUR
+      description: embedded synchronization unmask register
+      byte_offset: 28
+      fieldset: ESUR
+    - name: CWSTRT
+      description: crop window start
+      byte_offset: 32
+      fieldset: CWSTRT
+    - name: CWSIZE
+      description: crop window size
+      byte_offset: 36
+      fieldset: CWSIZE
+    - name: DR
+      description: data register
+      byte_offset: 40
+      access: Read
+      fieldset: DR
 fieldset/CR:
   description: control register 1
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Capture enable
-    name: CAPTURE
-  - bit_offset: 1
-    bit_size: 1
-    description: Capture mode
-    name: CM
-  - bit_offset: 2
-    bit_size: 1
-    description: Crop feature
-    name: CROP
-  - bit_offset: 3
-    bit_size: 1
-    description: JPEG format
-    name: JPEG
-  - bit_offset: 4
-    bit_size: 1
-    description: Embedded synchronization select
-    name: ESS
-  - bit_offset: 5
-    bit_size: 1
-    description: Pixel clock polarity
-    name: PCKPOL
-  - bit_offset: 6
-    bit_size: 1
-    description: Horizontal synchronization polarity
-    name: HSPOL
-  - bit_offset: 7
-    bit_size: 1
-    description: Vertical synchronization polarity
-    name: VSPOL
-  - bit_offset: 8
-    bit_size: 2
-    description: Frame capture rate control
-    name: FCRC
-  - bit_offset: 10
-    bit_size: 2
-    description: Extended data mode
-    name: EDM
-  - bit_offset: 14
-    bit_size: 1
-    description: DCMI enable
-    name: ENABLE
+    - name: CAPTURE
+      description: Capture enable
+      bit_offset: 0
+      bit_size: 1
+    - name: CM
+      description: Capture mode
+      bit_offset: 1
+      bit_size: 1
+    - name: CROP
+      description: Crop feature
+      bit_offset: 2
+      bit_size: 1
+    - name: JPEG
+      description: JPEG format
+      bit_offset: 3
+      bit_size: 1
+    - name: ESS
+      description: Embedded synchronization select
+      bit_offset: 4
+      bit_size: 1
+    - name: PCKPOL
+      description: Pixel clock polarity
+      bit_offset: 5
+      bit_size: 1
+    - name: HSPOL
+      description: Horizontal synchronization polarity
+      bit_offset: 6
+      bit_size: 1
+    - name: VSPOL
+      description: Vertical synchronization polarity
+      bit_offset: 7
+      bit_size: 1
+    - name: FCRC
+      description: Frame capture rate control
+      bit_offset: 8
+      bit_size: 2
+    - name: EDM
+      description: Extended data mode
+      bit_offset: 10
+      bit_size: 2
+    - name: ENABLE
+      description: DCMI enable
+      bit_offset: 14
+      bit_size: 1
 fieldset/CWSIZE:
   description: crop window size
   fields:
-  - bit_offset: 0
-    bit_size: 14
-    description: Capture count
-    name: CAPCNT
-  - bit_offset: 16
-    bit_size: 14
-    description: Vertical line count
-    name: VLINE
+    - name: CAPCNT
+      description: Capture count
+      bit_offset: 0
+      bit_size: 14
+    - name: VLINE
+      description: Vertical line count
+      bit_offset: 16
+      bit_size: 14
 fieldset/CWSTRT:
   description: crop window start
   fields:
-  - bit_offset: 0
-    bit_size: 14
-    description: Horizontal offset count
-    name: HOFFCNT
-  - bit_offset: 16
-    bit_size: 13
-    description: Vertical start line count
-    name: VST
+    - name: HOFFCNT
+      description: Horizontal offset count
+      bit_offset: 0
+      bit_size: 14
+    - name: VST
+      description: Vertical start line count
+      bit_offset: 16
+      bit_size: 13
 fieldset/DR:
   description: data register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: Data byte 0
-    name: Byte0
-  - bit_offset: 8
-    bit_size: 8
-    description: Data byte 1
-    name: Byte1
-  - bit_offset: 16
-    bit_size: 8
-    description: Data byte 2
-    name: Byte2
-  - bit_offset: 24
-    bit_size: 8
-    description: Data byte 3
-    name: Byte3
+    - name: Byte0
+      description: Data byte 0
+      bit_offset: 0
+      bit_size: 8
+    - name: Byte1
+      description: Data byte 1
+      bit_offset: 8
+      bit_size: 8
+    - name: Byte2
+      description: Data byte 2
+      bit_offset: 16
+      bit_size: 8
+    - name: Byte3
+      description: Data byte 3
+      bit_offset: 24
+      bit_size: 8
 fieldset/ESCR:
   description: embedded synchronization code register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: Frame start delimiter code
-    name: FSC
-  - bit_offset: 8
-    bit_size: 8
-    description: Line start delimiter code
-    name: LSC
-  - bit_offset: 16
-    bit_size: 8
-    description: Line end delimiter code
-    name: LEC
-  - bit_offset: 24
-    bit_size: 8
-    description: Frame end delimiter code
-    name: FEC
+    - name: FSC
+      description: Frame start delimiter code
+      bit_offset: 0
+      bit_size: 8
+    - name: LSC
+      description: Line start delimiter code
+      bit_offset: 8
+      bit_size: 8
+    - name: LEC
+      description: Line end delimiter code
+      bit_offset: 16
+      bit_size: 8
+    - name: FEC
+      description: Frame end delimiter code
+      bit_offset: 24
+      bit_size: 8
 fieldset/ESUR:
   description: embedded synchronization unmask register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: Frame start delimiter unmask
-    name: FSU
-  - bit_offset: 8
-    bit_size: 8
-    description: Line start delimiter unmask
-    name: LSU
-  - bit_offset: 16
-    bit_size: 8
-    description: Line end delimiter unmask
-    name: LEU
-  - bit_offset: 24
-    bit_size: 8
-    description: Frame end delimiter unmask
-    name: FEU
+    - name: FSU
+      description: Frame start delimiter unmask
+      bit_offset: 0
+      bit_size: 8
+    - name: LSU
+      description: Line start delimiter unmask
+      bit_offset: 8
+      bit_size: 8
+    - name: LEU
+      description: Line end delimiter unmask
+      bit_offset: 16
+      bit_size: 8
+    - name: FEU
+      description: Frame end delimiter unmask
+      bit_offset: 24
+      bit_size: 8
 fieldset/ICR:
   description: interrupt clear register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Capture complete interrupt status clear
-    name: FRAME_ISC
-  - bit_offset: 1
-    bit_size: 1
-    description: Overrun interrupt status clear
-    name: OVR_ISC
-  - bit_offset: 2
-    bit_size: 1
-    description: Synchronization error interrupt status clear
-    name: ERR_ISC
-  - bit_offset: 3
-    bit_size: 1
-    description: Vertical synch interrupt status clear
-    name: VSYNC_ISC
-  - bit_offset: 4
-    bit_size: 1
-    description: line interrupt status clear
-    name: LINE_ISC
+    - name: FRAME_ISC
+      description: Capture complete interrupt status clear
+      bit_offset: 0
+      bit_size: 1
+    - name: OVR_ISC
+      description: Overrun interrupt status clear
+      bit_offset: 1
+      bit_size: 1
+    - name: ERR_ISC
+      description: Synchronization error interrupt status clear
+      bit_offset: 2
+      bit_size: 1
+    - name: VSYNC_ISC
+      description: Vertical synch interrupt status clear
+      bit_offset: 3
+      bit_size: 1
+    - name: LINE_ISC
+      description: line interrupt status clear
+      bit_offset: 4
+      bit_size: 1
 fieldset/IER:
   description: interrupt enable register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Capture complete interrupt enable
-    name: FRAME_IE
-  - bit_offset: 1
-    bit_size: 1
-    description: Overrun interrupt enable
-    name: OVR_IE
-  - bit_offset: 2
-    bit_size: 1
-    description: Synchronization error interrupt enable
-    name: ERR_IE
-  - bit_offset: 3
-    bit_size: 1
-    description: VSYNC interrupt enable
-    name: VSYNC_IE
-  - bit_offset: 4
-    bit_size: 1
-    description: Line interrupt enable
-    name: LINE_IE
+    - name: FRAME_IE
+      description: Capture complete interrupt enable
+      bit_offset: 0
+      bit_size: 1
+    - name: OVR_IE
+      description: Overrun interrupt enable
+      bit_offset: 1
+      bit_size: 1
+    - name: ERR_IE
+      description: Synchronization error interrupt enable
+      bit_offset: 2
+      bit_size: 1
+    - name: VSYNC_IE
+      description: VSYNC interrupt enable
+      bit_offset: 3
+      bit_size: 1
+    - name: LINE_IE
+      description: Line interrupt enable
+      bit_offset: 4
+      bit_size: 1
 fieldset/MIS:
   description: masked interrupt status register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Capture complete masked interrupt status
-    name: FRAME_MIS
-  - bit_offset: 1
-    bit_size: 1
-    description: Overrun masked interrupt status
-    name: OVR_MIS
-  - bit_offset: 2
-    bit_size: 1
-    description: Synchronization error masked interrupt status
-    name: ERR_MIS
-  - bit_offset: 3
-    bit_size: 1
-    description: VSYNC masked interrupt status
-    name: VSYNC_MIS
-  - bit_offset: 4
-    bit_size: 1
-    description: Line masked interrupt status
-    name: LINE_MIS
+    - name: FRAME_MIS
+      description: Capture complete masked interrupt status
+      bit_offset: 0
+      bit_size: 1
+    - name: OVR_MIS
+      description: Overrun masked interrupt status
+      bit_offset: 1
+      bit_size: 1
+    - name: ERR_MIS
+      description: Synchronization error masked interrupt status
+      bit_offset: 2
+      bit_size: 1
+    - name: VSYNC_MIS
+      description: VSYNC masked interrupt status
+      bit_offset: 3
+      bit_size: 1
+    - name: LINE_MIS
+      description: Line masked interrupt status
+      bit_offset: 4
+      bit_size: 1
 fieldset/RIS:
   description: raw interrupt status register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Capture complete raw interrupt status
-    name: FRAME_RIS
-  - bit_offset: 1
-    bit_size: 1
-    description: Overrun raw interrupt status
-    name: OVR_RIS
-  - bit_offset: 2
-    bit_size: 1
-    description: Synchronization error raw interrupt status
-    name: ERR_RIS
-  - bit_offset: 3
-    bit_size: 1
-    description: VSYNC raw interrupt status
-    name: VSYNC_RIS
-  - bit_offset: 4
-    bit_size: 1
-    description: Line raw interrupt status
-    name: LINE_RIS
+    - name: FRAME_RIS
+      description: Capture complete raw interrupt status
+      bit_offset: 0
+      bit_size: 1
+    - name: OVR_RIS
+      description: Overrun raw interrupt status
+      bit_offset: 1
+      bit_size: 1
+    - name: ERR_RIS
+      description: Synchronization error raw interrupt status
+      bit_offset: 2
+      bit_size: 1
+    - name: VSYNC_RIS
+      description: VSYNC raw interrupt status
+      bit_offset: 3
+      bit_size: 1
+    - name: LINE_RIS
+      description: Line raw interrupt status
+      bit_offset: 4
+      bit_size: 1
 fieldset/SR:
   description: status register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: HSYNC
-    name: HSYNC
-  - bit_offset: 1
-    bit_size: 1
-    description: VSYNC
-    name: VSYNC
-  - bit_offset: 2
-    bit_size: 1
-    description: FIFO not empty
-    name: FNE
+    - name: HSYNC
+      description: HSYNC
+      bit_offset: 0
+      bit_size: 1
+    - name: VSYNC
+      description: VSYNC
+      bit_offset: 1
+      bit_size: 1
+    - name: FNE
+      description: FIFO not empty
+      bit_offset: 2
+      bit_size: 1

data/registers/dma_v1.yaml

@@ -8,7 +8,6 @@ block/DMA:
         len: 2
         stride: 4
       byte_offset: 0
-      reset_value: 0
       access: Read
       fieldset: IXR
     - name: IFCR
@@ -17,7 +16,6 @@ block/DMA:
         len: 2
         stride: 4
       byte_offset: 8
-      reset_value: 0
       access: Write
       fieldset: IXR
     - name: ST
@@ -33,29 +31,23 @@ block/ST:
     - name: CR
       description: stream x configuration register
       byte_offset: 0
-      reset_value: 0
       fieldset: CR
     - name: NDTR
       description: stream x number of data register
       byte_offset: 4
-      reset_value: 0
       fieldset: NDTR
     - name: PAR
       description: stream x peripheral address register
       byte_offset: 8
-      reset_value: 0
     - name: M0AR
       description: stream x memory 0 address register
       byte_offset: 12
-      reset_value: 0
     - name: M1AR
       description: stream x memory 1 address register
       byte_offset: 16
-      reset_value: 0
     - name: FCR
       description: stream x FIFO control register
       byte_offset: 20
-      reset_value: 33
       fieldset: FCR
 fieldset/CR:
   description: stream x configuration register
@@ -231,6 +223,21 @@ fieldset/NDTR:
       description: Number of data items to transfer
       bit_offset: 0
       bit_size: 16
+enum/BURST:
+  bit_size: 2
+  variants:
+    - name: Single
+      description: Single transfer
+      value: 0
+    - name: INCR4
+      description: Incremental burst of 4 beats
+      value: 1
+    - name: INCR8
+      description: Incremental burst of 8 beats
+      value: 2
+    - name: INCR16
+      description: Incremental burst of 16 beats
+      value: 3
 enum/CIRC:
   bit_size: 1
   variants:
@@ -315,21 +322,6 @@ enum/FTH:
     - name: Full
       description: Full FIFO
       value: 3
-enum/BURST:
-  bit_size: 2
-  variants:
-    - name: Single
-      description: Single transfer
-      value: 0
-    - name: INCR4
-      description: Incremental burst of 4 beats
-      value: 1
-    - name: INCR8
-      description: Incremental burst of 8 beats
-      value: 2
-    - name: INCR16
-      description: Incremental burst of 16 beats
-      value: 3
 enum/INC:
   bit_size: 1
   variants:
@@ -339,18 +331,6 @@ enum/INC:
     - name: Incremented
       description: Address pointer is incremented after each data transfer
       value: 1
-enum/SIZE:
-  bit_size: 2
-  variants:
-    - name: Bits8
-      description: Byte (8-bit)
-      value: 0
-    - name: Bits16
-      description: Half-word (16-bit)
-      value: 1
-    - name: Bits32
-      description: Word (32-bit)
-      value: 2
 enum/PFCTRL:
   bit_size: 1
   variants:
@@ -384,3 +364,15 @@ enum/PL:
     - name: VeryHigh
       description: Very high
       value: 3
+enum/SIZE:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: Byte (8-bit)
+      value: 0
+    - name: Bits16
+      description: Half-word (16-bit)
+      value: 1
+    - name: Bits32
+      description: Word (32-bit)
+      value: 2

data/registers/dma_v2.yaml

@@ -8,7 +8,6 @@ block/DMA:
         len: 2
         stride: 4
       byte_offset: 0
-      reset_value: 0
       access: Read
       fieldset: IXR
     - name: IFCR
@@ -17,7 +16,6 @@ block/DMA:
         len: 2
         stride: 4
       byte_offset: 8
-      reset_value: 0
       access: Write
       fieldset: IXR
     - name: ST
@@ -33,29 +31,23 @@ block/ST:
     - name: CR
       description: stream x configuration register
       byte_offset: 0
-      reset_value: 0
       fieldset: CR
     - name: NDTR
       description: stream x number of data register
       byte_offset: 4
-      reset_value: 0
       fieldset: NDTR
     - name: PAR
       description: stream x peripheral address register
       byte_offset: 8
-      reset_value: 0
     - name: M0AR
       description: stream x memory 0 address register
       byte_offset: 12
-      reset_value: 0
     - name: M1AR
       description: stream x memory 1 address register
       byte_offset: 16
-      reset_value: 0
     - name: FCR
       description: stream x FIFO control register
       byte_offset: 20
-      reset_value: 33
       fieldset: FCR
 fieldset/CR:
   description: stream x configuration register
@@ -231,6 +223,21 @@ fieldset/NDTR:
       description: Number of data items to transfer
       bit_offset: 0
       bit_size: 16
+enum/BURST:
+  bit_size: 2
+  variants:
+    - name: Single
+      description: Single transfer
+      value: 0
+    - name: INCR4
+      description: Incremental burst of 4 beats
+      value: 1
+    - name: INCR8
+      description: Incremental burst of 8 beats
+      value: 2
+    - name: INCR16
+      description: Incremental burst of 16 beats
+      value: 3
 enum/CIRC:
   bit_size: 1
   variants:
@@ -315,21 +322,6 @@ enum/FTH:
     - name: Full
       description: Full FIFO
       value: 3
-enum/BURST:
-  bit_size: 2
-  variants:
-    - name: Single
-      description: Single transfer
-      value: 0
-    - name: INCR4
-      description: Incremental burst of 4 beats
-      value: 1
-    - name: INCR8
-      description: Incremental burst of 8 beats
-      value: 2
-    - name: INCR16
-      description: Incremental burst of 16 beats
-      value: 3
 enum/INC:
   bit_size: 1
   variants:
@@ -339,18 +331,6 @@ enum/INC:
     - name: Incremented
       description: Address pointer is incremented after each data transfer
       value: 1
-enum/SIZE:
-  bit_size: 2
-  variants:
-    - name: Bits8
-      description: Byte (8-bit)
-      value: 0
-    - name: Bits16
-      description: Half-word (16-bit)
-      value: 1
-    - name: Bits32
-      description: Word (32-bit)
-      value: 2
 enum/PFCTRL:
   bit_size: 1
   variants:
@@ -384,3 +364,15 @@ enum/PL:
     - name: VeryHigh
       description: Very high
       value: 3
+enum/SIZE:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: Byte (8-bit)
+      value: 0
+    - name: Bits16
+      description: Half-word (16-bit)
+      value: 1
+    - name: Bits32
+      description: Word (32-bit)
+      value: 2

data/registers/exti_g0.yaml

@@ -48,7 +48,7 @@ block/EXTI:
       description: Interrupt mask register
       array:
         len: 2
-        stride: 16 
+        stride: 16
       byte_offset: 128
       fieldset: LINES
     - name: EMR
@@ -69,7 +69,7 @@ fieldset/EXTICR:
         len: 4
         stride: 8
 fieldset/LINES:
-  description: EXTI lines register, 1 bit per line
+  description: "EXTI lines register, 1 bit per line"
   fields:
     - name: LINE
       description: EXTI line

data/registers/exti_h7.yaml

@@ -45,7 +45,7 @@ block/EXTI:
       byte_offset: 136
       fieldset: LINES
 fieldset/LINES:
-  description: EXTI lines register, 1 bit per line
+  description: "EXTI lines register, 1 bit per line"
   fields:
     - name: LINE
       description: EXTI line

data/registers/exti_l5.yaml

@@ -87,7 +87,7 @@ fieldset/EXTICR:
         len: 4
         stride: 8
 fieldset/LINES:
-  description: EXTI lines register, 1 bit per line
+  description: "EXTI lines register, 1 bit per line"
   fields:
     - name: LINE
       description: EXTI line

data/registers/exti_u5.yaml

@@ -87,7 +87,7 @@ fieldset/EXTICR:
         len: 4
         stride: 8
 fieldset/LINES:
-  description: EXTI lines register, 1 bit per line
+  description: "EXTI lines register, 1 bit per line"
   fields:
     - name: LINE
       description: EXTI line

data/registers/exti_v1.yaml

@@ -45,7 +45,7 @@ block/EXTI:
       byte_offset: 20
       fieldset: LINES
 fieldset/LINES:
-  description: EXTI lines register, 1 bit per line
+  description: "EXTI lines register, 1 bit per line"
   fields:
     - name: LINE
       description: EXTI line

data/registers/exti_w.yaml

@@ -1,4 +1,21 @@
 ---
+block/CPU:
+  description: CPU-specific registers
+  items:
+    - name: IMR
+      description: CPU x interrupt mask register
+      array:
+        len: 2
+        stride: 16
+      byte_offset: 0
+      fieldset: LINES
+    - name: EMR
+      description: CPU x event mask register
+      array:
+        len: 2
+        stride: 16
+      byte_offset: 4
+      fieldset: LINES
 block/EXTI:
   description: External interrupt/event controller
   items:
@@ -32,30 +49,13 @@ block/EXTI:
       fieldset: LINES
     - name: CPU
       description: CPU specific registers
-      byte_offset: 128
-      block: CPU
       array:
         len: 2
         stride: 64
-block/CPU:
-  description: CPU-specific registers
-  items:
-    - name: IMR
-      description: CPU x interrupt mask register
-      byte_offset: 0
-      fieldset: LINES
-      array:
-        len: 2
-        stride: 16
-    - name: EMR
-      description: CPU x event mask register
-      array:
-        len: 2
-        stride: 16
-      byte_offset: 4
-      fieldset: LINES
+      byte_offset: 128
+      block: CPU
 fieldset/LINES:
-  description: EXTI lines register, 1 bit per line
+  description: "EXTI lines register, 1 bit per line"
   fields:
     - name: LINE
       description: EXTI line

data/registers/exti_wle.yaml

@@ -45,7 +45,7 @@ block/EXTI:
       byte_offset: 132
       fieldset: LINES
 fieldset/LINES:
-  description: EXTI lines register, 1 bit per line
+  description: "EXTI lines register, 1 bit per line"
   fields:
     - name: LINE
       description: EXTI line

data/registers/flash_f1.yaml

@@ -1,193 +1,194 @@
+---
 block/FLASH:
   description: FLASH
   items:
-  - byte_offset: 0
-    description: Flash access control register
-    fieldset: ACR
-    name: ACR
-  - access: Write
-    byte_offset: 4
-    description: Flash key register
-    fieldset: KEYR
-    name: KEYR
-  - access: Write
-    byte_offset: 8
-    description: Flash option key register
-    fieldset: OPTKEYR
-    name: OPTKEYR
-  - byte_offset: 12
-    description: Status register
-    fieldset: SR
-    name: SR
-  - byte_offset: 16
-    description: Control register
-    fieldset: CR
-    name: CR
-  - access: Write
-    byte_offset: 20
-    description: Flash address register
-    fieldset: AR
-    name: AR
-  - access: Read
-    byte_offset: 28
-    description: Option byte register
-    fieldset: OBR
-    name: OBR
-  - access: Read
-    byte_offset: 32
-    description: Write protection register
-    fieldset: WRPR
-    name: WRPR
-enum/LATENCY:
-  bit_size: 3
-  variants:
-  - description: "Zero wait state, if 0 < SYSCLK\u2264 24 MHz"
-    name: WS0
-    value: 0
-  - description: "One wait state, if 24 MHz < SYSCLK \u2264 48 MHz"
-    name: WS1
-    value: 1
-  - description: "Two wait states, if 48 MHz < SYSCLK \u2264 72 MHz"
-    name: WS2
-    value: 2
+    - name: ACR
+      description: Flash access control register
+      byte_offset: 0
+      fieldset: ACR
+    - name: KEYR
+      description: Flash key register
+      byte_offset: 4
+      access: Write
+      fieldset: KEYR
+    - name: OPTKEYR
+      description: Flash option key register
+      byte_offset: 8
+      access: Write
+      fieldset: OPTKEYR
+    - name: SR
+      description: Status register
+      byte_offset: 12
+      fieldset: SR
+    - name: CR
+      description: Control register
+      byte_offset: 16
+      fieldset: CR
+    - name: AR
+      description: Flash address register
+      byte_offset: 20
+      access: Write
+      fieldset: AR
+    - name: OBR
+      description: Option byte register
+      byte_offset: 28
+      access: Read
+      fieldset: OBR
+    - name: WRPR
+      description: Write protection register
+      byte_offset: 32
+      access: Read
+      fieldset: WRPR
 fieldset/ACR:
   description: Flash access control register
   fields:
-  - bit_offset: 0
-    bit_size: 3
-    description: Latency
-    enum: LATENCY
-    name: LATENCY
-  - bit_offset: 3
-    bit_size: 1
-    description: Flash half cycle access enable
-    name: HLFCYA
-  - bit_offset: 4
-    bit_size: 1
-    description: Prefetch buffer enable
-    name: PRFTBE
-  - bit_offset: 5
-    bit_size: 1
-    description: Prefetch buffer status
-    name: PRFTBS
+    - name: LATENCY
+      description: Latency
+      bit_offset: 0
+      bit_size: 3
+      enum: LATENCY
+    - name: HLFCYA
+      description: Flash half cycle access enable
+      bit_offset: 3
+      bit_size: 1
+    - name: PRFTBE
+      description: Prefetch buffer enable
+      bit_offset: 4
+      bit_size: 1
+    - name: PRFTBS
+      description: Prefetch buffer status
+      bit_offset: 5
+      bit_size: 1
 fieldset/AR:
   description: Flash address register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Flash Address
-    name: FAR
+    - name: FAR
+      description: Flash Address
+      bit_offset: 0
+      bit_size: 32
 fieldset/CR:
   description: Control register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Programming
-    name: PG
-  - bit_offset: 1
-    bit_size: 1
-    description: Page Erase
-    name: PER
-  - bit_offset: 2
-    bit_size: 1
-    description: Mass Erase
-    name: MER
-  - bit_offset: 4
-    bit_size: 1
-    description: Option byte programming
-    name: OPTPG
-  - bit_offset: 5
-    bit_size: 1
-    description: Option byte erase
-    name: OPTER
-  - bit_offset: 6
-    bit_size: 1
-    description: Start
-    name: STRT
-  - bit_offset: 7
-    bit_size: 1
-    description: Lock
-    name: LOCK
-  - bit_offset: 9
-    bit_size: 1
-    description: Option bytes write enable
-    name: OPTWRE
-  - bit_offset: 10
-    bit_size: 1
-    description: Error interrupt enable
-    name: ERRIE
-  - bit_offset: 12
-    bit_size: 1
-    description: End of operation interrupt enable
-    name: EOPIE
+    - name: PG
+      description: Programming
+      bit_offset: 0
+      bit_size: 1
+    - name: PER
+      description: Page Erase
+      bit_offset: 1
+      bit_size: 1
+    - name: MER
+      description: Mass Erase
+      bit_offset: 2
+      bit_size: 1
+    - name: OPTPG
+      description: Option byte programming
+      bit_offset: 4
+      bit_size: 1
+    - name: OPTER
+      description: Option byte erase
+      bit_offset: 5
+      bit_size: 1
+    - name: STRT
+      description: Start
+      bit_offset: 6
+      bit_size: 1
+    - name: LOCK
+      description: Lock
+      bit_offset: 7
+      bit_size: 1
+    - name: OPTWRE
+      description: Option bytes write enable
+      bit_offset: 9
+      bit_size: 1
+    - name: ERRIE
+      description: Error interrupt enable
+      bit_offset: 10
+      bit_size: 1
+    - name: EOPIE
+      description: End of operation interrupt enable
+      bit_offset: 12
+      bit_size: 1
 fieldset/KEYR:
   description: Flash key register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: FPEC key
-    name: KEY
+    - name: KEY
+      description: FPEC key
+      bit_offset: 0
+      bit_size: 32
 fieldset/OBR:
   description: Option byte register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Option byte error
-    name: OPTERR
-  - bit_offset: 1
-    bit_size: 1
-    description: Read protection
-    name: RDPRT
-  - bit_offset: 2
-    bit_size: 1
-    description: WDG_SW
-    name: WDG_SW
-  - bit_offset: 3
-    bit_size: 1
-    description: nRST_STOP
-    name: nRST_STOP
-  - bit_offset: 4
-    bit_size: 1
-    description: nRST_STDBY
-    name: nRST_STDBY
-  - bit_offset: 10
-    bit_size: 8
-    description: Data0
-    name: Data0
-  - bit_offset: 18
-    bit_size: 8
-    description: Data1
-    name: Data1
+    - name: OPTERR
+      description: Option byte error
+      bit_offset: 0
+      bit_size: 1
+    - name: RDPRT
+      description: Read protection
+      bit_offset: 1
+      bit_size: 1
+    - name: WDG_SW
+      description: WDG_SW
+      bit_offset: 2
+      bit_size: 1
+    - name: nRST_STOP
+      description: nRST_STOP
+      bit_offset: 3
+      bit_size: 1
+    - name: nRST_STDBY
+      description: nRST_STDBY
+      bit_offset: 4
+      bit_size: 1
+    - name: Data0
+      description: Data0
+      bit_offset: 10
+      bit_size: 8
+    - name: Data1
+      description: Data1
+      bit_offset: 18
+      bit_size: 8
 fieldset/OPTKEYR:
   description: Flash option key register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Option byte key
-    name: OPTKEY
+    - name: OPTKEY
+      description: Option byte key
+      bit_offset: 0
+      bit_size: 32
 fieldset/SR:
   description: Status register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Busy
-    name: BSY
-  - bit_offset: 2
-    bit_size: 1
-    description: Programming error
-    name: PGERR
-  - bit_offset: 4
-    bit_size: 1
-    description: Write protection error
-    name: WRPRTERR
-  - bit_offset: 5
-    bit_size: 1
-    description: End of operation
-    name: EOP
+    - name: BSY
+      description: Busy
+      bit_offset: 0
+      bit_size: 1
+    - name: PGERR
+      description: Programming error
+      bit_offset: 2
+      bit_size: 1
+    - name: WRPRTERR
+      description: Write protection error
+      bit_offset: 4
+      bit_size: 1
+    - name: EOP
+      description: End of operation
+      bit_offset: 5
+      bit_size: 1
 fieldset/WRPR:
   description: Write protection register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Write protect
-    name: WRP
+    - name: WRP
+      description: Write protect
+      bit_offset: 0
+      bit_size: 32
+enum/LATENCY:
+  bit_size: 3
+  variants:
+    - name: WS0
+      description: "Zero wait state, if 0 < SYSCLK≤ 24 MHz"
+      value: 0
+    - name: WS1
+      description: "One wait state, if 24 MHz < SYSCLK ≤ 48 MHz"
+      value: 1
+    - name: WS2
+      description: "Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz"
+      value: 2

data/registers/flash_f7.yaml

@@ -2,381 +2,381 @@
 block/FLASH:
   description: FLASH
   items:
-  - byte_offset: 0
-    description: Flash access control register
-    fieldset: ACR
-    name: ACR
-  - access: Write
-    byte_offset: 4
-    description: Flash key register
-    fieldset: KEYR
-    name: KEYR
-  - access: Write
-    byte_offset: 8
-    description: Flash option key register
-    fieldset: OPTKEYR
-    name: OPTKEYR
-  - byte_offset: 12
-    description: Status register
-    fieldset: SR
-    name: SR
-  - byte_offset: 16
-    description: Control register
-    fieldset: CR
-    name: CR
-  - byte_offset: 20
-    description: Flash option control register
-    fieldset: OPTCR
-    name: OPTCR
-  - byte_offset: 24
-    description: Flash option control register 1
-    fieldset: OPTCR1
-    name: OPTCR1
-  - byte_offset: 28
-    description: Flash option control register
-    fieldset: OPTCR2
-    name: OPTCR2
-enum/ARTEN:
-  bit_size: 1
-  variants:
-  - description: ART Accelerator is disabled
-    name: Disabled
-    value: 0
-  - description: ART Accelerator is enabled
-    name: Enabled
-    value: 1
-enum/ARTRST:
-  bit_size: 1
-  variants:
-  - description: Accelerator is not reset
-    name: NotReset
-    value: 0
-  - description: Accelerator is reset
-    name: Reset
-    value: 1
-enum/EOPIE:
-  bit_size: 1
-  variants:
-  - description: End of operation interrupt disabled
-    name: Disabled
-    value: 0
-  - description: End of operation interrupt enabled
-    name: Enabled
-    value: 1
-enum/ERRIE:
-  bit_size: 1
-  variants:
-  - description: Error interrupt generation disabled
-    name: Disabled
-    value: 0
-  - description: Error interrupt generation enabled
-    name: Enabled
-    value: 1
-enum/LATENCY:
-  bit_size: 4
-  variants:
-  - description: 0 wait states
-    name: WS0
-    value: 0
-  - description: 1 wait states
-    name: WS1
-    value: 1
-  - description: 2 wait states
-    name: WS2
-    value: 2
-  - description: 3 wait states
-    name: WS3
-    value: 3
-  - description: 4 wait states
-    name: WS4
-    value: 4
-  - description: 5 wait states
-    name: WS5
-    value: 5
-  - description: 6 wait states
-    name: WS6
-    value: 6
-  - description: 7 wait states
-    name: WS7
-    value: 7
-  - description: 8 wait states
-    name: WS8
-    value: 8
-  - description: 9 wait states
-    name: WS9
-    value: 9
-  - description: 10 wait states
-    name: WS10
-    value: 10
-  - description: 11 wait states
-    name: WS11
-    value: 11
-  - description: 12 wait states
-    name: WS12
-    value: 12
-  - description: 13 wait states
-    name: WS13
-    value: 13
-  - description: 14 wait states
-    name: WS14
-    value: 14
-  - description: 15 wait states
-    name: WS15
-    value: 15
-enum/LOCK:
-  bit_size: 1
-  variants:
-  - description: FLASH_CR register is unlocked
-    name: Unlocked
-    value: 0
-  - description: FLASH_CR register is locked
-    name: Locked
-    value: 1
-enum/MER:
-  bit_size: 1
-  variants:
-  - description: Erase activated for all user sectors
-    name: MassErase
-    value: 1
-enum/PG:
-  bit_size: 1
-  variants:
-  - description: Flash programming activated
-    name: Program
-    value: 1
-enum/PRFTEN:
-  bit_size: 1
-  variants:
-  - description: Prefetch is disabled
-    name: Disabled
-    value: 0
-  - description: Prefetch is enabled
-    name: Enabled
-    value: 1
-enum/PSIZE:
-  bit_size: 2
-  variants:
-  - description: Program x8
-    name: PSIZE8
-    value: 0
-  - description: Program x16
-    name: PSIZE16
-    value: 1
-  - description: Program x32
-    name: PSIZE32
-    value: 2
-  - description: Program x64
-    name: PSIZE64
-    value: 3
-enum/SER:
-  bit_size: 1
-  variants:
-  - description: Erase activated for selected sector
-    name: SectorErase
-    value: 1
-enum/STRT:
-  bit_size: 1
-  variants:
-  - description: Trigger an erase operation
-    name: Start
-    value: 1
+    - name: ACR
+      description: Flash access control register
+      byte_offset: 0
+      fieldset: ACR
+    - name: KEYR
+      description: Flash key register
+      byte_offset: 4
+      access: Write
+      fieldset: KEYR
+    - name: OPTKEYR
+      description: Flash option key register
+      byte_offset: 8
+      access: Write
+      fieldset: OPTKEYR
+    - name: SR
+      description: Status register
+      byte_offset: 12
+      fieldset: SR
+    - name: CR
+      description: Control register
+      byte_offset: 16
+      fieldset: CR
+    - name: OPTCR
+      description: Flash option control register
+      byte_offset: 20
+      fieldset: OPTCR
+    - name: OPTCR1
+      description: Flash option control register 1
+      byte_offset: 24
+      fieldset: OPTCR1
+    - name: OPTCR2
+      description: Flash option control register
+      byte_offset: 28
+      fieldset: OPTCR2
 fieldset/ACR:
   description: Flash access control register
   fields:
-  - bit_offset: 0
-    bit_size: 4
-    description: Latency
-    enum: LATENCY
-    name: LATENCY
-  - bit_offset: 8
-    bit_size: 1
-    description: Prefetch enable
-    enum: PRFTEN
-    name: PRFTEN
-  - bit_offset: 9
-    bit_size: 1
-    description: ART Accelerator Enable
-    enum: ARTEN
-    name: ARTEN
-  - bit_offset: 11
-    bit_size: 1
-    description: ART Accelerator reset
-    enum: ARTRST
-    name: ARTRST
+    - name: LATENCY
+      description: Latency
+      bit_offset: 0
+      bit_size: 4
+      enum: LATENCY
+    - name: PRFTEN
+      description: Prefetch enable
+      bit_offset: 8
+      bit_size: 1
+      enum: PRFTEN
+    - name: ARTEN
+      description: ART Accelerator Enable
+      bit_offset: 9
+      bit_size: 1
+      enum: ARTEN
+    - name: ARTRST
+      description: ART Accelerator reset
+      bit_offset: 11
+      bit_size: 1
+      enum: ARTRST
 fieldset/CR:
   description: Control register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Programming
-    enum: PG
-    name: PG
-  - bit_offset: 1
-    bit_size: 1
-    description: Sector Erase
-    enum: SER
-    name: SER
-  - bit_offset: 2
-    bit_size: 1
-    description: Mass Erase of sectors 0 to 11
-    enum: MER
-    name: MER
-  - bit_offset: 3
-    bit_size: 4
-    description: Sector number
-    name: SNB
-  - bit_offset: 8
-    bit_size: 2
-    description: Program size
-    enum: PSIZE
-    name: PSIZE
-  - bit_offset: 16
-    bit_size: 1
-    description: Start
-    enum: STRT
-    name: STRT
-  - bit_offset: 24
-    bit_size: 1
-    description: End of operation interrupt enable
-    enum: EOPIE
-    name: EOPIE
-  - bit_offset: 25
-    bit_size: 1
-    description: Error interrupt enable
-    enum: ERRIE
-    name: ERRIE
-  - bit_offset: 26
-    bit_size: 1
-    description: PCROP error interrupt enable
-    name: RDERRIE
-  - bit_offset: 31
-    bit_size: 1
-    description: Lock
-    enum: LOCK
-    name: LOCK
+    - name: PG
+      description: Programming
+      bit_offset: 0
+      bit_size: 1
+      enum: PG
+    - name: SER
+      description: Sector Erase
+      bit_offset: 1
+      bit_size: 1
+      enum: SER
+    - name: MER
+      description: Mass Erase of sectors 0 to 11
+      bit_offset: 2
+      bit_size: 1
+      enum: MER
+    - name: SNB
+      description: Sector number
+      bit_offset: 3
+      bit_size: 4
+    - name: PSIZE
+      description: Program size
+      bit_offset: 8
+      bit_size: 2
+      enum: PSIZE
+    - name: STRT
+      description: Start
+      bit_offset: 16
+      bit_size: 1
+      enum: STRT
+    - name: EOPIE
+      description: End of operation interrupt enable
+      bit_offset: 24
+      bit_size: 1
+      enum: EOPIE
+    - name: ERRIE
+      description: Error interrupt enable
+      bit_offset: 25
+      bit_size: 1
+      enum: ERRIE
+    - name: RDERRIE
+      description: PCROP error interrupt enable
+      bit_offset: 26
+      bit_size: 1
+    - name: LOCK
+      description: Lock
+      bit_offset: 31
+      bit_size: 1
+      enum: LOCK
 fieldset/KEYR:
   description: Flash key register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: FPEC key
-    name: KEY
+    - name: KEY
+      description: FPEC key
+      bit_offset: 0
+      bit_size: 32
 fieldset/OPTCR:
   description: Flash option control register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Option lock
-    name: OPTLOCK
-  - bit_offset: 1
-    bit_size: 1
-    description: Option start
-    name: OPTSTRT
-  - bit_offset: 2
-    bit_size: 2
-    description: BOR reset Level
-    name: BOR_LEV
-  - bit_offset: 4
-    bit_size: 1
-    description: User option bytes
-    name: WWDG_SW
-  - bit_offset: 5
-    bit_size: 1
-    description: WDG_SW User option bytes
-    name: IWDG_SW
-  - bit_offset: 6
-    bit_size: 1
-    description: nRST_STOP User option bytes
-    name: nRST_STOP
-  - bit_offset: 7
-    bit_size: 1
-    description: nRST_STDBY User option bytes
-    name: nRST_STDBY
-  - bit_offset: 8
-    bit_size: 8
-    description: Read protect
-    name: RDP
-  - bit_offset: 16
-    bit_size: 8
-    description: Not write protect
-    name: nWRP
-  - bit_offset: 28
-    bit_size: 1
-    description: Dual Boot mode (valid only when nDBANK=0)
-    name: nDBOOT
-  - bit_offset: 29
-    bit_size: 1
-    description: Not dual bank mode
-    name: nDBANK
-  - bit_offset: 30
-    bit_size: 1
-    description: Independent watchdog counter freeze in standby mode
-    name: IWDG_STDBY
-  - bit_offset: 31
-    bit_size: 1
-    description: Independent watchdog counter freeze in Stop mode
-    name: IWDG_STOP
+    - name: OPTLOCK
+      description: Option lock
+      bit_offset: 0
+      bit_size: 1
+    - name: OPTSTRT
+      description: Option start
+      bit_offset: 1
+      bit_size: 1
+    - name: BOR_LEV
+      description: BOR reset Level
+      bit_offset: 2
+      bit_size: 2
+    - name: WWDG_SW
+      description: User option bytes
+      bit_offset: 4
+      bit_size: 1
+    - name: IWDG_SW
+      description: WDG_SW User option bytes
+      bit_offset: 5
+      bit_size: 1
+    - name: nRST_STOP
+      description: nRST_STOP User option bytes
+      bit_offset: 6
+      bit_size: 1
+    - name: nRST_STDBY
+      description: nRST_STDBY User option bytes
+      bit_offset: 7
+      bit_size: 1
+    - name: RDP
+      description: Read protect
+      bit_offset: 8
+      bit_size: 8
+    - name: nWRP
+      description: Not write protect
+      bit_offset: 16
+      bit_size: 8
+    - name: nDBOOT
+      description: Dual Boot mode (valid only when nDBANK=0)
+      bit_offset: 28
+      bit_size: 1
+    - name: nDBANK
+      description: Not dual bank mode
+      bit_offset: 29
+      bit_size: 1
+    - name: IWDG_STDBY
+      description: Independent watchdog counter freeze in standby mode
+      bit_offset: 30
+      bit_size: 1
+    - name: IWDG_STOP
+      description: Independent watchdog counter freeze in Stop mode
+      bit_offset: 31
+      bit_size: 1
 fieldset/OPTCR1:
   description: Flash option control register 1
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Boot base address when Boot pin =0
-    name: BOOT_ADD0
-  - bit_offset: 16
-    bit_size: 16
-    description: Boot base address when Boot pin =1
-    name: BOOT_ADD1
+    - name: BOOT_ADD0
+      description: Boot base address when Boot pin =0
+      bit_offset: 0
+      bit_size: 16
+    - name: BOOT_ADD1
+      description: Boot base address when Boot pin =1
+      bit_offset: 16
+      bit_size: 16
 fieldset/OPTCR2:
   description: Flash option control register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: PCROP option byte
-    name: PCROPi
-  - bit_offset: 31
-    bit_size: 1
-    description: PCROP zone preserved when RDP level decreased
-    name: PCROP_RDP
+    - name: PCROPi
+      description: PCROP option byte
+      bit_offset: 0
+      bit_size: 8
+    - name: PCROP_RDP
+      description: PCROP zone preserved when RDP level decreased
+      bit_offset: 31
+      bit_size: 1
 fieldset/OPTKEYR:
   description: Flash option key register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Option byte key
-    name: OPTKEYR
+    - name: OPTKEYR
+      description: Option byte key
+      bit_offset: 0
+      bit_size: 32
 fieldset/SR:
   description: Status register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: End of operation
-    name: EOP
-  - bit_offset: 1
-    bit_size: 1
-    description: Operation error
-    name: OPERR
-  - bit_offset: 4
-    bit_size: 1
-    description: Write protection error
-    name: WRPERR
-  - bit_offset: 5
-    bit_size: 1
-    description: Programming alignment error
-    name: PGAERR
-  - bit_offset: 6
-    bit_size: 1
-    description: Programming parallelism error
-    name: PGPERR
-  - bit_offset: 7
-    bit_size: 1
-    description: Erase Sequence Error
-    name: ERSERR
-  - bit_offset: 8
-    bit_size: 1
-    description: RDERR
-    name: RDERR
-  - bit_offset: 16
-    bit_size: 1
-    description: Busy
-    name: BSY
+    - name: EOP
+      description: End of operation
+      bit_offset: 0
+      bit_size: 1
+    - name: OPERR
+      description: Operation error
+      bit_offset: 1
+      bit_size: 1
+    - name: WRPERR
+      description: Write protection error
+      bit_offset: 4
+      bit_size: 1
+    - name: PGAERR
+      description: Programming alignment error
+      bit_offset: 5
+      bit_size: 1
+    - name: PGPERR
+      description: Programming parallelism error
+      bit_offset: 6
+      bit_size: 1
+    - name: ERSERR
+      description: Erase Sequence Error
+      bit_offset: 7
+      bit_size: 1
+    - name: RDERR
+      description: RDERR
+      bit_offset: 8
+      bit_size: 1
+    - name: BSY
+      description: Busy
+      bit_offset: 16
+      bit_size: 1
+enum/ARTEN:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: ART Accelerator is disabled
+      value: 0
+    - name: Enabled
+      description: ART Accelerator is enabled
+      value: 1
+enum/ARTRST:
+  bit_size: 1
+  variants:
+    - name: NotReset
+      description: Accelerator is not reset
+      value: 0
+    - name: Reset
+      description: Accelerator is reset
+      value: 1
+enum/EOPIE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: End of operation interrupt disabled
+      value: 0
+    - name: Enabled
+      description: End of operation interrupt enabled
+      value: 1
+enum/ERRIE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Error interrupt generation disabled
+      value: 0
+    - name: Enabled
+      description: Error interrupt generation enabled
+      value: 1
+enum/LATENCY:
+  bit_size: 4
+  variants:
+    - name: WS0
+      description: 0 wait states
+      value: 0
+    - name: WS1
+      description: 1 wait states
+      value: 1
+    - name: WS2
+      description: 2 wait states
+      value: 2
+    - name: WS3
+      description: 3 wait states
+      value: 3
+    - name: WS4
+      description: 4 wait states
+      value: 4
+    - name: WS5
+      description: 5 wait states
+      value: 5
+    - name: WS6
+      description: 6 wait states
+      value: 6
+    - name: WS7
+      description: 7 wait states
+      value: 7
+    - name: WS8
+      description: 8 wait states
+      value: 8
+    - name: WS9
+      description: 9 wait states
+      value: 9
+    - name: WS10
+      description: 10 wait states
+      value: 10
+    - name: WS11
+      description: 11 wait states
+      value: 11
+    - name: WS12
+      description: 12 wait states
+      value: 12
+    - name: WS13
+      description: 13 wait states
+      value: 13
+    - name: WS14
+      description: 14 wait states
+      value: 14
+    - name: WS15
+      description: 15 wait states
+      value: 15
+enum/LOCK:
+  bit_size: 1
+  variants:
+    - name: Unlocked
+      description: FLASH_CR register is unlocked
+      value: 0
+    - name: Locked
+      description: FLASH_CR register is locked
+      value: 1
+enum/MER:
+  bit_size: 1
+  variants:
+    - name: MassErase
+      description: Erase activated for all user sectors
+      value: 1
+enum/PG:
+  bit_size: 1
+  variants:
+    - name: Program
+      description: Flash programming activated
+      value: 1
+enum/PRFTEN:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Prefetch is disabled
+      value: 0
+    - name: Enabled
+      description: Prefetch is enabled
+      value: 1
+enum/PSIZE:
+  bit_size: 2
+  variants:
+    - name: PSIZE8
+      description: Program x8
+      value: 0
+    - name: PSIZE16
+      description: Program x16
+      value: 1
+    - name: PSIZE32
+      description: Program x32
+      value: 2
+    - name: PSIZE64
+      description: Program x64
+      value: 3
+enum/SER:
+  bit_size: 1
+  variants:
+    - name: SectorErase
+      description: Erase activated for selected sector
+      value: 1
+enum/STRT:
+  bit_size: 1
+  variants:
+    - name: Start
+      description: Trigger an erase operation
+      value: 1

data/registers/flash_l4.yaml

@@ -1,408 +1,409 @@
+---
 block/FLASH:
   description: Flash
   items:
-  - byte_offset: 0
-    description: Access control register
-    fieldset: ACR
-    name: ACR
-  - access: Write
-    byte_offset: 4
-    description: Power down key register
-    fieldset: PDKEYR
-    name: PDKEYR
-  - access: Write
-    byte_offset: 8
-    description: Flash key register
-    fieldset: KEYR
-    name: KEYR
-  - access: Write
-    byte_offset: 12
-    description: Option byte key register
-    fieldset: OPTKEYR
-    name: OPTKEYR
-  - byte_offset: 16
-    description: Status register
-    fieldset: SR
-    name: SR
-  - byte_offset: 20
-    description: Flash control register
-    fieldset: CR
-    name: CR
-  - byte_offset: 24
-    description: Flash ECC register
-    fieldset: ECCR
-    name: ECCR
-  - byte_offset: 32
-    description: Flash option register
-    fieldset: OPTR
-    name: OPTR
-  - byte_offset: 36
-    description: Flash Bank 1 PCROP Start address register
-    fieldset: PCROP1SR
-    name: PCROP1SR
-  - byte_offset: 40
-    description: Flash Bank 1 PCROP End address register
-    fieldset: PCROP1ER
-    name: PCROP1ER
-  - byte_offset: 44
-    description: Flash Bank 1 WRP area A address register
-    fieldset: WRP1AR
-    name: WRP1AR
-  - byte_offset: 48
-    description: Flash Bank 1 WRP area B address register
-    fieldset: WRP1BR
-    name: WRP1BR
-  - byte_offset: 68
-    description: Flash Bank 2 PCROP Start address register
-    fieldset: PCROP2SR
-    name: PCROP2SR
-  - byte_offset: 72
-    description: Flash Bank 2 PCROP End address register
-    fieldset: PCROP2ER
-    name: PCROP2ER
-  - byte_offset: 76
-    description: Flash Bank 2 WRP area A address register
-    fieldset: WRP2AR
-    name: WRP2AR
-  - byte_offset: 80
-    description: Flash Bank 2 WRP area B address register
-    fieldset: WRP2BR
-    name: WRP2BR
+    - name: ACR
+      description: Access control register
+      byte_offset: 0
+      fieldset: ACR
+    - name: PDKEYR
+      description: Power down key register
+      byte_offset: 4
+      access: Write
+      fieldset: PDKEYR
+    - name: KEYR
+      description: Flash key register
+      byte_offset: 8
+      access: Write
+      fieldset: KEYR
+    - name: OPTKEYR
+      description: Option byte key register
+      byte_offset: 12
+      access: Write
+      fieldset: OPTKEYR
+    - name: SR
+      description: Status register
+      byte_offset: 16
+      fieldset: SR
+    - name: CR
+      description: Flash control register
+      byte_offset: 20
+      fieldset: CR
+    - name: ECCR
+      description: Flash ECC register
+      byte_offset: 24
+      fieldset: ECCR
+    - name: OPTR
+      description: Flash option register
+      byte_offset: 32
+      fieldset: OPTR
+    - name: PCROP1SR
+      description: Flash Bank 1 PCROP Start address register
+      byte_offset: 36
+      fieldset: PCROP1SR
+    - name: PCROP1ER
+      description: Flash Bank 1 PCROP End address register
+      byte_offset: 40
+      fieldset: PCROP1ER
+    - name: WRP1AR
+      description: Flash Bank 1 WRP area A address register
+      byte_offset: 44
+      fieldset: WRP1AR
+    - name: WRP1BR
+      description: Flash Bank 1 WRP area B address register
+      byte_offset: 48
+      fieldset: WRP1BR
+    - name: PCROP2SR
+      description: Flash Bank 2 PCROP Start address register
+      byte_offset: 68
+      fieldset: PCROP2SR
+    - name: PCROP2ER
+      description: Flash Bank 2 PCROP End address register
+      byte_offset: 72
+      fieldset: PCROP2ER
+    - name: WRP2AR
+      description: Flash Bank 2 WRP area A address register
+      byte_offset: 76
+      fieldset: WRP2AR
+    - name: WRP2BR
+      description: Flash Bank 2 WRP area B address register
+      byte_offset: 80
+      fieldset: WRP2BR
 fieldset/ACR:
   description: Access control register
   fields:
-  - bit_offset: 0
-    bit_size: 3
-    description: Latency
-    name: LATENCY
-  - bit_offset: 8
-    bit_size: 1
-    description: Prefetch enable
-    name: PRFTEN
-  - bit_offset: 9
-    bit_size: 1
-    description: Instruction cache enable
-    name: ICEN
-  - bit_offset: 10
-    bit_size: 1
-    description: Data cache enable
-    name: DCEN
-  - bit_offset: 11
-    bit_size: 1
-    description: Instruction cache reset
-    name: ICRST
-  - bit_offset: 12
-    bit_size: 1
-    description: Data cache reset
-    name: DCRST
-  - bit_offset: 13
-    bit_size: 1
-    description: Flash Power-down mode during Low-power run mode
-    name: RUN_PD
-  - bit_offset: 14
-    bit_size: 1
-    description: Flash Power-down mode during Low-power sleep mode
-    name: SLEEP_PD
+    - name: LATENCY
+      description: Latency
+      bit_offset: 0
+      bit_size: 3
+    - name: PRFTEN
+      description: Prefetch enable
+      bit_offset: 8
+      bit_size: 1
+    - name: ICEN
+      description: Instruction cache enable
+      bit_offset: 9
+      bit_size: 1
+    - name: DCEN
+      description: Data cache enable
+      bit_offset: 10
+      bit_size: 1
+    - name: ICRST
+      description: Instruction cache reset
+      bit_offset: 11
+      bit_size: 1
+    - name: DCRST
+      description: Data cache reset
+      bit_offset: 12
+      bit_size: 1
+    - name: RUN_PD
+      description: Flash Power-down mode during Low-power run mode
+      bit_offset: 13
+      bit_size: 1
+    - name: SLEEP_PD
+      description: Flash Power-down mode during Low-power sleep mode
+      bit_offset: 14
+      bit_size: 1
 fieldset/CR:
   description: Flash control register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Programming
-    name: PG
-  - bit_offset: 1
-    bit_size: 1
-    description: Page erase
-    name: PER
-  - array:
-      len: 2
-      stride: 13
-    bit_offset: 2
-    bit_size: 1
-    description: Bank 1 Mass erase
-    name: MER
-  - bit_offset: 3
-    bit_size: 8
-    description: Page number
-    name: PNB
-  - bit_offset: 11
-    bit_size: 1
-    description: Bank erase
-    name: BKER
-  - bit_offset: 16
-    bit_size: 1
-    description: Start
-    name: START
-  - bit_offset: 17
-    bit_size: 1
-    description: Options modification start
-    name: OPTSTRT
-  - bit_offset: 18
-    bit_size: 1
-    description: Fast programming
-    name: FSTPG
-  - bit_offset: 24
-    bit_size: 1
-    description: End of operation interrupt enable
-    name: EOPIE
-  - bit_offset: 25
-    bit_size: 1
-    description: Error interrupt enable
-    name: ERRIE
-  - bit_offset: 26
-    bit_size: 1
-    description: PCROP read error interrupt enable
-    name: RDERRIE
-  - bit_offset: 27
-    bit_size: 1
-    description: Force the option byte loading
-    name: OBL_LAUNCH
-  - bit_offset: 30
-    bit_size: 1
-    description: Options Lock
-    name: OPTLOCK
-  - bit_offset: 31
-    bit_size: 1
-    description: FLASH_CR Lock
-    name: LOCK
+    - name: PG
+      description: Programming
+      bit_offset: 0
+      bit_size: 1
+    - name: PER
+      description: Page erase
+      bit_offset: 1
+      bit_size: 1
+    - name: MER
+      description: Bank 1 Mass erase
+      bit_offset: 2
+      bit_size: 1
+      array:
+        len: 2
+        stride: 13
+    - name: PNB
+      description: Page number
+      bit_offset: 3
+      bit_size: 8
+    - name: BKER
+      description: Bank erase
+      bit_offset: 11
+      bit_size: 1
+    - name: START
+      description: Start
+      bit_offset: 16
+      bit_size: 1
+    - name: OPTSTRT
+      description: Options modification start
+      bit_offset: 17
+      bit_size: 1
+    - name: FSTPG
+      description: Fast programming
+      bit_offset: 18
+      bit_size: 1
+    - name: EOPIE
+      description: End of operation interrupt enable
+      bit_offset: 24
+      bit_size: 1
+    - name: ERRIE
+      description: Error interrupt enable
+      bit_offset: 25
+      bit_size: 1
+    - name: RDERRIE
+      description: PCROP read error interrupt enable
+      bit_offset: 26
+      bit_size: 1
+    - name: OBL_LAUNCH
+      description: Force the option byte loading
+      bit_offset: 27
+      bit_size: 1
+    - name: OPTLOCK
+      description: Options Lock
+      bit_offset: 30
+      bit_size: 1
+    - name: LOCK
+      description: FLASH_CR Lock
+      bit_offset: 31
+      bit_size: 1
 fieldset/ECCR:
   description: Flash ECC register
   fields:
-  - bit_offset: 0
-    bit_size: 19
-    description: ECC fail address
-    name: ADDR_ECC
-  - bit_offset: 19
-    bit_size: 1
-    description: ECC fail bank
-    name: BK_ECC
-  - bit_offset: 20
-    bit_size: 1
-    description: System Flash ECC fail
-    name: SYSF_ECC
-  - bit_offset: 24
-    bit_size: 1
-    description: ECC correction interrupt enable
-    name: ECCIE
-  - bit_offset: 30
-    bit_size: 1
-    description: ECC correction
-    name: ECCC
-  - bit_offset: 31
-    bit_size: 1
-    description: ECC detection
-    name: ECCD
+    - name: ADDR_ECC
+      description: ECC fail address
+      bit_offset: 0
+      bit_size: 19
+    - name: BK_ECC
+      description: ECC fail bank
+      bit_offset: 19
+      bit_size: 1
+    - name: SYSF_ECC
+      description: System Flash ECC fail
+      bit_offset: 20
+      bit_size: 1
+    - name: ECCIE
+      description: ECC correction interrupt enable
+      bit_offset: 24
+      bit_size: 1
+    - name: ECCC
+      description: ECC correction
+      bit_offset: 30
+      bit_size: 1
+    - name: ECCD
+      description: ECC detection
+      bit_offset: 31
+      bit_size: 1
 fieldset/KEYR:
   description: Flash key register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: KEYR
-    name: KEYR
+    - name: KEYR
+      description: KEYR
+      bit_offset: 0
+      bit_size: 32
 fieldset/OPTKEYR:
   description: Option byte key register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Option byte key
-    name: OPTKEYR
+    - name: OPTKEYR
+      description: Option byte key
+      bit_offset: 0
+      bit_size: 32
 fieldset/OPTR:
   description: Flash option register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: Read protection level
-    name: RDP
-  - bit_offset: 8
-    bit_size: 3
-    description: BOR reset Level
-    name: BOR_LEV
-  - bit_offset: 12
-    bit_size: 1
-    description: nRST_STOP
-    name: nRST_STOP
-  - bit_offset: 13
-    bit_size: 1
-    description: nRST_STDBY
-    name: nRST_STDBY
-  - bit_offset: 16
-    bit_size: 1
-    description: Independent watchdog selection
-    name: IDWG_SW
-  - bit_offset: 17
-    bit_size: 1
-    description: Independent watchdog counter freeze in Stop mode
-    name: IWDG_STOP
-  - bit_offset: 18
-    bit_size: 1
-    description: Independent watchdog counter freeze in Standby mode
-    name: IWDG_STDBY
-  - bit_offset: 19
-    bit_size: 1
-    description: Window watchdog selection
-    name: WWDG_SW
-  - array:
-      len: 1
-      stride: 0
-    bit_offset: 20
-    bit_size: 1
-    description: Dual-bank boot
-    name: BFB
-  - bit_offset: 21
-    bit_size: 1
-    description: Dual-Bank on 512 KB or 256 KB Flash memory devices
-    name: DUALBANK
-  - bit_offset: 23
-    bit_size: 1
-    description: Boot configuration
-    name: nBOOT1
-  - bit_offset: 24
-    bit_size: 1
-    description: SRAM2 parity check enable
-    name: SRAM2_PE
-  - bit_offset: 25
-    bit_size: 1
-    description: SRAM2 Erase when system reset
-    name: SRAM2_RST
-  - bit_offset: 26
-    bit_size: 1
-    description: Software BOOT0
-    name: nSWBOOT0
-  - bit_offset: 27
-    bit_size: 1
-    description: nBOOT0 option bit
-    name: nBOOT0
+    - name: RDP
+      description: Read protection level
+      bit_offset: 0
+      bit_size: 8
+    - name: BOR_LEV
+      description: BOR reset Level
+      bit_offset: 8
+      bit_size: 3
+    - name: nRST_STOP
+      description: nRST_STOP
+      bit_offset: 12
+      bit_size: 1
+    - name: nRST_STDBY
+      description: nRST_STDBY
+      bit_offset: 13
+      bit_size: 1
+    - name: IDWG_SW
+      description: Independent watchdog selection
+      bit_offset: 16
+      bit_size: 1
+    - name: IWDG_STOP
+      description: Independent watchdog counter freeze in Stop mode
+      bit_offset: 17
+      bit_size: 1
+    - name: IWDG_STDBY
+      description: Independent watchdog counter freeze in Standby mode
+      bit_offset: 18
+      bit_size: 1
+    - name: WWDG_SW
+      description: Window watchdog selection
+      bit_offset: 19
+      bit_size: 1
+    - name: BFB
+      description: Dual-bank boot
+      bit_offset: 20
+      bit_size: 1
+      array:
+        len: 1
+        stride: 0
+    - name: DUALBANK
+      description: Dual-Bank on 512 KB or 256 KB Flash memory devices
+      bit_offset: 21
+      bit_size: 1
+    - name: nBOOT1
+      description: Boot configuration
+      bit_offset: 23
+      bit_size: 1
+    - name: SRAM2_PE
+      description: SRAM2 parity check enable
+      bit_offset: 24
+      bit_size: 1
+    - name: SRAM2_RST
+      description: SRAM2 Erase when system reset
+      bit_offset: 25
+      bit_size: 1
+    - name: nSWBOOT0
+      description: Software BOOT0
+      bit_offset: 26
+      bit_size: 1
+    - name: nBOOT0
+      description: nBOOT0 option bit
+      bit_offset: 27
+      bit_size: 1
 fieldset/PCROP1ER:
   description: Flash Bank 1 PCROP End address register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Bank 1 PCROP area end offset
-    name: PCROP1_END
-  - bit_offset: 31
-    bit_size: 1
-    description: PCROP area preserved when RDP level decreased
-    name: PCROP_RDP
+    - name: PCROP1_END
+      description: Bank 1 PCROP area end offset
+      bit_offset: 0
+      bit_size: 16
+    - name: PCROP_RDP
+      description: PCROP area preserved when RDP level decreased
+      bit_offset: 31
+      bit_size: 1
 fieldset/PCROP1SR:
   description: Flash Bank 1 PCROP Start address register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Bank 1 PCROP area start offset
-    name: PCROP1_STRT
+    - name: PCROP1_STRT
+      description: Bank 1 PCROP area start offset
+      bit_offset: 0
+      bit_size: 16
 fieldset/PCROP2ER:
   description: Flash Bank 2 PCROP End address register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Bank 2 PCROP area end offset
-    name: PCROP2_END
+    - name: PCROP2_END
+      description: Bank 2 PCROP area end offset
+      bit_offset: 0
+      bit_size: 16
 fieldset/PCROP2SR:
   description: Flash Bank 2 PCROP Start address register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Bank 2 PCROP area start offset
-    name: PCROP2_STRT
+    - name: PCROP2_STRT
+      description: Bank 2 PCROP area start offset
+      bit_offset: 0
+      bit_size: 16
 fieldset/PDKEYR:
   description: Power down key register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: RUN_PD in FLASH_ACR key
-    name: PDKEYR
+    - name: PDKEYR
+      description: RUN_PD in FLASH_ACR key
+      bit_offset: 0
+      bit_size: 32
 fieldset/SR:
   description: Status register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: End of operation
-    name: EOP
-  - bit_offset: 1
-    bit_size: 1
-    description: Operation error
-    name: OPERR
-  - bit_offset: 3
-    bit_size: 1
-    description: Programming error
-    name: PROGERR
-  - bit_offset: 4
-    bit_size: 1
-    description: Write protected error
-    name: WRPERR
-  - bit_offset: 5
-    bit_size: 1
-    description: Programming alignment error
-    name: PGAERR
-  - bit_offset: 6
-    bit_size: 1
-    description: Size error
-    name: SIZERR
-  - bit_offset: 7
-    bit_size: 1
-    description: Programming sequence error
-    name: PGSERR
-  - bit_offset: 8
-    bit_size: 1
-    description: Fast programming data miss error
-    name: MISERR
-  - bit_offset: 9
-    bit_size: 1
-    description: Fast programming error
-    name: FASTERR
-  - bit_offset: 14
-    bit_size: 1
-    description: PCROP read error
-    name: RDERR
-  - bit_offset: 15
-    bit_size: 1
-    description: Option validity error
-    name: OPTVERR
-  - bit_offset: 16
-    bit_size: 1
-    description: Busy
-    name: BSY
+    - name: EOP
+      description: End of operation
+      bit_offset: 0
+      bit_size: 1
+    - name: OPERR
+      description: Operation error
+      bit_offset: 1
+      bit_size: 1
+    - name: PROGERR
+      description: Programming error
+      bit_offset: 3
+      bit_size: 1
+    - name: WRPERR
+      description: Write protected error
+      bit_offset: 4
+      bit_size: 1
+    - name: PGAERR
+      description: Programming alignment error
+      bit_offset: 5
+      bit_size: 1
+    - name: SIZERR
+      description: Size error
+      bit_offset: 6
+      bit_size: 1
+    - name: PGSERR
+      description: Programming sequence error
+      bit_offset: 7
+      bit_size: 1
+    - name: MISERR
+      description: Fast programming data miss error
+      bit_offset: 8
+      bit_size: 1
+    - name: FASTERR
+      description: Fast programming error
+      bit_offset: 9
+      bit_size: 1
+    - name: RDERR
+      description: PCROP read error
+      bit_offset: 14
+      bit_size: 1
+    - name: OPTVERR
+      description: Option validity error
+      bit_offset: 15
+      bit_size: 1
+    - name: BSY
+      description: Busy
+      bit_offset: 16
+      bit_size: 1
 fieldset/WRP1AR:
   description: Flash Bank 1 WRP area A address register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: Bank 1 WRP first area tart offset
-    name: WRP1A_STRT
-  - bit_offset: 16
-    bit_size: 8
-    description: Bank 1 WRP first area A end offset
-    name: WRP1A_END
+    - name: WRP1A_STRT
+      description: Bank 1 WRP first area tart offset
+      bit_offset: 0
+      bit_size: 8
+    - name: WRP1A_END
+      description: Bank 1 WRP first area A end offset
+      bit_offset: 16
+      bit_size: 8
 fieldset/WRP1BR:
   description: Flash Bank 1 WRP area B address register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: Bank 1 WRP second area B start offset
-    name: WRP1B_STRT
-  - bit_offset: 16
-    bit_size: 8
-    description: Bank 1 WRP second area B end offset
-    name: WRP1B_END
+    - name: WRP1B_STRT
+      description: Bank 1 WRP second area B start offset
+      bit_offset: 0
+      bit_size: 8
+    - name: WRP1B_END
+      description: Bank 1 WRP second area B end offset
+      bit_offset: 16
+      bit_size: 8
 fieldset/WRP2AR:
   description: Flash Bank 2 WRP area A address register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: Bank 2 WRP first area A start offset
-    name: WRP2A_STRT
-  - bit_offset: 16
-    bit_size: 8
-    description: Bank 2 WRP first area A end offset
-    name: WRP2A_END
+    - name: WRP2A_STRT
+      description: Bank 2 WRP first area A start offset
+      bit_offset: 0
+      bit_size: 8
+    - name: WRP2A_END
+      description: Bank 2 WRP first area A end offset
+      bit_offset: 16
+      bit_size: 8
 fieldset/WRP2BR:
   description: Flash Bank 2 WRP area B address register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: Bank 2 WRP second area B start offset
-    name: WRP2B_STRT
-  - bit_offset: 16
-    bit_size: 8
-    description: Bank 2 WRP second area B end offset
-    name: WRP2B_END
+    - name: WRP2B_STRT
+      description: Bank 2 WRP second area B start offset
+      bit_offset: 0
+      bit_size: 8
+    - name: WRP2B_END
+      description: Bank 2 WRP second area B end offset
+      bit_offset: 16
+      bit_size: 8

data/registers/gpio_v1.yaml

@@ -4,39 +4,33 @@ block/GPIO:
   items:
     - name: CR
       description: Port configuration register low (GPIOn_CRL)
-      byte_offset: 0
-      reset_value: 1145324612
       array:
         len: 2
         stride: 4
+      byte_offset: 0
       fieldset: CR
     - name: IDR
       description: Port input data register (GPIOn_IDR)
       byte_offset: 8
-      reset_value: 0
       access: Read
       fieldset: IDR
     - name: ODR
       description: Port output data register (GPIOn_ODR)
       byte_offset: 12
-      reset_value: 0
       fieldset: ODR
     - name: BSRR
       description: Port bit set/reset register (GPIOn_BSRR)
       byte_offset: 16
-      reset_value: 0
       access: Write
       fieldset: BSRR
     - name: BRR
       description: Port bit reset register (GPIOn_BRR)
       byte_offset: 20
-      reset_value: 0
       access: Write
       fieldset: BRR
     - name: LCKR
       description: Port configuration lock register
       byte_offset: 24
-      reset_value: 0
       fieldset: LCKR
 fieldset/BRR:
   description: Port bit reset register (GPIOn_BRR)
@@ -208,4 +202,4 @@ enum/ODR:
       value: 1
     - name: Low
       description: Set output to logic low
-      value: 0
+      value: 0

data/registers/gpio_v2.yaml

@@ -5,52 +5,43 @@ block/GPIO:
     - name: MODER
       description: GPIO port mode register
       byte_offset: 0
-      reset_value: 2818572288
       fieldset: MODER
     - name: OTYPER
       description: GPIO port output type register
       byte_offset: 4
-      reset_value: 0
       fieldset: OTYPER
     - name: OSPEEDR
       description: GPIO port output speed register
       byte_offset: 8
-      reset_value: 0
       fieldset: OSPEEDR
     - name: PUPDR
       description: GPIO port pull-up/pull-down register
       byte_offset: 12
-      reset_value: 1677721600
       fieldset: PUPDR
     - name: IDR
       description: GPIO port input data register
       byte_offset: 16
-      reset_value: 0
       access: Read
       fieldset: IDR
     - name: ODR
       description: GPIO port output data register
       byte_offset: 20
-      reset_value: 0
       fieldset: ODR
     - name: BSRR
       description: GPIO port bit set/reset register
       byte_offset: 24
-      reset_value: 0
       access: Write
       fieldset: BSRR
     - name: LCKR
       description: GPIO port configuration lock register
       byte_offset: 28
-      reset_value: 0
       fieldset: LCKR
     - name: AFR
-      description: GPIO alternate function register (low, high)
-      byte_offset: 32
-      reset_value: 0
+      description: "GPIO alternate function register (low, high)"
       array:
         len: 2
         stride: 4
+      byte_offset: 32
       fieldset: AFR
 fieldset/AFR:
   description: GPIO alternate function register
@@ -313,4 +304,4 @@ enum/PUPDR:
       value: 1
     - name: PullDown
       description: Pull-down
-      value: 2
+      value: 2

data/registers/ipcc_v1.yaml

@@ -4,11 +4,10 @@ block/IPCC:
   items:
     - name: CPU
       description: CPU specific registers
-      byte_offset: 0
       array:
         len: 2
         stride: 16
-
+      byte_offset: 0
 block/IPCC_CPU:
   description: IPCC
   items:

data/registers/iwdg_v2.yaml

@@ -2,109 +2,109 @@
 block/IWDG:
   description: Independent watchdog
   items:
-  - access: Write
-    byte_offset: 0
-    description: Key register
-    fieldset: KR
-    name: KR
-  - byte_offset: 4
-    description: Prescaler register
-    fieldset: PR
-    name: PR
-  - byte_offset: 8
-    description: Reload register
-    fieldset: RLR
-    name: RLR
-  - access: Read
-    byte_offset: 12
-    description: Status register
-    fieldset: SR
-    name: SR
-  - byte_offset: 16
-    description: Window register
-    fieldset: WINR
-    name: WINR
-enum/KEY:
-  bit_size: 16
-  variants:
-  - description: Enable access to PR, RLR and WINR registers (0x5555)
-    name: Enable
-    value: 21845
-  - description: Reset the watchdog value (0xAAAA)
-    name: Reset
-    value: 43690
-  - description: Start the watchdog (0xCCCC)
-    name: Start
-    value: 52428
-enum/PR:
-  bit_size: 3
-  variants:
-  - description: Divider /4
-    name: DivideBy4
-    value: 0
-  - description: Divider /8
-    name: DivideBy8
-    value: 1
-  - description: Divider /16
-    name: DivideBy16
-    value: 2
-  - description: Divider /32
-    name: DivideBy32
-    value: 3
-  - description: Divider /64
-    name: DivideBy64
-    value: 4
-  - description: Divider /128
-    name: DivideBy128
-    value: 5
-  - description: Divider /256
-    name: DivideBy256
-    value: 6
-  - description: Divider /256
-    name: DivideBy256bis
-    value: 7
+    - name: KR
+      description: Key register
+      byte_offset: 0
+      access: Write
+      fieldset: KR
+    - name: PR
+      description: Prescaler register
+      byte_offset: 4
+      fieldset: PR
+    - name: RLR
+      description: Reload register
+      byte_offset: 8
+      fieldset: RLR
+    - name: SR
+      description: Status register
+      byte_offset: 12
+      access: Read
+      fieldset: SR
+    - name: WINR
+      description: Window register
+      byte_offset: 16
+      fieldset: WINR
 fieldset/KR:
   description: Key register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Key value (write only, read 0000h)
-    enum: KEY
-    name: KEY
+    - name: KEY
+      description: "Key value (write only, read 0000h)"
+      bit_offset: 0
+      bit_size: 16
+      enum: KEY
 fieldset/PR:
   description: Prescaler register
   fields:
-  - bit_offset: 0
-    bit_size: 3
-    description: Prescaler divider
-    enum: PR
-    name: PR
+    - name: PR
+      description: Prescaler divider
+      bit_offset: 0
+      bit_size: 3
+      enum: PR
 fieldset/RLR:
   description: Reload register
   fields:
-  - bit_offset: 0
-    bit_size: 12
-    description: Watchdog counter reload value
-    name: RL
+    - name: RL
+      description: Watchdog counter reload value
+      bit_offset: 0
+      bit_size: 12
 fieldset/SR:
   description: Status register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Watchdog prescaler value update
-    name: PVU
-  - bit_offset: 1
-    bit_size: 1
-    description: Watchdog counter reload value update
-    name: RVU
-  - bit_offset: 2
-    bit_size: 1
-    description: Watchdog counter window value update
-    name: WVU
+    - name: PVU
+      description: Watchdog prescaler value update
+      bit_offset: 0
+      bit_size: 1
+    - name: RVU
+      description: Watchdog counter reload value update
+      bit_offset: 1
+      bit_size: 1
+    - name: WVU
+      description: Watchdog counter window value update
+      bit_offset: 2
+      bit_size: 1
 fieldset/WINR:
   description: Window register
   fields:
-  - bit_offset: 0
-    bit_size: 12
-    description: Watchdog counter window value
-    name: WIN
+    - name: WIN
+      description: Watchdog counter window value
+      bit_offset: 0
+      bit_size: 12
+enum/KEY:
+  bit_size: 16
+  variants:
+    - name: Enable
+      description: "Enable access to PR, RLR and WINR registers (0x5555)"
+      value: 21845
+    - name: Reset
+      description: Reset the watchdog value (0xAAAA)
+      value: 43690
+    - name: Start
+      description: Start the watchdog (0xCCCC)
+      value: 52428
+enum/PR:
+  bit_size: 3
+  variants:
+    - name: DivideBy4
+      description: Divider /4
+      value: 0
+    - name: DivideBy8
+      description: Divider /8
+      value: 1
+    - name: DivideBy16
+      description: Divider /16
+      value: 2
+    - name: DivideBy32
+      description: Divider /32
+      value: 3
+    - name: DivideBy64
+      description: Divider /64
+      value: 4
+    - name: DivideBy128
+      description: Divider /128
+      value: 5
+    - name: DivideBy256
+      description: Divider /256
+      value: 6
+    - name: DivideBy256bis
+      description: Divider /256
+      value: 7

data/registers/lptim_g0.yaml

@@ -260,33 +260,33 @@ enum/PRESC:
   bit_size: 3
   variants:
     - name: DIV_BY_1
-      value: 0x0
+      value: 0
     - name: DIV_BY_2
-      value: 0x1
+      value: 1
     - name: DIV_BY_4
-      value: 0x2
+      value: 2
     - name: DIV_BY_8
-      value: 0x3
+      value: 3
     - name: DIV_BY_16
-      value: 0x4
+      value: 4
     - name: DIV_BY_32
-      value: 0x5
+      value: 5
     - name: DIV_BY_64
-      value: 0x6
+      value: 6
     - name: DIV_BY_128
-      value: 0x7
+      value: 7
 enum/TRIGEN:
   bit_size: 2
   variants:
     - name: SOFTWARE
       description: software trigger (counting start is initiated by software)
-      value: 0x0
+      value: 0
     - name: RISING
       description: rising edge is the active edge
-      value: 0x1
+      value: 1
     - name: FALLING
       description: rising edge is the active edge
-      value: 0x2
+      value: 2
     - name: BOTH
       description: both edges are active edges
-      value: 0x3
+      value: 3

data/registers/lptim_v1.yaml

@@ -2,222 +2,222 @@
 block/LPTIM:
   description: Low power timer
   items:
-  - access: Read
-    byte_offset: 0
-    description: Interrupt and Status Register
-    fieldset: ISR
-    name: ISR
-  - access: Write
-    byte_offset: 4
-    description: Interrupt Clear Register
-    fieldset: ICR
-    name: ICR
-  - byte_offset: 8
-    description: Interrupt Enable Register
-    fieldset: IER
-    name: IER
-  - byte_offset: 12
-    description: Configuration Register
-    fieldset: CFGR
-    name: CFGR
-  - byte_offset: 16
-    description: Control Register
-    fieldset: CR
-    name: CR
-  - byte_offset: 20
-    description: Compare Register
-    fieldset: CMP
-    name: CMP
-  - byte_offset: 24
-    description: Autoreload Register
-    fieldset: ARR
-    name: ARR
-  - access: Read
-    byte_offset: 28
-    description: Counter Register
-    fieldset: CNT
-    name: CNT
+    - name: ISR
+      description: Interrupt and Status Register
+      byte_offset: 0
+      access: Read
+      fieldset: ISR
+    - name: ICR
+      description: Interrupt Clear Register
+      byte_offset: 4
+      access: Write
+      fieldset: ICR
+    - name: IER
+      description: Interrupt Enable Register
+      byte_offset: 8
+      fieldset: IER
+    - name: CFGR
+      description: Configuration Register
+      byte_offset: 12
+      fieldset: CFGR
+    - name: CR
+      description: Control Register
+      byte_offset: 16
+      fieldset: CR
+    - name: CMP
+      description: Compare Register
+      byte_offset: 20
+      fieldset: CMP
+    - name: ARR
+      description: Autoreload Register
+      byte_offset: 24
+      fieldset: ARR
+    - name: CNT
+      description: Counter Register
+      byte_offset: 28
+      access: Read
+      fieldset: CNT
 fieldset/ARR:
   description: Autoreload Register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Auto reload value
-    name: ARR
+    - name: ARR
+      description: Auto reload value
+      bit_offset: 0
+      bit_size: 16
 fieldset/CFGR:
   description: Configuration Register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Clock selector
-    name: CKSEL
-  - bit_offset: 1
-    bit_size: 2
-    description: Clock Polarity
-    name: CKPOL
-  - bit_offset: 3
-    bit_size: 2
-    description: Configurable digital filter for external clock
-    name: CKFLT
-  - bit_offset: 6
-    bit_size: 2
-    description: Configurable digital filter for trigger
-    name: TRGFLT
-  - bit_offset: 9
-    bit_size: 3
-    description: Clock prescaler
-    name: PRESC
-  - bit_offset: 13
-    bit_size: 3
-    description: Trigger selector
-    name: TRIGSEL
-  - bit_offset: 17
-    bit_size: 2
-    description: Trigger enable and polarity
-    name: TRIGEN
-  - bit_offset: 19
-    bit_size: 1
-    description: Timeout enable
-    name: TIMOUT
-  - bit_offset: 20
-    bit_size: 1
-    description: Waveform shape
-    name: WAVE
-  - bit_offset: 21
-    bit_size: 1
-    description: Waveform shape polarity
-    name: WAVPOL
-  - bit_offset: 22
-    bit_size: 1
-    description: Registers update mode
-    name: PRELOAD
-  - bit_offset: 23
-    bit_size: 1
-    description: counter mode enabled
-    name: COUNTMODE
-  - bit_offset: 24
-    bit_size: 1
-    description: Encoder mode enable
-    name: ENC
+    - name: CKSEL
+      description: Clock selector
+      bit_offset: 0
+      bit_size: 1
+    - name: CKPOL
+      description: Clock Polarity
+      bit_offset: 1
+      bit_size: 2
+    - name: CKFLT
+      description: Configurable digital filter for external clock
+      bit_offset: 3
+      bit_size: 2
+    - name: TRGFLT
+      description: Configurable digital filter for trigger
+      bit_offset: 6
+      bit_size: 2
+    - name: PRESC
+      description: Clock prescaler
+      bit_offset: 9
+      bit_size: 3
+    - name: TRIGSEL
+      description: Trigger selector
+      bit_offset: 13
+      bit_size: 3
+    - name: TRIGEN
+      description: Trigger enable and polarity
+      bit_offset: 17
+      bit_size: 2
+    - name: TIMOUT
+      description: Timeout enable
+      bit_offset: 19
+      bit_size: 1
+    - name: WAVE
+      description: Waveform shape
+      bit_offset: 20
+      bit_size: 1
+    - name: WAVPOL
+      description: Waveform shape polarity
+      bit_offset: 21
+      bit_size: 1
+    - name: PRELOAD
+      description: Registers update mode
+      bit_offset: 22
+      bit_size: 1
+    - name: COUNTMODE
+      description: counter mode enabled
+      bit_offset: 23
+      bit_size: 1
+    - name: ENC
+      description: Encoder mode enable
+      bit_offset: 24
+      bit_size: 1
 fieldset/CMP:
   description: Compare Register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Compare value
-    name: CMP
+    - name: CMP
+      description: Compare value
+      bit_offset: 0
+      bit_size: 16
 fieldset/CNT:
   description: Counter Register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Counter value
-    name: CNT
+    - name: CNT
+      description: Counter value
+      bit_offset: 0
+      bit_size: 16
 fieldset/CR:
   description: Control Register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: LPTIM Enable
-    name: ENABLE
-  - bit_offset: 1
-    bit_size: 1
-    description: LPTIM start in single mode
-    name: SNGSTRT
-  - bit_offset: 2
-    bit_size: 1
-    description: Timer start in continuous mode
-    name: CNTSTRT
+    - name: ENABLE
+      description: LPTIM Enable
+      bit_offset: 0
+      bit_size: 1
+    - name: SNGSTRT
+      description: LPTIM start in single mode
+      bit_offset: 1
+      bit_size: 1
+    - name: CNTSTRT
+      description: Timer start in continuous mode
+      bit_offset: 2
+      bit_size: 1
 fieldset/ICR:
   description: Interrupt Clear Register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: compare match Clear Flag
-    name: CMPMCF
-  - bit_offset: 1
-    bit_size: 1
-    description: Autoreload match Clear Flag
-    name: ARRMCF
-  - bit_offset: 2
-    bit_size: 1
-    description: External trigger valid edge Clear Flag
-    name: EXTTRIGCF
-  - bit_offset: 3
-    bit_size: 1
-    description: Compare register update OK Clear Flag
-    name: CMPOKCF
-  - bit_offset: 4
-    bit_size: 1
-    description: Autoreload register update OK Clear Flag
-    name: ARROKCF
-  - bit_offset: 5
-    bit_size: 1
-    description: Direction change to UP Clear Flag
-    name: UPCF
-  - bit_offset: 6
-    bit_size: 1
-    description: Direction change to down Clear Flag
-    name: DOWNCF
+    - name: CMPMCF
+      description: compare match Clear Flag
+      bit_offset: 0
+      bit_size: 1
+    - name: ARRMCF
+      description: Autoreload match Clear Flag
+      bit_offset: 1
+      bit_size: 1
+    - name: EXTTRIGCF
+      description: External trigger valid edge Clear Flag
+      bit_offset: 2
+      bit_size: 1
+    - name: CMPOKCF
+      description: Compare register update OK Clear Flag
+      bit_offset: 3
+      bit_size: 1
+    - name: ARROKCF
+      description: Autoreload register update OK Clear Flag
+      bit_offset: 4
+      bit_size: 1
+    - name: UPCF
+      description: Direction change to UP Clear Flag
+      bit_offset: 5
+      bit_size: 1
+    - name: DOWNCF
+      description: Direction change to down Clear Flag
+      bit_offset: 6
+      bit_size: 1
 fieldset/IER:
   description: Interrupt Enable Register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Compare match Interrupt Enable
-    name: CMPMIE
-  - bit_offset: 1
-    bit_size: 1
-    description: Autoreload match Interrupt Enable
-    name: ARRMIE
-  - bit_offset: 2
-    bit_size: 1
-    description: External trigger valid edge Interrupt Enable
-    name: EXTTRIGIE
-  - bit_offset: 3
-    bit_size: 1
-    description: Compare register update OK Interrupt Enable
-    name: CMPOKIE
-  - bit_offset: 4
-    bit_size: 1
-    description: Autoreload register update OK Interrupt Enable
-    name: ARROKIE
-  - bit_offset: 5
-    bit_size: 1
-    description: Direction change to UP Interrupt Enable
-    name: UPIE
-  - bit_offset: 6
-    bit_size: 1
-    description: Direction change to down Interrupt Enable
-    name: DOWNIE
+    - name: CMPMIE
+      description: Compare match Interrupt Enable
+      bit_offset: 0
+      bit_size: 1
+    - name: ARRMIE
+      description: Autoreload match Interrupt Enable
+      bit_offset: 1
+      bit_size: 1
+    - name: EXTTRIGIE
+      description: External trigger valid edge Interrupt Enable
+      bit_offset: 2
+      bit_size: 1
+    - name: CMPOKIE
+      description: Compare register update OK Interrupt Enable
+      bit_offset: 3
+      bit_size: 1
+    - name: ARROKIE
+      description: Autoreload register update OK Interrupt Enable
+      bit_offset: 4
+      bit_size: 1
+    - name: UPIE
+      description: Direction change to UP Interrupt Enable
+      bit_offset: 5
+      bit_size: 1
+    - name: DOWNIE
+      description: Direction change to down Interrupt Enable
+      bit_offset: 6
+      bit_size: 1
 fieldset/ISR:
   description: Interrupt and Status Register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Compare match
-    name: CMPM
-  - bit_offset: 1
-    bit_size: 1
-    description: Autoreload match
-    name: ARRM
-  - bit_offset: 2
-    bit_size: 1
-    description: External trigger edge event
-    name: EXTTRIG
-  - bit_offset: 3
-    bit_size: 1
-    description: Compare register update OK
-    name: CMPOK
-  - bit_offset: 4
-    bit_size: 1
-    description: Autoreload register update OK
-    name: ARROK
-  - bit_offset: 5
-    bit_size: 1
-    description: Counter direction change down to up
-    name: UP
-  - bit_offset: 6
-    bit_size: 1
-    description: Counter direction change up to down
-    name: DOWN
+    - name: CMPM
+      description: Compare match
+      bit_offset: 0
+      bit_size: 1
+    - name: ARRM
+      description: Autoreload match
+      bit_offset: 1
+      bit_size: 1
+    - name: EXTTRIG
+      description: External trigger edge event
+      bit_offset: 2
+      bit_size: 1
+    - name: CMPOK
+      description: Compare register update OK
+      bit_offset: 3
+      bit_size: 1
+    - name: ARROK
+      description: Autoreload register update OK
+      bit_offset: 4
+      bit_size: 1
+    - name: UP
+      description: Counter direction change down to up
+      bit_offset: 5
+      bit_size: 1
+    - name: DOWN
+      description: Counter direction change up to down
+      bit_offset: 6
+      bit_size: 1

data/registers/pwr_f7.yaml

@@ -2,181 +2,181 @@
 block/PWR:
   description: Power control
   items:
-  - byte_offset: 0
-    description: power control register
-    fieldset: CR1
-    name: CR1
-  - byte_offset: 4
-    description: power control/status register
-    fieldset: CSR1
-    name: CSR1
-  - byte_offset: 8
-    description: power control register
-    fieldset: CR2
-    name: CR2
-  - byte_offset: 12
-    description: power control/status register
-    fieldset: CSR2
-    name: CSR2
-enum/PDDS:
-  bit_size: 1
-  variants:
-  - description: Enter Stop mode when the CPU enters deepsleep
-    name: STOP_MODE
-    value: 0
-  - description: Enter Standby mode when the CPU enters deepsleep
-    name: STANDBY_MODE
-    value: 1
-enum/VOS:
-  bit_size: 2
-  variants:
-  - description: Scale 3 mode
-    name: SCALE3
-    value: 1
-  - description: Scale 2 mode
-    name: SCALE2
-    value: 2
-  - description: Scale 1 mode (reset value)
-    name: SCALE1
-    value: 3
+    - name: CR1
+      description: power control register
+      byte_offset: 0
+      fieldset: CR1
+    - name: CSR1
+      description: power control/status register
+      byte_offset: 4
+      fieldset: CSR1
+    - name: CR2
+      description: power control register
+      byte_offset: 8
+      fieldset: CR2
+    - name: CSR2
+      description: power control/status register
+      byte_offset: 12
+      fieldset: CSR2
 fieldset/CR1:
   description: power control register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Low-power deep sleep
-    name: LPDS
-  - bit_offset: 1
-    bit_size: 1
-    description: Power down deepsleep
-    enum: PDDS
-    name: PDDS
-  - bit_offset: 3
-    bit_size: 1
-    description: Clear standby flag
-    name: CSBF
-  - bit_offset: 4
-    bit_size: 1
-    description: Power voltage detector enable
-    name: PVDE
-  - bit_offset: 5
-    bit_size: 3
-    description: PVD level selection
-    name: PLS
-  - bit_offset: 8
-    bit_size: 1
-    description: Disable backup domain write protection
-    name: DBP
-  - bit_offset: 9
-    bit_size: 1
-    description: Flash power down in Stop mode
-    name: FPDS
-  - bit_offset: 10
-    bit_size: 1
-    description: Low-power regulator in deepsleep under-drive mode
-    name: LPUDS
-  - bit_offset: 11
-    bit_size: 1
-    description: Main regulator in deepsleep under-drive mode
-    name: MRUDS
-  - array:
-      len: 1
-      stride: 0
-    bit_offset: 13
-    bit_size: 1
-    description: ADCDC1
-    name: ADCDC
-  - bit_offset: 14
-    bit_size: 2
-    description: Regulator voltage scaling output selection
-    enum: VOS
-    name: VOS
-  - bit_offset: 16
-    bit_size: 1
-    description: Over-drive enable
-    name: ODEN
-  - bit_offset: 17
-    bit_size: 1
-    description: Over-drive switching enabled
-    name: ODSWEN
-  - bit_offset: 18
-    bit_size: 2
-    description: Under-drive enable in stop mode
-    name: UDEN
+    - name: LPDS
+      description: Low-power deep sleep
+      bit_offset: 0
+      bit_size: 1
+    - name: PDDS
+      description: Power down deepsleep
+      bit_offset: 1
+      bit_size: 1
+      enum: PDDS
+    - name: CSBF
+      description: Clear standby flag
+      bit_offset: 3
+      bit_size: 1
+    - name: PVDE
+      description: Power voltage detector enable
+      bit_offset: 4
+      bit_size: 1
+    - name: PLS
+      description: PVD level selection
+      bit_offset: 5
+      bit_size: 3
+    - name: DBP
+      description: Disable backup domain write protection
+      bit_offset: 8
+      bit_size: 1
+    - name: FPDS
+      description: Flash power down in Stop mode
+      bit_offset: 9
+      bit_size: 1
+    - name: LPUDS
+      description: Low-power regulator in deepsleep under-drive mode
+      bit_offset: 10
+      bit_size: 1
+    - name: MRUDS
+      description: Main regulator in deepsleep under-drive mode
+      bit_offset: 11
+      bit_size: 1
+    - name: ADCDC
+      description: ADCDC1
+      bit_offset: 13
+      bit_size: 1
+      array:
+        len: 1
+        stride: 0
+    - name: VOS
+      description: Regulator voltage scaling output selection
+      bit_offset: 14
+      bit_size: 2
+      enum: VOS
+    - name: ODEN
+      description: Over-drive enable
+      bit_offset: 16
+      bit_size: 1
+    - name: ODSWEN
+      description: Over-drive switching enabled
+      bit_offset: 17
+      bit_size: 1
+    - name: UDEN
+      description: Under-drive enable in stop mode
+      bit_offset: 18
+      bit_size: 2
 fieldset/CR2:
   description: power control register
   fields:
-  - array:
-      len: 6
-      stride: 1
-    bit_offset: 0
-    bit_size: 1
-    description: Clear Wakeup Pin flag for PA0
-    name: CWUPF
-  - array:
-      len: 6
-      stride: 1
-    bit_offset: 8
-    bit_size: 1
-    description: Wakeup pin polarity bit for PA0
-    name: WUPP
+    - name: CWUPF
+      description: Clear Wakeup Pin flag for PA0
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 6
+        stride: 1
+    - name: WUPP
+      description: Wakeup pin polarity bit for PA0
+      bit_offset: 8
+      bit_size: 1
+      array:
+        len: 6
+        stride: 1
 fieldset/CSR1:
   description: power control/status register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Wakeup internal flag
-    name: WUIF
-  - bit_offset: 1
-    bit_size: 1
-    description: Standby flag
-    name: SBF
-  - bit_offset: 2
-    bit_size: 1
-    description: PVD output
-    name: PVDO
-  - bit_offset: 3
-    bit_size: 1
-    description: Backup regulator ready
-    name: BRR
-  - bit_offset: 8
-    bit_size: 1
-    description: Enable internal wakeup
-    name: EIWUP
-  - bit_offset: 9
-    bit_size: 1
-    description: Backup regulator enable
-    name: BRE
-  - bit_offset: 14
-    bit_size: 1
-    description: Regulator voltage scaling output selection ready bit
-    name: VOSRDY
-  - bit_offset: 16
-    bit_size: 1
-    description: Over-drive mode ready
-    name: ODRDY
-  - bit_offset: 17
-    bit_size: 1
-    description: Over-drive mode switching ready
-    name: ODSWRDY
-  - bit_offset: 18
-    bit_size: 2
-    description: Under-drive ready flag
-    name: UDRDY
+    - name: WUIF
+      description: Wakeup internal flag
+      bit_offset: 0
+      bit_size: 1
+    - name: SBF
+      description: Standby flag
+      bit_offset: 1
+      bit_size: 1
+    - name: PVDO
+      description: PVD output
+      bit_offset: 2
+      bit_size: 1
+    - name: BRR
+      description: Backup regulator ready
+      bit_offset: 3
+      bit_size: 1
+    - name: EIWUP
+      description: Enable internal wakeup
+      bit_offset: 8
+      bit_size: 1
+    - name: BRE
+      description: Backup regulator enable
+      bit_offset: 9
+      bit_size: 1
+    - name: VOSRDY
+      description: Regulator voltage scaling output selection ready bit
+      bit_offset: 14
+      bit_size: 1
+    - name: ODRDY
+      description: Over-drive mode ready
+      bit_offset: 16
+      bit_size: 1
+    - name: ODSWRDY
+      description: Over-drive mode switching ready
+      bit_offset: 17
+      bit_size: 1
+    - name: UDRDY
+      description: Under-drive ready flag
+      bit_offset: 18
+      bit_size: 2
 fieldset/CSR2:
   description: power control/status register
   fields:
-  - array:
-      len: 6
-      stride: 1
-    bit_offset: 0
-    bit_size: 1
-    description: Wakeup Pin flag for PA0
-    name: WUPF
-  - array:
-      len: 6
-      stride: 1
-    bit_offset: 8
-    bit_size: 1
-    description: Enable Wakeup pin for PA0
-    name: EWUP
+    - name: WUPF
+      description: Wakeup Pin flag for PA0
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 6
+        stride: 1
+    - name: EWUP
+      description: Enable Wakeup pin for PA0
+      bit_offset: 8
+      bit_size: 1
+      array:
+        len: 6
+        stride: 1
+enum/PDDS:
+  bit_size: 1
+  variants:
+    - name: STOP_MODE
+      description: Enter Stop mode when the CPU enters deepsleep
+      value: 0
+    - name: STANDBY_MODE
+      description: Enter Standby mode when the CPU enters deepsleep
+      value: 1
+enum/VOS:
+  bit_size: 2
+  variants:
+    - name: SCALE3
+      description: Scale 3 mode
+      value: 1
+    - name: SCALE2
+      description: Scale 2 mode
+      value: 2
+    - name: SCALE1
+      description: Scale 1 mode (reset value)
+      value: 3

data/registers/quadspi_v1.yaml

@@ -2,295 +2,295 @@
 block/QUADSPI:
   description: QuadSPI interface
   items:
-  - byte_offset: 0
-    description: control register
-    fieldset: CR
-    name: CR
-  - byte_offset: 4
-    description: device configuration register
-    fieldset: DCR
-    name: DCR
-  - access: Read
-    byte_offset: 8
-    description: status register
-    fieldset: SR
-    name: SR
-  - byte_offset: 12
-    description: flag clear register
-    fieldset: FCR
-    name: FCR
-  - byte_offset: 16
-    description: data length register
-    fieldset: DLR
-    name: DLR
-  - byte_offset: 20
-    description: communication configuration register
-    fieldset: CCR
-    name: CCR
-  - byte_offset: 24
-    description: address register
-    fieldset: AR
-    name: AR
-  - byte_offset: 28
-    description: ABR
-    fieldset: ABR
-    name: ABR
-  - byte_offset: 32
-    description: data register
-    fieldset: DR
-    name: DR
-  - byte_offset: 36
-    description: polling status mask register
-    fieldset: PSMKR
-    name: PSMKR
-  - byte_offset: 40
-    description: polling status match register
-    fieldset: PSMAR
-    name: PSMAR
-  - byte_offset: 44
-    description: polling interval register
-    fieldset: PIR
-    name: PIR
-  - byte_offset: 48
-    description: low-power timeout register
-    fieldset: LPTR
-    name: LPTR
+    - name: CR
+      description: control register
+      byte_offset: 0
+      fieldset: CR
+    - name: DCR
+      description: device configuration register
+      byte_offset: 4
+      fieldset: DCR
+    - name: SR
+      description: status register
+      byte_offset: 8
+      access: Read
+      fieldset: SR
+    - name: FCR
+      description: flag clear register
+      byte_offset: 12
+      fieldset: FCR
+    - name: DLR
+      description: data length register
+      byte_offset: 16
+      fieldset: DLR
+    - name: CCR
+      description: communication configuration register
+      byte_offset: 20
+      fieldset: CCR
+    - name: AR
+      description: address register
+      byte_offset: 24
+      fieldset: AR
+    - name: ABR
+      description: ABR
+      byte_offset: 28
+      fieldset: ABR
+    - name: DR
+      description: data register
+      byte_offset: 32
+      fieldset: DR
+    - name: PSMKR
+      description: polling status mask register
+      byte_offset: 36
+      fieldset: PSMKR
+    - name: PSMAR
+      description: polling status match register
+      byte_offset: 40
+      fieldset: PSMAR
+    - name: PIR
+      description: polling interval register
+      byte_offset: 44
+      fieldset: PIR
+    - name: LPTR
+      description: low-power timeout register
+      byte_offset: 48
+      fieldset: LPTR
 fieldset/ABR:
   description: ABR
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: ALTERNATE
-    name: ALTERNATE
+    - name: ALTERNATE
+      description: ALTERNATE
+      bit_offset: 0
+      bit_size: 32
 fieldset/AR:
   description: address register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Address
-    name: ADDRESS
+    - name: ADDRESS
+      description: Address
+      bit_offset: 0
+      bit_size: 32
 fieldset/CCR:
   description: communication configuration register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: Instruction
-    name: INSTRUCTION
-  - bit_offset: 8
-    bit_size: 2
-    description: Instruction mode
-    name: IMODE
-  - bit_offset: 10
-    bit_size: 2
-    description: Address mode
-    name: ADMODE
-  - bit_offset: 12
-    bit_size: 2
-    description: Address size
-    name: ADSIZE
-  - bit_offset: 14
-    bit_size: 2
-    description: Alternate bytes mode
-    name: ABMODE
-  - bit_offset: 16
-    bit_size: 2
-    description: Alternate bytes size
-    name: ABSIZE
-  - bit_offset: 18
-    bit_size: 5
-    description: Number of dummy cycles
-    name: DCYC
-  - bit_offset: 24
-    bit_size: 2
-    description: Data mode
-    name: DMODE
-  - bit_offset: 26
-    bit_size: 2
-    description: Functional mode
-    name: FMODE
-  - bit_offset: 28
-    bit_size: 1
-    description: Send instruction only once mode
-    name: SIOO
-  - bit_offset: 30
-    bit_size: 1
-    description: DDR hold half cycle
-    name: DHHC
-  - bit_offset: 31
-    bit_size: 1
-    description: Double data rate mode
-    name: DDRM
+    - name: INSTRUCTION
+      description: Instruction
+      bit_offset: 0
+      bit_size: 8
+    - name: IMODE
+      description: Instruction mode
+      bit_offset: 8
+      bit_size: 2
+    - name: ADMODE
+      description: Address mode
+      bit_offset: 10
+      bit_size: 2
+    - name: ADSIZE
+      description: Address size
+      bit_offset: 12
+      bit_size: 2
+    - name: ABMODE
+      description: Alternate bytes mode
+      bit_offset: 14
+      bit_size: 2
+    - name: ABSIZE
+      description: Alternate bytes size
+      bit_offset: 16
+      bit_size: 2
+    - name: DCYC
+      description: Number of dummy cycles
+      bit_offset: 18
+      bit_size: 5
+    - name: DMODE
+      description: Data mode
+      bit_offset: 24
+      bit_size: 2
+    - name: FMODE
+      description: Functional mode
+      bit_offset: 26
+      bit_size: 2
+    - name: SIOO
+      description: Send instruction only once mode
+      bit_offset: 28
+      bit_size: 1
+    - name: DHHC
+      description: DDR hold half cycle
+      bit_offset: 30
+      bit_size: 1
+    - name: DDRM
+      description: Double data rate mode
+      bit_offset: 31
+      bit_size: 1
 fieldset/CR:
   description: control register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Enable
-    name: EN
-  - bit_offset: 1
-    bit_size: 1
-    description: Abort request
-    name: ABORT
-  - bit_offset: 2
-    bit_size: 1
-    description: DMA enable
-    name: DMAEN
-  - bit_offset: 3
-    bit_size: 1
-    description: Timeout counter enable
-    name: TCEN
-  - bit_offset: 4
-    bit_size: 1
-    description: Sample shift
-    name: SSHIFT
-  - bit_offset: 6
-    bit_size: 1
-    description: Dual-flash mode
-    name: DFM
-  - bit_offset: 7
-    bit_size: 1
-    description: FLASH memory selection
-    name: FSEL
-  - bit_offset: 8
-    bit_size: 5
-    description: IFO threshold level
-    name: FTHRES
-  - bit_offset: 16
-    bit_size: 1
-    description: Transfer error interrupt enable
-    name: TEIE
-  - bit_offset: 17
-    bit_size: 1
-    description: Transfer complete interrupt enable
-    name: TCIE
-  - bit_offset: 18
-    bit_size: 1
-    description: FIFO threshold interrupt enable
-    name: FTIE
-  - bit_offset: 19
-    bit_size: 1
-    description: Status match interrupt enable
-    name: SMIE
-  - bit_offset: 20
-    bit_size: 1
-    description: TimeOut interrupt enable
-    name: TOIE
-  - bit_offset: 22
-    bit_size: 1
-    description: Automatic poll mode stop
-    name: APMS
-  - bit_offset: 23
-    bit_size: 1
-    description: Polling match mode
-    name: PMM
-  - bit_offset: 24
-    bit_size: 8
-    description: Clock prescaler
-    name: PRESCALER
+    - name: EN
+      description: Enable
+      bit_offset: 0
+      bit_size: 1
+    - name: ABORT
+      description: Abort request
+      bit_offset: 1
+      bit_size: 1
+    - name: DMAEN
+      description: DMA enable
+      bit_offset: 2
+      bit_size: 1
+    - name: TCEN
+      description: Timeout counter enable
+      bit_offset: 3
+      bit_size: 1
+    - name: SSHIFT
+      description: Sample shift
+      bit_offset: 4
+      bit_size: 1
+    - name: DFM
+      description: Dual-flash mode
+      bit_offset: 6
+      bit_size: 1
+    - name: FSEL
+      description: FLASH memory selection
+      bit_offset: 7
+      bit_size: 1
+    - name: FTHRES
+      description: IFO threshold level
+      bit_offset: 8
+      bit_size: 5
+    - name: TEIE
+      description: Transfer error interrupt enable
+      bit_offset: 16
+      bit_size: 1
+    - name: TCIE
+      description: Transfer complete interrupt enable
+      bit_offset: 17
+      bit_size: 1
+    - name: FTIE
+      description: FIFO threshold interrupt enable
+      bit_offset: 18
+      bit_size: 1
+    - name: SMIE
+      description: Status match interrupt enable
+      bit_offset: 19
+      bit_size: 1
+    - name: TOIE
+      description: TimeOut interrupt enable
+      bit_offset: 20
+      bit_size: 1
+    - name: APMS
+      description: Automatic poll mode stop
+      bit_offset: 22
+      bit_size: 1
+    - name: PMM
+      description: Polling match mode
+      bit_offset: 23
+      bit_size: 1
+    - name: PRESCALER
+      description: Clock prescaler
+      bit_offset: 24
+      bit_size: 8
 fieldset/DCR:
   description: device configuration register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Mode 0 / mode 3
-    name: CKMODE
-  - bit_offset: 8
-    bit_size: 3
-    description: Chip select high time
-    name: CSHT
-  - bit_offset: 16
-    bit_size: 5
-    description: FLASH memory size
-    name: FSIZE
+    - name: CKMODE
+      description: Mode 0 / mode 3
+      bit_offset: 0
+      bit_size: 1
+    - name: CSHT
+      description: Chip select high time
+      bit_offset: 8
+      bit_size: 3
+    - name: FSIZE
+      description: FLASH memory size
+      bit_offset: 16
+      bit_size: 5
 fieldset/DLR:
   description: data length register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Data length
-    name: DL
+    - name: DL
+      description: Data length
+      bit_offset: 0
+      bit_size: 32
 fieldset/DR:
   description: data register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Data
-    name: DATA
+    - name: DATA
+      description: Data
+      bit_offset: 0
+      bit_size: 32
 fieldset/FCR:
   description: flag clear register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Clear transfer error flag
-    name: CTEF
-  - bit_offset: 1
-    bit_size: 1
-    description: Clear transfer complete flag
-    name: CTCF
-  - bit_offset: 3
-    bit_size: 1
-    description: Clear status match flag
-    name: CSMF
-  - bit_offset: 4
-    bit_size: 1
-    description: Clear timeout flag
-    name: CTOF
+    - name: CTEF
+      description: Clear transfer error flag
+      bit_offset: 0
+      bit_size: 1
+    - name: CTCF
+      description: Clear transfer complete flag
+      bit_offset: 1
+      bit_size: 1
+    - name: CSMF
+      description: Clear status match flag
+      bit_offset: 3
+      bit_size: 1
+    - name: CTOF
+      description: Clear timeout flag
+      bit_offset: 4
+      bit_size: 1
 fieldset/LPTR:
   description: low-power timeout register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Timeout period
-    name: TIMEOUT
+    - name: TIMEOUT
+      description: Timeout period
+      bit_offset: 0
+      bit_size: 16
 fieldset/PIR:
   description: polling interval register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Polling interval
-    name: INTERVAL
+    - name: INTERVAL
+      description: Polling interval
+      bit_offset: 0
+      bit_size: 16
 fieldset/PSMAR:
   description: polling status match register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Status match
-    name: MATCH
+    - name: MATCH
+      description: Status match
+      bit_offset: 0
+      bit_size: 32
 fieldset/PSMKR:
   description: polling status mask register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Status mask
-    name: MASK
+    - name: MASK
+      description: Status mask
+      bit_offset: 0
+      bit_size: 32
 fieldset/SR:
   description: status register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Transfer error flag
-    name: TEF
-  - bit_offset: 1
-    bit_size: 1
-    description: Transfer complete flag
-    name: TCF
-  - bit_offset: 2
-    bit_size: 1
-    description: FIFO threshold flag
-    name: FTF
-  - bit_offset: 3
-    bit_size: 1
-    description: Status match flag
-    name: SMF
-  - bit_offset: 4
-    bit_size: 1
-    description: Timeout flag
-    name: TOF
-  - bit_offset: 5
-    bit_size: 1
-    description: Busy
-    name: BUSY
-  - bit_offset: 8
-    bit_size: 7
-    description: FIFO level
-    name: FLEVEL
+    - name: TEF
+      description: Transfer error flag
+      bit_offset: 0
+      bit_size: 1
+    - name: TCF
+      description: Transfer complete flag
+      bit_offset: 1
+      bit_size: 1
+    - name: FTF
+      description: FIFO threshold flag
+      bit_offset: 2
+      bit_size: 1
+    - name: SMF
+      description: Status match flag
+      bit_offset: 3
+      bit_size: 1
+    - name: TOF
+      description: Timeout flag
+      bit_offset: 4
+      bit_size: 1
+    - name: BUSY
+      description: Busy
+      bit_offset: 5
+      bit_size: 1
+    - name: FLEVEL
+      description: FIFO level
+      bit_offset: 8
+      bit_size: 7

data/registers/rcc_f410.yaml

@@ -1,3 +1,4 @@
+---
 block/RCC:
   description: Reset and clock control
   items:

data/registers/rcc_u5.yaml

@@ -2560,6 +2560,24 @@ enum/MSIBIAS:
     - name: SAMPLING
       description: MSI bias sampling mode (ultra-low-power mode)
       value: 1
+enum/MSIPLLFAST:
+  bit_size: 1
+  variants:
+    - name: NORMAL
+      description: MSI PLL normal start-up
+      value: 0
+    - name: FAST
+      description: MSI PLL fast start-up
+      value: 1
+enum/MSIPLLSEL:
+  bit_size: 1
+  variants:
+    - name: MSIK
+      description: "PLL mode applied to MSIK (MSI kernel) clock output "
+      value: 0
+    - name: MSIS
+      description: PLL mode applied to MSIS (MSI system) clock output
+      value: 1
 enum/MSIRANGE:
   bit_size: 4
   variants:
@@ -2611,6 +2629,15 @@ enum/MSIRANGE:
     - name: RANGE_100KHZ
       description: "range 15 around 100 kHz "
       value: 15
+enum/MSIRGSEL:
+  bit_size: 1
+  variants:
+    - name: RCC_CSR
+      description: "MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR"
+      value: 0
+    - name: RCC_ICSCR1
+      description: "MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1"
+      value: 1
 enum/MSIXSRANGE:
   bit_size: 4
   variants:
@@ -2629,33 +2656,6 @@ enum/MSIXSRANGE:
     - name: RANGE_3_072MHZ
       description: "range 8 around 3.072 MHz "
       value: 8
-enum/MSIPLLFAST:
-  bit_size: 1
-  variants:
-    - name: NORMAL
-      description: MSI PLL normal start-up
-      value: 0
-    - name: FAST
-      description: MSI PLL fast start-up
-      value: 1
-enum/MSIPLLSEL:
-  bit_size: 1
-  variants:
-    - name: MSIK
-      description: "PLL mode applied to MSIK (MSI kernel) clock output "
-      value: 0
-    - name: MSIS
-      description: PLL mode applied to MSIS (MSI system) clock output
-      value: 1
-enum/MSIRGSEL:
-  bit_size: 1
-  variants:
-    - name: RCC_CSR
-      description: "MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR"
-      value: 0
-    - name: RCC_ICSCR1
-      description: "MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1"
-      value: 1
 enum/OCTOSPISEL:
   bit_size: 2
   variants:
@@ -2758,6 +2758,15 @@ enum/PPRE:
     - name: DIV16
       description: HCLK divided by 16
       value: 7
+enum/PRIV:
+  bit_size: 1
+  variants:
+    - name: UNPRIVILEGED
+      description: Read and write to secure functions can be done by privileged or unprivileged access.
+      value: 0
+    - name: PRIVILEGED
+      description: Read and write to secure functions can be done by privileged access only.
+      value: 1
 enum/RNGSEL:
   bit_size: 2
   variants:
@@ -2821,6 +2830,15 @@ enum/SDMMCSEL:
     - name: PLL1_P
       description: "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) "
       value: 1
+enum/SECURITY:
+  bit_size: 1
+  variants:
+    - name: NON_SECURE
+      description: non secure
+      value: 0
+    - name: SECURE
+      description: secure
+      value: 1
 enum/SPISEL:
   bit_size: 2
   variants:
@@ -2929,21 +2947,3 @@ enum/USARTSEL:
     - name: LSE
       description: LSE selected
       value: 3
-enum/SECURITY:
-  bit_size: 1
-  variants:
-    - name: NON_SECURE
-      description: non secure
-      value: 0
-    - name: SECURE
-      description: secure
-      value: 1
-enum/PRIV:
-  bit_size: 1
-  variants:
-    - name: UNPRIVILEGED
-      description: Read and write to secure functions can be done by privileged or unprivileged access.
-      value: 0
-    - name: PRIVILEGED
-      description: Read and write to secure functions can be done by privileged access only.
-      value: 1

data/registers/sdmmc_v1.yaml

@@ -2,506 +2,505 @@
 block/SDMMC:
   description: Secure digital input/output interface
   items:
-  - byte_offset: 0
-    description: power control register
-    fieldset: POWER
-    name: POWER
-  - byte_offset: 4
-    description: SDI clock control register
-    fieldset: CLKCR
-    name: CLKCR
-  - byte_offset: 8
-    description: argument register
-    fieldset: ARG
-    name: ARG
-  - byte_offset: 12
-    description: command register
-    fieldset: CMD
-    name: CMD
-  - access: Read
-    byte_offset: 16
-    description: command response register
-    fieldset: RESPCMD
-    name: RESPCMD
-  - access: Read
-    byte_offset: 20
-    description: response 1..4 register
-    fieldset: RESP1
-    name: RESP1
-  - access: Read
-    byte_offset: 24
-    description: response 1..4 register
-    fieldset: RESP2
-    name: RESP2
-  - access: Read
-    byte_offset: 28
-    description: response 1..4 register
-    fieldset: RESP3
-    name: RESP3
-  - access: Read
-    byte_offset: 32
-    description: response 1..4 register
-    fieldset: RESP4
-    name: RESP4
-  - byte_offset: 36
-    description: data timer register
-    fieldset: DTIMER
-    name: DTIMER
-  - byte_offset: 40
-    description: data length register
-    fieldset: DLEN
-    name: DLEN
-  - byte_offset: 44
-    description: data control register
-    fieldset: DCTRL
-    name: DCTRL
-  - access: Read
-    byte_offset: 48
-    description: data counter register
-    fieldset: DCOUNT
-    name: DCOUNT
-  - access: Read
-    byte_offset: 52
-    description: status register
-    fieldset: STA
-    name: STA
-  - byte_offset: 56
-    description: interrupt clear register
-    fieldset: ICR
-    name: ICR
-  - byte_offset: 60
-    description: mask register
-    fieldset: MASK
-    name: MASK
-  - access: Read
-    byte_offset: 72
-    description: FIFO counter register
-    fieldset: FIFOCNT
-    name: FIFOCNT
-  - byte_offset: 128
-    description: data FIFO register
-    fieldset: FIFO
-    name: FIFO
+    - name: POWER
+      description: power control register
+      byte_offset: 0
+      fieldset: POWER
+    - name: CLKCR
+      description: SDI clock control register
+      byte_offset: 4
+      fieldset: CLKCR
+    - name: ARG
+      description: argument register
+      byte_offset: 8
+      fieldset: ARG
+    - name: CMD
+      description: command register
+      byte_offset: 12
+      fieldset: CMD
+    - name: RESPCMD
+      description: command response register
+      byte_offset: 16
+      access: Read
+      fieldset: RESPCMD
+    - name: RESP1
+      description: response 1..4 register
+      byte_offset: 20
+      access: Read
+      fieldset: RESP1
+    - name: RESP2
+      description: response 1..4 register
+      byte_offset: 24
+      access: Read
+      fieldset: RESP2
+    - name: RESP3
+      description: response 1..4 register
+      byte_offset: 28
+      access: Read
+      fieldset: RESP3
+    - name: RESP4
+      description: response 1..4 register
+      byte_offset: 32
+      access: Read
+      fieldset: RESP4
+    - name: DTIMER
+      description: data timer register
+      byte_offset: 36
+      fieldset: DTIMER
+    - name: DLEN
+      description: data length register
+      byte_offset: 40
+      fieldset: DLEN
+    - name: DCTRL
+      description: data control register
+      byte_offset: 44
+      fieldset: DCTRL
+    - name: DCOUNT
+      description: data counter register
+      byte_offset: 48
+      access: Read
+      fieldset: DCOUNT
+    - name: STA
+      description: status register
+      byte_offset: 52
+      access: Read
+      fieldset: STA
+    - name: ICR
+      description: interrupt clear register
+      byte_offset: 56
+      fieldset: ICR
+    - name: MASK
+      description: mask register
+      byte_offset: 60
+      fieldset: MASK
+    - name: FIFOCNT
+      description: FIFO counter register
+      byte_offset: 72
+      access: Read
+      fieldset: FIFOCNT
+    - name: FIFO
+      description: data FIFO register
+      byte_offset: 128
+      fieldset: FIFO
 fieldset/ARG:
   description: argument register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Command argument
-    name: CMDARG
+    - name: CMDARG
+      description: Command argument
+      bit_offset: 0
+      bit_size: 32
 fieldset/CLKCR:
   description: SDI clock control register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: Clock divide factor
-    name: CLKDIV
-  - bit_offset: 8
-    bit_size: 1
-    description: Clock enable bit
-    name: CLKEN
-  - bit_offset: 9
-    bit_size: 1
-    description: Power saving configuration bit
-    name: PWRSAV
-  - bit_offset: 10
-    bit_size: 1
-    description: Clock divider bypass enable bit
-    name: BYPASS
-  - bit_offset: 11
-    bit_size: 2
-    description: Wide bus mode enable bit
-    name: WIDBUS
-  - bit_offset: 13
-    bit_size: 1
-    description: SDIO_CK dephasing selection bit
-    name: NEGEDGE
-  - bit_offset: 14
-    bit_size: 1
-    description: HW Flow Control enable
-    name: HWFC_EN
+    - name: CLKDIV
+      description: Clock divide factor
+      bit_offset: 0
+      bit_size: 8
+    - name: CLKEN
+      description: Clock enable bit
+      bit_offset: 8
+      bit_size: 1
+    - name: PWRSAV
+      description: Power saving configuration bit
+      bit_offset: 9
+      bit_size: 1
+    - name: BYPASS
+      description: Clock divider bypass enable bit
+      bit_offset: 10
+      bit_size: 1
+    - name: WIDBUS
+      description: Wide bus mode enable bit
+      bit_offset: 11
+      bit_size: 2
+    - name: NEGEDGE
+      description: SDIO_CK dephasing selection bit
+      bit_offset: 13
+      bit_size: 1
+    - name: HWFC_EN
+      description: HW Flow Control enable
+      bit_offset: 14
+      bit_size: 1
 fieldset/CMD:
   description: command register
   fields:
-  - bit_offset: 0
-    bit_size: 6
-    description: Command index
-    name: CMDINDEX
-  - bit_offset: 6
-    bit_size: 2
-    description: Wait for response bits
-    name: WAITRESP
-  - bit_offset: 8
-    bit_size: 1
-    description: CPSM waits for interrupt request
-    name: WAITINT
-  - bit_offset: 9
-    bit_size: 1
-    description: CPSM Waits for ends of data transfer (CmdPend internal signal)
-    name: WAITPEND
-  - bit_offset: 10
-    bit_size: 1
-    description: Command path state machine (CPSM) Enable bit
-    name: CPSMEN
-  - bit_offset: 11
-    bit_size: 1
-    description: SD I/O suspend command
-    name: SDIOSuspend
+    - name: CMDINDEX
+      description: Command index
+      bit_offset: 0
+      bit_size: 6
+    - name: WAITRESP
+      description: Wait for response bits
+      bit_offset: 6
+      bit_size: 2
+    - name: WAITINT
+      description: CPSM waits for interrupt request
+      bit_offset: 8
+      bit_size: 1
+    - name: WAITPEND
+      description: CPSM Waits for ends of data transfer (CmdPend internal signal)
+      bit_offset: 9
+      bit_size: 1
+    - name: CPSMEN
+      description: Command path state machine (CPSM) Enable bit
+      bit_offset: 10
+      bit_size: 1
+    - name: SDIOSuspend
+      description: SD I/O suspend command
+      bit_offset: 11
+      bit_size: 1
 fieldset/DCOUNT:
   description: data counter register
   fields:
-  - bit_offset: 0
-    bit_size: 25
-    description: Data count value
-    name: DATACOUNT
+    - name: DATACOUNT
+      description: Data count value
+      bit_offset: 0
+      bit_size: 25
 fieldset/DCTRL:
   description: data control register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: DTEN
-    name: DTEN
-  - bit_offset: 1
-    bit_size: 1
-    description: Data transfer direction selection
-    name: DTDIR
-  - bit_offset: 2
-    bit_size: 1
-    description: 'Data transfer mode selection 1: Stream or SDIO multibyte data transfer'
-    name: DTMODE
-  - bit_offset: 3
-    bit_size: 1
-    description: DMA enable bit
-    name: DMAEN
-  - bit_offset: 4
-    bit_size: 4
-    description: Data block size
-    name: DBLOCKSIZE
-  - bit_offset: 8
-    bit_size: 1
-    description: Read wait start
-    name: RWSTART
-  - bit_offset: 9
-    bit_size: 1
-    description: Read wait stop
-    name: RWSTOP
-  - bit_offset: 10
-    bit_size: 1
-    description: Read wait mode
-    name: RWMOD
-  - bit_offset: 11
-    bit_size: 1
-    description: SD I/O enable functions
-    name: SDIOEN
+    - name: DTEN
+      description: DTEN
+      bit_offset: 0
+      bit_size: 1
+    - name: DTDIR
+      description: Data transfer direction selection
+      bit_offset: 1
+      bit_size: 1
+    - name: DTMODE
+      description: "Data transfer mode selection 1: Stream or SDIO multibyte data transfer"
+      bit_offset: 2
+      bit_size: 1
+    - name: DMAEN
+      description: DMA enable bit
+      bit_offset: 3
+      bit_size: 1
+    - name: DBLOCKSIZE
+      description: Data block size
+      bit_offset: 4
+      bit_size: 4
+    - name: RWSTART
+      description: Read wait start
+      bit_offset: 8
+      bit_size: 1
+    - name: RWSTOP
+      description: Read wait stop
+      bit_offset: 9
+      bit_size: 1
+    - name: RWMOD
+      description: Read wait mode
+      bit_offset: 10
+      bit_size: 1
+    - name: SDIOEN
+      description: SD I/O enable functions
+      bit_offset: 11
+      bit_size: 1
 fieldset/DLEN:
   description: data length register
   fields:
-  - bit_offset: 0
-    bit_size: 25
-    description: Data length value
-    name: DATALENGTH
+    - name: DATALENGTH
+      description: Data length value
+      bit_offset: 0
+      bit_size: 25
 fieldset/DTIMER:
   description: data timer register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Data timeout period
-    name: DATATIME
+    - name: DATATIME
+      description: Data timeout period
+      bit_offset: 0
+      bit_size: 32
 fieldset/FIFO:
   description: data FIFO register
   fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Receive and transmit FIFO data
-    name: FIFOData
+    - name: FIFOData
+      description: Receive and transmit FIFO data
+      bit_offset: 0
+      bit_size: 32
 fieldset/FIFOCNT:
   description: FIFO counter register
   fields:
-  - bit_offset: 0
-    bit_size: 24
-    description: Remaining number of words to be written to or read from the FIFO
-    name: FIFOCOUNT
+    - name: FIFOCOUNT
+      description: Remaining number of words to be written to or read from the FIFO
+      bit_offset: 0
+      bit_size: 24
 fieldset/ICR:
   description: interrupt clear register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: CCRCFAIL flag clear bit
-    name: CCRCFAILC
-  - bit_offset: 1
-    bit_size: 1
-    description: DCRCFAIL flag clear bit
-    name: DCRCFAILC
-  - bit_offset: 2
-    bit_size: 1
-    description: CTIMEOUT flag clear bit
-    name: CTIMEOUTC
-  - bit_offset: 3
-    bit_size: 1
-    description: DTIMEOUT flag clear bit
-    name: DTIMEOUTC
-  - bit_offset: 4
-    bit_size: 1
-    description: TXUNDERR flag clear bit
-    name: TXUNDERRC
-  - bit_offset: 5
-    bit_size: 1
-    description: RXOVERR flag clear bit
-    name: RXOVERRC
-  - bit_offset: 6
-    bit_size: 1
-    description: CMDREND flag clear bit
-    name: CMDRENDC
-  - bit_offset: 7
-    bit_size: 1
-    description: CMDSENT flag clear bit
-    name: CMDSENTC
-  - bit_offset: 8
-    bit_size: 1
-    description: DATAEND flag clear bit
-    name: DATAENDC
-  - bit_offset: 10
-    bit_size: 1
-    description: DBCKEND flag clear bit
-    name: DBCKENDC
-  - bit_offset: 22
-    bit_size: 1
-    description: SDIOIT flag clear bit
-    name: SDIOITC
+    - name: CCRCFAILC
+      description: CCRCFAIL flag clear bit
+      bit_offset: 0
+      bit_size: 1
+    - name: DCRCFAILC
+      description: DCRCFAIL flag clear bit
+      bit_offset: 1
+      bit_size: 1
+    - name: CTIMEOUTC
+      description: CTIMEOUT flag clear bit
+      bit_offset: 2
+      bit_size: 1
+    - name: DTIMEOUTC
+      description: DTIMEOUT flag clear bit
+      bit_offset: 3
+      bit_size: 1
+    - name: TXUNDERRC
+      description: TXUNDERR flag clear bit
+      bit_offset: 4
+      bit_size: 1
+    - name: RXOVERRC
+      description: RXOVERR flag clear bit
+      bit_offset: 5
+      bit_size: 1
+    - name: CMDRENDC
+      description: CMDREND flag clear bit
+      bit_offset: 6
+      bit_size: 1
+    - name: CMDSENTC
+      description: CMDSENT flag clear bit
+      bit_offset: 7
+      bit_size: 1
+    - name: DATAENDC
+      description: DATAEND flag clear bit
+      bit_offset: 8
+      bit_size: 1
+    - name: DBCKENDC
+      description: DBCKEND flag clear bit
+      bit_offset: 10
+      bit_size: 1
+    - name: SDIOITC
+      description: SDIOIT flag clear bit
+      bit_offset: 22
+      bit_size: 1
 fieldset/MASK:
   description: mask register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Command CRC fail interrupt enable
-    name: CCRCFAILIE
-  - bit_offset: 1
-    bit_size: 1
-    description: Data CRC fail interrupt enable
-    name: DCRCFAILIE
-  - bit_offset: 2
-    bit_size: 1
-    description: Command timeout interrupt enable
-    name: CTIMEOUTIE
-  - bit_offset: 3
-    bit_size: 1
-    description: Data timeout interrupt enable
-    name: DTIMEOUTIE
-  - bit_offset: 4
-    bit_size: 1
-    description: Tx FIFO underrun error interrupt enable
-    name: TXUNDERRIE
-  - bit_offset: 5
-    bit_size: 1
-    description: Rx FIFO overrun error interrupt enable
-    name: RXOVERRIE
-  - bit_offset: 6
-    bit_size: 1
-    description: Command response received interrupt enable
-    name: CMDRENDIE
-  - bit_offset: 7
-    bit_size: 1
-    description: Command sent interrupt enable
-    name: CMDSENTIE
-  - bit_offset: 8
-    bit_size: 1
-    description: Data end interrupt enable
-    name: DATAENDIE
-  - bit_offset: 10
-    bit_size: 1
-    description: Data block end interrupt enable
-    name: DBCKENDIE
-  - bit_offset: 11
-    bit_size: 1
-    description: Command acting interrupt enable
-    name: CMDACTIE
-  - bit_offset: 12
-    bit_size: 1
-    description: Data transmit acting interrupt enable
-    name: TXACTIE
-  - bit_offset: 13
-    bit_size: 1
-    description: Data receive acting interrupt enable
-    name: RXACTIE
-  - bit_offset: 14
-    bit_size: 1
-    description: Tx FIFO half empty interrupt enable
-    name: TXFIFOHEIE
-  - bit_offset: 15
-    bit_size: 1
-    description: Rx FIFO half full interrupt enable
-    name: RXFIFOHFIE
-  - bit_offset: 16
-    bit_size: 1
-    description: Tx FIFO full interrupt enable
-    name: TXFIFOFIE
-  - bit_offset: 17
-    bit_size: 1
-    description: Rx FIFO full interrupt enable
-    name: RXFIFOFIE
-  - bit_offset: 18
-    bit_size: 1
-    description: Tx FIFO empty interrupt enable
-    name: TXFIFOEIE
-  - bit_offset: 19
-    bit_size: 1
-    description: Rx FIFO empty interrupt enable
-    name: RXFIFOEIE
-  - bit_offset: 20
-    bit_size: 1
-    description: Data available in Tx FIFO interrupt enable
-    name: TXDAVLIE
-  - bit_offset: 21
-    bit_size: 1
-    description: Data available in Rx FIFO interrupt enable
-    name: RXDAVLIE
-  - bit_offset: 22
-    bit_size: 1
-    description: SDIO mode interrupt received interrupt enable
-    name: SDIOITIE
+    - name: CCRCFAILIE
+      description: Command CRC fail interrupt enable
+      bit_offset: 0
+      bit_size: 1
+    - name: DCRCFAILIE
+      description: Data CRC fail interrupt enable
+      bit_offset: 1
+      bit_size: 1
+    - name: CTIMEOUTIE
+      description: Command timeout interrupt enable
+      bit_offset: 2
+      bit_size: 1
+    - name: DTIMEOUTIE
+      description: Data timeout interrupt enable
+      bit_offset: 3
+      bit_size: 1
+    - name: TXUNDERRIE
+      description: Tx FIFO underrun error interrupt enable
+      bit_offset: 4
+      bit_size: 1
+    - name: RXOVERRIE
+      description: Rx FIFO overrun error interrupt enable
+      bit_offset: 5
+      bit_size: 1
+    - name: CMDRENDIE
+      description: Command response received interrupt enable
+      bit_offset: 6
+      bit_size: 1
+    - name: CMDSENTIE
+      description: Command sent interrupt enable
+      bit_offset: 7
+      bit_size: 1
+    - name: DATAENDIE
+      description: Data end interrupt enable
+      bit_offset: 8
+      bit_size: 1
+    - name: DBCKENDIE
+      description: Data block end interrupt enable
+      bit_offset: 10
+      bit_size: 1
+    - name: CMDACTIE
+      description: Command acting interrupt enable
+      bit_offset: 11
+      bit_size: 1
+    - name: TXACTIE
+      description: Data transmit acting interrupt enable
+      bit_offset: 12
+      bit_size: 1
+    - name: RXACTIE
+      description: Data receive acting interrupt enable
+      bit_offset: 13
+      bit_size: 1
+    - name: TXFIFOHEIE
+      description: Tx FIFO half empty interrupt enable
+      bit_offset: 14
+      bit_size: 1
+    - name: RXFIFOHFIE
+      description: Rx FIFO half full interrupt enable
+      bit_offset: 15
+      bit_size: 1
+    - name: TXFIFOFIE
+      description: Tx FIFO full interrupt enable
+      bit_offset: 16
+      bit_size: 1
+    - name: RXFIFOFIE
+      description: Rx FIFO full interrupt enable
+      bit_offset: 17
+      bit_size: 1
+    - name: TXFIFOEIE
+      description: Tx FIFO empty interrupt enable
+      bit_offset: 18
+      bit_size: 1
+    - name: RXFIFOEIE
+      description: Rx FIFO empty interrupt enable
+      bit_offset: 19
+      bit_size: 1
+    - name: TXDAVLIE
+      description: Data available in Tx FIFO interrupt enable
+      bit_offset: 20
+      bit_size: 1
+    - name: RXDAVLIE
+      description: Data available in Rx FIFO interrupt enable
+      bit_offset: 21
+      bit_size: 1
+    - name: SDIOITIE
+      description: SDIO mode interrupt received interrupt enable
+      bit_offset: 22
+      bit_size: 1
 fieldset/POWER:
   description: power control register
   fields:
-  - bit_offset: 0
-    bit_size: 2
-    description: PWRCTRL
-    name: PWRCTRL
+    - name: PWRCTRL
+      description: PWRCTRL
+      bit_offset: 0
+      bit_size: 2
 fieldset/RESP1:
   description: response 1..4 register
   fields:
-  - array:
-      len: 1
-      stride: 0
-    bit_offset: 0
-    bit_size: 32
-    description: see Table 132
-    name: CARDSTATUS
+    - name: CARDSTATUS
+      description: see Table 132
+      bit_offset: 0
+      bit_size: 32
+      array:
+        len: 1
+        stride: 0
 fieldset/RESP2:
   description: response 1..4 register
   fields:
-  - array:
-      len: 1
-      stride: 0
-    bit_offset: 0
-    bit_size: 32
-    description: see Table 132
-    name: CARDSTATUS
+    - name: CARDSTATUS
+      description: see Table 132
+      bit_offset: 0
+      bit_size: 32
+      array:
+        len: 1
+        stride: 0
 fieldset/RESP3:
   description: response 1..4 register
   fields:
-  - array:
-      len: 1
-      stride: 0
-    bit_offset: 0
-    bit_size: 32
-    description: see Table 132
-    name: CARDSTATUS
+    - name: CARDSTATUS
+      description: see Table 132
+      bit_offset: 0
+      bit_size: 32
+      array:
+        len: 1
+        stride: 0
 fieldset/RESP4:
   description: response 1..4 register
   fields:
-  - array:
-      len: 1
-      stride: 0
-    bit_offset: 0
-    bit_size: 32
-    description: see Table 132
-    name: CARDSTATUS
+    - name: CARDSTATUS
+      description: see Table 132
+      bit_offset: 0
+      bit_size: 32
+      array:
+        len: 1
+        stride: 0
 fieldset/RESPCMD:
   description: command response register
   fields:
-  - bit_offset: 0
-    bit_size: 6
-    description: Response command index
-    name: RESPCMD
+    - name: RESPCMD
+      description: Response command index
+      bit_offset: 0
+      bit_size: 6
 fieldset/STA:
   description: status register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Command response received (CRC check failed)
-    name: CCRCFAIL
-  - bit_offset: 1
-    bit_size: 1
-    description: Data block sent/received (CRC check failed)
-    name: DCRCFAIL
-  - bit_offset: 2
-    bit_size: 1
-    description: Command response timeout
-    name: CTIMEOUT
-  - bit_offset: 3
-    bit_size: 1
-    description: Data timeout
-    name: DTIMEOUT
-  - bit_offset: 4
-    bit_size: 1
-    description: Transmit FIFO underrun error
-    name: TXUNDERR
-  - bit_offset: 5
-    bit_size: 1
-    description: Received FIFO overrun error
-    name: RXOVERR
-  - bit_offset: 6
-    bit_size: 1
-    description: Command response received (CRC check passed)
-    name: CMDREND
-  - bit_offset: 7
-    bit_size: 1
-    description: Command sent (no response required)
-    name: CMDSENT
-  - bit_offset: 8
-    bit_size: 1
-    description: Data end (data counter, SDIDCOUNT, is zero)
-    name: DATAEND
-  - bit_offset: 10
-    bit_size: 1
-    description: Data block sent/received (CRC check passed)
-    name: DBCKEND
-  - bit_offset: 11
-    bit_size: 1
-    description: Command transfer in progress
-    name: CMDACT
-  - bit_offset: 12
-    bit_size: 1
-    description: Data transmit in progress
-    name: TXACT
-  - bit_offset: 13
-    bit_size: 1
-    description: Data receive in progress
-    name: RXACT
-  - bit_offset: 14
-    bit_size: 1
-    description: 'Transmit FIFO half empty: at least 8 words can be written into the
-      FIFO'
-    name: TXFIFOHE
-  - bit_offset: 15
-    bit_size: 1
-    description: 'Receive FIFO half full: there are at least 8 words in the FIFO'
-    name: RXFIFOHF
-  - bit_offset: 16
-    bit_size: 1
-    description: Transmit FIFO full
-    name: TXFIFOF
-  - bit_offset: 17
-    bit_size: 1
-    description: Receive FIFO full
-    name: RXFIFOF
-  - bit_offset: 18
-    bit_size: 1
-    description: Transmit FIFO empty
-    name: TXFIFOE
-  - bit_offset: 19
-    bit_size: 1
-    description: Receive FIFO empty
-    name: RXFIFOE
-  - bit_offset: 20
-    bit_size: 1
-    description: Data available in transmit FIFO
-    name: TXDAVL
-  - bit_offset: 21
-    bit_size: 1
-    description: Data available in receive FIFO
-    name: RXDAVL
-  - bit_offset: 22
-    bit_size: 1
-    description: SDIO interrupt received
-    name: SDIOIT
+    - name: CCRCFAIL
+      description: Command response received (CRC check failed)
+      bit_offset: 0
+      bit_size: 1
+    - name: DCRCFAIL
+      description: Data block sent/received (CRC check failed)
+      bit_offset: 1
+      bit_size: 1
+    - name: CTIMEOUT
+      description: Command response timeout
+      bit_offset: 2
+      bit_size: 1
+    - name: DTIMEOUT
+      description: Data timeout
+      bit_offset: 3
+      bit_size: 1
+    - name: TXUNDERR
+      description: Transmit FIFO underrun error
+      bit_offset: 4
+      bit_size: 1
+    - name: RXOVERR
+      description: Received FIFO overrun error
+      bit_offset: 5
+      bit_size: 1
+    - name: CMDREND
+      description: Command response received (CRC check passed)
+      bit_offset: 6
+      bit_size: 1
+    - name: CMDSENT
+      description: Command sent (no response required)
+      bit_offset: 7
+      bit_size: 1
+    - name: DATAEND
+      description: "Data end (data counter, SDIDCOUNT, is zero)"
+      bit_offset: 8
+      bit_size: 1
+    - name: DBCKEND
+      description: Data block sent/received (CRC check passed)
+      bit_offset: 10
+      bit_size: 1
+    - name: CMDACT
+      description: Command transfer in progress
+      bit_offset: 11
+      bit_size: 1
+    - name: TXACT
+      description: Data transmit in progress
+      bit_offset: 12
+      bit_size: 1
+    - name: RXACT
+      description: Data receive in progress
+      bit_offset: 13
+      bit_size: 1
+    - name: TXFIFOHE
+      description: "Transmit FIFO half empty: at least 8 words can be written into the FIFO"
+      bit_offset: 14
+      bit_size: 1
+    - name: RXFIFOHF
+      description: "Receive FIFO half full: there are at least 8 words in the FIFO"
+      bit_offset: 15
+      bit_size: 1
+    - name: TXFIFOF
+      description: Transmit FIFO full
+      bit_offset: 16
+      bit_size: 1
+    - name: RXFIFOF
+      description: Receive FIFO full
+      bit_offset: 17
+      bit_size: 1
+    - name: TXFIFOE
+      description: Transmit FIFO empty
+      bit_offset: 18
+      bit_size: 1
+    - name: RXFIFOE
+      description: Receive FIFO empty
+      bit_offset: 19
+      bit_size: 1
+    - name: TXDAVL
+      description: Data available in transmit FIFO
+      bit_offset: 20
+      bit_size: 1
+    - name: RXDAVL
+      description: Data available in receive FIFO
+      bit_offset: 21
+      bit_size: 1
+    - name: SDIOIT
+      description: SDIO interrupt received
+      bit_offset: 22
+      bit_size: 1

data/registers/spdifrx_v1.yaml

@@ -2,240 +2,240 @@
 block/SPDIFRX:
   description: Receiver Interface
   items:
-  - byte_offset: 0
-    description: Control register
-    fieldset: CR
-    name: CR
-  - byte_offset: 4
-    description: Interrupt mask register
-    fieldset: IMR
-    name: IMR
-  - access: Read
-    byte_offset: 8
-    description: Status register
-    fieldset: SR
-    name: SR
-  - access: Write
-    byte_offset: 12
-    description: Interrupt Flag Clear register
-    fieldset: IFCR
-    name: IFCR
-  - access: Read
-    byte_offset: 16
-    description: Data input register
-    fieldset: DR
-    name: DR
-  - access: Read
-    byte_offset: 20
-    description: Channel Status register
-    fieldset: CSR
-    name: CSR
-  - access: Read
-    byte_offset: 24
-    description: Debug Information register
-    fieldset: DIR
-    name: DIR
+    - name: CR
+      description: Control register
+      byte_offset: 0
+      fieldset: CR
+    - name: IMR
+      description: Interrupt mask register
+      byte_offset: 4
+      fieldset: IMR
+    - name: SR
+      description: Status register
+      byte_offset: 8
+      access: Read
+      fieldset: SR
+    - name: IFCR
+      description: Interrupt Flag Clear register
+      byte_offset: 12
+      access: Write
+      fieldset: IFCR
+    - name: DR
+      description: Data input register
+      byte_offset: 16
+      access: Read
+      fieldset: DR
+    - name: CSR
+      description: Channel Status register
+      byte_offset: 20
+      access: Read
+      fieldset: CSR
+    - name: DIR
+      description: Debug Information register
+      byte_offset: 24
+      access: Read
+      fieldset: DIR
 fieldset/CR:
   description: Control register
   fields:
-  - bit_offset: 0
-    bit_size: 2
-    description: Peripheral Block Enable
-    name: SPDIFEN
-  - bit_offset: 2
-    bit_size: 1
-    description: Receiver DMA ENable for data flow
-    name: RXDMAEN
-  - bit_offset: 3
-    bit_size: 1
-    description: STerEO Mode
-    name: RXSTEO
-  - bit_offset: 4
-    bit_size: 2
-    description: RX Data format
-    name: DRFMT
-  - bit_offset: 6
-    bit_size: 1
-    description: Mask Parity error bit
-    name: PMSK
-  - bit_offset: 7
-    bit_size: 1
-    description: Mask of Validity bit
-    name: VMSK
-  - bit_offset: 8
-    bit_size: 1
-    description: Mask of channel status and user bits
-    name: CUMSK
-  - bit_offset: 9
-    bit_size: 1
-    description: Mask of Preamble Type bits
-    name: PTMSK
-  - bit_offset: 10
-    bit_size: 1
-    description: Control Buffer DMA ENable for control flow
-    name: CBDMAEN
-  - bit_offset: 11
-    bit_size: 1
-    description: Channel Selection
-    name: CHSEL
-  - bit_offset: 12
-    bit_size: 2
-    description: Maximum allowed re-tries during synchronization phase
-    name: NBTR
-  - bit_offset: 14
-    bit_size: 1
-    description: Wait For Activity
-    name: WFA
-  - bit_offset: 16
-    bit_size: 3
-    description: input selection
-    name: INSEL
+    - name: SPDIFEN
+      description: Peripheral Block Enable
+      bit_offset: 0
+      bit_size: 2
+    - name: RXDMAEN
+      description: Receiver DMA ENable for data flow
+      bit_offset: 2
+      bit_size: 1
+    - name: RXSTEO
+      description: STerEO Mode
+      bit_offset: 3
+      bit_size: 1
+    - name: DRFMT
+      description: RX Data format
+      bit_offset: 4
+      bit_size: 2
+    - name: PMSK
+      description: Mask Parity error bit
+      bit_offset: 6
+      bit_size: 1
+    - name: VMSK
+      description: Mask of Validity bit
+      bit_offset: 7
+      bit_size: 1
+    - name: CUMSK
+      description: Mask of channel status and user bits
+      bit_offset: 8
+      bit_size: 1
+    - name: PTMSK
+      description: Mask of Preamble Type bits
+      bit_offset: 9
+      bit_size: 1
+    - name: CBDMAEN
+      description: Control Buffer DMA ENable for control flow
+      bit_offset: 10
+      bit_size: 1
+    - name: CHSEL
+      description: Channel Selection
+      bit_offset: 11
+      bit_size: 1
+    - name: NBTR
+      description: Maximum allowed re-tries during synchronization phase
+      bit_offset: 12
+      bit_size: 2
+    - name: WFA
+      description: Wait For Activity
+      bit_offset: 14
+      bit_size: 1
+    - name: INSEL
+      description: input selection
+      bit_offset: 16
+      bit_size: 3
 fieldset/CSR:
   description: Channel Status register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: User data information
-    name: USR
-  - bit_offset: 16
-    bit_size: 8
-    description: Channel A status information
-    name: CS
-  - bit_offset: 24
-    bit_size: 1
-    description: Start Of Block
-    name: SOB
+    - name: USR
+      description: User data information
+      bit_offset: 0
+      bit_size: 16
+    - name: CS
+      description: Channel A status information
+      bit_offset: 16
+      bit_size: 8
+    - name: SOB
+      description: Start Of Block
+      bit_offset: 24
+      bit_size: 1
 fieldset/DIR:
   description: Debug Information register
   fields:
-  - bit_offset: 0
-    bit_size: 13
-    description: Threshold HIGH
-    name: THI
-  - bit_offset: 16
-    bit_size: 13
-    description: Threshold LOW
-    name: TLO
+    - name: THI
+      description: Threshold HIGH
+      bit_offset: 0
+      bit_size: 13
+    - name: TLO
+      description: Threshold LOW
+      bit_offset: 16
+      bit_size: 13
 fieldset/DR:
   description: Data input register
   fields:
-  - bit_offset: 0
-    bit_size: 24
-    description: Parity Error bit
-    name: DR
-  - bit_offset: 24
-    bit_size: 1
-    description: Parity Error bit
-    name: PE
-  - bit_offset: 25
-    bit_size: 1
-    description: Validity bit
-    name: V
-  - bit_offset: 26
-    bit_size: 1
-    description: User bit
-    name: U
-  - bit_offset: 27
-    bit_size: 1
-    description: Channel Status bit
-    name: C
-  - bit_offset: 28
-    bit_size: 2
-    description: Preamble Type
-    name: PT
+    - name: DR
+      description: Parity Error bit
+      bit_offset: 0
+      bit_size: 24
+    - name: PE
+      description: Parity Error bit
+      bit_offset: 24
+      bit_size: 1
+    - name: V
+      description: Validity bit
+      bit_offset: 25
+      bit_size: 1
+    - name: U
+      description: User bit
+      bit_offset: 26
+      bit_size: 1
+    - name: C
+      description: Channel Status bit
+      bit_offset: 27
+      bit_size: 1
+    - name: PT
+      description: Preamble Type
+      bit_offset: 28
+      bit_size: 2
 fieldset/IFCR:
   description: Interrupt Flag Clear register
   fields:
-  - bit_offset: 2
-    bit_size: 1
-    description: Clears the Parity error flag
-    name: PERRCF
-  - bit_offset: 3
-    bit_size: 1
-    description: Clears the Overrun error flag
-    name: OVRCF
-  - bit_offset: 4
-    bit_size: 1
-    description: Clears the Synchronization Block Detected flag
-    name: SBDCF
-  - bit_offset: 5
-    bit_size: 1
-    description: Clears the Synchronization Done flag
-    name: SYNCDCF
+    - name: PERRCF
+      description: Clears the Parity error flag
+      bit_offset: 2
+      bit_size: 1
+    - name: OVRCF
+      description: Clears the Overrun error flag
+      bit_offset: 3
+      bit_size: 1
+    - name: SBDCF
+      description: Clears the Synchronization Block Detected flag
+      bit_offset: 4
+      bit_size: 1
+    - name: SYNCDCF
+      description: Clears the Synchronization Done flag
+      bit_offset: 5
+      bit_size: 1
 fieldset/IMR:
   description: Interrupt mask register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: RXNE interrupt enable
-    name: RXNEIE
-  - bit_offset: 1
-    bit_size: 1
-    description: Control Buffer Ready Interrupt Enable
-    name: CSRNEIE
-  - bit_offset: 2
-    bit_size: 1
-    description: Parity error interrupt enable
-    name: PERRIE
-  - bit_offset: 3
-    bit_size: 1
-    description: Overrun error Interrupt Enable
-    name: OVRIE
-  - bit_offset: 4
-    bit_size: 1
-    description: Synchronization Block Detected Interrupt Enable
-    name: SBLKIE
-  - bit_offset: 5
-    bit_size: 1
-    description: Synchronization Done
-    name: SYNCDIE
-  - bit_offset: 6
-    bit_size: 1
-    description: Serial Interface Error Interrupt Enable
-    name: IFEIE
+    - name: RXNEIE
+      description: RXNE interrupt enable
+      bit_offset: 0
+      bit_size: 1
+    - name: CSRNEIE
+      description: Control Buffer Ready Interrupt Enable
+      bit_offset: 1
+      bit_size: 1
+    - name: PERRIE
+      description: Parity error interrupt enable
+      bit_offset: 2
+      bit_size: 1
+    - name: OVRIE
+      description: Overrun error Interrupt Enable
+      bit_offset: 3
+      bit_size: 1
+    - name: SBLKIE
+      description: Synchronization Block Detected Interrupt Enable
+      bit_offset: 4
+      bit_size: 1
+    - name: SYNCDIE
+      description: Synchronization Done
+      bit_offset: 5
+      bit_size: 1
+    - name: IFEIE
+      description: Serial Interface Error Interrupt Enable
+      bit_offset: 6
+      bit_size: 1
 fieldset/SR:
   description: Status register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Read data register not empty
-    name: RXNE
-  - bit_offset: 1
-    bit_size: 1
-    description: Control Buffer register is not empty
-    name: CSRNE
-  - bit_offset: 2
-    bit_size: 1
-    description: Parity error
-    name: PERR
-  - bit_offset: 3
-    bit_size: 1
-    description: Overrun error
-    name: OVR
-  - bit_offset: 4
-    bit_size: 1
-    description: Synchronization Block Detected
-    name: SBD
-  - bit_offset: 5
-    bit_size: 1
-    description: Synchronization Done
-    name: SYNCD
-  - bit_offset: 6
-    bit_size: 1
-    description: Framing error
-    name: FERR
-  - bit_offset: 7
-    bit_size: 1
-    description: Synchronization error
-    name: SERR
-  - bit_offset: 8
-    bit_size: 1
-    description: Time-out error
-    name: TERR
-  - array:
-      len: 1
-      stride: 0
-    bit_offset: 16
-    bit_size: 15
-    description: Duration of 5 symbols counted with SPDIF_CLK
-    name: WIDTH
+    - name: RXNE
+      description: Read data register not empty
+      bit_offset: 0
+      bit_size: 1
+    - name: CSRNE
+      description: Control Buffer register is not empty
+      bit_offset: 1
+      bit_size: 1
+    - name: PERR
+      description: Parity error
+      bit_offset: 2
+      bit_size: 1
+    - name: OVR
+      description: Overrun error
+      bit_offset: 3
+      bit_size: 1
+    - name: SBD
+      description: Synchronization Block Detected
+      bit_offset: 4
+      bit_size: 1
+    - name: SYNCD
+      description: Synchronization Done
+      bit_offset: 5
+      bit_size: 1
+    - name: FERR
+      description: Framing error
+      bit_offset: 6
+      bit_size: 1
+    - name: SERR
+      description: Synchronization error
+      bit_offset: 7
+      bit_size: 1
+    - name: TERR
+      description: Time-out error
+      bit_offset: 8
+      bit_size: 1
+    - name: WIDTH
+      description: Duration of 5 symbols counted with SPDIF_CLK
+      bit_offset: 16
+      bit_size: 15
+      array:
+        len: 1
+        stride: 0

data/registers/spi_f1.yaml

@@ -2,483 +2,483 @@
 block/SPI:
   description: Serial peripheral interface
   items:
-  - byte_offset: 0
-    description: control register 1
-    fieldset: CR1
-    name: CR1
-  - byte_offset: 4
-    description: control register 2
-    fieldset: CR2
-    name: CR2
-  - byte_offset: 8
-    description: status register
-    fieldset: SR
-    name: SR
-  - byte_offset: 12
-    description: data register
-    fieldset: DR
-    name: DR
-  - byte_offset: 16
-    description: CRC polynomial register
-    fieldset: CRCPR
-    name: CRCPR
-  - access: Read
-    byte_offset: 20
-    description: RX CRC register
-    fieldset: RXCRCR
-    name: RXCRCR
-  - access: Read
-    byte_offset: 24
-    description: TX CRC register
-    fieldset: TXCRCR
-    name: TXCRCR
-  - byte_offset: 28
-    description: I2S configuration register
-    fieldset: I2SCFGR
-    name: I2SCFGR
-  - byte_offset: 32
-    description: I2S prescaler register
-    fieldset: I2SPR
-    name: I2SPR
-enum/BIDIMODE:
-  bit_size: 1
-  variants:
-  - description: 2-line unidirectional data mode selected
-    name: Unidirectional
-    value: 0
-  - description: 1-line bidirectional data mode selected
-    name: Bidirectional
-    value: 1
-enum/BIDIOE:
-  bit_size: 1
-  variants:
-  - description: Output disabled (receive-only mode)
-    name: OutputDisabled
-    value: 0
-  - description: Output enabled (transmit-only mode)
-    name: OutputEnabled
-    value: 1
-enum/BR:
-  bit_size: 3
-  variants:
-  - description: f_PCLK / 2
-    name: Div2
-    value: 0
-  - description: f_PCLK / 4
-    name: Div4
-    value: 1
-  - description: f_PCLK / 8
-    name: Div8
-    value: 2
-  - description: f_PCLK / 16
-    name: Div16
-    value: 3
-  - description: f_PCLK / 32
-    name: Div32
-    value: 4
-  - description: f_PCLK / 64
-    name: Div64
-    value: 5
-  - description: f_PCLK / 128
-    name: Div128
-    value: 6
-  - description: f_PCLK / 256
-    name: Div256
-    value: 7
-enum/CHLEN:
-  bit_size: 1
-  variants:
-  - description: 16-bit wide
-    name: SixteenBit
-    value: 0
-  - description: 32-bit wide
-    name: ThirtyTwoBit
-    value: 1
-enum/CHSIDE:
-  bit_size: 1
-  variants:
-  - description: Channel left has to be transmitted or has been received
-    name: Left
-    value: 0
-  - description: Channel right has to be transmitted or has been received
-    name: Right
-    value: 1
-enum/CKPOL:
-  bit_size: 1
-  variants:
-  - description: I2S clock inactive state is low level
-    name: IdleLow
-    value: 0
-  - description: I2S clock inactive state is high level
-    name: IdleHigh
-    value: 1
-enum/CPHA:
-  bit_size: 1
-  variants:
-  - description: The first clock transition is the first data capture edge
-    name: FirstEdge
-    value: 0
-  - description: The second clock transition is the first data capture edge
-    name: SecondEdge
-    value: 1
-enum/CPOL:
-  bit_size: 1
-  variants:
-  - description: CK to 0 when idle
-    name: IdleLow
-    value: 0
-  - description: CK to 1 when idle
-    name: IdleHigh
-    value: 1
-enum/CRCNEXT:
-  bit_size: 1
-  variants:
-  - description: Next transmit value is from Tx buffer
-    name: TxBuffer
-    value: 0
-  - description: Next transmit value is from Tx CRC register
-    name: CRC
-    value: 1
-enum/DATLEN:
-  bit_size: 2
-  variants:
-  - description: 16-bit data length
-    name: SixteenBit
-    value: 0
-  - description: 24-bit data length
-    name: TwentyFourBit
-    value: 1
-  - description: 32-bit data length
-    name: ThirtyTwoBit
-    value: 2
-enum/DFF:
-  bit_size: 1
-  variants:
-  - description: 8-bit data frame format is selected for transmission/reception
-    name: EightBit
-    value: 0
-  - description: 16-bit data frame format is selected for transmission/reception
-    name: SixteenBit
-    value: 1
-enum/ERRIE:
-  bit_size: 1
-  variants:
-  - description: Error interrupt masked
-    name: Masked
-    value: 0
-  - description: Error interrupt not masked
-    name: NotMasked
-    value: 1
-enum/ISCFG:
-  bit_size: 2
-  variants:
-  - description: Slave - transmit
-    name: SlaveTx
-    value: 0
-  - description: Slave - receive
-    name: SlaveRx
-    value: 1
-  - description: Master - transmit
-    name: MasterTx
-    value: 2
-  - description: Master - receive
-    name: MasterRx
-    value: 3
-enum/ISMOD:
-  bit_size: 1
-  variants:
-  - description: SPI mode is selected
-    name: SPIMode
-    value: 0
-  - description: I2S mode is selected
-    name: I2SMode
-    value: 1
-enum/ISSTD:
-  bit_size: 2
-  variants:
-  - description: I2S Philips standard
-    name: Philips
-    value: 0
-  - description: MSB justified standard
-    name: MSB
-    value: 1
-  - description: LSB justified standard
-    name: LSB
-    value: 2
-  - description: PCM standard
-    name: PCM
-    value: 3
-enum/LSBFIRST:
-  bit_size: 1
-  variants:
-  - description: Data is transmitted/received with the MSB first
-    name: MSBFirst
-    value: 0
-  - description: Data is transmitted/received with the LSB first
-    name: LSBFirst
-    value: 1
-enum/MSTR:
-  bit_size: 1
-  variants:
-  - description: Slave configuration
-    name: Slave
-    value: 0
-  - description: Master configuration
-    name: Master
-    value: 1
-enum/ODD:
-  bit_size: 1
-  variants:
-  - description: Real divider value is I2SDIV * 2
-    name: Even
-    value: 0
-  - description: Real divider value is (I2SDIV * 2) + 1
-    name: Odd
-    value: 1
-enum/OVRR:
-  bit_size: 1
-  variants:
-  - description: No overrun occurred
-    name: NoOverrun
-    value: 0
-  - description: Overrun occurred
-    name: Overrun
-    value: 1
-enum/PCMSYNC:
-  bit_size: 1
-  variants:
-  - description: Short frame synchronisation
-    name: Short
-    value: 0
-  - description: Long frame synchronisation
-    name: Long
-    value: 1
-enum/RXONLY:
-  bit_size: 1
-  variants:
-  - description: Full duplex (Transmit and receive)
-    name: FullDuplex
-    value: 0
-  - description: Output disabled (Receive-only mode)
-    name: OutputDisabled
-    value: 1
+    - name: CR1
+      description: control register 1
+      byte_offset: 0
+      fieldset: CR1
+    - name: CR2
+      description: control register 2
+      byte_offset: 4
+      fieldset: CR2
+    - name: SR
+      description: status register
+      byte_offset: 8
+      fieldset: SR
+    - name: DR
+      description: data register
+      byte_offset: 12
+      fieldset: DR
+    - name: CRCPR
+      description: CRC polynomial register
+      byte_offset: 16
+      fieldset: CRCPR
+    - name: RXCRCR
+      description: RX CRC register
+      byte_offset: 20
+      access: Read
+      fieldset: RXCRCR
+    - name: TXCRCR
+      description: TX CRC register
+      byte_offset: 24
+      access: Read
+      fieldset: TXCRCR
+    - name: I2SCFGR
+      description: I2S configuration register
+      byte_offset: 28
+      fieldset: I2SCFGR
+    - name: I2SPR
+      description: I2S prescaler register
+      byte_offset: 32
+      fieldset: I2SPR
 fieldset/CR1:
   description: control register 1
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Clock phase
-    enum: CPHA
-    name: CPHA
-  - bit_offset: 1
-    bit_size: 1
-    description: Clock polarity
-    enum: CPOL
-    name: CPOL
-  - bit_offset: 2
-    bit_size: 1
-    description: Master selection
-    enum: MSTR
-    name: MSTR
-  - bit_offset: 3
-    bit_size: 3
-    description: Baud rate control
-    enum: BR
-    name: BR
-  - bit_offset: 6
-    bit_size: 1
-    description: SPI enable
-    name: SPE
-  - bit_offset: 7
-    bit_size: 1
-    description: Frame format
-    enum: LSBFIRST
-    name: LSBFIRST
-  - bit_offset: 8
-    bit_size: 1
-    description: Internal slave select
-    name: SSI
-  - bit_offset: 9
-    bit_size: 1
-    description: Software slave management
-    name: SSM
-  - bit_offset: 10
-    bit_size: 1
-    description: Receive only
-    enum: RXONLY
-    name: RXONLY
-  - bit_offset: 11
-    bit_size: 1
-    description: Data frame format
-    enum: DFF
-    name: DFF
-  - bit_offset: 12
-    bit_size: 1
-    description: CRC transfer next
-    enum: CRCNEXT
-    name: CRCNEXT
-  - bit_offset: 13
-    bit_size: 1
-    description: Hardware CRC calculation enable
-    name: CRCEN
-  - bit_offset: 14
-    bit_size: 1
-    description: Output enable in bidirectional mode
-    enum: BIDIOE
-    name: BIDIOE
-  - bit_offset: 15
-    bit_size: 1
-    description: Bidirectional data mode enable
-    enum: BIDIMODE
-    name: BIDIMODE
+    - name: CPHA
+      description: Clock phase
+      bit_offset: 0
+      bit_size: 1
+      enum: CPHA
+    - name: CPOL
+      description: Clock polarity
+      bit_offset: 1
+      bit_size: 1
+      enum: CPOL
+    - name: MSTR
+      description: Master selection
+      bit_offset: 2
+      bit_size: 1
+      enum: MSTR
+    - name: BR
+      description: Baud rate control
+      bit_offset: 3
+      bit_size: 3
+      enum: BR
+    - name: SPE
+      description: SPI enable
+      bit_offset: 6
+      bit_size: 1
+    - name: LSBFIRST
+      description: Frame format
+      bit_offset: 7
+      bit_size: 1
+      enum: LSBFIRST
+    - name: SSI
+      description: Internal slave select
+      bit_offset: 8
+      bit_size: 1
+    - name: SSM
+      description: Software slave management
+      bit_offset: 9
+      bit_size: 1
+    - name: RXONLY
+      description: Receive only
+      bit_offset: 10
+      bit_size: 1
+      enum: RXONLY
+    - name: DFF
+      description: Data frame format
+      bit_offset: 11
+      bit_size: 1
+      enum: DFF
+    - name: CRCNEXT
+      description: CRC transfer next
+      bit_offset: 12
+      bit_size: 1
+      enum: CRCNEXT
+    - name: CRCEN
+      description: Hardware CRC calculation enable
+      bit_offset: 13
+      bit_size: 1
+    - name: BIDIOE
+      description: Output enable in bidirectional mode
+      bit_offset: 14
+      bit_size: 1
+      enum: BIDIOE
+    - name: BIDIMODE
+      description: Bidirectional data mode enable
+      bit_offset: 15
+      bit_size: 1
+      enum: BIDIMODE
 fieldset/CR2:
   description: control register 2
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Rx buffer DMA enable
-    name: RXDMAEN
-  - bit_offset: 1
-    bit_size: 1
-    description: Tx buffer DMA enable
-    name: TXDMAEN
-  - bit_offset: 2
-    bit_size: 1
-    description: SS output enable
-    name: SSOE
-  - bit_offset: 5
-    bit_size: 1
-    description: Error interrupt enable
-    enum: ERRIE
-    name: ERRIE
-  - bit_offset: 6
-    bit_size: 1
-    description: RX buffer not empty interrupt enable
-    name: RXNEIE
-  - bit_offset: 7
-    bit_size: 1
-    description: Tx buffer empty interrupt enable
-    name: TXEIE
+    - name: RXDMAEN
+      description: Rx buffer DMA enable
+      bit_offset: 0
+      bit_size: 1
+    - name: TXDMAEN
+      description: Tx buffer DMA enable
+      bit_offset: 1
+      bit_size: 1
+    - name: SSOE
+      description: SS output enable
+      bit_offset: 2
+      bit_size: 1
+    - name: ERRIE
+      description: Error interrupt enable
+      bit_offset: 5
+      bit_size: 1
+      enum: ERRIE
+    - name: RXNEIE
+      description: RX buffer not empty interrupt enable
+      bit_offset: 6
+      bit_size: 1
+    - name: TXEIE
+      description: Tx buffer empty interrupt enable
+      bit_offset: 7
+      bit_size: 1
 fieldset/CRCPR:
   description: CRC polynomial register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: CRC polynomial register
-    name: CRCPOLY
+    - name: CRCPOLY
+      description: CRC polynomial register
+      bit_offset: 0
+      bit_size: 16
 fieldset/DR:
   description: data register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Data register
-    name: DR
+    - name: DR
+      description: Data register
+      bit_offset: 0
+      bit_size: 16
 fieldset/I2SCFGR:
   description: I2S configuration register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Channel length (number of bits per audio channel)
-    enum: CHLEN
-    name: CHLEN
-  - bit_offset: 1
-    bit_size: 2
-    description: Data length to be transferred
-    enum: DATLEN
-    name: DATLEN
-  - bit_offset: 3
-    bit_size: 1
-    description: Steady state clock polarity
-    enum: CKPOL
-    name: CKPOL
-  - bit_offset: 4
-    bit_size: 2
-    description: I2S standard selection
-    enum: ISSTD
-    name: I2SSTD
-  - bit_offset: 7
-    bit_size: 1
-    description: PCM frame synchronization
-    enum: PCMSYNC
-    name: PCMSYNC
-  - bit_offset: 8
-    bit_size: 2
-    description: I2S configuration mode
-    enum: ISCFG
-    name: I2SCFG
-  - bit_offset: 10
-    bit_size: 1
-    description: I2S Enable
-    name: I2SE
-  - bit_offset: 11
-    bit_size: 1
-    description: I2S mode selection
-    enum: ISMOD
-    name: I2SMOD
+    - name: CHLEN
+      description: Channel length (number of bits per audio channel)
+      bit_offset: 0
+      bit_size: 1
+      enum: CHLEN
+    - name: DATLEN
+      description: Data length to be transferred
+      bit_offset: 1
+      bit_size: 2
+      enum: DATLEN
+    - name: CKPOL
+      description: Steady state clock polarity
+      bit_offset: 3
+      bit_size: 1
+      enum: CKPOL
+    - name: I2SSTD
+      description: I2S standard selection
+      bit_offset: 4
+      bit_size: 2
+      enum: ISSTD
+    - name: PCMSYNC
+      description: PCM frame synchronization
+      bit_offset: 7
+      bit_size: 1
+      enum: PCMSYNC
+    - name: I2SCFG
+      description: I2S configuration mode
+      bit_offset: 8
+      bit_size: 2
+      enum: ISCFG
+    - name: I2SE
+      description: I2S Enable
+      bit_offset: 10
+      bit_size: 1
+    - name: I2SMOD
+      description: I2S mode selection
+      bit_offset: 11
+      bit_size: 1
+      enum: ISMOD
 fieldset/I2SPR:
   description: I2S prescaler register
   fields:
-  - bit_offset: 0
-    bit_size: 8
-    description: I2S Linear prescaler
-    name: I2SDIV
-  - bit_offset: 8
-    bit_size: 1
-    description: Odd factor for the prescaler
-    enum: ODD
-    name: ODD
-  - bit_offset: 9
-    bit_size: 1
-    description: Master clock output enable
-    name: MCKOE
+    - name: I2SDIV
+      description: I2S Linear prescaler
+      bit_offset: 0
+      bit_size: 8
+    - name: ODD
+      description: Odd factor for the prescaler
+      bit_offset: 8
+      bit_size: 1
+      enum: ODD
+    - name: MCKOE
+      description: Master clock output enable
+      bit_offset: 9
+      bit_size: 1
 fieldset/RXCRCR:
   description: RX CRC register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Rx CRC register
-    name: RxCRC
+    - name: RxCRC
+      description: Rx CRC register
+      bit_offset: 0
+      bit_size: 16
 fieldset/SR:
   description: status register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Receive buffer not empty
-    name: RXNE
-  - bit_offset: 1
-    bit_size: 1
-    description: Transmit buffer empty
-    name: TXE
-  - bit_offset: 2
-    bit_size: 1
-    description: Channel side
-    enum: CHSIDE
-    name: CHSIDE
-  - bit_offset: 3
-    bit_size: 1
-    description: Underrun flag
-    name: UDR
-  - bit_offset: 4
-    bit_size: 1
-    description: CRC error flag
-    name: CRCERR
-  - bit_offset: 5
-    bit_size: 1
-    description: Mode fault
-    name: MODF
-  - bit_offset: 6
-    bit_size: 1
-    description: Overrun flag
-    enum_read: OVRR
-    name: OVR
-  - bit_offset: 7
-    bit_size: 1
-    description: Busy flag
-    name: BSY
+    - name: RXNE
+      description: Receive buffer not empty
+      bit_offset: 0
+      bit_size: 1
+    - name: TXE
+      description: Transmit buffer empty
+      bit_offset: 1
+      bit_size: 1
+    - name: CHSIDE
+      description: Channel side
+      bit_offset: 2
+      bit_size: 1
+      enum: CHSIDE
+    - name: UDR
+      description: Underrun flag
+      bit_offset: 3
+      bit_size: 1
+    - name: CRCERR
+      description: CRC error flag
+      bit_offset: 4
+      bit_size: 1
+    - name: MODF
+      description: Mode fault
+      bit_offset: 5
+      bit_size: 1
+    - name: OVR
+      description: Overrun flag
+      bit_offset: 6
+      bit_size: 1
+      enum_read: OVRR
+    - name: BSY
+      description: Busy flag
+      bit_offset: 7
+      bit_size: 1
 fieldset/TXCRCR:
   description: TX CRC register
   fields:
-  - bit_offset: 0
-    bit_size: 16
-    description: Tx CRC register
-    name: TxCRC
+    - name: TxCRC
+      description: Tx CRC register
+      bit_offset: 0
+      bit_size: 16
+enum/BIDIMODE:
+  bit_size: 1
+  variants:
+    - name: Unidirectional
+      description: 2-line unidirectional data mode selected
+      value: 0
+    - name: Bidirectional
+      description: 1-line bidirectional data mode selected
+      value: 1
+enum/BIDIOE:
+  bit_size: 1
+  variants:
+    - name: OutputDisabled
+      description: Output disabled (receive-only mode)
+      value: 0
+    - name: OutputEnabled
+      description: Output enabled (transmit-only mode)
+      value: 1
+enum/BR:
+  bit_size: 3
+  variants:
+    - name: Div2
+      description: f_PCLK / 2
+      value: 0
+    - name: Div4
+      description: f_PCLK / 4
+      value: 1
+    - name: Div8
+      description: f_PCLK / 8
+      value: 2
+    - name: Div16
+      description: f_PCLK / 16
+      value: 3
+    - name: Div32
+      description: f_PCLK / 32
+      value: 4
+    - name: Div64
+      description: f_PCLK / 64
+      value: 5
+    - name: Div128
+      description: f_PCLK / 128
+      value: 6
+    - name: Div256
+      description: f_PCLK / 256
+      value: 7
+enum/CHLEN:
+  bit_size: 1
+  variants:
+    - name: SixteenBit
+      description: 16-bit wide
+      value: 0
+    - name: ThirtyTwoBit
+      description: 32-bit wide
+      value: 1
+enum/CHSIDE:
+  bit_size: 1
+  variants:
+    - name: Left
+      description: Channel left has to be transmitted or has been received
+      value: 0
+    - name: Right
+      description: Channel right has to be transmitted or has been received
+      value: 1
+enum/CKPOL:
+  bit_size: 1
+  variants:
+    - name: IdleLow
+      description: I2S clock inactive state is low level
+      value: 0
+    - name: IdleHigh
+      description: I2S clock inactive state is high level
+      value: 1
+enum/CPHA:
+  bit_size: 1
+  variants:
+    - name: FirstEdge
+      description: The first clock transition is the first data capture edge
+      value: 0
+    - name: SecondEdge
+      description: The second clock transition is the first data capture edge
+      value: 1
+enum/CPOL:
+  bit_size: 1
+  variants:
+    - name: IdleLow
+      description: CK to 0 when idle
+      value: 0
+    - name: IdleHigh
+      description: CK to 1 when idle
+      value: 1
+enum/CRCNEXT:
+  bit_size: 1
+  variants:
+    - name: TxBuffer
+      description: Next transmit value is from Tx buffer
+      value: 0
+    - name: CRC
+      description: Next transmit value is from Tx CRC register
+      value: 1
+enum/DATLEN:
+  bit_size: 2
+  variants:
+    - name: SixteenBit
+      description: 16-bit data length
+      value: 0
+    - name: TwentyFourBit
+      description: 24-bit data length
+      value: 1
+    - name: ThirtyTwoBit
+      description: 32-bit data length
+      value: 2
+enum/DFF:
+  bit_size: 1
+  variants:
+    - name: EightBit
+      description: 8-bit data frame format is selected for transmission/reception
+      value: 0
+    - name: SixteenBit
+      description: 16-bit data frame format is selected for transmission/reception
+      value: 1
+enum/ERRIE:
+  bit_size: 1
+  variants:
+    - name: Masked
+      description: Error interrupt masked
+      value: 0
+    - name: NotMasked
+      description: Error interrupt not masked
+      value: 1
+enum/ISCFG:
+  bit_size: 2
+  variants:
+    - name: SlaveTx
+      description: Slave - transmit
+      value: 0
+    - name: SlaveRx
+      description: Slave - receive
+      value: 1
+    - name: MasterTx
+      description: Master - transmit
+      value: 2
+    - name: MasterRx
+      description: Master - receive
+      value: 3
+enum/ISMOD:
+  bit_size: 1
+  variants:
+    - name: SPIMode
+      description: SPI mode is selected
+      value: 0
+    - name: I2SMode
+      description: I2S mode is selected
+      value: 1
+enum/ISSTD:
+  bit_size: 2
+  variants:
+    - name: Philips
+      description: I2S Philips standard
+      value: 0
+    - name: MSB
+      description: MSB justified standard
+      value: 1
+    - name: LSB
+      description: LSB justified standard
+      value: 2
+    - name: PCM
+      description: PCM standard
+      value: 3
+enum/LSBFIRST:
+  bit_size: 1
+  variants:
+    - name: MSBFirst
+      description: Data is transmitted/received with the MSB first
+      value: 0
+    - name: LSBFirst
+      description: Data is transmitted/received with the LSB first
+      value: 1
+enum/MSTR:
+  bit_size: 1
+  variants:
+    - name: Slave
+      description: Slave configuration
+      value: 0
+    - name: Master
+      description: Master configuration
+      value: 1
+enum/ODD:
+  bit_size: 1
+  variants:
+    - name: Even
+      description: Real divider value is I2SDIV * 2
+      value: 0
+    - name: Odd
+      description: Real divider value is (I2SDIV * 2) + 1
+      value: 1
+enum/OVRR:
+  bit_size: 1
+  variants:
+    - name: NoOverrun
+      description: No overrun occurred
+      value: 0
+    - name: Overrun
+      description: Overrun occurred
+      value: 1
+enum/PCMSYNC:
+  bit_size: 1
+  variants:
+    - name: Short
+      description: Short frame synchronisation
+      value: 0
+    - name: Long
+      description: Long frame synchronisation
+      value: 1
+enum/RXONLY:
+  bit_size: 1
+  variants:
+    - name: FullDuplex
+      description: Full duplex (Transmit and receive)
+      value: 0
+    - name: OutputDisabled
+      description: Output disabled (Receive-only mode)
+      value: 1

data/registers/syscfg_f4.yaml

@@ -5,12 +5,10 @@ block/SYSCFG:
     - name: MEMRM
       description: memory remap register
       byte_offset: 0
-      reset_value: 0
       fieldset: MEMRM
     - name: PMC
       description: peripheral mode configuration register
       byte_offset: 4
-      reset_value: 0
       fieldset: PMC
     - name: EXTICR
       description: external interrupt configuration register
@@ -18,12 +16,10 @@ block/SYSCFG:
         len: 4
         stride: 4
       byte_offset: 8
-      reset_value: 0
       fieldset: EXTICR
     - name: CMPCR
       description: Compensation cell control register
       byte_offset: 32
-      reset_value: 0
       access: Read
       fieldset: CMPCR
 fieldset/CMPCR:
@@ -80,4 +76,4 @@ fieldset/PMC:
     - name: MII_RMII_SEL
       description: Ethernet PHY interface selection
       bit_offset: 23
-      bit_size: 1
+      bit_size: 1

data/registers/syscfg_f7.yaml

@@ -2,110 +2,110 @@
 block/SYSCFG:
   description: System configuration controller
   items:
-  - byte_offset: 0
-    description: memory remap register
-    fieldset: MEMRMP
-    name: MEMRMP
-  - byte_offset: 4
-    description: peripheral mode configuration register
-    fieldset: PMC
-    name: PMC
-  - array:
-      len: 4
-      stride: 4
-    byte_offset: 8
-    description: external interrupt configuration register 1
-    fieldset: EXTICR
-    name: EXTICR
-  - access: Read
-    byte_offset: 32
-    description: Compensation cell control register
-    fieldset: CMPCR
-    name: CMPCR
+    - name: MEMRMP
+      description: memory remap register
+      byte_offset: 0
+      fieldset: MEMRMP
+    - name: PMC
+      description: peripheral mode configuration register
+      byte_offset: 4
+      fieldset: PMC
+    - name: EXTICR
+      description: external interrupt configuration register 1
+      array:
+        len: 4
+        stride: 4
+      byte_offset: 8
+      fieldset: EXTICR
+    - name: CMPCR
+      description: Compensation cell control register
+      byte_offset: 32
+      access: Read
+      fieldset: CMPCR
 fieldset/CMPCR:
   description: Compensation cell control register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Compensation cell power-down
-    name: CMP_PD
-  - bit_offset: 8
-    bit_size: 1
-    description: READY
-    name: READY
+    - name: CMP_PD
+      description: Compensation cell power-down
+      bit_offset: 0
+      bit_size: 1
+    - name: READY
+      description: READY
+      bit_offset: 8
+      bit_size: 1
 fieldset/EXTICR:
   description: external interrupt configuration register 1
   fields:
-  - array:
-      len: 4
-      stride: 4
-    bit_offset: 0
-    bit_size: 4
-    description: EXTI x configuration (x = 0 to 3)
-    name: EXTI
+    - name: EXTI
+      description: EXTI x configuration (x = 0 to 3)
+      bit_offset: 0
+      bit_size: 4
+      array:
+        len: 4
+        stride: 4
 fieldset/MEMRMP:
   description: memory remap register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Memory boot mapping
-    name: MEM_BOOT
-  - bit_offset: 8
-    bit_size: 1
-    description: Flash bank mode selection
-    name: FB_MODE
-  - bit_offset: 10
-    bit_size: 2
-    description: FMC memory mapping swap
-    name: SWP_FMC
+    - name: MEM_BOOT
+      description: Memory boot mapping
+      bit_offset: 0
+      bit_size: 1
+    - name: FB_MODE
+      description: Flash bank mode selection
+      bit_offset: 8
+      bit_size: 1
+    - name: SWP_FMC
+      description: FMC memory mapping swap
+      bit_offset: 10
+      bit_size: 2
 fieldset/PMC:
   description: peripheral mode configuration register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: I2C1_FMP I2C1 Fast Mode + Enable
-    name: I2C1_FMP
-  - bit_offset: 1
-    bit_size: 1
-    description: I2C2_FMP I2C2 Fast Mode + Enable
-    name: I2C2_FMP
-  - bit_offset: 2
-    bit_size: 1
-    description: I2C3_FMP I2C3 Fast Mode + Enable
-    name: I2C3_FMP
-  - bit_offset: 3
-    bit_size: 1
-    description: I2C4 Fast Mode + Enable
-    name: I2C4_FMP
-  - bit_offset: 4
-    bit_size: 1
-    description: PB6_FMP Fast Mode
-    name: PB6_FMP
-  - bit_offset: 5
-    bit_size: 1
-    description: PB7_FMP Fast Mode + Enable
-    name: PB7_FMP
-  - bit_offset: 6
-    bit_size: 1
-    description: PB8_FMP Fast Mode + Enable
-    name: PB8_FMP
-  - bit_offset: 7
-    bit_size: 1
-    description: Fast Mode + Enable
-    name: PB9_FMP
-  - bit_offset: 16
-    bit_size: 1
-    description: ADC3DC2
-    name: ADC1DC2
-  - bit_offset: 17
-    bit_size: 1
-    description: ADC2DC2
-    name: ADC2DC2
-  - bit_offset: 18
-    bit_size: 1
-    description: ADC3DC2
-    name: ADC3DC2
-  - bit_offset: 23
-    bit_size: 1
-    description: Ethernet PHY interface selection
-    name: MII_RMII_SEL
+    - name: I2C1_FMP
+      description: I2C1_FMP I2C1 Fast Mode + Enable
+      bit_offset: 0
+      bit_size: 1
+    - name: I2C2_FMP
+      description: I2C2_FMP I2C2 Fast Mode + Enable
+      bit_offset: 1
+      bit_size: 1
+    - name: I2C3_FMP
+      description: I2C3_FMP I2C3 Fast Mode + Enable
+      bit_offset: 2
+      bit_size: 1
+    - name: I2C4_FMP
+      description: I2C4 Fast Mode + Enable
+      bit_offset: 3
+      bit_size: 1
+    - name: PB6_FMP
+      description: PB6_FMP Fast Mode
+      bit_offset: 4
+      bit_size: 1
+    - name: PB7_FMP
+      description: PB7_FMP Fast Mode + Enable
+      bit_offset: 5
+      bit_size: 1
+    - name: PB8_FMP
+      description: PB8_FMP Fast Mode + Enable
+      bit_offset: 6
+      bit_size: 1
+    - name: PB9_FMP
+      description: Fast Mode + Enable
+      bit_offset: 7
+      bit_size: 1
+    - name: ADC1DC2
+      description: ADC3DC2
+      bit_offset: 16
+      bit_size: 1
+    - name: ADC2DC2
+      description: ADC2DC2
+      bit_offset: 17
+      bit_size: 1
+    - name: ADC3DC2
+      description: ADC3DC2
+      bit_offset: 18
+      bit_size: 1
+    - name: MII_RMII_SEL
+      description: Ethernet PHY interface selection
+      bit_offset: 23
+      bit_size: 1

data/registers/timer_v1.yaml

@@ -1,47 +1,72 @@
 ---
+block/TIM_ADV:
+  extends: TIM_GP16
+  description: Advanced-timers
+  items:
+    - name: RCR
+      description: repetition counter register
+      byte_offset: 48
+      fieldset: RCR
+    - name: BDTR
+      description: break and dead-time register
+      byte_offset: 68
+      fieldset: BDTR
+    - name: CCER
+      description: capture/compare enable register
+      byte_offset: 32
+      fieldset: CCER_ADV
+    - name: CR2
+      description: control register 2
+      byte_offset: 4
+      fieldset: CR2_ADV
+    - name: DIER
+      description: DMA/Interrupt enable register
+      byte_offset: 12
+      fieldset: DIER_ADV
+    - name: SR
+      description: status register
+      byte_offset: 16
+      fieldset: SR_ADV
+    - name: EGR
+      description: event generation register
+      byte_offset: 20
+      access: Write
+      fieldset: EGR_ADV
 block/TIM_BASIC:
   description: Basic timer
   items:
     - name: CR1
       description: control register 1
       byte_offset: 0
-      reset_value: 0
       fieldset: CR1_BASIC
     - name: CR2
       description: control register 2
       byte_offset: 4
-      reset_value: 0
       fieldset: CR2_BASIC
     - name: DIER
       description: DMA/Interrupt enable register
       byte_offset: 12
-      reset_value: 0
       fieldset: DIER_BASIC
     - name: SR
       description: status register
       byte_offset: 16
-      reset_value: 0
       fieldset: SR_BASIC
     - name: EGR
       description: event generation register
       byte_offset: 20
-      reset_value: 0
       access: Write
       fieldset: EGR_BASIC
     - name: CNT
       description: counter
       byte_offset: 36
-      reset_value: 0
       fieldset: CNT_16
     - name: PSC
       description: prescaler
       byte_offset: 40
-      reset_value: 0
       fieldset: PSC
     - name: ARR
       description: auto-reload register
       byte_offset: 44
-      reset_value: 0
       fieldset: ARR_16
 block/TIM_GP16:
   extends: TIM_BASIC
@@ -50,32 +75,26 @@ block/TIM_GP16:
     - name: CR1
       description: control register 1
       byte_offset: 0
-      reset_value: 0
       fieldset: CR1_GP
     - name: CR2
       description: control register 2
       byte_offset: 4
-      reset_value: 0
       fieldset: CR2_GP
     - name: SMCR
       description: slave mode control register
       byte_offset: 8
-      reset_value: 0
       fieldset: SMCR
     - name: DIER
       description: DMA/Interrupt enable register
       byte_offset: 12
-      reset_value: 0
       fieldset: DIER_GP
     - name: SR
       description: status register
       byte_offset: 16
-      reset_value: 0
       fieldset: SR_GP
     - name: EGR
       description: event generation register
       byte_offset: 20
-      reset_value: 0
       access: Write
       fieldset: EGR_GP
     - name: CCMR_Input
@@ -84,7 +103,6 @@ block/TIM_GP16:
         len: 2
         stride: 4
       byte_offset: 24
-      reset_value: 0
       fieldset: CCMR_Input
     - name: CCMR_Output
       description: capture/compare mode register 1 (output mode)
@@ -92,27 +110,22 @@ block/TIM_GP16:
         len: 2
         stride: 4
       byte_offset: 24
-      reset_value: 0
       fieldset: CCMR_Output
     - name: CCER
       description: capture/compare enable register
       byte_offset: 32
-      reset_value: 0
       fieldset: CCER_GP
     - name: PSC
       description: prescaler
       byte_offset: 40
-      reset_value: 0
       fieldset: PSC
     - name: DCR
       description: DMA control register
       byte_offset: 72
-      reset_value: 0
       fieldset: DCR
     - name: DMAR
       description: DMA address for full transfer
       byte_offset: 76
-      reset_value: 0
       fieldset: DMAR
     - name: CCR
       description: capture/compare register
@@ -120,7 +133,6 @@ block/TIM_GP16:
         len: 4
         stride: 4
       byte_offset: 52
-      reset_value: 0
       fieldset: CCR_16
 block/TIM_GP32:
   extends: TIM_GP16
@@ -129,12 +141,10 @@ block/TIM_GP32:
     - name: CNT
       description: counter
       byte_offset: 36
-      reset_value: 0
       fieldset: CNT_32
     - name: ARR
       description: auto-reload register
       byte_offset: 44
-      reset_value: 0
       fieldset: ARR_32
     - name: CCR
       description: capture/compare register
@@ -142,55 +152,7 @@ block/TIM_GP32:
         len: 4
         stride: 4
       byte_offset: 52
-      reset_value: 0
       fieldset: CCR_32
-block/TIM_ADV:
-  extends: TIM_GP16
-  description: Advanced-timers
-  items:
-    - name: RCR
-      description: repetition counter register
-      byte_offset: 48
-      reset_value: 0
-      fieldset: RCR
-    - name: BDTR
-      description: break and dead-time register
-      byte_offset: 68
-      reset_value: 0
-      fieldset: BDTR
-    - name: CCER
-      description: capture/compare enable register
-      byte_offset: 32
-      reset_value: 0
-      fieldset: CCER_ADV
-    - name: CR2
-      description: control register 2
-      byte_offset: 4
-      reset_value: 0
-      fieldset: CR2_ADV
-    - name: DIER
-      description: DMA/Interrupt enable register
-      byte_offset: 12
-      reset_value: 0
-      fieldset: DIER_ADV
-    - name: SR
-      description: status register
-      byte_offset: 16
-      reset_value: 0
-      fieldset: SR_ADV
-    - name: EGR
-      description: event generation register
-      byte_offset: 20
-      reset_value: 0
-      access: Write
-      fieldset: EGR_ADV
-fieldset/ARR_32:
-  description: auto-reload register
-  fields:
-    - name: ARR
-      description: Auto-reload value
-      bit_offset: 0
-      bit_size: 32
 fieldset/ARR_16:
   description: auto-reload register
   fields:
@@ -198,34 +160,13 @@ fieldset/ARR_16:
       description: Auto-reload value
       bit_offset: 0
       bit_size: 16
-fieldset/CCR_32:
-  description: capture/compare register 1
+fieldset/ARR_32:
+  description: auto-reload register
   fields:
-    - name: CCR
-      description: Capture/Compare 1 value
+    - name: ARR
+      description: Auto-reload value
       bit_offset: 0
       bit_size: 32
-fieldset/CCR_16:
-  description: capture/compare register 1
-  fields:
-    - name: CCR
-      description: Capture/Compare 1 value
-      bit_offset: 0
-      bit_size: 16
-fieldset/CNT_32:
-  description: counter
-  fields:
-    - name: CNT
-      description: counter value
-      bit_offset: 0
-      bit_size: 32
-fieldset/CNT_16:
-  description: counter
-  fields:
-    - name: CNT
-      description: counter value
-      bit_offset: 0
-      bit_size: 16
 fieldset/BDTR:
   description: break and dead-time register
   fields:
@@ -263,6 +204,17 @@ fieldset/BDTR:
       description: Main output enable
       bit_offset: 15
       bit_size: 1
+fieldset/CCER_ADV:
+  extends: CCER_GP
+  description: capture/compare enable register
+  fields:
+    - name: CCNE
+      description: Capture/Compare 1 complementary output enable
+      bit_offset: 2
+      bit_size: 1
+      array:
+        len: 4
+        stride: 4
 fieldset/CCER_GP:
   description: capture/compare enable register
   fields:
@@ -287,17 +239,6 @@ fieldset/CCER_GP:
       array:
         len: 4
         stride: 4
-fieldset/CCER_ADV:
-  extends: CCER_GP
-  description: capture/compare enable register
-  fields:
-    - name: CCNE
-      description: Capture/Compare 1 complementary output enable
-      bit_offset: 2
-      bit_size: 1
-      array:
-        len: 4
-        stride: 4
 fieldset/CCMR_Input:
   description: capture/compare mode register 1 (input mode)
   fields:
@@ -365,6 +306,34 @@ fieldset/CCMR_Output:
       array:
         len: 2
         stride: 8
+fieldset/CCR_16:
+  description: capture/compare register 1
+  fields:
+    - name: CCR
+      description: Capture/Compare 1 value
+      bit_offset: 0
+      bit_size: 16
+fieldset/CCR_32:
+  description: capture/compare register 1
+  fields:
+    - name: CCR
+      description: Capture/Compare 1 value
+      bit_offset: 0
+      bit_size: 32
+fieldset/CNT_16:
+  description: counter
+  fields:
+    - name: CNT
+      description: counter value
+      bit_offset: 0
+      bit_size: 16
+fieldset/CNT_32:
+  description: counter
+  fields:
+    - name: CNT
+      description: counter value
+      bit_offset: 0
+      bit_size: 32
 fieldset/CR1_BASIC:
   description: control register 1
   fields:
@@ -410,28 +379,6 @@ fieldset/CR1_GP:
       bit_offset: 8
       bit_size: 2
       enum: CKD
-fieldset/CR2_BASIC:
-  description: control register 2
-  fields:
-    - name: MMS
-      description: Master mode selection
-      bit_offset: 4
-      bit_size: 3
-      enum: MMS
-fieldset/CR2_GP:
-  extends: CR2_BASIC
-  description: control register 2
-  fields:
-    - name: CCDS
-      description: Capture/compare DMA selection
-      bit_offset: 3
-      bit_size: 1
-      enum: CCDS
-    - name: TI1S
-      description: TI1 selection
-      bit_offset: 7
-      bit_size: 1
-      enum: TIS
 fieldset/CR2_ADV:
   extends: CR2_GP
   description: control register 2
@@ -463,6 +410,28 @@ fieldset/CR2_ADV:
       description: Output Idle state 3
       bit_offset: 13
       bit_size: 1
+fieldset/CR2_BASIC:
+  description: control register 2
+  fields:
+    - name: MMS
+      description: Master mode selection
+      bit_offset: 4
+      bit_size: 3
+      enum: MMS
+fieldset/CR2_GP:
+  extends: CR2_BASIC
+  description: control register 2
+  fields:
+    - name: CCDS
+      description: Capture/compare DMA selection
+      bit_offset: 3
+      bit_size: 1
+      enum: CCDS
+    - name: TI1S
+      description: TI1 selection
+      bit_offset: 7
+      bit_size: 1
+      enum: TIS
 fieldset/DCR:
   description: DMA control register
   fields:
@@ -474,6 +443,22 @@ fieldset/DCR:
       description: DMA burst length
       bit_offset: 8
       bit_size: 5
+fieldset/DIER_ADV:
+  extends: DIER_GP
+  description: DMA/Interrupt enable register
+  fields:
+    - name: COMIE
+      description: COM interrupt enable
+      bit_offset: 5
+      bit_size: 1
+    - name: BIE
+      description: Break interrupt enable
+      bit_offset: 7
+      bit_size: 1
+    - name: COMDE
+      description: COM DMA request enable
+      bit_offset: 13
+      bit_size: 1
 fieldset/DIER_BASIC:
   description: DMA/Interrupt enable register
   fields:
@@ -511,22 +496,6 @@ fieldset/DIER_GP:
       description: Trigger DMA request enable
       bit_offset: 14
       bit_size: 1
-fieldset/DIER_ADV:
-  extends: DIER_GP
-  description: DMA/Interrupt enable register
-  fields:
-    - name: COMIE
-      description: COM interrupt enable
-      bit_offset: 5
-      bit_size: 1
-    - name: BIE
-      description: Break interrupt enable
-      bit_offset: 7
-      bit_size: 1
-    - name: COMDE
-      description: COM DMA request enable
-      bit_offset: 13
-      bit_size: 1
 fieldset/DMAR:
   description: DMA address for full transfer
   fields:
@@ -534,6 +503,18 @@ fieldset/DMAR:
       description: DMA register for burst accesses
       bit_offset: 0
       bit_size: 16
+fieldset/EGR_ADV:
+  extends: EGR_GP
+  description: event generation register
+  fields:
+    - name: COMG
+      description: Capture/Compare control update generation
+      bit_offset: 5
+      bit_size: 1
+    - name: BG
+      description: Break generation
+      bit_offset: 7
+      bit_size: 1
 fieldset/EGR_BASIC:
   description: event generation register
   fields:
@@ -564,18 +545,6 @@ fieldset/EGR_GP:
       description: Break generation
       bit_offset: 7
       bit_size: 1
-fieldset/EGR_ADV:
-  extends: EGR_GP
-  description: event generation register
-  fields:
-    - name: COMG
-      description: Capture/Compare control update generation
-      bit_offset: 5
-      bit_size: 1
-    - name: BG
-      description: Break generation
-      bit_offset: 7
-      bit_size: 1
 fieldset/PSC:
   description: prescaler
   fields:
@@ -628,6 +597,18 @@ fieldset/SMCR:
       bit_offset: 15
       bit_size: 1
       enum: ETP
+fieldset/SR_ADV:
+  extends: SR_GP
+  description: status register
+  fields:
+    - name: COMIF
+      description: COM interrupt flag
+      bit_offset: 5
+      bit_size: 1
+    - name: BIF
+      description: Break interrupt flag
+      bit_offset: 7
+      bit_size: 1
 fieldset/SR_BASIC:
   description: status register
   fields:
@@ -665,18 +646,6 @@ fieldset/SR_GP:
       array:
         len: 4
         stride: 1
-fieldset/SR_ADV:
-  extends: SR_GP
-  description: status register
-  fields:
-    - name: COMIF
-      description: COM interrupt flag
-      bit_offset: 5
-      bit_size: 1
-    - name: BIF
-      description: Break interrupt flag
-      bit_offset: 7
-      bit_size: 1
 enum/ARPE:
   bit_size: 1
   variants:
@@ -1051,4 +1020,4 @@ enum/URS:
       value: 0
     - name: CounterOnly
       description: Only counter overflow/underflow generates an update interrupt or DMA request
-      value: 1
+      value: 1

data/registers/usart_v1.yaml

@@ -5,32 +5,26 @@ block/UART:
     - name: SR
       description: Status register
       byte_offset: 0
-      reset_value: 192
       fieldset: SR
     - name: DR
       description: Data register
       byte_offset: 4
-      reset_value: 0
       fieldset: DR
     - name: BRR
       description: Baud rate register
       byte_offset: 8
-      reset_value: 0
       fieldset: BRR
     - name: CR1
       description: Control register 1
       byte_offset: 12
-      reset_value: 0
       fieldset: CR1
     - name: CR2
       description: Control register 2
       byte_offset: 16
-      reset_value: 0
       fieldset: CR2
     - name: CR3
       description: Control register 3
       byte_offset: 20
-      reset_value: 0
       fieldset: CR3
 block/USART:
   extends: UART
@@ -39,17 +33,14 @@ block/USART:
     - name: CR2
       description: Control register 2
       byte_offset: 16
-      reset_value: 0
       fieldset: CR2_USART
     - name: CR3
       description: Control register 3
       byte_offset: 20
-      reset_value: 0
       fieldset: CR3_USART
     - name: GTPR
       description: Guard time and prescaler register
       byte_offset: 24
-      reset_value: 0
       fieldset: GTPR
 fieldset/BRR:
   description: Baud rate register
@@ -395,4 +386,4 @@ enum/WAKE:
       value: 0
     - name: AddressMark
       description: USART wakeup on address mark
-      value: 1
+      value: 1

data/registers/usart_v2.yaml

@@ -327,6 +327,13 @@ fieldset/CR3:
       description: Wakeup from Stop mode interrupt enable
       bit_offset: 22
       bit_size: 1
+fieldset/DR:
+  description: Data register
+  fields:
+    - name: DR
+      description: Data value
+      bit_offset: 0
+      bit_size: 9
 fieldset/GTPR:
   description: Guard time and prescaler register
   fields:
@@ -429,13 +436,6 @@ fieldset/IXR:
       description: Receive enable acknowledge flag
       bit_offset: 22
       bit_size: 1
-fieldset/DR:
-  description: Data register
-  fields:
-    - name: DR
-      description: Data value
-      bit_offset: 0
-      bit_size: 9
 fieldset/RQR:
   description: Request register
   fields:
@@ -444,7 +444,7 @@ fieldset/RQR:
       bit_offset: 0
       bit_size: 1
     - name: SBKRQ
-      description: Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
+      description: "Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available"
       bit_offset: 1
       bit_size: 1
     - name: MMRQ
@@ -452,7 +452,7 @@ fieldset/RQR:
       bit_offset: 2
       bit_size: 1
     - name: RXFRQ
-      description: Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
+      description: "Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition"
       bit_offset: 3
       bit_size: 1
     - name: TXFRQ

data/registers/wwdg_v1.yaml

@@ -2,98 +2,98 @@
 block/WWDG:
   description: Window watchdog
   items:
-  - byte_offset: 0
-    description: Control register
-    fieldset: CR
-    name: CR
-  - byte_offset: 4
-    description: Configuration register
-    fieldset: CFR
-    name: CFR
-  - byte_offset: 8
-    description: Status register
-    fieldset: SR
-    name: SR
-enum/EWIFR:
-  bit_size: 1
-  variants:
-  - description: The EWI Interrupt Service Routine has been serviced
-    name: Finished
-    value: 0
-  - description: The EWI Interrupt Service Routine has been triggered
-    name: Pending
-    value: 1
-enum/EWIFW:
-  bit_size: 1
-  variants:
-  - description: The EWI Interrupt Service Routine has been serviced
-    name: Finished
-    value: 0
-enum/EWIW:
-  bit_size: 1
-  variants:
-  - description: interrupt occurs whenever the counter reaches the value 0x40
-    name: Enable
-    value: 1
-enum/WDGA:
-  bit_size: 1
-  variants:
-  - description: Watchdog disabled
-    name: Disabled
-    value: 0
-  - description: Watchdog enabled
-    name: Enabled
-    value: 1
-enum/WDGTB:
-  bit_size: 2
-  variants:
-  - description: Counter clock (PCLK1 div 4096) div 1
-    name: Div1
-    value: 0
-  - description: Counter clock (PCLK1 div 4096) div 2
-    name: Div2
-    value: 1
-  - description: Counter clock (PCLK1 div 4096) div 4
-    name: Div4
-    value: 2
-  - description: Counter clock (PCLK1 div 4096) div 8
-    name: Div8
-    value: 3
+    - name: CR
+      description: Control register
+      byte_offset: 0
+      fieldset: CR
+    - name: CFR
+      description: Configuration register
+      byte_offset: 4
+      fieldset: CFR
+    - name: SR
+      description: Status register
+      byte_offset: 8
+      fieldset: SR
 fieldset/CFR:
   description: Configuration register
   fields:
-  - bit_offset: 0
-    bit_size: 7
-    description: 7-bit window value
-    name: W
-  - bit_offset: 7
-    bit_size: 2
-    description: Timer base
-    enum: WDGTB
-    name: WDGTB
-  - bit_offset: 9
-    bit_size: 1
-    description: Early wakeup interrupt
-    enum_write: EWIW
-    name: EWI
+    - name: W
+      description: 7-bit window value
+      bit_offset: 0
+      bit_size: 7
+    - name: WDGTB
+      description: Timer base
+      bit_offset: 7
+      bit_size: 2
+      enum: WDGTB
+    - name: EWI
+      description: Early wakeup interrupt
+      bit_offset: 9
+      bit_size: 1
+      enum_write: EWIW
 fieldset/CR:
   description: Control register
   fields:
-  - bit_offset: 0
-    bit_size: 7
-    description: 7-bit counter (MSB to LSB)
-    name: T
-  - bit_offset: 7
-    bit_size: 1
-    description: Activation bit
-    enum: WDGA
-    name: WDGA
+    - name: T
+      description: 7-bit counter (MSB to LSB)
+      bit_offset: 0
+      bit_size: 7
+    - name: WDGA
+      description: Activation bit
+      bit_offset: 7
+      bit_size: 1
+      enum: WDGA
 fieldset/SR:
   description: Status register
   fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Early wakeup interrupt flag
-    enum_read: EWIFR
-    enum_write: EWIFW
-    name: EWIF
+    - name: EWIF
+      description: Early wakeup interrupt flag
+      bit_offset: 0
+      bit_size: 1
+      enum_read: EWIFR
+      enum_write: EWIFW
+enum/EWIFR:
+  bit_size: 1
+  variants:
+    - name: Finished
+      description: The EWI Interrupt Service Routine has been serviced
+      value: 0
+    - name: Pending
+      description: The EWI Interrupt Service Routine has been triggered
+      value: 1
+enum/EWIFW:
+  bit_size: 1
+  variants:
+    - name: Finished
+      description: The EWI Interrupt Service Routine has been serviced
+      value: 0
+enum/EWIW:
+  bit_size: 1
+  variants:
+    - name: Enable
+      description: interrupt occurs whenever the counter reaches the value 0x40
+      value: 1
+enum/WDGA:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Watchdog disabled
+      value: 0
+    - name: Enabled
+      description: Watchdog enabled
+      value: 1
+enum/WDGTB:
+  bit_size: 2
+  variants:
+    - name: Div1
+      description: Counter clock (PCLK1 div 4096) div 1
+      value: 0
+    - name: Div2
+      description: Counter clock (PCLK1 div 4096) div 2
+      value: 1
+    - name: Div4
+      description: Counter clock (PCLK1 div 4096) div 4
+      value: 2
+    - name: Div8
+      description: Counter clock (PCLK1 div 4096) div 8
+      value: 3