656 lines
16 KiB
YAML
656 lines
16 KiB
YAML
---
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block/SYSCFG:
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description: System configuration controller
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items:
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- name: CFGR1
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description: SYSCFG configuration register 1
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byte_offset: 0
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fieldset: CFGR1
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- name: CFGR2
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description: SYSCFG configuration register 1
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byte_offset: 24
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fieldset: CFGR2
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- name: VREFBUF_CSR
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description: VREFBUF control and status register
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byte_offset: 48
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fieldset: VREFBUF_CSR
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- name: VREFBUF_CCR
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description: VREFBUF calibration control register
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byte_offset: 52
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fieldset: VREFBUF_CCR
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- name: ITLINE0
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description: interrupt line 0 status register
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byte_offset: 128
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access: Read
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fieldset: ITLINE0
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- name: ITLINE1
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description: interrupt line 1 status register
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byte_offset: 132
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access: Read
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fieldset: ITLINE1
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- name: ITLINE2
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description: interrupt line 2 status register
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byte_offset: 136
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access: Read
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fieldset: ITLINE2
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- name: ITLINE3
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description: interrupt line 3 status register
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byte_offset: 140
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access: Read
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fieldset: ITLINE3
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- name: ITLINE4
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description: interrupt line 4 status register
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byte_offset: 144
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access: Read
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fieldset: ITLINE4
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- name: ITLINE5
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description: interrupt line 5 status register
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byte_offset: 148
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access: Read
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fieldset: ITLINE5
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- name: ITLINE6
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description: interrupt line 6 status register
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byte_offset: 152
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access: Read
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fieldset: ITLINE6
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- name: ITLINE7
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description: interrupt line 7 status register
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byte_offset: 156
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access: Read
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fieldset: ITLINE7
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- name: ITLINE8
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description: interrupt line 8 status register
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byte_offset: 160
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access: Read
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fieldset: ITLINE8
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- name: ITLINE9
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description: interrupt line 9 status register
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byte_offset: 164
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access: Read
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fieldset: ITLINE9
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- name: ITLINE10
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description: interrupt line 10 status register
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byte_offset: 168
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access: Read
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fieldset: ITLINE10
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- name: ITLINE11
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description: interrupt line 11 status register
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byte_offset: 172
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access: Read
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fieldset: ITLINE11
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- name: ITLINE12
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description: interrupt line 12 status register
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byte_offset: 176
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access: Read
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fieldset: ITLINE12
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- name: ITLINE13
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description: interrupt line 13 status register
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byte_offset: 180
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access: Read
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fieldset: ITLINE13
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- name: ITLINE14
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description: interrupt line 14 status register
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byte_offset: 184
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access: Read
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fieldset: ITLINE14
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- name: ITLINE15
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description: interrupt line 15 status register
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byte_offset: 188
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access: Read
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fieldset: ITLINE15
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- name: ITLINE16
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description: interrupt line 16 status register
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byte_offset: 192
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access: Read
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fieldset: ITLINE16
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- name: ITLINE17
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description: interrupt line 17 status register
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byte_offset: 196
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access: Read
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fieldset: ITLINE17
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- name: ITLINE18
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description: interrupt line 18 status register
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byte_offset: 200
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access: Read
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fieldset: ITLINE18
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- name: ITLINE19
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description: interrupt line 19 status register
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byte_offset: 204
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access: Read
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fieldset: ITLINE19
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- name: ITLINE20
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description: interrupt line 20 status register
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byte_offset: 208
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access: Read
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fieldset: ITLINE20
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- name: ITLINE21
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description: interrupt line 21 status register
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byte_offset: 212
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access: Read
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fieldset: ITLINE21
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- name: ITLINE22
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description: interrupt line 22 status register
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byte_offset: 216
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access: Read
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fieldset: ITLINE22
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- name: ITLINE23
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description: interrupt line 23 status register
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byte_offset: 220
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access: Read
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fieldset: ITLINE23
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- name: ITLINE24
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description: interrupt line 24 status register
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byte_offset: 224
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access: Read
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fieldset: ITLINE24
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- name: ITLINE25
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description: interrupt line 25 status register
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byte_offset: 228
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access: Read
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fieldset: ITLINE25
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- name: ITLINE26
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description: interrupt line 26 status register
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byte_offset: 232
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access: Read
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fieldset: ITLINE26
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- name: ITLINE27
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description: interrupt line 27 status register
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byte_offset: 236
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access: Read
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fieldset: ITLINE27
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- name: ITLINE28
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description: interrupt line 28 status register
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byte_offset: 240
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access: Read
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fieldset: ITLINE28
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- name: ITLINE29
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description: interrupt line 29 status register
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byte_offset: 244
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access: Read
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fieldset: ITLINE29
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- name: ITLINE30
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description: interrupt line 30 status register
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byte_offset: 248
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access: Read
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fieldset: ITLINE30
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- name: ITLINE31
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description: interrupt line 31 status register
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byte_offset: 252
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access: Read
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fieldset: ITLINE31
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fieldset/CFGR1:
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description: SYSCFG configuration register 1
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fields:
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- name: MEM_MODE
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description: Memory mapping selection bits
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bit_offset: 0
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bit_size: 2
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- name: PA11_PA12_RMP
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description: PA11 and PA12 remapping bit.
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bit_offset: 4
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bit_size: 1
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- name: IR_POL
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description: IR output polarity selection
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bit_offset: 5
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bit_size: 1
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- name: IR_MOD
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description: IR Modulation Envelope signal selection.
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bit_offset: 6
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bit_size: 2
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- name: BOOSTEN
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description: I/O analog switch voltage booster enable
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bit_offset: 8
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bit_size: 1
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- name: UCPD1_STROBE
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description: Strobe signal bit for UCPD1
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bit_offset: 9
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bit_size: 1
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- name: UCPD2_STROBE
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description: Strobe signal bit for UCPD2
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bit_offset: 10
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bit_size: 1
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- name: I2C_PBx_FMP
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description: Fast Mode Plus (FM+) driving capability activation bits
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bit_offset: 16
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bit_size: 4
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- name: I2C1_FMP
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description: FM+ driving capability activation for I2C1
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bit_offset: 20
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bit_size: 1
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- name: I2C2_FMP
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description: FM+ driving capability activation for I2C2
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bit_offset: 21
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bit_size: 1
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- name: I2C_PAx_FMP
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description: Fast Mode Plus (FM+) driving capability activation bits
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bit_offset: 22
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bit_size: 2
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fieldset/CFGR2:
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description: SYSCFG configuration register 1
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fields:
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- name: LOCKUP_LOCK
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description: Cortex-M0+ LOCKUP bit enable bit
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bit_offset: 0
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bit_size: 1
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- name: SRAM_PARITY_LOCK
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description: SRAM parity lock bit
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bit_offset: 1
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bit_size: 1
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- name: PVD_LOCK
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description: PVD lock enable bit
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bit_offset: 2
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bit_size: 1
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- name: ECC_LOCK
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description: ECC error lock bit
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bit_offset: 3
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bit_size: 1
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- name: SRAM_PEF
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description: SRAM parity error flag
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bit_offset: 8
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bit_size: 1
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- name: PA1_CDEN
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description: PA1_CDEN
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bit_offset: 16
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bit_size: 1
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- name: PA3_CDEN
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description: PA3_CDEN
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bit_offset: 17
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bit_size: 1
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- name: PA5_CDEN
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description: PA5_CDEN
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bit_offset: 18
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bit_size: 1
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- name: PA6_CDEN
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description: PA6_CDEN
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bit_offset: 19
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bit_size: 1
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- name: PA13_CDEN
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description: PA13_CDEN
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bit_offset: 20
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bit_size: 1
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- name: PB0_CDEN
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description: PB0_CDEN
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bit_offset: 21
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bit_size: 1
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- name: PB1_CDEN
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description: PB1_CDEN
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bit_offset: 22
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bit_size: 1
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- name: PB2_CDEN
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description: PB2_CDEN
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bit_offset: 23
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bit_size: 1
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fieldset/ITLINE0:
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description: interrupt line 0 status register
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fields:
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- name: WWDG
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description: Window watchdog interrupt pending flag
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE1:
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description: interrupt line 1 status register
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fields:
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- name: PVDOUT
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description: PVD supply monitoring interrupt request pending (EXTI line 16).
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE10:
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description: interrupt line 10 status register
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fields:
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- name: DMA1_CH2
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description: DMA1_CH1
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bit_offset: 0
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bit_size: 1
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- name: DMA1_CH3
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description: DMA1_CH3
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bit_offset: 1
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bit_size: 1
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fieldset/ITLINE11:
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description: interrupt line 11 status register
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fields:
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- name: DMAMUX
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description: DMAMUX
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bit_offset: 0
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bit_size: 1
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- name: DMA1_CH4
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description: DMA1_CH4
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bit_offset: 1
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bit_size: 1
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- name: DMA1_CH5
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description: DMA1_CH5
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bit_offset: 2
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bit_size: 1
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- name: DMA1_CH6
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description: DMA1_CH6
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bit_offset: 3
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bit_size: 1
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- name: DMA1_CH7
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description: DMA1_CH7
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bit_offset: 4
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bit_size: 1
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fieldset/ITLINE12:
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description: interrupt line 12 status register
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fields:
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- name: ADC
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description: ADC
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bit_offset: 0
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bit_size: 1
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- name: COMP
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description: COMP1
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bit_offset: 1
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bit_size: 1
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array:
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len: 2
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stride: 1
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fieldset/ITLINE13:
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description: interrupt line 13 status register
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fields:
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- name: TIM1_CCU
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description: TIM1_CCU
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bit_offset: 0
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bit_size: 1
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- name: TIM1_TRG
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description: TIM1_TRG
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bit_offset: 1
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bit_size: 1
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- name: TIM1_UPD
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description: TIM1_UPD
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bit_offset: 2
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bit_size: 1
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- name: TIM1_BRK
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description: TIM1_BRK
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bit_offset: 3
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bit_size: 1
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fieldset/ITLINE14:
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description: interrupt line 14 status register
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fields:
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- name: TIM1_CC
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description: TIM1_CC
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE15:
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description: interrupt line 15 status register
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fields:
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- name: TIM
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description: TIM2
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 0
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fieldset/ITLINE16:
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description: interrupt line 16 status register
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fields:
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- name: TIM
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description: TIM3
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 0
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fieldset/ITLINE17:
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description: interrupt line 17 status register
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fields:
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- name: TIM
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description: TIM6
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 0
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- name: DAC
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description: DAC
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bit_offset: 1
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bit_size: 1
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- name: LPTIM
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description: LPTIM1
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bit_offset: 2
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bit_size: 1
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array:
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len: 1
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stride: 0
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fieldset/ITLINE18:
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description: interrupt line 18 status register
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fields:
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- name: TIM
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description: TIM7
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 0
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- name: LPTIM
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description: LPTIM2
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bit_offset: 1
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bit_size: 1
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array:
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len: 1
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stride: 0
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fieldset/ITLINE19:
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description: interrupt line 19 status register
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fields:
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- name: TIM
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description: TIM14
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 0
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fieldset/ITLINE2:
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description: interrupt line 2 status register
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fields:
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- name: TAMP
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description: TAMP
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bit_offset: 0
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bit_size: 1
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- name: RTC
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description: RTC
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bit_offset: 1
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bit_size: 1
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fieldset/ITLINE20:
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description: interrupt line 20 status register
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fields:
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- name: TIM
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description: TIM15
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 0
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fieldset/ITLINE21:
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description: interrupt line 21 status register
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fields:
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- name: TIM
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description: TIM16
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 0
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fieldset/ITLINE22:
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description: interrupt line 22 status register
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fields:
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- name: TIM
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description: TIM17
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 0
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fieldset/ITLINE23:
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description: interrupt line 23 status register
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fields:
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- name: I2C1
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description: I2C1
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE24:
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description: interrupt line 24 status register
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fields:
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- name: I2C2
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description: I2C2
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE25:
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description: interrupt line 25 status register
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fields:
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- name: SPI
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description: SPI1
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 0
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fieldset/ITLINE26:
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description: interrupt line 26 status register
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fields:
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- name: SPI
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description: SPI2
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 0
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fieldset/ITLINE27:
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description: interrupt line 27 status register
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fields:
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- name: USART
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description: USART1
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 0
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fieldset/ITLINE28:
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description: interrupt line 28 status register
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fields:
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- name: USART
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description: USART2
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 0
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fieldset/ITLINE29:
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description: interrupt line 29 status register
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fields:
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- name: USART
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description: USART3
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bit_offset: 0
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bit_size: 1
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array:
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len: 3
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stride: 1
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fieldset/ITLINE3:
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description: interrupt line 3 status register
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fields:
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- name: FLASH_ITF
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description: FLASH_ITF
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bit_offset: 0
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bit_size: 1
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- name: FLASH_ECC
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description: FLASH_ECC
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bit_offset: 1
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bit_size: 1
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fieldset/ITLINE30:
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description: interrupt line 30 status register
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fields:
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- name: USART
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description: CEC
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 0
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fieldset/ITLINE31:
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description: interrupt line 31 status register
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fields:
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- name: RNG
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description: RNG
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bit_offset: 0
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bit_size: 1
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- name: AES
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description: AES
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bit_offset: 1
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bit_size: 1
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fieldset/ITLINE4:
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description: interrupt line 4 status register
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fields:
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- name: RCC
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description: RCC
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE5:
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description: interrupt line 5 status register
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fields:
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- name: EXTI
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description: EXTI0
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 1
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fieldset/ITLINE6:
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description: interrupt line 6 status register
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fields:
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- name: EXTI
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description: EXTI2
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 1
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fieldset/ITLINE7:
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description: interrupt line 7 status register
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fields:
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- name: EXTI
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description: EXTI4
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bit_offset: 0
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bit_size: 1
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array:
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len: 12
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stride: 1
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|
fieldset/ITLINE8:
|
|
description: interrupt line 8 status register
|
|
fields:
|
|
- name: UCPD
|
|
description: UCPD1
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 2
|
|
stride: 1
|
|
fieldset/ITLINE9:
|
|
description: interrupt line 9 status register
|
|
fields:
|
|
- name: DMA1_CH1
|
|
description: DMA1_CH1
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/VREFBUF_CCR:
|
|
description: VREFBUF calibration control register
|
|
fields:
|
|
- name: TRIM
|
|
description: Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.
|
|
bit_offset: 0
|
|
bit_size: 6
|
|
fieldset/VREFBUF_CSR:
|
|
description: VREFBUF control and status register
|
|
fields:
|
|
- name: ENVR
|
|
description: Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HIZ
|
|
description: "High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: VRR
|
|
description: Voltage reference buffer ready
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: VRS
|
|
description: "Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved"
|
|
bit_offset: 4
|
|
bit_size: 3
|