diff --git a/data/registers/adc_g0.yaml b/data/registers/adc_g0.yaml index 4221031..dab4a46 100644 --- a/data/registers/adc_g0.yaml +++ b/data/registers/adc_g0.yaml @@ -615,6 +615,21 @@ fieldset/VERR: description: Major Revision number bit_offset: 4 bit_size: 4 +enum/RES: + bit_size: 2 + variants: + - name: TwelveBit + description: 12-bit resolution + value: 0 + - name: TenBit + description: 10-bit resolution + value: 1 + - name: EightBit + description: 8-bit resolution + value: 2 + - name: SixBit + description: 6-bit resolution + value: 3 enum/SAMPLE_TIME: bit_size: 3 variants: @@ -642,18 +657,3 @@ enum/SAMPLE_TIME: - name: Cycles160_5 description: 160.5 ADC cycles value: 7 -enum/RES: - bit_size: 2 - variants: - - name: TwelveBit - description: 12-bit resolution - value: 0 - - name: TenBit - description: 10-bit resolution - value: 1 - - name: EightBit - description: 8-bit resolution - value: 2 - - name: SixBit - description: 6-bit resolution - value: 3 diff --git a/data/registers/adc_v2.yaml b/data/registers/adc_v2.yaml index 6391a0f..d7e6d2e 100644 --- a/data/registers/adc_v2.yaml +++ b/data/registers/adc_v2.yaml @@ -2,736 +2,736 @@ block/ADC: description: Analog-to-digital converter items: - - byte_offset: 0 - description: status register - fieldset: SR - name: SR - - byte_offset: 4 - description: control register 1 - fieldset: CR1 - name: CR1 - - byte_offset: 8 - description: control register 2 - fieldset: CR2 - name: CR2 - - byte_offset: 12 - description: sample time register 1 - fieldset: SMPR1 - name: SMPR1 - - byte_offset: 16 - description: sample time register 2 - fieldset: SMPR2 - name: SMPR2 - - array: - len: 4 - stride: 4 - byte_offset: 20 - description: injected channel data offset register x - fieldset: JOFR - name: JOFR - - byte_offset: 36 - description: watchdog higher threshold register - fieldset: HTR - name: HTR - - byte_offset: 40 - description: watchdog lower threshold register - fieldset: LTR - name: LTR - - byte_offset: 44 - description: regular sequence register 1 - fieldset: SQR1 - name: SQR1 - - byte_offset: 48 - description: regular sequence register 2 - fieldset: SQR2 - name: SQR2 - - byte_offset: 52 - description: regular sequence register 3 - fieldset: SQR3 - name: SQR3 - - byte_offset: 56 - description: injected sequence register - fieldset: JSQR - name: JSQR - - access: Read - array: - len: 4 - stride: 4 - byte_offset: 60 - description: injected data register x - fieldset: JDR - name: JDR - - access: Read - byte_offset: 76 - description: regular data register - fieldset: DR - name: DR -enum/ADON: - bit_size: 1 - variants: - - description: Disable ADC conversion and go to power down mode - name: Disabled - value: 0 - - description: Enable ADC - name: Enabled - value: 1 -enum/ALIGN: - bit_size: 1 - variants: - - description: Right alignment - name: Right - value: 0 - - description: Left alignment - name: Left - value: 1 -enum/AWD: - bit_size: 1 - variants: - - description: No analog watchdog event occurred - name: NoEvent - value: 0 - - description: Analog watchdog event occurred - name: Event - value: 1 -enum/AWDEN: - bit_size: 1 - variants: - - description: Analog watchdog disabled on regular channels - name: Disabled - value: 0 - - description: Analog watchdog enabled on regular channels - name: Enabled - value: 1 -enum/AWDIE: - bit_size: 1 - variants: - - description: Analogue watchdog interrupt disabled - name: Disabled - value: 0 - - description: Analogue watchdog interrupt enabled - name: Enabled - value: 1 -enum/AWDSGL: - bit_size: 1 - variants: - - description: Analog watchdog enabled on all channels - name: AllChannels - value: 0 - - description: Analog watchdog enabled on a single channel - name: SingleChannel - value: 1 -enum/CONT: - bit_size: 1 - variants: - - description: Single conversion mode - name: Single - value: 0 - - description: Continuous conversion mode - name: Continuous - value: 1 -enum/DDS: - bit_size: 1 - variants: - - description: No new DMA request is issued after the last transfer - name: Single - value: 0 - - description: DMA requests are issued as long as data are converted and DMA=1 - name: Continuous - value: 1 -enum/DISCEN: - bit_size: 1 - variants: - - description: Discontinuous mode on regular channels disabled - name: Disabled - value: 0 - - description: Discontinuous mode on regular channels enabled - name: Enabled - value: 1 -enum/DMA: - bit_size: 1 - variants: - - description: DMA mode disabled - name: Disabled - value: 0 - - description: DMA mode enabled - name: Enabled - value: 1 -enum/EOC: - bit_size: 1 - variants: - - description: Conversion is not complete - name: NotComplete - value: 0 - - description: Conversion complete - name: Complete - value: 1 -enum/EOCIE: - bit_size: 1 - variants: - - description: EOC interrupt disabled - name: Disabled - value: 0 - - description: EOC interrupt enabled - name: Enabled - value: 1 -enum/EOCS: - bit_size: 1 - variants: - - description: The EOC bit is set at the end of each sequence of regular conversions - name: EachSequence - value: 0 - - description: The EOC bit is set at the end of each regular conversion - name: EachConversion - value: 1 -enum/EXTEN: - bit_size: 2 - variants: - - description: Trigger detection disabled - name: Disabled - value: 0 - - description: Trigger detection on the rising edge - name: RisingEdge - value: 1 - - description: Trigger detection on the falling edge - name: FallingEdge - value: 2 - - description: Trigger detection on both the rising and falling edges - name: BothEdges - value: 3 -enum/EXTSEL: - bit_size: 4 - variants: - - description: Timer 1 CC1 event - name: TIM1CC1 - value: 0 - - description: Timer 1 CC2 event - name: TIM1CC2 - value: 1 - - description: Timer 1 CC3 event - name: TIM1CC3 - value: 2 - - description: Timer 2 CC2 event - name: TIM2CC2 - value: 3 - - description: Timer 2 CC3 event - name: TIM2CC3 - value: 4 - - description: Timer 2 CC4 event - name: TIM2CC4 - value: 5 - - description: Timer 2 TRGO event - name: TIM2TRGO - value: 6 -enum/JAUTO: - bit_size: 1 - variants: - - description: Automatic injected group conversion disabled - name: Disabled - value: 0 - - description: Automatic injected group conversion enabled - name: Enabled - value: 1 -enum/JAWDEN: - bit_size: 1 - variants: - - description: Analog watchdog disabled on injected channels - name: Disabled - value: 0 - - description: Analog watchdog enabled on injected channels - name: Enabled - value: 1 -enum/JDISCEN: - bit_size: 1 - variants: - - description: Discontinuous mode on injected channels disabled - name: Disabled - value: 0 - - description: Discontinuous mode on injected channels enabled - name: Enabled - value: 1 -enum/JEOC: - bit_size: 1 - variants: - - description: Conversion is not complete - name: NotComplete - value: 0 - - description: Conversion complete - name: Complete - value: 1 -enum/JEOCIE: - bit_size: 1 - variants: - - description: JEOC interrupt disabled - name: Disabled - value: 0 - - description: JEOC interrupt enabled - name: Enabled - value: 1 -enum/JEXTEN: - bit_size: 2 - variants: - - description: Trigger detection disabled - name: Disabled - value: 0 - - description: Trigger detection on the rising edge - name: RisingEdge - value: 1 - - description: Trigger detection on the falling edge - name: FallingEdge - value: 2 - - description: Trigger detection on both the rising and falling edges - name: BothEdges - value: 3 -enum/JEXTSEL: - bit_size: 4 - variants: - - description: Timer 1 TRGO event - name: TIM1TRGO - value: 0 - - description: Timer 1 CC4 event - name: TIM1CC4 - value: 1 - - description: Timer 2 TRGO event - name: TIM2TRGO - value: 2 - - description: Timer 2 CC1 event - name: TIM2CC1 - value: 3 - - description: Timer 3 CC4 event - name: TIM3CC4 - value: 4 - - description: Timer 4 TRGO event - name: TIM4TRGO - value: 5 - - description: Timer 8 CC4 event - name: TIM8CC4 - value: 7 - - description: Timer 1 TRGO(2) event - name: TIM1TRGO2 - value: 8 - - description: Timer 8 TRGO event - name: TIM8TRGO - value: 9 - - description: Timer 8 TRGO(2) event - name: TIM8TRGO2 - value: 10 - - description: Timer 3 CC3 event - name: TIM3CC3 - value: 11 - - description: Timer 5 TRGO event - name: TIM5TRGO - value: 12 - - description: Timer 3 CC1 event - name: TIM3CC1 - value: 13 - - description: Timer 6 TRGO event - name: TIM6TRGO - value: 14 -enum/JSTRT: - bit_size: 1 - variants: - - description: No injected channel conversion started - name: NotStarted - value: 0 - - description: Injected channel conversion has started - name: Started - value: 1 -enum/JSWSTARTW: - bit_size: 1 - variants: - - description: Starts conversion of injected channels - name: Start - value: 1 -enum/OVR: - bit_size: 1 - variants: - - description: No overrun occurred - name: NoOverrun - value: 0 - - description: Overrun occurred - name: Overrun - value: 1 -enum/OVRIE: - bit_size: 1 - variants: - - description: Overrun interrupt disabled - name: Disabled - value: 0 - - description: Overrun interrupt enabled - name: Enabled - value: 1 -enum/RES: - bit_size: 2 - variants: - - description: 12-bit (15 ADCCLK cycles) - name: TwelveBit - value: 0 - - description: 10-bit (13 ADCCLK cycles) - name: TenBit - value: 1 - - description: 8-bit (11 ADCCLK cycles) - name: EightBit - value: 2 - - description: 6-bit (9 ADCCLK cycles) - name: SixBit - value: 3 -enum/SCAN: - bit_size: 1 - variants: - - description: Scan mode disabled - name: Disabled - value: 0 - - description: Scan mode enabled - name: Enabled - value: 1 -enum/SMP: - bit_size: 3 - variants: - - description: 3 cycles - name: Cycles3 - value: 0 - - description: 15 cycles - name: Cycles15 - value: 1 - - description: 28 cycles - name: Cycles28 - value: 2 - - description: 56 cycles - name: Cycles56 - value: 3 - - description: 84 cycles - name: Cycles84 - value: 4 - - description: 112 cycles - name: Cycles112 - value: 5 - - description: 144 cycles - name: Cycles144 - value: 6 - - description: 480 cycles - name: Cycles480 - value: 7 -enum/SMPR_SMPx_x: - bit_size: 32 - variants: - - description: 3 cycles - name: Cycles3 - value: 0 - - description: 15 cycles - name: Cycles15 - value: 1 - - description: 28 cycles - name: Cycles28 - value: 2 - - description: 56 cycles - name: Cycles56 - value: 3 - - description: 84 cycles - name: Cycles84 - value: 4 - - description: 112 cycles - name: Cycles112 - value: 5 - - description: 144 cycles - name: Cycles144 - value: 6 - - description: 480 cycles - name: Cycles480 - value: 7 -enum/STRT: - bit_size: 1 - variants: - - description: No regular channel conversion started - name: NotStarted - value: 0 - - description: Regular channel conversion has started - name: Started - value: 1 -enum/SWSTARTW: - bit_size: 1 - variants: - - description: Starts conversion of regular channels - name: Start - value: 1 + - name: SR + description: status register + byte_offset: 0 + fieldset: SR + - name: CR1 + description: control register 1 + byte_offset: 4 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 8 + fieldset: CR2 + - name: SMPR1 + description: sample time register 1 + byte_offset: 12 + fieldset: SMPR1 + - name: SMPR2 + description: sample time register 2 + byte_offset: 16 + fieldset: SMPR2 + - name: JOFR + description: injected channel data offset register x + array: + len: 4 + stride: 4 + byte_offset: 20 + fieldset: JOFR + - name: HTR + description: watchdog higher threshold register + byte_offset: 36 + fieldset: HTR + - name: LTR + description: watchdog lower threshold register + byte_offset: 40 + fieldset: LTR + - name: SQR1 + description: regular sequence register 1 + byte_offset: 44 + fieldset: SQR1 + - name: SQR2 + description: regular sequence register 2 + byte_offset: 48 + fieldset: SQR2 + - name: SQR3 + description: regular sequence register 3 + byte_offset: 52 + fieldset: SQR3 + - name: JSQR + description: injected sequence register + byte_offset: 56 + fieldset: JSQR + - name: JDR + description: injected data register x + array: + len: 4 + stride: 4 + byte_offset: 60 + access: Read + fieldset: JDR + - name: DR + description: regular data register + byte_offset: 76 + access: Read + fieldset: DR fieldset/CR1: description: control register 1 fields: - - bit_offset: 0 - bit_size: 5 - description: Analog watchdog channel select bits - name: AWDCH - - bit_offset: 5 - bit_size: 1 - description: Interrupt enable for EOC - enum: EOCIE - name: EOCIE - - bit_offset: 6 - bit_size: 1 - description: Analog watchdog interrupt enable - enum: AWDIE - name: AWDIE - - bit_offset: 7 - bit_size: 1 - description: Interrupt enable for injected channels - enum: JEOCIE - name: JEOCIE - - bit_offset: 8 - bit_size: 1 - description: Scan mode - enum: SCAN - name: SCAN - - bit_offset: 9 - bit_size: 1 - description: Enable the watchdog on a single channel in scan mode - enum: AWDSGL - name: AWDSGL - - bit_offset: 10 - bit_size: 1 - description: Automatic injected group conversion - enum: JAUTO - name: JAUTO - - bit_offset: 11 - bit_size: 1 - description: Discontinuous mode on regular channels - enum: DISCEN - name: DISCEN - - bit_offset: 12 - bit_size: 1 - description: Discontinuous mode on injected channels - enum: JDISCEN - name: JDISCEN - - bit_offset: 13 - bit_size: 3 - description: Discontinuous mode channel count - name: DISCNUM - - bit_offset: 22 - bit_size: 1 - description: Analog watchdog enable on injected channels - enum: JAWDEN - name: JAWDEN - - bit_offset: 23 - bit_size: 1 - description: Analog watchdog enable on regular channels - enum: AWDEN - name: AWDEN - - bit_offset: 24 - bit_size: 2 - description: Resolution - enum: RES - name: RES - - bit_offset: 26 - bit_size: 1 - description: Overrun interrupt enable - enum: OVRIE - name: OVRIE + - name: AWDCH + description: Analog watchdog channel select bits + bit_offset: 0 + bit_size: 5 + - name: EOCIE + description: Interrupt enable for EOC + bit_offset: 5 + bit_size: 1 + enum: EOCIE + - name: AWDIE + description: Analog watchdog interrupt enable + bit_offset: 6 + bit_size: 1 + enum: AWDIE + - name: JEOCIE + description: Interrupt enable for injected channels + bit_offset: 7 + bit_size: 1 + enum: JEOCIE + - name: SCAN + description: Scan mode + bit_offset: 8 + bit_size: 1 + enum: SCAN + - name: AWDSGL + description: Enable the watchdog on a single channel in scan mode + bit_offset: 9 + bit_size: 1 + enum: AWDSGL + - name: JAUTO + description: Automatic injected group conversion + bit_offset: 10 + bit_size: 1 + enum: JAUTO + - name: DISCEN + description: Discontinuous mode on regular channels + bit_offset: 11 + bit_size: 1 + enum: DISCEN + - name: JDISCEN + description: Discontinuous mode on injected channels + bit_offset: 12 + bit_size: 1 + enum: JDISCEN + - name: DISCNUM + description: Discontinuous mode channel count + bit_offset: 13 + bit_size: 3 + - name: JAWDEN + description: Analog watchdog enable on injected channels + bit_offset: 22 + bit_size: 1 + enum: JAWDEN + - name: AWDEN + description: Analog watchdog enable on regular channels + bit_offset: 23 + bit_size: 1 + enum: AWDEN + - name: RES + description: Resolution + bit_offset: 24 + bit_size: 2 + enum: RES + - name: OVRIE + description: Overrun interrupt enable + bit_offset: 26 + bit_size: 1 + enum: OVRIE fieldset/CR2: description: control register 2 fields: - - bit_offset: 0 - bit_size: 1 - description: A/D Converter ON / OFF - enum: ADON - name: ADON - - bit_offset: 1 - bit_size: 1 - description: Continuous conversion - enum: CONT - name: CONT - - bit_offset: 8 - bit_size: 1 - description: Direct memory access mode (for single ADC mode) - enum: DMA - name: DMA - - bit_offset: 9 - bit_size: 1 - description: DMA disable selection (for single ADC mode) - enum: DDS - name: DDS - - bit_offset: 10 - bit_size: 1 - description: End of conversion selection - enum: EOCS - name: EOCS - - bit_offset: 11 - bit_size: 1 - description: Data alignment - enum: ALIGN - name: ALIGN - - bit_offset: 16 - bit_size: 4 - description: External event select for injected group - enum: JEXTSEL - name: JEXTSEL - - bit_offset: 20 - bit_size: 2 - description: External trigger enable for injected channels - enum: JEXTEN - name: JEXTEN - - bit_offset: 22 - bit_size: 1 - description: Start conversion of injected channels - enum_write: JSWSTARTW - name: JSWSTART - - bit_offset: 24 - bit_size: 4 - description: External event select for regular group - enum: EXTSEL - name: EXTSEL - - bit_offset: 28 - bit_size: 2 - description: External trigger enable for regular channels - enum: EXTEN - name: EXTEN - - bit_offset: 30 - bit_size: 1 - description: Start conversion of regular channels - enum_write: SWSTARTW - name: SWSTART + - name: ADON + description: A/D Converter ON / OFF + bit_offset: 0 + bit_size: 1 + enum: ADON + - name: CONT + description: Continuous conversion + bit_offset: 1 + bit_size: 1 + enum: CONT + - name: DMA + description: Direct memory access mode (for single ADC mode) + bit_offset: 8 + bit_size: 1 + enum: DMA + - name: DDS + description: DMA disable selection (for single ADC mode) + bit_offset: 9 + bit_size: 1 + enum: DDS + - name: EOCS + description: End of conversion selection + bit_offset: 10 + bit_size: 1 + enum: EOCS + - name: ALIGN + description: Data alignment + bit_offset: 11 + bit_size: 1 + enum: ALIGN + - name: JEXTSEL + description: External event select for injected group + bit_offset: 16 + bit_size: 4 + enum: JEXTSEL + - name: JEXTEN + description: External trigger enable for injected channels + bit_offset: 20 + bit_size: 2 + enum: JEXTEN + - name: JSWSTART + description: Start conversion of injected channels + bit_offset: 22 + bit_size: 1 + enum_write: JSWSTARTW + - name: EXTSEL + description: External event select for regular group + bit_offset: 24 + bit_size: 4 + enum: EXTSEL + - name: EXTEN + description: External trigger enable for regular channels + bit_offset: 28 + bit_size: 2 + enum: EXTEN + - name: SWSTART + description: Start conversion of regular channels + bit_offset: 30 + bit_size: 1 + enum_write: SWSTARTW fieldset/DR: description: regular data register fields: - - bit_offset: 0 - bit_size: 16 - description: Regular data - name: DATA + - name: DATA + description: Regular data + bit_offset: 0 + bit_size: 16 fieldset/HTR: description: watchdog higher threshold register fields: - - bit_offset: 0 - bit_size: 12 - description: Analog watchdog higher threshold - name: HT + - name: HT + description: Analog watchdog higher threshold + bit_offset: 0 + bit_size: 12 fieldset/JDR: description: injected data register x fields: - - bit_offset: 0 - bit_size: 16 - description: Injected data - name: JDATA + - name: JDATA + description: Injected data + bit_offset: 0 + bit_size: 16 fieldset/JOFR: description: injected channel data offset register x fields: - - bit_offset: 0 - bit_size: 12 - description: Data offset for injected channel x - name: JOFFSET + - name: JOFFSET + description: Data offset for injected channel x + bit_offset: 0 + bit_size: 12 fieldset/JSQR: description: injected sequence register fields: - - array: - len: 4 - stride: 5 - bit_offset: 0 - bit_size: 5 - description: 1st conversion in injected sequence - name: JSQ - - bit_offset: 20 - bit_size: 2 - description: Injected sequence length - name: JL + - name: JSQ + description: 1st conversion in injected sequence + bit_offset: 0 + bit_size: 5 + array: + len: 4 + stride: 5 + - name: JL + description: Injected sequence length + bit_offset: 20 + bit_size: 2 fieldset/LTR: description: watchdog lower threshold register fields: - - bit_offset: 0 - bit_size: 12 - description: Analog watchdog lower threshold - name: LT + - name: LT + description: Analog watchdog lower threshold + bit_offset: 0 + bit_size: 12 fieldset/SMPR1: description: sample time register 1 fields: - - array: - len: 9 - stride: 3 - bit_offset: 0 - bit_size: 3 - description: Channel 10 sampling time selection - enum: SMP - name: SMP - - bit_offset: 0 - bit_size: 32 - description: Sample time bits - enum: SMPR_SMPx_x - name: SMPx_x + - name: SMP + description: Channel 10 sampling time selection + bit_offset: 0 + bit_size: 3 + array: + len: 9 + stride: 3 + enum: SMP + - name: SMPx_x + description: Sample time bits + bit_offset: 0 + bit_size: 32 + enum: SMPR_SMPx_x fieldset/SMPR2: description: sample time register 2 fields: - - array: - len: 10 - stride: 3 - bit_offset: 0 - bit_size: 3 - description: Channel 0 sampling time selection - enum: SMP - name: SMP - - bit_offset: 0 - bit_size: 32 - description: Sample time bits - enum: SMPR_SMPx_x - name: SMPx_x + - name: SMP + description: Channel 0 sampling time selection + bit_offset: 0 + bit_size: 3 + array: + len: 10 + stride: 3 + enum: SMP + - name: SMPx_x + description: Sample time bits + bit_offset: 0 + bit_size: 32 + enum: SMPR_SMPx_x fieldset/SQR1: description: regular sequence register 1 fields: - - array: - len: 4 - stride: 5 - bit_offset: 0 - bit_size: 5 - description: 13th conversion in regular sequence - name: SQ - - bit_offset: 20 - bit_size: 4 - description: Regular channel sequence length - name: L + - name: SQ + description: 13th conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 4 + stride: 5 + - name: L + description: Regular channel sequence length + bit_offset: 20 + bit_size: 4 fieldset/SQR2: description: regular sequence register 2 fields: - - array: - len: 6 - stride: 5 - bit_offset: 0 - bit_size: 5 - description: 7th conversion in regular sequence - name: SQ + - name: SQ + description: 7th conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 6 + stride: 5 fieldset/SQR3: description: regular sequence register 3 fields: - - array: - len: 6 - stride: 5 - bit_offset: 0 - bit_size: 5 - description: 1st conversion in regular sequence - name: SQ + - name: SQ + description: 1st conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 6 + stride: 5 fieldset/SR: description: status register fields: - - bit_offset: 0 - bit_size: 1 - description: Analog watchdog flag - enum: AWD - name: AWD - - bit_offset: 1 - bit_size: 1 - description: Regular channel end of conversion - enum: EOC - name: EOC - - bit_offset: 2 - bit_size: 1 - description: Injected channel end of conversion - enum: JEOC - name: JEOC - - bit_offset: 3 - bit_size: 1 - description: Injected channel start flag - enum: JSTRT - name: JSTRT - - bit_offset: 4 - bit_size: 1 - description: Regular channel start flag - enum: STRT - name: STRT - - bit_offset: 5 - bit_size: 1 - description: Overrun - enum: OVR - name: OVR + - name: AWD + description: Analog watchdog flag + bit_offset: 0 + bit_size: 1 + enum: AWD + - name: EOC + description: Regular channel end of conversion + bit_offset: 1 + bit_size: 1 + enum: EOC + - name: JEOC + description: Injected channel end of conversion + bit_offset: 2 + bit_size: 1 + enum: JEOC + - name: JSTRT + description: Injected channel start flag + bit_offset: 3 + bit_size: 1 + enum: JSTRT + - name: STRT + description: Regular channel start flag + bit_offset: 4 + bit_size: 1 + enum: STRT + - name: OVR + description: Overrun + bit_offset: 5 + bit_size: 1 + enum: OVR +enum/ADON: + bit_size: 1 + variants: + - name: Disabled + description: Disable ADC conversion and go to power down mode + value: 0 + - name: Enabled + description: Enable ADC + value: 1 +enum/ALIGN: + bit_size: 1 + variants: + - name: Right + description: Right alignment + value: 0 + - name: Left + description: Left alignment + value: 1 +enum/AWD: + bit_size: 1 + variants: + - name: NoEvent + description: No analog watchdog event occurred + value: 0 + - name: Event + description: Analog watchdog event occurred + value: 1 +enum/AWDEN: + bit_size: 1 + variants: + - name: Disabled + description: Analog watchdog disabled on regular channels + value: 0 + - name: Enabled + description: Analog watchdog enabled on regular channels + value: 1 +enum/AWDIE: + bit_size: 1 + variants: + - name: Disabled + description: Analogue watchdog interrupt disabled + value: 0 + - name: Enabled + description: Analogue watchdog interrupt enabled + value: 1 +enum/AWDSGL: + bit_size: 1 + variants: + - name: AllChannels + description: Analog watchdog enabled on all channels + value: 0 + - name: SingleChannel + description: Analog watchdog enabled on a single channel + value: 1 +enum/CONT: + bit_size: 1 + variants: + - name: Single + description: Single conversion mode + value: 0 + - name: Continuous + description: Continuous conversion mode + value: 1 +enum/DDS: + bit_size: 1 + variants: + - name: Single + description: No new DMA request is issued after the last transfer + value: 0 + - name: Continuous + description: DMA requests are issued as long as data are converted and DMA=1 + value: 1 +enum/DISCEN: + bit_size: 1 + variants: + - name: Disabled + description: Discontinuous mode on regular channels disabled + value: 0 + - name: Enabled + description: Discontinuous mode on regular channels enabled + value: 1 +enum/DMA: + bit_size: 1 + variants: + - name: Disabled + description: DMA mode disabled + value: 0 + - name: Enabled + description: DMA mode enabled + value: 1 +enum/EOC: + bit_size: 1 + variants: + - name: NotComplete + description: Conversion is not complete + value: 0 + - name: Complete + description: Conversion complete + value: 1 +enum/EOCIE: + bit_size: 1 + variants: + - name: Disabled + description: EOC interrupt disabled + value: 0 + - name: Enabled + description: EOC interrupt enabled + value: 1 +enum/EOCS: + bit_size: 1 + variants: + - name: EachSequence + description: The EOC bit is set at the end of each sequence of regular conversions + value: 0 + - name: EachConversion + description: The EOC bit is set at the end of each regular conversion + value: 1 +enum/EXTEN: + bit_size: 2 + variants: + - name: Disabled + description: Trigger detection disabled + value: 0 + - name: RisingEdge + description: Trigger detection on the rising edge + value: 1 + - name: FallingEdge + description: Trigger detection on the falling edge + value: 2 + - name: BothEdges + description: Trigger detection on both the rising and falling edges + value: 3 +enum/EXTSEL: + bit_size: 4 + variants: + - name: TIM1CC1 + description: Timer 1 CC1 event + value: 0 + - name: TIM1CC2 + description: Timer 1 CC2 event + value: 1 + - name: TIM1CC3 + description: Timer 1 CC3 event + value: 2 + - name: TIM2CC2 + description: Timer 2 CC2 event + value: 3 + - name: TIM2CC3 + description: Timer 2 CC3 event + value: 4 + - name: TIM2CC4 + description: Timer 2 CC4 event + value: 5 + - name: TIM2TRGO + description: Timer 2 TRGO event + value: 6 +enum/JAUTO: + bit_size: 1 + variants: + - name: Disabled + description: Automatic injected group conversion disabled + value: 0 + - name: Enabled + description: Automatic injected group conversion enabled + value: 1 +enum/JAWDEN: + bit_size: 1 + variants: + - name: Disabled + description: Analog watchdog disabled on injected channels + value: 0 + - name: Enabled + description: Analog watchdog enabled on injected channels + value: 1 +enum/JDISCEN: + bit_size: 1 + variants: + - name: Disabled + description: Discontinuous mode on injected channels disabled + value: 0 + - name: Enabled + description: Discontinuous mode on injected channels enabled + value: 1 +enum/JEOC: + bit_size: 1 + variants: + - name: NotComplete + description: Conversion is not complete + value: 0 + - name: Complete + description: Conversion complete + value: 1 +enum/JEOCIE: + bit_size: 1 + variants: + - name: Disabled + description: JEOC interrupt disabled + value: 0 + - name: Enabled + description: JEOC interrupt enabled + value: 1 +enum/JEXTEN: + bit_size: 2 + variants: + - name: Disabled + description: Trigger detection disabled + value: 0 + - name: RisingEdge + description: Trigger detection on the rising edge + value: 1 + - name: FallingEdge + description: Trigger detection on the falling edge + value: 2 + - name: BothEdges + description: Trigger detection on both the rising and falling edges + value: 3 +enum/JEXTSEL: + bit_size: 4 + variants: + - name: TIM1TRGO + description: Timer 1 TRGO event + value: 0 + - name: TIM1CC4 + description: Timer 1 CC4 event + value: 1 + - name: TIM2TRGO + description: Timer 2 TRGO event + value: 2 + - name: TIM2CC1 + description: Timer 2 CC1 event + value: 3 + - name: TIM3CC4 + description: Timer 3 CC4 event + value: 4 + - name: TIM4TRGO + description: Timer 4 TRGO event + value: 5 + - name: TIM8CC4 + description: Timer 8 CC4 event + value: 7 + - name: TIM1TRGO2 + description: Timer 1 TRGO(2) event + value: 8 + - name: TIM8TRGO + description: Timer 8 TRGO event + value: 9 + - name: TIM8TRGO2 + description: Timer 8 TRGO(2) event + value: 10 + - name: TIM3CC3 + description: Timer 3 CC3 event + value: 11 + - name: TIM5TRGO + description: Timer 5 TRGO event + value: 12 + - name: TIM3CC1 + description: Timer 3 CC1 event + value: 13 + - name: TIM6TRGO + description: Timer 6 TRGO event + value: 14 +enum/JSTRT: + bit_size: 1 + variants: + - name: NotStarted + description: No injected channel conversion started + value: 0 + - name: Started + description: Injected channel conversion has started + value: 1 +enum/JSWSTARTW: + bit_size: 1 + variants: + - name: Start + description: Starts conversion of injected channels + value: 1 +enum/OVR: + bit_size: 1 + variants: + - name: NoOverrun + description: No overrun occurred + value: 0 + - name: Overrun + description: Overrun occurred + value: 1 +enum/OVRIE: + bit_size: 1 + variants: + - name: Disabled + description: Overrun interrupt disabled + value: 0 + - name: Enabled + description: Overrun interrupt enabled + value: 1 +enum/RES: + bit_size: 2 + variants: + - name: TwelveBit + description: 12-bit (15 ADCCLK cycles) + value: 0 + - name: TenBit + description: 10-bit (13 ADCCLK cycles) + value: 1 + - name: EightBit + description: 8-bit (11 ADCCLK cycles) + value: 2 + - name: SixBit + description: 6-bit (9 ADCCLK cycles) + value: 3 +enum/SCAN: + bit_size: 1 + variants: + - name: Disabled + description: Scan mode disabled + value: 0 + - name: Enabled + description: Scan mode enabled + value: 1 +enum/SMP: + bit_size: 3 + variants: + - name: Cycles3 + description: 3 cycles + value: 0 + - name: Cycles15 + description: 15 cycles + value: 1 + - name: Cycles28 + description: 28 cycles + value: 2 + - name: Cycles56 + description: 56 cycles + value: 3 + - name: Cycles84 + description: 84 cycles + value: 4 + - name: Cycles112 + description: 112 cycles + value: 5 + - name: Cycles144 + description: 144 cycles + value: 6 + - name: Cycles480 + description: 480 cycles + value: 7 +enum/SMPR_SMPx_x: + bit_size: 32 + variants: + - name: Cycles3 + description: 3 cycles + value: 0 + - name: Cycles15 + description: 15 cycles + value: 1 + - name: Cycles28 + description: 28 cycles + value: 2 + - name: Cycles56 + description: 56 cycles + value: 3 + - name: Cycles84 + description: 84 cycles + value: 4 + - name: Cycles112 + description: 112 cycles + value: 5 + - name: Cycles144 + description: 144 cycles + value: 6 + - name: Cycles480 + description: 480 cycles + value: 7 +enum/STRT: + bit_size: 1 + variants: + - name: NotStarted + description: No regular channel conversion started + value: 0 + - name: Started + description: Regular channel conversion has started + value: 1 +enum/SWSTARTW: + bit_size: 1 + variants: + - name: Start + description: Starts conversion of regular channels + value: 1 diff --git a/data/registers/adc_v3.yaml b/data/registers/adc_v3.yaml index 1b77899..cb7283f 100644 --- a/data/registers/adc_v3.yaml +++ b/data/registers/adc_v3.yaml @@ -521,10 +521,10 @@ fieldset/SMPR1: description: Channel 0 sampling time selection bit_offset: 0 bit_size: 3 - enum: SAMPLE_TIME array: len: 10 stride: 3 + enum: SAMPLE_TIME fieldset/SMPR2: description: sample time register 2 fields: @@ -532,10 +532,10 @@ fieldset/SMPR2: description: Channel 10 sampling time selection bit_offset: 0 bit_size: 3 - enum: SAMPLE_TIME array: len: 9 stride: 3 + enum: SAMPLE_TIME fieldset/SQR1: description: regular sequence register 1 fields: @@ -631,6 +631,21 @@ fieldset/TR3: array: len: 1 stride: 0 +enum/RES: + bit_size: 2 + variants: + - name: TwelveBit + description: 12-bit resolution + value: 0 + - name: TenBit + description: 10-bit resolution + value: 1 + - name: EightBit + description: 8-bit resolution + value: 2 + - name: SixBit + description: 6-bit resolution + value: 3 enum/SAMPLE_TIME: bit_size: 3 variants: @@ -658,18 +673,3 @@ enum/SAMPLE_TIME: - name: Cycles640_5 description: 640.5 ADC cycles value: 7 -enum/RES: - bit_size: 2 - variants: - - name: TwelveBit - description: 12-bit resolution - value: 0 - - name: TenBit - description: 10-bit resolution - value: 1 - - name: EightBit - description: 8-bit resolution - value: 2 - - name: SixBit - description: 6-bit resolution - value: 3 diff --git a/data/registers/adccommon_v2.yaml b/data/registers/adccommon_v2.yaml index 512e946..037ade7 100644 --- a/data/registers/adccommon_v2.yaml +++ b/data/registers/adccommon_v2.yaml @@ -2,271 +2,268 @@ block/ADC_COMMON: description: ADC common registers items: - - access: Read - byte_offset: 0 - description: ADC Common status register - fieldset: CSR - name: CSR - - byte_offset: 4 - description: ADC common control register - fieldset: CCR - name: CCR - - access: Read - byte_offset: 8 - description: ADC common regular data register for dual and triple modes - fieldset: CDR - name: CDR -enum/ADCPRE: - bit_size: 2 - variants: - - description: PCLK2 divided by 2 - name: Div2 - value: 0 - - description: PCLK2 divided by 4 - name: Div4 - value: 1 - - description: PCLK2 divided by 6 - name: Div6 - value: 2 - - description: PCLK2 divided by 8 - name: Div8 - value: 3 -enum/AWD: - bit_size: 1 - variants: - - description: No analog watchdog event occurred - name: NoEvent - value: 0 - - description: Analog watchdog event occurred - name: Event - value: 1 -enum/DDS: - bit_size: 1 - variants: - - description: No new DMA request is issued after the last transfer - name: Single - value: 0 - - description: DMA requests are issued as long as data are converted and DMA=01, - 10 or 11 - name: Continuous - value: 1 -enum/DMA: - bit_size: 2 - variants: - - description: DMA mode disabled - name: Disabled - value: 0 - - description: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3) - name: Mode1 - value: 1 - - description: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then - 3&2) - name: Mode2 - value: 2 - - description: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then - 3&2) - name: Mode3 - value: 3 -enum/EOC: - bit_size: 1 - variants: - - description: Conversion is not complete - name: NotComplete - value: 0 - - description: Conversion complete - name: Complete - value: 1 -enum/JEOC: - bit_size: 1 - variants: - - description: Conversion is not complete - name: NotComplete - value: 0 - - description: Conversion complete - name: Complete - value: 1 -enum/JSTRT: - bit_size: 1 - variants: - - description: No injected channel conversion started - name: NotStarted - value: 0 - - description: Injected channel conversion has started - name: Started - value: 1 -enum/MULTI: - bit_size: 5 - variants: - - description: 'All the ADCs independent: independent mode' - name: Independent - value: 0 - - description: Dual ADC1 and ADC2, combined regular and injected simultaneous mode - name: DualRJ - value: 1 - - description: Dual ADC1 and ADC2, combined regular and alternate trigger mode - name: DualRA - value: 2 - - description: Dual ADC1 and ADC2, injected simultaneous mode only - name: DualJ - value: 5 - - description: Dual ADC1 and ADC2, regular simultaneous mode only - name: DualR - value: 6 - - description: Dual ADC1 and ADC2, interleaved mode only - name: DualI - value: 7 - - description: Dual ADC1 and ADC2, alternate trigger mode only - name: DualA - value: 9 - - description: Triple ADC, regular and injected simultaneous mode - name: TripleRJ - value: 17 - - description: Triple ADC, regular and alternate trigger mode - name: TripleRA - value: 18 - - description: Triple ADC, injected simultaneous mode only - name: TripleJ - value: 21 - - description: Triple ADC, regular simultaneous mode only - name: TripleR - value: 22 - - description: Triple ADC, interleaved mode only - name: TripleI - value: 23 - - description: Triple ADC, alternate trigger mode only - name: TripleA - value: 24 -enum/OVR: - bit_size: 1 - variants: - - description: No overrun occurred - name: NoOverrun - value: 0 - - description: Overrun occurred - name: Overrun - value: 1 -enum/STRT: - bit_size: 1 - variants: - - description: No regular channel conversion started - name: NotStarted - value: 0 - - description: Regular channel conversion has started - name: Started - value: 1 -enum/TSVREFE: - bit_size: 1 - variants: - - description: Temperature sensor and V_REFINT channel disabled - name: Disabled - value: 0 - - description: Temperature sensor and V_REFINT channel enabled - name: Enabled - value: 1 -enum/VBATE: - bit_size: 1 - variants: - - description: V_BAT channel disabled - name: Disabled - value: 0 - - description: V_BAT channel enabled - name: Enabled - value: 1 + - name: CSR + description: ADC Common status register + byte_offset: 0 + access: Read + fieldset: CSR + - name: CCR + description: ADC common control register + byte_offset: 4 + fieldset: CCR + - name: CDR + description: ADC common regular data register for dual and triple modes + byte_offset: 8 + access: Read + fieldset: CDR fieldset/CCR: description: ADC common control register fields: - - bit_offset: 0 - bit_size: 5 - description: Multi ADC mode selection - enum: MULTI - name: MULTI - - bit_offset: 8 - bit_size: 4 - description: Delay between 2 sampling phases - name: DELAY - - bit_offset: 13 - bit_size: 1 - description: DMA disable selection for multi-ADC mode - enum: DDS - name: DDS - - bit_offset: 14 - bit_size: 2 - description: Direct memory access mode for multi ADC mode - enum: DMA - name: DMA - - bit_offset: 16 - bit_size: 2 - description: ADC prescaler - enum: ADCPRE - name: ADCPRE - - bit_offset: 22 - bit_size: 1 - description: VBAT enable - enum: VBATE - name: VBATE - - bit_offset: 23 - bit_size: 1 - description: Temperature sensor and VREFINT enable - enum: TSVREFE - name: TSVREFE + - name: MULTI + description: Multi ADC mode selection + bit_offset: 0 + bit_size: 5 + enum: MULTI + - name: DELAY + description: Delay between 2 sampling phases + bit_offset: 8 + bit_size: 4 + - name: DDS + description: DMA disable selection for multi-ADC mode + bit_offset: 13 + bit_size: 1 + enum: DDS + - name: DMA + description: Direct memory access mode for multi ADC mode + bit_offset: 14 + bit_size: 2 + enum: DMA + - name: ADCPRE + description: ADC prescaler + bit_offset: 16 + bit_size: 2 + enum: ADCPRE + - name: VBATE + description: VBAT enable + bit_offset: 22 + bit_size: 1 + enum: VBATE + - name: TSVREFE + description: Temperature sensor and VREFINT enable + bit_offset: 23 + bit_size: 1 + enum: TSVREFE fieldset/CDR: description: ADC common regular data register for dual and triple modes fields: - - array: - len: 2 - stride: 16 - bit_offset: 0 - bit_size: 16 - description: 1st data item of a pair of regular conversions - name: DATA + - name: DATA + description: 1st data item of a pair of regular conversions + bit_offset: 0 + bit_size: 16 + array: + len: 2 + stride: 16 fieldset/CSR: description: ADC common status register fields: - - array: - len: 3 - stride: 8 - bit_offset: 0 - bit_size: 1 - description: Analog watchdog flag of ADC 1 - enum: AWD - name: AWD - - array: - len: 3 - stride: 8 - bit_offset: 1 - bit_size: 1 - description: End of conversion of ADC 1 - enum: EOC - name: EOC - - array: - len: 3 - stride: 8 - bit_offset: 2 - bit_size: 1 - description: Injected channel end of conversion of ADC 1 - enum: JEOC - name: JEOC - - array: - len: 3 - stride: 8 - bit_offset: 3 - bit_size: 1 - description: Injected channel Start flag of ADC 1 - enum: JSTRT - name: JSTRT - - array: - len: 3 - stride: 8 - bit_offset: 4 - bit_size: 1 - description: Regular channel Start flag of ADC 1 - enum: STRT - name: STRT - - array: - len: 3 - stride: 8 - bit_offset: 5 - bit_size: 1 - description: Overrun flag of ADC 1 - enum: OVR - name: OVR + - name: AWD + description: Analog watchdog flag of ADC 1 + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 8 + enum: AWD + - name: EOC + description: End of conversion of ADC 1 + bit_offset: 1 + bit_size: 1 + array: + len: 3 + stride: 8 + enum: EOC + - name: JEOC + description: Injected channel end of conversion of ADC 1 + bit_offset: 2 + bit_size: 1 + array: + len: 3 + stride: 8 + enum: JEOC + - name: JSTRT + description: Injected channel Start flag of ADC 1 + bit_offset: 3 + bit_size: 1 + array: + len: 3 + stride: 8 + enum: JSTRT + - name: STRT + description: Regular channel Start flag of ADC 1 + bit_offset: 4 + bit_size: 1 + array: + len: 3 + stride: 8 + enum: STRT + - name: OVR + description: Overrun flag of ADC 1 + bit_offset: 5 + bit_size: 1 + array: + len: 3 + stride: 8 + enum: OVR +enum/ADCPRE: + bit_size: 2 + variants: + - name: Div2 + description: PCLK2 divided by 2 + value: 0 + - name: Div4 + description: PCLK2 divided by 4 + value: 1 + - name: Div6 + description: PCLK2 divided by 6 + value: 2 + - name: Div8 + description: PCLK2 divided by 8 + value: 3 +enum/AWD: + bit_size: 1 + variants: + - name: NoEvent + description: No analog watchdog event occurred + value: 0 + - name: Event + description: Analog watchdog event occurred + value: 1 +enum/DDS: + bit_size: 1 + variants: + - name: Single + description: No new DMA request is issued after the last transfer + value: 0 + - name: Continuous + description: "DMA requests are issued as long as data are converted and DMA=01, 10 or 11" + value: 1 +enum/DMA: + bit_size: 2 + variants: + - name: Disabled + description: DMA mode disabled + value: 0 + - name: Mode1 + description: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3) + value: 1 + - name: Mode2 + description: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) + value: 2 + - name: Mode3 + description: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) + value: 3 +enum/EOC: + bit_size: 1 + variants: + - name: NotComplete + description: Conversion is not complete + value: 0 + - name: Complete + description: Conversion complete + value: 1 +enum/JEOC: + bit_size: 1 + variants: + - name: NotComplete + description: Conversion is not complete + value: 0 + - name: Complete + description: Conversion complete + value: 1 +enum/JSTRT: + bit_size: 1 + variants: + - name: NotStarted + description: No injected channel conversion started + value: 0 + - name: Started + description: Injected channel conversion has started + value: 1 +enum/MULTI: + bit_size: 5 + variants: + - name: Independent + description: "All the ADCs independent: independent mode" + value: 0 + - name: DualRJ + description: "Dual ADC1 and ADC2, combined regular and injected simultaneous mode" + value: 1 + - name: DualRA + description: "Dual ADC1 and ADC2, combined regular and alternate trigger mode" + value: 2 + - name: DualJ + description: "Dual ADC1 and ADC2, injected simultaneous mode only" + value: 5 + - name: DualR + description: "Dual ADC1 and ADC2, regular simultaneous mode only" + value: 6 + - name: DualI + description: "Dual ADC1 and ADC2, interleaved mode only" + value: 7 + - name: DualA + description: "Dual ADC1 and ADC2, alternate trigger mode only" + value: 9 + - name: TripleRJ + description: "Triple ADC, regular and injected simultaneous mode" + value: 17 + - name: TripleRA + description: "Triple ADC, regular and alternate trigger mode" + value: 18 + - name: TripleJ + description: "Triple ADC, injected simultaneous mode only" + value: 21 + - name: TripleR + description: "Triple ADC, regular simultaneous mode only" + value: 22 + - name: TripleI + description: "Triple ADC, interleaved mode only" + value: 23 + - name: TripleA + description: "Triple ADC, alternate trigger mode only" + value: 24 +enum/OVR: + bit_size: 1 + variants: + - name: NoOverrun + description: No overrun occurred + value: 0 + - name: Overrun + description: Overrun occurred + value: 1 +enum/STRT: + bit_size: 1 + variants: + - name: NotStarted + description: No regular channel conversion started + value: 0 + - name: Started + description: Regular channel conversion has started + value: 1 +enum/TSVREFE: + bit_size: 1 + variants: + - name: Disabled + description: Temperature sensor and V_REFINT channel disabled + value: 0 + - name: Enabled + description: Temperature sensor and V_REFINT channel enabled + value: 1 +enum/VBATE: + bit_size: 1 + variants: + - name: Disabled + description: V_BAT channel disabled + value: 0 + - name: Enabled + description: V_BAT channel enabled + value: 1 diff --git a/data/registers/afio_f1.yaml b/data/registers/afio_f1.yaml index 6facdf7..e804f23 100644 --- a/data/registers/afio_f1.yaml +++ b/data/registers/afio_f1.yaml @@ -1,205 +1,206 @@ +--- block/AFIO: description: Alternate function I/O items: - - byte_offset: 0 - description: Event Control Register (AFIO_EVCR) - fieldset: EVCR - name: EVCR - - byte_offset: 4 - description: AF remap and debug I/O configuration register (AFIO_MAPR) - fieldset: MAPR - name: MAPR - - array: - len: 4 - stride: 4 - byte_offset: 8 - description: External interrupt configuration register 1 (AFIO_EXTICR1) - fieldset: EXTICR - name: EXTICR - - byte_offset: 28 - description: AF remap and debug I/O configuration register - fieldset: MAPR2 - name: MAPR2 + - name: EVCR + description: Event Control Register (AFIO_EVCR) + byte_offset: 0 + fieldset: EVCR + - name: MAPR + description: AF remap and debug I/O configuration register (AFIO_MAPR) + byte_offset: 4 + fieldset: MAPR + - name: EXTICR + description: External interrupt configuration register 1 (AFIO_EXTICR1) + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: MAPR2 + description: AF remap and debug I/O configuration register + byte_offset: 28 + fieldset: MAPR2 fieldset/EVCR: description: Event Control Register (AFIO_EVCR) fields: - - bit_offset: 0 - bit_size: 4 - description: Pin selection - name: PIN - - bit_offset: 4 - bit_size: 3 - description: Port selection - name: PORT - - bit_offset: 7 - bit_size: 1 - description: Event Output Enable - name: EVOE + - name: PIN + description: Pin selection + bit_offset: 0 + bit_size: 4 + - name: PORT + description: Port selection + bit_offset: 4 + bit_size: 3 + - name: EVOE + description: Event Output Enable + bit_offset: 7 + bit_size: 1 fieldset/EXTICR: description: External interrupt configuration register 3 (AFIO_EXTICR3) fields: - - array: - len: 4 - stride: 4 - bit_offset: 0 - bit_size: 4 - description: EXTI12 configuration - name: EXTI + - name: EXTI + description: EXTI12 configuration + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 fieldset/MAPR: description: AF remap and debug I/O configuration register (AFIO_MAPR) fields: - - bit_offset: 0 - bit_size: 1 - description: SPI1 remapping - name: SPI1_REMAP - - bit_offset: 1 - bit_size: 1 - description: I2C1 remapping - name: I2C1_REMAP - - bit_offset: 2 - bit_size: 1 - description: USART1 remapping - name: USART1_REMAP - - bit_offset: 3 - bit_size: 1 - description: USART2 remapping - name: USART2_REMAP - - bit_offset: 4 - bit_size: 2 - description: USART3 remapping - name: USART3_REMAP - - bit_offset: 6 - bit_size: 2 - description: TIM1 remapping - name: TIM1_REMAP - - bit_offset: 8 - bit_size: 2 - description: TIM2 remapping - name: TIM2_REMAP - - bit_offset: 10 - bit_size: 2 - description: TIM3 remapping - name: TIM3_REMAP - - bit_offset: 12 - bit_size: 1 - description: TIM4 remapping - name: TIM4_REMAP - - bit_offset: 13 - bit_size: 2 - description: CAN1 remapping - name: CAN_REMAP - - bit_offset: 13 - bit_size: 2 - description: CAN1 remapping - name: CAN1_REMAP - - bit_offset: 15 - bit_size: 1 - description: Port D0/Port D1 mapping on OSCIN/OSCOUT - name: PD01_REMAP - - bit_offset: 16 - bit_size: 1 - description: Set and cleared by software - name: TIM5CH4_IREMAP - - bit_offset: 17 - bit_size: 1 - description: ADC 1 External trigger injected conversion remapping - name: ADC1_ETRGINJ_REMAP - - bit_offset: 18 - bit_size: 1 - description: ADC 1 external trigger regular conversion remapping - name: ADC1_ETRGREG_REMAP - - bit_offset: 19 - bit_size: 1 - description: ADC 2 external trigger injected conversion remapping - name: ADC2_ETRGINJ_REMAP - - bit_offset: 20 - bit_size: 1 - description: ADC 2 external trigger regular conversion remapping - name: ADC2_ETRGREG_REMAP - - bit_offset: 21 - bit_size: 1 - description: Ethernet MAC I/O remapping - name: ETH_REMAP - - bit_offset: 22 - bit_size: 1 - description: CAN2 I/O remapping - name: CAN2_REMAP - - bit_offset: 23 - bit_size: 1 - description: MII or RMII selection - name: MII_RMII_SEL - - bit_offset: 24 - bit_size: 3 - description: Serial wire JTAG configuration - name: SWJ_CFG - - bit_offset: 28 - bit_size: 1 - description: SPI3/I2S3 remapping - name: SPI3_REMAP - - bit_offset: 29 - bit_size: 1 - description: TIM2 internal trigger 1 remapping - name: TIM2ITR1_IREMAP - - bit_offset: 30 - bit_size: 1 - description: Ethernet PTP PPS remapping - name: PTP_PPS_REMAP + - name: SPI1_REMAP + description: SPI1 remapping + bit_offset: 0 + bit_size: 1 + - name: I2C1_REMAP + description: I2C1 remapping + bit_offset: 1 + bit_size: 1 + - name: USART1_REMAP + description: USART1 remapping + bit_offset: 2 + bit_size: 1 + - name: USART2_REMAP + description: USART2 remapping + bit_offset: 3 + bit_size: 1 + - name: USART3_REMAP + description: USART3 remapping + bit_offset: 4 + bit_size: 2 + - name: TIM1_REMAP + description: TIM1 remapping + bit_offset: 6 + bit_size: 2 + - name: TIM2_REMAP + description: TIM2 remapping + bit_offset: 8 + bit_size: 2 + - name: TIM3_REMAP + description: TIM3 remapping + bit_offset: 10 + bit_size: 2 + - name: TIM4_REMAP + description: TIM4 remapping + bit_offset: 12 + bit_size: 1 + - name: CAN_REMAP + description: CAN1 remapping + bit_offset: 13 + bit_size: 2 + - name: CAN1_REMAP + description: CAN1 remapping + bit_offset: 13 + bit_size: 2 + - name: PD01_REMAP + description: Port D0/Port D1 mapping on OSCIN/OSCOUT + bit_offset: 15 + bit_size: 1 + - name: TIM5CH4_IREMAP + description: Set and cleared by software + bit_offset: 16 + bit_size: 1 + - name: ADC1_ETRGINJ_REMAP + description: ADC 1 External trigger injected conversion remapping + bit_offset: 17 + bit_size: 1 + - name: ADC1_ETRGREG_REMAP + description: ADC 1 external trigger regular conversion remapping + bit_offset: 18 + bit_size: 1 + - name: ADC2_ETRGINJ_REMAP + description: ADC 2 external trigger injected conversion remapping + bit_offset: 19 + bit_size: 1 + - name: ADC2_ETRGREG_REMAP + description: ADC 2 external trigger regular conversion remapping + bit_offset: 20 + bit_size: 1 + - name: ETH_REMAP + description: Ethernet MAC I/O remapping + bit_offset: 21 + bit_size: 1 + - name: CAN2_REMAP + description: CAN2 I/O remapping + bit_offset: 22 + bit_size: 1 + - name: MII_RMII_SEL + description: MII or RMII selection + bit_offset: 23 + bit_size: 1 + - name: SWJ_CFG + description: Serial wire JTAG configuration + bit_offset: 24 + bit_size: 3 + - name: SPI3_REMAP + description: SPI3/I2S3 remapping + bit_offset: 28 + bit_size: 1 + - name: TIM2ITR1_IREMAP + description: TIM2 internal trigger 1 remapping + bit_offset: 29 + bit_size: 1 + - name: PTP_PPS_REMAP + description: Ethernet PTP PPS remapping + bit_offset: 30 + bit_size: 1 fieldset/MAPR2: description: AF remap and debug I/O configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM15 remapping - name: TIM15_REMAP - - bit_offset: 1 - bit_size: 1 - description: TIM16 remapping - name: TIM16_REMAP - - bit_offset: 2 - bit_size: 1 - description: TIM17 remapping - name: TIM17_REMAP - - bit_offset: 3 - bit_size: 1 - description: CEC remapping - name: CEC_REMAP - - bit_offset: 4 - bit_size: 1 - description: TIM1 DMA remapping - name: TIM1_DMA_REMAP - - bit_offset: 5 - bit_size: 1 - description: TIM9 remapping - name: TIM9_REMAP - - bit_offset: 6 - bit_size: 1 - description: TIM10 remapping - name: TIM10_REMAP - - bit_offset: 7 - bit_size: 1 - description: TIM11 remapping - name: TIM11_REMAP - - bit_offset: 8 - bit_size: 1 - description: TIM13 remapping - name: TIM13_REMAP - - bit_offset: 9 - bit_size: 1 - description: TIM14 remapping - name: TIM14_REMAP - - bit_offset: 10 - bit_size: 1 - description: NADV connect/disconnect - name: FSMC_NADV - - bit_offset: 11 - bit_size: 1 - description: TIM67_DAC DMA remapping - name: TIM67_DAC_DMA_REMAP - - bit_offset: 12 - bit_size: 1 - description: TIM12 remapping - name: TIM12_REMAP - - bit_offset: 13 - bit_size: 1 - description: Miscellaneous features remapping - name: MISC_REMAP + - name: TIM15_REMAP + description: TIM15 remapping + bit_offset: 0 + bit_size: 1 + - name: TIM16_REMAP + description: TIM16 remapping + bit_offset: 1 + bit_size: 1 + - name: TIM17_REMAP + description: TIM17 remapping + bit_offset: 2 + bit_size: 1 + - name: CEC_REMAP + description: CEC remapping + bit_offset: 3 + bit_size: 1 + - name: TIM1_DMA_REMAP + description: TIM1 DMA remapping + bit_offset: 4 + bit_size: 1 + - name: TIM9_REMAP + description: TIM9 remapping + bit_offset: 5 + bit_size: 1 + - name: TIM10_REMAP + description: TIM10 remapping + bit_offset: 6 + bit_size: 1 + - name: TIM11_REMAP + description: TIM11 remapping + bit_offset: 7 + bit_size: 1 + - name: TIM13_REMAP + description: TIM13 remapping + bit_offset: 8 + bit_size: 1 + - name: TIM14_REMAP + description: TIM14 remapping + bit_offset: 9 + bit_size: 1 + - name: FSMC_NADV + description: NADV connect/disconnect + bit_offset: 10 + bit_size: 1 + - name: TIM67_DAC_DMA_REMAP + description: TIM67_DAC DMA remapping + bit_offset: 11 + bit_size: 1 + - name: TIM12_REMAP + description: TIM12 remapping + bit_offset: 12 + bit_size: 1 + - name: MISC_REMAP + description: Miscellaneous features remapping + bit_offset: 13 + bit_size: 1 diff --git a/data/registers/bdma_v1.yaml b/data/registers/bdma_v1.yaml index 224d1ec..bf19cd5 100644 --- a/data/registers/bdma_v1.yaml +++ b/data/registers/bdma_v1.yaml @@ -1,17 +1,32 @@ --- +block/CH: + description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" + items: + - name: CR + description: DMA channel configuration register (DMA_CCR) + byte_offset: 0 + fieldset: CR + - name: NDTR + description: DMA channel 1 number of data register + byte_offset: 4 + fieldset: NDTR + - name: PAR + description: DMA channel 1 peripheral address register + byte_offset: 8 + - name: MAR + description: DMA channel 1 memory address register + byte_offset: 12 block/DMA: description: DMA controller items: - name: ISR description: DMA interrupt status register (DMA_ISR) byte_offset: 0 - reset_value: 0 access: Read fieldset: ISR - name: IFCR description: DMA interrupt flag clear register (DMA_IFCR) byte_offset: 4 - reset_value: 0 access: Write fieldset: ISR - name: CH @@ -21,27 +36,6 @@ block/DMA: stride: 20 byte_offset: 8 block: CH -block/CH: - description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" - items: - - name: CR - description: DMA channel configuration register (DMA_CCR) - byte_offset: 0 - reset_value: 0 - fieldset: CR - - name: NDTR - description: DMA channel 1 number of data register - byte_offset: 4 - reset_value: 0 - fieldset: NDTR - - name: PAR - description: DMA channel 1 peripheral address register - byte_offset: 8 - reset_value: 0 - - name: MAR - description: DMA channel 1 memory address register - byte_offset: 12 - reset_value: 0 fieldset/CR: description: DMA channel configuration register (DMA_CCR) fields: @@ -157,15 +151,6 @@ enum/DIR: - name: FromMemory description: Read from memory value: 1 -enum/MEMMEM: - bit_size: 1 - variants: - - name: Disabled - description: Memory to memory mode disabled - value: 0 - - name: Enabled - description: Memory to memory mode enabled - value: 1 enum/INC: bit_size: 1 variants: @@ -175,6 +160,15 @@ enum/INC: - name: Enabled description: Increment mode enabled value: 1 +enum/MEMMEM: + bit_size: 1 + variants: + - name: Disabled + description: Memory to memory mode disabled + value: 0 + - name: Enabled + description: Memory to memory mode enabled + value: 1 enum/PL: bit_size: 2 variants: diff --git a/data/registers/bdma_v2.yaml b/data/registers/bdma_v2.yaml index 83ed231..ed7839d 100644 --- a/data/registers/bdma_v2.yaml +++ b/data/registers/bdma_v2.yaml @@ -1,17 +1,32 @@ --- +block/CH: + description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" + items: + - name: CR + description: DMA channel configuration register (DMA_CCR) + byte_offset: 0 + fieldset: CR + - name: NDTR + description: DMA channel 1 number of data register + byte_offset: 4 + fieldset: NDTR + - name: PAR + description: DMA channel 1 peripheral address register + byte_offset: 8 + - name: MAR + description: DMA channel 1 memory address register + byte_offset: 12 block/DMA: description: DMA controller items: - name: ISR description: DMA interrupt status register (DMA_ISR) byte_offset: 0 - reset_value: 0 access: Read fieldset: ISR - name: IFCR description: DMA interrupt flag clear register (DMA_IFCR) byte_offset: 4 - reset_value: 0 access: Write fieldset: ISR - name: CH @@ -25,27 +40,6 @@ block/DMA: description: channel selection register byte_offset: 168 fieldset: CSELR -block/CH: - description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" - items: - - name: CR - description: DMA channel configuration register (DMA_CCR) - byte_offset: 0 - reset_value: 0 - fieldset: CR - - name: NDTR - description: DMA channel 1 number of data register - byte_offset: 4 - reset_value: 0 - fieldset: NDTR - - name: PAR - description: DMA channel 1 peripheral address register - byte_offset: 8 - reset_value: 0 - - name: MAR - description: DMA channel 1 memory address register - byte_offset: 12 - reset_value: 0 fieldset/CR: description: DMA channel configuration register (DMA_CCR) fields: @@ -171,15 +165,6 @@ enum/DIR: - name: FromMemory description: Read from memory value: 1 -enum/MEMMEM: - bit_size: 1 - variants: - - name: Disabled - description: Memory to memory mode disabled - value: 0 - - name: Enabled - description: Memory to memory mode enabled - value: 1 enum/INC: bit_size: 1 variants: @@ -189,6 +174,15 @@ enum/INC: - name: Enabled description: Increment mode enabled value: 1 +enum/MEMMEM: + bit_size: 1 + variants: + - name: Disabled + description: Memory to memory mode disabled + value: 0 + - name: Enabled + description: Memory to memory mode enabled + value: 1 enum/PL: bit_size: 2 variants: diff --git a/data/registers/can_bxcan.yaml b/data/registers/can_bxcan.yaml index 57d310c..73fb865 100644 --- a/data/registers/can_bxcan.yaml +++ b/data/registers/can_bxcan.yaml @@ -1,820 +1,817 @@ +--- block/CAN: description: Controller area network items: - - byte_offset: 0 - description: master control register - fieldset: MCR - name: MCR - - byte_offset: 4 - description: master status register - fieldset: MSR - name: MSR - - byte_offset: 8 - description: transmit status register - fieldset: TSR - name: TSR - - array: - len: 2 - stride: 4 - byte_offset: 12 - description: receive FIFO 0 register - fieldset: RFR - name: RFR - - byte_offset: 20 - description: interrupt enable register - fieldset: IER - name: IER - - byte_offset: 24 - description: error status register - fieldset: ESR - name: ESR - - byte_offset: 28 - description: bit timing register - fieldset: BTR - name: BTR - - array: - len: 3 - stride: 16 - block: TX - byte_offset: 384 - description: CAN Transmit cluster - name: TX - - array: - len: 2 - stride: 16 - block: RX - byte_offset: 432 - description: CAN Receive cluster - name: RX - - byte_offset: 512 - description: filter master register - fieldset: FMR - name: FMR - - byte_offset: 516 - description: filter mode register - fieldset: FM1R - name: FM1R - - byte_offset: 524 - description: filter scale register - fieldset: FS1R - name: FS1R - - byte_offset: 532 - description: filter FIFO assignment register - fieldset: FFA1R - name: FFA1R - - byte_offset: 540 - description: filter activation register - fieldset: FA1R - name: FA1R - - array: - len: 28 - stride: 8 - block: FB - byte_offset: 576 - description: CAN Filter Bank cluster - name: FB + - name: MCR + description: master control register + byte_offset: 0 + fieldset: MCR + - name: MSR + description: master status register + byte_offset: 4 + fieldset: MSR + - name: TSR + description: transmit status register + byte_offset: 8 + fieldset: TSR + - name: RFR + description: receive FIFO 0 register + array: + len: 2 + stride: 4 + byte_offset: 12 + fieldset: RFR + - name: IER + description: interrupt enable register + byte_offset: 20 + fieldset: IER + - name: ESR + description: error status register + byte_offset: 24 + fieldset: ESR + - name: BTR + description: bit timing register + byte_offset: 28 + fieldset: BTR + - name: TX + description: CAN Transmit cluster + array: + len: 3 + stride: 16 + byte_offset: 384 + block: TX + - name: RX + description: CAN Receive cluster + array: + len: 2 + stride: 16 + byte_offset: 432 + block: RX + - name: FMR + description: filter master register + byte_offset: 512 + fieldset: FMR + - name: FM1R + description: filter mode register + byte_offset: 516 + fieldset: FM1R + - name: FS1R + description: filter scale register + byte_offset: 524 + fieldset: FS1R + - name: FFA1R + description: filter FIFO assignment register + byte_offset: 532 + fieldset: FFA1R + - name: FA1R + description: filter activation register + byte_offset: 540 + fieldset: FA1R + - name: FB + description: CAN Filter Bank cluster + array: + len: 28 + stride: 8 + byte_offset: 576 + block: FB block/FB: description: CAN Filter Bank cluster items: - - byte_offset: 0 - description: Filter bank 0 register 1 - fieldset: FR1 - name: FR1 - - byte_offset: 4 - description: Filter bank 0 register 2 - fieldset: FR2 - name: FR2 + - name: FR1 + description: Filter bank 0 register 1 + byte_offset: 0 + fieldset: FR1 + - name: FR2 + description: Filter bank 0 register 2 + byte_offset: 4 + fieldset: FR2 block/RX: description: CAN Receive cluster items: - - access: Read - byte_offset: 0 - description: receive FIFO mailbox identifier register - fieldset: RIR - name: RIR - - access: Read - byte_offset: 4 - description: mailbox data high register - fieldset: RDTR - name: RDTR - - access: Read - byte_offset: 8 - description: mailbox data high register - fieldset: RDLR - name: RDLR - - access: Read - byte_offset: 12 - description: receive FIFO mailbox data high register - fieldset: RDHR - name: RDHR + - name: RIR + description: receive FIFO mailbox identifier register + byte_offset: 0 + access: Read + fieldset: RIR + - name: RDTR + description: mailbox data high register + byte_offset: 4 + access: Read + fieldset: RDTR + - name: RDLR + description: mailbox data high register + byte_offset: 8 + access: Read + fieldset: RDLR + - name: RDHR + description: receive FIFO mailbox data high register + byte_offset: 12 + access: Read + fieldset: RDHR block/TX: description: CAN Transmit cluster items: - - byte_offset: 0 - description: TX mailbox identifier register - fieldset: TIR - name: TIR - - byte_offset: 4 - description: mailbox data length control and time stamp register - fieldset: TDTR - name: TDTR - - byte_offset: 8 - description: mailbox data low register - fieldset: TDLR - name: TDLR - - byte_offset: 12 - description: mailbox data high register - fieldset: TDHR - name: TDHR -enum/BOFIE: - bit_size: 1 - variants: - - description: ERRI bit will not be set when BOFF is set - name: Disabled - value: 0 - - description: ERRI bit will be set when BOFF is set - name: Enabled - value: 1 -enum/EPVIE: - bit_size: 1 - variants: - - description: ERRI bit will not be set when EPVF is set - name: Disabled - value: 0 - - description: ERRI bit will be set when EPVF is set - name: Enabled - value: 1 -enum/ERRIE: - bit_size: 1 - variants: - - description: No interrupt will be generated when an error condition is pending - in the CAN_ESR - name: Disabled - value: 0 - - description: An interrupt will be generation when an error condition is pending - in the CAN_ESR - name: Enabled - value: 1 -enum/EWGIE: - bit_size: 1 - variants: - - description: ERRI bit will not be set when EWGF is set - name: Disabled - value: 0 - - description: ERRI bit will be set when EWGF is set - name: Enabled - value: 1 -enum/FFIE: - bit_size: 1 - variants: - - description: No interrupt when FULL bit is set - name: Disabled - value: 0 - - description: Interrupt generated when FULL bit is set - name: Enabled - value: 1 -enum/FMPIE: - bit_size: 1 - variants: - - description: No interrupt generated when state of FMP[1:0] bits are not 00b - name: Disabled - value: 0 - - description: Interrupt generated when state of FMP[1:0] bits are not 00b - name: Enabled - value: 1 -enum/FOVIE: - bit_size: 1 - variants: - - description: No interrupt when FOVR bit is set - name: Disabled - value: 0 - - description: Interrupt generated when FOVR bit is set - name: Enabled - value: 1 -enum/FOVRR: - bit_size: 1 - variants: - - description: No FIFO x overrun - name: NoOverrun - value: 0 - - description: FIFO x overrun - name: Overrun - value: 1 -enum/FOVRW: - bit_size: 1 - variants: - - description: Clear flag - name: Clear - value: 1 -enum/FULLR: - bit_size: 1 - variants: - - description: FIFO x is not full - name: NotFull - value: 0 - - description: FIFO x is full - name: Full - value: 1 -enum/FULLW: - bit_size: 1 - variants: - - description: Clear flag - name: Clear - value: 1 -enum/LBKM: - bit_size: 1 - variants: - - description: Loop Back Mode disabled - name: Disabled - value: 0 - - description: Loop Back Mode enabled - name: Enabled - value: 1 -enum/LEC: - bit_size: 3 - variants: - - description: No Error - name: NoError - value: 0 - - description: Stuff Error - name: Stuff - value: 1 - - description: Form Error - name: Form - value: 2 - - description: Acknowledgment Error - name: Ack - value: 3 - - description: Bit recessive Error - name: BitRecessive - value: 4 - - description: Bit dominant Error - name: BitDominant - value: 5 - - description: CRC Error - name: Crc - value: 6 - - description: Set by software - name: Custom - value: 7 -enum/LECIE: - bit_size: 1 - variants: - - description: ERRI bit will not be set when the error code in LEC[2:0] is set by - hardware on error detection - name: Disabled - value: 0 - - description: ERRI bit will be set when the error code in LEC[2:0] is set by hardware - on error detection - name: Enabled - value: 1 -enum/RFOMW: - bit_size: 1 - variants: - - description: Set by software to release the output mailbox of the FIFO - name: Release - value: 1 -enum/RIR_IDE: - bit_size: 1 - variants: - - description: Standard identifier - name: Standard - value: 0 - - description: Extended identifier - name: Extended - value: 1 -enum/RIR_RTR: - bit_size: 1 - variants: - - description: Data frame - name: Data - value: 0 - - description: Remote frame - name: Remote - value: 1 -enum/SILM: - bit_size: 1 - variants: - - description: Normal operation - name: Normal - value: 0 - - description: Silent Mode - name: Silent - value: 1 -enum/SLKIE: - bit_size: 1 - variants: - - description: No interrupt when SLAKI bit is set - name: Disabled - value: 0 - - description: Interrupt generated when SLAKI bit is set - name: Enabled - value: 1 -enum/TIR_IDE: - bit_size: 1 - variants: - - description: Standard identifier - name: Standard - value: 0 - - description: Extended identifier - name: Extended - value: 1 -enum/TIR_RTR: - bit_size: 1 - variants: - - description: Data frame - name: Data - value: 0 - - description: Remote frame - name: Remote - value: 1 -enum/TMEIE: - bit_size: 1 - variants: - - description: No interrupt when RQCPx bit is set - name: Disabled - value: 0 - - description: Interrupt generated when RQCPx bit is set - name: Enabled - value: 1 -enum/WKUIE: - bit_size: 1 - variants: - - description: No interrupt when WKUI is set - name: Disabled - value: 0 - - description: Interrupt generated when WKUI bit is set - name: Enabled - value: 1 + - name: TIR + description: TX mailbox identifier register + byte_offset: 0 + fieldset: TIR + - name: TDTR + description: mailbox data length control and time stamp register + byte_offset: 4 + fieldset: TDTR + - name: TDLR + description: mailbox data low register + byte_offset: 8 + fieldset: TDLR + - name: TDHR + description: mailbox data high register + byte_offset: 12 + fieldset: TDHR fieldset/BTR: description: bit timing register fields: - - bit_offset: 0 - bit_size: 10 - description: BRP - name: BRP - - array: - len: 2 - stride: 4 - bit_offset: 16 - bit_size: 4 - description: TS1 - name: TS - - bit_offset: 24 - bit_size: 2 - description: SJW - name: SJW - - bit_offset: 30 - bit_size: 1 - description: LBKM - enum: LBKM - name: LBKM - - bit_offset: 31 - bit_size: 1 - description: SILM - enum: SILM - name: SILM + - name: BRP + description: BRP + bit_offset: 0 + bit_size: 10 + - name: TS + description: TS1 + bit_offset: 16 + bit_size: 4 + array: + len: 2 + stride: 4 + - name: SJW + description: SJW + bit_offset: 24 + bit_size: 2 + - name: LBKM + description: LBKM + bit_offset: 30 + bit_size: 1 + enum: LBKM + - name: SILM + description: SILM + bit_offset: 31 + bit_size: 1 + enum: SILM fieldset/ESR: description: interrupt enable register fields: - - bit_offset: 0 - bit_size: 1 - description: EWGF - name: EWGF - - bit_offset: 1 - bit_size: 1 - description: EPVF - name: EPVF - - bit_offset: 2 - bit_size: 1 - description: BOFF - name: BOFF - - bit_offset: 4 - bit_size: 3 - description: LEC - enum: LEC - name: LEC - - bit_offset: 16 - bit_size: 8 - description: TEC - name: TEC - - bit_offset: 24 - bit_size: 8 - description: REC - name: REC + - name: EWGF + description: EWGF + bit_offset: 0 + bit_size: 1 + - name: EPVF + description: EPVF + bit_offset: 1 + bit_size: 1 + - name: BOFF + description: BOFF + bit_offset: 2 + bit_size: 1 + - name: LEC + description: LEC + bit_offset: 4 + bit_size: 3 + enum: LEC + - name: TEC + description: TEC + bit_offset: 16 + bit_size: 8 + - name: REC + description: REC + bit_offset: 24 + bit_size: 8 fieldset/FA1R: description: filter activation register fields: - - array: - len: 28 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: Filter active - name: FACT + - name: FACT + description: Filter active + bit_offset: 0 + bit_size: 1 + array: + len: 28 + stride: 1 fieldset/FFA1R: description: filter FIFO assignment register fields: - - array: - len: 28 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: Filter FIFO assignment for filter 0 - name: FFA + - name: FFA + description: Filter FIFO assignment for filter 0 + bit_offset: 0 + bit_size: 1 + array: + len: 28 + stride: 1 fieldset/FM1R: description: filter mode register fields: - - array: - len: 28 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: Filter mode - name: FBM + - name: FBM + description: Filter mode + bit_offset: 0 + bit_size: 1 + array: + len: 28 + stride: 1 fieldset/FMR: description: filter master register fields: - - bit_offset: 0 - bit_size: 1 - description: FINIT - name: FINIT - - bit_offset: 8 - bit_size: 6 - description: CAN2SB - name: CAN2SB + - name: FINIT + description: FINIT + bit_offset: 0 + bit_size: 1 + - name: CAN2SB + description: CAN2SB + bit_offset: 8 + bit_size: 6 fieldset/FR1: description: Filter bank 0 register 1 fields: - - array: - len: 32 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: Filter bits - name: FB + - name: FB + description: Filter bits + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 fieldset/FR2: description: Filter bank 0 register 2 fields: - - array: - len: 32 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: Filter bits - name: FB + - name: FB + description: Filter bits + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 fieldset/FS1R: description: filter scale register fields: - - array: - len: 28 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: Filter scale configuration - name: FSC + - name: FSC + description: Filter scale configuration + bit_offset: 0 + bit_size: 1 + array: + len: 28 + stride: 1 fieldset/IER: description: interrupt enable register fields: - - bit_offset: 0 - bit_size: 1 - description: TMEIE - enum: TMEIE - name: TMEIE - - array: - len: 2 - stride: 3 - bit_offset: 1 - bit_size: 1 - description: FMPIE0 - enum: FMPIE - name: FMPIE - - array: - len: 2 - stride: 3 - bit_offset: 2 - bit_size: 1 - description: FFIE0 - enum: FFIE - name: FFIE - - array: - len: 2 - stride: 3 - bit_offset: 3 - bit_size: 1 - description: FOVIE0 - enum: FOVIE - name: FOVIE - - bit_offset: 8 - bit_size: 1 - description: EWGIE - enum: EWGIE - name: EWGIE - - bit_offset: 9 - bit_size: 1 - description: EPVIE - enum: EPVIE - name: EPVIE - - bit_offset: 10 - bit_size: 1 - description: BOFIE - enum: BOFIE - name: BOFIE - - bit_offset: 11 - bit_size: 1 - description: LECIE - enum: LECIE - name: LECIE - - bit_offset: 15 - bit_size: 1 - description: ERRIE - enum: ERRIE - name: ERRIE - - bit_offset: 16 - bit_size: 1 - description: WKUIE - enum: WKUIE - name: WKUIE - - bit_offset: 17 - bit_size: 1 - description: SLKIE - enum: SLKIE - name: SLKIE + - name: TMEIE + description: TMEIE + bit_offset: 0 + bit_size: 1 + enum: TMEIE + - name: FMPIE + description: FMPIE0 + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 3 + enum: FMPIE + - name: FFIE + description: FFIE0 + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 3 + enum: FFIE + - name: FOVIE + description: FOVIE0 + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 3 + enum: FOVIE + - name: EWGIE + description: EWGIE + bit_offset: 8 + bit_size: 1 + enum: EWGIE + - name: EPVIE + description: EPVIE + bit_offset: 9 + bit_size: 1 + enum: EPVIE + - name: BOFIE + description: BOFIE + bit_offset: 10 + bit_size: 1 + enum: BOFIE + - name: LECIE + description: LECIE + bit_offset: 11 + bit_size: 1 + enum: LECIE + - name: ERRIE + description: ERRIE + bit_offset: 15 + bit_size: 1 + enum: ERRIE + - name: WKUIE + description: WKUIE + bit_offset: 16 + bit_size: 1 + enum: WKUIE + - name: SLKIE + description: SLKIE + bit_offset: 17 + bit_size: 1 + enum: SLKIE fieldset/MCR: description: master control register fields: - - bit_offset: 0 - bit_size: 1 - description: INRQ - name: INRQ - - bit_offset: 1 - bit_size: 1 - description: SLEEP - name: SLEEP - - bit_offset: 2 - bit_size: 1 - description: TXFP - name: TXFP - - bit_offset: 3 - bit_size: 1 - description: RFLM - name: RFLM - - bit_offset: 4 - bit_size: 1 - description: NART - name: NART - - bit_offset: 5 - bit_size: 1 - description: AWUM - name: AWUM - - bit_offset: 6 - bit_size: 1 - description: ABOM - name: ABOM - - bit_offset: 7 - bit_size: 1 - description: TTCM - name: TTCM - - bit_offset: 15 - bit_size: 1 - description: RESET - name: RESET - - bit_offset: 16 - bit_size: 1 - description: DBF - name: DBF + - name: INRQ + description: INRQ + bit_offset: 0 + bit_size: 1 + - name: SLEEP + description: SLEEP + bit_offset: 1 + bit_size: 1 + - name: TXFP + description: TXFP + bit_offset: 2 + bit_size: 1 + - name: RFLM + description: RFLM + bit_offset: 3 + bit_size: 1 + - name: NART + description: NART + bit_offset: 4 + bit_size: 1 + - name: AWUM + description: AWUM + bit_offset: 5 + bit_size: 1 + - name: ABOM + description: ABOM + bit_offset: 6 + bit_size: 1 + - name: TTCM + description: TTCM + bit_offset: 7 + bit_size: 1 + - name: RESET + description: RESET + bit_offset: 15 + bit_size: 1 + - name: DBF + description: DBF + bit_offset: 16 + bit_size: 1 fieldset/MSR: description: master status register fields: - - bit_offset: 0 - bit_size: 1 - description: INAK - name: INAK - - bit_offset: 1 - bit_size: 1 - description: SLAK - name: SLAK - - bit_offset: 2 - bit_size: 1 - description: ERRI - name: ERRI - - bit_offset: 3 - bit_size: 1 - description: WKUI - name: WKUI - - bit_offset: 4 - bit_size: 1 - description: SLAKI - name: SLAKI - - bit_offset: 8 - bit_size: 1 - description: TXM - name: TXM - - bit_offset: 9 - bit_size: 1 - description: RXM - name: RXM - - bit_offset: 10 - bit_size: 1 - description: SAMP - name: SAMP - - bit_offset: 11 - bit_size: 1 - description: RX - name: RX + - name: INAK + description: INAK + bit_offset: 0 + bit_size: 1 + - name: SLAK + description: SLAK + bit_offset: 1 + bit_size: 1 + - name: ERRI + description: ERRI + bit_offset: 2 + bit_size: 1 + - name: WKUI + description: WKUI + bit_offset: 3 + bit_size: 1 + - name: SLAKI + description: SLAKI + bit_offset: 4 + bit_size: 1 + - name: TXM + description: TXM + bit_offset: 8 + bit_size: 1 + - name: RXM + description: RXM + bit_offset: 9 + bit_size: 1 + - name: SAMP + description: SAMP + bit_offset: 10 + bit_size: 1 + - name: RX + description: RX + bit_offset: 11 + bit_size: 1 fieldset/RDHR: description: receive FIFO mailbox data high register fields: - - array: - len: 4 - stride: 8 - bit_offset: 0 - bit_size: 8 - description: DATA4 - name: DATA + - name: DATA + description: DATA4 + bit_offset: 0 + bit_size: 8 + array: + len: 4 + stride: 8 fieldset/RDLR: description: mailbox data high register fields: - - array: - len: 4 - stride: 8 - bit_offset: 0 - bit_size: 8 - description: DATA0 - name: DATA + - name: DATA + description: DATA0 + bit_offset: 0 + bit_size: 8 + array: + len: 4 + stride: 8 fieldset/RDTR: description: mailbox data high register fields: - - bit_offset: 0 - bit_size: 4 - description: DLC - name: DLC - - bit_offset: 8 - bit_size: 8 - description: FMI - name: FMI - - bit_offset: 16 - bit_size: 16 - description: TIME - name: TIME + - name: DLC + description: DLC + bit_offset: 0 + bit_size: 4 + - name: FMI + description: FMI + bit_offset: 8 + bit_size: 8 + - name: TIME + description: TIME + bit_offset: 16 + bit_size: 16 fieldset/RFR: description: receive FIFO 0 register fields: - - bit_offset: 0 - bit_size: 2 - description: FMP0 - name: FMP - - bit_offset: 3 - bit_size: 1 - description: FULL0 - enum_read: FULLR - enum_write: FULLW - name: FULL - - bit_offset: 4 - bit_size: 1 - description: FOVR0 - enum_read: FOVRR - enum_write: FOVRW - name: FOVR - - bit_offset: 5 - bit_size: 1 - description: RFOM0 - enum_write: RFOMW - name: RFOM + - name: FMP + description: FMP0 + bit_offset: 0 + bit_size: 2 + - name: FULL + description: FULL0 + bit_offset: 3 + bit_size: 1 + enum_read: FULLR + enum_write: FULLW + - name: FOVR + description: FOVR0 + bit_offset: 4 + bit_size: 1 + enum_read: FOVRR + enum_write: FOVRW + - name: RFOM + description: RFOM0 + bit_offset: 5 + bit_size: 1 + enum_write: RFOMW fieldset/RIR: description: receive FIFO mailbox identifier register fields: - - bit_offset: 1 - bit_size: 1 - description: RTR - enum: RIR_RTR - name: RTR - - bit_offset: 2 - bit_size: 1 - description: IDE - enum: RIR_IDE - name: IDE - - bit_offset: 3 - bit_size: 18 - description: EXID - name: EXID - - bit_offset: 21 - bit_size: 11 - description: STID - name: STID + - name: RTR + description: RTR + bit_offset: 1 + bit_size: 1 + enum: RIR_RTR + - name: IDE + description: IDE + bit_offset: 2 + bit_size: 1 + enum: RIR_IDE + - name: EXID + description: EXID + bit_offset: 3 + bit_size: 18 + - name: STID + description: STID + bit_offset: 21 + bit_size: 11 fieldset/TDHR: description: mailbox data high register fields: - - array: - len: 4 - stride: 8 - bit_offset: 0 - bit_size: 8 - description: DATA4 - name: DATA + - name: DATA + description: DATA4 + bit_offset: 0 + bit_size: 8 + array: + len: 4 + stride: 8 fieldset/TDLR: description: mailbox data low register fields: - - array: - len: 4 - stride: 8 - bit_offset: 0 - bit_size: 8 - description: DATA0 - name: DATA + - name: DATA + description: DATA0 + bit_offset: 0 + bit_size: 8 + array: + len: 4 + stride: 8 fieldset/TDTR: description: mailbox data length control and time stamp register fields: - - bit_offset: 0 - bit_size: 4 - description: DLC - name: DLC - - bit_offset: 8 - bit_size: 1 - description: TGT - name: TGT - - bit_offset: 16 - bit_size: 16 - description: TIME - name: TIME + - name: DLC + description: DLC + bit_offset: 0 + bit_size: 4 + - name: TGT + description: TGT + bit_offset: 8 + bit_size: 1 + - name: TIME + description: TIME + bit_offset: 16 + bit_size: 16 fieldset/TIR: description: TX mailbox identifier register fields: - - bit_offset: 0 - bit_size: 1 - description: TXRQ - name: TXRQ - - bit_offset: 1 - bit_size: 1 - description: RTR - enum: TIR_RTR - name: RTR - - bit_offset: 2 - bit_size: 1 - description: IDE - enum: TIR_IDE - name: IDE - - bit_offset: 3 - bit_size: 18 - description: EXID - name: EXID - - bit_offset: 21 - bit_size: 11 - description: STID - name: STID + - name: TXRQ + description: TXRQ + bit_offset: 0 + bit_size: 1 + - name: RTR + description: RTR + bit_offset: 1 + bit_size: 1 + enum: TIR_RTR + - name: IDE + description: IDE + bit_offset: 2 + bit_size: 1 + enum: TIR_IDE + - name: EXID + description: EXID + bit_offset: 3 + bit_size: 18 + - name: STID + description: STID + bit_offset: 21 + bit_size: 11 fieldset/TSR: description: transmit status register fields: - - array: - len: 3 - stride: 8 - bit_offset: 0 - bit_size: 1 - description: RQCP0 - name: RQCP - - array: - len: 3 - stride: 8 - bit_offset: 1 - bit_size: 1 - description: TXOK0 - name: TXOK - - array: - len: 3 - stride: 8 - bit_offset: 2 - bit_size: 1 - description: ALST0 - name: ALST - - array: - len: 3 - stride: 8 - bit_offset: 3 - bit_size: 1 - description: TERR0 - name: TERR - - array: - len: 3 - stride: 8 - bit_offset: 7 - bit_size: 1 - description: ABRQ0 - name: ABRQ - - bit_offset: 24 - bit_size: 2 - description: CODE - name: CODE - - array: - len: 3 - stride: 1 - bit_offset: 26 - bit_size: 1 - description: Lowest priority flag for mailbox 0 - name: TME - - array: - len: 3 - stride: 1 - bit_offset: 29 - bit_size: 1 - description: Lowest priority flag for mailbox 0 - name: LOW + - name: RQCP + description: RQCP0 + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 8 + - name: TXOK + description: TXOK0 + bit_offset: 1 + bit_size: 1 + array: + len: 3 + stride: 8 + - name: ALST + description: ALST0 + bit_offset: 2 + bit_size: 1 + array: + len: 3 + stride: 8 + - name: TERR + description: TERR0 + bit_offset: 3 + bit_size: 1 + array: + len: 3 + stride: 8 + - name: ABRQ + description: ABRQ0 + bit_offset: 7 + bit_size: 1 + array: + len: 3 + stride: 8 + - name: CODE + description: CODE + bit_offset: 24 + bit_size: 2 + - name: TME + description: Lowest priority flag for mailbox 0 + bit_offset: 26 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: LOW + description: Lowest priority flag for mailbox 0 + bit_offset: 29 + bit_size: 1 + array: + len: 3 + stride: 1 +enum/BOFIE: + bit_size: 1 + variants: + - name: Disabled + description: ERRI bit will not be set when BOFF is set + value: 0 + - name: Enabled + description: ERRI bit will be set when BOFF is set + value: 1 +enum/EPVIE: + bit_size: 1 + variants: + - name: Disabled + description: ERRI bit will not be set when EPVF is set + value: 0 + - name: Enabled + description: ERRI bit will be set when EPVF is set + value: 1 +enum/ERRIE: + bit_size: 1 + variants: + - name: Disabled + description: No interrupt will be generated when an error condition is pending in the CAN_ESR + value: 0 + - name: Enabled + description: An interrupt will be generation when an error condition is pending in the CAN_ESR + value: 1 +enum/EWGIE: + bit_size: 1 + variants: + - name: Disabled + description: ERRI bit will not be set when EWGF is set + value: 0 + - name: Enabled + description: ERRI bit will be set when EWGF is set + value: 1 +enum/FFIE: + bit_size: 1 + variants: + - name: Disabled + description: No interrupt when FULL bit is set + value: 0 + - name: Enabled + description: Interrupt generated when FULL bit is set + value: 1 +enum/FMPIE: + bit_size: 1 + variants: + - name: Disabled + description: "No interrupt generated when state of FMP[1:0] bits are not 00b" + value: 0 + - name: Enabled + description: "Interrupt generated when state of FMP[1:0] bits are not 00b" + value: 1 +enum/FOVIE: + bit_size: 1 + variants: + - name: Disabled + description: No interrupt when FOVR bit is set + value: 0 + - name: Enabled + description: Interrupt generated when FOVR bit is set + value: 1 +enum/FOVRR: + bit_size: 1 + variants: + - name: NoOverrun + description: No FIFO x overrun + value: 0 + - name: Overrun + description: FIFO x overrun + value: 1 +enum/FOVRW: + bit_size: 1 + variants: + - name: Clear + description: Clear flag + value: 1 +enum/FULLR: + bit_size: 1 + variants: + - name: NotFull + description: FIFO x is not full + value: 0 + - name: Full + description: FIFO x is full + value: 1 +enum/FULLW: + bit_size: 1 + variants: + - name: Clear + description: Clear flag + value: 1 +enum/LBKM: + bit_size: 1 + variants: + - name: Disabled + description: Loop Back Mode disabled + value: 0 + - name: Enabled + description: Loop Back Mode enabled + value: 1 +enum/LEC: + bit_size: 3 + variants: + - name: NoError + description: No Error + value: 0 + - name: Stuff + description: Stuff Error + value: 1 + - name: Form + description: Form Error + value: 2 + - name: Ack + description: Acknowledgment Error + value: 3 + - name: BitRecessive + description: Bit recessive Error + value: 4 + - name: BitDominant + description: Bit dominant Error + value: 5 + - name: Crc + description: CRC Error + value: 6 + - name: Custom + description: Set by software + value: 7 +enum/LECIE: + bit_size: 1 + variants: + - name: Disabled + description: "ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection" + value: 0 + - name: Enabled + description: "ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection" + value: 1 +enum/RFOMW: + bit_size: 1 + variants: + - name: Release + description: Set by software to release the output mailbox of the FIFO + value: 1 +enum/RIR_IDE: + bit_size: 1 + variants: + - name: Standard + description: Standard identifier + value: 0 + - name: Extended + description: Extended identifier + value: 1 +enum/RIR_RTR: + bit_size: 1 + variants: + - name: Data + description: Data frame + value: 0 + - name: Remote + description: Remote frame + value: 1 +enum/SILM: + bit_size: 1 + variants: + - name: Normal + description: Normal operation + value: 0 + - name: Silent + description: Silent Mode + value: 1 +enum/SLKIE: + bit_size: 1 + variants: + - name: Disabled + description: No interrupt when SLAKI bit is set + value: 0 + - name: Enabled + description: Interrupt generated when SLAKI bit is set + value: 1 +enum/TIR_IDE: + bit_size: 1 + variants: + - name: Standard + description: Standard identifier + value: 0 + - name: Extended + description: Extended identifier + value: 1 +enum/TIR_RTR: + bit_size: 1 + variants: + - name: Data + description: Data frame + value: 0 + - name: Remote + description: Remote frame + value: 1 +enum/TMEIE: + bit_size: 1 + variants: + - name: Disabled + description: No interrupt when RQCPx bit is set + value: 0 + - name: Enabled + description: Interrupt generated when RQCPx bit is set + value: 1 +enum/WKUIE: + bit_size: 1 + variants: + - name: Disabled + description: No interrupt when WKUI is set + value: 0 + - name: Enabled + description: Interrupt generated when WKUI bit is set + value: 1 diff --git a/data/registers/dac_v1.yaml b/data/registers/dac_v1.yaml index d081aa0..e1ec912 100644 --- a/data/registers/dac_v1.yaml +++ b/data/registers/dac_v1.yaml @@ -2,365 +2,365 @@ block/DAC: description: Digital-to-analog converter items: - - byte_offset: 0 - description: control register - fieldset: CR - name: CR - - access: Write - byte_offset: 4 - description: software trigger register - fieldset: SWTRIGR - name: SWTRIGR - - byte_offset: 8 - description: channel1 12-bit right-aligned data holding register - fieldset: DHR12R1 - name: DHR12R1 - - byte_offset: 12 - description: channel1 12-bit left aligned data holding register - fieldset: DHR12L1 - name: DHR12L1 - - byte_offset: 16 - description: channel1 8-bit right aligned data holding register - fieldset: DHR8R1 - name: DHR8R1 - - byte_offset: 20 - description: channel2 12-bit right aligned data holding register - fieldset: DHR12R2 - name: DHR12R2 - - byte_offset: 24 - description: channel2 12-bit left aligned data holding register - fieldset: DHR12L2 - name: DHR12L2 - - byte_offset: 28 - description: channel2 8-bit right-aligned data holding register - fieldset: DHR8R2 - name: DHR8R2 - - byte_offset: 32 - description: Dual DAC 12-bit right-aligned data holding register - fieldset: DHR12RD - name: DHR12RD - - byte_offset: 36 - description: DUAL DAC 12-bit left aligned data holding register - fieldset: DHR12LD - name: DHR12LD - - byte_offset: 40 - description: DUAL DAC 8-bit right aligned data holding register - fieldset: DHR8RD - name: DHR8RD - - access: Read - byte_offset: 44 - description: channel1 data output register - fieldset: DOR1 - name: DOR1 - - access: Read - byte_offset: 48 - description: channel2 data output register - fieldset: DOR2 - name: DOR2 - - byte_offset: 52 - description: status register - fieldset: SR - name: SR -enum/BOFF: - bit_size: 1 - variants: - - description: DAC channel X output buffer enabled - name: Enabled - value: 0 - - description: DAC channel X output buffer disabled - name: Disabled - value: 1 -enum/DMAEN: - bit_size: 1 - variants: - - description: DAC channel X DMA mode disabled - name: Disabled - value: 0 - - description: DAC channel X DMA mode enabled - name: Enabled - value: 1 -enum/DMAUDR: - bit_size: 1 - variants: - - description: No DMA underrun error condition occurred for DAC channel X - name: NoUnderrun - value: 0 - - description: DMA underrun error condition occurred for DAC channel X - name: Underrun - value: 1 -enum/DMAUDRIE: - bit_size: 1 - variants: - - description: DAC channel X DMA Underrun Interrupt disabled - name: Disabled - value: 0 - - description: DAC channel X DMA Underrun Interrupt enabled - name: Enabled - value: 1 -enum/EN: - bit_size: 1 - variants: - - description: DAC channel X disabled - name: Disabled - value: 0 - - description: DAC channel X enabled - name: Enabled - value: 1 -enum/SWTRIG: - bit_size: 1 - variants: - - description: DAC channel X software trigger disabled - name: Disabled - value: 0 - - description: DAC channel X software trigger enabled - name: Enabled - value: 1 -enum/TEN: - bit_size: 1 - variants: - - description: DAC channel X trigger disabled - name: Disabled - value: 0 - - description: DAC channel X trigger enabled - name: Enabled - value: 1 -enum/TSEL1: - bit_size: 3 - variants: - - description: Timer 6 TRGO event - name: TIM6_TRGO - value: 0 - - description: Timer 3 TRGO event - name: TIM3_TRGO - value: 1 - - description: Timer 7 TRGO event - name: TIM7_TRGO - value: 2 - - description: Timer 15 TRGO event - name: TIM15_TRGO - value: 3 - - description: Timer 2 TRGO event - name: TIM2_TRGO - value: 4 - - description: EXTI line9 - name: EXTI9 - value: 6 - - description: Software trigger - name: SOFTWARE - value: 7 -enum/TSEL2: - bit_size: 3 - variants: - - description: Timer 6 TRGO event - name: TIM6_TRGO - value: 0 - - description: Timer 8 TRGO event - name: TIM8_TRGO - value: 1 - - description: Timer 7 TRGO event - name: TIM7_TRGO - value: 2 - - description: Timer 5 TRGO event - name: TIM5_TRGO - value: 3 - - description: Timer 2 TRGO event - name: TIM2_TRGO - value: 4 - - description: Timer 4 TRGO event - name: TIM4_TRGO - value: 5 - - description: EXTI line9 - name: EXTI9 - value: 6 - - description: Software trigger - name: SOFTWARE - value: 7 -enum/WAVE: - bit_size: 2 - variants: - - description: Wave generation disabled - name: Disabled - value: 0 - - description: Noise wave generation enabled - name: Noise - value: 1 - - description: Triangle wave generation enabled - name: Triangle - value: 2 + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SWTRIGR + description: software trigger register + byte_offset: 4 + access: Write + fieldset: SWTRIGR + - name: DHR12R1 + description: channel1 12-bit right-aligned data holding register + byte_offset: 8 + fieldset: DHR12R1 + - name: DHR12L1 + description: channel1 12-bit left aligned data holding register + byte_offset: 12 + fieldset: DHR12L1 + - name: DHR8R1 + description: channel1 8-bit right aligned data holding register + byte_offset: 16 + fieldset: DHR8R1 + - name: DHR12R2 + description: channel2 12-bit right aligned data holding register + byte_offset: 20 + fieldset: DHR12R2 + - name: DHR12L2 + description: channel2 12-bit left aligned data holding register + byte_offset: 24 + fieldset: DHR12L2 + - name: DHR8R2 + description: channel2 8-bit right-aligned data holding register + byte_offset: 28 + fieldset: DHR8R2 + - name: DHR12RD + description: Dual DAC 12-bit right-aligned data holding register + byte_offset: 32 + fieldset: DHR12RD + - name: DHR12LD + description: DUAL DAC 12-bit left aligned data holding register + byte_offset: 36 + fieldset: DHR12LD + - name: DHR8RD + description: DUAL DAC 8-bit right aligned data holding register + byte_offset: 40 + fieldset: DHR8RD + - name: DOR1 + description: channel1 data output register + byte_offset: 44 + access: Read + fieldset: DOR1 + - name: DOR2 + description: channel2 data output register + byte_offset: 48 + access: Read + fieldset: DOR2 + - name: SR + description: status register + byte_offset: 52 + fieldset: SR fieldset/CR: description: control register fields: - - array: - len: 2 - stride: 16 - bit_offset: 0 - bit_size: 1 - description: DAC channel1 enable - enum: EN - name: EN - - array: - len: 2 - stride: 16 - bit_offset: 1 - bit_size: 1 - description: DAC channel1 output buffer disable - enum: BOFF - name: BOFF - - array: - len: 2 - stride: 16 - bit_offset: 2 - bit_size: 1 - description: DAC channel1 trigger enable - enum: TEN - name: TEN - - array: - len: 2 - stride: 16 - bit_offset: 3 - bit_size: 3 - description: DAC channel1 trigger selection - enum: TSEL1 - name: TSEL - - array: - len: 2 - stride: 16 - bit_offset: 6 - bit_size: 2 - description: DAC channel1 noise/triangle wave generation enable - enum: WAVE - name: WAVE - - array: - len: 2 - stride: 16 - bit_offset: 8 - bit_size: 4 - description: DAC channel1 mask/amplitude selector - name: MAMP - - array: - len: 2 - stride: 16 - bit_offset: 12 - bit_size: 1 - description: DAC channel1 DMA enable - enum: DMAEN - name: DMAEN - - array: - len: 2 - stride: 16 - bit_offset: 13 - bit_size: 1 - description: DAC channel1 DMA Underrun Interrupt enable - enum: DMAUDRIE - name: DMAUDRIE + - name: EN + description: DAC channel1 enable + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 16 + enum: EN + - name: BOFF + description: DAC channel1 output buffer disable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 16 + enum: BOFF + - name: TEN + description: DAC channel1 trigger enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 16 + enum: TEN + - name: TSEL + description: DAC channel1 trigger selection + bit_offset: 3 + bit_size: 3 + array: + len: 2 + stride: 16 + enum: TSEL1 + - name: WAVE + description: DAC channel1 noise/triangle wave generation enable + bit_offset: 6 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: WAVE + - name: MAMP + description: DAC channel1 mask/amplitude selector + bit_offset: 8 + bit_size: 4 + array: + len: 2 + stride: 16 + - name: DMAEN + description: DAC channel1 DMA enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 16 + enum: DMAEN + - name: DMAUDRIE + description: DAC channel1 DMA Underrun Interrupt enable + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 16 + enum: DMAUDRIE fieldset/DHR12L1: description: channel1 12-bit left aligned data holding register fields: - - bit_offset: 4 - bit_size: 12 - description: DAC channel1 12-bit left-aligned data - name: DACC1DHR + - name: DACC1DHR + description: DAC channel1 12-bit left-aligned data + bit_offset: 4 + bit_size: 12 fieldset/DHR12L2: description: channel2 12-bit left aligned data holding register fields: - - bit_offset: 4 - bit_size: 12 - description: DAC channel2 12-bit left-aligned data - name: DACC2DHR + - name: DACC2DHR + description: DAC channel2 12-bit left-aligned data + bit_offset: 4 + bit_size: 12 fieldset/DHR12LD: description: DUAL DAC 12-bit left aligned data holding register fields: - - bit_offset: 4 - bit_size: 12 - description: DAC channel1 12-bit left-aligned data - name: DACC1DHR - - bit_offset: 20 - bit_size: 12 - description: DAC channel2 12-bit left-aligned data - name: DACC2DHR + - name: DACC1DHR + description: DAC channel1 12-bit left-aligned data + bit_offset: 4 + bit_size: 12 + - name: DACC2DHR + description: DAC channel2 12-bit left-aligned data + bit_offset: 20 + bit_size: 12 fieldset/DHR12R1: description: channel1 12-bit right-aligned data holding register fields: - - bit_offset: 0 - bit_size: 12 - description: DAC channel1 12-bit right-aligned data - name: DACC1DHR + - name: DACC1DHR + description: DAC channel1 12-bit right-aligned data + bit_offset: 0 + bit_size: 12 fieldset/DHR12R2: description: channel2 12-bit right aligned data holding register fields: - - bit_offset: 0 - bit_size: 12 - description: DAC channel2 12-bit right-aligned data - name: DACC2DHR + - name: DACC2DHR + description: DAC channel2 12-bit right-aligned data + bit_offset: 0 + bit_size: 12 fieldset/DHR12RD: description: Dual DAC 12-bit right-aligned data holding register fields: - - bit_offset: 0 - bit_size: 12 - description: DAC channel1 12-bit right-aligned data - name: DACC1DHR - - bit_offset: 16 - bit_size: 12 - description: DAC channel2 12-bit right-aligned data - name: DACC2DHR + - name: DACC1DHR + description: DAC channel1 12-bit right-aligned data + bit_offset: 0 + bit_size: 12 + - name: DACC2DHR + description: DAC channel2 12-bit right-aligned data + bit_offset: 16 + bit_size: 12 fieldset/DHR8R1: description: channel1 8-bit right aligned data holding register fields: - - bit_offset: 0 - bit_size: 8 - description: DAC channel1 8-bit right-aligned data - name: DACC1DHR + - name: DACC1DHR + description: DAC channel1 8-bit right-aligned data + bit_offset: 0 + bit_size: 8 fieldset/DHR8R2: description: channel2 8-bit right-aligned data holding register fields: - - bit_offset: 0 - bit_size: 8 - description: DAC channel2 8-bit right-aligned data - name: DACC2DHR + - name: DACC2DHR + description: DAC channel2 8-bit right-aligned data + bit_offset: 0 + bit_size: 8 fieldset/DHR8RD: description: DUAL DAC 8-bit right aligned data holding register fields: - - bit_offset: 0 - bit_size: 8 - description: DAC channel1 8-bit right-aligned data - name: DACC1DHR - - bit_offset: 8 - bit_size: 8 - description: DAC channel2 8-bit right-aligned data - name: DACC2DHR + - name: DACC1DHR + description: DAC channel1 8-bit right-aligned data + bit_offset: 0 + bit_size: 8 + - name: DACC2DHR + description: DAC channel2 8-bit right-aligned data + bit_offset: 8 + bit_size: 8 fieldset/DOR1: description: channel1 data output register fields: - - bit_offset: 0 - bit_size: 12 - description: DAC channel1 data output - name: DACC1DOR + - name: DACC1DOR + description: DAC channel1 data output + bit_offset: 0 + bit_size: 12 fieldset/DOR2: description: channel2 data output register fields: - - bit_offset: 0 - bit_size: 12 - description: DAC channel2 data output - name: DACC2DOR + - name: DACC2DOR + description: DAC channel2 data output + bit_offset: 0 + bit_size: 12 fieldset/SR: description: status register fields: - - array: - len: 2 - stride: 16 - bit_offset: 13 - bit_size: 1 - description: DAC channel1 DMA underrun flag - enum: DMAUDR - name: DMAUDR + - name: DMAUDR + description: DAC channel1 DMA underrun flag + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 16 + enum: DMAUDR fieldset/SWTRIGR: description: software trigger register fields: - - array: - len: 2 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: DAC channel1 software trigger - enum: SWTRIG - name: SWTRIG + - name: SWTRIG + description: DAC channel1 software trigger + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: SWTRIG +enum/BOFF: + bit_size: 1 + variants: + - name: Enabled + description: DAC channel X output buffer enabled + value: 0 + - name: Disabled + description: DAC channel X output buffer disabled + value: 1 +enum/DMAEN: + bit_size: 1 + variants: + - name: Disabled + description: DAC channel X DMA mode disabled + value: 0 + - name: Enabled + description: DAC channel X DMA mode enabled + value: 1 +enum/DMAUDR: + bit_size: 1 + variants: + - name: NoUnderrun + description: No DMA underrun error condition occurred for DAC channel X + value: 0 + - name: Underrun + description: DMA underrun error condition occurred for DAC channel X + value: 1 +enum/DMAUDRIE: + bit_size: 1 + variants: + - name: Disabled + description: DAC channel X DMA Underrun Interrupt disabled + value: 0 + - name: Enabled + description: DAC channel X DMA Underrun Interrupt enabled + value: 1 +enum/EN: + bit_size: 1 + variants: + - name: Disabled + description: DAC channel X disabled + value: 0 + - name: Enabled + description: DAC channel X enabled + value: 1 +enum/SWTRIG: + bit_size: 1 + variants: + - name: Disabled + description: DAC channel X software trigger disabled + value: 0 + - name: Enabled + description: DAC channel X software trigger enabled + value: 1 +enum/TEN: + bit_size: 1 + variants: + - name: Disabled + description: DAC channel X trigger disabled + value: 0 + - name: Enabled + description: DAC channel X trigger enabled + value: 1 +enum/TSEL1: + bit_size: 3 + variants: + - name: TIM6_TRGO + description: Timer 6 TRGO event + value: 0 + - name: TIM3_TRGO + description: Timer 3 TRGO event + value: 1 + - name: TIM7_TRGO + description: Timer 7 TRGO event + value: 2 + - name: TIM15_TRGO + description: Timer 15 TRGO event + value: 3 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 4 + - name: EXTI9 + description: EXTI line9 + value: 6 + - name: SOFTWARE + description: Software trigger + value: 7 +enum/TSEL2: + bit_size: 3 + variants: + - name: TIM6_TRGO + description: Timer 6 TRGO event + value: 0 + - name: TIM8_TRGO + description: Timer 8 TRGO event + value: 1 + - name: TIM7_TRGO + description: Timer 7 TRGO event + value: 2 + - name: TIM5_TRGO + description: Timer 5 TRGO event + value: 3 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 4 + - name: TIM4_TRGO + description: Timer 4 TRGO event + value: 5 + - name: EXTI9 + description: EXTI line9 + value: 6 + - name: SOFTWARE + description: Software trigger + value: 7 +enum/WAVE: + bit_size: 2 + variants: + - name: Disabled + description: Wave generation disabled + value: 0 + - name: Noise + description: Noise wave generation enabled + value: 1 + - name: Triangle + description: Triangle wave generation enabled + value: 2 diff --git a/data/registers/dcmi_v1.yaml b/data/registers/dcmi_v1.yaml index d9c69ed..71101e5 100644 --- a/data/registers/dcmi_v1.yaml +++ b/data/registers/dcmi_v1.yaml @@ -2,285 +2,285 @@ block/DCMI: description: Digital camera interface items: - - byte_offset: 0 - description: control register 1 - fieldset: CR - name: CR - - access: Read - byte_offset: 4 - description: status register - fieldset: SR - name: SR - - access: Read - byte_offset: 8 - description: raw interrupt status register - fieldset: RIS - name: RIS - - byte_offset: 12 - description: interrupt enable register - fieldset: IER - name: IER - - access: Read - byte_offset: 16 - description: masked interrupt status register - fieldset: MIS - name: MIS - - access: Write - byte_offset: 20 - description: interrupt clear register - fieldset: ICR - name: ICR - - byte_offset: 24 - description: embedded synchronization code register - fieldset: ESCR - name: ESCR - - byte_offset: 28 - description: embedded synchronization unmask register - fieldset: ESUR - name: ESUR - - byte_offset: 32 - description: crop window start - fieldset: CWSTRT - name: CWSTRT - - byte_offset: 36 - description: crop window size - fieldset: CWSIZE - name: CWSIZE - - access: Read - byte_offset: 40 - description: data register - fieldset: DR - name: DR + - name: CR + description: control register 1 + byte_offset: 0 + fieldset: CR + - name: SR + description: status register + byte_offset: 4 + access: Read + fieldset: SR + - name: RIS + description: raw interrupt status register + byte_offset: 8 + access: Read + fieldset: RIS + - name: IER + description: interrupt enable register + byte_offset: 12 + fieldset: IER + - name: MIS + description: masked interrupt status register + byte_offset: 16 + access: Read + fieldset: MIS + - name: ICR + description: interrupt clear register + byte_offset: 20 + access: Write + fieldset: ICR + - name: ESCR + description: embedded synchronization code register + byte_offset: 24 + fieldset: ESCR + - name: ESUR + description: embedded synchronization unmask register + byte_offset: 28 + fieldset: ESUR + - name: CWSTRT + description: crop window start + byte_offset: 32 + fieldset: CWSTRT + - name: CWSIZE + description: crop window size + byte_offset: 36 + fieldset: CWSIZE + - name: DR + description: data register + byte_offset: 40 + access: Read + fieldset: DR fieldset/CR: description: control register 1 fields: - - bit_offset: 0 - bit_size: 1 - description: Capture enable - name: CAPTURE - - bit_offset: 1 - bit_size: 1 - description: Capture mode - name: CM - - bit_offset: 2 - bit_size: 1 - description: Crop feature - name: CROP - - bit_offset: 3 - bit_size: 1 - description: JPEG format - name: JPEG - - bit_offset: 4 - bit_size: 1 - description: Embedded synchronization select - name: ESS - - bit_offset: 5 - bit_size: 1 - description: Pixel clock polarity - name: PCKPOL - - bit_offset: 6 - bit_size: 1 - description: Horizontal synchronization polarity - name: HSPOL - - bit_offset: 7 - bit_size: 1 - description: Vertical synchronization polarity - name: VSPOL - - bit_offset: 8 - bit_size: 2 - description: Frame capture rate control - name: FCRC - - bit_offset: 10 - bit_size: 2 - description: Extended data mode - name: EDM - - bit_offset: 14 - bit_size: 1 - description: DCMI enable - name: ENABLE + - name: CAPTURE + description: Capture enable + bit_offset: 0 + bit_size: 1 + - name: CM + description: Capture mode + bit_offset: 1 + bit_size: 1 + - name: CROP + description: Crop feature + bit_offset: 2 + bit_size: 1 + - name: JPEG + description: JPEG format + bit_offset: 3 + bit_size: 1 + - name: ESS + description: Embedded synchronization select + bit_offset: 4 + bit_size: 1 + - name: PCKPOL + description: Pixel clock polarity + bit_offset: 5 + bit_size: 1 + - name: HSPOL + description: Horizontal synchronization polarity + bit_offset: 6 + bit_size: 1 + - name: VSPOL + description: Vertical synchronization polarity + bit_offset: 7 + bit_size: 1 + - name: FCRC + description: Frame capture rate control + bit_offset: 8 + bit_size: 2 + - name: EDM + description: Extended data mode + bit_offset: 10 + bit_size: 2 + - name: ENABLE + description: DCMI enable + bit_offset: 14 + bit_size: 1 fieldset/CWSIZE: description: crop window size fields: - - bit_offset: 0 - bit_size: 14 - description: Capture count - name: CAPCNT - - bit_offset: 16 - bit_size: 14 - description: Vertical line count - name: VLINE + - name: CAPCNT + description: Capture count + bit_offset: 0 + bit_size: 14 + - name: VLINE + description: Vertical line count + bit_offset: 16 + bit_size: 14 fieldset/CWSTRT: description: crop window start fields: - - bit_offset: 0 - bit_size: 14 - description: Horizontal offset count - name: HOFFCNT - - bit_offset: 16 - bit_size: 13 - description: Vertical start line count - name: VST + - name: HOFFCNT + description: Horizontal offset count + bit_offset: 0 + bit_size: 14 + - name: VST + description: Vertical start line count + bit_offset: 16 + bit_size: 13 fieldset/DR: description: data register fields: - - bit_offset: 0 - bit_size: 8 - description: Data byte 0 - name: Byte0 - - bit_offset: 8 - bit_size: 8 - description: Data byte 1 - name: Byte1 - - bit_offset: 16 - bit_size: 8 - description: Data byte 2 - name: Byte2 - - bit_offset: 24 - bit_size: 8 - description: Data byte 3 - name: Byte3 + - name: Byte0 + description: Data byte 0 + bit_offset: 0 + bit_size: 8 + - name: Byte1 + description: Data byte 1 + bit_offset: 8 + bit_size: 8 + - name: Byte2 + description: Data byte 2 + bit_offset: 16 + bit_size: 8 + - name: Byte3 + description: Data byte 3 + bit_offset: 24 + bit_size: 8 fieldset/ESCR: description: embedded synchronization code register fields: - - bit_offset: 0 - bit_size: 8 - description: Frame start delimiter code - name: FSC - - bit_offset: 8 - bit_size: 8 - description: Line start delimiter code - name: LSC - - bit_offset: 16 - bit_size: 8 - description: Line end delimiter code - name: LEC - - bit_offset: 24 - bit_size: 8 - description: Frame end delimiter code - name: FEC + - name: FSC + description: Frame start delimiter code + bit_offset: 0 + bit_size: 8 + - name: LSC + description: Line start delimiter code + bit_offset: 8 + bit_size: 8 + - name: LEC + description: Line end delimiter code + bit_offset: 16 + bit_size: 8 + - name: FEC + description: Frame end delimiter code + bit_offset: 24 + bit_size: 8 fieldset/ESUR: description: embedded synchronization unmask register fields: - - bit_offset: 0 - bit_size: 8 - description: Frame start delimiter unmask - name: FSU - - bit_offset: 8 - bit_size: 8 - description: Line start delimiter unmask - name: LSU - - bit_offset: 16 - bit_size: 8 - description: Line end delimiter unmask - name: LEU - - bit_offset: 24 - bit_size: 8 - description: Frame end delimiter unmask - name: FEU + - name: FSU + description: Frame start delimiter unmask + bit_offset: 0 + bit_size: 8 + - name: LSU + description: Line start delimiter unmask + bit_offset: 8 + bit_size: 8 + - name: LEU + description: Line end delimiter unmask + bit_offset: 16 + bit_size: 8 + - name: FEU + description: Frame end delimiter unmask + bit_offset: 24 + bit_size: 8 fieldset/ICR: description: interrupt clear register fields: - - bit_offset: 0 - bit_size: 1 - description: Capture complete interrupt status clear - name: FRAME_ISC - - bit_offset: 1 - bit_size: 1 - description: Overrun interrupt status clear - name: OVR_ISC - - bit_offset: 2 - bit_size: 1 - description: Synchronization error interrupt status clear - name: ERR_ISC - - bit_offset: 3 - bit_size: 1 - description: Vertical synch interrupt status clear - name: VSYNC_ISC - - bit_offset: 4 - bit_size: 1 - description: line interrupt status clear - name: LINE_ISC + - name: FRAME_ISC + description: Capture complete interrupt status clear + bit_offset: 0 + bit_size: 1 + - name: OVR_ISC + description: Overrun interrupt status clear + bit_offset: 1 + bit_size: 1 + - name: ERR_ISC + description: Synchronization error interrupt status clear + bit_offset: 2 + bit_size: 1 + - name: VSYNC_ISC + description: Vertical synch interrupt status clear + bit_offset: 3 + bit_size: 1 + - name: LINE_ISC + description: line interrupt status clear + bit_offset: 4 + bit_size: 1 fieldset/IER: description: interrupt enable register fields: - - bit_offset: 0 - bit_size: 1 - description: Capture complete interrupt enable - name: FRAME_IE - - bit_offset: 1 - bit_size: 1 - description: Overrun interrupt enable - name: OVR_IE - - bit_offset: 2 - bit_size: 1 - description: Synchronization error interrupt enable - name: ERR_IE - - bit_offset: 3 - bit_size: 1 - description: VSYNC interrupt enable - name: VSYNC_IE - - bit_offset: 4 - bit_size: 1 - description: Line interrupt enable - name: LINE_IE + - name: FRAME_IE + description: Capture complete interrupt enable + bit_offset: 0 + bit_size: 1 + - name: OVR_IE + description: Overrun interrupt enable + bit_offset: 1 + bit_size: 1 + - name: ERR_IE + description: Synchronization error interrupt enable + bit_offset: 2 + bit_size: 1 + - name: VSYNC_IE + description: VSYNC interrupt enable + bit_offset: 3 + bit_size: 1 + - name: LINE_IE + description: Line interrupt enable + bit_offset: 4 + bit_size: 1 fieldset/MIS: description: masked interrupt status register fields: - - bit_offset: 0 - bit_size: 1 - description: Capture complete masked interrupt status - name: FRAME_MIS - - bit_offset: 1 - bit_size: 1 - description: Overrun masked interrupt status - name: OVR_MIS - - bit_offset: 2 - bit_size: 1 - description: Synchronization error masked interrupt status - name: ERR_MIS - - bit_offset: 3 - bit_size: 1 - description: VSYNC masked interrupt status - name: VSYNC_MIS - - bit_offset: 4 - bit_size: 1 - description: Line masked interrupt status - name: LINE_MIS + - name: FRAME_MIS + description: Capture complete masked interrupt status + bit_offset: 0 + bit_size: 1 + - name: OVR_MIS + description: Overrun masked interrupt status + bit_offset: 1 + bit_size: 1 + - name: ERR_MIS + description: Synchronization error masked interrupt status + bit_offset: 2 + bit_size: 1 + - name: VSYNC_MIS + description: VSYNC masked interrupt status + bit_offset: 3 + bit_size: 1 + - name: LINE_MIS + description: Line masked interrupt status + bit_offset: 4 + bit_size: 1 fieldset/RIS: description: raw interrupt status register fields: - - bit_offset: 0 - bit_size: 1 - description: Capture complete raw interrupt status - name: FRAME_RIS - - bit_offset: 1 - bit_size: 1 - description: Overrun raw interrupt status - name: OVR_RIS - - bit_offset: 2 - bit_size: 1 - description: Synchronization error raw interrupt status - name: ERR_RIS - - bit_offset: 3 - bit_size: 1 - description: VSYNC raw interrupt status - name: VSYNC_RIS - - bit_offset: 4 - bit_size: 1 - description: Line raw interrupt status - name: LINE_RIS + - name: FRAME_RIS + description: Capture complete raw interrupt status + bit_offset: 0 + bit_size: 1 + - name: OVR_RIS + description: Overrun raw interrupt status + bit_offset: 1 + bit_size: 1 + - name: ERR_RIS + description: Synchronization error raw interrupt status + bit_offset: 2 + bit_size: 1 + - name: VSYNC_RIS + description: VSYNC raw interrupt status + bit_offset: 3 + bit_size: 1 + - name: LINE_RIS + description: Line raw interrupt status + bit_offset: 4 + bit_size: 1 fieldset/SR: description: status register fields: - - bit_offset: 0 - bit_size: 1 - description: HSYNC - name: HSYNC - - bit_offset: 1 - bit_size: 1 - description: VSYNC - name: VSYNC - - bit_offset: 2 - bit_size: 1 - description: FIFO not empty - name: FNE + - name: HSYNC + description: HSYNC + bit_offset: 0 + bit_size: 1 + - name: VSYNC + description: VSYNC + bit_offset: 1 + bit_size: 1 + - name: FNE + description: FIFO not empty + bit_offset: 2 + bit_size: 1 diff --git a/data/registers/dma2d_v1.yaml b/data/registers/dma2d_v1.yaml index 5acc5fe..5e778ac 100644 --- a/data/registers/dma2d_v1.yaml +++ b/data/registers/dma2d_v1.yaml @@ -2,727 +2,727 @@ block/DMA2D: description: DMA2D controller items: - - byte_offset: 0 - description: control register - fieldset: CR - name: CR - - access: Read - byte_offset: 4 - description: Interrupt Status Register - fieldset: ISR - name: ISR - - byte_offset: 8 - description: interrupt flag clear register - fieldset: IFCR - name: IFCR - - byte_offset: 12 - description: foreground memory address register - fieldset: FGMAR - name: FGMAR - - byte_offset: 16 - description: foreground offset register - fieldset: FGOR - name: FGOR - - byte_offset: 20 - description: background memory address register - fieldset: BGMAR - name: BGMAR - - byte_offset: 24 - description: background offset register - fieldset: BGOR - name: BGOR - - byte_offset: 28 - description: foreground PFC control register - fieldset: FGPFCCR - name: FGPFCCR - - byte_offset: 32 - description: foreground color register - fieldset: FGCOLR - name: FGCOLR - - byte_offset: 36 - description: background PFC control register - fieldset: BGPFCCR - name: BGPFCCR - - byte_offset: 40 - description: background color register - fieldset: BGCOLR - name: BGCOLR - - byte_offset: 44 - description: foreground CLUT memory address register - fieldset: FGCMAR - name: FGCMAR - - byte_offset: 48 - description: background CLUT memory address register - fieldset: BGCMAR - name: BGCMAR - - byte_offset: 52 - description: output PFC control register - fieldset: OPFCCR - name: OPFCCR - - byte_offset: 56 - description: output color register - fieldset: OCOLR - name: OCOLR - - byte_offset: 60 - description: output memory address register - fieldset: OMAR - name: OMAR - - byte_offset: 64 - description: output offset register - fieldset: OOR - name: OOR - - byte_offset: 68 - description: number of line register - fieldset: NLR - name: NLR - - byte_offset: 72 - description: line watermark register - fieldset: LWR - name: LWR - - byte_offset: 76 - description: AHB master timer configuration register - fieldset: AMTCR - name: AMTCR - - byte_offset: 1024 - description: FGCLUT - fieldset: FGCLUT - name: FGCLUT - - byte_offset: 2048 - description: BGCLUT - fieldset: BGCLUT - name: BGCLUT -enum/ABORT: - bit_size: 1 - variants: - - description: Transfer abort requested - name: AbortRequest - value: 1 -enum/BGPFCCR_AM: - bit_size: 2 - variants: - - description: No modification of alpha channel - name: NoModify - value: 0 - - description: Replace with value in ALPHA[7:0] - name: Replace - value: 1 - - description: Multiply with value in ALPHA[7:0] - name: Multiply - value: 2 -enum/BGPFCCR_CCM: - bit_size: 1 - variants: - - description: CLUT color format ARGB8888 - name: ARGB8888 - value: 0 - - description: CLUT color format RGB888 - name: RGB888 - value: 1 -enum/BGPFCCR_CM: - bit_size: 4 - variants: - - description: Color mode ARGB8888 - name: ARGB8888 - value: 0 - - description: Color mode RGB888 - name: RGB888 - value: 1 - - description: Color mode RGB565 - name: RGB565 - value: 2 - - description: Color mode ARGB1555 - name: ARGB1555 - value: 3 - - description: Color mode ARGB4444 - name: ARGB4444 - value: 4 - - description: Color mode L8 - name: L8 - value: 5 - - description: Color mode AL44 - name: AL44 - value: 6 - - description: Color mode AL88 - name: AL88 - value: 7 - - description: Color mode L4 - name: L4 - value: 8 - - description: Color mode A8 - name: A8 - value: 9 - - description: Color mode A4 - name: A4 - value: 10 -enum/BGPFCCR_START: - bit_size: 1 - variants: - - description: Start the automatic loading of the CLUT - name: Start - value: 1 -enum/CAECIF: - bit_size: 1 - variants: - - description: Clear the CAEIF flag in the ISR register - name: Clear - value: 1 -enum/CAEIE: - bit_size: 1 - variants: - - description: CAE interrupt disabled - name: Disabled - value: 0 - - description: CAE interrupt enabled - name: Enabled - value: 1 -enum/CCEIF: - bit_size: 1 - variants: - - description: Clear the CEIF flag in the ISR register - name: Clear - value: 1 -enum/CCTCIF: - bit_size: 1 - variants: - - description: Clear the CTCIF flag in the ISR register - name: Clear - value: 1 -enum/CEIE: - bit_size: 1 - variants: - - description: CE interrupt disabled - name: Disabled - value: 0 - - description: CE interrupt enabled - name: Enabled - value: 1 -enum/CR_START: - bit_size: 1 - variants: - - description: Launch the DMA2D - name: Start - value: 1 -enum/CTCIE: - bit_size: 1 - variants: - - description: CTC interrupt disabled - name: Disabled - value: 0 - - description: CTC interrupt enabled - name: Enabled - value: 1 -enum/CTCIF: - bit_size: 1 - variants: - - description: Clear the TCIF flag in the ISR register - name: Clear - value: 1 -enum/CTEIF: - bit_size: 1 - variants: - - description: Clear the TEIF flag in the ISR register - name: Clear - value: 1 -enum/CTWIF: - bit_size: 1 - variants: - - description: Clear the TWIF flag in the ISR register - name: Clear - value: 1 -enum/EN: - bit_size: 1 - variants: - - description: Disabled AHB/AXI dead-time functionality - name: Disabled - value: 0 - - description: Enabled AHB/AXI dead-time functionality - name: Enabled - value: 1 -enum/FGPFCCR_AM: - bit_size: 2 - variants: - - description: No modification of alpha channel - name: NoModify - value: 0 - - description: Replace with value in ALPHA[7:0] - name: Replace - value: 1 - - description: Multiply with value in ALPHA[7:0] - name: Multiply - value: 2 -enum/FGPFCCR_CCM: - bit_size: 1 - variants: - - description: CLUT color format ARGB8888 - name: ARGB8888 - value: 0 - - description: CLUT color format RGB888 - name: RGB888 - value: 1 -enum/FGPFCCR_CM: - bit_size: 4 - variants: - - description: Color mode ARGB8888 - name: ARGB8888 - value: 0 - - description: Color mode RGB888 - name: RGB888 - value: 1 - - description: Color mode RGB565 - name: RGB565 - value: 2 - - description: Color mode ARGB1555 - name: ARGB1555 - value: 3 - - description: Color mode ARGB4444 - name: ARGB4444 - value: 4 - - description: Color mode L8 - name: L8 - value: 5 - - description: Color mode AL44 - name: AL44 - value: 6 - - description: Color mode AL88 - name: AL88 - value: 7 - - description: Color mode L4 - name: L4 - value: 8 - - description: Color mode A8 - name: A8 - value: 9 - - description: Color mode A4 - name: A4 - value: 10 -enum/FGPFCCR_START: - bit_size: 1 - variants: - - description: Start the automatic loading of the CLUT - name: Start - value: 1 -enum/MODE: - bit_size: 2 - variants: - - description: Memory-to-memory (FG fetch only) - name: MemoryToMemory - value: 0 - - description: Memory-to-memory with PFC (FG fetch only with FG PFC active) - name: MemoryToMemoryPFC - value: 1 - - description: Memory-to-memory with blending (FG and BG fetch with PFC and blending) - name: MemoryToMemoryPFCBlending - value: 2 - - description: Register-to-memory - name: RegisterToMemory - value: 3 -enum/OPFCCR_CM: - bit_size: 3 - variants: - - description: ARGB8888 - name: ARGB8888 - value: 0 - - description: RGB888 - name: RGB888 - value: 1 - - description: RGB565 - name: RGB565 - value: 2 - - description: ARGB1555 - name: ARGB1555 - value: 3 - - description: ARGB4444 - name: ARGB4444 - value: 4 -enum/SUSP: - bit_size: 1 - variants: - - description: Transfer not suspended - name: NotSuspended - value: 0 - - description: Transfer suspended - name: Suspended - value: 1 -enum/TCIE: - bit_size: 1 - variants: - - description: TC interrupt disabled - name: Disabled - value: 0 - - description: TC interrupt enabled - name: Enabled - value: 1 -enum/TEIE: - bit_size: 1 - variants: - - description: TE interrupt disabled - name: Disabled - value: 0 - - description: TE interrupt enabled - name: Enabled - value: 1 -enum/TWIE: - bit_size: 1 - variants: - - description: TW interrupt disabled - name: Disabled - value: 0 - - description: TW interrupt enabled - name: Enabled - value: 1 + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: ISR + description: Interrupt Status Register + byte_offset: 4 + access: Read + fieldset: ISR + - name: IFCR + description: interrupt flag clear register + byte_offset: 8 + fieldset: IFCR + - name: FGMAR + description: foreground memory address register + byte_offset: 12 + fieldset: FGMAR + - name: FGOR + description: foreground offset register + byte_offset: 16 + fieldset: FGOR + - name: BGMAR + description: background memory address register + byte_offset: 20 + fieldset: BGMAR + - name: BGOR + description: background offset register + byte_offset: 24 + fieldset: BGOR + - name: FGPFCCR + description: foreground PFC control register + byte_offset: 28 + fieldset: FGPFCCR + - name: FGCOLR + description: foreground color register + byte_offset: 32 + fieldset: FGCOLR + - name: BGPFCCR + description: background PFC control register + byte_offset: 36 + fieldset: BGPFCCR + - name: BGCOLR + description: background color register + byte_offset: 40 + fieldset: BGCOLR + - name: FGCMAR + description: foreground CLUT memory address register + byte_offset: 44 + fieldset: FGCMAR + - name: BGCMAR + description: background CLUT memory address register + byte_offset: 48 + fieldset: BGCMAR + - name: OPFCCR + description: output PFC control register + byte_offset: 52 + fieldset: OPFCCR + - name: OCOLR + description: output color register + byte_offset: 56 + fieldset: OCOLR + - name: OMAR + description: output memory address register + byte_offset: 60 + fieldset: OMAR + - name: OOR + description: output offset register + byte_offset: 64 + fieldset: OOR + - name: NLR + description: number of line register + byte_offset: 68 + fieldset: NLR + - name: LWR + description: line watermark register + byte_offset: 72 + fieldset: LWR + - name: AMTCR + description: AHB master timer configuration register + byte_offset: 76 + fieldset: AMTCR + - name: FGCLUT + description: FGCLUT + byte_offset: 1024 + fieldset: FGCLUT + - name: BGCLUT + description: BGCLUT + byte_offset: 2048 + fieldset: BGCLUT fieldset/AMTCR: description: AHB master timer configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: Enable - enum: EN - name: EN - - bit_offset: 8 - bit_size: 8 - description: Dead Time - name: DT + - name: EN + description: Enable + bit_offset: 0 + bit_size: 1 + enum: EN + - name: DT + description: Dead Time + bit_offset: 8 + bit_size: 8 fieldset/BGCLUT: description: BGCLUT fields: - - bit_offset: 0 - bit_size: 8 - description: BLUE - name: BLUE - - bit_offset: 8 - bit_size: 8 - description: GREEN - name: GREEN - - bit_offset: 16 - bit_size: 8 - description: RED - name: RED - - bit_offset: 24 - bit_size: 8 - description: APLHA - name: APLHA + - name: BLUE + description: BLUE + bit_offset: 0 + bit_size: 8 + - name: GREEN + description: GREEN + bit_offset: 8 + bit_size: 8 + - name: RED + description: RED + bit_offset: 16 + bit_size: 8 + - name: APLHA + description: APLHA + bit_offset: 24 + bit_size: 8 fieldset/BGCMAR: description: background CLUT memory address register fields: - - bit_offset: 0 - bit_size: 32 - description: Memory address - name: MA + - name: MA + description: Memory address + bit_offset: 0 + bit_size: 32 fieldset/BGCOLR: description: background color register fields: - - bit_offset: 0 - bit_size: 8 - description: Blue Value - name: BLUE - - bit_offset: 8 - bit_size: 8 - description: Green Value - name: GREEN - - bit_offset: 16 - bit_size: 8 - description: Red Value - name: RED + - name: BLUE + description: Blue Value + bit_offset: 0 + bit_size: 8 + - name: GREEN + description: Green Value + bit_offset: 8 + bit_size: 8 + - name: RED + description: Red Value + bit_offset: 16 + bit_size: 8 fieldset/BGMAR: description: background memory address register fields: - - bit_offset: 0 - bit_size: 32 - description: Memory address - name: MA + - name: MA + description: Memory address + bit_offset: 0 + bit_size: 32 fieldset/BGOR: description: background offset register fields: - - bit_offset: 0 - bit_size: 14 - description: Line offset - name: LO + - name: LO + description: Line offset + bit_offset: 0 + bit_size: 14 fieldset/BGPFCCR: description: background PFC control register fields: - - bit_offset: 0 - bit_size: 4 - description: Color mode - enum: BGPFCCR_CM - name: CM - - bit_offset: 4 - bit_size: 1 - description: CLUT Color mode - enum: BGPFCCR_CCM - name: CCM - - bit_offset: 5 - bit_size: 1 - description: Start - enum: BGPFCCR_START - name: START - - bit_offset: 8 - bit_size: 8 - description: CLUT size - name: CS - - bit_offset: 16 - bit_size: 2 - description: Alpha mode - enum: BGPFCCR_AM - name: AM - - bit_offset: 24 - bit_size: 8 - description: Alpha value - name: ALPHA + - name: CM + description: Color mode + bit_offset: 0 + bit_size: 4 + enum: BGPFCCR_CM + - name: CCM + description: CLUT Color mode + bit_offset: 4 + bit_size: 1 + enum: BGPFCCR_CCM + - name: START + description: Start + bit_offset: 5 + bit_size: 1 + enum: BGPFCCR_START + - name: CS + description: CLUT size + bit_offset: 8 + bit_size: 8 + - name: AM + description: Alpha mode + bit_offset: 16 + bit_size: 2 + enum: BGPFCCR_AM + - name: ALPHA + description: Alpha value + bit_offset: 24 + bit_size: 8 fieldset/CR: description: control register fields: - - bit_offset: 0 - bit_size: 1 - description: Start - enum: CR_START - name: START - - bit_offset: 1 - bit_size: 1 - description: Suspend - enum: SUSP - name: SUSP - - bit_offset: 2 - bit_size: 1 - description: Abort - enum: ABORT - name: ABORT - - bit_offset: 8 - bit_size: 1 - description: Transfer error interrupt enable - enum: TEIE - name: TEIE - - bit_offset: 9 - bit_size: 1 - description: Transfer complete interrupt enable - enum: TCIE - name: TCIE - - bit_offset: 10 - bit_size: 1 - description: Transfer watermark interrupt enable - enum: TWIE - name: TWIE - - bit_offset: 11 - bit_size: 1 - description: CLUT access error interrupt enable - enum: CAEIE - name: CAEIE - - bit_offset: 12 - bit_size: 1 - description: CLUT transfer complete interrupt enable - enum: CTCIE - name: CTCIE - - bit_offset: 13 - bit_size: 1 - description: Configuration Error Interrupt Enable - enum: CEIE - name: CEIE - - bit_offset: 16 - bit_size: 2 - description: DMA2D mode - enum: MODE - name: MODE + - name: START + description: Start + bit_offset: 0 + bit_size: 1 + enum: CR_START + - name: SUSP + description: Suspend + bit_offset: 1 + bit_size: 1 + enum: SUSP + - name: ABORT + description: Abort + bit_offset: 2 + bit_size: 1 + enum: ABORT + - name: TEIE + description: Transfer error interrupt enable + bit_offset: 8 + bit_size: 1 + enum: TEIE + - name: TCIE + description: Transfer complete interrupt enable + bit_offset: 9 + bit_size: 1 + enum: TCIE + - name: TWIE + description: Transfer watermark interrupt enable + bit_offset: 10 + bit_size: 1 + enum: TWIE + - name: CAEIE + description: CLUT access error interrupt enable + bit_offset: 11 + bit_size: 1 + enum: CAEIE + - name: CTCIE + description: CLUT transfer complete interrupt enable + bit_offset: 12 + bit_size: 1 + enum: CTCIE + - name: CEIE + description: Configuration Error Interrupt Enable + bit_offset: 13 + bit_size: 1 + enum: CEIE + - name: MODE + description: DMA2D mode + bit_offset: 16 + bit_size: 2 + enum: MODE fieldset/FGCLUT: description: FGCLUT fields: - - bit_offset: 0 - bit_size: 8 - description: BLUE - name: BLUE - - bit_offset: 8 - bit_size: 8 - description: GREEN - name: GREEN - - bit_offset: 16 - bit_size: 8 - description: RED - name: RED - - bit_offset: 24 - bit_size: 8 - description: APLHA - name: APLHA + - name: BLUE + description: BLUE + bit_offset: 0 + bit_size: 8 + - name: GREEN + description: GREEN + bit_offset: 8 + bit_size: 8 + - name: RED + description: RED + bit_offset: 16 + bit_size: 8 + - name: APLHA + description: APLHA + bit_offset: 24 + bit_size: 8 fieldset/FGCMAR: description: foreground CLUT memory address register fields: - - bit_offset: 0 - bit_size: 32 - description: Memory Address - name: MA + - name: MA + description: Memory Address + bit_offset: 0 + bit_size: 32 fieldset/FGCOLR: description: foreground color register fields: - - bit_offset: 0 - bit_size: 8 - description: Blue Value - name: BLUE - - bit_offset: 8 - bit_size: 8 - description: Green Value - name: GREEN - - bit_offset: 16 - bit_size: 8 - description: Red Value - name: RED + - name: BLUE + description: Blue Value + bit_offset: 0 + bit_size: 8 + - name: GREEN + description: Green Value + bit_offset: 8 + bit_size: 8 + - name: RED + description: Red Value + bit_offset: 16 + bit_size: 8 fieldset/FGMAR: description: foreground memory address register fields: - - bit_offset: 0 - bit_size: 32 - description: Memory address - name: MA + - name: MA + description: Memory address + bit_offset: 0 + bit_size: 32 fieldset/FGOR: description: foreground offset register fields: - - bit_offset: 0 - bit_size: 14 - description: Line offset - name: LO + - name: LO + description: Line offset + bit_offset: 0 + bit_size: 14 fieldset/FGPFCCR: description: foreground PFC control register fields: - - bit_offset: 0 - bit_size: 4 - description: Color mode - enum: FGPFCCR_CM - name: CM - - bit_offset: 4 - bit_size: 1 - description: CLUT color mode - enum: FGPFCCR_CCM - name: CCM - - bit_offset: 5 - bit_size: 1 - description: Start - enum: FGPFCCR_START - name: START - - bit_offset: 8 - bit_size: 8 - description: CLUT size - name: CS - - bit_offset: 16 - bit_size: 2 - description: Alpha mode - enum: FGPFCCR_AM - name: AM - - bit_offset: 24 - bit_size: 8 - description: Alpha value - name: ALPHA + - name: CM + description: Color mode + bit_offset: 0 + bit_size: 4 + enum: FGPFCCR_CM + - name: CCM + description: CLUT color mode + bit_offset: 4 + bit_size: 1 + enum: FGPFCCR_CCM + - name: START + description: Start + bit_offset: 5 + bit_size: 1 + enum: FGPFCCR_START + - name: CS + description: CLUT size + bit_offset: 8 + bit_size: 8 + - name: AM + description: Alpha mode + bit_offset: 16 + bit_size: 2 + enum: FGPFCCR_AM + - name: ALPHA + description: Alpha value + bit_offset: 24 + bit_size: 8 fieldset/IFCR: description: interrupt flag clear register fields: - - bit_offset: 0 - bit_size: 1 - description: Clear Transfer error interrupt flag - enum: CTEIF - name: CTEIF - - bit_offset: 1 - bit_size: 1 - description: Clear transfer complete interrupt flag - enum: CTCIF - name: CTCIF - - bit_offset: 2 - bit_size: 1 - description: Clear transfer watermark interrupt flag - enum: CTWIF - name: CTWIF - - bit_offset: 3 - bit_size: 1 - description: Clear CLUT access error interrupt flag - enum: CAECIF - name: CAECIF - - bit_offset: 4 - bit_size: 1 - description: Clear CLUT transfer complete interrupt flag - enum: CCTCIF - name: CCTCIF - - bit_offset: 5 - bit_size: 1 - description: Clear configuration error interrupt flag - enum: CCEIF - name: CCEIF + - name: CTEIF + description: Clear Transfer error interrupt flag + bit_offset: 0 + bit_size: 1 + enum: CTEIF + - name: CTCIF + description: Clear transfer complete interrupt flag + bit_offset: 1 + bit_size: 1 + enum: CTCIF + - name: CTWIF + description: Clear transfer watermark interrupt flag + bit_offset: 2 + bit_size: 1 + enum: CTWIF + - name: CAECIF + description: Clear CLUT access error interrupt flag + bit_offset: 3 + bit_size: 1 + enum: CAECIF + - name: CCTCIF + description: Clear CLUT transfer complete interrupt flag + bit_offset: 4 + bit_size: 1 + enum: CCTCIF + - name: CCEIF + description: Clear configuration error interrupt flag + bit_offset: 5 + bit_size: 1 + enum: CCEIF fieldset/ISR: description: Interrupt Status Register fields: - - bit_offset: 0 - bit_size: 1 - description: Transfer error interrupt flag - name: TEIF - - bit_offset: 1 - bit_size: 1 - description: Transfer complete interrupt flag - name: TCIF - - bit_offset: 2 - bit_size: 1 - description: Transfer watermark interrupt flag - name: TWIF - - bit_offset: 3 - bit_size: 1 - description: CLUT access error interrupt flag - name: CAEIF - - bit_offset: 4 - bit_size: 1 - description: CLUT transfer complete interrupt flag - name: CTCIF - - bit_offset: 5 - bit_size: 1 - description: Configuration error interrupt flag - name: CEIF + - name: TEIF + description: Transfer error interrupt flag + bit_offset: 0 + bit_size: 1 + - name: TCIF + description: Transfer complete interrupt flag + bit_offset: 1 + bit_size: 1 + - name: TWIF + description: Transfer watermark interrupt flag + bit_offset: 2 + bit_size: 1 + - name: CAEIF + description: CLUT access error interrupt flag + bit_offset: 3 + bit_size: 1 + - name: CTCIF + description: CLUT transfer complete interrupt flag + bit_offset: 4 + bit_size: 1 + - name: CEIF + description: Configuration error interrupt flag + bit_offset: 5 + bit_size: 1 fieldset/LWR: description: line watermark register fields: - - bit_offset: 0 - bit_size: 16 - description: Line watermark - name: LW + - name: LW + description: Line watermark + bit_offset: 0 + bit_size: 16 fieldset/NLR: description: number of line register fields: - - bit_offset: 0 - bit_size: 16 - description: Number of lines - name: NL - - bit_offset: 16 - bit_size: 14 - description: Pixel per lines - name: PL + - name: NL + description: Number of lines + bit_offset: 0 + bit_size: 16 + - name: PL + description: Pixel per lines + bit_offset: 16 + bit_size: 14 fieldset/OCOLR: description: output color register fields: - - bit_offset: 0 - bit_size: 8 - description: Blue Value - name: BLUE - - bit_offset: 8 - bit_size: 8 - description: Green Value - name: GREEN - - bit_offset: 16 - bit_size: 8 - description: Red Value - name: RED - - bit_offset: 24 - bit_size: 8 - description: Alpha Channel Value - name: APLHA + - name: BLUE + description: Blue Value + bit_offset: 0 + bit_size: 8 + - name: GREEN + description: Green Value + bit_offset: 8 + bit_size: 8 + - name: RED + description: Red Value + bit_offset: 16 + bit_size: 8 + - name: APLHA + description: Alpha Channel Value + bit_offset: 24 + bit_size: 8 fieldset/OMAR: description: output memory address register fields: - - bit_offset: 0 - bit_size: 32 - description: Memory Address - name: MA + - name: MA + description: Memory Address + bit_offset: 0 + bit_size: 32 fieldset/OOR: description: output offset register fields: - - bit_offset: 0 - bit_size: 14 - description: Line Offset - name: LO + - name: LO + description: Line Offset + bit_offset: 0 + bit_size: 14 fieldset/OPFCCR: description: output PFC control register fields: - - bit_offset: 0 - bit_size: 3 - description: Color mode - enum: OPFCCR_CM - name: CM + - name: CM + description: Color mode + bit_offset: 0 + bit_size: 3 + enum: OPFCCR_CM +enum/ABORT: + bit_size: 1 + variants: + - name: AbortRequest + description: Transfer abort requested + value: 1 +enum/BGPFCCR_AM: + bit_size: 2 + variants: + - name: NoModify + description: No modification of alpha channel + value: 0 + - name: Replace + description: "Replace with value in ALPHA[7:0]" + value: 1 + - name: Multiply + description: "Multiply with value in ALPHA[7:0]" + value: 2 +enum/BGPFCCR_CCM: + bit_size: 1 + variants: + - name: ARGB8888 + description: CLUT color format ARGB8888 + value: 0 + - name: RGB888 + description: CLUT color format RGB888 + value: 1 +enum/BGPFCCR_CM: + bit_size: 4 + variants: + - name: ARGB8888 + description: Color mode ARGB8888 + value: 0 + - name: RGB888 + description: Color mode RGB888 + value: 1 + - name: RGB565 + description: Color mode RGB565 + value: 2 + - name: ARGB1555 + description: Color mode ARGB1555 + value: 3 + - name: ARGB4444 + description: Color mode ARGB4444 + value: 4 + - name: L8 + description: Color mode L8 + value: 5 + - name: AL44 + description: Color mode AL44 + value: 6 + - name: AL88 + description: Color mode AL88 + value: 7 + - name: L4 + description: Color mode L4 + value: 8 + - name: A8 + description: Color mode A8 + value: 9 + - name: A4 + description: Color mode A4 + value: 10 +enum/BGPFCCR_START: + bit_size: 1 + variants: + - name: Start + description: Start the automatic loading of the CLUT + value: 1 +enum/CAECIF: + bit_size: 1 + variants: + - name: Clear + description: Clear the CAEIF flag in the ISR register + value: 1 +enum/CAEIE: + bit_size: 1 + variants: + - name: Disabled + description: CAE interrupt disabled + value: 0 + - name: Enabled + description: CAE interrupt enabled + value: 1 +enum/CCEIF: + bit_size: 1 + variants: + - name: Clear + description: Clear the CEIF flag in the ISR register + value: 1 +enum/CCTCIF: + bit_size: 1 + variants: + - name: Clear + description: Clear the CTCIF flag in the ISR register + value: 1 +enum/CEIE: + bit_size: 1 + variants: + - name: Disabled + description: CE interrupt disabled + value: 0 + - name: Enabled + description: CE interrupt enabled + value: 1 +enum/CR_START: + bit_size: 1 + variants: + - name: Start + description: Launch the DMA2D + value: 1 +enum/CTCIE: + bit_size: 1 + variants: + - name: Disabled + description: CTC interrupt disabled + value: 0 + - name: Enabled + description: CTC interrupt enabled + value: 1 +enum/CTCIF: + bit_size: 1 + variants: + - name: Clear + description: Clear the TCIF flag in the ISR register + value: 1 +enum/CTEIF: + bit_size: 1 + variants: + - name: Clear + description: Clear the TEIF flag in the ISR register + value: 1 +enum/CTWIF: + bit_size: 1 + variants: + - name: Clear + description: Clear the TWIF flag in the ISR register + value: 1 +enum/EN: + bit_size: 1 + variants: + - name: Disabled + description: Disabled AHB/AXI dead-time functionality + value: 0 + - name: Enabled + description: Enabled AHB/AXI dead-time functionality + value: 1 +enum/FGPFCCR_AM: + bit_size: 2 + variants: + - name: NoModify + description: No modification of alpha channel + value: 0 + - name: Replace + description: "Replace with value in ALPHA[7:0]" + value: 1 + - name: Multiply + description: "Multiply with value in ALPHA[7:0]" + value: 2 +enum/FGPFCCR_CCM: + bit_size: 1 + variants: + - name: ARGB8888 + description: CLUT color format ARGB8888 + value: 0 + - name: RGB888 + description: CLUT color format RGB888 + value: 1 +enum/FGPFCCR_CM: + bit_size: 4 + variants: + - name: ARGB8888 + description: Color mode ARGB8888 + value: 0 + - name: RGB888 + description: Color mode RGB888 + value: 1 + - name: RGB565 + description: Color mode RGB565 + value: 2 + - name: ARGB1555 + description: Color mode ARGB1555 + value: 3 + - name: ARGB4444 + description: Color mode ARGB4444 + value: 4 + - name: L8 + description: Color mode L8 + value: 5 + - name: AL44 + description: Color mode AL44 + value: 6 + - name: AL88 + description: Color mode AL88 + value: 7 + - name: L4 + description: Color mode L4 + value: 8 + - name: A8 + description: Color mode A8 + value: 9 + - name: A4 + description: Color mode A4 + value: 10 +enum/FGPFCCR_START: + bit_size: 1 + variants: + - name: Start + description: Start the automatic loading of the CLUT + value: 1 +enum/MODE: + bit_size: 2 + variants: + - name: MemoryToMemory + description: Memory-to-memory (FG fetch only) + value: 0 + - name: MemoryToMemoryPFC + description: Memory-to-memory with PFC (FG fetch only with FG PFC active) + value: 1 + - name: MemoryToMemoryPFCBlending + description: Memory-to-memory with blending (FG and BG fetch with PFC and blending) + value: 2 + - name: RegisterToMemory + description: Register-to-memory + value: 3 +enum/OPFCCR_CM: + bit_size: 3 + variants: + - name: ARGB8888 + description: ARGB8888 + value: 0 + - name: RGB888 + description: RGB888 + value: 1 + - name: RGB565 + description: RGB565 + value: 2 + - name: ARGB1555 + description: ARGB1555 + value: 3 + - name: ARGB4444 + description: ARGB4444 + value: 4 +enum/SUSP: + bit_size: 1 + variants: + - name: NotSuspended + description: Transfer not suspended + value: 0 + - name: Suspended + description: Transfer suspended + value: 1 +enum/TCIE: + bit_size: 1 + variants: + - name: Disabled + description: TC interrupt disabled + value: 0 + - name: Enabled + description: TC interrupt enabled + value: 1 +enum/TEIE: + bit_size: 1 + variants: + - name: Disabled + description: TE interrupt disabled + value: 0 + - name: Enabled + description: TE interrupt enabled + value: 1 +enum/TWIE: + bit_size: 1 + variants: + - name: Disabled + description: TW interrupt disabled + value: 0 + - name: Enabled + description: TW interrupt enabled + value: 1 diff --git a/data/registers/dma2d_v2.yaml b/data/registers/dma2d_v2.yaml index a48a27b..2c55e6e 100644 --- a/data/registers/dma2d_v2.yaml +++ b/data/registers/dma2d_v2.yaml @@ -1,919 +1,787 @@ +--- block/DMA2D: description: DMA2D items: - - byte_offset: 0 - description: DMA2D control register - fieldset: CR - name: CR - - access: Read - byte_offset: 4 - description: DMA2D Interrupt Status Register - fieldset: ISR - name: ISR - - byte_offset: 8 - description: DMA2D interrupt flag clear register - fieldset: IFCR - name: IFCR - - byte_offset: 12 - description: DMA2D foreground memory address register - fieldset: FGMAR - name: FGMAR - - byte_offset: 16 - description: DMA2D foreground offset register - fieldset: FGOR - name: FGOR - - byte_offset: 20 - description: DMA2D background memory address register - fieldset: BGMAR - name: BGMAR - - byte_offset: 24 - description: DMA2D background offset register - fieldset: BGOR - name: BGOR - - byte_offset: 28 - description: DMA2D foreground PFC control register - fieldset: FGPFCCR - name: FGPFCCR - - byte_offset: 32 - description: DMA2D foreground color register - fieldset: FGCOLR - name: FGCOLR - - byte_offset: 36 - description: DMA2D background PFC control register - fieldset: BGPFCCR - name: BGPFCCR - - byte_offset: 40 - description: DMA2D background color register - fieldset: BGCOLR - name: BGCOLR - - byte_offset: 44 - description: DMA2D foreground CLUT memory address register - fieldset: FGCMAR - name: FGCMAR - - byte_offset: 48 - description: DMA2D background CLUT memory address register - fieldset: BGCMAR - name: BGCMAR - - byte_offset: 52 - description: DMA2D output PFC control register - fieldset: OPFCCR - name: OPFCCR - - byte_offset: 56 - description: DMA2D output color register - fieldset: OCOLR - name: OCOLR - - byte_offset: 60 - description: DMA2D output memory address register - fieldset: OMAR - name: OMAR - - byte_offset: 64 - description: DMA2D output offset register - fieldset: OOR - name: OOR - - byte_offset: 68 - description: DMA2D number of line register - fieldset: NLR - name: NLR - - byte_offset: 72 - description: DMA2D line watermark register - fieldset: LWR - name: LWR - - byte_offset: 76 - description: DMA2D AXI master timer configuration register - fieldset: AMTCR - name: AMTCR -enum/ABORT: - bit_size: 1 - variants: - - description: Transfer abort requested - name: AbortRequest - value: 1 -enum/BGPFCCR_AI: - bit_size: 1 - variants: - - description: Regular alpha - name: RegularAlpha - value: 0 - - description: Inverted alpha - name: InvertedAlpha - value: 1 -enum/BGPFCCR_AM: - bit_size: 2 - variants: - - description: No modification of alpha channel - name: NoModify - value: 0 - - description: Replace with value in ALPHA[7:0] - name: Replace - value: 1 - - description: Multiply with value in ALPHA[7:0] - name: Multiply - value: 2 -enum/BGPFCCR_CCM: - bit_size: 1 - variants: - - description: CLUT color format ARGB8888 - name: ARGB8888 - value: 0 - - description: CLUT color format RGB888 - name: RGB888 - value: 1 -enum/BGPFCCR_CM: - bit_size: 4 - variants: - - description: Color mode ARGB8888 - name: ARGB8888 - value: 0 - - description: Color mode RGB888 - name: RGB888 - value: 1 - - description: Color mode RGB565 - name: RGB565 - value: 2 - - description: Color mode ARGB1555 - name: ARGB1555 - value: 3 - - description: Color mode ARGB4444 - name: ARGB4444 - value: 4 - - description: Color mode L8 - name: L8 - value: 5 - - description: Color mode AL44 - name: AL44 - value: 6 - - description: Color mode AL88 - name: AL88 - value: 7 - - description: Color mode L4 - name: L4 - value: 8 - - description: Color mode A8 - name: A8 - value: 9 - - description: Color mode A4 - name: A4 - value: 10 -enum/BGPFCCR_RBS: - bit_size: 1 - variants: - - description: No Red Blue Swap (RGB or ARGB) - name: Regular - value: 0 - - description: Red Blue Swap (BGR or ABGR) - name: Swap - value: 1 -enum/BGPFCCR_START: - bit_size: 1 - variants: - - description: Start the automatic loading of the CLUT - name: Start - value: 1 -enum/CAECIF: - bit_size: 1 - variants: - - description: Clear the CAEIF flag in the ISR register - name: Clear - value: 1 -enum/CAEIE: - bit_size: 1 - variants: - - description: CAE interrupt disabled - name: Disabled - value: 0 - - description: CAE interrupt enabled - name: Enabled - value: 1 -enum/CCEIF: - bit_size: 1 - variants: - - description: Clear the CEIF flag in the ISR register - name: Clear - value: 1 -enum/CCTCIF: - bit_size: 1 - variants: - - description: Clear the CTCIF flag in the ISR register - name: Clear - value: 1 -enum/CEIE: - bit_size: 1 - variants: - - description: CE interrupt disabled - name: Disabled - value: 0 - - description: CE interrupt enabled - name: Enabled - value: 1 -enum/CR_START: - bit_size: 1 - variants: - - description: Launch the DMA2D - name: Start - value: 1 -enum/CTCIE: - bit_size: 1 - variants: - - description: CTC interrupt disabled - name: Disabled - value: 0 - - description: CTC interrupt enabled - name: Enabled - value: 1 -enum/CTCIF: - bit_size: 1 - variants: - - description: Clear the TCIF flag in the ISR register - name: Clear - value: 1 -enum/CTEIF: - bit_size: 1 - variants: - - description: Clear the TEIF flag in the ISR register - name: Clear - value: 1 -enum/CTWIF: - bit_size: 1 - variants: - - description: Clear the TWIF flag in the ISR register - name: Clear - value: 1 -enum/EN: - bit_size: 1 - variants: - - description: Disabled AHB/AXI dead-time functionality - name: Disabled - value: 0 - - description: Enabled AHB/AXI dead-time functionality - name: Enabled - value: 1 -enum/FGPFCCR_AI: - bit_size: 1 - variants: - - description: Regular alpha - name: RegularAlpha - value: 0 - - description: Inverted alpha - name: InvertedAlpha - value: 1 -enum/FGPFCCR_AM: - bit_size: 2 - variants: - - description: No modification of alpha channel - name: NoModify - value: 0 - - description: Replace with value in ALPHA[7:0] - name: Replace - value: 1 - - description: Multiply with value in ALPHA[7:0] - name: Multiply - value: 2 -enum/FGPFCCR_CCM: - bit_size: 1 - variants: - - description: CLUT color format ARGB8888 - name: ARGB8888 - value: 0 - - description: CLUT color format RGB888 - name: RGB888 - value: 1 -enum/FGPFCCR_CM: - bit_size: 4 - variants: - - description: Color mode ARGB8888 - name: ARGB8888 - value: 0 - - description: Color mode RGB888 - name: RGB888 - value: 1 - - description: Color mode RGB565 - name: RGB565 - value: 2 - - description: Color mode ARGB1555 - name: ARGB1555 - value: 3 - - description: Color mode ARGB4444 - name: ARGB4444 - value: 4 - - description: Color mode L8 - name: L8 - value: 5 - - description: Color mode AL44 - name: AL44 - value: 6 - - description: Color mode AL88 - name: AL88 - value: 7 - - description: Color mode L4 - name: L4 - value: 8 - - description: Color mode A8 - name: A8 - value: 9 - - description: Color mode A4 - name: A4 - value: 10 - - description: Color mode YCbCr - name: YCbCr - value: 11 -enum/FGPFCCR_RBS: - bit_size: 1 - variants: - - description: No Red Blue Swap (RGB or ARGB) - name: Regular - value: 0 - - description: Red Blue Swap (BGR or ABGR) - name: Swap - value: 1 -enum/FGPFCCR_START: - bit_size: 1 - variants: - - description: Start the automatic loading of the CLUT - name: Start - value: 1 -enum/MODE: - bit_size: 2 - variants: - - description: Memory-to-memory (FG fetch only) - name: MemoryToMemory - value: 0 - - description: Memory-to-memory with PFC (FG fetch only with FG PFC active) - name: MemoryToMemoryPFC - value: 1 - - description: Memory-to-memory with blending (FG and BG fetch with PFC and blending) - name: MemoryToMemoryPFCBlending - value: 2 - - description: Register-to-memory - name: RegisterToMemory - value: 3 -enum/OPFCCR_AI: - bit_size: 1 - variants: - - description: Regular alpha - name: RegularAlpha - value: 0 - - description: Inverted alpha - name: InvertedAlpha - value: 1 -enum/OPFCCR_CM: - bit_size: 3 - variants: - - description: ARGB8888 - name: ARGB8888 - value: 0 - - description: RGB888 - name: RGB888 - value: 1 - - description: RGB565 - name: RGB565 - value: 2 - - description: ARGB1555 - name: ARGB1555 - value: 3 - - description: ARGB4444 - name: ARGB4444 - value: 4 -enum/OPFCCR_RBS: - bit_size: 1 - variants: - - description: No Red Blue Swap (RGB or ARGB) - name: Regular - value: 0 - - description: Red Blue Swap (BGR or ABGR) - name: Swap - value: 1 -enum/SB: - bit_size: 1 - variants: - - description: Regular byte order - name: Regular - value: 0 - - description: Bytes are swapped two by two - name: SwapBytes - value: 1 -enum/SUSP: - bit_size: 1 - variants: - - description: Transfer not suspended - name: NotSuspended - value: 0 - - description: Transfer suspended - name: Suspended - value: 1 -enum/TCIE: - bit_size: 1 - variants: - - description: TC interrupt disabled - name: Disabled - value: 0 - - description: TC interrupt enabled - name: Enabled - value: 1 -enum/TEIE: - bit_size: 1 - variants: - - description: TE interrupt disabled - name: Disabled - value: 0 - - description: TE interrupt enabled - name: Enabled - value: 1 -enum/TWIE: - bit_size: 1 - variants: - - description: TW interrupt disabled - name: Disabled - value: 0 - - description: TW interrupt enabled - name: Enabled - value: 1 + - name: CR + description: DMA2D control register + byte_offset: 0 + fieldset: CR + - name: ISR + description: DMA2D Interrupt Status Register + byte_offset: 4 + access: Read + fieldset: ISR + - name: IFCR + description: DMA2D interrupt flag clear register + byte_offset: 8 + fieldset: IFCR + - name: FGMAR + description: DMA2D foreground memory address register + byte_offset: 12 + fieldset: FGMAR + - name: FGOR + description: DMA2D foreground offset register + byte_offset: 16 + fieldset: FGOR + - name: BGMAR + description: DMA2D background memory address register + byte_offset: 20 + fieldset: BGMAR + - name: BGOR + description: DMA2D background offset register + byte_offset: 24 + fieldset: BGOR + - name: FGPFCCR + description: DMA2D foreground PFC control register + byte_offset: 28 + fieldset: FGPFCCR + - name: FGCOLR + description: DMA2D foreground color register + byte_offset: 32 + fieldset: FGCOLR + - name: BGPFCCR + description: DMA2D background PFC control register + byte_offset: 36 + fieldset: BGPFCCR + - name: BGCOLR + description: DMA2D background color register + byte_offset: 40 + fieldset: BGCOLR + - name: FGCMAR + description: DMA2D foreground CLUT memory address register + byte_offset: 44 + fieldset: FGCMAR + - name: BGCMAR + description: DMA2D background CLUT memory address register + byte_offset: 48 + fieldset: BGCMAR + - name: OPFCCR + description: DMA2D output PFC control register + byte_offset: 52 + fieldset: OPFCCR + - name: OCOLR + description: DMA2D output color register + byte_offset: 56 + fieldset: OCOLR + - name: OMAR + description: DMA2D output memory address register + byte_offset: 60 + fieldset: OMAR + - name: OOR + description: DMA2D output offset register + byte_offset: 64 + fieldset: OOR + - name: NLR + description: DMA2D number of line register + byte_offset: 68 + fieldset: NLR + - name: LWR + description: DMA2D line watermark register + byte_offset: 72 + fieldset: LWR + - name: AMTCR + description: DMA2D AXI master timer configuration register + byte_offset: 76 + fieldset: AMTCR fieldset/AMTCR: description: DMA2D AXI master timer configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: Enable Enables the dead time functionality. - enum: EN - name: EN - - bit_offset: 8 - bit_size: 8 - description: Dead Time Dead time value in the AXI clock cycle inserted between - two consecutive accesses on the AXI master port. These bits represent the minimum - guaranteed number of cycles between two consecutive AXI accesses. - name: DT + - name: EN + description: Enable Enables the dead time functionality. + bit_offset: 0 + bit_size: 1 + enum: EN + - name: DT + description: Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses. + bit_offset: 8 + bit_size: 8 fieldset/BGCMAR: description: DMA2D background CLUT memory address register fields: - - bit_offset: 0 - bit_size: 32 - description: Memory address Address of the data used for the CLUT address dedicated - to the background image. This register can only be written when no transfer - is on going. Once the CLUT transfer has started, this register is read-only. - If the background CLUT format is 32-bit, the address must be 32-bit aligned. - name: MA + - name: MA + description: "Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned." + bit_offset: 0 + bit_size: 32 fieldset/BGCOLR: description: DMA2D background color register fields: - - bit_offset: 0 - bit_size: 8 - description: Blue Value These bits define the blue value for the A4 or A8 mode - of the background. These bits can only be written when data transfers are disabled. - Once the transfer has started, they are read-only. - name: BLUE - - bit_offset: 8 - bit_size: 8 - description: Green Value These bits define the green value for the A4 or A8 mode - of the background. These bits can only be written when data transfers are disabled. - Once the transfer has started, they are read-only. - name: GREEN - - bit_offset: 16 - bit_size: 8 - description: Red Value These bits define the red value for the A4 or A8 mode of - the background. These bits can only be written when data transfers are disabled. - Once the transfer has started, they are read-only. - name: RED + - name: BLUE + description: "Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." + bit_offset: 0 + bit_size: 8 + - name: GREEN + description: "Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." + bit_offset: 8 + bit_size: 8 + - name: RED + description: "Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." + bit_offset: 16 + bit_size: 8 fieldset/BGMAR: description: DMA2D background memory address register fields: - - bit_offset: 0 - bit_size: 32 - description: Memory address Address of the data used for the background image. - This register can only be written when data transfers are disabled. Once a data - transfer has started, this register is read-only. The address alignment must - match the image format selected e.g. a 32-bit per pixel format must be 32-bit - aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel - format must be 8-bit aligned. - name: MA + - name: MA + description: "Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned." + bit_offset: 0 + bit_size: 32 fieldset/BGOR: description: DMA2D background offset register fields: - - bit_offset: 0 - bit_size: 16 - description: Line offset Line offset used for the background image (expressed - in pixel). This value is used for the address generation. It is added at the - end of each line to determine the starting address of the next line. These bits - can only be written when data transfers are disabled. Once data transfer has - started, they become read-only. If the image format is 4-bit per pixel, the - line offset must be even. - name: LO + - name: LO + description: "Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even." + bit_offset: 0 + bit_size: 16 fieldset/BGPFCCR: description: DMA2D background PFC control register fields: - - bit_offset: 0 - bit_size: 4 - description: 'Color mode These bits define the color format of the foreground - image. These bits can only be written when data transfers are disabled. Once - the transfer has started, they are read-only. others: meaningless' - enum: BGPFCCR_CM - name: CM - - bit_offset: 4 - bit_size: 1 - description: CLUT Color mode These bits define the color format of the CLUT. This - register can only be written when the transfer is disabled. Once the CLUT transfer - has started, this bit is read-only. - enum: BGPFCCR_CCM - name: CCM - - bit_offset: 5 - bit_size: 1 - description: 'Start This bit is set to start the automatic loading of the CLUT. - This bit is automatically reset: ** at the end of the transfer ** when the transfer - is aborted by the user application by setting the ABORT bit in the DMA2D_CR - ** when a transfer error occurs ** when the transfer has not started due to - a configuration error or another transfer operation already on going (data transfer - or automatic BackGround CLUT transfer).' - enum: BGPFCCR_START - name: START - - bit_offset: 8 - bit_size: 8 - description: CLUT size These bits define the size of the CLUT used for the BG. - Once the CLUT transfer has started, this field is read-only. The number of CLUT - entries is equal to CS[7:0] + 1. - name: CS - - bit_offset: 16 - bit_size: 2 - description: 'Alpha mode These bits define which alpha channel value to be used - for the background image. These bits can only be written when data transfers - are disabled. Once the transfer has started, they are read-only. others: meaningless' - enum: BGPFCCR_AM - name: AM - - bit_offset: 20 - bit_size: 1 - description: Alpha Inverted This bit inverts the alpha value. Once the transfer - has started, this bit is read-only. - enum: BGPFCCR_AI - name: AI - - bit_offset: 21 - bit_size: 1 - description: Red Blue Swap This bit allows to swap the R & B to support BGR - or ABGR color formats. Once the transfer has started, this bit is read-only. - enum: BGPFCCR_RBS - name: RBS - - bit_offset: 24 - bit_size: 8 - description: 'Alpha value These bits define a fixed alpha channel value which - can replace the original alpha value or be multiplied with the original alpha - value according to the alpha mode selected with bits AM[1: 0]. These bits can - only be written when data transfers are disabled. Once the transfer has started, - they are read-only.' - name: ALPHA + - name: CM + description: "Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless" + bit_offset: 0 + bit_size: 4 + enum: BGPFCCR_CM + - name: CCM + description: "CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only." + bit_offset: 4 + bit_size: 1 + enum: BGPFCCR_CCM + - name: START + description: "Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer)." + bit_offset: 5 + bit_size: 1 + enum: BGPFCCR_START + - name: CS + description: "CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1." + bit_offset: 8 + bit_size: 8 + - name: AM + description: "Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless" + bit_offset: 16 + bit_size: 2 + enum: BGPFCCR_AM + - name: AI + description: "Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only." + bit_offset: 20 + bit_size: 1 + enum: BGPFCCR_AI + - name: RBS + description: "Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only." + bit_offset: 21 + bit_size: 1 + enum: BGPFCCR_RBS + - name: ALPHA + description: "Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." + bit_offset: 24 + bit_size: 8 fieldset/CR: description: DMA2D control register fields: - - bit_offset: 0 - bit_size: 1 - description: Start This bit can be used to launch the DMA2D according to the parameters - loaded in the various configuration registers - enum: CR_START - name: START - - bit_offset: 1 - bit_size: 1 - description: Suspend This bit can be used to suspend the current transfer. This - bit is set and reset by software. It is automatically reset by hardware when - the START bit is reset. - enum: SUSP - name: SUSP - - bit_offset: 2 - bit_size: 1 - description: Abort This bit can be used to abort the current transfer. This bit - is set by software and is automatically reset by hardware when the START bit - is reset. - enum: ABORT - name: ABORT - - bit_offset: 8 - bit_size: 1 - description: Transfer error interrupt enable This bit is set and cleared by software. - enum: TEIE - name: TEIE - - bit_offset: 9 - bit_size: 1 - description: Transfer complete interrupt enable This bit is set and cleared by - software. - enum: TCIE - name: TCIE - - bit_offset: 10 - bit_size: 1 - description: Transfer watermark interrupt enable This bit is set and cleared by - software. - enum: TWIE - name: TWIE - - bit_offset: 11 - bit_size: 1 - description: CLUT access error interrupt enable This bit is set and cleared by - software. - enum: CAEIE - name: CAEIE - - bit_offset: 12 - bit_size: 1 - description: CLUT transfer complete interrupt enable This bit is set and cleared - by software. - enum: CTCIE - name: CTCIE - - bit_offset: 13 - bit_size: 1 - description: Configuration Error Interrupt Enable This bit is set and cleared - by software. - enum: CEIE - name: CEIE - - bit_offset: 16 - bit_size: 2 - description: DMA2D mode This bit is set and cleared by software. It cannot be - modified while a transfer is ongoing. - enum: MODE - name: MODE + - name: START + description: Start This bit can be used to launch the DMA2D according to the parameters loaded in the various configuration registers + bit_offset: 0 + bit_size: 1 + enum: CR_START + - name: SUSP + description: Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset. + bit_offset: 1 + bit_size: 1 + enum: SUSP + - name: ABORT + description: Abort This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset. + bit_offset: 2 + bit_size: 1 + enum: ABORT + - name: TEIE + description: Transfer error interrupt enable This bit is set and cleared by software. + bit_offset: 8 + bit_size: 1 + enum: TEIE + - name: TCIE + description: Transfer complete interrupt enable This bit is set and cleared by software. + bit_offset: 9 + bit_size: 1 + enum: TCIE + - name: TWIE + description: Transfer watermark interrupt enable This bit is set and cleared by software. + bit_offset: 10 + bit_size: 1 + enum: TWIE + - name: CAEIE + description: CLUT access error interrupt enable This bit is set and cleared by software. + bit_offset: 11 + bit_size: 1 + enum: CAEIE + - name: CTCIE + description: CLUT transfer complete interrupt enable This bit is set and cleared by software. + bit_offset: 12 + bit_size: 1 + enum: CTCIE + - name: CEIE + description: Configuration Error Interrupt Enable This bit is set and cleared by software. + bit_offset: 13 + bit_size: 1 + enum: CEIE + - name: MODE + description: DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing. + bit_offset: 16 + bit_size: 2 + enum: MODE fieldset/FGCMAR: description: DMA2D foreground CLUT memory address register fields: - - bit_offset: 0 - bit_size: 32 - description: Memory Address Address of the data used for the CLUT address dedicated - to the foreground image. This register can only be written when no transfer - is ongoing. Once the CLUT transfer has started, this register is read-only. - If the foreground CLUT format is 32-bit, the address must be 32-bit aligned. - name: MA + - name: MA + description: "Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned." + bit_offset: 0 + bit_size: 32 fieldset/FGCOLR: description: DMA2D foreground color register fields: - - bit_offset: 0 - bit_size: 8 - description: Blue Value These bits defines the blue value for the A4 or A8 mode - of the foreground image. They can only be written when data transfers are disabled. - Once the transfer has started, They are read-only. - name: BLUE - - bit_offset: 8 - bit_size: 8 - description: Green Value These bits defines the green value for the A4 or A8 mode - of the foreground image. They can only be written when data transfers are disabled. - Once the transfer has started, They are read-only. - name: GREEN - - bit_offset: 16 - bit_size: 8 - description: Red Value These bits defines the red value for the A4 or A8 mode - of the foreground image. They can only be written when data transfers are disabled. - Once the transfer has started, they are read-only. - name: RED + - name: BLUE + description: "Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only." + bit_offset: 0 + bit_size: 8 + - name: GREEN + description: "Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only." + bit_offset: 8 + bit_size: 8 + - name: RED + description: "Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only." + bit_offset: 16 + bit_size: 8 fieldset/FGMAR: description: DMA2D foreground memory address register fields: - - bit_offset: 0 - bit_size: 32 - description: Memory address Address of the data used for the foreground image. - This register can only be written when data transfers are disabled. Once the - data transfer has started, this register is read-only. The address alignment - must match the image format selected e.g. a 32-bit per pixel format must be - 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit - per pixel format must be 8-bit aligned. - name: MA + - name: MA + description: "Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned." + bit_offset: 0 + bit_size: 32 fieldset/FGOR: description: DMA2D foreground offset register fields: - - bit_offset: 0 - bit_size: 16 - description: Line offset Line offset used for the foreground expressed in pixel. - This value is used to generate the address. It is added at the end of each line - to determine the starting address of the next line. These bits can only be written - when data transfers are disabled. Once a data transfer has started, they become - read-only. If the image format is 4-bit per pixel, the line offset must be even. - name: LO + - name: LO + description: "Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even." + bit_offset: 0 + bit_size: 16 fieldset/FGPFCCR: description: DMA2D foreground PFC control register fields: - - bit_offset: 0 - bit_size: 4 - description: 'Color mode These bits defines the color format of the foreground - image. They can only be written when data transfers are disabled. Once the transfer - has started, they are read-only. others: meaningless' - enum: FGPFCCR_CM - name: CM - - bit_offset: 4 - bit_size: 1 - description: CLUT color mode This bit defines the color format of the CLUT. It - can only be written when the transfer is disabled. Once the CLUT transfer has - started, this bit is read-only. - enum: FGPFCCR_CCM - name: CCM - - bit_offset: 5 - bit_size: 1 - description: 'Start This bit can be set to start the automatic loading of the - CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer - is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when - a transfer error occurs ** when the transfer has not started due to a configuration - error or another transfer operation already ongoing (data transfer or automatic - background CLUT transfer).' - enum: FGPFCCR_START - name: START - - bit_offset: 8 - bit_size: 8 - description: CLUT size These bits define the size of the CLUT used for the foreground - image. Once the CLUT transfer has started, this field is read-only. The number - of CLUT entries is equal to CS[7:0] + 1. - name: CS - - bit_offset: 16 - bit_size: 2 - description: Alpha mode These bits select the alpha channel value to be used for - the foreground image. They can only be written data the transfer are disabled. - Once the transfer has started, they become read-only. other configurations are - meaningless - enum: FGPFCCR_AM - name: AM - - bit_offset: 18 - bit_size: 2 - description: 'Chroma Sub-Sampling These bits define the chroma sub-sampling mode - for YCbCr color mode. Once the transfer has started, these bits are read-only. - others: meaningless' - name: CSS - - bit_offset: 20 - bit_size: 1 - description: Alpha Inverted This bit inverts the alpha value. Once the transfer - has started, this bit is read-only. - enum: FGPFCCR_AI - name: AI - - bit_offset: 21 - bit_size: 1 - description: Red Blue Swap This bit allows to swap the R & B to support BGR - or ABGR color formats. Once the transfer has started, this bit is read-only. - enum: FGPFCCR_RBS - name: RBS - - bit_offset: 24 - bit_size: 8 - description: Alpha value These bits define a fixed alpha channel value which can - replace the original alpha value or be multiplied by the original alpha value - according to the alpha mode selected through the AM[1:0] bits. These bits can - only be written when data transfers are disabled. Once a transfer has started, - they become read-only. - name: ALPHA + - name: CM + description: "Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless" + bit_offset: 0 + bit_size: 4 + enum: FGPFCCR_CM + - name: CCM + description: "CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only." + bit_offset: 4 + bit_size: 1 + enum: FGPFCCR_CCM + - name: START + description: "Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer)." + bit_offset: 5 + bit_size: 1 + enum: FGPFCCR_START + - name: CS + description: "CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1." + bit_offset: 8 + bit_size: 8 + - name: AM + description: "Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless" + bit_offset: 16 + bit_size: 2 + enum: FGPFCCR_AM + - name: CSS + description: "Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless" + bit_offset: 18 + bit_size: 2 + - name: AI + description: "Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only." + bit_offset: 20 + bit_size: 1 + enum: FGPFCCR_AI + - name: RBS + description: "Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only." + bit_offset: 21 + bit_size: 1 + enum: FGPFCCR_RBS + - name: ALPHA + description: "Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only." + bit_offset: 24 + bit_size: 8 fieldset/IFCR: description: DMA2D interrupt flag clear register fields: - - bit_offset: 0 - bit_size: 1 - description: Clear Transfer error interrupt flag Programming this bit to 1 clears - the TEIF flag in the DMA2D_ISR register - enum: CTEIF - name: CTEIF - - bit_offset: 1 - bit_size: 1 - description: Clear transfer complete interrupt flag Programming this bit to 1 - clears the TCIF flag in the DMA2D_ISR register - enum: CTCIF - name: CTCIF - - bit_offset: 2 - bit_size: 1 - description: Clear transfer watermark interrupt flag Programming this bit to 1 - clears the TWIF flag in the DMA2D_ISR register - enum: CTWIF - name: CTWIF - - bit_offset: 3 - bit_size: 1 - description: Clear CLUT access error interrupt flag Programming this bit to 1 - clears the CAEIF flag in the DMA2D_ISR register - enum: CAECIF - name: CAECIF - - bit_offset: 4 - bit_size: 1 - description: Clear CLUT transfer complete interrupt flag Programming this bit - to 1 clears the CTCIF flag in the DMA2D_ISR register - enum: CCTCIF - name: CCTCIF - - bit_offset: 5 - bit_size: 1 - description: Clear configuration error interrupt flag Programming this bit to - 1 clears the CEIF flag in the DMA2D_ISR register - enum: CCEIF - name: CCEIF + - name: CTEIF + description: Clear Transfer error interrupt flag Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register + bit_offset: 0 + bit_size: 1 + enum: CTEIF + - name: CTCIF + description: Clear transfer complete interrupt flag Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register + bit_offset: 1 + bit_size: 1 + enum: CTCIF + - name: CTWIF + description: Clear transfer watermark interrupt flag Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register + bit_offset: 2 + bit_size: 1 + enum: CTWIF + - name: CAECIF + description: Clear CLUT access error interrupt flag Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register + bit_offset: 3 + bit_size: 1 + enum: CAECIF + - name: CCTCIF + description: Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register + bit_offset: 4 + bit_size: 1 + enum: CCTCIF + - name: CCEIF + description: Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register + bit_offset: 5 + bit_size: 1 + enum: CCEIF fieldset/ISR: description: DMA2D Interrupt Status Register fields: - - bit_offset: 0 - bit_size: 1 - description: Transfer error interrupt flag This bit is set when an error occurs - during a DMA transfer (data transfer or automatic CLUT loading). - name: TEIF - - bit_offset: 1 - bit_size: 1 - description: Transfer complete interrupt flag This bit is set when a DMA2D transfer - operation is complete (data transfer only). - name: TCIF - - bit_offset: 2 - bit_size: 1 - description: Transfer watermark interrupt flag This bit is set when the last pixel - of the watermarked line has been transferred. - name: TWIF - - bit_offset: 3 - bit_size: 1 - description: CLUT access error interrupt flag This bit is set when the CPU accesses - the CLUT while the CLUT is being automatically copied from a system memory to - the internal DMA2D. - name: CAEIF - - bit_offset: 4 - bit_size: 1 - description: CLUT transfer complete interrupt flag This bit is set when the CLUT - copy from a system memory area to the internal DMA2D memory is complete. - name: CTCIF - - bit_offset: 5 - bit_size: 1 - description: Configuration error interrupt flag This bit is set when the START - bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration - has been programmed. - name: CEIF + - name: TEIF + description: Transfer error interrupt flag This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading). + bit_offset: 0 + bit_size: 1 + - name: TCIF + description: Transfer complete interrupt flag This bit is set when a DMA2D transfer operation is complete (data transfer only). + bit_offset: 1 + bit_size: 1 + - name: TWIF + description: Transfer watermark interrupt flag This bit is set when the last pixel of the watermarked line has been transferred. + bit_offset: 2 + bit_size: 1 + - name: CAEIF + description: CLUT access error interrupt flag This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D. + bit_offset: 3 + bit_size: 1 + - name: CTCIF + description: CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete. + bit_offset: 4 + bit_size: 1 + - name: CEIF + description: "Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed." + bit_offset: 5 + bit_size: 1 fieldset/LWR: description: DMA2D line watermark register fields: - - bit_offset: 0 - bit_size: 16 - description: Line watermark These bits allow to configure the line watermark for - interrupt generation. An interrupt is raised when the last pixel of the watermarked - line has been transferred. These bits can only be written when data transfers - are disabled. Once the transfer has started, they are read-only. - name: LW + - name: LW + description: "Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." + bit_offset: 0 + bit_size: 16 fieldset/NLR: description: DMA2D number of line register fields: - - bit_offset: 0 - bit_size: 16 - description: Number of lines Number of lines of the area to be transferred. These - bits can only be written when data transfers are disabled. Once the transfer - has started, they are read-only. - name: NL - - bit_offset: 16 - bit_size: 14 - description: Pixel per lines Number of pixels per lines of the area to be transferred. - These bits can only be written when data transfers are disabled. Once the transfer - has started, they are read-only. If any of the input image format is 4-bit per - pixel, pixel per lines must be even. - name: PL + - name: NL + description: "Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." + bit_offset: 0 + bit_size: 16 + - name: PL + description: "Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even." + bit_offset: 16 + bit_size: 14 fieldset/OCOLR: description: DMA2D output color register fields: - - bit_offset: 0 - bit_size: 8 - description: Blue Value These bits define the blue value of the output image. - These bits can only be written when data transfers are disabled. Once the transfer - has started, they are read-only. - name: BLUE - - bit_offset: 8 - bit_size: 8 - description: Green Value These bits define the green value of the output image. - These bits can only be written when data transfers are disabled. Once the transfer - has started, they are read-only. - name: GREEN - - bit_offset: 16 - bit_size: 8 - description: Red Value These bits define the red value of the output image. These - bits can only be written when data transfers are disabled. Once the transfer - has started, they are read-only. - name: RED - - bit_offset: 24 - bit_size: 8 - description: Alpha Channel Value These bits define the alpha channel of the output - color. These bits can only be written when data transfers are disabled. Once - the transfer has started, they are read-only. - name: ALPHA + - name: BLUE + description: "Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." + bit_offset: 0 + bit_size: 8 + - name: GREEN + description: "Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." + bit_offset: 8 + bit_size: 8 + - name: RED + description: "Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." + bit_offset: 16 + bit_size: 8 + - name: ALPHA + description: "Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." + bit_offset: 24 + bit_size: 8 fieldset/OMAR: description: DMA2D output memory address register fields: - - bit_offset: 0 - bit_size: 32 - description: Memory Address Address of the data used for the output FIFO. These - bits can only be written when data transfers are disabled. Once the transfer - has started, they are read-only. The address alignment must match the image - format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a - 16-bit per pixel format must be 16-bit aligned. - name: MA + - name: MA + description: "Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned." + bit_offset: 0 + bit_size: 32 fieldset/OOR: description: DMA2D output offset register fields: - - bit_offset: 0 - bit_size: 16 - description: Line Offset Line offset used for the output (expressed in pixels). - This value is used for the address generation. It is added at the end of each - line to determine the starting address of the next line. These bits can only - be written when data transfers are disabled. Once the transfer has started, - they are read-only. - name: LO + - name: LO + description: "Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." + bit_offset: 0 + bit_size: 16 fieldset/OPFCCR: description: DMA2D output PFC control register fields: - - bit_offset: 0 - bit_size: 3 - description: 'Color mode These bits define the color format of the output image. - These bits can only be written when data transfers are disabled. Once the transfer - has started, they are read-only. others: meaningless' - enum: OPFCCR_CM - name: CM - - bit_offset: 8 - bit_size: 1 - description: Swap Bytes - enum: SB - name: SB - - bit_offset: 20 - bit_size: 1 - description: Alpha Inverted This bit inverts the alpha value. Once the transfer - has started, this bit is read-only. - enum: OPFCCR_AI - name: AI - - bit_offset: 21 - bit_size: 1 - description: Red Blue Swap This bit allows to swap the R & B to support BGR - or ABGR color formats. Once the transfer has started, this bit is read-only. - enum: OPFCCR_RBS - name: RBS + - name: CM + description: "Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless" + bit_offset: 0 + bit_size: 3 + enum: OPFCCR_CM + - name: SB + description: Swap Bytes + bit_offset: 8 + bit_size: 1 + enum: SB + - name: AI + description: "Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only." + bit_offset: 20 + bit_size: 1 + enum: OPFCCR_AI + - name: RBS + description: "Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only." + bit_offset: 21 + bit_size: 1 + enum: OPFCCR_RBS +enum/ABORT: + bit_size: 1 + variants: + - name: AbortRequest + description: Transfer abort requested + value: 1 +enum/BGPFCCR_AI: + bit_size: 1 + variants: + - name: RegularAlpha + description: Regular alpha + value: 0 + - name: InvertedAlpha + description: Inverted alpha + value: 1 +enum/BGPFCCR_AM: + bit_size: 2 + variants: + - name: NoModify + description: No modification of alpha channel + value: 0 + - name: Replace + description: "Replace with value in ALPHA[7:0]" + value: 1 + - name: Multiply + description: "Multiply with value in ALPHA[7:0]" + value: 2 +enum/BGPFCCR_CCM: + bit_size: 1 + variants: + - name: ARGB8888 + description: CLUT color format ARGB8888 + value: 0 + - name: RGB888 + description: CLUT color format RGB888 + value: 1 +enum/BGPFCCR_CM: + bit_size: 4 + variants: + - name: ARGB8888 + description: Color mode ARGB8888 + value: 0 + - name: RGB888 + description: Color mode RGB888 + value: 1 + - name: RGB565 + description: Color mode RGB565 + value: 2 + - name: ARGB1555 + description: Color mode ARGB1555 + value: 3 + - name: ARGB4444 + description: Color mode ARGB4444 + value: 4 + - name: L8 + description: Color mode L8 + value: 5 + - name: AL44 + description: Color mode AL44 + value: 6 + - name: AL88 + description: Color mode AL88 + value: 7 + - name: L4 + description: Color mode L4 + value: 8 + - name: A8 + description: Color mode A8 + value: 9 + - name: A4 + description: Color mode A4 + value: 10 +enum/BGPFCCR_RBS: + bit_size: 1 + variants: + - name: Regular + description: No Red Blue Swap (RGB or ARGB) + value: 0 + - name: Swap + description: Red Blue Swap (BGR or ABGR) + value: 1 +enum/BGPFCCR_START: + bit_size: 1 + variants: + - name: Start + description: Start the automatic loading of the CLUT + value: 1 +enum/CAECIF: + bit_size: 1 + variants: + - name: Clear + description: Clear the CAEIF flag in the ISR register + value: 1 +enum/CAEIE: + bit_size: 1 + variants: + - name: Disabled + description: CAE interrupt disabled + value: 0 + - name: Enabled + description: CAE interrupt enabled + value: 1 +enum/CCEIF: + bit_size: 1 + variants: + - name: Clear + description: Clear the CEIF flag in the ISR register + value: 1 +enum/CCTCIF: + bit_size: 1 + variants: + - name: Clear + description: Clear the CTCIF flag in the ISR register + value: 1 +enum/CEIE: + bit_size: 1 + variants: + - name: Disabled + description: CE interrupt disabled + value: 0 + - name: Enabled + description: CE interrupt enabled + value: 1 +enum/CR_START: + bit_size: 1 + variants: + - name: Start + description: Launch the DMA2D + value: 1 +enum/CTCIE: + bit_size: 1 + variants: + - name: Disabled + description: CTC interrupt disabled + value: 0 + - name: Enabled + description: CTC interrupt enabled + value: 1 +enum/CTCIF: + bit_size: 1 + variants: + - name: Clear + description: Clear the TCIF flag in the ISR register + value: 1 +enum/CTEIF: + bit_size: 1 + variants: + - name: Clear + description: Clear the TEIF flag in the ISR register + value: 1 +enum/CTWIF: + bit_size: 1 + variants: + - name: Clear + description: Clear the TWIF flag in the ISR register + value: 1 +enum/EN: + bit_size: 1 + variants: + - name: Disabled + description: Disabled AHB/AXI dead-time functionality + value: 0 + - name: Enabled + description: Enabled AHB/AXI dead-time functionality + value: 1 +enum/FGPFCCR_AI: + bit_size: 1 + variants: + - name: RegularAlpha + description: Regular alpha + value: 0 + - name: InvertedAlpha + description: Inverted alpha + value: 1 +enum/FGPFCCR_AM: + bit_size: 2 + variants: + - name: NoModify + description: No modification of alpha channel + value: 0 + - name: Replace + description: "Replace with value in ALPHA[7:0]" + value: 1 + - name: Multiply + description: "Multiply with value in ALPHA[7:0]" + value: 2 +enum/FGPFCCR_CCM: + bit_size: 1 + variants: + - name: ARGB8888 + description: CLUT color format ARGB8888 + value: 0 + - name: RGB888 + description: CLUT color format RGB888 + value: 1 +enum/FGPFCCR_CM: + bit_size: 4 + variants: + - name: ARGB8888 + description: Color mode ARGB8888 + value: 0 + - name: RGB888 + description: Color mode RGB888 + value: 1 + - name: RGB565 + description: Color mode RGB565 + value: 2 + - name: ARGB1555 + description: Color mode ARGB1555 + value: 3 + - name: ARGB4444 + description: Color mode ARGB4444 + value: 4 + - name: L8 + description: Color mode L8 + value: 5 + - name: AL44 + description: Color mode AL44 + value: 6 + - name: AL88 + description: Color mode AL88 + value: 7 + - name: L4 + description: Color mode L4 + value: 8 + - name: A8 + description: Color mode A8 + value: 9 + - name: A4 + description: Color mode A4 + value: 10 + - name: YCbCr + description: Color mode YCbCr + value: 11 +enum/FGPFCCR_RBS: + bit_size: 1 + variants: + - name: Regular + description: No Red Blue Swap (RGB or ARGB) + value: 0 + - name: Swap + description: Red Blue Swap (BGR or ABGR) + value: 1 +enum/FGPFCCR_START: + bit_size: 1 + variants: + - name: Start + description: Start the automatic loading of the CLUT + value: 1 +enum/MODE: + bit_size: 2 + variants: + - name: MemoryToMemory + description: Memory-to-memory (FG fetch only) + value: 0 + - name: MemoryToMemoryPFC + description: Memory-to-memory with PFC (FG fetch only with FG PFC active) + value: 1 + - name: MemoryToMemoryPFCBlending + description: Memory-to-memory with blending (FG and BG fetch with PFC and blending) + value: 2 + - name: RegisterToMemory + description: Register-to-memory + value: 3 +enum/OPFCCR_AI: + bit_size: 1 + variants: + - name: RegularAlpha + description: Regular alpha + value: 0 + - name: InvertedAlpha + description: Inverted alpha + value: 1 +enum/OPFCCR_CM: + bit_size: 3 + variants: + - name: ARGB8888 + description: ARGB8888 + value: 0 + - name: RGB888 + description: RGB888 + value: 1 + - name: RGB565 + description: RGB565 + value: 2 + - name: ARGB1555 + description: ARGB1555 + value: 3 + - name: ARGB4444 + description: ARGB4444 + value: 4 +enum/OPFCCR_RBS: + bit_size: 1 + variants: + - name: Regular + description: No Red Blue Swap (RGB or ARGB) + value: 0 + - name: Swap + description: Red Blue Swap (BGR or ABGR) + value: 1 +enum/SB: + bit_size: 1 + variants: + - name: Regular + description: Regular byte order + value: 0 + - name: SwapBytes + description: Bytes are swapped two by two + value: 1 +enum/SUSP: + bit_size: 1 + variants: + - name: NotSuspended + description: Transfer not suspended + value: 0 + - name: Suspended + description: Transfer suspended + value: 1 +enum/TCIE: + bit_size: 1 + variants: + - name: Disabled + description: TC interrupt disabled + value: 0 + - name: Enabled + description: TC interrupt enabled + value: 1 +enum/TEIE: + bit_size: 1 + variants: + - name: Disabled + description: TE interrupt disabled + value: 0 + - name: Enabled + description: TE interrupt enabled + value: 1 +enum/TWIE: + bit_size: 1 + variants: + - name: Disabled + description: TW interrupt disabled + value: 0 + - name: Enabled + description: TW interrupt enabled + value: 1 diff --git a/data/registers/dma_v1.yaml b/data/registers/dma_v1.yaml index 413f791..b714785 100644 --- a/data/registers/dma_v1.yaml +++ b/data/registers/dma_v1.yaml @@ -8,7 +8,6 @@ block/DMA: len: 2 stride: 4 byte_offset: 0 - reset_value: 0 access: Read fieldset: IXR - name: IFCR @@ -17,7 +16,6 @@ block/DMA: len: 2 stride: 4 byte_offset: 8 - reset_value: 0 access: Write fieldset: IXR - name: ST @@ -33,29 +31,23 @@ block/ST: - name: CR description: stream x configuration register byte_offset: 0 - reset_value: 0 fieldset: CR - name: NDTR description: stream x number of data register byte_offset: 4 - reset_value: 0 fieldset: NDTR - name: PAR description: stream x peripheral address register byte_offset: 8 - reset_value: 0 - name: M0AR description: stream x memory 0 address register byte_offset: 12 - reset_value: 0 - name: M1AR description: stream x memory 1 address register byte_offset: 16 - reset_value: 0 - name: FCR description: stream x FIFO control register byte_offset: 20 - reset_value: 33 fieldset: FCR fieldset/CR: description: stream x configuration register @@ -231,6 +223,21 @@ fieldset/NDTR: description: Number of data items to transfer bit_offset: 0 bit_size: 16 +enum/BURST: + bit_size: 2 + variants: + - name: Single + description: Single transfer + value: 0 + - name: INCR4 + description: Incremental burst of 4 beats + value: 1 + - name: INCR8 + description: Incremental burst of 8 beats + value: 2 + - name: INCR16 + description: Incremental burst of 16 beats + value: 3 enum/CIRC: bit_size: 1 variants: @@ -315,21 +322,6 @@ enum/FTH: - name: Full description: Full FIFO value: 3 -enum/BURST: - bit_size: 2 - variants: - - name: Single - description: Single transfer - value: 0 - - name: INCR4 - description: Incremental burst of 4 beats - value: 1 - - name: INCR8 - description: Incremental burst of 8 beats - value: 2 - - name: INCR16 - description: Incremental burst of 16 beats - value: 3 enum/INC: bit_size: 1 variants: @@ -339,18 +331,6 @@ enum/INC: - name: Incremented description: Address pointer is incremented after each data transfer value: 1 -enum/SIZE: - bit_size: 2 - variants: - - name: Bits8 - description: Byte (8-bit) - value: 0 - - name: Bits16 - description: Half-word (16-bit) - value: 1 - - name: Bits32 - description: Word (32-bit) - value: 2 enum/PFCTRL: bit_size: 1 variants: @@ -384,3 +364,15 @@ enum/PL: - name: VeryHigh description: Very high value: 3 +enum/SIZE: + bit_size: 2 + variants: + - name: Bits8 + description: Byte (8-bit) + value: 0 + - name: Bits16 + description: Half-word (16-bit) + value: 1 + - name: Bits32 + description: Word (32-bit) + value: 2 diff --git a/data/registers/dma_v2.yaml b/data/registers/dma_v2.yaml index 44d6963..e13e370 100644 --- a/data/registers/dma_v2.yaml +++ b/data/registers/dma_v2.yaml @@ -8,7 +8,6 @@ block/DMA: len: 2 stride: 4 byte_offset: 0 - reset_value: 0 access: Read fieldset: IXR - name: IFCR @@ -17,7 +16,6 @@ block/DMA: len: 2 stride: 4 byte_offset: 8 - reset_value: 0 access: Write fieldset: IXR - name: ST @@ -33,29 +31,23 @@ block/ST: - name: CR description: stream x configuration register byte_offset: 0 - reset_value: 0 fieldset: CR - name: NDTR description: stream x number of data register byte_offset: 4 - reset_value: 0 fieldset: NDTR - name: PAR description: stream x peripheral address register byte_offset: 8 - reset_value: 0 - name: M0AR description: stream x memory 0 address register byte_offset: 12 - reset_value: 0 - name: M1AR description: stream x memory 1 address register byte_offset: 16 - reset_value: 0 - name: FCR description: stream x FIFO control register byte_offset: 20 - reset_value: 33 fieldset: FCR fieldset/CR: description: stream x configuration register @@ -231,6 +223,21 @@ fieldset/NDTR: description: Number of data items to transfer bit_offset: 0 bit_size: 16 +enum/BURST: + bit_size: 2 + variants: + - name: Single + description: Single transfer + value: 0 + - name: INCR4 + description: Incremental burst of 4 beats + value: 1 + - name: INCR8 + description: Incremental burst of 8 beats + value: 2 + - name: INCR16 + description: Incremental burst of 16 beats + value: 3 enum/CIRC: bit_size: 1 variants: @@ -315,21 +322,6 @@ enum/FTH: - name: Full description: Full FIFO value: 3 -enum/BURST: - bit_size: 2 - variants: - - name: Single - description: Single transfer - value: 0 - - name: INCR4 - description: Incremental burst of 4 beats - value: 1 - - name: INCR8 - description: Incremental burst of 8 beats - value: 2 - - name: INCR16 - description: Incremental burst of 16 beats - value: 3 enum/INC: bit_size: 1 variants: @@ -339,18 +331,6 @@ enum/INC: - name: Incremented description: Address pointer is incremented after each data transfer value: 1 -enum/SIZE: - bit_size: 2 - variants: - - name: Bits8 - description: Byte (8-bit) - value: 0 - - name: Bits16 - description: Half-word (16-bit) - value: 1 - - name: Bits32 - description: Word (32-bit) - value: 2 enum/PFCTRL: bit_size: 1 variants: @@ -384,3 +364,15 @@ enum/PL: - name: VeryHigh description: Very high value: 3 +enum/SIZE: + bit_size: 2 + variants: + - name: Bits8 + description: Byte (8-bit) + value: 0 + - name: Bits16 + description: Half-word (16-bit) + value: 1 + - name: Bits32 + description: Word (32-bit) + value: 2 diff --git a/data/registers/eth_v1c.yaml b/data/registers/eth_v1c.yaml index bb07d17..fec0571 100644 --- a/data/registers/eth_v1c.yaml +++ b/data/registers/eth_v1c.yaml @@ -1,6 +1,6 @@ --- block/ETH: - description: "Ethernet Peripheral" + description: Ethernet Peripheral items: - name: ETHERNET_MAC description: "Ethernet: media access control (MAC)" @@ -14,2241 +14,2207 @@ block/ETH: description: "Ethernet: DMA mode register (DMA)" byte_offset: 4096 block: ETHERNET_DMA -block/ETHERNET_MAC: - description: 'Ethernet: media access control (MAC)' +block/ETHERNET_DMA: + description: "Ethernet: DMA controller operation" items: - - byte_offset: 0 - description: Ethernet MAC configuration register - fieldset: MACCR - name: MACCR - - byte_offset: 4 - description: Ethernet MAC frame filter register - fieldset: MACFFR - name: MACFFR - - byte_offset: 8 - description: Ethernet MAC hash table high register - fieldset: MACHTHR - name: MACHTHR - - byte_offset: 12 - description: Ethernet MAC hash table low register - fieldset: MACHTLR - name: MACHTLR - - byte_offset: 16 - description: Ethernet MAC MII address register - fieldset: MACMIIAR - name: MACMIIAR - - byte_offset: 20 - description: Ethernet MAC MII data register - fieldset: MACMIIDR - name: MACMIIDR - - byte_offset: 24 - description: Ethernet MAC flow control register - fieldset: MACFCR - name: MACFCR - - byte_offset: 28 - description: Ethernet MAC VLAN tag register - fieldset: MACVLANTR - name: MACVLANTR - - byte_offset: 40 - description: Ethernet MAC remote wakeup frame filter register - name: MACRWUFFR - - byte_offset: 44 - description: Ethernet MAC PMT control and status register - fieldset: MACPMTCSR - name: MACPMTCSR - - access: Read - byte_offset: 52 - description: Ethernet MAC debug register - fieldset: MACDBGR - name: MACDBGR - - byte_offset: 56 - description: Ethernet MAC interrupt status register - fieldset: MACSR - name: MACSR - - byte_offset: 60 - description: Ethernet MAC interrupt mask register - fieldset: MACIMR - name: MACIMR - - byte_offset: 64 - description: Ethernet MAC address 0 high register - fieldset: MACA0HR - name: MACA0HR - - byte_offset: 68 - description: Ethernet MAC address 0 low register - fieldset: MACA0LR - name: MACA0LR - - byte_offset: 72 - description: Ethernet MAC address 1 high register - fieldset: MACA1HR - name: MACA1HR - - byte_offset: 76 - description: Ethernet MAC address1 low register - fieldset: MACA1LR - name: MACA1LR - - byte_offset: 80 - description: Ethernet MAC address 2 high register - fieldset: MACA2HR - name: MACA2HR - - byte_offset: 84 - description: Ethernet MAC address 2 low register - fieldset: MACA2LR - name: MACA2LR - - byte_offset: 88 - description: Ethernet MAC address 3 high register - fieldset: MACA3HR - name: MACA3HR - - byte_offset: 92 - description: Ethernet MAC address 3 low register - fieldset: MACA3LR - name: MACA3LR - - byte_offset: 256 - description: Ethernet MMC control register - fieldset: MMCCR - name: MMCCR - - byte_offset: 260 - description: Ethernet MMC receive interrupt register - fieldset: MMCRIR - name: MMCRIR - - access: Read - byte_offset: 264 - description: Ethernet MMC transmit interrupt register - fieldset: MMCTIR - name: MMCTIR - - byte_offset: 268 - description: Ethernet MMC receive interrupt mask register - fieldset: MMCRIMR - name: MMCRIMR - - byte_offset: 272 - description: Ethernet MMC transmit interrupt mask register - fieldset: MMCTIMR - name: MMCTIMR - - access: Read - byte_offset: 332 - description: Ethernet MMC transmitted good frames after a single collision counter - fieldset: MMCTGFSCCR - name: MMCTGFSCCR - - access: Read - byte_offset: 336 - description: Ethernet MMC transmitted good frames after more than a single collision - fieldset: MMCTGFMSCCR - name: MMCTGFMSCCR - - access: Read - byte_offset: 360 - description: Ethernet MMC transmitted good frames counter register - fieldset: MMCTGFCR - name: MMCTGFCR - - access: Read - byte_offset: 404 - description: Ethernet MMC received frames with CRC error counter register - fieldset: MMCRFCECR - name: MMCRFCECR - - access: Read - byte_offset: 408 - description: Ethernet MMC received frames with alignment error counter register - fieldset: MMCRFAECR - name: MMCRFAECR - - access: Read - byte_offset: 452 - description: MMC received good unicast frames counter register - fieldset: MMCRGUFCR - name: MMCRGUFCR + - name: DMABMR + description: Ethernet DMA bus mode register + byte_offset: 0 + fieldset: DMABMR + - name: DMATPDR + description: Ethernet DMA transmit poll demand register + byte_offset: 4 + fieldset: DMATPDR + - name: DMARPDR + description: EHERNET DMA receive poll demand register + byte_offset: 8 + fieldset: DMARPDR + - name: DMARDLAR + description: Ethernet DMA receive descriptor list address register + byte_offset: 12 + fieldset: DMARDLAR + - name: DMATDLAR + description: Ethernet DMA transmit descriptor list address register + byte_offset: 16 + fieldset: DMATDLAR + - name: DMASR + description: Ethernet DMA status register + byte_offset: 20 + fieldset: DMASR + - name: DMAOMR + description: Ethernet DMA operation mode register + byte_offset: 24 + fieldset: DMAOMR + - name: DMAIER + description: Ethernet DMA interrupt enable register + byte_offset: 28 + fieldset: DMAIER + - name: DMAMFBOCR + description: Ethernet DMA missed frame and buffer overflow counter register + byte_offset: 32 + fieldset: DMAMFBOCR + - name: DMARSWTR + description: Ethernet DMA receive status watchdog timer register + byte_offset: 36 + fieldset: DMARSWTR + - name: DMACHTDR + description: Ethernet DMA current host transmit descriptor register + byte_offset: 72 + access: Read + fieldset: DMACHTDR + - name: DMACHRDR + description: Ethernet DMA current host receive descriptor register + byte_offset: 76 + access: Read + fieldset: DMACHRDR + - name: DMACHTBAR + description: Ethernet DMA current host transmit buffer address register + byte_offset: 80 + access: Read + fieldset: DMACHTBAR + - name: DMACHRBAR + description: Ethernet DMA current host receive buffer address register + byte_offset: 84 + access: Read + fieldset: DMACHRBAR +block/ETHERNET_MAC: + description: "Ethernet: media access control (MAC)" + items: + - name: MACCR + description: Ethernet MAC configuration register + byte_offset: 0 + fieldset: MACCR + - name: MACFFR + description: Ethernet MAC frame filter register + byte_offset: 4 + fieldset: MACFFR + - name: MACHTHR + description: Ethernet MAC hash table high register + byte_offset: 8 + fieldset: MACHTHR + - name: MACHTLR + description: Ethernet MAC hash table low register + byte_offset: 12 + fieldset: MACHTLR + - name: MACMIIAR + description: Ethernet MAC MII address register + byte_offset: 16 + fieldset: MACMIIAR + - name: MACMIIDR + description: Ethernet MAC MII data register + byte_offset: 20 + fieldset: MACMIIDR + - name: MACFCR + description: Ethernet MAC flow control register + byte_offset: 24 + fieldset: MACFCR + - name: MACVLANTR + description: Ethernet MAC VLAN tag register + byte_offset: 28 + fieldset: MACVLANTR + - name: MACRWUFFR + description: Ethernet MAC remote wakeup frame filter register + byte_offset: 40 + - name: MACPMTCSR + description: Ethernet MAC PMT control and status register + byte_offset: 44 + fieldset: MACPMTCSR + - name: MACDBGR + description: Ethernet MAC debug register + byte_offset: 52 + access: Read + fieldset: MACDBGR + - name: MACSR + description: Ethernet MAC interrupt status register + byte_offset: 56 + fieldset: MACSR + - name: MACIMR + description: Ethernet MAC interrupt mask register + byte_offset: 60 + fieldset: MACIMR + - name: MACA0HR + description: Ethernet MAC address 0 high register + byte_offset: 64 + fieldset: MACA0HR + - name: MACA0LR + description: Ethernet MAC address 0 low register + byte_offset: 68 + fieldset: MACA0LR + - name: MACA1HR + description: Ethernet MAC address 1 high register + byte_offset: 72 + fieldset: MACA1HR + - name: MACA1LR + description: Ethernet MAC address1 low register + byte_offset: 76 + fieldset: MACA1LR + - name: MACA2HR + description: Ethernet MAC address 2 high register + byte_offset: 80 + fieldset: MACA2HR + - name: MACA2LR + description: Ethernet MAC address 2 low register + byte_offset: 84 + fieldset: MACA2LR + - name: MACA3HR + description: Ethernet MAC address 3 high register + byte_offset: 88 + fieldset: MACA3HR + - name: MACA3LR + description: Ethernet MAC address 3 low register + byte_offset: 92 + fieldset: MACA3LR + - name: MMCCR + description: Ethernet MMC control register + byte_offset: 256 + fieldset: MMCCR + - name: MMCRIR + description: Ethernet MMC receive interrupt register + byte_offset: 260 + fieldset: MMCRIR + - name: MMCTIR + description: Ethernet MMC transmit interrupt register + byte_offset: 264 + access: Read + fieldset: MMCTIR + - name: MMCRIMR + description: Ethernet MMC receive interrupt mask register + byte_offset: 268 + fieldset: MMCRIMR + - name: MMCTIMR + description: Ethernet MMC transmit interrupt mask register + byte_offset: 272 + fieldset: MMCTIMR + - name: MMCTGFSCCR + description: Ethernet MMC transmitted good frames after a single collision counter + byte_offset: 332 + access: Read + fieldset: MMCTGFSCCR + - name: MMCTGFMSCCR + description: Ethernet MMC transmitted good frames after more than a single collision + byte_offset: 336 + access: Read + fieldset: MMCTGFMSCCR + - name: MMCTGFCR + description: Ethernet MMC transmitted good frames counter register + byte_offset: 360 + access: Read + fieldset: MMCTGFCR + - name: MMCRFCECR + description: Ethernet MMC received frames with CRC error counter register + byte_offset: 404 + access: Read + fieldset: MMCRFCECR + - name: MMCRFAECR + description: Ethernet MMC received frames with alignment error counter register + byte_offset: 408 + access: Read + fieldset: MMCRFAECR + - name: MMCRGUFCR + description: MMC received good unicast frames counter register + byte_offset: 452 + access: Read + fieldset: MMCRGUFCR +block/ETHERNET_PTP: + description: "Ethernet: Precision time protocol" + items: + - name: PTPTSCR + description: Ethernet PTP time stamp control register + byte_offset: 0 + fieldset: PTPTSCR + - name: PTPSSIR + description: Ethernet PTP subsecond increment register + byte_offset: 4 + fieldset: PTPSSIR + - name: PTPTSHR + description: Ethernet PTP time stamp high register + byte_offset: 8 + access: Read + fieldset: PTPTSHR + - name: PTPTSLR + description: Ethernet PTP time stamp low register + byte_offset: 12 + access: Read + fieldset: PTPTSLR + - name: PTPTSHUR + description: Ethernet PTP time stamp high update register + byte_offset: 16 + fieldset: PTPTSHUR + - name: PTPTSLUR + description: Ethernet PTP time stamp low update register + byte_offset: 20 + fieldset: PTPTSLUR + - name: PTPTSAR + description: Ethernet PTP time stamp addend register + byte_offset: 24 + fieldset: PTPTSAR + - name: PTPTTHR + description: Ethernet PTP target time high register + byte_offset: 28 + fieldset: PTPTTHR + - name: PTPTTLR + description: Ethernet PTP target time low register + byte_offset: 32 + fieldset: PTPTTLR + - name: PTPTSSR + description: Ethernet PTP time stamp status register + byte_offset: 40 + access: Read + fieldset: PTPTSSR + - name: PTPPPSCR + description: Ethernet PTP PPS control register + byte_offset: 44 + access: Read + fieldset: PTPPPSCR +fieldset/DMABMR: + description: Ethernet DMA bus mode register + fields: + - name: SR + description: Software reset + bit_offset: 0 + bit_size: 1 + - name: DA + description: DMA arbitration + bit_offset: 1 + bit_size: 1 + enum: DA + - name: DSL + description: Descriptor skip length + bit_offset: 2 + bit_size: 5 + - name: EDFE + description: Enhanced descriptor format enable + bit_offset: 7 + bit_size: 1 + enum: EDFE + - name: PBL + description: Programmable burst length + bit_offset: 8 + bit_size: 6 + enum: PBL + - name: PM + description: Rx-Tx priority ratio + bit_offset: 14 + bit_size: 2 + enum: PriorityRxOverTx + - name: FB + description: Fixed burst + bit_offset: 16 + bit_size: 1 + enum: FB + - name: RDP + description: Rx DMA PBL + bit_offset: 17 + bit_size: 6 + enum: RDP + - name: USP + description: Use separate PBL + bit_offset: 23 + bit_size: 1 + enum: USP + - name: FPM + description: 4xPBL mode + bit_offset: 24 + bit_size: 1 + enum: FPM + - name: AAB + description: Address-aligned beats + bit_offset: 25 + bit_size: 1 + enum: AAB + - name: MB + description: Mixed burst + bit_offset: 26 + bit_size: 1 + enum: MB +fieldset/DMACHRBAR: + description: Ethernet DMA current host receive buffer address register + fields: + - name: HRBAP + description: Host receive buffer address pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACHRDR: + description: Ethernet DMA current host receive descriptor register + fields: + - name: HRDAP + description: Host receive descriptor address pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACHTBAR: + description: Ethernet DMA current host transmit buffer address register + fields: + - name: HTBAP + description: Host transmit buffer address pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACHTDR: + description: Ethernet DMA current host transmit descriptor register + fields: + - name: HTDAP + description: Host transmit descriptor address pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMAIER: + description: Ethernet DMA interrupt enable register + fields: + - name: TIE + description: Transmit interrupt enable + bit_offset: 0 + bit_size: 1 + - name: TPSIE + description: Transmit process stopped interrupt enable + bit_offset: 1 + bit_size: 1 + - name: TBUIE + description: Transmit buffer unavailable interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TJTIE + description: Transmit jabber timeout interrupt enable + bit_offset: 3 + bit_size: 1 + - name: ROIE + description: Receive overflow interrupt enable + bit_offset: 4 + bit_size: 1 + - name: TUIE + description: Transmit underflow interrupt enable + bit_offset: 5 + bit_size: 1 + - name: RIE + description: Receive interrupt enable + bit_offset: 6 + bit_size: 1 + - name: RBUIE + description: Receive buffer unavailable interrupt enable + bit_offset: 7 + bit_size: 1 + - name: RPSIE + description: Receive process stopped interrupt enable + bit_offset: 8 + bit_size: 1 + - name: RWTIE + description: Receive watchdog timeout interrupt enable + bit_offset: 9 + bit_size: 1 + - name: ETIE + description: Early transmit interrupt enable + bit_offset: 10 + bit_size: 1 + - name: FBEIE + description: Fatal bus error interrupt enable + bit_offset: 13 + bit_size: 1 + - name: ERIE + description: Early receive interrupt enable + bit_offset: 14 + bit_size: 1 + - name: AISE + description: Abnormal interrupt summary enable + bit_offset: 15 + bit_size: 1 + - name: NISE + description: Normal interrupt summary enable + bit_offset: 16 + bit_size: 1 +fieldset/DMAMFBOCR: + description: Ethernet DMA missed frame and buffer overflow counter register + fields: + - name: MFC + description: Missed frames by the controller + bit_offset: 0 + bit_size: 16 + - name: OMFC + description: Overflow bit for missed frame counter + bit_offset: 16 + bit_size: 1 + - name: MFA + description: Missed frames by the application + bit_offset: 17 + bit_size: 11 + - name: OFOC + description: Overflow bit for FIFO overflow counter + bit_offset: 28 + bit_size: 1 +fieldset/DMAOMR: + description: Ethernet DMA operation mode register + fields: + - name: SR + description: Start/stop receive + bit_offset: 1 + bit_size: 1 + enum: DMAOMR_SR + - name: OSF + description: Operate on second frame + bit_offset: 2 + bit_size: 1 + - name: RTC + description: Receive threshold control + bit_offset: 3 + bit_size: 2 + enum: RTC + - name: FUGF + description: Forward undersized good frames + bit_offset: 6 + bit_size: 1 + enum: FUGF + - name: FEF + description: Forward error frames + bit_offset: 7 + bit_size: 1 + enum: FEF + - name: ST + description: Start/stop transmission + bit_offset: 13 + bit_size: 1 + enum: ST + - name: TTC + description: Transmit threshold control + bit_offset: 14 + bit_size: 3 + enum: TTC + - name: FTF + description: Flush transmit FIFO + bit_offset: 20 + bit_size: 1 + enum: FTF + - name: TSF + description: Transmit store and forward + bit_offset: 21 + bit_size: 1 + enum: TSF + - name: DFRF + description: Disable flushing of received frames + bit_offset: 24 + bit_size: 1 + - name: RSF + description: Receive store and forward + bit_offset: 25 + bit_size: 1 + enum: RSF + - name: DTCEFD + description: Dropping of TCP/IP checksum error frames disable + bit_offset: 26 + bit_size: 1 + enum: DTCEFD +fieldset/DMARDLAR: + description: Ethernet DMA receive descriptor list address register + fields: + - name: SRL + description: Start of receive list + bit_offset: 0 + bit_size: 32 +fieldset/DMARPDR: + description: EHERNET DMA receive poll demand register + fields: + - name: RPD + description: Receive poll demand + bit_offset: 0 + bit_size: 32 + enum: RPD +fieldset/DMARSWTR: + description: Ethernet DMA receive status watchdog timer register + fields: + - name: RSWTC + description: Receive status watchdog timer count + bit_offset: 0 + bit_size: 8 +fieldset/DMASR: + description: Ethernet DMA status register + fields: + - name: TS + description: Transmit status + bit_offset: 0 + bit_size: 1 + - name: TPSS + description: Transmit process stopped status + bit_offset: 1 + bit_size: 1 + - name: TBUS + description: Transmit buffer unavailable status + bit_offset: 2 + bit_size: 1 + - name: TJTS + description: Transmit jabber timeout status + bit_offset: 3 + bit_size: 1 + - name: ROS + description: Receive overflow status + bit_offset: 4 + bit_size: 1 + - name: TUS + description: Transmit underflow status + bit_offset: 5 + bit_size: 1 + - name: RS + description: Receive status + bit_offset: 6 + bit_size: 1 + - name: RBUS + description: Receive buffer unavailable status + bit_offset: 7 + bit_size: 1 + - name: RPSS + description: Receive process stopped status + bit_offset: 8 + bit_size: 1 + - name: PWTS + description: PWTS + bit_offset: 9 + bit_size: 1 + - name: ETS + description: Early transmit status + bit_offset: 10 + bit_size: 1 + - name: FBES + description: Fatal bus error status + bit_offset: 13 + bit_size: 1 + - name: ERS + description: Early receive status + bit_offset: 14 + bit_size: 1 + - name: AIS + description: Abnormal interrupt summary + bit_offset: 15 + bit_size: 1 + - name: NIS + description: Normal interrupt summary + bit_offset: 16 + bit_size: 1 + - name: RPS + description: Receive process state + bit_offset: 17 + bit_size: 3 + enum: RPS + - name: TPS + description: Transmit process state + bit_offset: 20 + bit_size: 3 + enum: TPS + - name: EBS + description: Error bits status + bit_offset: 23 + bit_size: 3 + - name: MMCS + description: MMC status + bit_offset: 27 + bit_size: 1 + - name: PMTS + description: PMT status + bit_offset: 28 + bit_size: 1 + - name: TSTS + description: Time stamp trigger status + bit_offset: 29 + bit_size: 1 +fieldset/DMATDLAR: + description: Ethernet DMA transmit descriptor list address register + fields: + - name: STL + description: Start of transmit list + bit_offset: 0 + bit_size: 32 +fieldset/DMATPDR: + description: Ethernet DMA transmit poll demand register + fields: + - name: TPD + description: Transmit poll demand + bit_offset: 0 + bit_size: 32 + enum: TPD fieldset/MACA0HR: description: Ethernet MAC address 0 high register fields: - - bit_offset: 0 - bit_size: 16 + - name: MACA0H description: MAC address0 high - name: MACA0H - - bit_offset: 31 - bit_size: 1 + bit_offset: 0 + bit_size: 16 + - name: MO description: Always 1 - name: MO + bit_offset: 31 + bit_size: 1 fieldset/MACA0LR: description: Ethernet MAC address 0 low register fields: - - bit_offset: 0 + - name: MACA0L + description: "0" + bit_offset: 0 bit_size: 32 - description: '0' - name: MACA0L fieldset/MACA1HR: description: Ethernet MAC address 1 high register fields: - - bit_offset: 0 - bit_size: 16 + - name: MACA1H description: MACA1H - name: MACA1H - - bit_offset: 24 - bit_size: 6 + bit_offset: 0 + bit_size: 16 + - name: MBC description: MBC - name: MBC - - bit_offset: 30 - bit_size: 1 + bit_offset: 24 + bit_size: 6 + - name: SA description: SA - enum: MACAHR_SA - name: SA - - bit_offset: 31 + bit_offset: 30 bit_size: 1 + enum: MACAHR_SA + - name: AE description: AE + bit_offset: 31 + bit_size: 1 enum: MACAHR_AE - name: AE fieldset/MACA1LR: description: Ethernet MAC address1 low register fields: - - bit_offset: 0 - bit_size: 32 + - name: MACA1L description: MACA1LR - name: MACA1L + bit_offset: 0 + bit_size: 32 fieldset/MACA2HR: description: Ethernet MAC address 2 high register fields: - - bit_offset: 0 - bit_size: 16 + - name: MACA2H description: MAC2AH - name: MACA2H - - bit_offset: 24 - bit_size: 6 + bit_offset: 0 + bit_size: 16 + - name: MBC description: MBC - name: MBC - - bit_offset: 30 - bit_size: 1 + bit_offset: 24 + bit_size: 6 + - name: SA description: SA - enum: MACAHR_SA - name: SA - - bit_offset: 31 + bit_offset: 30 bit_size: 1 + enum: MACAHR_SA + - name: AE description: AE + bit_offset: 31 + bit_size: 1 enum: MACAHR_AE - name: AE fieldset/MACA2LR: description: Ethernet MAC address 2 low register fields: - - bit_offset: 0 - bit_size: 32 + - name: MACA2L description: MACA2L - name: MACA2L + bit_offset: 0 + bit_size: 32 fieldset/MACA3HR: description: Ethernet MAC address 3 high register fields: - - bit_offset: 0 - bit_size: 16 + - name: MACA3H description: MACA3H - name: MACA3H - - bit_offset: 24 - bit_size: 6 + bit_offset: 0 + bit_size: 16 + - name: MBC description: MBC - name: MBC - - bit_offset: 30 - bit_size: 1 + bit_offset: 24 + bit_size: 6 + - name: SA description: SA - enum: MACAHR_SA - name: SA - - bit_offset: 31 + bit_offset: 30 bit_size: 1 + enum: MACAHR_SA + - name: AE description: AE + bit_offset: 31 + bit_size: 1 enum: MACAHR_AE - name: AE fieldset/MACA3LR: description: Ethernet MAC address 3 low register fields: - - bit_offset: 0 - bit_size: 32 + - name: MACA3L description: MBCA3L - name: MACA3L + bit_offset: 0 + bit_size: 32 fieldset/MACCR: description: Ethernet MAC configuration register fields: - - bit_offset: 2 - bit_size: 1 + - name: RE description: Receiver enable - name: RE - - bit_offset: 3 + bit_offset: 2 bit_size: 1 + - name: TE description: Transmitter enable - name: TE - - bit_offset: 4 + bit_offset: 3 bit_size: 1 + - name: DC description: Deferral check + bit_offset: 4 + bit_size: 1 enum: DC - name: DC - - bit_offset: 5 - bit_size: 2 + - name: BL description: Back-off limit + bit_offset: 5 + bit_size: 2 enum: BL - name: BL - - bit_offset: 7 - bit_size: 1 + - name: APCS description: Automatic pad/CRC stripping + bit_offset: 7 + bit_size: 1 enum: APCS - name: APCS - - bit_offset: 9 - bit_size: 1 + - name: RD description: Retry disable + bit_offset: 9 + bit_size: 1 enum: RD - name: RD - - bit_offset: 10 - bit_size: 1 + - name: IPCO description: IPv4 checksum offload + bit_offset: 10 + bit_size: 1 enum: IPCO - name: IPCO - - bit_offset: 11 - bit_size: 1 + - name: DM description: Duplex mode + bit_offset: 11 + bit_size: 1 enum: DM - name: DM - - bit_offset: 12 - bit_size: 1 + - name: LM description: Loopback mode + bit_offset: 12 + bit_size: 1 enum: LM - name: LM - - bit_offset: 13 - bit_size: 1 + - name: ROD description: Receive own disable + bit_offset: 13 + bit_size: 1 enum: ROD - name: ROD - - bit_offset: 14 - bit_size: 1 + - name: FES description: Fast Ethernet speed + bit_offset: 14 + bit_size: 1 enum: FES - name: FES - - bit_offset: 16 - bit_size: 1 + - name: CSD description: Carrier sense disable + bit_offset: 16 + bit_size: 1 enum: CSD - name: CSD - - bit_offset: 17 - bit_size: 3 + - name: IFG description: Interframe gap + bit_offset: 17 + bit_size: 3 enum: IFG - name: IFG - - bit_offset: 22 - bit_size: 1 + - name: JD description: Jabber disable + bit_offset: 22 + bit_size: 1 enum: JD - name: JD - - bit_offset: 23 - bit_size: 1 + - name: WD description: Watchdog disable - enum: WD - name: WD - - bit_offset: 25 + bit_offset: 23 bit_size: 1 + enum: WD + - name: CSTF description: CRC stripping for type frames + bit_offset: 25 + bit_size: 1 enum: CSTF - name: CSTF fieldset/MACDBGR: description: Ethernet MAC debug register fields: - - bit_offset: 0 - bit_size: 1 + - name: MMRPEA description: MAC MII receive protocol engine active - name: MMRPEA - - bit_offset: 1 - bit_size: 2 + bit_offset: 0 + bit_size: 1 + - name: MSFRWCS description: MAC small FIFO read/write controllers status - name: MSFRWCS - - bit_offset: 4 - bit_size: 1 + bit_offset: 1 + bit_size: 2 + - name: RFWRA description: Rx FIFO write controller active - name: RFWRA - - bit_offset: 5 - bit_size: 2 + bit_offset: 4 + bit_size: 1 + - name: RFRCS description: Rx FIFO read controller status - name: RFRCS - - bit_offset: 8 + bit_offset: 5 bit_size: 2 + - name: RFFL description: Rx FIFO fill level - name: RFFL - - bit_offset: 16 - bit_size: 1 + bit_offset: 8 + bit_size: 2 + - name: MMTEA description: MAC MII transmit engine active - name: MMTEA - - bit_offset: 17 - bit_size: 2 + bit_offset: 16 + bit_size: 1 + - name: MTFCS description: MAC transmit frame controller status - name: MTFCS - - bit_offset: 19 - bit_size: 1 - description: MAC transmitter in pause - name: MTP - - bit_offset: 20 + bit_offset: 17 bit_size: 2 + - name: MTP + description: MAC transmitter in pause + bit_offset: 19 + bit_size: 1 + - name: TFRS description: Tx FIFO read status - name: TFRS - - bit_offset: 22 - bit_size: 1 + bit_offset: 20 + bit_size: 2 + - name: TFWA description: Tx FIFO write active - name: TFWA - - bit_offset: 24 + bit_offset: 22 bit_size: 1 + - name: TFNE description: Tx FIFO not empty - name: TFNE - - bit_offset: 25 + bit_offset: 24 bit_size: 1 + - name: TFF description: Tx FIFO full - name: TFF + bit_offset: 25 + bit_size: 1 fieldset/MACFCR: description: Ethernet MAC flow control register fields: - - bit_offset: 0 - bit_size: 1 + - name: FCB description: Flow control busy/back pressure activate + bit_offset: 0 + bit_size: 1 enum: FCB - name: FCB - - bit_offset: 1 - bit_size: 1 + - name: TFCE description: Transmit flow control enable + bit_offset: 1 + bit_size: 1 enum: TFCE - name: TFCE - - bit_offset: 2 - bit_size: 1 + - name: RFCE description: Receive flow control enable + bit_offset: 2 + bit_size: 1 enum: RFCE - name: RFCE - - bit_offset: 3 - bit_size: 1 + - name: UPFD description: Unicast pause frame detect - enum: UPFD - name: UPFD - - bit_offset: 4 - bit_size: 2 - description: Pause low threshold - enum: PLT - name: PLT - - bit_offset: 7 + bit_offset: 3 bit_size: 1 + enum: UPFD + - name: PLT + description: Pause low threshold + bit_offset: 4 + bit_size: 2 + enum: PLT + - name: ZQPD description: Zero-quanta pause disable + bit_offset: 7 + bit_size: 1 enum: ZQPD - name: ZQPD - - bit_offset: 16 - bit_size: 16 + - name: PT description: Pause time - name: PT + bit_offset: 16 + bit_size: 16 fieldset/MACFFR: description: Ethernet MAC frame filter register fields: - - bit_offset: 0 - bit_size: 1 + - name: PM description: Promiscuous mode + bit_offset: 0 + bit_size: 1 enum: PM - name: PM - - bit_offset: 1 - bit_size: 1 + - name: HU description: Hash unicast + bit_offset: 1 + bit_size: 1 enum: HU - name: HU - - bit_offset: 2 - bit_size: 1 + - name: HM description: Hash multicast + bit_offset: 2 + bit_size: 1 enum: HM - name: HM - - bit_offset: 3 - bit_size: 1 + - name: DAIF description: Destination address unique filtering + bit_offset: 3 + bit_size: 1 enum: DAIF - name: DAIF - - bit_offset: 4 - bit_size: 1 + - name: PAM description: Pass all multicast + bit_offset: 4 + bit_size: 1 enum: PAM - name: PAM - - bit_offset: 5 - bit_size: 1 + - name: BFD description: Broadcast frames disable + bit_offset: 5 + bit_size: 1 enum: BFD - name: BFD - - bit_offset: 6 - bit_size: 2 + - name: PCF description: Pass control frames + bit_offset: 6 + bit_size: 2 enum: PCF - name: PCF - - bit_offset: 7 - bit_size: 1 + - name: SAIF description: Source address inverse filtering + bit_offset: 7 + bit_size: 1 enum: SAIF - name: SAIF - - bit_offset: 8 - bit_size: 1 + - name: SAF description: Source address filter + bit_offset: 8 + bit_size: 1 enum: SAF - name: SAF - - bit_offset: 9 - bit_size: 1 + - name: HPF description: Hash or perfect filter - enum: HPF - name: HPF - - bit_offset: 31 + bit_offset: 9 bit_size: 1 + enum: HPF + - name: RA description: Receive all + bit_offset: 31 + bit_size: 1 enum: RA - name: RA fieldset/MACHTHR: description: Ethernet MAC hash table high register fields: - - bit_offset: 0 - bit_size: 32 + - name: HTH description: Upper 32 bits of hash table - name: HTH + bit_offset: 0 + bit_size: 32 fieldset/MACHTLR: description: Ethernet MAC hash table low register fields: - - bit_offset: 0 - bit_size: 32 + - name: HTL description: Lower 32 bits of hash table - name: HTL + bit_offset: 0 + bit_size: 32 fieldset/MACIMR: description: Ethernet MAC interrupt mask register fields: - - bit_offset: 3 - bit_size: 1 + - name: PMTIM description: PMT interrupt mask - enum: PMTIM - name: PMTIM - - bit_offset: 9 + bit_offset: 3 bit_size: 1 + enum: PMTIM + - name: TSTIM description: Time stamp trigger interrupt mask + bit_offset: 9 + bit_size: 1 enum: TSTIM - name: TSTIM fieldset/MACMIIAR: description: Ethernet MAC MII address register fields: - - bit_offset: 0 - bit_size: 1 + - name: MB description: MII busy - enum: MB_progress - name: MB - - bit_offset: 1 + bit_offset: 0 bit_size: 1 + enum: MB_progress + - name: MW description: MII write + bit_offset: 1 + bit_size: 1 enum: MW - name: MW - - bit_offset: 2 - bit_size: 3 + - name: CR description: Clock range + bit_offset: 2 + bit_size: 3 enum: CR - name: CR - - bit_offset: 6 - bit_size: 5 + - name: MR description: MII register - select the desired MII register in the PHY device - name: MR - - bit_offset: 11 + bit_offset: 6 bit_size: 5 + - name: PA description: PHY address - select which of possible 32 PHYs is being accessed - name: PA + bit_offset: 11 + bit_size: 5 fieldset/MACMIIDR: description: Ethernet MAC MII data register fields: - - bit_offset: 0 - bit_size: 16 + - name: MD description: MII data read from/written to the PHY - name: MD + bit_offset: 0 + bit_size: 16 fieldset/MACPMTCSR: description: Ethernet MAC PMT control and status register fields: - - bit_offset: 0 - bit_size: 1 + - name: PD description: Power down + bit_offset: 0 + bit_size: 1 enum: PD - name: PD - - bit_offset: 1 - bit_size: 1 + - name: MPE description: Magic packet enable + bit_offset: 1 + bit_size: 1 enum: MPE - name: MPE - - bit_offset: 2 - bit_size: 1 + - name: WFE description: Wakeup frame enable + bit_offset: 2 + bit_size: 1 enum: WFE - name: WFE - - bit_offset: 5 - bit_size: 1 + - name: MPR description: Magic packet received - name: MPR - - bit_offset: 6 + bit_offset: 5 bit_size: 1 + - name: WFR description: Wakeup frame received - name: WFR - - bit_offset: 9 + bit_offset: 6 bit_size: 1 + - name: GU description: Global unicast - enum: GU - name: GU - - bit_offset: 31 + bit_offset: 9 bit_size: 1 + enum: GU + - name: WFFRPR description: Wakeup frame filter register pointer reset + bit_offset: 31 + bit_size: 1 enum: WFFRPR - name: WFFRPR fieldset/MACSR: description: Ethernet MAC interrupt status register fields: - - bit_offset: 3 - bit_size: 1 + - name: PMTS description: PMT status - name: PMTS - - bit_offset: 4 + bit_offset: 3 bit_size: 1 + - name: MMCS description: MMC status - name: MMCS - - bit_offset: 5 + bit_offset: 4 bit_size: 1 + - name: MMCRS description: MMC receive status - name: MMCRS - - bit_offset: 6 + bit_offset: 5 bit_size: 1 + - name: MMCTS description: MMC transmit status - name: MMCTS - - bit_offset: 9 + bit_offset: 6 bit_size: 1 + - name: TSTS description: Time stamp trigger status - name: TSTS + bit_offset: 9 + bit_size: 1 fieldset/MACVLANTR: description: Ethernet MAC VLAN tag register fields: - - bit_offset: 0 - bit_size: 16 + - name: VLANTI description: VLAN tag identifier (for receive frames) - name: VLANTI - - bit_offset: 16 - bit_size: 1 + bit_offset: 0 + bit_size: 16 + - name: VLANTC description: 12-bit VLAN tag comparison + bit_offset: 16 + bit_size: 1 enum: VLANTC - name: VLANTC - +fieldset/MMCCR: + description: Ethernet MMC control register + fields: + - name: CR + description: Counter reset + bit_offset: 0 + bit_size: 1 + enum: CounterReset + - name: CSR + description: Counter stop rollover + bit_offset: 1 + bit_size: 1 + enum: CSR + - name: ROR + description: Reset on read + bit_offset: 2 + bit_size: 1 + enum: ROR + - name: MCF + description: MMC counter freeze + bit_offset: 3 + bit_size: 1 + enum: MCF + - name: MCP + description: MMC counter preset + bit_offset: 4 + bit_size: 1 + enum: MCP + - name: MCFHP + description: MMC counter Full-Half preset + bit_offset: 5 + bit_size: 1 + enum: MCFHP +fieldset/MMCRFAECR: + description: Ethernet MMC received frames with alignment error counter register + fields: + - name: RFAEC + description: RFAEC + bit_offset: 0 + bit_size: 32 +fieldset/MMCRFCECR: + description: Ethernet MMC received frames with CRC error counter register + fields: + - name: RFCFC + description: RFCFC + bit_offset: 0 + bit_size: 32 +fieldset/MMCRGUFCR: + description: MMC received good unicast frames counter register + fields: + - name: RGUFC + description: RGUFC + bit_offset: 0 + bit_size: 32 +fieldset/MMCRIMR: + description: Ethernet MMC receive interrupt mask register + fields: + - name: RFCEM + description: Received frame CRC error mask + bit_offset: 5 + bit_size: 1 + enum: RFCEM + - name: RFAEM + description: Received frames alignment error mask + bit_offset: 6 + bit_size: 1 + enum: RFAEM + - name: RGUFM + description: Received good Unicast frames mask + bit_offset: 17 + bit_size: 1 + enum: RGUFM +fieldset/MMCRIR: + description: Ethernet MMC receive interrupt register + fields: + - name: RFCES + description: Received frames CRC error status + bit_offset: 5 + bit_size: 1 + - name: RFAES + description: Received frames alignment error status + bit_offset: 6 + bit_size: 1 + - name: RGUFS + description: Received good Unicast frames status + bit_offset: 17 + bit_size: 1 +fieldset/MMCTGFCR: + description: Ethernet MMC transmitted good frames counter register + fields: + - name: TGFC + description: HTL + bit_offset: 0 + bit_size: 32 +fieldset/MMCTGFMSCCR: + description: Ethernet MMC transmitted good frames after more than a single collision + fields: + - name: TGFMSCC + description: TGFMSCC + bit_offset: 0 + bit_size: 32 +fieldset/MMCTGFSCCR: + description: Ethernet MMC transmitted good frames after a single collision counter + fields: + - name: TGFSCC + description: Transmitted good frames single collision counter + bit_offset: 0 + bit_size: 32 +fieldset/MMCTIMR: + description: Ethernet MMC transmit interrupt mask register + fields: + - name: TGFSCM + description: Transmitted good frames single collision mask + bit_offset: 14 + bit_size: 1 + enum: TGFSCM + - name: TGFMSCM + description: Transmitted good frames more than single collision mask + bit_offset: 15 + bit_size: 1 + enum: TGFMSCM + - name: TGFM + description: Transmitted good frames mask + bit_offset: 16 + bit_size: 1 + enum: TGFM +fieldset/MMCTIR: + description: Ethernet MMC transmit interrupt register + fields: + - name: TGFSCS + description: Transmitted good frames single collision status + bit_offset: 14 + bit_size: 1 + - name: TGFMSCS + description: Transmitted good frames more than single collision status + bit_offset: 15 + bit_size: 1 + - name: TGFS + description: Transmitted good frames status + bit_offset: 21 + bit_size: 1 +fieldset/PTPPPSCR: + description: Ethernet PTP PPS control register + fields: + - name: TSSO + description: TSSO + bit_offset: 0 + bit_size: 1 + - name: TSTTR + description: TSTTR + bit_offset: 1 + bit_size: 1 +fieldset/PTPSSIR: + description: Ethernet PTP subsecond increment register + fields: + - name: STSSI + description: STSSI + bit_offset: 0 + bit_size: 8 +fieldset/PTPTSAR: + description: Ethernet PTP time stamp addend register + fields: + - name: TSA + description: TSA + bit_offset: 0 + bit_size: 32 +fieldset/PTPTSCR: + description: Ethernet PTP time stamp control register + fields: + - name: TSE + description: TSE + bit_offset: 0 + bit_size: 1 + - name: TSFCU + description: TSFCU + bit_offset: 1 + bit_size: 1 + - name: TSSTI + description: TSSTI + bit_offset: 2 + bit_size: 1 + - name: TSSTU + description: TSSTU + bit_offset: 3 + bit_size: 1 + - name: TSITE + description: TSITE + bit_offset: 4 + bit_size: 1 + - name: TTSARU + description: TTSARU + bit_offset: 5 + bit_size: 1 + - name: TSSARFE + description: TSSARFE + bit_offset: 8 + bit_size: 1 + - name: TSSSR + description: TSSSR + bit_offset: 9 + bit_size: 1 + - name: TSPTPPSV2E + description: TSPTPPSV2E + bit_offset: 10 + bit_size: 1 + - name: TSSPTPOEFE + description: TSSPTPOEFE + bit_offset: 11 + bit_size: 1 + - name: TSSIPV6FE + description: TSSIPV6FE + bit_offset: 12 + bit_size: 1 + - name: TSSIPV4FE + description: TSSIPV4FE + bit_offset: 13 + bit_size: 1 + - name: TSSEME + description: TSSEME + bit_offset: 14 + bit_size: 1 + - name: TSSMRME + description: TSSMRME + bit_offset: 15 + bit_size: 1 + - name: TSCNT + description: TSCNT + bit_offset: 16 + bit_size: 2 + - name: TSPFFMAE + description: TSPFFMAE + bit_offset: 18 + bit_size: 1 +fieldset/PTPTSHR: + description: Ethernet PTP time stamp high register + fields: + - name: STS + description: STS + bit_offset: 0 + bit_size: 32 +fieldset/PTPTSHUR: + description: Ethernet PTP time stamp high update register + fields: + - name: TSUS + description: TSUS + bit_offset: 0 + bit_size: 32 +fieldset/PTPTSLR: + description: Ethernet PTP time stamp low register + fields: + - name: STSS + description: STSS + bit_offset: 0 + bit_size: 31 + - name: STPNS + description: STPNS + bit_offset: 31 + bit_size: 1 +fieldset/PTPTSLUR: + description: Ethernet PTP time stamp low update register + fields: + - name: TSUSS + description: TSUSS + bit_offset: 0 + bit_size: 31 + - name: TSUPNS + description: TSUPNS + bit_offset: 31 + bit_size: 1 +fieldset/PTPTSSR: + description: Ethernet PTP time stamp status register + fields: + - name: TSSO + description: TSSO + bit_offset: 0 + bit_size: 1 + - name: TSTTR + description: TSSO + bit_offset: 1 + bit_size: 1 +fieldset/PTPTTHR: + description: Ethernet PTP target time high register + fields: + - name: TTSH + description: "0" + bit_offset: 0 + bit_size: 32 +fieldset/PTPTTLR: + description: Ethernet PTP target time low register + fields: + - name: TTSL + description: TTSL + bit_offset: 0 + bit_size: 32 +enum/AAB: + bit_size: 1 + variants: + - name: Unaligned + description: Bursts are not aligned + value: 0 + - name: Aligned + description: Align bursts to start address LS bits. First burst alignment depends on FB bit + value: 1 enum/APCS: bit_size: 1 variants: - - description: MAC passes all incoming frames unmodified - name: Disabled - value: 0 - - description: MAC strips the Pad/FCS field on incoming frames only for lengths - less than or equal to 1500 bytes - name: Strip - value: 1 + - name: Disabled + description: MAC passes all incoming frames unmodified + value: 0 + - name: Strip + description: MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes + value: 1 enum/BFD: bit_size: 1 variants: - - description: Address filters pass all received broadcast frames - name: Enabled - value: 0 - - description: Address filters filter all incoming broadcast frames - name: Disabled - value: 1 + - name: Enabled + description: Address filters pass all received broadcast frames + value: 0 + - name: Disabled + description: Address filters filter all incoming broadcast frames + value: 1 enum/BL: bit_size: 2 variants: - - description: For retransmission n, wait up to 2^min(n, 10) time slots - name: BL10 - value: 0 - - description: For retransmission n, wait up to 2^min(n, 8) time slots - name: BL8 - value: 1 - - description: For retransmission n, wait up to 2^min(n, 4) time slots - name: BL4 - value: 2 - - description: For retransmission n, wait up to 2^min(n, 1) time slots - name: BL1 - value: 3 + - name: BL10 + description: "For retransmission n, wait up to 2^min(n, 10) time slots" + value: 0 + - name: BL8 + description: "For retransmission n, wait up to 2^min(n, 8) time slots" + value: 1 + - name: BL4 + description: "For retransmission n, wait up to 2^min(n, 4) time slots" + value: 2 + - name: BL1 + description: "For retransmission n, wait up to 2^min(n, 1) time slots" + value: 3 enum/CR: bit_size: 3 variants: - - description: 60-100MHz HCLK/42 - name: CR_60_100 - value: 0 - - description: 100-150 MHz HCLK/62 - name: CR_100_150 - value: 1 - - description: 20-35MHz HCLK/16 - name: CR_20_35 - value: 2 - - description: 35-60MHz HCLK/16 - name: CR_35_60 - value: 3 - - description: 150-168MHz HCLK/102 - name: CR_150_168 - value: 4 + - name: CR_60_100 + description: 60-100MHz HCLK/42 + value: 0 + - name: CR_100_150 + description: 100-150 MHz HCLK/62 + value: 1 + - name: CR_20_35 + description: 20-35MHz HCLK/16 + value: 2 + - name: CR_35_60 + description: 35-60MHz HCLK/16 + value: 3 + - name: CR_150_168 + description: 150-168MHz HCLK/102 + value: 4 enum/CSD: bit_size: 1 variants: - - description: Errors generated due to loss of carrier - name: Enabled - value: 0 - - description: No error generated due to loss of carrier - name: Disabled - value: 1 -enum/CSTF: - bit_size: 1 - variants: - - description: CRC not stripped - name: Disabled - value: 0 - - description: CRC stripped - name: Enabled - value: 1 -enum/DAIF: - bit_size: 1 - variants: - - description: Normal filtering of frames - name: Normal - value: 0 - - description: Address check block operates in inverse filtering mode for the DA - address comparison - name: Invert - value: 1 -enum/DC: - bit_size: 1 - variants: - - description: MAC defers until CRS signal goes inactive - name: Disabled - value: 0 - - description: Deferral check function enabled - name: Enabled - value: 1 -enum/DM: - bit_size: 1 - variants: - - description: MAC operates in half-duplex mode - name: HalfDuplex - value: 0 - - description: MAC operates in full-duplex mode - name: FullDuplex - value: 1 -enum/FCB: - bit_size: 1 - variants: - - description: In half duplex only, deasserts back pressure - name: DisableBackPressure - value: 0 - - description: In full duplex, initiate a Pause control frame. In half duplex, assert - back pressure - name: PauseOrBackPressure - value: 1 -enum/FES: - bit_size: 1 - variants: - - description: 10 Mbit/s - name: FES10 - value: 0 - - description: 100 Mbit/s - name: FES100 - value: 1 -enum/GU: - bit_size: 1 - variants: - - description: Normal operation - name: Disabled - value: 0 - - description: Any unicast packet filtered by the MAC address recognition may be - a wakeup frame - name: Enabled - value: 1 -enum/HM: - bit_size: 1 - variants: - - description: MAC performs a perfect destination address filtering for multicast - frames - name: Perfect - value: 0 - - description: MAC performs destination address filtering of received multicast - frames according to the hash table - name: Hash - value: 1 -enum/HPF: - bit_size: 1 - variants: - - description: If HM or HU is set, only frames that match the Hash filter are passed - name: HashOnly - value: 0 - - description: If HM or HU is set, frames that match either the perfect filter or - the hash filter are passed - name: HashOrPerfect - value: 1 -enum/HU: - bit_size: 1 - variants: - - description: MAC performs a perfect destination address filtering for unicast - frames - name: Perfect - value: 0 - - description: MAC performs destination address filtering of received unicast frames - according to the hash table - name: Hash - value: 1 -enum/IFG: - bit_size: 3 - variants: - - description: 96 bit times - name: IFG96 - value: 0 - - description: 88 bit times - name: IFG88 - value: 1 - - description: 80 bit times - name: IFG80 - value: 2 - - description: 72 bit times - name: IFG72 - value: 3 - - description: 64 bit times - name: IFG64 - value: 4 - - description: 56 bit times - name: IFG56 - value: 5 - - description: 48 bit times - name: IFG48 - value: 6 - - description: 40 bit times - name: IFG40 - value: 7 -enum/IPCO: - bit_size: 1 - variants: - - description: IPv4 checksum offload disabled - name: Disabled - value: 0 - - description: IPv4 checksums are checked in received frames - name: Offload - value: 1 -enum/JD: - bit_size: 1 - variants: - - description: Jabber enabled, transmit frames up to 2048 bytes - name: Enabled - value: 0 - - description: Jabber disabled, transmit frames up to 16384 bytes - name: Disabled - value: 1 -enum/LM: - bit_size: 1 - variants: - - description: Normal mode - name: Normal - value: 0 - - description: MAC operates in loopback mode at the MII - name: Loopback - value: 1 -enum/MACAHR_AE: - bit_size: 1 - variants: - - description: Address filters ignore this address - name: Disabled - value: 0 - - description: Address filters use this address - name: Enabled - value: 1 -enum/MACAHR_SA: - bit_size: 1 - variants: - - description: This address is used for comparison with DA fields of the received - frame - name: Destination - value: 0 - - description: This address is used for comparison with SA fields of received frames - name: Source - value: 1 -enum/MB_progress: - bit_size: 1 - variants: - - description: This bit is set to 1 by the application to indicate that a read or - write access is in progress - name: Busy - value: 1 -enum/MPE: - bit_size: 1 - variants: - - description: No power management event generated due to Magic Packet reception - name: Disabled - value: 0 - - description: Enable generation of a power management event due to Magic Packet - reception - name: Enabled - value: 1 -enum/MW: - bit_size: 1 - variants: - - description: Read operation - name: Read - value: 0 - - description: Write operation - name: Write - value: 1 -enum/PAM: - bit_size: 1 - variants: - - description: Filtering of multicast frames depends on HM - name: Disabled - value: 0 - - description: All received frames with a multicast destination address are passed - name: Enabled - value: 1 -enum/PCF: - bit_size: 2 - variants: - - description: MAC prevents all control frames from reaching the application - name: PreventAll - value: 0 - - description: MAC forwards all control frames to application except Pause - name: ForwardAllExceptPause - value: 1 - - description: MAC forwards all control frames to application even if they fail - the address filter - name: ForwardAll - value: 2 - - description: MAC forwards control frames that pass the address filter - name: ForwardAllFiltered - value: 3 -enum/PD: - bit_size: 1 - variants: - - description: All received frames will be dropped. Cleared automatically when a - magic packet or wakeup frame is received - name: Enabled - value: 1 -enum/PLT: - bit_size: 2 - variants: - - description: Pause time minus 4 slot times - name: PLT4 - value: 0 - - description: Pause time minus 28 slot times - name: PLT28 - value: 1 - - description: Pause time minus 144 slot times - name: PLT144 - value: 2 - - description: Pause time minus 256 slot times - name: PLT256 - value: 3 -enum/PM: - bit_size: 1 - variants: - - description: Normal address filtering - name: Disabled - value: 0 - - description: Address filters pass all incoming frames regardless of their destination - or source address - name: Enabled - value: 1 -enum/PMTIM: - bit_size: 1 - variants: - - description: PMT Status interrupt generation enabled - name: Unmasked - value: 0 - - description: PMT Status interrupt generation disabled - name: Masked - value: 1 -enum/RA: - bit_size: 1 - variants: - - description: MAC receiver passes on to the application only those frames that - have passed the SA/DA address file - name: Disabled - value: 0 - - description: MAC receiver passes oll received frames on to the application - name: Enabled - value: 1 -enum/RD: - bit_size: 1 - variants: - - description: MAC attempts retries based on the settings of BL - name: Enabled - value: 0 - - description: MAC attempts only 1 transmission - name: Disabled - value: 1 -enum/RE: - bit_size: 1 - variants: - - description: MAC receive state machine is disabled after the completion of the - reception of the current frame - name: Disabled - value: 0 - - description: MAC receive state machine is enabled - name: Enabled - value: 1 -enum/RFCE: - bit_size: 1 - variants: - - description: Pause frames are not decoded - name: Disabled - value: 0 - - description: MAC decodes received Pause frames and disables its transmitted for - a specified time - name: Enabled - value: 1 -enum/ROD: - bit_size: 1 - variants: - - description: MAC receives all packets from PHY while transmitting - name: Enabled - value: 0 - - description: MAC disables reception of frames in half-duplex mode - name: Disabled - value: 1 -enum/SAF: - bit_size: 1 - variants: - - description: Source address ignored - name: Disabled - value: 0 - - description: MAC drops frames that fail the source address filter - name: Enabled - value: 1 -enum/SAIF: - bit_size: 1 - variants: - - description: Source address filter operates normally - name: Normal - value: 0 - - description: Source address filter operation inverted - name: Invert - value: 1 -enum/TE: - bit_size: 1 - variants: - - description: MAC transmit state machine is disabled after completion of the transmission - of the current frame - name: Disabled - value: 0 - - description: MAC transmit state machine is enabled - name: Enabled - value: 1 -enum/TFCE: - bit_size: 1 - variants: - - description: In full duplex, flow control is disabled. In half duplex, back pressure - is disabled - name: Disabled - value: 0 - - description: In full duplex, flow control is enabled. In half duplex, back pressure - is enabled - name: Enabled - value: 1 -enum/TSTIM: - bit_size: 1 - variants: - - description: Time stamp interrupt generation enabled - name: Unmasked - value: 0 - - description: Time stamp interrupt generation disabled - name: Masked - value: 1 -enum/UPFD: - bit_size: 1 - variants: - - description: MAC detects only a Pause frame with the multicast address specified - in the 802.3x standard - name: Disabled - value: 0 - - description: MAC additionally detects Pause frames with the station's unicast - address - name: Enabled - value: 1 -enum/VLANTC: - bit_size: 1 - variants: - - description: Full 16 bit VLAN identifiers are used for comparison and filtering - name: VLANTC16 - value: 0 - - description: 12 bit VLAN identifies are used for comparison and filtering - name: VLANTC12 - value: 1 -enum/WD: - bit_size: 1 - variants: - - description: Watchdog enabled, receive frames limited to 2048 bytes - name: Enabled - value: 0 - - description: Watchdog disabled, receive frames may be up to to 16384 bytes - name: Disabled - value: 1 -enum/WFE: - bit_size: 1 - variants: - - description: No power management event generated due to wakeup frame reception - name: Disabled - value: 0 - - description: Enable generation of a power management event due to wakeup frame - reception - name: Enabled - value: 1 -enum/WFFRPR: - bit_size: 1 - variants: - - description: Reset wakeup frame filter register point to 0b000. Automatically - cleared - name: Reset - value: 1 -enum/ZQPD: - bit_size: 1 - variants: - - description: Normal operation with automatic zero-quanta pause control frame generation - name: Enabled - value: 0 - - description: Automatic generation of zero-quanta pause control frames is disabled - name: Disabled - value: 1 -enum/CounterReset: - bit_size: 1 - variants: - - description: Reset all counters. Cleared automatically - name: Reset + - name: Enabled + description: Errors generated due to loss of carrier + value: 0 + - name: Disabled + description: No error generated due to loss of carrier value: 1 enum/CSR: bit_size: 1 variants: - - description: Counters roll over to zero after reaching the maximum value - name: Disabled + - name: Disabled + description: Counters roll over to zero after reaching the maximum value value: 0 - - description: Counters do not roll over to zero after reaching the maximum value - name: Enabled + - name: Enabled + description: Counters do not roll over to zero after reaching the maximum value value: 1 -enum/MCF: +enum/CSTF: bit_size: 1 variants: - - description: All MMC counters update normally - name: Unfrozen + - name: Disabled + description: CRC not stripped value: 0 - - description: All MMC counters frozen to their current value - name: Frozen + - name: Enabled + description: CRC stripped value: 1 -enum/MCFHP: +enum/CounterReset: bit_size: 1 variants: - - description: When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0 - name: AlmostHalf - value: 0 - - description: When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0 - name: AlmostFull - value: 1 -enum/MCP: - bit_size: 1 - variants: - - description: MMC counters will be preset to almost full or almost half. Cleared - automatically - name: Preset - value: 1 -enum/RFAEM: - bit_size: 1 - variants: - - description: Received-alignment-error counter half-full interrupt enabled - name: Unmasked - value: 0 - - description: Received-alignment-error counter half-full interrupt disabled - name: Masked - value: 1 -enum/RFCEM: - bit_size: 1 - variants: - - description: Received-crc-error counter half-full interrupt enabled - name: Unmasked - value: 0 - - description: Received-crc-error counter half-full interrupt disabled - name: Masked - value: 1 -enum/RGUFM: - bit_size: 1 - variants: - - description: Received-good-unicast counter half-full interrupt enabled - name: Unmasked - value: 0 - - description: Received-good-unicast counter half-full interrupt disabled - name: Masked - value: 1 -enum/ROR: - bit_size: 1 - variants: - - description: MMC counters do not reset on read - name: Disabled - value: 0 - - description: MMC counters reset to zero after read - name: Enabled - value: 1 -enum/TGFM: - bit_size: 1 - variants: - - description: Transmitted-good counter half-full interrupt enabled - name: Unmasked - value: 0 - - description: Transmitted-good counter half-full interrupt disabled - name: Masked - value: 1 -enum/TGFMSCM: - bit_size: 1 - variants: - - description: Transmitted-good-multiple-collision half-full interrupt enabled - name: Unmasked - value: 0 - - description: Transmitted-good-multiple-collision half-full interrupt disabled - name: Masked - value: 1 -enum/TGFSCM: - bit_size: 1 - variants: - - description: Transmitted-good-single-collision half-full interrupt enabled - name: Unmasked - value: 0 - - description: Transmitted-good-single-collision half-full interrupt disabled - name: Masked - value: 1 -fieldset/MMCCR: - description: Ethernet MMC control register - fields: - - bit_offset: 0 - bit_size: 1 - description: Counter reset - enum: CounterReset - name: CR - - bit_offset: 1 - bit_size: 1 - description: Counter stop rollover - enum: CSR - name: CSR - - bit_offset: 2 - bit_size: 1 - description: Reset on read - enum: ROR - name: ROR - - bit_offset: 3 - bit_size: 1 - description: MMC counter freeze - enum: MCF - name: MCF - - bit_offset: 4 - bit_size: 1 - description: MMC counter preset - enum: MCP - name: MCP - - bit_offset: 5 - bit_size: 1 - description: MMC counter Full-Half preset - enum: MCFHP - name: MCFHP -fieldset/MMCRFAECR: - description: Ethernet MMC received frames with alignment error counter register - fields: - - bit_offset: 0 - bit_size: 32 - description: RFAEC - name: RFAEC -fieldset/MMCRFCECR: - description: Ethernet MMC received frames with CRC error counter register - fields: - - bit_offset: 0 - bit_size: 32 - description: RFCFC - name: RFCFC -fieldset/MMCRGUFCR: - description: MMC received good unicast frames counter register - fields: - - bit_offset: 0 - bit_size: 32 - description: RGUFC - name: RGUFC -fieldset/MMCRIMR: - description: Ethernet MMC receive interrupt mask register - fields: - - bit_offset: 5 - bit_size: 1 - description: Received frame CRC error mask - enum: RFCEM - name: RFCEM - - bit_offset: 6 - bit_size: 1 - description: Received frames alignment error mask - enum: RFAEM - name: RFAEM - - bit_offset: 17 - bit_size: 1 - description: Received good Unicast frames mask - enum: RGUFM - name: RGUFM -fieldset/MMCRIR: - description: Ethernet MMC receive interrupt register - fields: - - bit_offset: 5 - bit_size: 1 - description: Received frames CRC error status - name: RFCES - - bit_offset: 6 - bit_size: 1 - description: Received frames alignment error status - name: RFAES - - bit_offset: 17 - bit_size: 1 - description: Received good Unicast frames status - name: RGUFS -fieldset/MMCTGFCR: - description: Ethernet MMC transmitted good frames counter register - fields: - - bit_offset: 0 - bit_size: 32 - description: HTL - name: TGFC -fieldset/MMCTGFMSCCR: - description: Ethernet MMC transmitted good frames after more than a single collision - fields: - - bit_offset: 0 - bit_size: 32 - description: TGFMSCC - name: TGFMSCC -fieldset/MMCTGFSCCR: - description: Ethernet MMC transmitted good frames after a single collision counter - fields: - - bit_offset: 0 - bit_size: 32 - description: Transmitted good frames single collision counter - name: TGFSCC -fieldset/MMCTIMR: - description: Ethernet MMC transmit interrupt mask register - fields: - - bit_offset: 14 - bit_size: 1 - description: Transmitted good frames single collision mask - enum: TGFSCM - name: TGFSCM - - bit_offset: 15 - bit_size: 1 - description: Transmitted good frames more than single collision mask - enum: TGFMSCM - name: TGFMSCM - - bit_offset: 16 - bit_size: 1 - description: Transmitted good frames mask - enum: TGFM - name: TGFM -fieldset/MMCTIR: - description: Ethernet MMC transmit interrupt register - fields: - - bit_offset: 14 - bit_size: 1 - description: Transmitted good frames single collision status - name: TGFSCS - - bit_offset: 15 - bit_size: 1 - description: Transmitted good frames more than single collision status - name: TGFMSCS - - bit_offset: 21 - bit_size: 1 - description: Transmitted good frames status - name: TGFS -block/ETHERNET_PTP: - description: 'Ethernet: Precision time protocol' - items: - - byte_offset: 0 - description: Ethernet PTP time stamp control register - fieldset: PTPTSCR - name: PTPTSCR - - byte_offset: 4 - description: Ethernet PTP subsecond increment register - fieldset: PTPSSIR - name: PTPSSIR - - access: Read - byte_offset: 8 - description: Ethernet PTP time stamp high register - fieldset: PTPTSHR - name: PTPTSHR - - access: Read - byte_offset: 12 - description: Ethernet PTP time stamp low register - fieldset: PTPTSLR - name: PTPTSLR - - byte_offset: 16 - description: Ethernet PTP time stamp high update register - fieldset: PTPTSHUR - name: PTPTSHUR - - byte_offset: 20 - description: Ethernet PTP time stamp low update register - fieldset: PTPTSLUR - name: PTPTSLUR - - byte_offset: 24 - description: Ethernet PTP time stamp addend register - fieldset: PTPTSAR - name: PTPTSAR - - byte_offset: 28 - description: Ethernet PTP target time high register - fieldset: PTPTTHR - name: PTPTTHR - - byte_offset: 32 - description: Ethernet PTP target time low register - fieldset: PTPTTLR - name: PTPTTLR - - access: Read - byte_offset: 40 - description: Ethernet PTP time stamp status register - fieldset: PTPTSSR - name: PTPTSSR - - access: Read - byte_offset: 44 - description: Ethernet PTP PPS control register - fieldset: PTPPPSCR - name: PTPPPSCR -fieldset/PTPPPSCR: - description: Ethernet PTP PPS control register - fields: - - bit_offset: 0 - bit_size: 1 - description: TSSO - name: TSSO - - bit_offset: 1 - bit_size: 1 - description: TSTTR - name: TSTTR -fieldset/PTPSSIR: - description: Ethernet PTP subsecond increment register - fields: - - bit_offset: 0 - bit_size: 8 - description: STSSI - name: STSSI -fieldset/PTPTSAR: - description: Ethernet PTP time stamp addend register - fields: - - bit_offset: 0 - bit_size: 32 - description: TSA - name: TSA -fieldset/PTPTSCR: - description: Ethernet PTP time stamp control register - fields: - - bit_offset: 0 - bit_size: 1 - description: TSE - name: TSE - - bit_offset: 1 - bit_size: 1 - description: TSFCU - name: TSFCU - - bit_offset: 2 - bit_size: 1 - description: TSSTI - name: TSSTI - - bit_offset: 3 - bit_size: 1 - description: TSSTU - name: TSSTU - - bit_offset: 4 - bit_size: 1 - description: TSITE - name: TSITE - - bit_offset: 5 - bit_size: 1 - description: TTSARU - name: TTSARU - - bit_offset: 8 - bit_size: 1 - description: TSSARFE - name: TSSARFE - - bit_offset: 9 - bit_size: 1 - description: TSSSR - name: TSSSR - - bit_offset: 10 - bit_size: 1 - description: TSPTPPSV2E - name: TSPTPPSV2E - - bit_offset: 11 - bit_size: 1 - description: TSSPTPOEFE - name: TSSPTPOEFE - - bit_offset: 12 - bit_size: 1 - description: TSSIPV6FE - name: TSSIPV6FE - - bit_offset: 13 - bit_size: 1 - description: TSSIPV4FE - name: TSSIPV4FE - - bit_offset: 14 - bit_size: 1 - description: TSSEME - name: TSSEME - - bit_offset: 15 - bit_size: 1 - description: TSSMRME - name: TSSMRME - - bit_offset: 16 - bit_size: 2 - description: TSCNT - name: TSCNT - - bit_offset: 18 - bit_size: 1 - description: TSPFFMAE - name: TSPFFMAE -fieldset/PTPTSHR: - description: Ethernet PTP time stamp high register - fields: - - bit_offset: 0 - bit_size: 32 - description: STS - name: STS -fieldset/PTPTSHUR: - description: Ethernet PTP time stamp high update register - fields: - - bit_offset: 0 - bit_size: 32 - description: TSUS - name: TSUS -fieldset/PTPTSLR: - description: Ethernet PTP time stamp low register - fields: - - bit_offset: 0 - bit_size: 31 - description: STSS - name: STSS - - bit_offset: 31 - bit_size: 1 - description: STPNS - name: STPNS -fieldset/PTPTSLUR: - description: Ethernet PTP time stamp low update register - fields: - - bit_offset: 0 - bit_size: 31 - description: TSUSS - name: TSUSS - - bit_offset: 31 - bit_size: 1 - description: TSUPNS - name: TSUPNS -fieldset/PTPTSSR: - description: Ethernet PTP time stamp status register - fields: - - bit_offset: 0 - bit_size: 1 - description: TSSO - name: TSSO - - bit_offset: 1 - bit_size: 1 - description: TSSO - name: TSTTR -fieldset/PTPTTHR: - description: Ethernet PTP target time high register - fields: - - bit_offset: 0 - bit_size: 32 - description: '0' - name: TTSH -fieldset/PTPTTLR: - description: Ethernet PTP target time low register - fields: - - bit_offset: 0 - bit_size: 32 - description: TTSL - name: TTSL -block/ETHERNET_DMA: - description: 'Ethernet: DMA controller operation' - items: - - byte_offset: 0 - description: Ethernet DMA bus mode register - fieldset: DMABMR - name: DMABMR - - byte_offset: 4 - description: Ethernet DMA transmit poll demand register - fieldset: DMATPDR - name: DMATPDR - - byte_offset: 8 - description: EHERNET DMA receive poll demand register - fieldset: DMARPDR - name: DMARPDR - - byte_offset: 12 - description: Ethernet DMA receive descriptor list address register - fieldset: DMARDLAR - name: DMARDLAR - - byte_offset: 16 - description: Ethernet DMA transmit descriptor list address register - fieldset: DMATDLAR - name: DMATDLAR - - byte_offset: 20 - description: Ethernet DMA status register - fieldset: DMASR - name: DMASR - - byte_offset: 24 - description: Ethernet DMA operation mode register - fieldset: DMAOMR - name: DMAOMR - - byte_offset: 28 - description: Ethernet DMA interrupt enable register - fieldset: DMAIER - name: DMAIER - - byte_offset: 32 - description: Ethernet DMA missed frame and buffer overflow counter register - fieldset: DMAMFBOCR - name: DMAMFBOCR - - byte_offset: 36 - description: Ethernet DMA receive status watchdog timer register - fieldset: DMARSWTR - name: DMARSWTR - - access: Read - byte_offset: 72 - description: Ethernet DMA current host transmit descriptor register - fieldset: DMACHTDR - name: DMACHTDR - - access: Read - byte_offset: 76 - description: Ethernet DMA current host receive descriptor register - fieldset: DMACHRDR - name: DMACHRDR - - access: Read - byte_offset: 80 - description: Ethernet DMA current host transmit buffer address register - fieldset: DMACHTBAR - name: DMACHTBAR - - access: Read - byte_offset: 84 - description: Ethernet DMA current host receive buffer address register - fieldset: DMACHRBAR - name: DMACHRBAR -enum/AAB: - bit_size: 1 - variants: - - description: Bursts are not aligned - name: Unaligned - value: 0 - - description: Align bursts to start address LS bits. First burst alignment depends - on FB bit - name: Aligned + - name: Reset + description: Reset all counters. Cleared automatically value: 1 enum/DA: bit_size: 1 variants: - - description: Round-robin with Rx:Tx priority given by PM - name: RoundRobin + - name: RoundRobin + description: "Round-robin with Rx:Tx priority given by PM" value: 0 - - description: Rx has priority over Tx - name: RxPriority + - name: RxPriority + description: Rx has priority over Tx + value: 1 +enum/DAIF: + bit_size: 1 + variants: + - name: Normal + description: Normal filtering of frames + value: 0 + - name: Invert + description: Address check block operates in inverse filtering mode for the DA address comparison + value: 1 +enum/DC: + bit_size: 1 + variants: + - name: Disabled + description: MAC defers until CRS signal goes inactive + value: 0 + - name: Enabled + description: Deferral check function enabled + value: 1 +enum/DM: + bit_size: 1 + variants: + - name: HalfDuplex + description: MAC operates in half-duplex mode + value: 0 + - name: FullDuplex + description: MAC operates in full-duplex mode value: 1 enum/DMABMR_SR: bit_size: 1 variants: - - description: Reset all MAC subsystem internal registers and logic. Cleared automatically - name: Reset + - name: Reset + description: Reset all MAC subsystem internal registers and logic. Cleared automatically value: 1 enum/DMAOMR_SR: bit_size: 1 variants: - - description: Reception is stopped after transfer of the current frame - name: Stopped + - name: Stopped + description: Reception is stopped after transfer of the current frame value: 0 - - description: Reception is placed in the Running state - name: Started + - name: Started + description: Reception is placed in the Running state value: 1 enum/DTCEFD: bit_size: 1 variants: - - description: Drop frames with errors only in the receive checksum offload engine - name: Enabled + - name: Enabled + description: Drop frames with errors only in the receive checksum offload engine value: 0 - - description: Do not drop frames that only have errors in the receive checksum - offload engine - name: Disabled + - name: Disabled + description: Do not drop frames that only have errors in the receive checksum offload engine value: 1 enum/EDFE: bit_size: 1 variants: - - description: Normal descriptor format - name: Disabled + - name: Disabled + description: Normal descriptor format value: 0 - - description: Enhanced 32-byte descriptor format, required for timestamping and - IPv4 checksum offload - name: Enabled + - name: Enabled + description: "Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload" value: 1 enum/FB: bit_size: 1 variants: - - description: AHB uses SINGLE and INCR burst transfers - name: Variable + - name: Variable + description: AHB uses SINGLE and INCR burst transfers value: 0 - - description: AHB uses only fixed burst transfers - name: Fixed + - name: Fixed + description: AHB uses only fixed burst transfers + value: 1 +enum/FCB: + bit_size: 1 + variants: + - name: DisableBackPressure + description: "In half duplex only, deasserts back pressure" + value: 0 + - name: PauseOrBackPressure + description: "In full duplex, initiate a Pause control frame. In half duplex, assert back pressure" value: 1 enum/FEF: bit_size: 1 variants: - - description: Rx FIFO drops frames with error status - name: Drop + - name: Drop + description: Rx FIFO drops frames with error status value: 0 - - description: All frames except runt error frames are forwarded to the DMA - name: Forward + - name: Forward + description: All frames except runt error frames are forwarded to the DMA + value: 1 +enum/FES: + bit_size: 1 + variants: + - name: FES10 + description: 10 Mbit/s + value: 0 + - name: FES100 + description: 100 Mbit/s value: 1 enum/FPM: bit_size: 1 variants: - - description: PBL values used as-is - name: x1 + - name: x1 + description: PBL values used as-is value: 0 - - description: PBL values multiplied by 4 - name: x4 + - name: x4 + description: PBL values multiplied by 4 value: 1 enum/FTF: bit_size: 1 variants: - - description: Transmit FIFO controller logic is reset to its default values. Cleared - automatically - name: Flush + - name: Flush + description: Transmit FIFO controller logic is reset to its default values. Cleared automatically value: 1 enum/FUGF: bit_size: 1 variants: - - description: Rx FIFO drops all frames of less than 64 bytes - name: Drop + - name: Drop + description: Rx FIFO drops all frames of less than 64 bytes value: 0 - - description: Rx FIFO forwards undersized frames - name: Forward + - name: Forward + description: Rx FIFO forwards undersized frames + value: 1 +enum/GU: + bit_size: 1 + variants: + - name: Disabled + description: Normal operation + value: 0 + - name: Enabled + description: Any unicast packet filtered by the MAC address recognition may be a wakeup frame + value: 1 +enum/HM: + bit_size: 1 + variants: + - name: Perfect + description: MAC performs a perfect destination address filtering for multicast frames + value: 0 + - name: Hash + description: MAC performs destination address filtering of received multicast frames according to the hash table + value: 1 +enum/HPF: + bit_size: 1 + variants: + - name: HashOnly + description: "If HM or HU is set, only frames that match the Hash filter are passed" + value: 0 + - name: HashOrPerfect + description: "If HM or HU is set, frames that match either the perfect filter or the hash filter are passed" + value: 1 +enum/HU: + bit_size: 1 + variants: + - name: Perfect + description: MAC performs a perfect destination address filtering for unicast frames + value: 0 + - name: Hash + description: MAC performs destination address filtering of received unicast frames according to the hash table + value: 1 +enum/IFG: + bit_size: 3 + variants: + - name: IFG96 + description: 96 bit times + value: 0 + - name: IFG88 + description: 88 bit times + value: 1 + - name: IFG80 + description: 80 bit times + value: 2 + - name: IFG72 + description: 72 bit times + value: 3 + - name: IFG64 + description: 64 bit times + value: 4 + - name: IFG56 + description: 56 bit times + value: 5 + - name: IFG48 + description: 48 bit times + value: 6 + - name: IFG40 + description: 40 bit times + value: 7 +enum/IPCO: + bit_size: 1 + variants: + - name: Disabled + description: IPv4 checksum offload disabled + value: 0 + - name: Offload + description: IPv4 checksums are checked in received frames + value: 1 +enum/JD: + bit_size: 1 + variants: + - name: Enabled + description: "Jabber enabled, transmit frames up to 2048 bytes" + value: 0 + - name: Disabled + description: "Jabber disabled, transmit frames up to 16384 bytes" + value: 1 +enum/LM: + bit_size: 1 + variants: + - name: Normal + description: Normal mode + value: 0 + - name: Loopback + description: MAC operates in loopback mode at the MII + value: 1 +enum/MACAHR_AE: + bit_size: 1 + variants: + - name: Disabled + description: Address filters ignore this address + value: 0 + - name: Enabled + description: Address filters use this address + value: 1 +enum/MACAHR_SA: + bit_size: 1 + variants: + - name: Destination + description: This address is used for comparison with DA fields of the received frame + value: 0 + - name: Source + description: This address is used for comparison with SA fields of received frames value: 1 enum/MB: bit_size: 1 variants: - - description: Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 - and below - name: Normal + - name: Normal + description: Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below value: 0 - - description: If FB is low, start all bursts greater than 16 with INCR (undefined - burst) - name: Mixed + - name: Mixed + description: "If FB is low, start all bursts greater than 16 with INCR (undefined burst)" + value: 1 +enum/MB_progress: + bit_size: 1 + variants: + - name: Busy + description: This bit is set to 1 by the application to indicate that a read or write access is in progress + value: 1 +enum/MCF: + bit_size: 1 + variants: + - name: Unfrozen + description: All MMC counters update normally + value: 0 + - name: Frozen + description: All MMC counters frozen to their current value + value: 1 +enum/MCFHP: + bit_size: 1 + variants: + - name: AlmostHalf + description: "When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0" + value: 0 + - name: AlmostFull + description: "When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0" + value: 1 +enum/MCP: + bit_size: 1 + variants: + - name: Preset + description: MMC counters will be preset to almost full or almost half. Cleared automatically + value: 1 +enum/MPE: + bit_size: 1 + variants: + - name: Disabled + description: No power management event generated due to Magic Packet reception + value: 0 + - name: Enabled + description: Enable generation of a power management event due to Magic Packet reception + value: 1 +enum/MW: + bit_size: 1 + variants: + - name: Read + description: Read operation + value: 0 + - name: Write + description: Write operation + value: 1 +enum/PAM: + bit_size: 1 + variants: + - name: Disabled + description: Filtering of multicast frames depends on HM + value: 0 + - name: Enabled + description: All received frames with a multicast destination address are passed value: 1 enum/PBL: bit_size: 6 variants: - - description: Maximum of 1 beat per DMA transaction - name: PBL1 + - name: PBL1 + description: Maximum of 1 beat per DMA transaction value: 1 - - description: Maximum of 2 beats per DMA transaction - name: PBL2 + - name: PBL2 + description: Maximum of 2 beats per DMA transaction value: 2 - - description: Maximum of 4 beats per DMA transaction - name: PBL4 + - name: PBL4 + description: Maximum of 4 beats per DMA transaction value: 4 - - description: Maximum of 8 beats per DMA transaction - name: PBL8 + - name: PBL8 + description: Maximum of 8 beats per DMA transaction value: 8 - - description: Maximum of 16 beats per DMA transaction - name: PBL16 + - name: PBL16 + description: Maximum of 16 beats per DMA transaction value: 16 - - description: Maximum of 32 beats per DMA transaction - name: PBL32 + - name: PBL32 + description: Maximum of 32 beats per DMA transaction value: 32 +enum/PCF: + bit_size: 2 + variants: + - name: PreventAll + description: MAC prevents all control frames from reaching the application + value: 0 + - name: ForwardAllExceptPause + description: MAC forwards all control frames to application except Pause + value: 1 + - name: ForwardAll + description: MAC forwards all control frames to application even if they fail the address filter + value: 2 + - name: ForwardAllFiltered + description: MAC forwards control frames that pass the address filter + value: 3 +enum/PD: + bit_size: 1 + variants: + - name: Enabled + description: All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received + value: 1 +enum/PLT: + bit_size: 2 + variants: + - name: PLT4 + description: Pause time minus 4 slot times + value: 0 + - name: PLT28 + description: Pause time minus 28 slot times + value: 1 + - name: PLT144 + description: Pause time minus 144 slot times + value: 2 + - name: PLT256 + description: Pause time minus 256 slot times + value: 3 +enum/PM: + bit_size: 1 + variants: + - name: Disabled + description: Normal address filtering + value: 0 + - name: Enabled + description: Address filters pass all incoming frames regardless of their destination or source address + value: 1 +enum/PMTIM: + bit_size: 1 + variants: + - name: Unmasked + description: PMT Status interrupt generation enabled + value: 0 + - name: Masked + description: PMT Status interrupt generation disabled + value: 1 enum/PriorityRxOverTx: bit_size: 2 variants: - - description: RxDMA priority over TxDMA is 1:1 - name: OneToOne + - name: OneToOne + description: "RxDMA priority over TxDMA is 1:1" value: 0 - - description: RxDMA priority over TxDMA is 2:1 - name: TwoToOne + - name: TwoToOne + description: "RxDMA priority over TxDMA is 2:1" value: 1 - - description: RxDMA priority over TxDMA is 3:1 - name: ThreeToOne + - name: ThreeToOne + description: "RxDMA priority over TxDMA is 3:1" value: 2 - - description: RxDMA priority over TxDMA is 4:1 - name: FourToOne + - name: FourToOne + description: "RxDMA priority over TxDMA is 4:1" value: 3 +enum/RA: + bit_size: 1 + variants: + - name: Disabled + description: MAC receiver passes on to the application only those frames that have passed the SA/DA address file + value: 0 + - name: Enabled + description: MAC receiver passes oll received frames on to the application + value: 1 +enum/RD: + bit_size: 1 + variants: + - name: Enabled + description: MAC attempts retries based on the settings of BL + value: 0 + - name: Disabled + description: MAC attempts only 1 transmission + value: 1 enum/RDP: bit_size: 6 variants: - - description: 1 beat per RxDMA transaction - name: RDP1 + - name: RDP1 + description: 1 beat per RxDMA transaction value: 1 - - description: 2 beats per RxDMA transaction - name: RDP2 + - name: RDP2 + description: 2 beats per RxDMA transaction value: 2 - - description: 4 beats per RxDMA transaction - name: RDP4 + - name: RDP4 + description: 4 beats per RxDMA transaction value: 4 - - description: 8 beats per RxDMA transaction - name: RDP8 + - name: RDP8 + description: 8 beats per RxDMA transaction value: 8 - - description: 16 beats per RxDMA transaction - name: RDP16 + - name: RDP16 + description: 16 beats per RxDMA transaction value: 16 - - description: 32 beats per RxDMA transaction - name: RDP32 + - name: RDP32 + description: 32 beats per RxDMA transaction value: 32 +enum/RE: + bit_size: 1 + variants: + - name: Disabled + description: MAC receive state machine is disabled after the completion of the reception of the current frame + value: 0 + - name: Enabled + description: MAC receive state machine is enabled + value: 1 +enum/RFAEM: + bit_size: 1 + variants: + - name: Unmasked + description: Received-alignment-error counter half-full interrupt enabled + value: 0 + - name: Masked + description: Received-alignment-error counter half-full interrupt disabled + value: 1 +enum/RFCE: + bit_size: 1 + variants: + - name: Disabled + description: Pause frames are not decoded + value: 0 + - name: Enabled + description: MAC decodes received Pause frames and disables its transmitted for a specified time + value: 1 +enum/RFCEM: + bit_size: 1 + variants: + - name: Unmasked + description: Received-crc-error counter half-full interrupt enabled + value: 0 + - name: Masked + description: Received-crc-error counter half-full interrupt disabled + value: 1 +enum/RGUFM: + bit_size: 1 + variants: + - name: Unmasked + description: Received-good-unicast counter half-full interrupt enabled + value: 0 + - name: Masked + description: Received-good-unicast counter half-full interrupt disabled + value: 1 +enum/ROD: + bit_size: 1 + variants: + - name: Enabled + description: MAC receives all packets from PHY while transmitting + value: 0 + - name: Disabled + description: MAC disables reception of frames in half-duplex mode + value: 1 +enum/ROR: + bit_size: 1 + variants: + - name: Disabled + description: MMC counters do not reset on read + value: 0 + - name: Enabled + description: MMC counters reset to zero after read + value: 1 enum/RPD: bit_size: 32 variants: - - description: Poll the receive descriptor list - name: Poll + - name: Poll + description: Poll the receive descriptor list value: 0 enum/RPS: bit_size: 3 variants: - - description: Stopped, reset or Stop Receive command issued - name: Stopped + - name: Stopped + description: "Stopped, reset or Stop Receive command issued" value: 0 - - description: Running, fetching receive transfer descriptor - name: RunningFetching + - name: RunningFetching + description: "Running, fetching receive transfer descriptor" value: 1 - - description: Running, waiting for receive packet - name: RunningWaiting + - name: RunningWaiting + description: "Running, waiting for receive packet" value: 3 - - description: Suspended, receive descriptor unavailable - name: Suspended + - name: Suspended + description: "Suspended, receive descriptor unavailable" value: 4 - - description: Running, writing data to host memory buffer - name: RunningWriting + - name: RunningWriting + description: "Running, writing data to host memory buffer" value: 7 enum/RSF: bit_size: 1 variants: - - description: Rx FIFO operates in cut-through mode, subject to RTC bits - name: CutThrough + - name: CutThrough + description: "Rx FIFO operates in cut-through mode, subject to RTC bits" value: 0 - - description: Frames are read from Rx FIFO after complete frame has been written - name: StoreForward + - name: StoreForward + description: Frames are read from Rx FIFO after complete frame has been written value: 1 enum/RTC: bit_size: 2 variants: - - description: 64 bytes - name: RTC64 + - name: RTC64 + description: 64 bytes value: 0 - - description: 32 bytes - name: RTC32 + - name: RTC32 + description: 32 bytes value: 1 - - description: 96 bytes - name: RTC96 + - name: RTC96 + description: 96 bytes value: 2 - - description: 128 bytes - name: RTC128 + - name: RTC128 + description: 128 bytes value: 3 +enum/SAF: + bit_size: 1 + variants: + - name: Disabled + description: Source address ignored + value: 0 + - name: Enabled + description: MAC drops frames that fail the source address filter + value: 1 +enum/SAIF: + bit_size: 1 + variants: + - name: Normal + description: Source address filter operates normally + value: 0 + - name: Invert + description: Source address filter operation inverted + value: 1 enum/ST: bit_size: 1 variants: - - description: Transmission is placed in the Stopped state - name: Stopped + - name: Stopped + description: Transmission is placed in the Stopped state value: 0 - - description: Transmission is placed in Running state - name: Started + - name: Started + description: Transmission is placed in Running state + value: 1 +enum/TE: + bit_size: 1 + variants: + - name: Disabled + description: MAC transmit state machine is disabled after completion of the transmission of the current frame + value: 0 + - name: Enabled + description: MAC transmit state machine is enabled + value: 1 +enum/TFCE: + bit_size: 1 + variants: + - name: Disabled + description: "In full duplex, flow control is disabled. In half duplex, back pressure is disabled" + value: 0 + - name: Enabled + description: "In full duplex, flow control is enabled. In half duplex, back pressure is enabled" + value: 1 +enum/TGFM: + bit_size: 1 + variants: + - name: Unmasked + description: Transmitted-good counter half-full interrupt enabled + value: 0 + - name: Masked + description: Transmitted-good counter half-full interrupt disabled + value: 1 +enum/TGFMSCM: + bit_size: 1 + variants: + - name: Unmasked + description: Transmitted-good-multiple-collision half-full interrupt enabled + value: 0 + - name: Masked + description: Transmitted-good-multiple-collision half-full interrupt disabled + value: 1 +enum/TGFSCM: + bit_size: 1 + variants: + - name: Unmasked + description: Transmitted-good-single-collision half-full interrupt enabled + value: 0 + - name: Masked + description: Transmitted-good-single-collision half-full interrupt disabled value: 1 enum/TPD: bit_size: 32 variants: - - description: Poll the transmit descriptor list - name: Poll + - name: Poll + description: Poll the transmit descriptor list value: 0 enum/TPS: bit_size: 3 variants: - - description: Stopped, Reset or Stop Transmit command issued - name: Stopped + - name: Stopped + description: "Stopped, Reset or Stop Transmit command issued" value: 0 - - description: Running, fetching transmit transfer descriptor - name: RunningFetching + - name: RunningFetching + description: "Running, fetching transmit transfer descriptor" value: 1 - - description: Running, waiting for status - name: RunningWaiting + - name: RunningWaiting + description: "Running, waiting for status" value: 2 - - description: Running, reading data from host memory buffer - name: RunningReading + - name: RunningReading + description: "Running, reading data from host memory buffer" value: 3 - - description: Suspended, transmit descriptor unavailable or transmit buffer underflow - name: Suspended + - name: Suspended + description: "Suspended, transmit descriptor unavailable or transmit buffer underflow" value: 6 - - description: Running, closing transmit descriptor - name: Running + - name: Running + description: "Running, closing transmit descriptor" value: 7 enum/TSF: bit_size: 1 variants: - - description: Transmission starts when the frame size in the Tx FIFO exceeds TTC - threshold - name: CutThrough + - name: CutThrough + description: Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold value: 0 - - description: Transmission starts when a full frame is in the Tx FIFO - name: StoreForward + - name: StoreForward + description: Transmission starts when a full frame is in the Tx FIFO + value: 1 +enum/TSTIM: + bit_size: 1 + variants: + - name: Unmasked + description: Time stamp interrupt generation enabled + value: 0 + - name: Masked + description: Time stamp interrupt generation disabled value: 1 enum/TTC: bit_size: 3 variants: - - description: 64 bytes - name: TTC64 + - name: TTC64 + description: 64 bytes value: 0 - - description: 128 bytes - name: TTC128 + - name: TTC128 + description: 128 bytes value: 1 - - description: 192 bytes - name: TTC192 + - name: TTC192 + description: 192 bytes value: 2 - - description: 256 bytes - name: TTC256 + - name: TTC256 + description: 256 bytes value: 3 - - description: 40 bytes - name: TTC40 + - name: TTC40 + description: 40 bytes value: 4 - - description: 32 bytes - name: TTC32 + - name: TTC32 + description: 32 bytes value: 5 - - description: 24 bytes - name: TTC24 + - name: TTC24 + description: 24 bytes value: 6 - - description: 16 bytes - name: TTC16 + - name: TTC16 + description: 16 bytes value: 7 +enum/UPFD: + bit_size: 1 + variants: + - name: Disabled + description: MAC detects only a Pause frame with the multicast address specified in the 802.3x standard + value: 0 + - name: Enabled + description: "MAC additionally detects Pause frames with the station's unicast address" + value: 1 enum/USP: bit_size: 1 variants: - - description: PBL value used for both Rx and Tx DMA - name: Combined + - name: Combined + description: PBL value used for both Rx and Tx DMA value: 0 - - description: RxDMA uses RDP value, TxDMA uses PBL value - name: Separate + - name: Separate + description: "RxDMA uses RDP value, TxDMA uses PBL value" + value: 1 +enum/VLANTC: + bit_size: 1 + variants: + - name: VLANTC16 + description: Full 16 bit VLAN identifiers are used for comparison and filtering + value: 0 + - name: VLANTC12 + description: 12 bit VLAN identifies are used for comparison and filtering + value: 1 +enum/WD: + bit_size: 1 + variants: + - name: Enabled + description: "Watchdog enabled, receive frames limited to 2048 bytes" + value: 0 + - name: Disabled + description: "Watchdog disabled, receive frames may be up to to 16384 bytes" + value: 1 +enum/WFE: + bit_size: 1 + variants: + - name: Disabled + description: No power management event generated due to wakeup frame reception + value: 0 + - name: Enabled + description: Enable generation of a power management event due to wakeup frame reception + value: 1 +enum/WFFRPR: + bit_size: 1 + variants: + - name: Reset + description: Reset wakeup frame filter register point to 0b000. Automatically cleared + value: 1 +enum/ZQPD: + bit_size: 1 + variants: + - name: Enabled + description: Normal operation with automatic zero-quanta pause control frame generation + value: 0 + - name: Disabled + description: Automatic generation of zero-quanta pause control frames is disabled value: 1 -fieldset/DMABMR: - description: Ethernet DMA bus mode register - fields: - - bit_offset: 0 - bit_size: 1 - description: Software reset - name: SR - - bit_offset: 1 - bit_size: 1 - description: DMA arbitration - enum: DA - name: DA - - bit_offset: 2 - bit_size: 5 - description: Descriptor skip length - name: DSL - - bit_offset: 7 - bit_size: 1 - description: Enhanced descriptor format enable - enum: EDFE - name: EDFE - - bit_offset: 8 - bit_size: 6 - description: Programmable burst length - enum: PBL - name: PBL - - bit_offset: 14 - bit_size: 2 - description: Rx-Tx priority ratio - enum: PriorityRxOverTx - name: PM - - bit_offset: 16 - bit_size: 1 - description: Fixed burst - enum: FB - name: FB - - bit_offset: 17 - bit_size: 6 - description: Rx DMA PBL - enum: RDP - name: RDP - - bit_offset: 23 - bit_size: 1 - description: Use separate PBL - enum: USP - name: USP - - bit_offset: 24 - bit_size: 1 - description: 4xPBL mode - enum: FPM - name: FPM - - bit_offset: 25 - bit_size: 1 - description: Address-aligned beats - enum: AAB - name: AAB - - bit_offset: 26 - bit_size: 1 - description: Mixed burst - enum: MB - name: MB -fieldset/DMACHRBAR: - description: Ethernet DMA current host receive buffer address register - fields: - - bit_offset: 0 - bit_size: 32 - description: Host receive buffer address pointer - name: HRBAP -fieldset/DMACHRDR: - description: Ethernet DMA current host receive descriptor register - fields: - - bit_offset: 0 - bit_size: 32 - description: Host receive descriptor address pointer - name: HRDAP -fieldset/DMACHTBAR: - description: Ethernet DMA current host transmit buffer address register - fields: - - bit_offset: 0 - bit_size: 32 - description: Host transmit buffer address pointer - name: HTBAP -fieldset/DMACHTDR: - description: Ethernet DMA current host transmit descriptor register - fields: - - bit_offset: 0 - bit_size: 32 - description: Host transmit descriptor address pointer - name: HTDAP -fieldset/DMAIER: - description: Ethernet DMA interrupt enable register - fields: - - bit_offset: 0 - bit_size: 1 - description: Transmit interrupt enable - name: TIE - - bit_offset: 1 - bit_size: 1 - description: Transmit process stopped interrupt enable - name: TPSIE - - bit_offset: 2 - bit_size: 1 - description: Transmit buffer unavailable interrupt enable - name: TBUIE - - bit_offset: 3 - bit_size: 1 - description: Transmit jabber timeout interrupt enable - name: TJTIE - - bit_offset: 4 - bit_size: 1 - description: Receive overflow interrupt enable - name: ROIE - - bit_offset: 5 - bit_size: 1 - description: Transmit underflow interrupt enable - name: TUIE - - bit_offset: 6 - bit_size: 1 - description: Receive interrupt enable - name: RIE - - bit_offset: 7 - bit_size: 1 - description: Receive buffer unavailable interrupt enable - name: RBUIE - - bit_offset: 8 - bit_size: 1 - description: Receive process stopped interrupt enable - name: RPSIE - - bit_offset: 9 - bit_size: 1 - description: Receive watchdog timeout interrupt enable - name: RWTIE - - bit_offset: 10 - bit_size: 1 - description: Early transmit interrupt enable - name: ETIE - - bit_offset: 13 - bit_size: 1 - description: Fatal bus error interrupt enable - name: FBEIE - - bit_offset: 14 - bit_size: 1 - description: Early receive interrupt enable - name: ERIE - - bit_offset: 15 - bit_size: 1 - description: Abnormal interrupt summary enable - name: AISE - - bit_offset: 16 - bit_size: 1 - description: Normal interrupt summary enable - name: NISE -fieldset/DMAMFBOCR: - description: Ethernet DMA missed frame and buffer overflow counter register - fields: - - bit_offset: 0 - bit_size: 16 - description: Missed frames by the controller - name: MFC - - bit_offset: 16 - bit_size: 1 - description: Overflow bit for missed frame counter - name: OMFC - - bit_offset: 17 - bit_size: 11 - description: Missed frames by the application - name: MFA - - bit_offset: 28 - bit_size: 1 - description: Overflow bit for FIFO overflow counter - name: OFOC -fieldset/DMAOMR: - description: Ethernet DMA operation mode register - fields: - - bit_offset: 1 - bit_size: 1 - description: Start/stop receive - enum: DMAOMR_SR - name: SR - - bit_offset: 2 - bit_size: 1 - description: Operate on second frame - name: OSF - - bit_offset: 3 - bit_size: 2 - description: Receive threshold control - enum: RTC - name: RTC - - bit_offset: 6 - bit_size: 1 - description: Forward undersized good frames - enum: FUGF - name: FUGF - - bit_offset: 7 - bit_size: 1 - description: Forward error frames - enum: FEF - name: FEF - - bit_offset: 13 - bit_size: 1 - description: Start/stop transmission - enum: ST - name: ST - - bit_offset: 14 - bit_size: 3 - description: Transmit threshold control - enum: TTC - name: TTC - - bit_offset: 20 - bit_size: 1 - description: Flush transmit FIFO - enum: FTF - name: FTF - - bit_offset: 21 - bit_size: 1 - description: Transmit store and forward - enum: TSF - name: TSF - - bit_offset: 24 - bit_size: 1 - description: Disable flushing of received frames - name: DFRF - - bit_offset: 25 - bit_size: 1 - description: Receive store and forward - enum: RSF - name: RSF - - bit_offset: 26 - bit_size: 1 - description: Dropping of TCP/IP checksum error frames disable - enum: DTCEFD - name: DTCEFD -fieldset/DMARDLAR: - description: Ethernet DMA receive descriptor list address register - fields: - - bit_offset: 0 - bit_size: 32 - description: Start of receive list - name: SRL -fieldset/DMARPDR: - description: EHERNET DMA receive poll demand register - fields: - - bit_offset: 0 - bit_size: 32 - description: Receive poll demand - enum: RPD - name: RPD -fieldset/DMARSWTR: - description: Ethernet DMA receive status watchdog timer register - fields: - - bit_offset: 0 - bit_size: 8 - description: Receive status watchdog timer count - name: RSWTC -fieldset/DMASR: - description: Ethernet DMA status register - fields: - - bit_offset: 0 - bit_size: 1 - description: Transmit status - name: TS - - bit_offset: 1 - bit_size: 1 - description: Transmit process stopped status - name: TPSS - - bit_offset: 2 - bit_size: 1 - description: Transmit buffer unavailable status - name: TBUS - - bit_offset: 3 - bit_size: 1 - description: Transmit jabber timeout status - name: TJTS - - bit_offset: 4 - bit_size: 1 - description: Receive overflow status - name: ROS - - bit_offset: 5 - bit_size: 1 - description: Transmit underflow status - name: TUS - - bit_offset: 6 - bit_size: 1 - description: Receive status - name: RS - - bit_offset: 7 - bit_size: 1 - description: Receive buffer unavailable status - name: RBUS - - bit_offset: 8 - bit_size: 1 - description: Receive process stopped status - name: RPSS - - bit_offset: 9 - bit_size: 1 - description: PWTS - name: PWTS - - bit_offset: 10 - bit_size: 1 - description: Early transmit status - name: ETS - - bit_offset: 13 - bit_size: 1 - description: Fatal bus error status - name: FBES - - bit_offset: 14 - bit_size: 1 - description: Early receive status - name: ERS - - bit_offset: 15 - bit_size: 1 - description: Abnormal interrupt summary - name: AIS - - bit_offset: 16 - bit_size: 1 - description: Normal interrupt summary - name: NIS - - bit_offset: 17 - bit_size: 3 - description: Receive process state - enum: RPS - name: RPS - - bit_offset: 20 - bit_size: 3 - description: Transmit process state - enum: TPS - name: TPS - - bit_offset: 23 - bit_size: 3 - description: Error bits status - name: EBS - - bit_offset: 27 - bit_size: 1 - description: MMC status - name: MMCS - - bit_offset: 28 - bit_size: 1 - description: PMT status - name: PMTS - - bit_offset: 29 - bit_size: 1 - description: Time stamp trigger status - name: TSTS -fieldset/DMATDLAR: - description: Ethernet DMA transmit descriptor list address register - fields: - - bit_offset: 0 - bit_size: 32 - description: Start of transmit list - name: STL -fieldset/DMATPDR: - description: Ethernet DMA transmit poll demand register - fields: - - bit_offset: 0 - bit_size: 32 - description: Transmit poll demand - enum: TPD - name: TPD diff --git a/data/registers/eth_v2.yaml b/data/registers/eth_v2.yaml index be35f67..017fe62 100644 --- a/data/registers/eth_v2.yaml +++ b/data/registers/eth_v2.yaml @@ -1,6 +1,6 @@ --- block/ETH: - description: "Ethernet Peripheral" + description: Ethernet Peripheral items: - name: ETHERNET_MAC description: "Ethernet: media access control (MAC)" @@ -14,6 +14,100 @@ block/ETH: description: "Ethernet: DMA mode register (DMA)" byte_offset: 4096 block: ETHERNET_DMA +block/ETHERNET_DMA: + description: "Ethernet: DMA mode register (DMA)" + items: + - name: DMAMR + description: DMA mode register + byte_offset: 0 + fieldset: DMAMR + - name: DMASBMR + description: System bus mode register + byte_offset: 4 + fieldset: DMASBMR + - name: DMAISR + description: Interrupt status register + byte_offset: 8 + access: Read + fieldset: DMAISR + - name: DMADSR + description: Debug status register + byte_offset: 12 + access: Read + fieldset: DMADSR + - name: DMACCR + description: Channel control register + byte_offset: 256 + fieldset: DMACCR + - name: DMACTxCR + description: Channel transmit control register + byte_offset: 260 + fieldset: DMACTxCR + - name: DMACRxCR + description: Channel receive control register + byte_offset: 264 + fieldset: DMACRxCR + - name: DMACTxDLAR + description: Channel Tx descriptor list address register + byte_offset: 276 + fieldset: DMACTxDLAR + - name: DMACRxDLAR + description: Channel Rx descriptor list address register + byte_offset: 284 + fieldset: DMACRxDLAR + - name: DMACTxDTPR + description: Channel Tx descriptor tail pointer register + byte_offset: 288 + fieldset: DMACTxDTPR + - name: DMACRxDTPR + description: Channel Rx descriptor tail pointer register + byte_offset: 296 + fieldset: DMACRxDTPR + - name: DMACTxRLR + description: Channel Tx descriptor ring length register + byte_offset: 300 + fieldset: DMACTxRLR + - name: DMACRxRLR + description: Channel Rx descriptor ring length register + byte_offset: 304 + fieldset: DMACRxRLR + - name: DMACIER + description: Channel interrupt enable register + byte_offset: 308 + fieldset: DMACIER + - name: DMACRxIWTR + description: Channel Rx interrupt watchdog timer register + byte_offset: 312 + fieldset: DMACRxIWTR + - name: DMACCATxDR + description: Channel current application transmit descriptor register + byte_offset: 324 + access: Read + fieldset: DMACCATxDR + - name: DMACCARxDR + description: Channel current application receive descriptor register + byte_offset: 332 + access: Read + fieldset: DMACCARxDR + - name: DMACCATxBR + description: Channel current application transmit buffer register + byte_offset: 340 + access: Read + fieldset: DMACCATxBR + - name: DMACCARxBR + description: Channel current application receive buffer register + byte_offset: 348 + access: Read + fieldset: DMACCARxBR + - name: DMACSR + description: Channel status register + byte_offset: 352 + fieldset: DMACSR + - name: DMACMFCR + description: Channel missed frame count register + byte_offset: 364 + access: Read + fieldset: DMACMFCR block/ETHERNET_MAC: description: "Ethernet: media access control (MAC)" items: @@ -402,6 +496,381 @@ block/ETHERNET_MAC: description: Log message interval register byte_offset: 3024 fieldset: MACLMIR +block/ETHERNET_MTL: + description: "Ethernet: MTL mode register (MTL)" + items: + - name: MTLOMR + description: Operating mode Register + byte_offset: 0 + fieldset: MTLOMR + - name: MTLISR + description: Interrupt status Register + byte_offset: 32 + access: Read + fieldset: MTLISR + - name: MTLTxQOMR + description: Tx queue operating mode Register + byte_offset: 256 + fieldset: MTLTxQOMR + - name: MTLTxQUR + description: Tx queue underflow register + byte_offset: 260 + access: Read + fieldset: MTLTxQUR + - name: MTLTxQDR + description: Tx queue debug Register + byte_offset: 264 + access: Read + fieldset: MTLTxQDR + - name: MTLQICSR + description: Queue interrupt control status Register + byte_offset: 300 + fieldset: MTLQICSR + - name: MTLRxQOMR + description: Rx queue operating mode register + byte_offset: 304 + fieldset: MTLRxQOMR + - name: MTLRxQMPOCR + description: Rx queue missed packet and overflow counter register + byte_offset: 308 + access: Read + fieldset: MTLRxQMPOCR + - name: MTLRxQDR + description: Rx queue debug register + byte_offset: 312 + access: Read + fieldset: MTLRxQDR +fieldset/DMACCARxBR: + description: Channel current application receive buffer register + fields: + - name: CURRBUFAPTR + description: Application Receive Buffer Address Pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACCARxDR: + description: Channel current application receive descriptor register + fields: + - name: CURRDESAPTR + description: Application Receive Descriptor Address Pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACCATxBR: + description: Channel current application transmit buffer register + fields: + - name: CURTBUFAPTR + description: Application Transmit Buffer Address Pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACCATxDR: + description: Channel current application transmit descriptor register + fields: + - name: CURTDESAPTR + description: Application Transmit Descriptor Address Pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACCR: + description: Channel control register + fields: + - name: MSS + description: Maximum Segment Size + bit_offset: 0 + bit_size: 14 + - name: PBLX8 + description: 8xPBL mode + bit_offset: 16 + bit_size: 1 + - name: DSL + description: Descriptor Skip Length + bit_offset: 18 + bit_size: 3 +fieldset/DMACIER: + description: Channel interrupt enable register + fields: + - name: TIE + description: Transmit Interrupt Enable + bit_offset: 0 + bit_size: 1 + - name: TXSE + description: Transmit Stopped Enable + bit_offset: 1 + bit_size: 1 + - name: TBUE + description: Transmit Buffer Unavailable Enable + bit_offset: 2 + bit_size: 1 + - name: RIE + description: Receive Interrupt Enable + bit_offset: 6 + bit_size: 1 + - name: RBUE + description: Receive Buffer Unavailable Enable + bit_offset: 7 + bit_size: 1 + - name: RSE + description: Receive Stopped Enable + bit_offset: 8 + bit_size: 1 + - name: RWTE + description: Receive Watchdog Timeout Enable + bit_offset: 9 + bit_size: 1 + - name: ETIE + description: Early Transmit Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: ERIE + description: Early Receive Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: FBEE + description: Fatal Bus Error Enable + bit_offset: 12 + bit_size: 1 + - name: CDEE + description: Context Descriptor Error Enable + bit_offset: 13 + bit_size: 1 + - name: AIE + description: Abnormal Interrupt Summary Enable + bit_offset: 14 + bit_size: 1 + - name: NIE + description: Normal Interrupt Summary Enable + bit_offset: 15 + bit_size: 1 +fieldset/DMACMFCR: + description: Channel missed frame count register + fields: + - name: MFC + description: Dropped Packet Counters + bit_offset: 0 + bit_size: 11 + - name: MFCO + description: Overflow status of the MFC Counter + bit_offset: 15 + bit_size: 1 +fieldset/DMACRxCR: + description: Channel receive control register + fields: + - name: SR + description: Start or Stop Receive Command + bit_offset: 0 + bit_size: 1 + - name: RBSZ + description: Receive Buffer size + bit_offset: 1 + bit_size: 14 + - name: RXPBL + description: RXPBL + bit_offset: 16 + bit_size: 6 + - name: RPF + description: DMA Rx Channel Packet Flush + bit_offset: 31 + bit_size: 1 +fieldset/DMACRxDLAR: + description: Channel Rx descriptor list address register + fields: + - name: RDESLA + description: Start of Receive List + bit_offset: 0 + bit_size: 32 +fieldset/DMACRxDTPR: + description: Channel Rx descriptor tail pointer register + fields: + - name: RDT + description: Receive Descriptor Tail Pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACRxIWTR: + description: Channel Rx interrupt watchdog timer register + fields: + - name: RWT + description: Receive Interrupt Watchdog Timer Count + bit_offset: 0 + bit_size: 8 +fieldset/DMACRxRLR: + description: Channel Rx descriptor ring length register + fields: + - name: RDRL + description: Receive Descriptor Ring Length + bit_offset: 0 + bit_size: 10 +fieldset/DMACSR: + description: Channel status register + fields: + - name: TI + description: Transmit Interrupt + bit_offset: 0 + bit_size: 1 + - name: TPS + description: Transmit Process Stopped + bit_offset: 1 + bit_size: 1 + - name: TBU + description: Transmit Buffer Unavailable + bit_offset: 2 + bit_size: 1 + - name: RI + description: Receive Interrupt + bit_offset: 6 + bit_size: 1 + - name: RBU + description: Receive Buffer Unavailable + bit_offset: 7 + bit_size: 1 + - name: RPS + description: Receive Process Stopped + bit_offset: 8 + bit_size: 1 + - name: RWT + description: Receive Watchdog Timeout + bit_offset: 9 + bit_size: 1 + - name: ET + description: Early Transmit Interrupt + bit_offset: 10 + bit_size: 1 + - name: ER + description: Early Receive Interrupt + bit_offset: 11 + bit_size: 1 + - name: FBE + description: Fatal Bus Error + bit_offset: 12 + bit_size: 1 + - name: CDE + description: Context Descriptor Error + bit_offset: 13 + bit_size: 1 + - name: AIS + description: Abnormal Interrupt Summary + bit_offset: 14 + bit_size: 1 + - name: NIS + description: Normal Interrupt Summary + bit_offset: 15 + bit_size: 1 + - name: TEB + description: Tx DMA Error Bits + bit_offset: 16 + bit_size: 3 + - name: REB + description: Rx DMA Error Bits + bit_offset: 19 + bit_size: 3 +fieldset/DMACTxCR: + description: Channel transmit control register + fields: + - name: ST + description: Start or Stop Transmission Command + bit_offset: 0 + bit_size: 1 + - name: OSF + description: Operate on Second Packet + bit_offset: 4 + bit_size: 1 + - name: TSE + description: TCP Segmentation Enabled + bit_offset: 12 + bit_size: 1 + - name: TXPBL + description: Transmit Programmable Burst Length + bit_offset: 16 + bit_size: 6 +fieldset/DMACTxDLAR: + description: Channel Tx descriptor list address register + fields: + - name: TDESLA + description: Start of Transmit List + bit_offset: 0 + bit_size: 32 +fieldset/DMACTxDTPR: + description: Channel Tx descriptor tail pointer register + fields: + - name: TDT + description: Transmit Descriptor Tail Pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACTxRLR: + description: Channel Tx descriptor ring length register + fields: + - name: TDRL + description: Transmit Descriptor Ring Length + bit_offset: 0 + bit_size: 10 +fieldset/DMADSR: + description: Debug status register + fields: + - name: AXWHSTS + description: AHB Master Write Channel + bit_offset: 0 + bit_size: 1 + - name: RPS0 + description: DMA Channel Receive Process State + bit_offset: 8 + bit_size: 4 + - name: TPS0 + description: DMA Channel Transmit Process State + bit_offset: 12 + bit_size: 4 +fieldset/DMAISR: + description: Interrupt status register + fields: + - name: DC0IS + description: DMA Channel Interrupt Status + bit_offset: 0 + bit_size: 1 + - name: MTLIS + description: MTL Interrupt Status + bit_offset: 16 + bit_size: 1 + - name: MACIS + description: MAC Interrupt Status + bit_offset: 17 + bit_size: 1 +fieldset/DMAMR: + description: DMA mode register + fields: + - name: SWR + description: Software Reset + bit_offset: 0 + bit_size: 1 + - name: DA + description: DMA Tx or Rx Arbitration Scheme + bit_offset: 1 + bit_size: 1 + - name: TXPR + description: Transmit priority + bit_offset: 11 + bit_size: 1 + - name: PR + description: Priority ratio + bit_offset: 12 + bit_size: 3 + - name: INTM + description: Interrupt Mode + bit_offset: 16 + bit_size: 2 +fieldset/DMASBMR: + description: System bus mode register + fields: + - name: FB + description: Fixed Burst Length + bit_offset: 0 + bit_size: 1 + - name: AAL + description: Address-Aligned Beats + bit_offset: 12 + bit_size: 1 + - name: MB + description: Mixed Burst + bit_offset: 14 + bit_size: 1 + - name: RB + description: Rebuild INCRx Burst + bit_offset: 15 + bit_size: 1 fieldset/MAC1USTCR: description: 1-microsecond-tick counter register fields: @@ -1890,120 +2359,6 @@ fieldset/MMC_TX_INTERRUPT_MASK: description: MMC Transmit LPI transition counter interrupt Mask bit_offset: 27 bit_size: 1 -fieldset/RX_ALIGNMENT_ERROR_PACKETS: - description: Rx alignment error packets register - fields: - - name: RXALGNERR - description: Rx Alignment Error Packets - bit_offset: 0 - bit_size: 32 -fieldset/RX_CRC_ERROR_PACKETS: - description: Rx CRC error packets register - fields: - - name: RXCRCERR - description: Rx CRC Error Packets - bit_offset: 0 - bit_size: 32 -fieldset/RX_LPI_TRAN_CNTR: - description: Rx LPI transition counter register - fields: - - name: RXLPITRC - description: Rx LPI Transition counter - bit_offset: 0 - bit_size: 32 -fieldset/RX_LPI_USEC_CNTR: - description: Rx LPI microsecond counter register - fields: - - name: RXLPIUSC - description: Rx LPI Microseconds Counter - bit_offset: 0 - bit_size: 32 -fieldset/RX_UNICAST_PACKETS_GOOD: - description: Rx unicast packets good register - fields: - - name: RXUCASTG - description: Rx Unicast Packets Good - bit_offset: 0 - bit_size: 32 -fieldset/TX_LPI_TRAN_CNTR: - description: Tx LPI transition counter register - fields: - - name: TXLPITRC - description: Tx LPI Transition counter - bit_offset: 0 - bit_size: 32 -fieldset/TX_LPI_USEC_CNTR: - description: Tx LPI microsecond timer register - fields: - - name: TXLPIUSC - description: Tx LPI Microseconds Counter - bit_offset: 0 - bit_size: 32 -fieldset/TX_MULTIPLE_COLLISION_GOOD_PACKETS: - description: Tx multiple collision good packets register - fields: - - name: TXMULTCOLG - description: Tx Multiple Collision Good Packets - bit_offset: 0 - bit_size: 32 -fieldset/TX_PACKET_COUNT_GOOD: - description: Tx packet count good register - fields: - - name: TXPKTG - description: Tx Packet Count Good - bit_offset: 0 - bit_size: 32 -fieldset/TX_SINGLE_COLLISION_GOOD_PACKETS: - description: Tx single collision good packets register - fields: - - name: TXSNGLCOLG - description: Tx Single Collision Good Packets - bit_offset: 0 - bit_size: 32 -block/ETHERNET_MTL: - description: "Ethernet: MTL mode register (MTL)" - items: - - name: MTLOMR - description: Operating mode Register - byte_offset: 0 - fieldset: MTLOMR - - name: MTLISR - description: Interrupt status Register - byte_offset: 32 - access: Read - fieldset: MTLISR - - name: MTLTxQOMR - description: Tx queue operating mode Register - byte_offset: 256 - fieldset: MTLTxQOMR - - name: MTLTxQUR - description: Tx queue underflow register - byte_offset: 260 - access: Read - fieldset: MTLTxQUR - - name: MTLTxQDR - description: Tx queue debug Register - byte_offset: 264 - access: Read - fieldset: MTLTxQDR - - name: MTLQICSR - description: Queue interrupt control status Register - byte_offset: 300 - fieldset: MTLQICSR - - name: MTLRxQOMR - description: Rx queue operating mode register - byte_offset: 304 - fieldset: MTLRxQOMR - - name: MTLRxQMPOCR - description: Rx queue missed packet and overflow counter register - byte_offset: 308 - access: Read - fieldset: MTLRxQMPOCR - - name: MTLRxQDR - description: Rx queue debug register - byte_offset: 312 - access: Read - fieldset: MTLRxQDR fieldset/MTLISR: description: Interrupt status Register fields: @@ -2187,428 +2542,73 @@ fieldset/MTLTxQUR: description: Overflow Bit for Underflow Packet Counter bit_offset: 11 bit_size: 1 -block/ETHERNET_DMA: - description: "Ethernet: DMA mode register (DMA)" - items: - - name: DMAMR - description: DMA mode register - byte_offset: 0 - fieldset: DMAMR - - name: DMASBMR - description: System bus mode register - byte_offset: 4 - fieldset: DMASBMR - - name: DMAISR - description: Interrupt status register - byte_offset: 8 - access: Read - fieldset: DMAISR - - name: DMADSR - description: Debug status register - byte_offset: 12 - access: Read - fieldset: DMADSR - - name: DMACCR - description: Channel control register - byte_offset: 256 - fieldset: DMACCR - - name: DMACTxCR - description: Channel transmit control register - byte_offset: 260 - fieldset: DMACTxCR - - name: DMACRxCR - description: Channel receive control register - byte_offset: 264 - fieldset: DMACRxCR - - name: DMACTxDLAR - description: Channel Tx descriptor list address register - byte_offset: 276 - fieldset: DMACTxDLAR - - name: DMACRxDLAR - description: Channel Rx descriptor list address register - byte_offset: 284 - fieldset: DMACRxDLAR - - name: DMACTxDTPR - description: Channel Tx descriptor tail pointer register - byte_offset: 288 - fieldset: DMACTxDTPR - - name: DMACRxDTPR - description: Channel Rx descriptor tail pointer register - byte_offset: 296 - fieldset: DMACRxDTPR - - name: DMACTxRLR - description: Channel Tx descriptor ring length register - byte_offset: 300 - fieldset: DMACTxRLR - - name: DMACRxRLR - description: Channel Rx descriptor ring length register - byte_offset: 304 - fieldset: DMACRxRLR - - name: DMACIER - description: Channel interrupt enable register - byte_offset: 308 - fieldset: DMACIER - - name: DMACRxIWTR - description: Channel Rx interrupt watchdog timer register - byte_offset: 312 - fieldset: DMACRxIWTR - - name: DMACCATxDR - description: Channel current application transmit descriptor register - byte_offset: 324 - access: Read - fieldset: DMACCATxDR - - name: DMACCARxDR - description: Channel current application receive descriptor register - byte_offset: 332 - access: Read - fieldset: DMACCARxDR - - name: DMACCATxBR - description: Channel current application transmit buffer register - byte_offset: 340 - access: Read - fieldset: DMACCATxBR - - name: DMACCARxBR - description: Channel current application receive buffer register - byte_offset: 348 - access: Read - fieldset: DMACCARxBR - - name: DMACSR - description: Channel status register - byte_offset: 352 - fieldset: DMACSR - - name: DMACMFCR - description: Channel missed frame count register - byte_offset: 364 - access: Read - fieldset: DMACMFCR -fieldset/DMACCARxBR: - description: Channel current application receive buffer register +fieldset/RX_ALIGNMENT_ERROR_PACKETS: + description: Rx alignment error packets register fields: - - name: CURRBUFAPTR - description: Application Receive Buffer Address Pointer + - name: RXALGNERR + description: Rx Alignment Error Packets bit_offset: 0 bit_size: 32 -fieldset/DMACCARxDR: - description: Channel current application receive descriptor register +fieldset/RX_CRC_ERROR_PACKETS: + description: Rx CRC error packets register fields: - - name: CURRDESAPTR - description: Application Receive Descriptor Address Pointer + - name: RXCRCERR + description: Rx CRC Error Packets bit_offset: 0 bit_size: 32 -fieldset/DMACCATxBR: - description: Channel current application transmit buffer register +fieldset/RX_LPI_TRAN_CNTR: + description: Rx LPI transition counter register fields: - - name: CURTBUFAPTR - description: Application Transmit Buffer Address Pointer + - name: RXLPITRC + description: Rx LPI Transition counter bit_offset: 0 bit_size: 32 -fieldset/DMACCATxDR: - description: Channel current application transmit descriptor register +fieldset/RX_LPI_USEC_CNTR: + description: Rx LPI microsecond counter register fields: - - name: CURTDESAPTR - description: Application Transmit Descriptor Address Pointer + - name: RXLPIUSC + description: Rx LPI Microseconds Counter bit_offset: 0 bit_size: 32 -fieldset/DMACCR: - description: Channel control register +fieldset/RX_UNICAST_PACKETS_GOOD: + description: Rx unicast packets good register fields: - - name: MSS - description: Maximum Segment Size - bit_offset: 0 - bit_size: 14 - - name: PBLX8 - description: 8xPBL mode - bit_offset: 16 - bit_size: 1 - - name: DSL - description: Descriptor Skip Length - bit_offset: 18 - bit_size: 3 -fieldset/DMACIER: - description: Channel interrupt enable register - fields: - - name: TIE - description: Transmit Interrupt Enable - bit_offset: 0 - bit_size: 1 - - name: TXSE - description: Transmit Stopped Enable - bit_offset: 1 - bit_size: 1 - - name: TBUE - description: Transmit Buffer Unavailable Enable - bit_offset: 2 - bit_size: 1 - - name: RIE - description: Receive Interrupt Enable - bit_offset: 6 - bit_size: 1 - - name: RBUE - description: Receive Buffer Unavailable Enable - bit_offset: 7 - bit_size: 1 - - name: RSE - description: Receive Stopped Enable - bit_offset: 8 - bit_size: 1 - - name: RWTE - description: Receive Watchdog Timeout Enable - bit_offset: 9 - bit_size: 1 - - name: ETIE - description: Early Transmit Interrupt Enable - bit_offset: 10 - bit_size: 1 - - name: ERIE - description: Early Receive Interrupt Enable - bit_offset: 11 - bit_size: 1 - - name: FBEE - description: Fatal Bus Error Enable - bit_offset: 12 - bit_size: 1 - - name: CDEE - description: Context Descriptor Error Enable - bit_offset: 13 - bit_size: 1 - - name: AIE - description: Abnormal Interrupt Summary Enable - bit_offset: 14 - bit_size: 1 - - name: NIE - description: Normal Interrupt Summary Enable - bit_offset: 15 - bit_size: 1 -fieldset/DMACMFCR: - description: Channel missed frame count register - fields: - - name: MFC - description: Dropped Packet Counters - bit_offset: 0 - bit_size: 11 - - name: MFCO - description: Overflow status of the MFC Counter - bit_offset: 15 - bit_size: 1 -fieldset/DMACRxCR: - description: Channel receive control register - fields: - - name: SR - description: Start or Stop Receive Command - bit_offset: 0 - bit_size: 1 - - name: RBSZ - description: Receive Buffer size - bit_offset: 1 - bit_size: 14 - - name: RXPBL - description: RXPBL - bit_offset: 16 - bit_size: 6 - - name: RPF - description: DMA Rx Channel Packet Flush - bit_offset: 31 - bit_size: 1 -fieldset/DMACRxDLAR: - description: Channel Rx descriptor list address register - fields: - - name: RDESLA - description: Start of Receive List + - name: RXUCASTG + description: Rx Unicast Packets Good bit_offset: 0 bit_size: 32 -fieldset/DMACRxDTPR: - description: Channel Rx descriptor tail pointer register +fieldset/TX_LPI_TRAN_CNTR: + description: Tx LPI transition counter register fields: - - name: RDT - description: Receive Descriptor Tail Pointer + - name: TXLPITRC + description: Tx LPI Transition counter bit_offset: 0 bit_size: 32 -fieldset/DMACRxIWTR: - description: Channel Rx interrupt watchdog timer register +fieldset/TX_LPI_USEC_CNTR: + description: Tx LPI microsecond timer register fields: - - name: RWT - description: Receive Interrupt Watchdog Timer Count - bit_offset: 0 - bit_size: 8 -fieldset/DMACRxRLR: - description: Channel Rx descriptor ring length register - fields: - - name: RDRL - description: Receive Descriptor Ring Length - bit_offset: 0 - bit_size: 10 -fieldset/DMACSR: - description: Channel status register - fields: - - name: TI - description: Transmit Interrupt - bit_offset: 0 - bit_size: 1 - - name: TPS - description: Transmit Process Stopped - bit_offset: 1 - bit_size: 1 - - name: TBU - description: Transmit Buffer Unavailable - bit_offset: 2 - bit_size: 1 - - name: RI - description: Receive Interrupt - bit_offset: 6 - bit_size: 1 - - name: RBU - description: Receive Buffer Unavailable - bit_offset: 7 - bit_size: 1 - - name: RPS - description: Receive Process Stopped - bit_offset: 8 - bit_size: 1 - - name: RWT - description: Receive Watchdog Timeout - bit_offset: 9 - bit_size: 1 - - name: ET - description: Early Transmit Interrupt - bit_offset: 10 - bit_size: 1 - - name: ER - description: Early Receive Interrupt - bit_offset: 11 - bit_size: 1 - - name: FBE - description: Fatal Bus Error - bit_offset: 12 - bit_size: 1 - - name: CDE - description: Context Descriptor Error - bit_offset: 13 - bit_size: 1 - - name: AIS - description: Abnormal Interrupt Summary - bit_offset: 14 - bit_size: 1 - - name: NIS - description: Normal Interrupt Summary - bit_offset: 15 - bit_size: 1 - - name: TEB - description: Tx DMA Error Bits - bit_offset: 16 - bit_size: 3 - - name: REB - description: Rx DMA Error Bits - bit_offset: 19 - bit_size: 3 -fieldset/DMACTxCR: - description: Channel transmit control register - fields: - - name: ST - description: Start or Stop Transmission Command - bit_offset: 0 - bit_size: 1 - - name: OSF - description: Operate on Second Packet - bit_offset: 4 - bit_size: 1 - - name: TSE - description: TCP Segmentation Enabled - bit_offset: 12 - bit_size: 1 - - name: TXPBL - description: Transmit Programmable Burst Length - bit_offset: 16 - bit_size: 6 -fieldset/DMACTxDLAR: - description: Channel Tx descriptor list address register - fields: - - name: TDESLA - description: Start of Transmit List + - name: TXLPIUSC + description: Tx LPI Microseconds Counter bit_offset: 0 bit_size: 32 -fieldset/DMACTxDTPR: - description: Channel Tx descriptor tail pointer register +fieldset/TX_MULTIPLE_COLLISION_GOOD_PACKETS: + description: Tx multiple collision good packets register fields: - - name: TDT - description: Transmit Descriptor Tail Pointer + - name: TXMULTCOLG + description: Tx Multiple Collision Good Packets bit_offset: 0 bit_size: 32 -fieldset/DMACTxRLR: - description: Channel Tx descriptor ring length register +fieldset/TX_PACKET_COUNT_GOOD: + description: Tx packet count good register fields: - - name: TDRL - description: Transmit Descriptor Ring Length + - name: TXPKTG + description: Tx Packet Count Good bit_offset: 0 - bit_size: 10 -fieldset/DMADSR: - description: Debug status register + bit_size: 32 +fieldset/TX_SINGLE_COLLISION_GOOD_PACKETS: + description: Tx single collision good packets register fields: - - name: AXWHSTS - description: AHB Master Write Channel + - name: TXSNGLCOLG + description: Tx Single Collision Good Packets bit_offset: 0 - bit_size: 1 - - name: RPS0 - description: DMA Channel Receive Process State - bit_offset: 8 - bit_size: 4 - - name: TPS0 - description: DMA Channel Transmit Process State - bit_offset: 12 - bit_size: 4 -fieldset/DMAISR: - description: Interrupt status register - fields: - - name: DC0IS - description: DMA Channel Interrupt Status - bit_offset: 0 - bit_size: 1 - - name: MTLIS - description: MTL Interrupt Status - bit_offset: 16 - bit_size: 1 - - name: MACIS - description: MAC Interrupt Status - bit_offset: 17 - bit_size: 1 -fieldset/DMAMR: - description: DMA mode register - fields: - - name: SWR - description: Software Reset - bit_offset: 0 - bit_size: 1 - - name: DA - description: DMA Tx or Rx Arbitration Scheme - bit_offset: 1 - bit_size: 1 - - name: TXPR - description: Transmit priority - bit_offset: 11 - bit_size: 1 - - name: PR - description: Priority ratio - bit_offset: 12 - bit_size: 3 - - name: INTM - description: Interrupt Mode - bit_offset: 16 - bit_size: 2 -fieldset/DMASBMR: - description: System bus mode register - fields: - - name: FB - description: Fixed Burst Length - bit_offset: 0 - bit_size: 1 - - name: AAL - description: Address-Aligned Beats - bit_offset: 12 - bit_size: 1 - - name: MB - description: Mixed Burst - bit_offset: 14 - bit_size: 1 - - name: RB - description: Rebuild INCRx Burst - bit_offset: 15 - bit_size: 1 + bit_size: 32 diff --git a/data/registers/exti_g0.yaml b/data/registers/exti_g0.yaml index de76df0..22d9c2a 100644 --- a/data/registers/exti_g0.yaml +++ b/data/registers/exti_g0.yaml @@ -48,7 +48,7 @@ block/EXTI: description: Interrupt mask register array: len: 2 - stride: 16 + stride: 16 byte_offset: 128 fieldset: LINES - name: EMR @@ -69,7 +69,7 @@ fieldset/EXTICR: len: 4 stride: 8 fieldset/LINES: - description: EXTI lines register, 1 bit per line + description: "EXTI lines register, 1 bit per line" fields: - name: LINE description: EXTI line diff --git a/data/registers/exti_h7.yaml b/data/registers/exti_h7.yaml index 98caf07..d6276dd 100644 --- a/data/registers/exti_h7.yaml +++ b/data/registers/exti_h7.yaml @@ -45,7 +45,7 @@ block/EXTI: byte_offset: 136 fieldset: LINES fieldset/LINES: - description: EXTI lines register, 1 bit per line + description: "EXTI lines register, 1 bit per line" fields: - name: LINE description: EXTI line diff --git a/data/registers/exti_l5.yaml b/data/registers/exti_l5.yaml index c56c9ae..f8a7a14 100644 --- a/data/registers/exti_l5.yaml +++ b/data/registers/exti_l5.yaml @@ -87,7 +87,7 @@ fieldset/EXTICR: len: 4 stride: 8 fieldset/LINES: - description: EXTI lines register, 1 bit per line + description: "EXTI lines register, 1 bit per line" fields: - name: LINE description: EXTI line diff --git a/data/registers/exti_u5.yaml b/data/registers/exti_u5.yaml index c56c9ae..f8a7a14 100644 --- a/data/registers/exti_u5.yaml +++ b/data/registers/exti_u5.yaml @@ -87,7 +87,7 @@ fieldset/EXTICR: len: 4 stride: 8 fieldset/LINES: - description: EXTI lines register, 1 bit per line + description: "EXTI lines register, 1 bit per line" fields: - name: LINE description: EXTI line diff --git a/data/registers/exti_v1.yaml b/data/registers/exti_v1.yaml index 5657456..ec0f62e 100644 --- a/data/registers/exti_v1.yaml +++ b/data/registers/exti_v1.yaml @@ -45,7 +45,7 @@ block/EXTI: byte_offset: 20 fieldset: LINES fieldset/LINES: - description: EXTI lines register, 1 bit per line + description: "EXTI lines register, 1 bit per line" fields: - name: LINE description: EXTI line diff --git a/data/registers/exti_w.yaml b/data/registers/exti_w.yaml index 5cacddc..e9f9e6b 100644 --- a/data/registers/exti_w.yaml +++ b/data/registers/exti_w.yaml @@ -1,4 +1,21 @@ --- +block/CPU: + description: CPU-specific registers + items: + - name: IMR + description: CPU x interrupt mask register + array: + len: 2 + stride: 16 + byte_offset: 0 + fieldset: LINES + - name: EMR + description: CPU x event mask register + array: + len: 2 + stride: 16 + byte_offset: 4 + fieldset: LINES block/EXTI: description: External interrupt/event controller items: @@ -32,30 +49,13 @@ block/EXTI: fieldset: LINES - name: CPU description: CPU specific registers - byte_offset: 128 - block: CPU array: len: 2 stride: 64 -block/CPU: - description: CPU-specific registers - items: - - name: IMR - description: CPU x interrupt mask register - byte_offset: 0 - fieldset: LINES - array: - len: 2 - stride: 16 - - name: EMR - description: CPU x event mask register - array: - len: 2 - stride: 16 - byte_offset: 4 - fieldset: LINES + byte_offset: 128 + block: CPU fieldset/LINES: - description: EXTI lines register, 1 bit per line + description: "EXTI lines register, 1 bit per line" fields: - name: LINE description: EXTI line diff --git a/data/registers/exti_wle.yaml b/data/registers/exti_wle.yaml index 92d7d80..3bdaff5 100644 --- a/data/registers/exti_wle.yaml +++ b/data/registers/exti_wle.yaml @@ -45,7 +45,7 @@ block/EXTI: byte_offset: 132 fieldset: LINES fieldset/LINES: - description: EXTI lines register, 1 bit per line + description: "EXTI lines register, 1 bit per line" fields: - name: LINE description: EXTI line diff --git a/data/registers/flash_f1.yaml b/data/registers/flash_f1.yaml index 83b7b51..4841a1c 100644 --- a/data/registers/flash_f1.yaml +++ b/data/registers/flash_f1.yaml @@ -1,193 +1,194 @@ +--- block/FLASH: description: FLASH items: - - byte_offset: 0 - description: Flash access control register - fieldset: ACR - name: ACR - - access: Write - byte_offset: 4 - description: Flash key register - fieldset: KEYR - name: KEYR - - access: Write - byte_offset: 8 - description: Flash option key register - fieldset: OPTKEYR - name: OPTKEYR - - byte_offset: 12 - description: Status register - fieldset: SR - name: SR - - byte_offset: 16 - description: Control register - fieldset: CR - name: CR - - access: Write - byte_offset: 20 - description: Flash address register - fieldset: AR - name: AR - - access: Read - byte_offset: 28 - description: Option byte register - fieldset: OBR - name: OBR - - access: Read - byte_offset: 32 - description: Write protection register - fieldset: WRPR - name: WRPR -enum/LATENCY: - bit_size: 3 - variants: - - description: "Zero wait state, if 0 < SYSCLK\u2264 24 MHz" - name: WS0 - value: 0 - - description: "One wait state, if 24 MHz < SYSCLK \u2264 48 MHz" - name: WS1 - value: 1 - - description: "Two wait states, if 48 MHz < SYSCLK \u2264 72 MHz" - name: WS2 - value: 2 + - name: ACR + description: Flash access control register + byte_offset: 0 + fieldset: ACR + - name: KEYR + description: Flash key register + byte_offset: 4 + access: Write + fieldset: KEYR + - name: OPTKEYR + description: Flash option key register + byte_offset: 8 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 12 + fieldset: SR + - name: CR + description: Control register + byte_offset: 16 + fieldset: CR + - name: AR + description: Flash address register + byte_offset: 20 + access: Write + fieldset: AR + - name: OBR + description: Option byte register + byte_offset: 28 + access: Read + fieldset: OBR + - name: WRPR + description: Write protection register + byte_offset: 32 + access: Read + fieldset: WRPR fieldset/ACR: description: Flash access control register fields: - - bit_offset: 0 - bit_size: 3 - description: Latency - enum: LATENCY - name: LATENCY - - bit_offset: 3 - bit_size: 1 - description: Flash half cycle access enable - name: HLFCYA - - bit_offset: 4 - bit_size: 1 - description: Prefetch buffer enable - name: PRFTBE - - bit_offset: 5 - bit_size: 1 - description: Prefetch buffer status - name: PRFTBS + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 3 + enum: LATENCY + - name: HLFCYA + description: Flash half cycle access enable + bit_offset: 3 + bit_size: 1 + - name: PRFTBE + description: Prefetch buffer enable + bit_offset: 4 + bit_size: 1 + - name: PRFTBS + description: Prefetch buffer status + bit_offset: 5 + bit_size: 1 fieldset/AR: description: Flash address register fields: - - bit_offset: 0 - bit_size: 32 - description: Flash Address - name: FAR + - name: FAR + description: Flash Address + bit_offset: 0 + bit_size: 32 fieldset/CR: description: Control register fields: - - bit_offset: 0 - bit_size: 1 - description: Programming - name: PG - - bit_offset: 1 - bit_size: 1 - description: Page Erase - name: PER - - bit_offset: 2 - bit_size: 1 - description: Mass Erase - name: MER - - bit_offset: 4 - bit_size: 1 - description: Option byte programming - name: OPTPG - - bit_offset: 5 - bit_size: 1 - description: Option byte erase - name: OPTER - - bit_offset: 6 - bit_size: 1 - description: Start - name: STRT - - bit_offset: 7 - bit_size: 1 - description: Lock - name: LOCK - - bit_offset: 9 - bit_size: 1 - description: Option bytes write enable - name: OPTWRE - - bit_offset: 10 - bit_size: 1 - description: Error interrupt enable - name: ERRIE - - bit_offset: 12 - bit_size: 1 - description: End of operation interrupt enable - name: EOPIE + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Page Erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: Mass Erase + bit_offset: 2 + bit_size: 1 + - name: OPTPG + description: Option byte programming + bit_offset: 4 + bit_size: 1 + - name: OPTER + description: Option byte erase + bit_offset: 5 + bit_size: 1 + - name: STRT + description: Start + bit_offset: 6 + bit_size: 1 + - name: LOCK + description: Lock + bit_offset: 7 + bit_size: 1 + - name: OPTWRE + description: Option bytes write enable + bit_offset: 9 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 10 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 12 + bit_size: 1 fieldset/KEYR: description: Flash key register fields: - - bit_offset: 0 - bit_size: 32 - description: FPEC key - name: KEY + - name: KEY + description: FPEC key + bit_offset: 0 + bit_size: 32 fieldset/OBR: description: Option byte register fields: - - bit_offset: 0 - bit_size: 1 - description: Option byte error - name: OPTERR - - bit_offset: 1 - bit_size: 1 - description: Read protection - name: RDPRT - - bit_offset: 2 - bit_size: 1 - description: WDG_SW - name: WDG_SW - - bit_offset: 3 - bit_size: 1 - description: nRST_STOP - name: nRST_STOP - - bit_offset: 4 - bit_size: 1 - description: nRST_STDBY - name: nRST_STDBY - - bit_offset: 10 - bit_size: 8 - description: Data0 - name: Data0 - - bit_offset: 18 - bit_size: 8 - description: Data1 - name: Data1 + - name: OPTERR + description: Option byte error + bit_offset: 0 + bit_size: 1 + - name: RDPRT + description: Read protection + bit_offset: 1 + bit_size: 1 + - name: WDG_SW + description: WDG_SW + bit_offset: 2 + bit_size: 1 + - name: nRST_STOP + description: nRST_STOP + bit_offset: 3 + bit_size: 1 + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 4 + bit_size: 1 + - name: Data0 + description: Data0 + bit_offset: 10 + bit_size: 8 + - name: Data1 + description: Data1 + bit_offset: 18 + bit_size: 8 fieldset/OPTKEYR: description: Flash option key register fields: - - bit_offset: 0 - bit_size: 32 - description: Option byte key - name: OPTKEY + - name: OPTKEY + description: Option byte key + bit_offset: 0 + bit_size: 32 fieldset/SR: description: Status register fields: - - bit_offset: 0 - bit_size: 1 - description: Busy - name: BSY - - bit_offset: 2 - bit_size: 1 - description: Programming error - name: PGERR - - bit_offset: 4 - bit_size: 1 - description: Write protection error - name: WRPRTERR - - bit_offset: 5 - bit_size: 1 - description: End of operation - name: EOP + - name: BSY + description: Busy + bit_offset: 0 + bit_size: 1 + - name: PGERR + description: Programming error + bit_offset: 2 + bit_size: 1 + - name: WRPRTERR + description: Write protection error + bit_offset: 4 + bit_size: 1 + - name: EOP + description: End of operation + bit_offset: 5 + bit_size: 1 fieldset/WRPR: description: Write protection register fields: - - bit_offset: 0 - bit_size: 32 - description: Write protect - name: WRP + - name: WRP + description: Write protect + bit_offset: 0 + bit_size: 32 +enum/LATENCY: + bit_size: 3 + variants: + - name: WS0 + description: "Zero wait state, if 0 < SYSCLK≤ 24 MHz" + value: 0 + - name: WS1 + description: "One wait state, if 24 MHz < SYSCLK ≤ 48 MHz" + value: 1 + - name: WS2 + description: "Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz" + value: 2 diff --git a/data/registers/flash_f7.yaml b/data/registers/flash_f7.yaml index e58e05d..5f34009 100644 --- a/data/registers/flash_f7.yaml +++ b/data/registers/flash_f7.yaml @@ -2,381 +2,381 @@ block/FLASH: description: FLASH items: - - byte_offset: 0 - description: Flash access control register - fieldset: ACR - name: ACR - - access: Write - byte_offset: 4 - description: Flash key register - fieldset: KEYR - name: KEYR - - access: Write - byte_offset: 8 - description: Flash option key register - fieldset: OPTKEYR - name: OPTKEYR - - byte_offset: 12 - description: Status register - fieldset: SR - name: SR - - byte_offset: 16 - description: Control register - fieldset: CR - name: CR - - byte_offset: 20 - description: Flash option control register - fieldset: OPTCR - name: OPTCR - - byte_offset: 24 - description: Flash option control register 1 - fieldset: OPTCR1 - name: OPTCR1 - - byte_offset: 28 - description: Flash option control register - fieldset: OPTCR2 - name: OPTCR2 -enum/ARTEN: - bit_size: 1 - variants: - - description: ART Accelerator is disabled - name: Disabled - value: 0 - - description: ART Accelerator is enabled - name: Enabled - value: 1 -enum/ARTRST: - bit_size: 1 - variants: - - description: Accelerator is not reset - name: NotReset - value: 0 - - description: Accelerator is reset - name: Reset - value: 1 -enum/EOPIE: - bit_size: 1 - variants: - - description: End of operation interrupt disabled - name: Disabled - value: 0 - - description: End of operation interrupt enabled - name: Enabled - value: 1 -enum/ERRIE: - bit_size: 1 - variants: - - description: Error interrupt generation disabled - name: Disabled - value: 0 - - description: Error interrupt generation enabled - name: Enabled - value: 1 -enum/LATENCY: - bit_size: 4 - variants: - - description: 0 wait states - name: WS0 - value: 0 - - description: 1 wait states - name: WS1 - value: 1 - - description: 2 wait states - name: WS2 - value: 2 - - description: 3 wait states - name: WS3 - value: 3 - - description: 4 wait states - name: WS4 - value: 4 - - description: 5 wait states - name: WS5 - value: 5 - - description: 6 wait states - name: WS6 - value: 6 - - description: 7 wait states - name: WS7 - value: 7 - - description: 8 wait states - name: WS8 - value: 8 - - description: 9 wait states - name: WS9 - value: 9 - - description: 10 wait states - name: WS10 - value: 10 - - description: 11 wait states - name: WS11 - value: 11 - - description: 12 wait states - name: WS12 - value: 12 - - description: 13 wait states - name: WS13 - value: 13 - - description: 14 wait states - name: WS14 - value: 14 - - description: 15 wait states - name: WS15 - value: 15 -enum/LOCK: - bit_size: 1 - variants: - - description: FLASH_CR register is unlocked - name: Unlocked - value: 0 - - description: FLASH_CR register is locked - name: Locked - value: 1 -enum/MER: - bit_size: 1 - variants: - - description: Erase activated for all user sectors - name: MassErase - value: 1 -enum/PG: - bit_size: 1 - variants: - - description: Flash programming activated - name: Program - value: 1 -enum/PRFTEN: - bit_size: 1 - variants: - - description: Prefetch is disabled - name: Disabled - value: 0 - - description: Prefetch is enabled - name: Enabled - value: 1 -enum/PSIZE: - bit_size: 2 - variants: - - description: Program x8 - name: PSIZE8 - value: 0 - - description: Program x16 - name: PSIZE16 - value: 1 - - description: Program x32 - name: PSIZE32 - value: 2 - - description: Program x64 - name: PSIZE64 - value: 3 -enum/SER: - bit_size: 1 - variants: - - description: Erase activated for selected sector - name: SectorErase - value: 1 -enum/STRT: - bit_size: 1 - variants: - - description: Trigger an erase operation - name: Start - value: 1 + - name: ACR + description: Flash access control register + byte_offset: 0 + fieldset: ACR + - name: KEYR + description: Flash key register + byte_offset: 4 + access: Write + fieldset: KEYR + - name: OPTKEYR + description: Flash option key register + byte_offset: 8 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 12 + fieldset: SR + - name: CR + description: Control register + byte_offset: 16 + fieldset: CR + - name: OPTCR + description: Flash option control register + byte_offset: 20 + fieldset: OPTCR + - name: OPTCR1 + description: Flash option control register 1 + byte_offset: 24 + fieldset: OPTCR1 + - name: OPTCR2 + description: Flash option control register + byte_offset: 28 + fieldset: OPTCR2 fieldset/ACR: description: Flash access control register fields: - - bit_offset: 0 - bit_size: 4 - description: Latency - enum: LATENCY - name: LATENCY - - bit_offset: 8 - bit_size: 1 - description: Prefetch enable - enum: PRFTEN - name: PRFTEN - - bit_offset: 9 - bit_size: 1 - description: ART Accelerator Enable - enum: ARTEN - name: ARTEN - - bit_offset: 11 - bit_size: 1 - description: ART Accelerator reset - enum: ARTRST - name: ARTRST + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 4 + enum: LATENCY + - name: PRFTEN + description: Prefetch enable + bit_offset: 8 + bit_size: 1 + enum: PRFTEN + - name: ARTEN + description: ART Accelerator Enable + bit_offset: 9 + bit_size: 1 + enum: ARTEN + - name: ARTRST + description: ART Accelerator reset + bit_offset: 11 + bit_size: 1 + enum: ARTRST fieldset/CR: description: Control register fields: - - bit_offset: 0 - bit_size: 1 - description: Programming - enum: PG - name: PG - - bit_offset: 1 - bit_size: 1 - description: Sector Erase - enum: SER - name: SER - - bit_offset: 2 - bit_size: 1 - description: Mass Erase of sectors 0 to 11 - enum: MER - name: MER - - bit_offset: 3 - bit_size: 4 - description: Sector number - name: SNB - - bit_offset: 8 - bit_size: 2 - description: Program size - enum: PSIZE - name: PSIZE - - bit_offset: 16 - bit_size: 1 - description: Start - enum: STRT - name: STRT - - bit_offset: 24 - bit_size: 1 - description: End of operation interrupt enable - enum: EOPIE - name: EOPIE - - bit_offset: 25 - bit_size: 1 - description: Error interrupt enable - enum: ERRIE - name: ERRIE - - bit_offset: 26 - bit_size: 1 - description: PCROP error interrupt enable - name: RDERRIE - - bit_offset: 31 - bit_size: 1 - description: Lock - enum: LOCK - name: LOCK + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + enum: PG + - name: SER + description: Sector Erase + bit_offset: 1 + bit_size: 1 + enum: SER + - name: MER + description: Mass Erase of sectors 0 to 11 + bit_offset: 2 + bit_size: 1 + enum: MER + - name: SNB + description: Sector number + bit_offset: 3 + bit_size: 4 + - name: PSIZE + description: Program size + bit_offset: 8 + bit_size: 2 + enum: PSIZE + - name: STRT + description: Start + bit_offset: 16 + bit_size: 1 + enum: STRT + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 24 + bit_size: 1 + enum: EOPIE + - name: ERRIE + description: Error interrupt enable + bit_offset: 25 + bit_size: 1 + enum: ERRIE + - name: RDERRIE + description: PCROP error interrupt enable + bit_offset: 26 + bit_size: 1 + - name: LOCK + description: Lock + bit_offset: 31 + bit_size: 1 + enum: LOCK fieldset/KEYR: description: Flash key register fields: - - bit_offset: 0 - bit_size: 32 - description: FPEC key - name: KEY + - name: KEY + description: FPEC key + bit_offset: 0 + bit_size: 32 fieldset/OPTCR: description: Flash option control register fields: - - bit_offset: 0 - bit_size: 1 - description: Option lock - name: OPTLOCK - - bit_offset: 1 - bit_size: 1 - description: Option start - name: OPTSTRT - - bit_offset: 2 - bit_size: 2 - description: BOR reset Level - name: BOR_LEV - - bit_offset: 4 - bit_size: 1 - description: User option bytes - name: WWDG_SW - - bit_offset: 5 - bit_size: 1 - description: WDG_SW User option bytes - name: IWDG_SW - - bit_offset: 6 - bit_size: 1 - description: nRST_STOP User option bytes - name: nRST_STOP - - bit_offset: 7 - bit_size: 1 - description: nRST_STDBY User option bytes - name: nRST_STDBY - - bit_offset: 8 - bit_size: 8 - description: Read protect - name: RDP - - bit_offset: 16 - bit_size: 8 - description: Not write protect - name: nWRP - - bit_offset: 28 - bit_size: 1 - description: Dual Boot mode (valid only when nDBANK=0) - name: nDBOOT - - bit_offset: 29 - bit_size: 1 - description: Not dual bank mode - name: nDBANK - - bit_offset: 30 - bit_size: 1 - description: Independent watchdog counter freeze in standby mode - name: IWDG_STDBY - - bit_offset: 31 - bit_size: 1 - description: Independent watchdog counter freeze in Stop mode - name: IWDG_STOP + - name: OPTLOCK + description: Option lock + bit_offset: 0 + bit_size: 1 + - name: OPTSTRT + description: Option start + bit_offset: 1 + bit_size: 1 + - name: BOR_LEV + description: BOR reset Level + bit_offset: 2 + bit_size: 2 + - name: WWDG_SW + description: User option bytes + bit_offset: 4 + bit_size: 1 + - name: IWDG_SW + description: WDG_SW User option bytes + bit_offset: 5 + bit_size: 1 + - name: nRST_STOP + description: nRST_STOP User option bytes + bit_offset: 6 + bit_size: 1 + - name: nRST_STDBY + description: nRST_STDBY User option bytes + bit_offset: 7 + bit_size: 1 + - name: RDP + description: Read protect + bit_offset: 8 + bit_size: 8 + - name: nWRP + description: Not write protect + bit_offset: 16 + bit_size: 8 + - name: nDBOOT + description: Dual Boot mode (valid only when nDBANK=0) + bit_offset: 28 + bit_size: 1 + - name: nDBANK + description: Not dual bank mode + bit_offset: 29 + bit_size: 1 + - name: IWDG_STDBY + description: Independent watchdog counter freeze in standby mode + bit_offset: 30 + bit_size: 1 + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 31 + bit_size: 1 fieldset/OPTCR1: description: Flash option control register 1 fields: - - bit_offset: 0 - bit_size: 16 - description: Boot base address when Boot pin =0 - name: BOOT_ADD0 - - bit_offset: 16 - bit_size: 16 - description: Boot base address when Boot pin =1 - name: BOOT_ADD1 + - name: BOOT_ADD0 + description: Boot base address when Boot pin =0 + bit_offset: 0 + bit_size: 16 + - name: BOOT_ADD1 + description: Boot base address when Boot pin =1 + bit_offset: 16 + bit_size: 16 fieldset/OPTCR2: description: Flash option control register fields: - - bit_offset: 0 - bit_size: 8 - description: PCROP option byte - name: PCROPi - - bit_offset: 31 - bit_size: 1 - description: PCROP zone preserved when RDP level decreased - name: PCROP_RDP + - name: PCROPi + description: PCROP option byte + bit_offset: 0 + bit_size: 8 + - name: PCROP_RDP + description: PCROP zone preserved when RDP level decreased + bit_offset: 31 + bit_size: 1 fieldset/OPTKEYR: description: Flash option key register fields: - - bit_offset: 0 - bit_size: 32 - description: Option byte key - name: OPTKEYR + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 fieldset/SR: description: Status register fields: - - bit_offset: 0 - bit_size: 1 - description: End of operation - name: EOP - - bit_offset: 1 - bit_size: 1 - description: Operation error - name: OPERR - - bit_offset: 4 - bit_size: 1 - description: Write protection error - name: WRPERR - - bit_offset: 5 - bit_size: 1 - description: Programming alignment error - name: PGAERR - - bit_offset: 6 - bit_size: 1 - description: Programming parallelism error - name: PGPERR - - bit_offset: 7 - bit_size: 1 - description: Erase Sequence Error - name: ERSERR - - bit_offset: 8 - bit_size: 1 - description: RDERR - name: RDERR - - bit_offset: 16 - bit_size: 1 - description: Busy - name: BSY + - name: EOP + description: End of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Operation error + bit_offset: 1 + bit_size: 1 + - name: WRPERR + description: Write protection error + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 5 + bit_size: 1 + - name: PGPERR + description: Programming parallelism error + bit_offset: 6 + bit_size: 1 + - name: ERSERR + description: Erase Sequence Error + bit_offset: 7 + bit_size: 1 + - name: RDERR + description: RDERR + bit_offset: 8 + bit_size: 1 + - name: BSY + description: Busy + bit_offset: 16 + bit_size: 1 +enum/ARTEN: + bit_size: 1 + variants: + - name: Disabled + description: ART Accelerator is disabled + value: 0 + - name: Enabled + description: ART Accelerator is enabled + value: 1 +enum/ARTRST: + bit_size: 1 + variants: + - name: NotReset + description: Accelerator is not reset + value: 0 + - name: Reset + description: Accelerator is reset + value: 1 +enum/EOPIE: + bit_size: 1 + variants: + - name: Disabled + description: End of operation interrupt disabled + value: 0 + - name: Enabled + description: End of operation interrupt enabled + value: 1 +enum/ERRIE: + bit_size: 1 + variants: + - name: Disabled + description: Error interrupt generation disabled + value: 0 + - name: Enabled + description: Error interrupt generation enabled + value: 1 +enum/LATENCY: + bit_size: 4 + variants: + - name: WS0 + description: 0 wait states + value: 0 + - name: WS1 + description: 1 wait states + value: 1 + - name: WS2 + description: 2 wait states + value: 2 + - name: WS3 + description: 3 wait states + value: 3 + - name: WS4 + description: 4 wait states + value: 4 + - name: WS5 + description: 5 wait states + value: 5 + - name: WS6 + description: 6 wait states + value: 6 + - name: WS7 + description: 7 wait states + value: 7 + - name: WS8 + description: 8 wait states + value: 8 + - name: WS9 + description: 9 wait states + value: 9 + - name: WS10 + description: 10 wait states + value: 10 + - name: WS11 + description: 11 wait states + value: 11 + - name: WS12 + description: 12 wait states + value: 12 + - name: WS13 + description: 13 wait states + value: 13 + - name: WS14 + description: 14 wait states + value: 14 + - name: WS15 + description: 15 wait states + value: 15 +enum/LOCK: + bit_size: 1 + variants: + - name: Unlocked + description: FLASH_CR register is unlocked + value: 0 + - name: Locked + description: FLASH_CR register is locked + value: 1 +enum/MER: + bit_size: 1 + variants: + - name: MassErase + description: Erase activated for all user sectors + value: 1 +enum/PG: + bit_size: 1 + variants: + - name: Program + description: Flash programming activated + value: 1 +enum/PRFTEN: + bit_size: 1 + variants: + - name: Disabled + description: Prefetch is disabled + value: 0 + - name: Enabled + description: Prefetch is enabled + value: 1 +enum/PSIZE: + bit_size: 2 + variants: + - name: PSIZE8 + description: Program x8 + value: 0 + - name: PSIZE16 + description: Program x16 + value: 1 + - name: PSIZE32 + description: Program x32 + value: 2 + - name: PSIZE64 + description: Program x64 + value: 3 +enum/SER: + bit_size: 1 + variants: + - name: SectorErase + description: Erase activated for selected sector + value: 1 +enum/STRT: + bit_size: 1 + variants: + - name: Start + description: Trigger an erase operation + value: 1 diff --git a/data/registers/flash_l4.yaml b/data/registers/flash_l4.yaml index 3de8c51..8cc2bc1 100644 --- a/data/registers/flash_l4.yaml +++ b/data/registers/flash_l4.yaml @@ -1,408 +1,409 @@ +--- block/FLASH: description: Flash items: - - byte_offset: 0 - description: Access control register - fieldset: ACR - name: ACR - - access: Write - byte_offset: 4 - description: Power down key register - fieldset: PDKEYR - name: PDKEYR - - access: Write - byte_offset: 8 - description: Flash key register - fieldset: KEYR - name: KEYR - - access: Write - byte_offset: 12 - description: Option byte key register - fieldset: OPTKEYR - name: OPTKEYR - - byte_offset: 16 - description: Status register - fieldset: SR - name: SR - - byte_offset: 20 - description: Flash control register - fieldset: CR - name: CR - - byte_offset: 24 - description: Flash ECC register - fieldset: ECCR - name: ECCR - - byte_offset: 32 - description: Flash option register - fieldset: OPTR - name: OPTR - - byte_offset: 36 - description: Flash Bank 1 PCROP Start address register - fieldset: PCROP1SR - name: PCROP1SR - - byte_offset: 40 - description: Flash Bank 1 PCROP End address register - fieldset: PCROP1ER - name: PCROP1ER - - byte_offset: 44 - description: Flash Bank 1 WRP area A address register - fieldset: WRP1AR - name: WRP1AR - - byte_offset: 48 - description: Flash Bank 1 WRP area B address register - fieldset: WRP1BR - name: WRP1BR - - byte_offset: 68 - description: Flash Bank 2 PCROP Start address register - fieldset: PCROP2SR - name: PCROP2SR - - byte_offset: 72 - description: Flash Bank 2 PCROP End address register - fieldset: PCROP2ER - name: PCROP2ER - - byte_offset: 76 - description: Flash Bank 2 WRP area A address register - fieldset: WRP2AR - name: WRP2AR - - byte_offset: 80 - description: Flash Bank 2 WRP area B address register - fieldset: WRP2BR - name: WRP2BR + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: PDKEYR + description: Power down key register + byte_offset: 4 + access: Write + fieldset: PDKEYR + - name: KEYR + description: Flash key register + byte_offset: 8 + access: Write + fieldset: KEYR + - name: OPTKEYR + description: Option byte key register + byte_offset: 12 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 16 + fieldset: SR + - name: CR + description: Flash control register + byte_offset: 20 + fieldset: CR + - name: ECCR + description: Flash ECC register + byte_offset: 24 + fieldset: ECCR + - name: OPTR + description: Flash option register + byte_offset: 32 + fieldset: OPTR + - name: PCROP1SR + description: Flash Bank 1 PCROP Start address register + byte_offset: 36 + fieldset: PCROP1SR + - name: PCROP1ER + description: Flash Bank 1 PCROP End address register + byte_offset: 40 + fieldset: PCROP1ER + - name: WRP1AR + description: Flash Bank 1 WRP area A address register + byte_offset: 44 + fieldset: WRP1AR + - name: WRP1BR + description: Flash Bank 1 WRP area B address register + byte_offset: 48 + fieldset: WRP1BR + - name: PCROP2SR + description: Flash Bank 2 PCROP Start address register + byte_offset: 68 + fieldset: PCROP2SR + - name: PCROP2ER + description: Flash Bank 2 PCROP End address register + byte_offset: 72 + fieldset: PCROP2ER + - name: WRP2AR + description: Flash Bank 2 WRP area A address register + byte_offset: 76 + fieldset: WRP2AR + - name: WRP2BR + description: Flash Bank 2 WRP area B address register + byte_offset: 80 + fieldset: WRP2BR fieldset/ACR: description: Access control register fields: - - bit_offset: 0 - bit_size: 3 - description: Latency - name: LATENCY - - bit_offset: 8 - bit_size: 1 - description: Prefetch enable - name: PRFTEN - - bit_offset: 9 - bit_size: 1 - description: Instruction cache enable - name: ICEN - - bit_offset: 10 - bit_size: 1 - description: Data cache enable - name: DCEN - - bit_offset: 11 - bit_size: 1 - description: Instruction cache reset - name: ICRST - - bit_offset: 12 - bit_size: 1 - description: Data cache reset - name: DCRST - - bit_offset: 13 - bit_size: 1 - description: Flash Power-down mode during Low-power run mode - name: RUN_PD - - bit_offset: 14 - bit_size: 1 - description: Flash Power-down mode during Low-power sleep mode - name: SLEEP_PD + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 3 + - name: PRFTEN + description: Prefetch enable + bit_offset: 8 + bit_size: 1 + - name: ICEN + description: Instruction cache enable + bit_offset: 9 + bit_size: 1 + - name: DCEN + description: Data cache enable + bit_offset: 10 + bit_size: 1 + - name: ICRST + description: Instruction cache reset + bit_offset: 11 + bit_size: 1 + - name: DCRST + description: Data cache reset + bit_offset: 12 + bit_size: 1 + - name: RUN_PD + description: Flash Power-down mode during Low-power run mode + bit_offset: 13 + bit_size: 1 + - name: SLEEP_PD + description: Flash Power-down mode during Low-power sleep mode + bit_offset: 14 + bit_size: 1 fieldset/CR: description: Flash control register fields: - - bit_offset: 0 - bit_size: 1 - description: Programming - name: PG - - bit_offset: 1 - bit_size: 1 - description: Page erase - name: PER - - array: - len: 2 - stride: 13 - bit_offset: 2 - bit_size: 1 - description: Bank 1 Mass erase - name: MER - - bit_offset: 3 - bit_size: 8 - description: Page number - name: PNB - - bit_offset: 11 - bit_size: 1 - description: Bank erase - name: BKER - - bit_offset: 16 - bit_size: 1 - description: Start - name: START - - bit_offset: 17 - bit_size: 1 - description: Options modification start - name: OPTSTRT - - bit_offset: 18 - bit_size: 1 - description: Fast programming - name: FSTPG - - bit_offset: 24 - bit_size: 1 - description: End of operation interrupt enable - name: EOPIE - - bit_offset: 25 - bit_size: 1 - description: Error interrupt enable - name: ERRIE - - bit_offset: 26 - bit_size: 1 - description: PCROP read error interrupt enable - name: RDERRIE - - bit_offset: 27 - bit_size: 1 - description: Force the option byte loading - name: OBL_LAUNCH - - bit_offset: 30 - bit_size: 1 - description: Options Lock - name: OPTLOCK - - bit_offset: 31 - bit_size: 1 - description: FLASH_CR Lock - name: LOCK + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: Bank 1 Mass erase + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 13 + - name: PNB + description: Page number + bit_offset: 3 + bit_size: 8 + - name: BKER + description: Bank erase + bit_offset: 11 + bit_size: 1 + - name: START + description: Start + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: Options modification start + bit_offset: 17 + bit_size: 1 + - name: FSTPG + description: Fast programming + bit_offset: 18 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 25 + bit_size: 1 + - name: RDERRIE + description: PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 + - name: OBL_LAUNCH + description: Force the option byte loading + bit_offset: 27 + bit_size: 1 + - name: OPTLOCK + description: Options Lock + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: FLASH_CR Lock + bit_offset: 31 + bit_size: 1 fieldset/ECCR: description: Flash ECC register fields: - - bit_offset: 0 - bit_size: 19 - description: ECC fail address - name: ADDR_ECC - - bit_offset: 19 - bit_size: 1 - description: ECC fail bank - name: BK_ECC - - bit_offset: 20 - bit_size: 1 - description: System Flash ECC fail - name: SYSF_ECC - - bit_offset: 24 - bit_size: 1 - description: ECC correction interrupt enable - name: ECCIE - - bit_offset: 30 - bit_size: 1 - description: ECC correction - name: ECCC - - bit_offset: 31 - bit_size: 1 - description: ECC detection - name: ECCD + - name: ADDR_ECC + description: ECC fail address + bit_offset: 0 + bit_size: 19 + - name: BK_ECC + description: ECC fail bank + bit_offset: 19 + bit_size: 1 + - name: SYSF_ECC + description: System Flash ECC fail + bit_offset: 20 + bit_size: 1 + - name: ECCIE + description: ECC correction interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ECCC + description: ECC correction + bit_offset: 30 + bit_size: 1 + - name: ECCD + description: ECC detection + bit_offset: 31 + bit_size: 1 fieldset/KEYR: description: Flash key register fields: - - bit_offset: 0 - bit_size: 32 - description: KEYR - name: KEYR + - name: KEYR + description: KEYR + bit_offset: 0 + bit_size: 32 fieldset/OPTKEYR: description: Option byte key register fields: - - bit_offset: 0 - bit_size: 32 - description: Option byte key - name: OPTKEYR + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 fieldset/OPTR: description: Flash option register fields: - - bit_offset: 0 - bit_size: 8 - description: Read protection level - name: RDP - - bit_offset: 8 - bit_size: 3 - description: BOR reset Level - name: BOR_LEV - - bit_offset: 12 - bit_size: 1 - description: nRST_STOP - name: nRST_STOP - - bit_offset: 13 - bit_size: 1 - description: nRST_STDBY - name: nRST_STDBY - - bit_offset: 16 - bit_size: 1 - description: Independent watchdog selection - name: IDWG_SW - - bit_offset: 17 - bit_size: 1 - description: Independent watchdog counter freeze in Stop mode - name: IWDG_STOP - - bit_offset: 18 - bit_size: 1 - description: Independent watchdog counter freeze in Standby mode - name: IWDG_STDBY - - bit_offset: 19 - bit_size: 1 - description: Window watchdog selection - name: WWDG_SW - - array: - len: 1 - stride: 0 - bit_offset: 20 - bit_size: 1 - description: Dual-bank boot - name: BFB - - bit_offset: 21 - bit_size: 1 - description: Dual-Bank on 512 KB or 256 KB Flash memory devices - name: DUALBANK - - bit_offset: 23 - bit_size: 1 - description: Boot configuration - name: nBOOT1 - - bit_offset: 24 - bit_size: 1 - description: SRAM2 parity check enable - name: SRAM2_PE - - bit_offset: 25 - bit_size: 1 - description: SRAM2 Erase when system reset - name: SRAM2_RST - - bit_offset: 26 - bit_size: 1 - description: Software BOOT0 - name: nSWBOOT0 - - bit_offset: 27 - bit_size: 1 - description: nBOOT0 option bit - name: nBOOT0 + - name: RDP + description: Read protection level + bit_offset: 0 + bit_size: 8 + - name: BOR_LEV + description: BOR reset Level + bit_offset: 8 + bit_size: 3 + - name: nRST_STOP + description: nRST_STOP + bit_offset: 12 + bit_size: 1 + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 13 + bit_size: 1 + - name: IDWG_SW + description: Independent watchdog selection + bit_offset: 16 + bit_size: 1 + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 17 + bit_size: 1 + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode + bit_offset: 18 + bit_size: 1 + - name: WWDG_SW + description: Window watchdog selection + bit_offset: 19 + bit_size: 1 + - name: BFB + description: Dual-bank boot + bit_offset: 20 + bit_size: 1 + array: + len: 1 + stride: 0 + - name: DUALBANK + description: Dual-Bank on 512 KB or 256 KB Flash memory devices + bit_offset: 21 + bit_size: 1 + - name: nBOOT1 + description: Boot configuration + bit_offset: 23 + bit_size: 1 + - name: SRAM2_PE + description: SRAM2 parity check enable + bit_offset: 24 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 Erase when system reset + bit_offset: 25 + bit_size: 1 + - name: nSWBOOT0 + description: Software BOOT0 + bit_offset: 26 + bit_size: 1 + - name: nBOOT0 + description: nBOOT0 option bit + bit_offset: 27 + bit_size: 1 fieldset/PCROP1ER: description: Flash Bank 1 PCROP End address register fields: - - bit_offset: 0 - bit_size: 16 - description: Bank 1 PCROP area end offset - name: PCROP1_END - - bit_offset: 31 - bit_size: 1 - description: PCROP area preserved when RDP level decreased - name: PCROP_RDP + - name: PCROP1_END + description: Bank 1 PCROP area end offset + bit_offset: 0 + bit_size: 16 + - name: PCROP_RDP + description: PCROP area preserved when RDP level decreased + bit_offset: 31 + bit_size: 1 fieldset/PCROP1SR: description: Flash Bank 1 PCROP Start address register fields: - - bit_offset: 0 - bit_size: 16 - description: Bank 1 PCROP area start offset - name: PCROP1_STRT + - name: PCROP1_STRT + description: Bank 1 PCROP area start offset + bit_offset: 0 + bit_size: 16 fieldset/PCROP2ER: description: Flash Bank 2 PCROP End address register fields: - - bit_offset: 0 - bit_size: 16 - description: Bank 2 PCROP area end offset - name: PCROP2_END + - name: PCROP2_END + description: Bank 2 PCROP area end offset + bit_offset: 0 + bit_size: 16 fieldset/PCROP2SR: description: Flash Bank 2 PCROP Start address register fields: - - bit_offset: 0 - bit_size: 16 - description: Bank 2 PCROP area start offset - name: PCROP2_STRT + - name: PCROP2_STRT + description: Bank 2 PCROP area start offset + bit_offset: 0 + bit_size: 16 fieldset/PDKEYR: description: Power down key register fields: - - bit_offset: 0 - bit_size: 32 - description: RUN_PD in FLASH_ACR key - name: PDKEYR + - name: PDKEYR + description: RUN_PD in FLASH_ACR key + bit_offset: 0 + bit_size: 32 fieldset/SR: description: Status register fields: - - bit_offset: 0 - bit_size: 1 - description: End of operation - name: EOP - - bit_offset: 1 - bit_size: 1 - description: Operation error - name: OPERR - - bit_offset: 3 - bit_size: 1 - description: Programming error - name: PROGERR - - bit_offset: 4 - bit_size: 1 - description: Write protected error - name: WRPERR - - bit_offset: 5 - bit_size: 1 - description: Programming alignment error - name: PGAERR - - bit_offset: 6 - bit_size: 1 - description: Size error - name: SIZERR - - bit_offset: 7 - bit_size: 1 - description: Programming sequence error - name: PGSERR - - bit_offset: 8 - bit_size: 1 - description: Fast programming data miss error - name: MISERR - - bit_offset: 9 - bit_size: 1 - description: Fast programming error - name: FASTERR - - bit_offset: 14 - bit_size: 1 - description: PCROP read error - name: RDERR - - bit_offset: 15 - bit_size: 1 - description: Option validity error - name: OPTVERR - - bit_offset: 16 - bit_size: 1 - description: Busy - name: BSY + - name: EOP + description: End of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Programming error + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: Write protected error + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Programming sequence error + bit_offset: 7 + bit_size: 1 + - name: MISERR + description: Fast programming data miss error + bit_offset: 8 + bit_size: 1 + - name: FASTERR + description: Fast programming error + bit_offset: 9 + bit_size: 1 + - name: RDERR + description: PCROP read error + bit_offset: 14 + bit_size: 1 + - name: OPTVERR + description: Option validity error + bit_offset: 15 + bit_size: 1 + - name: BSY + description: Busy + bit_offset: 16 + bit_size: 1 fieldset/WRP1AR: description: Flash Bank 1 WRP area A address register fields: - - bit_offset: 0 - bit_size: 8 - description: Bank 1 WRP first area tart offset - name: WRP1A_STRT - - bit_offset: 16 - bit_size: 8 - description: Bank 1 WRP first area A end offset - name: WRP1A_END + - name: WRP1A_STRT + description: Bank 1 WRP first area tart offset + bit_offset: 0 + bit_size: 8 + - name: WRP1A_END + description: Bank 1 WRP first area A end offset + bit_offset: 16 + bit_size: 8 fieldset/WRP1BR: description: Flash Bank 1 WRP area B address register fields: - - bit_offset: 0 - bit_size: 8 - description: Bank 1 WRP second area B start offset - name: WRP1B_STRT - - bit_offset: 16 - bit_size: 8 - description: Bank 1 WRP second area B end offset - name: WRP1B_END + - name: WRP1B_STRT + description: Bank 1 WRP second area B start offset + bit_offset: 0 + bit_size: 8 + - name: WRP1B_END + description: Bank 1 WRP second area B end offset + bit_offset: 16 + bit_size: 8 fieldset/WRP2AR: description: Flash Bank 2 WRP area A address register fields: - - bit_offset: 0 - bit_size: 8 - description: Bank 2 WRP first area A start offset - name: WRP2A_STRT - - bit_offset: 16 - bit_size: 8 - description: Bank 2 WRP first area A end offset - name: WRP2A_END + - name: WRP2A_STRT + description: Bank 2 WRP first area A start offset + bit_offset: 0 + bit_size: 8 + - name: WRP2A_END + description: Bank 2 WRP first area A end offset + bit_offset: 16 + bit_size: 8 fieldset/WRP2BR: description: Flash Bank 2 WRP area B address register fields: - - bit_offset: 0 - bit_size: 8 - description: Bank 2 WRP second area B start offset - name: WRP2B_STRT - - bit_offset: 16 - bit_size: 8 - description: Bank 2 WRP second area B end offset - name: WRP2B_END + - name: WRP2B_STRT + description: Bank 2 WRP second area B start offset + bit_offset: 0 + bit_size: 8 + - name: WRP2B_END + description: Bank 2 WRP second area B end offset + bit_offset: 16 + bit_size: 8 diff --git a/data/registers/gpio_v1.yaml b/data/registers/gpio_v1.yaml index bbec2b7..386d4c0 100644 --- a/data/registers/gpio_v1.yaml +++ b/data/registers/gpio_v1.yaml @@ -4,39 +4,33 @@ block/GPIO: items: - name: CR description: Port configuration register low (GPIOn_CRL) - byte_offset: 0 - reset_value: 1145324612 array: len: 2 stride: 4 + byte_offset: 0 fieldset: CR - name: IDR description: Port input data register (GPIOn_IDR) byte_offset: 8 - reset_value: 0 access: Read fieldset: IDR - name: ODR description: Port output data register (GPIOn_ODR) byte_offset: 12 - reset_value: 0 fieldset: ODR - name: BSRR description: Port bit set/reset register (GPIOn_BSRR) byte_offset: 16 - reset_value: 0 access: Write fieldset: BSRR - name: BRR description: Port bit reset register (GPIOn_BRR) byte_offset: 20 - reset_value: 0 access: Write fieldset: BRR - name: LCKR description: Port configuration lock register byte_offset: 24 - reset_value: 0 fieldset: LCKR fieldset/BRR: description: Port bit reset register (GPIOn_BRR) @@ -208,4 +202,4 @@ enum/ODR: value: 1 - name: Low description: Set output to logic low - value: 0 \ No newline at end of file + value: 0 diff --git a/data/registers/gpio_v2.yaml b/data/registers/gpio_v2.yaml index 106d4b4..cd9f3c5 100644 --- a/data/registers/gpio_v2.yaml +++ b/data/registers/gpio_v2.yaml @@ -5,52 +5,43 @@ block/GPIO: - name: MODER description: GPIO port mode register byte_offset: 0 - reset_value: 2818572288 fieldset: MODER - name: OTYPER description: GPIO port output type register byte_offset: 4 - reset_value: 0 fieldset: OTYPER - name: OSPEEDR description: GPIO port output speed register byte_offset: 8 - reset_value: 0 fieldset: OSPEEDR - name: PUPDR description: GPIO port pull-up/pull-down register byte_offset: 12 - reset_value: 1677721600 fieldset: PUPDR - name: IDR description: GPIO port input data register byte_offset: 16 - reset_value: 0 access: Read fieldset: IDR - name: ODR description: GPIO port output data register byte_offset: 20 - reset_value: 0 fieldset: ODR - name: BSRR description: GPIO port bit set/reset register byte_offset: 24 - reset_value: 0 access: Write fieldset: BSRR - name: LCKR description: GPIO port configuration lock register byte_offset: 28 - reset_value: 0 fieldset: LCKR - name: AFR - description: GPIO alternate function register (low, high) - byte_offset: 32 - reset_value: 0 + description: "GPIO alternate function register (low, high)" array: len: 2 stride: 4 + byte_offset: 32 fieldset: AFR fieldset/AFR: description: GPIO alternate function register @@ -313,4 +304,4 @@ enum/PUPDR: value: 1 - name: PullDown description: Pull-down - value: 2 \ No newline at end of file + value: 2 diff --git a/data/registers/ipcc_v1.yaml b/data/registers/ipcc_v1.yaml index 7b38019..caee0b1 100644 --- a/data/registers/ipcc_v1.yaml +++ b/data/registers/ipcc_v1.yaml @@ -4,11 +4,10 @@ block/IPCC: items: - name: CPU description: CPU specific registers - byte_offset: 0 array: len: 2 stride: 16 - + byte_offset: 0 block/IPCC_CPU: description: IPCC items: diff --git a/data/registers/iwdg_v2.yaml b/data/registers/iwdg_v2.yaml index 1ca5c4d..a74774c 100644 --- a/data/registers/iwdg_v2.yaml +++ b/data/registers/iwdg_v2.yaml @@ -2,109 +2,109 @@ block/IWDG: description: Independent watchdog items: - - access: Write - byte_offset: 0 - description: Key register - fieldset: KR - name: KR - - byte_offset: 4 - description: Prescaler register - fieldset: PR - name: PR - - byte_offset: 8 - description: Reload register - fieldset: RLR - name: RLR - - access: Read - byte_offset: 12 - description: Status register - fieldset: SR - name: SR - - byte_offset: 16 - description: Window register - fieldset: WINR - name: WINR -enum/KEY: - bit_size: 16 - variants: - - description: Enable access to PR, RLR and WINR registers (0x5555) - name: Enable - value: 21845 - - description: Reset the watchdog value (0xAAAA) - name: Reset - value: 43690 - - description: Start the watchdog (0xCCCC) - name: Start - value: 52428 -enum/PR: - bit_size: 3 - variants: - - description: Divider /4 - name: DivideBy4 - value: 0 - - description: Divider /8 - name: DivideBy8 - value: 1 - - description: Divider /16 - name: DivideBy16 - value: 2 - - description: Divider /32 - name: DivideBy32 - value: 3 - - description: Divider /64 - name: DivideBy64 - value: 4 - - description: Divider /128 - name: DivideBy128 - value: 5 - - description: Divider /256 - name: DivideBy256 - value: 6 - - description: Divider /256 - name: DivideBy256bis - value: 7 + - name: KR + description: Key register + byte_offset: 0 + access: Write + fieldset: KR + - name: PR + description: Prescaler register + byte_offset: 4 + fieldset: PR + - name: RLR + description: Reload register + byte_offset: 8 + fieldset: RLR + - name: SR + description: Status register + byte_offset: 12 + access: Read + fieldset: SR + - name: WINR + description: Window register + byte_offset: 16 + fieldset: WINR fieldset/KR: description: Key register fields: - - bit_offset: 0 - bit_size: 16 - description: Key value (write only, read 0000h) - enum: KEY - name: KEY + - name: KEY + description: "Key value (write only, read 0000h)" + bit_offset: 0 + bit_size: 16 + enum: KEY fieldset/PR: description: Prescaler register fields: - - bit_offset: 0 - bit_size: 3 - description: Prescaler divider - enum: PR - name: PR + - name: PR + description: Prescaler divider + bit_offset: 0 + bit_size: 3 + enum: PR fieldset/RLR: description: Reload register fields: - - bit_offset: 0 - bit_size: 12 - description: Watchdog counter reload value - name: RL + - name: RL + description: Watchdog counter reload value + bit_offset: 0 + bit_size: 12 fieldset/SR: description: Status register fields: - - bit_offset: 0 - bit_size: 1 - description: Watchdog prescaler value update - name: PVU - - bit_offset: 1 - bit_size: 1 - description: Watchdog counter reload value update - name: RVU - - bit_offset: 2 - bit_size: 1 - description: Watchdog counter window value update - name: WVU + - name: PVU + description: Watchdog prescaler value update + bit_offset: 0 + bit_size: 1 + - name: RVU + description: Watchdog counter reload value update + bit_offset: 1 + bit_size: 1 + - name: WVU + description: Watchdog counter window value update + bit_offset: 2 + bit_size: 1 fieldset/WINR: description: Window register fields: - - bit_offset: 0 - bit_size: 12 - description: Watchdog counter window value - name: WIN + - name: WIN + description: Watchdog counter window value + bit_offset: 0 + bit_size: 12 +enum/KEY: + bit_size: 16 + variants: + - name: Enable + description: "Enable access to PR, RLR and WINR registers (0x5555)" + value: 21845 + - name: Reset + description: Reset the watchdog value (0xAAAA) + value: 43690 + - name: Start + description: Start the watchdog (0xCCCC) + value: 52428 +enum/PR: + bit_size: 3 + variants: + - name: DivideBy4 + description: Divider /4 + value: 0 + - name: DivideBy8 + description: Divider /8 + value: 1 + - name: DivideBy16 + description: Divider /16 + value: 2 + - name: DivideBy32 + description: Divider /32 + value: 3 + - name: DivideBy64 + description: Divider /64 + value: 4 + - name: DivideBy128 + description: Divider /128 + value: 5 + - name: DivideBy256 + description: Divider /256 + value: 6 + - name: DivideBy256bis + description: Divider /256 + value: 7 diff --git a/data/registers/jpeg_v1.yaml b/data/registers/jpeg_v1.yaml index 6ea011e..5783765 100644 --- a/data/registers/jpeg_v1.yaml +++ b/data/registers/jpeg_v1.yaml @@ -2,5848 +2,5848 @@ block/JPEG: description: JPEG codec items: - - access: Write - byte_offset: 0 - description: JPEG codec configuration register 0 - fieldset: JPEG_CONFR0 - name: JPEG_CONFR0 - - byte_offset: 4 - description: JPEG codec configuration register 1 - fieldset: JPEG_CONFR1 - name: JPEG_CONFR1 - - byte_offset: 8 - description: JPEG codec configuration register 2 - fieldset: JPEG_CONFR2 - name: JPEG_CONFR2 - - byte_offset: 12 - description: JPEG codec configuration register 3 - fieldset: JPEG_CONFR3 - name: JPEG_CONFR3 - - byte_offset: 16 - description: JPEG codec configuration register 4 - fieldset: JPEG_CONFR4 - name: JPEG_CONFR4 - - byte_offset: 20 - description: JPEG codec configuration register 5 - fieldset: JPEG_CONFR5 - name: JPEG_CONFR5 - - byte_offset: 24 - description: JPEG codec configuration register 6 - fieldset: JPEG_CONFR6 - name: JPEG_CONFR6 - - byte_offset: 28 - description: JPEG codec configuration register 7 - fieldset: JPEG_CONFR7 - name: JPEG_CONFR7 - - byte_offset: 48 - description: JPEG control register - fieldset: JPEG_CR - name: JPEG_CR - - access: Read - byte_offset: 52 - description: JPEG status register - fieldset: JPEG_SR - name: JPEG_SR - - access: Write - byte_offset: 56 - description: JPEG clear flag register - fieldset: JPEG_CFR - name: JPEG_CFR - - access: Write - byte_offset: 64 - description: JPEG data input register - fieldset: JPEG_DIR - name: JPEG_DIR - - access: Read - byte_offset: 68 - description: JPEG data output register - fieldset: JPEG_DOR - name: JPEG_DOR - - byte_offset: 80 - description: JPEG quantization tables - fieldset: QMEM0_0 - name: QMEM0_0 - - byte_offset: 84 - description: JPEG quantization tables - fieldset: QMEM0_1 - name: QMEM0_1 - - byte_offset: 88 - description: JPEG quantization tables - fieldset: QMEM0_2 - name: QMEM0_2 - - byte_offset: 92 - description: JPEG quantization tables - fieldset: QMEM0_3 - name: QMEM0_3 - - byte_offset: 96 - description: JPEG quantization tables - fieldset: QMEM0_4 - name: QMEM0_4 - - byte_offset: 100 - description: JPEG quantization tables - fieldset: QMEM0_5 - name: QMEM0_5 - - byte_offset: 104 - description: JPEG quantization tables - fieldset: QMEM0_6 - name: QMEM0_6 - - byte_offset: 108 - description: JPEG quantization tables - fieldset: QMEM0_7 - name: QMEM0_7 - - byte_offset: 112 - description: JPEG quantization tables - fieldset: QMEM0_8 - name: QMEM0_8 - - byte_offset: 116 - description: JPEG quantization tables - fieldset: QMEM0_9 - name: QMEM0_9 - - byte_offset: 120 - description: JPEG quantization tables - fieldset: QMEM0_10 - name: QMEM0_10 - - byte_offset: 124 - description: JPEG quantization tables - fieldset: QMEM0_11 - name: QMEM0_11 - - byte_offset: 128 - description: JPEG quantization tables - fieldset: QMEM0_12 - name: QMEM0_12 - - byte_offset: 132 - description: JPEG quantization tables - fieldset: QMEM0_13 - name: QMEM0_13 - - byte_offset: 136 - description: JPEG quantization tables - fieldset: QMEM0_14 - name: QMEM0_14 - - byte_offset: 140 - description: JPEG quantization tables - fieldset: QMEM0_15 - name: QMEM0_15 - - byte_offset: 144 - description: JPEG quantization tables - fieldset: QMEM1_0 - name: QMEM1_0 - - byte_offset: 148 - description: JPEG quantization tables - fieldset: QMEM1_1 - name: QMEM1_1 - - byte_offset: 152 - description: JPEG quantization tables - fieldset: QMEM1_2 - name: QMEM1_2 - - byte_offset: 156 - description: JPEG quantization tables - fieldset: QMEM1_3 - name: QMEM1_3 - - byte_offset: 160 - description: JPEG quantization tables - fieldset: QMEM1_4 - name: QMEM1_4 - - byte_offset: 164 - description: JPEG quantization tables - fieldset: QMEM1_5 - name: QMEM1_5 - - byte_offset: 168 - description: JPEG quantization tables - fieldset: QMEM1_6 - name: QMEM1_6 - - byte_offset: 172 - description: JPEG quantization tables - fieldset: QMEM1_7 - name: QMEM1_7 - - byte_offset: 176 - description: JPEG quantization tables - fieldset: QMEM1_8 - name: QMEM1_8 - - byte_offset: 180 - description: JPEG quantization tables - fieldset: QMEM1_9 - name: QMEM1_9 - - byte_offset: 184 - description: JPEG quantization tables - fieldset: QMEM1_10 - name: QMEM1_10 - - byte_offset: 188 - description: JPEG quantization tables - fieldset: QMEM1_11 - name: QMEM1_11 - - byte_offset: 192 - description: JPEG quantization tables - fieldset: QMEM1_12 - name: QMEM1_12 - - byte_offset: 196 - description: JPEG quantization tables - fieldset: QMEM1_13 - name: QMEM1_13 - - byte_offset: 200 - description: JPEG quantization tables - fieldset: QMEM1_14 - name: QMEM1_14 - - byte_offset: 204 - description: JPEG quantization tables - fieldset: QMEM1_15 - name: QMEM1_15 - - byte_offset: 208 - description: JPEG quantization tables - fieldset: QMEM2_0 - name: QMEM2_0 - - byte_offset: 212 - description: JPEG quantization tables - fieldset: QMEM2_1 - name: QMEM2_1 - - byte_offset: 216 - description: JPEG quantization tables - fieldset: QMEM2_2 - name: QMEM2_2 - - byte_offset: 220 - description: JPEG quantization tables - fieldset: QMEM2_3 - name: QMEM2_3 - - byte_offset: 224 - description: JPEG quantization tables - fieldset: QMEM2_4 - name: QMEM2_4 - - byte_offset: 228 - description: JPEG quantization tables - fieldset: QMEM2_5 - name: QMEM2_5 - - byte_offset: 232 - description: JPEG quantization tables - fieldset: QMEM2_6 - name: QMEM2_6 - - byte_offset: 236 - description: JPEG quantization tables - fieldset: QMEM2_7 - name: QMEM2_7 - - byte_offset: 240 - description: JPEG quantization tables - fieldset: QMEM2_8 - name: QMEM2_8 - - byte_offset: 244 - description: JPEG quantization tables - fieldset: QMEM2_9 - name: QMEM2_9 - - byte_offset: 248 - description: JPEG quantization tables - fieldset: QMEM2_10 - name: QMEM2_10 - - byte_offset: 252 - description: JPEG quantization tables - fieldset: QMEM2_11 - name: QMEM2_11 - - byte_offset: 256 - description: JPEG quantization tables - fieldset: QMEM2_12 - name: QMEM2_12 - - byte_offset: 260 - description: JPEG quantization tables - fieldset: QMEM2_13 - name: QMEM2_13 - - byte_offset: 264 - description: JPEG quantization tables - fieldset: QMEM2_14 - name: QMEM2_14 - - byte_offset: 268 - description: JPEG quantization tables - fieldset: QMEM2_15 - name: QMEM2_15 - - byte_offset: 272 - description: JPEG quantization tables - fieldset: QMEM3_0 - name: QMEM3_0 - - byte_offset: 276 - description: JPEG quantization tables - fieldset: QMEM3_1 - name: QMEM3_1 - - byte_offset: 280 - description: JPEG quantization tables - fieldset: QMEM3_2 - name: QMEM3_2 - - byte_offset: 284 - description: JPEG quantization tables - fieldset: QMEM3_3 - name: QMEM3_3 - - byte_offset: 288 - description: JPEG quantization tables - fieldset: QMEM3_4 - name: QMEM3_4 - - byte_offset: 292 - description: JPEG quantization tables - fieldset: QMEM3_5 - name: QMEM3_5 - - byte_offset: 296 - description: JPEG quantization tables - fieldset: QMEM3_6 - name: QMEM3_6 - - byte_offset: 300 - description: JPEG quantization tables - fieldset: QMEM3_7 - name: QMEM3_7 - - byte_offset: 304 - description: JPEG quantization tables - fieldset: QMEM3_8 - name: QMEM3_8 - - byte_offset: 308 - description: JPEG quantization tables - fieldset: QMEM3_9 - name: QMEM3_9 - - byte_offset: 312 - description: JPEG quantization tables - fieldset: QMEM3_10 - name: QMEM3_10 - - byte_offset: 316 - description: JPEG quantization tables - fieldset: QMEM3_11 - name: QMEM3_11 - - byte_offset: 320 - description: JPEG quantization tables - fieldset: QMEM3_12 - name: QMEM3_12 - - byte_offset: 324 - description: JPEG quantization tables - fieldset: QMEM3_13 - name: QMEM3_13 - - byte_offset: 328 - description: JPEG quantization tables - fieldset: QMEM3_14 - name: QMEM3_14 - - byte_offset: 332 - description: JPEG quantization tables - fieldset: QMEM3_15 - name: QMEM3_15 - - byte_offset: 336 - description: JPEG HuffMin tables - fieldset: HUFFMIN_0 - name: HUFFMIN_0 - - byte_offset: 340 - description: JPEG HuffMin tables - fieldset: HUFFMIN_1 - name: HUFFMIN_1 - - byte_offset: 344 - description: JPEG HuffMin tables - fieldset: HUFFMIN_2 - name: HUFFMIN_2 - - byte_offset: 348 - description: JPEG HuffMin tables - fieldset: HUFFMIN_3 - name: HUFFMIN_3 - - byte_offset: 352 - description: JPEG HuffMin tables - fieldset: HUFFMIN_4 - name: HUFFMIN_4 - - byte_offset: 356 - description: JPEG HuffMin tables - fieldset: HUFFMIN_5 - name: HUFFMIN_5 - - byte_offset: 360 - description: JPEG HuffMin tables - fieldset: HUFFMIN_6 - name: HUFFMIN_6 - - byte_offset: 364 - description: JPEG HuffMin tables - fieldset: HUFFMIN_7 - name: HUFFMIN_7 - - byte_offset: 368 - description: JPEG HuffMin tables - fieldset: HUFFMIN_8 - name: HUFFMIN_8 - - byte_offset: 372 - description: JPEG HuffMin tables - fieldset: HUFFMIN_9 - name: HUFFMIN_9 - - byte_offset: 376 - description: JPEG HuffMin tables - fieldset: HUFFMIN_10 - name: HUFFMIN_10 - - byte_offset: 380 - description: JPEG HuffMin tables - fieldset: HUFFMIN_11 - name: HUFFMIN_11 - - byte_offset: 384 - description: JPEG HuffMin tables - fieldset: HUFFMIN_12 - name: HUFFMIN_12 - - byte_offset: 388 - description: JPEG HuffMin tables - fieldset: HUFFMIN_13 - name: HUFFMIN_13 - - byte_offset: 392 - description: JPEG HuffMin tables - fieldset: HUFFMIN_14 - name: HUFFMIN_14 - - byte_offset: 396 - description: JPEG HuffMin tables - fieldset: HUFFMIN_15 - name: HUFFMIN_15 - - byte_offset: 400 - description: JPEG HuffSymb tables - fieldset: HUFFBASE0 - name: HUFFBASE0 - - byte_offset: 404 - description: JPEG HuffSymb tables - fieldset: HUFFBASE1 - name: HUFFBASE1 - - byte_offset: 408 - description: JPEG HuffSymb tables - fieldset: HUFFBASE2 - name: HUFFBASE2 - - byte_offset: 412 - description: JPEG HuffSymb tables - fieldset: HUFFBASE3 - name: HUFFBASE3 - - byte_offset: 416 - description: JPEG HuffSymb tables - fieldset: HUFFBASE4 - name: HUFFBASE4 - - byte_offset: 420 - description: JPEG HuffSymb tables - fieldset: HUFFBASE5 - name: HUFFBASE5 - - byte_offset: 424 - description: JPEG HuffSymb tables - fieldset: HUFFBASE6 - name: HUFFBASE6 - - byte_offset: 428 - description: JPEG HuffSymb tables - fieldset: HUFFBASE7 - name: HUFFBASE7 - - byte_offset: 432 - description: JPEG HuffSymb tables - fieldset: HUFFBASE8 - name: HUFFBASE8 - - byte_offset: 436 - description: JPEG HuffSymb tables - fieldset: HUFFBASE9 - name: HUFFBASE9 - - byte_offset: 440 - description: JPEG HuffSymb tables - fieldset: HUFFBASE10 - name: HUFFBASE10 - - byte_offset: 444 - description: JPEG HuffSymb tables - fieldset: HUFFBASE11 - name: HUFFBASE11 - - byte_offset: 448 - description: JPEG HuffSymb tables - fieldset: HUFFBASE12 - name: HUFFBASE12 - - byte_offset: 452 - description: JPEG HuffSymb tables - fieldset: HUFFBASE13 - name: HUFFBASE13 - - byte_offset: 456 - description: JPEG HuffSymb tables - fieldset: HUFFBASE14 - name: HUFFBASE14 - - byte_offset: 460 - description: JPEG HuffSymb tables - fieldset: HUFFBASE15 - name: HUFFBASE15 - - byte_offset: 464 - description: JPEG HuffSymb tables - fieldset: HUFFBASE16 - name: HUFFBASE16 - - byte_offset: 468 - description: JPEG HuffSymb tables - fieldset: HUFFBASE17 - name: HUFFBASE17 - - byte_offset: 472 - description: JPEG HuffSymb tables - fieldset: HUFFBASE18 - name: HUFFBASE18 - - byte_offset: 476 - description: JPEG HuffSymb tables - fieldset: HUFFBASE19 - name: HUFFBASE19 - - byte_offset: 480 - description: JPEG HuffSymb tables - fieldset: HUFFBASE20 - name: HUFFBASE20 - - byte_offset: 484 - description: JPEG HuffSymb tables - fieldset: HUFFBASE21 - name: HUFFBASE21 - - byte_offset: 488 - description: JPEG HuffSymb tables - fieldset: HUFFBASE22 - name: HUFFBASE22 - - byte_offset: 492 - description: JPEG HuffSymb tables - fieldset: HUFFBASE23 - name: HUFFBASE23 - - byte_offset: 496 - description: JPEG HuffSymb tables - fieldset: HUFFBASE24 - name: HUFFBASE24 - - byte_offset: 500 - description: JPEG HuffSymb tables - fieldset: HUFFBASE25 - name: HUFFBASE25 - - byte_offset: 504 - description: JPEG HuffSymb tables - fieldset: HUFFBASE26 - name: HUFFBASE26 - - byte_offset: 508 - description: JPEG HuffSymb tables - fieldset: HUFFBASE27 - name: HUFFBASE27 - - byte_offset: 512 - description: JPEG HuffSymb tables - fieldset: HUFFBASE28 - name: HUFFBASE28 - - byte_offset: 516 - description: JPEG HuffSymb tables - fieldset: HUFFBASE29 - name: HUFFBASE29 - - byte_offset: 520 - description: JPEG HuffSymb tables - fieldset: HUFFBASE30 - name: HUFFBASE30 - - byte_offset: 524 - description: JPEG HuffSymb tables - fieldset: HUFFBASE31 - name: HUFFBASE31 - - byte_offset: 528 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB0 - name: HUFFSYMB0 - - byte_offset: 532 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB1 - name: HUFFSYMB1 - - byte_offset: 536 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB2 - name: HUFFSYMB2 - - byte_offset: 540 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB3 - name: HUFFSYMB3 - - byte_offset: 544 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB4 - name: HUFFSYMB4 - - byte_offset: 548 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB5 - name: HUFFSYMB5 - - byte_offset: 552 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB6 - name: HUFFSYMB6 - - byte_offset: 556 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB7 - name: HUFFSYMB7 - - byte_offset: 560 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB8 - name: HUFFSYMB8 - - byte_offset: 564 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB9 - name: HUFFSYMB9 - - byte_offset: 568 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB10 - name: HUFFSYMB10 - - byte_offset: 572 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB11 - name: HUFFSYMB11 - - byte_offset: 576 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB12 - name: HUFFSYMB12 - - byte_offset: 580 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB13 - name: HUFFSYMB13 - - byte_offset: 584 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB14 - name: HUFFSYMB14 - - byte_offset: 588 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB15 - name: HUFFSYMB15 - - byte_offset: 592 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB16 - name: HUFFSYMB16 - - byte_offset: 596 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB17 - name: HUFFSYMB17 - - byte_offset: 600 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB18 - name: HUFFSYMB18 - - byte_offset: 604 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB19 - name: HUFFSYMB19 - - byte_offset: 608 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB20 - name: HUFFSYMB20 - - byte_offset: 612 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB21 - name: HUFFSYMB21 - - byte_offset: 616 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB22 - name: HUFFSYMB22 - - byte_offset: 620 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB23 - name: HUFFSYMB23 - - byte_offset: 624 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB24 - name: HUFFSYMB24 - - byte_offset: 628 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB25 - name: HUFFSYMB25 - - byte_offset: 632 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB26 - name: HUFFSYMB26 - - byte_offset: 636 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB27 - name: HUFFSYMB27 - - byte_offset: 640 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB28 - name: HUFFSYMB28 - - byte_offset: 644 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB29 - name: HUFFSYMB29 - - byte_offset: 648 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB30 - name: HUFFSYMB30 - - byte_offset: 652 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB31 - name: HUFFSYMB31 - - byte_offset: 656 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB32 - name: HUFFSYMB32 - - byte_offset: 660 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB33 - name: HUFFSYMB33 - - byte_offset: 664 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB34 - name: HUFFSYMB34 - - byte_offset: 668 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB35 - name: HUFFSYMB35 - - byte_offset: 672 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB36 - name: HUFFSYMB36 - - byte_offset: 676 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB37 - name: HUFFSYMB37 - - byte_offset: 680 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB38 - name: HUFFSYMB38 - - byte_offset: 684 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB39 - name: HUFFSYMB39 - - byte_offset: 688 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB40 - name: HUFFSYMB40 - - byte_offset: 692 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB41 - name: HUFFSYMB41 - - byte_offset: 696 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB42 - name: HUFFSYMB42 - - byte_offset: 700 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB43 - name: HUFFSYMB43 - - byte_offset: 704 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB44 - name: HUFFSYMB44 - - byte_offset: 708 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB45 - name: HUFFSYMB45 - - byte_offset: 712 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB46 - name: HUFFSYMB46 - - byte_offset: 716 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB47 - name: HUFFSYMB47 - - byte_offset: 720 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB48 - name: HUFFSYMB48 - - byte_offset: 724 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB49 - name: HUFFSYMB49 - - byte_offset: 728 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB50 - name: HUFFSYMB50 - - byte_offset: 732 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB51 - name: HUFFSYMB51 - - byte_offset: 736 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB52 - name: HUFFSYMB52 - - byte_offset: 740 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB53 - name: HUFFSYMB53 - - byte_offset: 744 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB54 - name: HUFFSYMB54 - - byte_offset: 748 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB55 - name: HUFFSYMB55 - - byte_offset: 752 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB56 - name: HUFFSYMB56 - - byte_offset: 756 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB57 - name: HUFFSYMB57 - - byte_offset: 760 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB58 - name: HUFFSYMB58 - - byte_offset: 764 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB59 - name: HUFFSYMB59 - - byte_offset: 768 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB60 - name: HUFFSYMB60 - - byte_offset: 772 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB61 - name: HUFFSYMB61 - - byte_offset: 776 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB62 - name: HUFFSYMB62 - - byte_offset: 780 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB63 - name: HUFFSYMB63 - - byte_offset: 784 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB64 - name: HUFFSYMB64 - - byte_offset: 788 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB65 - name: HUFFSYMB65 - - byte_offset: 792 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB66 - name: HUFFSYMB66 - - byte_offset: 796 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB67 - name: HUFFSYMB67 - - byte_offset: 800 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB68 - name: HUFFSYMB68 - - byte_offset: 804 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB69 - name: HUFFSYMB69 - - byte_offset: 808 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB70 - name: HUFFSYMB70 - - byte_offset: 812 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB71 - name: HUFFSYMB71 - - byte_offset: 816 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB72 - name: HUFFSYMB72 - - byte_offset: 820 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB73 - name: HUFFSYMB73 - - byte_offset: 824 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB74 - name: HUFFSYMB74 - - byte_offset: 828 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB75 - name: HUFFSYMB75 - - byte_offset: 832 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB76 - name: HUFFSYMB76 - - byte_offset: 836 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB77 - name: HUFFSYMB77 - - byte_offset: 840 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB78 - name: HUFFSYMB78 - - byte_offset: 844 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB79 - name: HUFFSYMB79 - - byte_offset: 848 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB80 - name: HUFFSYMB80 - - byte_offset: 852 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB81 - name: HUFFSYMB81 - - byte_offset: 856 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB82 - name: HUFFSYMB82 - - byte_offset: 860 - description: JPEG HUFFSYMB tables - fieldset: HUFFSYMB83 - name: HUFFSYMB83 - - byte_offset: 864 - description: JPEG DHTMem tables - fieldset: DHTMEM0 - name: DHTMEM0 - - byte_offset: 868 - description: JPEG DHTMem tables - fieldset: DHTMEM2 - name: DHTMEM2 - - byte_offset: 872 - description: JPEG DHTMem tables - fieldset: DHTMEM3 - name: DHTMEM3 - - byte_offset: 876 - description: JPEG DHTMem tables - fieldset: DHTMEM4 - name: DHTMEM4 - - byte_offset: 880 - description: JPEG DHTMem tables - fieldset: DHTMEM5 - name: DHTMEM5 - - byte_offset: 884 - description: JPEG DHTMem tables - fieldset: DHTMEM6 - name: DHTMEM6 - - byte_offset: 888 - description: JPEG DHTMem tables - fieldset: DHTMEM7 - name: DHTMEM7 - - byte_offset: 892 - description: JPEG DHTMem tables - fieldset: DHTMEM8 - name: DHTMEM8 - - byte_offset: 896 - description: JPEG DHTMem tables - fieldset: DHTMEM9 - name: DHTMEM9 - - byte_offset: 900 - description: JPEG DHTMem tables - fieldset: DHTMEM10 - name: DHTMEM10 - - byte_offset: 904 - description: JPEG DHTMem tables - fieldset: DHTMEM11 - name: DHTMEM11 - - byte_offset: 908 - description: JPEG DHTMem tables - fieldset: DHTMEM12 - name: DHTMEM12 - - byte_offset: 912 - description: JPEG DHTMem tables - fieldset: DHTMEM13 - name: DHTMEM13 - - byte_offset: 916 - description: JPEG DHTMem tables - fieldset: DHTMEM14 - name: DHTMEM14 - - byte_offset: 920 - description: JPEG DHTMem tables - fieldset: DHTMEM15 - name: DHTMEM15 - - byte_offset: 924 - description: JPEG DHTMem tables - fieldset: DHTMEM16 - name: DHTMEM16 - - byte_offset: 928 - description: JPEG DHTMem tables - fieldset: DHTMEM17 - name: DHTMEM17 - - byte_offset: 932 - description: JPEG DHTMem tables - fieldset: DHTMEM18 - name: DHTMEM18 - - byte_offset: 936 - description: JPEG DHTMem tables - fieldset: DHTMEM19 - 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fieldset: DHTMEM30 - name: DHTMEM30 - - byte_offset: 984 - description: JPEG DHTMem tables - fieldset: DHTMEM31 - name: DHTMEM31 - - byte_offset: 988 - description: JPEG DHTMem tables - fieldset: DHTMEM32 - name: DHTMEM32 - - byte_offset: 992 - description: JPEG DHTMem tables - fieldset: DHTMEM33 - name: DHTMEM33 - - byte_offset: 996 - description: JPEG DHTMem tables - fieldset: DHTMEM34 - name: DHTMEM34 - - byte_offset: 1000 - description: JPEG DHTMem tables - fieldset: DHTMEM35 - name: DHTMEM35 - - byte_offset: 1004 - description: JPEG DHTMem tables - fieldset: DHTMEM36 - name: DHTMEM36 - - byte_offset: 1008 - description: JPEG DHTMem tables - fieldset: DHTMEM37 - name: DHTMEM37 - - byte_offset: 1012 - description: JPEG DHTMem tables - fieldset: DHTMEM38 - name: DHTMEM38 - - byte_offset: 1016 - description: JPEG DHTMem tables - fieldset: DHTMEM39 - name: DHTMEM39 - - byte_offset: 1020 - description: JPEG DHTMem tables - fieldset: DHTMEM40 - name: DHTMEM40 - - byte_offset: 1024 - description: JPEG DHTMem tables - fieldset: DHTMEM41 - name: DHTMEM41 - - byte_offset: 1028 - description: JPEG DHTMem tables - fieldset: DHTMEM42 - name: DHTMEM42 - - byte_offset: 1032 - description: JPEG DHTMem tables - fieldset: DHTMEM43 - name: DHTMEM43 - - byte_offset: 1036 - description: JPEG DHTMem tables - fieldset: DHTMEM44 - name: DHTMEM44 - - byte_offset: 1040 - description: JPEG DHTMem tables - fieldset: DHTMEM45 - name: DHTMEM45 - - byte_offset: 1044 - description: JPEG DHTMem tables - fieldset: DHTMEM46 - name: DHTMEM46 - - byte_offset: 1048 - description: JPEG DHTMem tables - fieldset: DHTMEM47 - name: DHTMEM47 - - byte_offset: 1052 - description: JPEG DHTMem tables - fieldset: DHTMEM48 - name: DHTMEM48 - - byte_offset: 1056 - description: JPEG DHTMem tables - fieldset: DHTMEM49 - name: DHTMEM49 - - byte_offset: 1060 - description: JPEG DHTMem tables - fieldset: DHTMEM50 - name: DHTMEM50 - - byte_offset: 1064 - description: JPEG DHTMem tables - fieldset: DHTMEM51 - name: DHTMEM51 - - byte_offset: 1068 - description: JPEG DHTMem tables - fieldset: DHTMEM52 - name: DHTMEM52 - - byte_offset: 1072 - description: JPEG DHTMem tables - fieldset: DHTMEM53 - name: DHTMEM53 - - byte_offset: 1076 - description: JPEG DHTMem tables - fieldset: DHTMEM54 - name: DHTMEM54 - - byte_offset: 1080 - description: JPEG DHTMem tables - fieldset: DHTMEM55 - name: DHTMEM55 - - byte_offset: 1084 - description: JPEG DHTMem tables - fieldset: DHTMEM56 - name: DHTMEM56 - - byte_offset: 1088 - description: JPEG DHTMem tables - fieldset: DHTMEM57 - name: DHTMEM57 - - byte_offset: 1092 - description: JPEG DHTMem tables - fieldset: DHTMEM58 - name: DHTMEM58 - - byte_offset: 1096 - description: JPEG DHTMem tables - fieldset: DHTMEM59 - name: DHTMEM59 - - byte_offset: 1100 - description: JPEG DHTMem tables - fieldset: DHTMEM60 - name: DHTMEM60 - - byte_offset: 1104 - description: JPEG DHTMem tables - fieldset: DHTMEM61 - name: DHTMEM61 - - byte_offset: 1108 - description: JPEG DHTMem tables - fieldset: DHTMEM62 - name: DHTMEM62 - - byte_offset: 1112 - description: JPEG DHTMem tables - fieldset: DHTMEM63 - name: DHTMEM63 - - byte_offset: 1116 - description: JPEG DHTMem tables - fieldset: DHTMEM64 - name: DHTMEM64 - - byte_offset: 1120 - description: JPEG DHTMem tables - fieldset: DHTMEM65 - name: DHTMEM65 - - byte_offset: 1124 - description: JPEG DHTMem tables - fieldset: DHTMEM66 - name: DHTMEM66 - - byte_offset: 1128 - description: JPEG DHTMem tables - fieldset: DHTMEM67 - name: DHTMEM67 - - byte_offset: 1132 - description: JPEG DHTMem tables - fieldset: DHTMEM68 - name: DHTMEM68 - - byte_offset: 1136 - description: JPEG DHTMem tables - fieldset: DHTMEM69 - name: DHTMEM69 - - byte_offset: 1140 - description: JPEG DHTMem tables - fieldset: DHTMEM70 - name: DHTMEM70 - - byte_offset: 1144 - description: JPEG DHTMem tables - fieldset: DHTMEM71 - name: DHTMEM71 - - byte_offset: 1148 - description: JPEG DHTMem tables - fieldset: DHTMEM72 - name: DHTMEM72 - - byte_offset: 1152 - description: JPEG DHTMem tables - fieldset: DHTMEM73 - name: DHTMEM73 - - byte_offset: 1156 - description: JPEG DHTMem tables - fieldset: DHTMEM74 - name: DHTMEM74 - - byte_offset: 1160 - description: JPEG DHTMem tables - fieldset: DHTMEM75 - name: DHTMEM75 - - byte_offset: 1164 - description: JPEG DHTMem tables - fieldset: DHTMEM76 - name: DHTMEM76 - - byte_offset: 1168 - description: JPEG DHTMem tables - fieldset: DHTMEM77 - name: DHTMEM77 - - byte_offset: 1172 - description: JPEG DHTMem tables - fieldset: DHTMEM78 - name: DHTMEM78 - - byte_offset: 1176 - description: JPEG DHTMem tables - fieldset: DHTMEM79 - name: DHTMEM79 - - byte_offset: 1180 - description: JPEG DHTMem tables - fieldset: DHTMEM80 - name: DHTMEM80 - - byte_offset: 1184 - description: JPEG DHTMem tables - fieldset: DHTMEM81 - name: DHTMEM81 - - byte_offset: 1188 - description: JPEG DHTMem tables - fieldset: DHTMEM82 - name: DHTMEM82 - - byte_offset: 1192 - description: JPEG DHTMem tables - fieldset: DHTMEM83 - name: DHTMEM83 - - byte_offset: 1196 - description: JPEG DHTMem tables - fieldset: DHTMEM84 - name: DHTMEM84 - - byte_offset: 1200 - description: JPEG DHTMem tables - fieldset: DHTMEM85 - name: DHTMEM85 - - byte_offset: 1204 - description: JPEG DHTMem tables - fieldset: DHTMEM86 - name: DHTMEM86 - - byte_offset: 1208 - description: JPEG DHTMem tables - fieldset: DHTMEM87 - name: DHTMEM87 - - byte_offset: 1212 - description: JPEG DHTMem tables - fieldset: DHTMEM88 - name: DHTMEM88 - - byte_offset: 1216 - description: JPEG DHTMem tables - fieldset: DHTMEM89 - name: DHTMEM89 - - byte_offset: 1220 - description: JPEG DHTMem tables - fieldset: DHTMEM90 - name: DHTMEM90 - - byte_offset: 1224 - description: JPEG DHTMem tables - fieldset: DHTMEM91 - name: DHTMEM91 - - byte_offset: 1228 - description: JPEG DHTMem tables - fieldset: DHTMEM92 - name: DHTMEM92 - - byte_offset: 1232 - description: JPEG DHTMem tables - fieldset: DHTMEM93 - name: DHTMEM93 - - byte_offset: 1236 - description: JPEG DHTMem tables - fieldset: DHTMEM94 - name: DHTMEM94 - - byte_offset: 1240 - description: JPEG DHTMem tables - fieldset: DHTMEM95 - name: DHTMEM95 - - byte_offset: 1244 - description: JPEG DHTMem tables - fieldset: DHTMEM96 - name: DHTMEM96 - - byte_offset: 1248 - description: JPEG DHTMem tables - fieldset: DHTMEM97 - name: DHTMEM97 - - byte_offset: 1252 - description: JPEG DHTMem tables - fieldset: DHTMEM98 - name: DHTMEM98 - - byte_offset: 1256 - description: JPEG DHTMem tables - fieldset: DHTMEM99 - name: DHTMEM99 - - byte_offset: 1260 - description: JPEG DHTMem tables - fieldset: DHTMEM100 - name: DHTMEM100 - - byte_offset: 1264 - description: JPEG DHTMem tables - fieldset: DHTMEM101 - name: DHTMEM101 - - byte_offset: 1268 - description: JPEG DHTMem tables - fieldset: DHTMEM102 - name: DHTMEM102 - - byte_offset: 1272 - description: JPEG DHTMem tables - fieldset: DHTMEM103 - name: DHTMEM103 - - byte_offset: 1280 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_0 - name: HUFFENC_AC0_0 - - byte_offset: 1284 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_1 - name: HUFFENC_AC0_1 - - byte_offset: 1288 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_2 - name: HUFFENC_AC0_2 - - byte_offset: 1292 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_3 - name: HUFFENC_AC0_3 - - byte_offset: 1296 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_4 - name: HUFFENC_AC0_4 - - byte_offset: 1300 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_5 - name: HUFFENC_AC0_5 - - byte_offset: 1304 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_6 - name: HUFFENC_AC0_6 - - byte_offset: 1308 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_7 - name: HUFFENC_AC0_7 - - byte_offset: 1312 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_8 - name: HUFFENC_AC0_8 - - byte_offset: 1316 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_9 - name: HUFFENC_AC0_9 - - byte_offset: 1320 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_10 - name: HUFFENC_AC0_10 - - byte_offset: 1324 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_11 - name: HUFFENC_AC0_11 - - byte_offset: 1328 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_12 - name: HUFFENC_AC0_12 - - byte_offset: 1332 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_13 - name: HUFFENC_AC0_13 - - byte_offset: 1336 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_14 - name: HUFFENC_AC0_14 - - byte_offset: 1340 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_15 - name: HUFFENC_AC0_15 - - byte_offset: 1344 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_16 - name: HUFFENC_AC0_16 - - byte_offset: 1348 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_17 - name: HUFFENC_AC0_17 - - byte_offset: 1352 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_18 - name: HUFFENC_AC0_18 - - byte_offset: 1356 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_19 - name: HUFFENC_AC0_19 - - byte_offset: 1360 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_20 - name: HUFFENC_AC0_20 - - byte_offset: 1364 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_21 - name: HUFFENC_AC0_21 - - byte_offset: 1368 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_22 - name: HUFFENC_AC0_22 - - byte_offset: 1372 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_23 - name: HUFFENC_AC0_23 - - byte_offset: 1376 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_24 - name: HUFFENC_AC0_24 - - byte_offset: 1380 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_25 - name: HUFFENC_AC0_25 - - byte_offset: 1384 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_26 - name: HUFFENC_AC0_26 - - byte_offset: 1388 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_27 - name: HUFFENC_AC0_27 - - byte_offset: 1392 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_28 - name: HUFFENC_AC0_28 - - byte_offset: 1396 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_29 - name: HUFFENC_AC0_29 - - byte_offset: 1400 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_30 - name: HUFFENC_AC0_30 - - byte_offset: 1404 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_31 - name: HUFFENC_AC0_31 - - byte_offset: 1408 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_32 - name: HUFFENC_AC0_32 - - byte_offset: 1412 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_33 - name: HUFFENC_AC0_33 - - byte_offset: 1416 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_34 - name: HUFFENC_AC0_34 - - byte_offset: 1420 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_35 - name: HUFFENC_AC0_35 - - byte_offset: 1424 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_36 - name: HUFFENC_AC0_36 - - byte_offset: 1428 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_37 - name: HUFFENC_AC0_37 - - byte_offset: 1432 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_38 - name: HUFFENC_AC0_38 - - byte_offset: 1436 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_39 - name: HUFFENC_AC0_39 - - byte_offset: 1440 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_40 - name: HUFFENC_AC0_40 - - byte_offset: 1444 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_41 - name: HUFFENC_AC0_41 - - byte_offset: 1448 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_42 - name: HUFFENC_AC0_42 - - byte_offset: 1452 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_43 - name: HUFFENC_AC0_43 - - byte_offset: 1456 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_44 - name: HUFFENC_AC0_44 - - byte_offset: 1460 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_45 - name: HUFFENC_AC0_45 - - byte_offset: 1464 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_46 - name: HUFFENC_AC0_46 - - byte_offset: 1468 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_47 - name: HUFFENC_AC0_47 - - byte_offset: 1472 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_48 - name: HUFFENC_AC0_48 - - byte_offset: 1476 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_49 - name: HUFFENC_AC0_49 - - byte_offset: 1480 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_50 - name: HUFFENC_AC0_50 - - byte_offset: 1484 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_51 - name: HUFFENC_AC0_51 - - byte_offset: 1488 - description: JPEG encoder, AC Huffman table 0 - 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- byte_offset: 1524 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_61 - name: HUFFENC_AC0_61 - - byte_offset: 1528 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_62 - name: HUFFENC_AC0_62 - - byte_offset: 1532 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_63 - name: HUFFENC_AC0_63 - - byte_offset: 1536 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_64 - name: HUFFENC_AC0_64 - - byte_offset: 1540 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_65 - name: HUFFENC_AC0_65 - - byte_offset: 1544 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_66 - name: HUFFENC_AC0_66 - - byte_offset: 1548 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_67 - name: HUFFENC_AC0_67 - - byte_offset: 1552 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_68 - name: HUFFENC_AC0_68 - - byte_offset: 1556 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_69 - name: HUFFENC_AC0_69 - - byte_offset: 1560 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_70 - name: HUFFENC_AC0_70 - - byte_offset: 1564 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_71 - name: HUFFENC_AC0_71 - - byte_offset: 1568 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_72 - name: HUFFENC_AC0_72 - - byte_offset: 1572 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_73 - name: HUFFENC_AC0_73 - - byte_offset: 1576 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_74 - name: HUFFENC_AC0_74 - - byte_offset: 1580 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_75 - name: HUFFENC_AC0_75 - - byte_offset: 1584 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_76 - name: HUFFENC_AC0_76 - - byte_offset: 1588 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_77 - name: HUFFENC_AC0_77 - - byte_offset: 1592 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_78 - name: HUFFENC_AC0_78 - - byte_offset: 1596 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_79 - name: HUFFENC_AC0_79 - - byte_offset: 1600 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_80 - name: HUFFENC_AC0_80 - - byte_offset: 1604 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_81 - name: HUFFENC_AC0_81 - - byte_offset: 1608 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_82 - name: HUFFENC_AC0_82 - - byte_offset: 1612 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_83 - name: HUFFENC_AC0_83 - - byte_offset: 1616 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_84 - name: HUFFENC_AC0_84 - - byte_offset: 1620 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_85 - name: HUFFENC_AC0_85 - - byte_offset: 1624 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_86 - name: HUFFENC_AC0_86 - - byte_offset: 1628 - description: JPEG encoder, AC Huffman table 0 - fieldset: HUFFENC_AC0_87 - name: HUFFENC_AC0_87 - - byte_offset: 1632 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_0 - name: HUFFENC_AC1_0 - - byte_offset: 1636 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_1 - name: HUFFENC_AC1_1 - - byte_offset: 1640 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_2 - name: HUFFENC_AC1_2 - - byte_offset: 1644 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_3 - name: HUFFENC_AC1_3 - - byte_offset: 1648 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_4 - name: HUFFENC_AC1_4 - - byte_offset: 1652 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_5 - name: HUFFENC_AC1_5 - - byte_offset: 1656 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_6 - name: HUFFENC_AC1_6 - - byte_offset: 1660 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_7 - name: HUFFENC_AC1_7 - - byte_offset: 1664 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_8 - name: HUFFENC_AC1_8 - - byte_offset: 1668 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_9 - name: HUFFENC_AC1_9 - - byte_offset: 1672 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_10 - name: HUFFENC_AC1_10 - - byte_offset: 1676 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_11 - name: HUFFENC_AC1_11 - - byte_offset: 1680 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_12 - name: HUFFENC_AC1_12 - - byte_offset: 1684 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_13 - name: HUFFENC_AC1_13 - - byte_offset: 1688 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_14 - name: HUFFENC_AC1_14 - - byte_offset: 1692 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_15 - name: HUFFENC_AC1_15 - - byte_offset: 1696 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_16 - name: HUFFENC_AC1_16 - - byte_offset: 1700 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_17 - name: HUFFENC_AC1_17 - - byte_offset: 1704 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_18 - name: HUFFENC_AC1_18 - - byte_offset: 1708 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_19 - name: HUFFENC_AC1_19 - - byte_offset: 1712 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_20 - name: HUFFENC_AC1_20 - - byte_offset: 1716 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_21 - name: HUFFENC_AC1_21 - - byte_offset: 1720 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_22 - name: HUFFENC_AC1_22 - - byte_offset: 1724 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_23 - name: HUFFENC_AC1_23 - - byte_offset: 1728 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_24 - name: HUFFENC_AC1_24 - - byte_offset: 1732 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_25 - name: HUFFENC_AC1_25 - - byte_offset: 1736 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_26 - name: HUFFENC_AC1_26 - - byte_offset: 1740 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_27 - name: HUFFENC_AC1_27 - - byte_offset: 1744 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_28 - name: HUFFENC_AC1_28 - - byte_offset: 1748 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_29 - name: HUFFENC_AC1_29 - - byte_offset: 1752 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_30 - name: HUFFENC_AC1_30 - - byte_offset: 1756 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_31 - name: HUFFENC_AC1_31 - - byte_offset: 1760 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_32 - name: HUFFENC_AC1_32 - - byte_offset: 1764 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_33 - name: HUFFENC_AC1_33 - - byte_offset: 1768 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_34 - name: HUFFENC_AC1_34 - - byte_offset: 1772 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_35 - name: HUFFENC_AC1_35 - - byte_offset: 1776 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_36 - name: HUFFENC_AC1_36 - - byte_offset: 1780 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_37 - name: HUFFENC_AC1_37 - - byte_offset: 1784 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_38 - name: HUFFENC_AC1_38 - - byte_offset: 1788 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_39 - name: HUFFENC_AC1_39 - - byte_offset: 1792 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_40 - name: HUFFENC_AC1_40 - - byte_offset: 1796 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_41 - name: HUFFENC_AC1_41 - - byte_offset: 1800 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_42 - name: HUFFENC_AC1_42 - - byte_offset: 1804 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_43 - name: HUFFENC_AC1_43 - - byte_offset: 1808 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_44 - name: HUFFENC_AC1_44 - - byte_offset: 1812 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_45 - name: HUFFENC_AC1_45 - - byte_offset: 1816 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_46 - name: HUFFENC_AC1_46 - - byte_offset: 1820 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_47 - name: HUFFENC_AC1_47 - - byte_offset: 1824 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_48 - name: HUFFENC_AC1_48 - - byte_offset: 1828 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_49 - name: HUFFENC_AC1_49 - - byte_offset: 1832 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_50 - name: HUFFENC_AC1_50 - - byte_offset: 1836 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_51 - name: HUFFENC_AC1_51 - - byte_offset: 1840 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_52 - name: HUFFENC_AC1_52 - - byte_offset: 1844 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_53 - name: HUFFENC_AC1_53 - - byte_offset: 1848 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_54 - name: HUFFENC_AC1_54 - - byte_offset: 1852 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_55 - name: HUFFENC_AC1_55 - - byte_offset: 1856 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_56 - name: HUFFENC_AC1_56 - - byte_offset: 1860 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_57 - name: HUFFENC_AC1_57 - - byte_offset: 1864 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_58 - name: HUFFENC_AC1_58 - - byte_offset: 1868 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_59 - name: HUFFENC_AC1_59 - - byte_offset: 1872 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_60 - name: HUFFENC_AC1_60 - - byte_offset: 1876 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_61 - name: HUFFENC_AC1_61 - - byte_offset: 1880 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_62 - name: HUFFENC_AC1_62 - - byte_offset: 1884 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_63 - name: HUFFENC_AC1_63 - - byte_offset: 1888 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_64 - name: HUFFENC_AC1_64 - - byte_offset: 1892 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_65 - name: HUFFENC_AC1_65 - - byte_offset: 1896 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_66 - name: HUFFENC_AC1_66 - - byte_offset: 1900 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_67 - name: HUFFENC_AC1_67 - - byte_offset: 1904 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_68 - name: HUFFENC_AC1_68 - - byte_offset: 1908 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_69 - name: HUFFENC_AC1_69 - - byte_offset: 1912 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_70 - name: HUFFENC_AC1_70 - - byte_offset: 1916 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_71 - name: HUFFENC_AC1_71 - - byte_offset: 1920 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_72 - name: HUFFENC_AC1_72 - - byte_offset: 1924 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_73 - name: HUFFENC_AC1_73 - - byte_offset: 1928 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_74 - name: HUFFENC_AC1_74 - - byte_offset: 1932 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_75 - name: HUFFENC_AC1_75 - - byte_offset: 1936 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_76 - name: HUFFENC_AC1_76 - - byte_offset: 1940 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_77 - name: HUFFENC_AC1_77 - - byte_offset: 1944 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_78 - name: HUFFENC_AC1_78 - - byte_offset: 1948 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_79 - name: HUFFENC_AC1_79 - - byte_offset: 1952 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_80 - name: HUFFENC_AC1_80 - - byte_offset: 1956 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_81 - name: HUFFENC_AC1_81 - - byte_offset: 1960 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_82 - name: HUFFENC_AC1_82 - - byte_offset: 1964 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_83 - name: HUFFENC_AC1_83 - - byte_offset: 1968 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_84 - name: HUFFENC_AC1_84 - - byte_offset: 1972 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_85 - name: HUFFENC_AC1_85 - - byte_offset: 1976 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_86 - name: HUFFENC_AC1_86 - - byte_offset: 1980 - description: JPEG encoder, AC Huffman table 1 - fieldset: HUFFENC_AC1_87 - name: HUFFENC_AC1_87 - - byte_offset: 1984 - description: JPEG encoder, DC Huffman table 0 - fieldset: HUFFENC_DC0_0 - name: HUFFENC_DC0_0 - - byte_offset: 1988 - description: JPEG encoder, DC Huffman table 0 - fieldset: HUFFENC_DC0_1 - name: HUFFENC_DC0_1 - - byte_offset: 1992 - description: JPEG encoder, DC Huffman table 0 - fieldset: HUFFENC_DC0_2 - name: HUFFENC_DC0_2 - - byte_offset: 1996 - description: JPEG encoder, DC Huffman table 0 - fieldset: HUFFENC_DC0_3 - name: HUFFENC_DC0_3 - - byte_offset: 2000 - description: JPEG encoder, DC Huffman table 0 - fieldset: HUFFENC_DC0_4 - name: HUFFENC_DC0_4 - - byte_offset: 2004 - description: JPEG encoder, DC Huffman table 0 - fieldset: HUFFENC_DC0_5 - name: HUFFENC_DC0_5 - - byte_offset: 2008 - description: JPEG encoder, DC Huffman table 0 - fieldset: HUFFENC_DC0_6 - name: HUFFENC_DC0_6 - - byte_offset: 2012 - description: JPEG encoder, DC Huffman table 0 - fieldset: HUFFENC_DC0_7 - name: HUFFENC_DC0_7 - - byte_offset: 2016 - description: JPEG encoder, DC Huffman table 1 - fieldset: HUFFENC_DC1_0 - name: HUFFENC_DC1_0 - - byte_offset: 2020 - description: JPEG encoder, DC Huffman table 1 - fieldset: HUFFENC_DC1_1 - name: HUFFENC_DC1_1 - - byte_offset: 2024 - description: JPEG encoder, DC Huffman table 1 - fieldset: HUFFENC_DC1_2 - name: HUFFENC_DC1_2 - - byte_offset: 2028 - description: JPEG encoder, DC Huffman table 1 - fieldset: HUFFENC_DC1_3 - name: HUFFENC_DC1_3 - - byte_offset: 2032 - description: JPEG encoder, DC Huffman table 1 - fieldset: HUFFENC_DC1_4 - name: HUFFENC_DC1_4 - - byte_offset: 2036 - description: JPEG encoder, DC Huffman table 1 - fieldset: HUFFENC_DC1_5 - name: HUFFENC_DC1_5 - - byte_offset: 2040 - description: JPEG encoder, DC Huffman table 1 - fieldset: HUFFENC_DC1_6 - name: HUFFENC_DC1_6 - - byte_offset: 2044 - description: JPEG encoder, DC Huffman table 1 - fieldset: HUFFENC_DC1_7 - name: HUFFENC_DC1_7 + - name: JPEG_CONFR0 + description: JPEG codec configuration register 0 + byte_offset: 0 + access: Write + fieldset: JPEG_CONFR0 + - name: JPEG_CONFR1 + description: JPEG codec configuration register 1 + byte_offset: 4 + fieldset: JPEG_CONFR1 + - name: JPEG_CONFR2 + description: JPEG codec configuration register 2 + byte_offset: 8 + fieldset: JPEG_CONFR2 + - name: JPEG_CONFR3 + description: JPEG codec configuration register 3 + byte_offset: 12 + fieldset: JPEG_CONFR3 + - name: JPEG_CONFR4 + description: JPEG codec configuration register 4 + byte_offset: 16 + fieldset: JPEG_CONFR4 + - name: JPEG_CONFR5 + description: JPEG codec configuration register 5 + byte_offset: 20 + fieldset: JPEG_CONFR5 + - name: JPEG_CONFR6 + description: JPEG codec configuration register 6 + byte_offset: 24 + fieldset: JPEG_CONFR6 + - name: JPEG_CONFR7 + description: JPEG codec configuration register 7 + byte_offset: 28 + fieldset: JPEG_CONFR7 + - name: JPEG_CR + description: JPEG control register + byte_offset: 48 + fieldset: JPEG_CR + - name: JPEG_SR + description: JPEG status register + byte_offset: 52 + access: Read + fieldset: JPEG_SR + - name: JPEG_CFR + description: JPEG clear flag register + byte_offset: 56 + access: Write + fieldset: JPEG_CFR + - name: JPEG_DIR + description: JPEG data input register + byte_offset: 64 + access: Write + fieldset: JPEG_DIR + - name: JPEG_DOR + description: JPEG data output register + byte_offset: 68 + access: Read + fieldset: JPEG_DOR + - name: QMEM0_0 + description: JPEG quantization tables + byte_offset: 80 + fieldset: QMEM0_0 + - name: QMEM0_1 + description: JPEG quantization tables + byte_offset: 84 + fieldset: QMEM0_1 + - name: QMEM0_2 + description: JPEG quantization tables + byte_offset: 88 + fieldset: QMEM0_2 + - name: QMEM0_3 + description: JPEG quantization tables + byte_offset: 92 + fieldset: QMEM0_3 + - name: QMEM0_4 + description: JPEG quantization tables + byte_offset: 96 + fieldset: QMEM0_4 + - name: QMEM0_5 + description: JPEG quantization tables + byte_offset: 100 + fieldset: QMEM0_5 + - name: QMEM0_6 + description: JPEG quantization tables + byte_offset: 104 + fieldset: QMEM0_6 + - name: QMEM0_7 + description: JPEG quantization tables + byte_offset: 108 + fieldset: QMEM0_7 + - name: QMEM0_8 + description: JPEG quantization tables + byte_offset: 112 + fieldset: QMEM0_8 + - name: QMEM0_9 + description: JPEG quantization tables + byte_offset: 116 + fieldset: QMEM0_9 + - name: QMEM0_10 + description: JPEG quantization tables + byte_offset: 120 + fieldset: QMEM0_10 + - name: QMEM0_11 + description: JPEG quantization tables + byte_offset: 124 + fieldset: QMEM0_11 + - name: QMEM0_12 + description: JPEG quantization tables + byte_offset: 128 + fieldset: QMEM0_12 + - name: QMEM0_13 + description: JPEG quantization tables + byte_offset: 132 + fieldset: QMEM0_13 + - name: QMEM0_14 + description: JPEG quantization tables + byte_offset: 136 + fieldset: QMEM0_14 + - name: QMEM0_15 + description: JPEG quantization tables + byte_offset: 140 + fieldset: QMEM0_15 + - name: QMEM1_0 + description: JPEG quantization tables + byte_offset: 144 + fieldset: QMEM1_0 + - name: QMEM1_1 + description: JPEG quantization tables + byte_offset: 148 + fieldset: QMEM1_1 + - name: QMEM1_2 + description: JPEG quantization tables + byte_offset: 152 + fieldset: QMEM1_2 + - name: QMEM1_3 + description: JPEG quantization tables + byte_offset: 156 + fieldset: QMEM1_3 + - name: QMEM1_4 + description: JPEG quantization tables + byte_offset: 160 + fieldset: QMEM1_4 + - name: QMEM1_5 + description: JPEG quantization tables + byte_offset: 164 + fieldset: QMEM1_5 + - name: QMEM1_6 + description: JPEG quantization tables + byte_offset: 168 + fieldset: QMEM1_6 + - name: QMEM1_7 + description: JPEG quantization tables + byte_offset: 172 + fieldset: QMEM1_7 + - name: QMEM1_8 + description: JPEG quantization tables + byte_offset: 176 + fieldset: QMEM1_8 + - name: QMEM1_9 + description: JPEG quantization tables + byte_offset: 180 + fieldset: QMEM1_9 + - name: QMEM1_10 + description: JPEG quantization tables + byte_offset: 184 + fieldset: QMEM1_10 + - name: QMEM1_11 + description: JPEG quantization tables + byte_offset: 188 + fieldset: QMEM1_11 + - name: QMEM1_12 + description: JPEG quantization tables + byte_offset: 192 + fieldset: QMEM1_12 + - name: QMEM1_13 + description: JPEG quantization tables + byte_offset: 196 + fieldset: QMEM1_13 + - name: QMEM1_14 + description: JPEG quantization tables + byte_offset: 200 + fieldset: QMEM1_14 + - name: QMEM1_15 + description: JPEG quantization tables + byte_offset: 204 + fieldset: QMEM1_15 + - name: QMEM2_0 + description: JPEG quantization tables + byte_offset: 208 + fieldset: QMEM2_0 + - name: QMEM2_1 + description: JPEG quantization tables + byte_offset: 212 + fieldset: QMEM2_1 + - name: QMEM2_2 + description: JPEG quantization tables + byte_offset: 216 + fieldset: QMEM2_2 + - name: QMEM2_3 + description: JPEG quantization tables + byte_offset: 220 + fieldset: QMEM2_3 + - name: QMEM2_4 + description: JPEG quantization tables + byte_offset: 224 + fieldset: QMEM2_4 + - name: QMEM2_5 + description: JPEG quantization tables + byte_offset: 228 + fieldset: QMEM2_5 + - name: QMEM2_6 + description: JPEG quantization tables + byte_offset: 232 + fieldset: QMEM2_6 + - name: QMEM2_7 + description: JPEG quantization tables + byte_offset: 236 + fieldset: QMEM2_7 + - name: QMEM2_8 + description: JPEG quantization tables + byte_offset: 240 + fieldset: QMEM2_8 + - name: QMEM2_9 + description: JPEG quantization tables + byte_offset: 244 + fieldset: QMEM2_9 + - name: QMEM2_10 + description: JPEG quantization tables + byte_offset: 248 + fieldset: QMEM2_10 + - name: QMEM2_11 + description: JPEG quantization tables + byte_offset: 252 + fieldset: QMEM2_11 + - name: QMEM2_12 + description: JPEG quantization tables + byte_offset: 256 + fieldset: QMEM2_12 + - name: QMEM2_13 + description: JPEG quantization tables + byte_offset: 260 + fieldset: QMEM2_13 + - name: QMEM2_14 + description: JPEG quantization tables + byte_offset: 264 + fieldset: QMEM2_14 + - name: QMEM2_15 + description: JPEG quantization tables + byte_offset: 268 + fieldset: QMEM2_15 + - name: QMEM3_0 + description: JPEG quantization tables + byte_offset: 272 + fieldset: QMEM3_0 + - name: QMEM3_1 + description: JPEG quantization tables + byte_offset: 276 + fieldset: QMEM3_1 + - name: QMEM3_2 + description: JPEG quantization tables + byte_offset: 280 + fieldset: QMEM3_2 + - name: QMEM3_3 + description: JPEG quantization tables + byte_offset: 284 + fieldset: QMEM3_3 + - name: QMEM3_4 + description: JPEG quantization tables + byte_offset: 288 + fieldset: QMEM3_4 + - name: QMEM3_5 + description: JPEG quantization tables + byte_offset: 292 + fieldset: QMEM3_5 + - name: QMEM3_6 + description: JPEG quantization tables + byte_offset: 296 + fieldset: QMEM3_6 + - name: QMEM3_7 + description: JPEG quantization tables + byte_offset: 300 + fieldset: QMEM3_7 + - name: QMEM3_8 + description: JPEG quantization tables + byte_offset: 304 + fieldset: QMEM3_8 + - name: QMEM3_9 + description: JPEG quantization tables + byte_offset: 308 + fieldset: QMEM3_9 + - name: QMEM3_10 + description: JPEG quantization tables + byte_offset: 312 + fieldset: QMEM3_10 + - name: QMEM3_11 + description: JPEG quantization tables + byte_offset: 316 + fieldset: QMEM3_11 + - name: QMEM3_12 + description: JPEG quantization tables + byte_offset: 320 + fieldset: QMEM3_12 + - name: QMEM3_13 + description: JPEG quantization tables + byte_offset: 324 + fieldset: QMEM3_13 + - name: QMEM3_14 + description: JPEG quantization tables + byte_offset: 328 + fieldset: QMEM3_14 + - name: QMEM3_15 + description: JPEG quantization tables + byte_offset: 332 + fieldset: QMEM3_15 + - name: HUFFMIN_0 + description: JPEG HuffMin tables + byte_offset: 336 + fieldset: HUFFMIN_0 + - name: HUFFMIN_1 + description: JPEG HuffMin tables + byte_offset: 340 + fieldset: HUFFMIN_1 + - name: HUFFMIN_2 + description: JPEG HuffMin tables + byte_offset: 344 + fieldset: HUFFMIN_2 + - name: HUFFMIN_3 + description: JPEG HuffMin tables + byte_offset: 348 + fieldset: HUFFMIN_3 + - name: HUFFMIN_4 + description: JPEG HuffMin tables + byte_offset: 352 + fieldset: HUFFMIN_4 + - name: HUFFMIN_5 + description: JPEG HuffMin tables + byte_offset: 356 + fieldset: HUFFMIN_5 + - name: HUFFMIN_6 + description: JPEG HuffMin tables + byte_offset: 360 + fieldset: HUFFMIN_6 + - name: HUFFMIN_7 + description: JPEG HuffMin tables + byte_offset: 364 + fieldset: HUFFMIN_7 + - name: HUFFMIN_8 + description: JPEG HuffMin tables + byte_offset: 368 + fieldset: HUFFMIN_8 + - name: HUFFMIN_9 + description: JPEG HuffMin tables + byte_offset: 372 + fieldset: HUFFMIN_9 + - name: HUFFMIN_10 + description: JPEG HuffMin tables + byte_offset: 376 + fieldset: HUFFMIN_10 + - name: HUFFMIN_11 + description: JPEG HuffMin tables + byte_offset: 380 + fieldset: HUFFMIN_11 + - name: HUFFMIN_12 + description: JPEG HuffMin tables + byte_offset: 384 + fieldset: HUFFMIN_12 + - name: HUFFMIN_13 + description: JPEG HuffMin tables + byte_offset: 388 + fieldset: HUFFMIN_13 + - name: HUFFMIN_14 + description: JPEG HuffMin tables + byte_offset: 392 + fieldset: HUFFMIN_14 + - name: HUFFMIN_15 + description: JPEG HuffMin tables + byte_offset: 396 + fieldset: HUFFMIN_15 + - name: HUFFBASE0 + description: JPEG HuffSymb tables + byte_offset: 400 + fieldset: HUFFBASE0 + - name: HUFFBASE1 + description: JPEG HuffSymb tables + byte_offset: 404 + fieldset: HUFFBASE1 + - name: HUFFBASE2 + description: JPEG HuffSymb tables + byte_offset: 408 + fieldset: HUFFBASE2 + - name: HUFFBASE3 + description: JPEG HuffSymb tables + byte_offset: 412 + fieldset: HUFFBASE3 + - name: HUFFBASE4 + description: JPEG HuffSymb tables + byte_offset: 416 + fieldset: HUFFBASE4 + - name: HUFFBASE5 + description: JPEG HuffSymb tables + byte_offset: 420 + fieldset: HUFFBASE5 + - name: HUFFBASE6 + description: JPEG HuffSymb tables + byte_offset: 424 + fieldset: HUFFBASE6 + - name: HUFFBASE7 + description: JPEG HuffSymb tables + byte_offset: 428 + fieldset: HUFFBASE7 + - name: HUFFBASE8 + description: JPEG HuffSymb tables + byte_offset: 432 + fieldset: HUFFBASE8 + - name: HUFFBASE9 + description: JPEG HuffSymb tables + byte_offset: 436 + fieldset: HUFFBASE9 + - name: HUFFBASE10 + description: JPEG HuffSymb tables + byte_offset: 440 + fieldset: HUFFBASE10 + - name: HUFFBASE11 + description: JPEG HuffSymb tables + byte_offset: 444 + fieldset: HUFFBASE11 + - name: HUFFBASE12 + description: JPEG HuffSymb tables + byte_offset: 448 + fieldset: HUFFBASE12 + - name: HUFFBASE13 + description: JPEG HuffSymb tables + byte_offset: 452 + fieldset: HUFFBASE13 + - name: HUFFBASE14 + description: JPEG HuffSymb tables + byte_offset: 456 + fieldset: HUFFBASE14 + - name: HUFFBASE15 + description: JPEG HuffSymb tables + byte_offset: 460 + fieldset: HUFFBASE15 + - name: HUFFBASE16 + description: JPEG HuffSymb tables + byte_offset: 464 + fieldset: HUFFBASE16 + - name: HUFFBASE17 + description: JPEG HuffSymb tables + byte_offset: 468 + fieldset: HUFFBASE17 + - name: HUFFBASE18 + description: JPEG HuffSymb tables + byte_offset: 472 + fieldset: HUFFBASE18 + - name: HUFFBASE19 + description: JPEG HuffSymb tables + byte_offset: 476 + fieldset: HUFFBASE19 + - name: HUFFBASE20 + description: JPEG HuffSymb tables + byte_offset: 480 + fieldset: HUFFBASE20 + - name: HUFFBASE21 + description: JPEG HuffSymb tables + byte_offset: 484 + fieldset: HUFFBASE21 + - name: HUFFBASE22 + description: JPEG HuffSymb tables + byte_offset: 488 + fieldset: HUFFBASE22 + - name: HUFFBASE23 + description: JPEG HuffSymb tables + byte_offset: 492 + fieldset: HUFFBASE23 + - name: HUFFBASE24 + description: JPEG HuffSymb tables + byte_offset: 496 + fieldset: HUFFBASE24 + - name: HUFFBASE25 + description: JPEG HuffSymb tables + byte_offset: 500 + fieldset: HUFFBASE25 + - name: HUFFBASE26 + description: JPEG HuffSymb tables + byte_offset: 504 + fieldset: HUFFBASE26 + - name: HUFFBASE27 + description: JPEG HuffSymb tables + byte_offset: 508 + fieldset: HUFFBASE27 + - name: HUFFBASE28 + description: JPEG HuffSymb tables + byte_offset: 512 + fieldset: HUFFBASE28 + - name: HUFFBASE29 + description: JPEG HuffSymb tables + byte_offset: 516 + fieldset: HUFFBASE29 + - name: HUFFBASE30 + description: JPEG HuffSymb tables + byte_offset: 520 + fieldset: HUFFBASE30 + - name: HUFFBASE31 + description: JPEG HuffSymb tables + byte_offset: 524 + fieldset: HUFFBASE31 + - name: HUFFSYMB0 + description: JPEG HUFFSYMB tables + byte_offset: 528 + fieldset: HUFFSYMB0 + - name: HUFFSYMB1 + description: JPEG HUFFSYMB tables + byte_offset: 532 + fieldset: HUFFSYMB1 + - name: HUFFSYMB2 + description: JPEG HUFFSYMB tables + byte_offset: 536 + fieldset: HUFFSYMB2 + - name: HUFFSYMB3 + description: JPEG HUFFSYMB tables + byte_offset: 540 + fieldset: HUFFSYMB3 + - name: HUFFSYMB4 + description: JPEG HUFFSYMB tables + byte_offset: 544 + fieldset: HUFFSYMB4 + - name: HUFFSYMB5 + description: JPEG HUFFSYMB tables + byte_offset: 548 + fieldset: HUFFSYMB5 + - name: HUFFSYMB6 + description: JPEG HUFFSYMB tables + byte_offset: 552 + fieldset: HUFFSYMB6 + - name: HUFFSYMB7 + description: JPEG HUFFSYMB tables + byte_offset: 556 + fieldset: HUFFSYMB7 + - name: HUFFSYMB8 + description: JPEG HUFFSYMB tables + byte_offset: 560 + fieldset: HUFFSYMB8 + - name: HUFFSYMB9 + description: JPEG HUFFSYMB tables + byte_offset: 564 + fieldset: HUFFSYMB9 + - name: HUFFSYMB10 + description: JPEG HUFFSYMB tables + byte_offset: 568 + fieldset: HUFFSYMB10 + - name: HUFFSYMB11 + description: JPEG HUFFSYMB tables + byte_offset: 572 + fieldset: HUFFSYMB11 + - name: HUFFSYMB12 + description: JPEG HUFFSYMB tables + byte_offset: 576 + fieldset: HUFFSYMB12 + - name: HUFFSYMB13 + description: JPEG HUFFSYMB tables + byte_offset: 580 + fieldset: HUFFSYMB13 + - name: HUFFSYMB14 + description: JPEG HUFFSYMB tables + byte_offset: 584 + fieldset: HUFFSYMB14 + - name: HUFFSYMB15 + description: JPEG HUFFSYMB tables + byte_offset: 588 + fieldset: HUFFSYMB15 + - name: HUFFSYMB16 + description: JPEG HUFFSYMB tables + byte_offset: 592 + fieldset: HUFFSYMB16 + - name: HUFFSYMB17 + description: JPEG HUFFSYMB tables + byte_offset: 596 + fieldset: HUFFSYMB17 + - name: HUFFSYMB18 + description: JPEG HUFFSYMB tables + byte_offset: 600 + fieldset: HUFFSYMB18 + - name: HUFFSYMB19 + description: JPEG HUFFSYMB tables + byte_offset: 604 + fieldset: HUFFSYMB19 + - name: HUFFSYMB20 + description: JPEG HUFFSYMB tables + byte_offset: 608 + fieldset: HUFFSYMB20 + - name: HUFFSYMB21 + description: JPEG HUFFSYMB tables + byte_offset: 612 + fieldset: HUFFSYMB21 + - name: HUFFSYMB22 + description: JPEG HUFFSYMB tables + byte_offset: 616 + fieldset: HUFFSYMB22 + - name: HUFFSYMB23 + description: JPEG HUFFSYMB tables + byte_offset: 620 + fieldset: HUFFSYMB23 + - name: HUFFSYMB24 + description: JPEG HUFFSYMB tables + byte_offset: 624 + fieldset: HUFFSYMB24 + - name: HUFFSYMB25 + description: JPEG HUFFSYMB tables + byte_offset: 628 + fieldset: HUFFSYMB25 + - name: HUFFSYMB26 + description: JPEG HUFFSYMB tables + byte_offset: 632 + fieldset: HUFFSYMB26 + - name: HUFFSYMB27 + description: JPEG HUFFSYMB tables + byte_offset: 636 + fieldset: HUFFSYMB27 + - name: HUFFSYMB28 + description: JPEG HUFFSYMB tables + byte_offset: 640 + fieldset: HUFFSYMB28 + - name: HUFFSYMB29 + description: JPEG HUFFSYMB tables + byte_offset: 644 + fieldset: HUFFSYMB29 + - name: HUFFSYMB30 + description: JPEG HUFFSYMB tables + byte_offset: 648 + fieldset: HUFFSYMB30 + - name: HUFFSYMB31 + description: JPEG HUFFSYMB tables + byte_offset: 652 + fieldset: HUFFSYMB31 + - name: HUFFSYMB32 + description: JPEG HUFFSYMB tables + byte_offset: 656 + fieldset: HUFFSYMB32 + - name: HUFFSYMB33 + description: JPEG HUFFSYMB tables + byte_offset: 660 + fieldset: HUFFSYMB33 + - name: HUFFSYMB34 + description: JPEG HUFFSYMB tables + byte_offset: 664 + fieldset: HUFFSYMB34 + - name: HUFFSYMB35 + description: JPEG HUFFSYMB tables + byte_offset: 668 + fieldset: HUFFSYMB35 + - name: HUFFSYMB36 + description: JPEG HUFFSYMB tables + byte_offset: 672 + fieldset: HUFFSYMB36 + - name: HUFFSYMB37 + description: JPEG HUFFSYMB tables + byte_offset: 676 + fieldset: HUFFSYMB37 + - name: HUFFSYMB38 + description: JPEG HUFFSYMB tables + byte_offset: 680 + fieldset: HUFFSYMB38 + - name: HUFFSYMB39 + description: JPEG HUFFSYMB tables + byte_offset: 684 + fieldset: HUFFSYMB39 + - name: HUFFSYMB40 + description: JPEG HUFFSYMB tables + byte_offset: 688 + fieldset: HUFFSYMB40 + - name: HUFFSYMB41 + description: JPEG HUFFSYMB tables + byte_offset: 692 + fieldset: HUFFSYMB41 + - name: HUFFSYMB42 + description: JPEG HUFFSYMB tables + byte_offset: 696 + fieldset: HUFFSYMB42 + - name: HUFFSYMB43 + description: JPEG HUFFSYMB tables + byte_offset: 700 + fieldset: HUFFSYMB43 + - name: HUFFSYMB44 + description: JPEG HUFFSYMB tables + byte_offset: 704 + fieldset: HUFFSYMB44 + - name: HUFFSYMB45 + description: JPEG HUFFSYMB tables + byte_offset: 708 + fieldset: HUFFSYMB45 + - name: HUFFSYMB46 + description: JPEG HUFFSYMB tables + byte_offset: 712 + fieldset: HUFFSYMB46 + - name: HUFFSYMB47 + description: JPEG HUFFSYMB tables + byte_offset: 716 + fieldset: HUFFSYMB47 + - name: HUFFSYMB48 + description: JPEG HUFFSYMB tables + byte_offset: 720 + fieldset: HUFFSYMB48 + - name: HUFFSYMB49 + description: JPEG HUFFSYMB tables + byte_offset: 724 + fieldset: HUFFSYMB49 + - name: HUFFSYMB50 + description: JPEG HUFFSYMB tables + byte_offset: 728 + fieldset: HUFFSYMB50 + - name: HUFFSYMB51 + description: JPEG HUFFSYMB tables + byte_offset: 732 + fieldset: HUFFSYMB51 + - name: HUFFSYMB52 + description: JPEG HUFFSYMB tables + byte_offset: 736 + fieldset: HUFFSYMB52 + - name: HUFFSYMB53 + description: JPEG HUFFSYMB tables + byte_offset: 740 + fieldset: HUFFSYMB53 + - name: HUFFSYMB54 + description: JPEG HUFFSYMB tables + byte_offset: 744 + fieldset: HUFFSYMB54 + - name: HUFFSYMB55 + description: JPEG HUFFSYMB tables + byte_offset: 748 + fieldset: HUFFSYMB55 + - name: HUFFSYMB56 + description: JPEG HUFFSYMB tables + byte_offset: 752 + fieldset: HUFFSYMB56 + - name: HUFFSYMB57 + description: JPEG HUFFSYMB tables + byte_offset: 756 + fieldset: HUFFSYMB57 + - name: HUFFSYMB58 + description: JPEG HUFFSYMB tables + byte_offset: 760 + fieldset: HUFFSYMB58 + - name: HUFFSYMB59 + description: JPEG HUFFSYMB tables + byte_offset: 764 + fieldset: HUFFSYMB59 + - name: HUFFSYMB60 + description: JPEG HUFFSYMB tables + byte_offset: 768 + fieldset: HUFFSYMB60 + - name: HUFFSYMB61 + description: JPEG HUFFSYMB tables + byte_offset: 772 + fieldset: HUFFSYMB61 + - name: HUFFSYMB62 + description: JPEG HUFFSYMB tables + byte_offset: 776 + fieldset: HUFFSYMB62 + - name: HUFFSYMB63 + description: JPEG HUFFSYMB tables + byte_offset: 780 + fieldset: HUFFSYMB63 + - name: HUFFSYMB64 + description: JPEG HUFFSYMB tables + byte_offset: 784 + fieldset: HUFFSYMB64 + - name: HUFFSYMB65 + description: JPEG HUFFSYMB tables + byte_offset: 788 + fieldset: HUFFSYMB65 + - name: HUFFSYMB66 + description: JPEG HUFFSYMB tables + byte_offset: 792 + fieldset: HUFFSYMB66 + - name: HUFFSYMB67 + description: JPEG HUFFSYMB tables + byte_offset: 796 + fieldset: HUFFSYMB67 + - name: HUFFSYMB68 + description: JPEG HUFFSYMB tables + byte_offset: 800 + fieldset: HUFFSYMB68 + - name: HUFFSYMB69 + description: JPEG HUFFSYMB tables + byte_offset: 804 + fieldset: HUFFSYMB69 + - name: HUFFSYMB70 + description: JPEG HUFFSYMB tables + byte_offset: 808 + fieldset: HUFFSYMB70 + - name: HUFFSYMB71 + description: JPEG HUFFSYMB tables + byte_offset: 812 + fieldset: HUFFSYMB71 + - name: HUFFSYMB72 + description: JPEG HUFFSYMB tables + byte_offset: 816 + fieldset: HUFFSYMB72 + - name: HUFFSYMB73 + description: JPEG HUFFSYMB tables + byte_offset: 820 + fieldset: HUFFSYMB73 + - name: HUFFSYMB74 + description: JPEG HUFFSYMB tables + byte_offset: 824 + fieldset: HUFFSYMB74 + - name: HUFFSYMB75 + description: JPEG HUFFSYMB tables + byte_offset: 828 + fieldset: HUFFSYMB75 + - name: HUFFSYMB76 + description: JPEG HUFFSYMB tables + byte_offset: 832 + fieldset: HUFFSYMB76 + - name: HUFFSYMB77 + description: JPEG HUFFSYMB tables + byte_offset: 836 + fieldset: HUFFSYMB77 + - name: HUFFSYMB78 + description: JPEG HUFFSYMB tables + byte_offset: 840 + fieldset: HUFFSYMB78 + - name: HUFFSYMB79 + description: JPEG HUFFSYMB tables + byte_offset: 844 + fieldset: HUFFSYMB79 + - name: HUFFSYMB80 + description: JPEG HUFFSYMB tables + byte_offset: 848 + fieldset: HUFFSYMB80 + - name: HUFFSYMB81 + description: JPEG HUFFSYMB tables + byte_offset: 852 + fieldset: HUFFSYMB81 + - name: HUFFSYMB82 + description: JPEG HUFFSYMB tables + byte_offset: 856 + fieldset: HUFFSYMB82 + - name: HUFFSYMB83 + description: JPEG HUFFSYMB tables + byte_offset: 860 + fieldset: HUFFSYMB83 + - name: DHTMEM0 + description: JPEG DHTMem tables + byte_offset: 864 + fieldset: DHTMEM0 + - name: DHTMEM2 + description: JPEG DHTMem tables + byte_offset: 868 + fieldset: DHTMEM2 + - name: DHTMEM3 + description: JPEG DHTMem tables + byte_offset: 872 + fieldset: DHTMEM3 + - name: DHTMEM4 + description: JPEG DHTMem tables + byte_offset: 876 + fieldset: DHTMEM4 + - name: DHTMEM5 + description: JPEG DHTMem tables + byte_offset: 880 + fieldset: DHTMEM5 + - name: DHTMEM6 + description: JPEG DHTMem tables + byte_offset: 884 + fieldset: DHTMEM6 + - name: DHTMEM7 + description: JPEG DHTMem tables + byte_offset: 888 + fieldset: DHTMEM7 + - name: DHTMEM8 + description: JPEG DHTMem tables + byte_offset: 892 + fieldset: DHTMEM8 + - name: DHTMEM9 + description: JPEG DHTMem tables + byte_offset: 896 + fieldset: DHTMEM9 + - name: DHTMEM10 + description: JPEG DHTMem tables + byte_offset: 900 + fieldset: DHTMEM10 + - name: DHTMEM11 + description: JPEG DHTMem tables + byte_offset: 904 + fieldset: DHTMEM11 + - name: DHTMEM12 + description: JPEG DHTMem tables + byte_offset: 908 + fieldset: DHTMEM12 + - name: DHTMEM13 + description: JPEG DHTMem tables + byte_offset: 912 + fieldset: DHTMEM13 + - name: DHTMEM14 + description: JPEG DHTMem tables + byte_offset: 916 + fieldset: DHTMEM14 + - name: DHTMEM15 + description: JPEG DHTMem tables + byte_offset: 920 + fieldset: DHTMEM15 + - name: DHTMEM16 + description: JPEG DHTMem tables + byte_offset: 924 + fieldset: DHTMEM16 + - name: DHTMEM17 + description: JPEG DHTMem tables + byte_offset: 928 + fieldset: DHTMEM17 + - name: DHTMEM18 + description: JPEG DHTMem tables + byte_offset: 932 + fieldset: DHTMEM18 + - name: DHTMEM19 + description: JPEG DHTMem tables + byte_offset: 936 + fieldset: DHTMEM19 + - name: DHTMEM20 + description: JPEG DHTMem tables + byte_offset: 940 + fieldset: DHTMEM20 + - name: DHTMEM21 + description: JPEG DHTMem tables + byte_offset: 944 + fieldset: DHTMEM21 + - name: DHTMEM22 + description: JPEG DHTMem tables + byte_offset: 948 + fieldset: DHTMEM22 + - name: DHTMEM23 + description: JPEG DHTMem tables + byte_offset: 952 + fieldset: DHTMEM23 + - name: DHTMEM24 + description: JPEG DHTMem tables + byte_offset: 956 + fieldset: DHTMEM24 + - name: DHTMEM25 + description: JPEG DHTMem tables + byte_offset: 960 + fieldset: DHTMEM25 + - name: DHTMEM26 + description: JPEG DHTMem tables + byte_offset: 964 + fieldset: DHTMEM26 + - name: DHTMEM27 + description: JPEG DHTMem tables + byte_offset: 968 + fieldset: DHTMEM27 + - name: DHTMEM28 + description: JPEG DHTMem tables + byte_offset: 972 + fieldset: DHTMEM28 + - name: DHTMEM29 + description: JPEG DHTMem tables + byte_offset: 976 + fieldset: DHTMEM29 + - name: DHTMEM30 + description: JPEG DHTMem tables + byte_offset: 980 + fieldset: DHTMEM30 + - name: DHTMEM31 + description: JPEG DHTMem tables + byte_offset: 984 + fieldset: DHTMEM31 + - name: DHTMEM32 + description: JPEG DHTMem tables + byte_offset: 988 + fieldset: DHTMEM32 + - name: DHTMEM33 + description: JPEG DHTMem tables + byte_offset: 992 + fieldset: DHTMEM33 + - name: DHTMEM34 + description: JPEG DHTMem tables + byte_offset: 996 + fieldset: DHTMEM34 + - name: DHTMEM35 + description: JPEG DHTMem tables + byte_offset: 1000 + fieldset: DHTMEM35 + - name: DHTMEM36 + description: JPEG DHTMem tables + byte_offset: 1004 + fieldset: DHTMEM36 + - name: DHTMEM37 + description: JPEG DHTMem tables + byte_offset: 1008 + fieldset: DHTMEM37 + - name: DHTMEM38 + description: JPEG DHTMem tables + byte_offset: 1012 + fieldset: DHTMEM38 + - name: DHTMEM39 + description: JPEG DHTMem tables + byte_offset: 1016 + fieldset: DHTMEM39 + - name: DHTMEM40 + description: JPEG DHTMem tables + byte_offset: 1020 + fieldset: DHTMEM40 + - name: DHTMEM41 + description: JPEG DHTMem tables + byte_offset: 1024 + fieldset: DHTMEM41 + - name: DHTMEM42 + description: JPEG DHTMem tables + byte_offset: 1028 + fieldset: DHTMEM42 + - name: DHTMEM43 + description: JPEG DHTMem tables + byte_offset: 1032 + fieldset: DHTMEM43 + - name: DHTMEM44 + description: JPEG DHTMem tables + byte_offset: 1036 + fieldset: DHTMEM44 + - name: DHTMEM45 + description: JPEG DHTMem tables + byte_offset: 1040 + fieldset: DHTMEM45 + - name: DHTMEM46 + description: JPEG DHTMem tables + byte_offset: 1044 + fieldset: DHTMEM46 + - name: DHTMEM47 + description: JPEG DHTMem tables + byte_offset: 1048 + fieldset: DHTMEM47 + - name: DHTMEM48 + description: JPEG DHTMem tables + byte_offset: 1052 + fieldset: DHTMEM48 + - name: DHTMEM49 + description: JPEG DHTMem tables + byte_offset: 1056 + fieldset: DHTMEM49 + - name: DHTMEM50 + description: JPEG DHTMem tables + byte_offset: 1060 + fieldset: DHTMEM50 + - name: DHTMEM51 + description: JPEG DHTMem tables + byte_offset: 1064 + fieldset: DHTMEM51 + - name: DHTMEM52 + description: JPEG DHTMem tables + byte_offset: 1068 + fieldset: DHTMEM52 + - name: DHTMEM53 + description: JPEG DHTMem tables + byte_offset: 1072 + fieldset: DHTMEM53 + - name: DHTMEM54 + description: JPEG DHTMem tables + byte_offset: 1076 + fieldset: DHTMEM54 + - name: DHTMEM55 + description: JPEG DHTMem tables + byte_offset: 1080 + fieldset: DHTMEM55 + - name: DHTMEM56 + description: JPEG DHTMem tables + byte_offset: 1084 + fieldset: DHTMEM56 + - name: DHTMEM57 + description: JPEG DHTMem tables + byte_offset: 1088 + fieldset: DHTMEM57 + - name: DHTMEM58 + description: JPEG DHTMem tables + byte_offset: 1092 + fieldset: DHTMEM58 + - name: DHTMEM59 + description: JPEG DHTMem tables + byte_offset: 1096 + fieldset: DHTMEM59 + - name: DHTMEM60 + description: JPEG DHTMem tables + byte_offset: 1100 + fieldset: DHTMEM60 + - name: DHTMEM61 + description: JPEG DHTMem tables + byte_offset: 1104 + fieldset: DHTMEM61 + - name: DHTMEM62 + description: JPEG DHTMem tables + byte_offset: 1108 + fieldset: DHTMEM62 + - name: DHTMEM63 + description: JPEG DHTMem tables + byte_offset: 1112 + fieldset: DHTMEM63 + - name: DHTMEM64 + description: JPEG DHTMem tables + byte_offset: 1116 + fieldset: DHTMEM64 + - name: DHTMEM65 + description: JPEG DHTMem tables + byte_offset: 1120 + fieldset: DHTMEM65 + - name: DHTMEM66 + description: JPEG DHTMem tables + byte_offset: 1124 + fieldset: DHTMEM66 + - name: DHTMEM67 + description: JPEG DHTMem tables + byte_offset: 1128 + fieldset: DHTMEM67 + - name: DHTMEM68 + description: JPEG DHTMem tables + byte_offset: 1132 + fieldset: DHTMEM68 + - name: DHTMEM69 + description: JPEG DHTMem tables + byte_offset: 1136 + fieldset: DHTMEM69 + - name: DHTMEM70 + description: JPEG DHTMem tables + byte_offset: 1140 + fieldset: DHTMEM70 + - name: DHTMEM71 + description: JPEG DHTMem tables + byte_offset: 1144 + fieldset: DHTMEM71 + - name: DHTMEM72 + description: JPEG DHTMem tables + byte_offset: 1148 + fieldset: DHTMEM72 + - name: DHTMEM73 + description: JPEG DHTMem tables + byte_offset: 1152 + fieldset: DHTMEM73 + - name: DHTMEM74 + description: JPEG DHTMem tables + byte_offset: 1156 + fieldset: DHTMEM74 + - name: DHTMEM75 + description: JPEG DHTMem tables + byte_offset: 1160 + fieldset: DHTMEM75 + - name: DHTMEM76 + description: JPEG DHTMem tables + byte_offset: 1164 + fieldset: DHTMEM76 + - name: DHTMEM77 + description: JPEG DHTMem tables + byte_offset: 1168 + fieldset: DHTMEM77 + - name: DHTMEM78 + description: JPEG DHTMem tables + byte_offset: 1172 + fieldset: DHTMEM78 + - name: DHTMEM79 + description: JPEG DHTMem tables + byte_offset: 1176 + fieldset: DHTMEM79 + - name: DHTMEM80 + description: JPEG DHTMem tables + byte_offset: 1180 + fieldset: DHTMEM80 + - name: DHTMEM81 + description: JPEG DHTMem tables + byte_offset: 1184 + fieldset: DHTMEM81 + - name: DHTMEM82 + description: JPEG DHTMem tables + byte_offset: 1188 + fieldset: DHTMEM82 + - name: DHTMEM83 + description: JPEG DHTMem tables + byte_offset: 1192 + fieldset: DHTMEM83 + - name: DHTMEM84 + description: JPEG DHTMem tables + byte_offset: 1196 + fieldset: DHTMEM84 + - name: DHTMEM85 + description: JPEG DHTMem tables + byte_offset: 1200 + fieldset: DHTMEM85 + - name: DHTMEM86 + description: JPEG DHTMem tables + byte_offset: 1204 + fieldset: DHTMEM86 + - name: DHTMEM87 + description: JPEG DHTMem tables + byte_offset: 1208 + fieldset: DHTMEM87 + - name: DHTMEM88 + description: JPEG DHTMem tables + byte_offset: 1212 + fieldset: DHTMEM88 + - name: DHTMEM89 + description: JPEG DHTMem tables + byte_offset: 1216 + fieldset: DHTMEM89 + - name: DHTMEM90 + description: JPEG DHTMem tables + byte_offset: 1220 + fieldset: DHTMEM90 + - name: DHTMEM91 + description: JPEG DHTMem tables + byte_offset: 1224 + fieldset: DHTMEM91 + - name: DHTMEM92 + description: JPEG DHTMem tables + byte_offset: 1228 + fieldset: DHTMEM92 + - name: DHTMEM93 + description: JPEG DHTMem tables + byte_offset: 1232 + fieldset: DHTMEM93 + - name: DHTMEM94 + description: JPEG DHTMem tables + byte_offset: 1236 + fieldset: DHTMEM94 + - name: DHTMEM95 + description: JPEG DHTMem tables + byte_offset: 1240 + fieldset: DHTMEM95 + - name: DHTMEM96 + description: JPEG DHTMem tables + byte_offset: 1244 + fieldset: DHTMEM96 + - name: DHTMEM97 + description: JPEG DHTMem tables + byte_offset: 1248 + fieldset: DHTMEM97 + - name: DHTMEM98 + description: JPEG DHTMem tables + byte_offset: 1252 + fieldset: DHTMEM98 + - name: DHTMEM99 + description: JPEG DHTMem tables + byte_offset: 1256 + fieldset: DHTMEM99 + - name: DHTMEM100 + description: JPEG DHTMem tables + byte_offset: 1260 + fieldset: DHTMEM100 + - name: DHTMEM101 + description: JPEG DHTMem tables + byte_offset: 1264 + fieldset: DHTMEM101 + - name: DHTMEM102 + description: JPEG DHTMem tables + byte_offset: 1268 + fieldset: DHTMEM102 + - name: DHTMEM103 + description: JPEG DHTMem tables + byte_offset: 1272 + fieldset: DHTMEM103 + - name: HUFFENC_AC0_0 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1280 + fieldset: HUFFENC_AC0_0 + - name: HUFFENC_AC0_1 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1284 + fieldset: HUFFENC_AC0_1 + - name: HUFFENC_AC0_2 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1288 + fieldset: HUFFENC_AC0_2 + - name: HUFFENC_AC0_3 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1292 + fieldset: HUFFENC_AC0_3 + - name: HUFFENC_AC0_4 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1296 + fieldset: HUFFENC_AC0_4 + - name: HUFFENC_AC0_5 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1300 + fieldset: HUFFENC_AC0_5 + - name: HUFFENC_AC0_6 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1304 + fieldset: HUFFENC_AC0_6 + - name: HUFFENC_AC0_7 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1308 + fieldset: HUFFENC_AC0_7 + - name: HUFFENC_AC0_8 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1312 + fieldset: HUFFENC_AC0_8 + - name: HUFFENC_AC0_9 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1316 + fieldset: HUFFENC_AC0_9 + - name: HUFFENC_AC0_10 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1320 + fieldset: HUFFENC_AC0_10 + - name: HUFFENC_AC0_11 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1324 + fieldset: HUFFENC_AC0_11 + - name: HUFFENC_AC0_12 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1328 + fieldset: HUFFENC_AC0_12 + - name: HUFFENC_AC0_13 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1332 + fieldset: HUFFENC_AC0_13 + - name: HUFFENC_AC0_14 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1336 + fieldset: HUFFENC_AC0_14 + - name: HUFFENC_AC0_15 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1340 + fieldset: HUFFENC_AC0_15 + - name: HUFFENC_AC0_16 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1344 + fieldset: HUFFENC_AC0_16 + - name: HUFFENC_AC0_17 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1348 + fieldset: HUFFENC_AC0_17 + - name: HUFFENC_AC0_18 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1352 + fieldset: HUFFENC_AC0_18 + - name: HUFFENC_AC0_19 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1356 + fieldset: HUFFENC_AC0_19 + - name: HUFFENC_AC0_20 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1360 + fieldset: HUFFENC_AC0_20 + - name: HUFFENC_AC0_21 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1364 + fieldset: HUFFENC_AC0_21 + - name: HUFFENC_AC0_22 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1368 + fieldset: HUFFENC_AC0_22 + - name: HUFFENC_AC0_23 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1372 + fieldset: HUFFENC_AC0_23 + - name: HUFFENC_AC0_24 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1376 + fieldset: HUFFENC_AC0_24 + - name: HUFFENC_AC0_25 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1380 + fieldset: HUFFENC_AC0_25 + - name: HUFFENC_AC0_26 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1384 + fieldset: HUFFENC_AC0_26 + - name: HUFFENC_AC0_27 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1388 + fieldset: HUFFENC_AC0_27 + - name: HUFFENC_AC0_28 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1392 + fieldset: HUFFENC_AC0_28 + - name: HUFFENC_AC0_29 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1396 + fieldset: HUFFENC_AC0_29 + - name: HUFFENC_AC0_30 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1400 + fieldset: HUFFENC_AC0_30 + - name: HUFFENC_AC0_31 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1404 + fieldset: HUFFENC_AC0_31 + - name: HUFFENC_AC0_32 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1408 + fieldset: HUFFENC_AC0_32 + - name: HUFFENC_AC0_33 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1412 + fieldset: HUFFENC_AC0_33 + - name: HUFFENC_AC0_34 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1416 + fieldset: HUFFENC_AC0_34 + - name: HUFFENC_AC0_35 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1420 + fieldset: HUFFENC_AC0_35 + - name: HUFFENC_AC0_36 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1424 + fieldset: HUFFENC_AC0_36 + - name: HUFFENC_AC0_37 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1428 + fieldset: HUFFENC_AC0_37 + - name: HUFFENC_AC0_38 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1432 + fieldset: HUFFENC_AC0_38 + - name: HUFFENC_AC0_39 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1436 + fieldset: HUFFENC_AC0_39 + - name: HUFFENC_AC0_40 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1440 + fieldset: HUFFENC_AC0_40 + - name: HUFFENC_AC0_41 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1444 + fieldset: HUFFENC_AC0_41 + - name: HUFFENC_AC0_42 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1448 + fieldset: HUFFENC_AC0_42 + - name: HUFFENC_AC0_43 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1452 + fieldset: HUFFENC_AC0_43 + - name: HUFFENC_AC0_44 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1456 + fieldset: HUFFENC_AC0_44 + - name: HUFFENC_AC0_45 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1460 + fieldset: HUFFENC_AC0_45 + - name: HUFFENC_AC0_46 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1464 + fieldset: HUFFENC_AC0_46 + - name: HUFFENC_AC0_47 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1468 + fieldset: HUFFENC_AC0_47 + - name: HUFFENC_AC0_48 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1472 + fieldset: HUFFENC_AC0_48 + - name: HUFFENC_AC0_49 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1476 + fieldset: HUFFENC_AC0_49 + - name: HUFFENC_AC0_50 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1480 + fieldset: HUFFENC_AC0_50 + - name: HUFFENC_AC0_51 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1484 + fieldset: HUFFENC_AC0_51 + - name: HUFFENC_AC0_52 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1488 + fieldset: HUFFENC_AC0_52 + - name: HUFFENC_AC0_53 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1492 + fieldset: HUFFENC_AC0_53 + - name: HUFFENC_AC0_54 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1496 + fieldset: HUFFENC_AC0_54 + - name: HUFFENC_AC0_55 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1500 + fieldset: HUFFENC_AC0_55 + - name: HUFFENC_AC0_56 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1504 + fieldset: HUFFENC_AC0_56 + - name: HUFFENC_AC0_57 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1508 + fieldset: HUFFENC_AC0_57 + - name: HUFFENC_AC0_58 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1512 + fieldset: HUFFENC_AC0_58 + - name: HUFFENC_AC0_59 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1516 + fieldset: HUFFENC_AC0_59 + - name: HUFFENC_AC0_60 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1520 + fieldset: HUFFENC_AC0_60 + - name: HUFFENC_AC0_61 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1524 + fieldset: HUFFENC_AC0_61 + - name: HUFFENC_AC0_62 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1528 + fieldset: HUFFENC_AC0_62 + - name: HUFFENC_AC0_63 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1532 + fieldset: HUFFENC_AC0_63 + - name: HUFFENC_AC0_64 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1536 + fieldset: HUFFENC_AC0_64 + - name: HUFFENC_AC0_65 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1540 + fieldset: HUFFENC_AC0_65 + - name: HUFFENC_AC0_66 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1544 + fieldset: HUFFENC_AC0_66 + - name: HUFFENC_AC0_67 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1548 + fieldset: HUFFENC_AC0_67 + - name: HUFFENC_AC0_68 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1552 + fieldset: HUFFENC_AC0_68 + - name: HUFFENC_AC0_69 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1556 + fieldset: HUFFENC_AC0_69 + - name: HUFFENC_AC0_70 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1560 + fieldset: HUFFENC_AC0_70 + - name: HUFFENC_AC0_71 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1564 + fieldset: HUFFENC_AC0_71 + - name: HUFFENC_AC0_72 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1568 + fieldset: HUFFENC_AC0_72 + - name: HUFFENC_AC0_73 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1572 + fieldset: HUFFENC_AC0_73 + - name: HUFFENC_AC0_74 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1576 + fieldset: HUFFENC_AC0_74 + - name: HUFFENC_AC0_75 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1580 + fieldset: HUFFENC_AC0_75 + - name: HUFFENC_AC0_76 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1584 + fieldset: HUFFENC_AC0_76 + - name: HUFFENC_AC0_77 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1588 + fieldset: HUFFENC_AC0_77 + - name: HUFFENC_AC0_78 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1592 + fieldset: HUFFENC_AC0_78 + - name: HUFFENC_AC0_79 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1596 + fieldset: HUFFENC_AC0_79 + - name: HUFFENC_AC0_80 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1600 + fieldset: HUFFENC_AC0_80 + - name: HUFFENC_AC0_81 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1604 + fieldset: HUFFENC_AC0_81 + - name: HUFFENC_AC0_82 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1608 + fieldset: HUFFENC_AC0_82 + - name: HUFFENC_AC0_83 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1612 + fieldset: HUFFENC_AC0_83 + - name: HUFFENC_AC0_84 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1616 + fieldset: HUFFENC_AC0_84 + - name: HUFFENC_AC0_85 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1620 + fieldset: HUFFENC_AC0_85 + - name: HUFFENC_AC0_86 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1624 + fieldset: HUFFENC_AC0_86 + - name: HUFFENC_AC0_87 + description: "JPEG encoder, AC Huffman table 0" + byte_offset: 1628 + fieldset: HUFFENC_AC0_87 + - name: HUFFENC_AC1_0 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1632 + fieldset: HUFFENC_AC1_0 + - name: HUFFENC_AC1_1 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1636 + fieldset: HUFFENC_AC1_1 + - name: HUFFENC_AC1_2 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1640 + fieldset: HUFFENC_AC1_2 + - name: HUFFENC_AC1_3 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1644 + fieldset: HUFFENC_AC1_3 + - name: HUFFENC_AC1_4 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1648 + fieldset: HUFFENC_AC1_4 + - name: HUFFENC_AC1_5 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1652 + fieldset: HUFFENC_AC1_5 + - name: HUFFENC_AC1_6 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1656 + fieldset: HUFFENC_AC1_6 + - name: HUFFENC_AC1_7 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1660 + fieldset: HUFFENC_AC1_7 + - name: HUFFENC_AC1_8 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1664 + fieldset: HUFFENC_AC1_8 + - name: HUFFENC_AC1_9 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1668 + fieldset: HUFFENC_AC1_9 + - name: HUFFENC_AC1_10 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1672 + fieldset: HUFFENC_AC1_10 + - name: HUFFENC_AC1_11 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1676 + fieldset: HUFFENC_AC1_11 + - name: HUFFENC_AC1_12 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1680 + fieldset: HUFFENC_AC1_12 + - name: HUFFENC_AC1_13 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1684 + fieldset: HUFFENC_AC1_13 + - name: HUFFENC_AC1_14 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1688 + fieldset: HUFFENC_AC1_14 + - name: HUFFENC_AC1_15 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1692 + fieldset: HUFFENC_AC1_15 + - name: HUFFENC_AC1_16 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1696 + fieldset: HUFFENC_AC1_16 + - name: HUFFENC_AC1_17 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1700 + fieldset: HUFFENC_AC1_17 + - name: HUFFENC_AC1_18 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1704 + fieldset: HUFFENC_AC1_18 + - name: HUFFENC_AC1_19 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1708 + fieldset: HUFFENC_AC1_19 + - name: HUFFENC_AC1_20 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1712 + fieldset: HUFFENC_AC1_20 + - name: HUFFENC_AC1_21 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1716 + fieldset: HUFFENC_AC1_21 + - name: HUFFENC_AC1_22 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1720 + fieldset: HUFFENC_AC1_22 + - name: HUFFENC_AC1_23 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1724 + fieldset: HUFFENC_AC1_23 + - name: HUFFENC_AC1_24 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1728 + fieldset: HUFFENC_AC1_24 + - name: HUFFENC_AC1_25 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1732 + fieldset: HUFFENC_AC1_25 + - name: HUFFENC_AC1_26 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1736 + fieldset: HUFFENC_AC1_26 + - name: HUFFENC_AC1_27 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1740 + fieldset: HUFFENC_AC1_27 + - name: HUFFENC_AC1_28 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1744 + fieldset: HUFFENC_AC1_28 + - name: HUFFENC_AC1_29 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1748 + fieldset: HUFFENC_AC1_29 + - name: HUFFENC_AC1_30 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1752 + fieldset: HUFFENC_AC1_30 + - name: HUFFENC_AC1_31 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1756 + fieldset: HUFFENC_AC1_31 + - name: HUFFENC_AC1_32 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1760 + fieldset: HUFFENC_AC1_32 + - name: HUFFENC_AC1_33 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1764 + fieldset: HUFFENC_AC1_33 + - name: HUFFENC_AC1_34 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1768 + fieldset: HUFFENC_AC1_34 + - name: HUFFENC_AC1_35 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1772 + fieldset: HUFFENC_AC1_35 + - name: HUFFENC_AC1_36 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1776 + fieldset: HUFFENC_AC1_36 + - name: HUFFENC_AC1_37 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1780 + fieldset: HUFFENC_AC1_37 + - name: HUFFENC_AC1_38 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1784 + fieldset: HUFFENC_AC1_38 + - name: HUFFENC_AC1_39 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1788 + fieldset: HUFFENC_AC1_39 + - name: HUFFENC_AC1_40 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1792 + fieldset: HUFFENC_AC1_40 + - name: HUFFENC_AC1_41 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1796 + fieldset: HUFFENC_AC1_41 + - name: HUFFENC_AC1_42 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1800 + fieldset: HUFFENC_AC1_42 + - name: HUFFENC_AC1_43 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1804 + fieldset: HUFFENC_AC1_43 + - name: HUFFENC_AC1_44 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1808 + fieldset: HUFFENC_AC1_44 + - name: HUFFENC_AC1_45 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1812 + fieldset: HUFFENC_AC1_45 + - name: HUFFENC_AC1_46 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1816 + fieldset: HUFFENC_AC1_46 + - name: HUFFENC_AC1_47 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1820 + fieldset: HUFFENC_AC1_47 + - name: HUFFENC_AC1_48 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1824 + fieldset: HUFFENC_AC1_48 + - name: HUFFENC_AC1_49 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1828 + fieldset: HUFFENC_AC1_49 + - name: HUFFENC_AC1_50 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1832 + fieldset: HUFFENC_AC1_50 + - name: HUFFENC_AC1_51 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1836 + fieldset: HUFFENC_AC1_51 + - name: HUFFENC_AC1_52 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1840 + fieldset: HUFFENC_AC1_52 + - name: HUFFENC_AC1_53 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1844 + fieldset: HUFFENC_AC1_53 + - name: HUFFENC_AC1_54 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1848 + fieldset: HUFFENC_AC1_54 + - name: HUFFENC_AC1_55 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1852 + fieldset: HUFFENC_AC1_55 + - name: HUFFENC_AC1_56 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1856 + fieldset: HUFFENC_AC1_56 + - name: HUFFENC_AC1_57 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1860 + fieldset: HUFFENC_AC1_57 + - name: HUFFENC_AC1_58 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1864 + fieldset: HUFFENC_AC1_58 + - name: HUFFENC_AC1_59 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1868 + fieldset: HUFFENC_AC1_59 + - name: HUFFENC_AC1_60 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1872 + fieldset: HUFFENC_AC1_60 + - name: HUFFENC_AC1_61 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1876 + fieldset: HUFFENC_AC1_61 + - name: HUFFENC_AC1_62 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1880 + fieldset: HUFFENC_AC1_62 + - name: HUFFENC_AC1_63 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1884 + fieldset: HUFFENC_AC1_63 + - name: HUFFENC_AC1_64 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1888 + fieldset: HUFFENC_AC1_64 + - name: HUFFENC_AC1_65 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1892 + fieldset: HUFFENC_AC1_65 + - name: HUFFENC_AC1_66 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1896 + fieldset: HUFFENC_AC1_66 + - name: HUFFENC_AC1_67 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1900 + fieldset: HUFFENC_AC1_67 + - name: HUFFENC_AC1_68 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1904 + fieldset: HUFFENC_AC1_68 + - name: HUFFENC_AC1_69 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1908 + fieldset: HUFFENC_AC1_69 + - name: HUFFENC_AC1_70 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1912 + fieldset: HUFFENC_AC1_70 + - name: HUFFENC_AC1_71 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1916 + fieldset: HUFFENC_AC1_71 + - name: HUFFENC_AC1_72 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1920 + fieldset: HUFFENC_AC1_72 + - name: HUFFENC_AC1_73 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1924 + fieldset: HUFFENC_AC1_73 + - name: HUFFENC_AC1_74 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1928 + fieldset: HUFFENC_AC1_74 + - name: HUFFENC_AC1_75 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1932 + fieldset: HUFFENC_AC1_75 + - name: HUFFENC_AC1_76 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1936 + fieldset: HUFFENC_AC1_76 + - name: HUFFENC_AC1_77 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1940 + fieldset: HUFFENC_AC1_77 + - name: HUFFENC_AC1_78 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1944 + fieldset: HUFFENC_AC1_78 + - name: HUFFENC_AC1_79 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1948 + fieldset: HUFFENC_AC1_79 + - name: HUFFENC_AC1_80 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1952 + fieldset: HUFFENC_AC1_80 + - name: HUFFENC_AC1_81 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1956 + fieldset: HUFFENC_AC1_81 + - name: HUFFENC_AC1_82 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1960 + fieldset: HUFFENC_AC1_82 + - name: HUFFENC_AC1_83 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1964 + fieldset: HUFFENC_AC1_83 + - name: HUFFENC_AC1_84 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1968 + fieldset: HUFFENC_AC1_84 + - name: HUFFENC_AC1_85 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1972 + fieldset: HUFFENC_AC1_85 + - name: HUFFENC_AC1_86 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1976 + fieldset: HUFFENC_AC1_86 + - name: HUFFENC_AC1_87 + description: "JPEG encoder, AC Huffman table 1" + byte_offset: 1980 + fieldset: HUFFENC_AC1_87 + - name: HUFFENC_DC0_0 + description: "JPEG encoder, DC Huffman table 0" + byte_offset: 1984 + fieldset: HUFFENC_DC0_0 + - name: HUFFENC_DC0_1 + description: "JPEG encoder, DC Huffman table 0" + byte_offset: 1988 + fieldset: HUFFENC_DC0_1 + - name: HUFFENC_DC0_2 + description: "JPEG encoder, DC Huffman table 0" + byte_offset: 1992 + fieldset: HUFFENC_DC0_2 + - name: HUFFENC_DC0_3 + description: "JPEG encoder, DC Huffman table 0" + byte_offset: 1996 + fieldset: HUFFENC_DC0_3 + - name: HUFFENC_DC0_4 + description: "JPEG encoder, DC Huffman table 0" + byte_offset: 2000 + fieldset: HUFFENC_DC0_4 + - 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description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_3: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_30: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_31: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_32: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_33: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_34: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_35: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_36: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_37: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_38: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_39: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_4: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_40: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_41: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_42: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_43: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_44: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_45: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_46: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_47: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_48: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_49: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_5: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_50: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_51: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_52: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_53: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_54: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_55: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_56: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_57: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_58: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_59: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_6: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_60: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_61: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_62: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_63: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_64: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_65: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_66: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_67: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_68: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_69: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_7: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_70: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_71: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_72: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_73: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_74: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_75: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_76: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_77: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_78: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_79: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_8: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_80: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_81: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_82: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_83: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_84: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_85: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_86: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_87: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC0_9: - description: JPEG encoder, AC Huffman table 0 + description: "JPEG encoder, AC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_0: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_1: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_10: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_11: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_12: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_13: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_14: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_15: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_16: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_17: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_18: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_19: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_2: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_20: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_21: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_22: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_23: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_24: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_25: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_26: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_27: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_28: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_29: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_3: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_30: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_31: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_32: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_33: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_34: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_35: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_36: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_37: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_38: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_39: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_4: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_40: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_41: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_42: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_43: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_44: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_45: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_46: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_47: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_48: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_49: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_5: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_50: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_51: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_52: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_53: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_54: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_55: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_56: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_57: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_58: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_59: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_6: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_60: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_61: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_62: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_63: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_64: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_65: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_66: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_67: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_68: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_69: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_7: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_70: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_71: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_72: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_73: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_74: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_75: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_76: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_77: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_78: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_79: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_8: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_80: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_81: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_82: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_83: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_84: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_85: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_86: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_87: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_AC1_9: - description: JPEG encoder, AC Huffman table 1 + description: "JPEG encoder, AC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_0: - description: JPEG encoder, DC Huffman table 0 + description: "JPEG encoder, DC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_1: - description: JPEG encoder, DC Huffman table 0 + description: "JPEG encoder, DC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_2: - description: JPEG encoder, DC Huffman table 0 + description: "JPEG encoder, DC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_3: - description: JPEG encoder, DC Huffman table 0 + description: "JPEG encoder, DC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_4: - description: JPEG encoder, DC Huffman table 0 + description: "JPEG encoder, DC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_5: - description: JPEG encoder, DC Huffman table 0 + description: "JPEG encoder, DC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_6: - description: JPEG encoder, DC Huffman table 0 + description: "JPEG encoder, DC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC0_7: - description: JPEG encoder, DC Huffman table 0 + description: "JPEG encoder, DC Huffman table 0" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_0: - description: JPEG encoder, DC Huffman table 1 + description: "JPEG encoder, DC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_1: - description: JPEG encoder, DC Huffman table 1 + description: "JPEG encoder, DC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_2: - description: JPEG encoder, DC Huffman table 1 + description: "JPEG encoder, DC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_3: - description: JPEG encoder, DC Huffman table 1 + description: "JPEG encoder, DC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_4: - description: JPEG encoder, DC Huffman table 1 + description: "JPEG encoder, DC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_5: - description: JPEG encoder, DC Huffman table 1 + description: "JPEG encoder, DC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_6: - description: JPEG encoder, DC Huffman table 1 + description: "JPEG encoder, DC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFENC_DC1_7: - description: JPEG encoder, DC Huffman table 1 + description: "JPEG encoder, DC Huffman table 1" fields: - - bit_offset: 0 - bit_size: 32 - description: DHTMem RAM - name: DHTMem_RAM + - name: DHTMem_RAM + description: DHTMem RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_0: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_1: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_10: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_11: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_12: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_13: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_14: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_15: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_2: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_3: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_4: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_5: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_6: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_7: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_8: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFMIN_9: description: JPEG HuffMin tables fields: - - bit_offset: 0 - bit_size: 32 - description: HuffMin RAM - name: HuffMin_RAM + - name: HuffMin_RAM + description: HuffMin RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB0: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB1: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB10: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB11: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB12: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB13: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB14: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB15: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB16: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB17: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB18: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB19: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB2: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB20: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB21: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB22: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB23: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB24: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB25: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB26: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB27: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB28: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB29: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB3: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB30: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB31: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB32: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB33: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB34: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB35: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB36: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB37: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB38: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB39: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB4: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB40: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB41: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB42: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB43: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB44: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB45: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB46: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB47: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB48: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB49: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB5: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB50: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB51: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB52: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB53: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB54: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB55: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB56: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB57: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB58: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB59: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB6: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB60: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB61: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB62: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB63: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB64: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB65: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB66: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB67: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB68: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB69: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB7: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB70: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB71: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB72: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB73: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB74: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB75: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB76: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB77: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB78: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB79: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB8: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB80: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB81: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB82: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB83: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/HUFFSYMB9: description: JPEG HUFFSYMB tables fields: - - bit_offset: 0 - bit_size: 32 - description: DHTSymb RAM - name: HuffSymb_RAM + - name: HuffSymb_RAM + description: DHTSymb RAM + bit_offset: 0 + bit_size: 32 fieldset/JPEG_CFR: description: JPEG clear flag register fields: - - bit_offset: 5 - bit_size: 1 - description: Clear End of Conversion Flag - name: CEOCF - - bit_offset: 6 - bit_size: 1 - description: Clear Header Parsing Done Flag - name: CHPDF + - name: CEOCF + description: Clear End of Conversion Flag + bit_offset: 5 + bit_size: 1 + - name: CHPDF + description: Clear Header Parsing Done Flag + bit_offset: 6 + bit_size: 1 fieldset/JPEG_CONFR0: description: JPEG codec configuration register 0 fields: - - bit_offset: 0 - bit_size: 1 - description: Start - name: START + - name: START + description: Start + bit_offset: 0 + bit_size: 1 fieldset/JPEG_CONFR1: description: JPEG codec configuration register 1 fields: - - bit_offset: 0 - bit_size: 2 - description: Number of color components - name: NF - - bit_offset: 3 - bit_size: 1 - description: Decoding Enable - name: DE - - bit_offset: 4 - bit_size: 2 - description: Color Space - name: COLORSPACE - - bit_offset: 6 - bit_size: 2 - description: Number of components for Scan - name: NS - - bit_offset: 8 - bit_size: 1 - description: Header Processing - name: HDR - - bit_offset: 16 - bit_size: 16 - description: Y Size - name: YSIZE + - name: NF + description: Number of color components + bit_offset: 0 + bit_size: 2 + - name: DE + description: Decoding Enable + bit_offset: 3 + bit_size: 1 + - name: COLORSPACE + description: Color Space + bit_offset: 4 + bit_size: 2 + - name: NS + description: Number of components for Scan + bit_offset: 6 + bit_size: 2 + - name: HDR + description: Header Processing + bit_offset: 8 + bit_size: 1 + - name: YSIZE + description: Y Size + bit_offset: 16 + bit_size: 16 fieldset/JPEG_CONFR2: description: JPEG codec configuration register 2 fields: - - bit_offset: 0 - bit_size: 26 - description: Number of MCU - name: NMCU + - name: NMCU + description: Number of MCU + bit_offset: 0 + bit_size: 26 fieldset/JPEG_CONFR3: description: JPEG codec configuration register 3 fields: - - bit_offset: 16 - bit_size: 16 - description: X size - name: XSIZE + - name: XSIZE + description: X size + bit_offset: 16 + bit_size: 16 fieldset/JPEG_CONFR4: description: JPEG codec configuration register 4 fields: - - bit_offset: 0 - bit_size: 1 - description: Huffman DC - name: HD - - bit_offset: 1 - bit_size: 1 - description: Huffman AC - name: HA - - bit_offset: 2 - bit_size: 2 - description: Quantization Table - name: QT - - bit_offset: 4 - bit_size: 4 - description: Number of Block - name: NB - - bit_offset: 8 - bit_size: 4 - description: Vertical Sampling Factor - name: VSF - - bit_offset: 12 - bit_size: 4 - description: Horizontal Sampling Factor - name: HSF + - name: HD + description: Huffman DC + bit_offset: 0 + bit_size: 1 + - name: HA + description: Huffman AC + bit_offset: 1 + bit_size: 1 + - name: QT + description: Quantization Table + bit_offset: 2 + bit_size: 2 + - name: NB + description: Number of Block + bit_offset: 4 + bit_size: 4 + - name: VSF + description: Vertical Sampling Factor + bit_offset: 8 + bit_size: 4 + - name: HSF + description: Horizontal Sampling Factor + bit_offset: 12 + bit_size: 4 fieldset/JPEG_CONFR5: description: JPEG codec configuration register 5 fields: - - bit_offset: 0 - bit_size: 1 - description: Huffman DC - name: HD - - bit_offset: 1 - bit_size: 1 - description: Huffman AC - name: HA - - bit_offset: 2 - bit_size: 2 - description: Quantization Table - name: QT - - bit_offset: 4 - bit_size: 4 - description: Number of Block - name: NB - - bit_offset: 8 - bit_size: 4 - description: Vertical Sampling Factor - name: VSF - - bit_offset: 12 - bit_size: 4 - description: Horizontal Sampling Factor - name: HSF + - name: HD + description: Huffman DC + bit_offset: 0 + bit_size: 1 + - name: HA + description: Huffman AC + bit_offset: 1 + bit_size: 1 + - name: QT + description: Quantization Table + bit_offset: 2 + bit_size: 2 + - name: NB + description: Number of Block + bit_offset: 4 + bit_size: 4 + - name: VSF + description: Vertical Sampling Factor + bit_offset: 8 + bit_size: 4 + - name: HSF + description: Horizontal Sampling Factor + bit_offset: 12 + bit_size: 4 fieldset/JPEG_CONFR6: description: JPEG codec configuration register 6 fields: - - bit_offset: 0 - bit_size: 1 - description: Huffman DC - name: HD - - bit_offset: 1 - bit_size: 1 - description: Huffman AC - name: HA - - bit_offset: 2 - bit_size: 2 - description: Quantization Table - name: QT - - bit_offset: 4 - bit_size: 4 - description: Number of Block - name: NB - - bit_offset: 8 - bit_size: 4 - description: Vertical Sampling Factor - name: VSF - - bit_offset: 12 - bit_size: 4 - description: Horizontal Sampling Factor - name: HSF + - name: HD + description: Huffman DC + bit_offset: 0 + bit_size: 1 + - name: HA + description: Huffman AC + bit_offset: 1 + bit_size: 1 + - name: QT + description: Quantization Table + bit_offset: 2 + bit_size: 2 + - name: NB + description: Number of Block + bit_offset: 4 + bit_size: 4 + - name: VSF + description: Vertical Sampling Factor + bit_offset: 8 + bit_size: 4 + - name: HSF + description: Horizontal Sampling Factor + bit_offset: 12 + bit_size: 4 fieldset/JPEG_CONFR7: description: JPEG codec configuration register 7 fields: - - bit_offset: 0 - bit_size: 1 - description: Huffman DC - name: HD - - bit_offset: 1 - bit_size: 1 - description: Huffman AC - name: HA - - bit_offset: 2 - bit_size: 2 - description: Quantization Table - name: QT - - bit_offset: 4 - bit_size: 4 - description: Number of Block - name: NB - - bit_offset: 8 - bit_size: 4 - description: Vertical Sampling Factor - name: VSF - - bit_offset: 12 - bit_size: 4 - description: Horizontal Sampling Factor - name: HSF + - name: HD + description: Huffman DC + bit_offset: 0 + bit_size: 1 + - name: HA + description: Huffman AC + bit_offset: 1 + bit_size: 1 + - name: QT + description: Quantization Table + bit_offset: 2 + bit_size: 2 + - name: NB + description: Number of Block + bit_offset: 4 + bit_size: 4 + - name: VSF + description: Vertical Sampling Factor + bit_offset: 8 + bit_size: 4 + - name: HSF + description: Horizontal Sampling Factor + bit_offset: 12 + bit_size: 4 fieldset/JPEG_CR: description: JPEG control register fields: - - bit_offset: 0 - bit_size: 1 - description: JPEG Core Enable - name: JCEN - - bit_offset: 1 - bit_size: 1 - description: Input FIFO Threshold Interrupt Enable - name: IFTIE - - bit_offset: 2 - bit_size: 1 - description: Input FIFO Not Full Interrupt Enable - name: IFNFIE - - bit_offset: 3 - bit_size: 1 - description: Output FIFO Threshold Interrupt Enable - name: OFTIE - - bit_offset: 4 - bit_size: 1 - description: Output FIFO Not Empty Interrupt Enable - name: OFNEIE - - bit_offset: 5 - bit_size: 1 - description: End of Conversion Interrupt Enable - name: EOCIE - - bit_offset: 6 - bit_size: 1 - description: Header Parsing Done Interrupt Enable - name: HPDIE - - bit_offset: 11 - bit_size: 1 - description: Input DMA Enable - name: IDMAEN - - bit_offset: 12 - bit_size: 1 - description: Output DMA Enable - name: ODMAEN - - bit_offset: 13 - bit_size: 1 - description: Input FIFO Flush - name: IFF - - bit_offset: 14 - bit_size: 1 - description: Output FIFO Flush - name: 'OFF' + - name: JCEN + description: JPEG Core Enable + bit_offset: 0 + bit_size: 1 + - name: IFTIE + description: Input FIFO Threshold Interrupt Enable + bit_offset: 1 + bit_size: 1 + - name: IFNFIE + description: Input FIFO Not Full Interrupt Enable + bit_offset: 2 + bit_size: 1 + - name: OFTIE + description: Output FIFO Threshold Interrupt Enable + bit_offset: 3 + bit_size: 1 + - name: OFNEIE + description: Output FIFO Not Empty Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: EOCIE + description: End of Conversion Interrupt Enable + bit_offset: 5 + bit_size: 1 + - name: HPDIE + description: Header Parsing Done Interrupt Enable + bit_offset: 6 + bit_size: 1 + - name: IDMAEN + description: Input DMA Enable + bit_offset: 11 + bit_size: 1 + - name: ODMAEN + description: Output DMA Enable + bit_offset: 12 + bit_size: 1 + - name: IFF + description: Input FIFO Flush + bit_offset: 13 + bit_size: 1 + - name: "OFF" + description: Output FIFO Flush + bit_offset: 14 + bit_size: 1 fieldset/JPEG_DIR: description: JPEG data input register fields: - - bit_offset: 0 - bit_size: 32 - description: Data Input FIFO - name: DATAIN + - name: DATAIN + description: Data Input FIFO + bit_offset: 0 + bit_size: 32 fieldset/JPEG_DOR: description: JPEG data output register fields: - - bit_offset: 0 - bit_size: 32 - description: Data Output FIFO - name: DATAOUT + - name: DATAOUT + description: Data Output FIFO + bit_offset: 0 + bit_size: 32 fieldset/JPEG_SR: description: JPEG status register fields: - - bit_offset: 1 - bit_size: 1 - description: Input FIFO Threshold Flag - name: IFTF - - bit_offset: 2 - bit_size: 1 - description: Input FIFO Not Full Flag - name: IFNFF - - bit_offset: 3 - bit_size: 1 - description: Output FIFO Threshold Flag - name: OFTF - - bit_offset: 4 - bit_size: 1 - description: Output FIFO Not Empty Flag - name: OFNEF - - bit_offset: 5 - bit_size: 1 - description: End of Conversion Flag - name: EOCF - - bit_offset: 6 - bit_size: 1 - description: Header Parsing Done Flag - name: HPDF - - bit_offset: 7 - bit_size: 1 - description: Codec Operation Flag - name: COF + - name: IFTF + description: Input FIFO Threshold Flag + bit_offset: 1 + bit_size: 1 + - name: IFNFF + description: Input FIFO Not Full Flag + bit_offset: 2 + bit_size: 1 + - name: OFTF + description: Output FIFO Threshold Flag + bit_offset: 3 + bit_size: 1 + - name: OFNEF + description: Output FIFO Not Empty Flag + bit_offset: 4 + bit_size: 1 + - name: EOCF + description: End of Conversion Flag + bit_offset: 5 + bit_size: 1 + - name: HPDF + description: Header Parsing Done Flag + bit_offset: 6 + bit_size: 1 + - name: COF + description: Codec Operation Flag + bit_offset: 7 + bit_size: 1 fieldset/QMEM0_0: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_1: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_10: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_11: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_12: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_13: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_14: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_15: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_2: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_3: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_4: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_5: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_6: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_7: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_8: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM0_9: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_0: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_1: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_10: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_11: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_12: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_13: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_14: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_15: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_2: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_3: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_4: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_5: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_6: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_7: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_8: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM1_9: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_0: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_1: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_10: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_11: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_12: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_13: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_14: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_15: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_2: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_3: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_4: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_5: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_6: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_7: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_8: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM2_9: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_0: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_1: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_10: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_11: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_12: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_13: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_14: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_15: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_2: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_3: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_4: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_5: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_6: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_7: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_8: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 fieldset/QMEM3_9: description: JPEG quantization tables fields: - - bit_offset: 0 - bit_size: 32 - description: QMem RAM - name: QMem_RAM + - name: QMem_RAM + description: QMem RAM + bit_offset: 0 + bit_size: 32 diff --git a/data/registers/lptim_g0.yaml b/data/registers/lptim_g0.yaml index 403b419..553dec5 100644 --- a/data/registers/lptim_g0.yaml +++ b/data/registers/lptim_g0.yaml @@ -260,33 +260,33 @@ enum/PRESC: bit_size: 3 variants: - name: DIV_BY_1 - value: 0x0 + value: 0 - name: DIV_BY_2 - value: 0x1 + value: 1 - name: DIV_BY_4 - value: 0x2 + value: 2 - name: DIV_BY_8 - value: 0x3 + value: 3 - name: DIV_BY_16 - value: 0x4 + value: 4 - name: DIV_BY_32 - value: 0x5 + value: 5 - name: DIV_BY_64 - value: 0x6 + value: 6 - name: DIV_BY_128 - value: 0x7 + value: 7 enum/TRIGEN: bit_size: 2 variants: - name: SOFTWARE description: software trigger (counting start is initiated by software) - value: 0x0 + value: 0 - name: RISING description: rising edge is the active edge - value: 0x1 + value: 1 - name: FALLING description: rising edge is the active edge - value: 0x2 + value: 2 - name: BOTH description: both edges are active edges - value: 0x3 + value: 3 diff --git a/data/registers/lptim_v1.yaml b/data/registers/lptim_v1.yaml index e72e219..839d7c3 100644 --- a/data/registers/lptim_v1.yaml +++ b/data/registers/lptim_v1.yaml @@ -2,222 +2,222 @@ block/LPTIM: description: Low power timer items: - - access: Read - byte_offset: 0 - description: Interrupt and Status Register - fieldset: ISR - name: ISR - - access: Write - byte_offset: 4 - description: Interrupt Clear Register - fieldset: ICR - name: ICR - - byte_offset: 8 - description: Interrupt Enable Register - fieldset: IER - name: IER - - byte_offset: 12 - description: Configuration Register - fieldset: CFGR - name: CFGR - - byte_offset: 16 - description: Control Register - fieldset: CR - name: CR - - byte_offset: 20 - description: Compare Register - fieldset: CMP - name: CMP - - byte_offset: 24 - description: Autoreload Register - fieldset: ARR - name: ARR - - access: Read - byte_offset: 28 - description: Counter Register - fieldset: CNT - name: CNT + - name: ISR + description: Interrupt and Status Register + byte_offset: 0 + access: Read + fieldset: ISR + - name: ICR + description: Interrupt Clear Register + byte_offset: 4 + access: Write + fieldset: ICR + - name: IER + description: Interrupt Enable Register + byte_offset: 8 + fieldset: IER + - name: CFGR + description: Configuration Register + byte_offset: 12 + fieldset: CFGR + - name: CR + description: Control Register + byte_offset: 16 + fieldset: CR + - name: CMP + description: Compare Register + byte_offset: 20 + fieldset: CMP + - name: ARR + description: Autoreload Register + byte_offset: 24 + fieldset: ARR + - name: CNT + description: Counter Register + byte_offset: 28 + access: Read + fieldset: CNT fieldset/ARR: description: Autoreload Register fields: - - bit_offset: 0 - bit_size: 16 - description: Auto reload value - name: ARR + - name: ARR + description: Auto reload value + bit_offset: 0 + bit_size: 16 fieldset/CFGR: description: Configuration Register fields: - - bit_offset: 0 - bit_size: 1 - description: Clock selector - name: CKSEL - - bit_offset: 1 - bit_size: 2 - description: Clock Polarity - name: CKPOL - - bit_offset: 3 - bit_size: 2 - description: Configurable digital filter for external clock - name: CKFLT - - bit_offset: 6 - bit_size: 2 - description: Configurable digital filter for trigger - name: TRGFLT - - bit_offset: 9 - bit_size: 3 - description: Clock prescaler - name: PRESC - - bit_offset: 13 - bit_size: 3 - description: Trigger selector - name: TRIGSEL - - bit_offset: 17 - bit_size: 2 - description: Trigger enable and polarity - name: TRIGEN - - bit_offset: 19 - bit_size: 1 - description: Timeout enable - name: TIMOUT - - bit_offset: 20 - bit_size: 1 - description: Waveform shape - name: WAVE - - bit_offset: 21 - bit_size: 1 - description: Waveform shape polarity - name: WAVPOL - - bit_offset: 22 - bit_size: 1 - description: Registers update mode - name: PRELOAD - - bit_offset: 23 - bit_size: 1 - description: counter mode enabled - name: COUNTMODE - - bit_offset: 24 - bit_size: 1 - description: Encoder mode enable - name: ENC + - name: CKSEL + description: Clock selector + bit_offset: 0 + bit_size: 1 + - name: CKPOL + description: Clock Polarity + bit_offset: 1 + bit_size: 2 + - name: CKFLT + description: Configurable digital filter for external clock + bit_offset: 3 + bit_size: 2 + - name: TRGFLT + description: Configurable digital filter for trigger + bit_offset: 6 + bit_size: 2 + - name: PRESC + description: Clock prescaler + bit_offset: 9 + bit_size: 3 + - name: TRIGSEL + description: Trigger selector + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity + bit_offset: 17 + bit_size: 2 + - name: TIMOUT + description: Timeout enable + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: Waveform shape polarity + bit_offset: 21 + bit_size: 1 + - name: PRELOAD + description: Registers update mode + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled + bit_offset: 23 + bit_size: 1 + - name: ENC + description: Encoder mode enable + bit_offset: 24 + bit_size: 1 fieldset/CMP: description: Compare Register fields: - - bit_offset: 0 - bit_size: 16 - description: Compare value - name: CMP + - name: CMP + description: Compare value + bit_offset: 0 + bit_size: 16 fieldset/CNT: description: Counter Register fields: - - bit_offset: 0 - bit_size: 16 - description: Counter value - name: CNT + - name: CNT + description: Counter value + bit_offset: 0 + bit_size: 16 fieldset/CR: description: Control Register fields: - - bit_offset: 0 - bit_size: 1 - description: LPTIM Enable - name: ENABLE - - bit_offset: 1 - bit_size: 1 - description: LPTIM start in single mode - name: SNGSTRT - - bit_offset: 2 - bit_size: 1 - description: Timer start in continuous mode - name: CNTSTRT + - name: ENABLE + description: LPTIM Enable + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in single mode + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in continuous mode + bit_offset: 2 + bit_size: 1 fieldset/ICR: description: Interrupt Clear Register fields: - - bit_offset: 0 - bit_size: 1 - description: compare match Clear Flag - name: CMPMCF - - bit_offset: 1 - bit_size: 1 - description: Autoreload match Clear Flag - name: ARRMCF - - bit_offset: 2 - bit_size: 1 - description: External trigger valid edge Clear Flag - name: EXTTRIGCF - - bit_offset: 3 - bit_size: 1 - description: Compare register update OK Clear Flag - name: CMPOKCF - - bit_offset: 4 - bit_size: 1 - description: Autoreload register update OK Clear Flag - name: ARROKCF - - bit_offset: 5 - bit_size: 1 - description: Direction change to UP Clear Flag - name: UPCF - - bit_offset: 6 - bit_size: 1 - description: Direction change to down Clear Flag - name: DOWNCF + - name: CMPMCF + description: compare match Clear Flag + bit_offset: 0 + bit_size: 1 + - name: ARRMCF + description: Autoreload match Clear Flag + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge Clear Flag + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register update OK Clear Flag + bit_offset: 3 + bit_size: 1 + - name: ARROKCF + description: Autoreload register update OK Clear Flag + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: Direction change to UP Clear Flag + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: Direction change to down Clear Flag + bit_offset: 6 + bit_size: 1 fieldset/IER: description: Interrupt Enable Register fields: - - bit_offset: 0 - bit_size: 1 - description: Compare match Interrupt Enable - name: CMPMIE - - bit_offset: 1 - bit_size: 1 - description: Autoreload match Interrupt Enable - name: ARRMIE - - bit_offset: 2 - bit_size: 1 - description: External trigger valid edge Interrupt Enable - name: EXTTRIGIE - - bit_offset: 3 - bit_size: 1 - description: Compare register update OK Interrupt Enable - name: CMPOKIE - - bit_offset: 4 - bit_size: 1 - description: Autoreload register update OK Interrupt Enable - name: ARROKIE - - bit_offset: 5 - bit_size: 1 - description: Direction change to UP Interrupt Enable - name: UPIE - - bit_offset: 6 - bit_size: 1 - description: Direction change to down Interrupt Enable - name: DOWNIE + - name: CMPMIE + description: Compare match Interrupt Enable + bit_offset: 0 + bit_size: 1 + - name: ARRMIE + description: Autoreload match Interrupt Enable + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register update OK Interrupt Enable + bit_offset: 3 + bit_size: 1 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: Direction change to UP Interrupt Enable + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: Direction change to down Interrupt Enable + bit_offset: 6 + bit_size: 1 fieldset/ISR: description: Interrupt and Status Register fields: - - bit_offset: 0 - bit_size: 1 - description: Compare match - name: CMPM - - bit_offset: 1 - bit_size: 1 - description: Autoreload match - name: ARRM - - bit_offset: 2 - bit_size: 1 - description: External trigger edge event - name: EXTTRIG - - bit_offset: 3 - bit_size: 1 - description: Compare register update OK - name: CMPOK - - bit_offset: 4 - bit_size: 1 - description: Autoreload register update OK - name: ARROK - - bit_offset: 5 - bit_size: 1 - description: Counter direction change down to up - name: UP - - bit_offset: 6 - bit_size: 1 - description: Counter direction change up to down - name: DOWN + - name: CMPM + description: Compare match + bit_offset: 0 + bit_size: 1 + - name: ARRM + description: Autoreload match + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register update OK + bit_offset: 3 + bit_size: 1 + - name: ARROK + description: Autoreload register update OK + bit_offset: 4 + bit_size: 1 + - name: UP + description: Counter direction change down to up + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: Counter direction change up to down + bit_offset: 6 + bit_size: 1 diff --git a/data/registers/ltdc_v1.yaml b/data/registers/ltdc_v1.yaml index db13233..90638ff 100644 --- a/data/registers/ltdc_v1.yaml +++ b/data/registers/ltdc_v1.yaml @@ -1,774 +1,766 @@ --- block/LAYER: - description: Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, - L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR + description: "Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR" items: - - byte_offset: 0 - description: Layerx Control Register - fieldset: CR - name: CR - - byte_offset: 4 - description: Layerx Window Horizontal Position Configuration Register - fieldset: WHPCR - name: WHPCR - - byte_offset: 8 - description: Layerx Window Vertical Position Configuration Register - fieldset: WVPCR - name: WVPCR - - byte_offset: 12 - description: Layerx Color Keying Configuration Register - fieldset: CKCR - name: CKCR - - byte_offset: 16 - description: Layerx Pixel Format Configuration Register - fieldset: PFCR - name: PFCR - - byte_offset: 20 - description: Layerx Constant Alpha Configuration Register - fieldset: CACR - name: CACR - - byte_offset: 24 - description: Layerx Default Color Configuration Register - fieldset: DCCR - name: DCCR - - byte_offset: 28 - description: Layerx Blending Factors Configuration Register - fieldset: BFCR - name: BFCR - - byte_offset: 40 - description: Layerx Color Frame Buffer Address Register - fieldset: CFBAR - name: CFBAR - - byte_offset: 44 - description: Layerx Color Frame Buffer Length Register - fieldset: CFBLR - name: CFBLR - - byte_offset: 48 - description: Layerx ColorFrame Buffer Line Number Register - fieldset: CFBLNR - name: CFBLNR - - access: Write - byte_offset: 64 - description: Layerx CLUT Write Register - fieldset: CLUTWR - name: CLUTWR + - name: CR + description: Layerx Control Register + byte_offset: 0 + fieldset: CR + - name: WHPCR + description: Layerx Window Horizontal Position Configuration Register + byte_offset: 4 + fieldset: WHPCR + - name: WVPCR + description: Layerx Window Vertical Position Configuration Register + byte_offset: 8 + fieldset: WVPCR + - name: CKCR + description: Layerx Color Keying Configuration Register + byte_offset: 12 + fieldset: CKCR + - name: PFCR + description: Layerx Pixel Format Configuration Register + byte_offset: 16 + fieldset: PFCR + - name: CACR + description: Layerx Constant Alpha Configuration Register + byte_offset: 20 + fieldset: CACR + - name: DCCR + description: Layerx Default Color Configuration Register + byte_offset: 24 + fieldset: DCCR + - name: BFCR + description: Layerx Blending Factors Configuration Register + byte_offset: 28 + fieldset: BFCR + - name: CFBAR + description: Layerx Color Frame Buffer Address Register + byte_offset: 40 + fieldset: CFBAR + - name: CFBLR + description: Layerx Color Frame Buffer Length Register + byte_offset: 44 + fieldset: CFBLR + - name: CFBLNR + description: Layerx ColorFrame Buffer Line Number Register + byte_offset: 48 + fieldset: CFBLNR + - name: CLUTWR + description: Layerx CLUT Write Register + byte_offset: 64 + access: Write + fieldset: CLUTWR block/LTDC: description: LCD-TFT Controller items: - - byte_offset: 8 - description: Synchronization Size Configuration Register - fieldset: SSCR - name: SSCR - - byte_offset: 12 - description: Back Porch Configuration Register - fieldset: BPCR - name: BPCR - - byte_offset: 16 - description: Active Width Configuration Register - fieldset: AWCR - name: AWCR - - byte_offset: 20 - description: Total Width Configuration Register - fieldset: TWCR - name: TWCR - - byte_offset: 24 - description: Global Control Register - fieldset: GCR - name: GCR - - byte_offset: 36 - description: Shadow Reload Configuration Register - fieldset: SRCR - name: SRCR - - byte_offset: 44 - description: Background Color Configuration Register - fieldset: BCCR - name: BCCR - - byte_offset: 52 - description: Interrupt Enable Register - fieldset: IER - name: IER - - access: Read - byte_offset: 56 - description: Interrupt Status Register - fieldset: ISR - name: ISR - - access: Write - byte_offset: 60 - description: Interrupt Clear Register - fieldset: ICR - name: ICR - - byte_offset: 64 - description: Line Interrupt Position Configuration Register - fieldset: LIPCR - name: LIPCR - - access: Read - byte_offset: 68 - description: Current Position Status Register - fieldset: CPSR - name: CPSR - - access: Read - byte_offset: 72 - description: Current Display Status Register - fieldset: CDSR - name: CDSR - - array: - len: 2 - stride: 128 - block: LAYER - byte_offset: 132 - description: Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, - L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR - name: LAYER -enum/BF1: - bit_size: 3 - variants: - - description: BF1 = constant alpha - name: Constant - value: 4 - - description: BF1 = pixel alpha * constant alpha - name: Pixel - value: 6 -enum/BF2: - bit_size: 3 - variants: - - description: BF2 = 1 - constant alpha - name: Constant - value: 5 - - description: BF2 = 1 - pixel alpha * constant alpha - name: Pixel - value: 7 -enum/CFUIF: - bit_size: 1 - variants: - - description: Clears the FUIF flag in the ISR register - name: Clear - value: 1 -enum/CLIF: - bit_size: 1 - variants: - - description: Clears the LIF flag in the ISR register - name: Clear - value: 1 -enum/CLUTEN: - bit_size: 1 - variants: - - description: Color look-up table disabled - name: Disabled - value: 0 - - description: Color look-up table enabled - name: Enabled - value: 1 -enum/COLKEN: - bit_size: 1 - variants: - - description: Color keying disabled - name: Disabled - value: 0 - - description: Color keying enabled - name: Enabled - value: 1 -enum/CRRIF: - bit_size: 1 - variants: - - description: Clears the RRIF flag in the ISR register - name: Clear - value: 1 -enum/CTERRIF: - bit_size: 1 - variants: - - description: Clears the TERRIF flag in the ISR register - name: Clear - value: 1 -enum/DEN: - bit_size: 1 - variants: - - description: Dither disabled - name: Disabled - value: 0 - - description: Dither enabled - name: Enabled - value: 1 -enum/DEPOL: - bit_size: 1 - variants: - - description: Data enable polarity is active low - name: ActiveLow - value: 0 - - description: Data enable polarity is active high - name: ActiveHigh - value: 1 -enum/FUIE: - bit_size: 1 - variants: - - description: FIFO underrun interrupt disabled - name: Disabled - value: 0 - - description: FIFO underrun interrupt enabled - name: Enabled - value: 1 -enum/FUIF: - bit_size: 1 - variants: - - description: No FIFO underrun - name: NoUnderrun - value: 0 - - description: FIFO underrun interrupt generated, if one of the layer FIFOs is empty - and pixel data is read from the FIFO - name: Underrun - value: 1 -enum/HDES: - bit_size: 1 - variants: - - description: Currently not in horizontal Data Enable phase - name: NotActive - value: 0 - - description: Currently in horizontal Data Enable phase - name: Active - value: 1 -enum/HSPOL: - bit_size: 1 - variants: - - description: Horizontal synchronization polarity is active low - name: ActiveLow - value: 0 - - description: Horizontal synchronization polarity is active high - name: ActiveHigh - value: 1 -enum/HSYNCS: - bit_size: 1 - variants: - - description: Currently not in HSYNC phase - name: NotActive - value: 0 - - description: Currently in HSYNC phase - name: Active - value: 1 -enum/IMR: - bit_size: 1 - variants: - - description: This bit is set by software and cleared only by hardware after reload - (it cannot be cleared through register write once it is set) - name: NoEffect - value: 0 - - description: The shadow registers are reloaded immediately. This bit is set by - software and cleared only by hardware after reload - name: Reload - value: 1 -enum/LEN: - bit_size: 1 - variants: - - description: Layer disabled - name: Disabled - value: 0 - - description: Layer enabled - name: Enabled - value: 1 -enum/LIE: - bit_size: 1 - variants: - - description: Line interrupt disabled - name: Disabled - value: 0 - - description: Line interrupt enabled - name: Enabled - value: 1 -enum/LIF: - bit_size: 1 - variants: - - description: Programmed line not reached - name: NotReached - value: 0 - - description: Line interrupt generated when a programmed line is reached - name: Reached - value: 1 -enum/LTDCEN: - bit_size: 1 - variants: - - description: LCD-TFT controller disabled - name: Disabled - value: 0 - - description: LCD-TFT controller enabled - name: Enabled - value: 1 -enum/PCPOL: - bit_size: 1 - variants: - - description: Pixel clock on rising edge - name: RisingEdge - value: 0 - - description: Pixel clock on falling edge - name: FallingEdge - value: 1 -enum/PF: - bit_size: 3 - variants: - - description: ARGB8888 - name: ARGB8888 - value: 0 - - description: RGB888 - name: RGB888 - value: 1 - - description: RGB565 - name: RGB565 - value: 2 - - description: ARGB1555 - name: ARGB1555 - value: 3 - - description: ARGB4444 - name: ARGB4444 - value: 4 - - description: L8 (8-bit luminance) - name: L8 - value: 5 - - description: AL44 (4-bit alpha, 4-bit luminance) - name: AL44 - value: 6 - - description: AL88 (8-bit alpha, 8-bit luminance) - name: AL88 - value: 7 -enum/RRIE: - bit_size: 1 - variants: - - description: Register reload interrupt disabled - name: Disabled - value: 0 - - description: Register reload interrupt enabled - name: Enabled - value: 1 -enum/RRIF: - bit_size: 1 - variants: - - description: No register reload - name: NoReload - value: 0 - - description: Register reload interrupt generated when a vertical blanking reload - occurs (and the first line after the active area is reached) - name: Reload - value: 1 -enum/TERRIE: - bit_size: 1 - variants: - - description: Transfer error interrupt disabled - name: Disabled - value: 0 - - description: Transfer error interrupt enabled - name: Enabled - value: 1 -enum/TERRIF: - bit_size: 1 - variants: - - description: No transfer error - name: NoError - value: 0 - - description: Transfer error interrupt generated when a bus error occurs - name: Error - value: 1 -enum/VBR: - bit_size: 1 - variants: - - description: This bit is set by software and cleared only by hardware after reload - (it cannot be cleared through register write once it is set) - name: NoEffect - value: 0 - - description: The shadow registers are reloaded during the vertical blanking period - (at the beginning of the first line after the active display area). - name: Reload - value: 1 -enum/VDES: - bit_size: 1 - variants: - - description: Currently not in vertical Data Enable phase - name: NotActive - value: 0 - - description: Currently in vertical Data Enable phase - name: Active - value: 1 -enum/VSPOL: - bit_size: 1 - variants: - - description: Vertical synchronization polarity is active low - name: ActiveLow - value: 0 - - description: Vertical synchronization polarity is active high - name: ActiveHigh - value: 1 -enum/VSYNCS: - bit_size: 1 - variants: - - description: Currently not in VSYNC phase - name: NotActive - value: 0 - - description: Currently in VSYNC phase - name: Active - value: 1 + - name: SSCR + description: Synchronization Size Configuration Register + byte_offset: 8 + fieldset: SSCR + - name: BPCR + description: Back Porch Configuration Register + byte_offset: 12 + fieldset: BPCR + - name: AWCR + description: Active Width Configuration Register + byte_offset: 16 + fieldset: AWCR + - name: TWCR + description: Total Width Configuration Register + byte_offset: 20 + fieldset: TWCR + - name: GCR + description: Global Control Register + byte_offset: 24 + fieldset: GCR + - name: SRCR + description: Shadow Reload Configuration Register + byte_offset: 36 + fieldset: SRCR + - name: BCCR + description: Background Color Configuration Register + byte_offset: 44 + fieldset: BCCR + - name: IER + description: Interrupt Enable Register + byte_offset: 52 + fieldset: IER + - name: ISR + description: Interrupt Status Register + byte_offset: 56 + access: Read + fieldset: ISR + - name: ICR + description: Interrupt Clear Register + byte_offset: 60 + access: Write + fieldset: ICR + - name: LIPCR + description: Line Interrupt Position Configuration Register + byte_offset: 64 + fieldset: LIPCR + - name: CPSR + description: Current Position Status Register + byte_offset: 68 + access: Read + fieldset: CPSR + - name: CDSR + description: Current Display Status Register + byte_offset: 72 + access: Read + fieldset: CDSR + - name: LAYER + description: "Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR" + array: + len: 2 + stride: 128 + byte_offset: 132 + block: LAYER fieldset/AWCR: description: Active Width Configuration Register fields: - - bit_offset: 0 - bit_size: 11 - description: Accumulated Active Height (in units of horizontal scan line) - name: AAH - - bit_offset: 16 - bit_size: 12 - description: Accumulated Active Width (in units of pixel clock period) - name: AAW + - name: AAH + description: Accumulated Active Height (in units of horizontal scan line) + bit_offset: 0 + bit_size: 11 + - name: AAW + description: Accumulated Active Width (in units of pixel clock period) + bit_offset: 16 + bit_size: 12 fieldset/BCCR: description: Background Color Configuration Register fields: - - bit_offset: 0 - bit_size: 8 - description: Background color blue value - name: BCBLUE - - bit_offset: 8 - bit_size: 8 - description: Background color green value - name: BCGREEN - - bit_offset: 16 - bit_size: 8 - description: Background color red value - name: BCRED + - name: BCBLUE + description: Background color blue value + bit_offset: 0 + bit_size: 8 + - name: BCGREEN + description: Background color green value + bit_offset: 8 + bit_size: 8 + - name: BCRED + description: Background color red value + bit_offset: 16 + bit_size: 8 fieldset/BFCR: description: Layerx Blending Factors Configuration Register fields: - - array: - len: 2 - stride: 8 - bit_offset: 0 - bit_size: 3 - description: Blending Factor 2 - enum: BF2 - name: BF + - name: BF + description: Blending Factor 2 + bit_offset: 0 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: BF2 fieldset/BPCR: description: Back Porch Configuration Register fields: - - bit_offset: 0 - bit_size: 11 - description: Accumulated Vertical back porch (in units of horizontal scan line) - name: AVBP - - bit_offset: 16 - bit_size: 12 - description: Accumulated Horizontal back porch (in units of pixel clock period) - name: AHBP + - name: AVBP + description: Accumulated Vertical back porch (in units of horizontal scan line) + bit_offset: 0 + bit_size: 11 + - name: AHBP + description: Accumulated Horizontal back porch (in units of pixel clock period) + bit_offset: 16 + bit_size: 12 fieldset/CACR: description: Layerx Constant Alpha Configuration Register fields: - - bit_offset: 0 - bit_size: 8 - description: Constant Alpha - name: CONSTA + - name: CONSTA + description: Constant Alpha + bit_offset: 0 + bit_size: 8 fieldset/CDSR: description: Current Display Status Register fields: - - bit_offset: 0 - bit_size: 1 - description: Vertical Data Enable display Status - enum: VDES - name: VDES - - bit_offset: 1 - bit_size: 1 - description: Horizontal Data Enable display Status - enum: HDES - name: HDES - - bit_offset: 2 - bit_size: 1 - description: Vertical Synchronization display Status - enum: VSYNCS - name: VSYNCS - - bit_offset: 3 - bit_size: 1 - description: Horizontal Synchronization display Status - enum: HSYNCS - name: HSYNCS + - name: VDES + description: Vertical Data Enable display Status + bit_offset: 0 + bit_size: 1 + enum: VDES + - name: HDES + description: Horizontal Data Enable display Status + bit_offset: 1 + bit_size: 1 + enum: HDES + - name: VSYNCS + description: Vertical Synchronization display Status + bit_offset: 2 + bit_size: 1 + enum: VSYNCS + - name: HSYNCS + description: Horizontal Synchronization display Status + bit_offset: 3 + bit_size: 1 + enum: HSYNCS fieldset/CFBAR: description: Layerx Color Frame Buffer Address Register fields: - - bit_offset: 0 - bit_size: 32 - description: Color Frame Buffer Start Address - name: CFBADD + - name: CFBADD + description: Color Frame Buffer Start Address + bit_offset: 0 + bit_size: 32 fieldset/CFBLNR: description: Layerx ColorFrame Buffer Line Number Register fields: - - bit_offset: 0 - bit_size: 11 - description: Frame Buffer Line Number - name: CFBLNBR + - name: CFBLNBR + description: Frame Buffer Line Number + bit_offset: 0 + bit_size: 11 fieldset/CFBLR: description: Layerx Color Frame Buffer Length Register fields: - - bit_offset: 0 - bit_size: 13 - description: Color Frame Buffer Line Length - name: CFBLL - - bit_offset: 16 - bit_size: 13 - description: Color Frame Buffer Pitch in bytes - name: CFBP + - name: CFBLL + description: Color Frame Buffer Line Length + bit_offset: 0 + bit_size: 13 + - name: CFBP + description: Color Frame Buffer Pitch in bytes + bit_offset: 16 + bit_size: 13 fieldset/CKCR: description: Layerx Color Keying Configuration Register fields: - - bit_offset: 0 - bit_size: 8 - description: Color Key Blue value - name: CKBLUE - - bit_offset: 8 - bit_size: 8 - description: Color Key Green value - name: CKGREEN - - bit_offset: 16 - bit_size: 8 - description: Color Key Red value - name: CKRED + - name: CKBLUE + description: Color Key Blue value + bit_offset: 0 + bit_size: 8 + - name: CKGREEN + description: Color Key Green value + bit_offset: 8 + bit_size: 8 + - name: CKRED + description: Color Key Red value + bit_offset: 16 + bit_size: 8 fieldset/CLUTWR: description: Layerx CLUT Write Register fields: - - bit_offset: 0 - bit_size: 8 - description: Blue value - name: BLUE - - bit_offset: 8 - bit_size: 8 - description: Green value - name: GREEN - - bit_offset: 16 - bit_size: 8 - description: Red value - name: RED - - bit_offset: 24 - bit_size: 8 - description: CLUT Address - name: CLUTADD + - name: BLUE + description: Blue value + bit_offset: 0 + bit_size: 8 + - name: GREEN + description: Green value + bit_offset: 8 + bit_size: 8 + - name: RED + description: Red value + bit_offset: 16 + bit_size: 8 + - name: CLUTADD + description: CLUT Address + bit_offset: 24 + bit_size: 8 fieldset/CPSR: description: Current Position Status Register fields: - - bit_offset: 0 - bit_size: 16 - description: Current Y Position - name: CYPOS - - bit_offset: 16 - bit_size: 16 - description: Current X Position - name: CXPOS + - name: CYPOS + description: Current Y Position + bit_offset: 0 + bit_size: 16 + - name: CXPOS + description: Current X Position + bit_offset: 16 + bit_size: 16 fieldset/CR: description: Layerx Control Register fields: - - bit_offset: 0 - bit_size: 1 - description: Layer Enable - enum: LEN - name: LEN - - bit_offset: 1 - bit_size: 1 - description: Color Keying Enable - enum: COLKEN - name: COLKEN - - bit_offset: 4 - bit_size: 1 - description: Color Look-Up Table Enable - enum: CLUTEN - name: CLUTEN + - name: LEN + description: Layer Enable + bit_offset: 0 + bit_size: 1 + enum: LEN + - name: COLKEN + description: Color Keying Enable + bit_offset: 1 + bit_size: 1 + enum: COLKEN + - name: CLUTEN + description: Color Look-Up Table Enable + bit_offset: 4 + bit_size: 1 + enum: CLUTEN fieldset/DCCR: description: Layerx Default Color Configuration Register fields: - - bit_offset: 0 - bit_size: 8 - description: Default Color Blue - name: DCBLUE - - bit_offset: 8 - bit_size: 8 - description: Default Color Green - name: DCGREEN - - bit_offset: 16 - bit_size: 8 - description: Default Color Red - name: DCRED - - bit_offset: 24 - bit_size: 8 - description: Default Color Alpha - name: DCALPHA + - name: DCBLUE + description: Default Color Blue + bit_offset: 0 + bit_size: 8 + - name: DCGREEN + description: Default Color Green + bit_offset: 8 + bit_size: 8 + - name: DCRED + description: Default Color Red + bit_offset: 16 + bit_size: 8 + - name: DCALPHA + description: Default Color Alpha + bit_offset: 24 + bit_size: 8 fieldset/GCR: description: Global Control Register fields: - - bit_offset: 0 - bit_size: 1 - description: LCD-TFT controller enable bit - enum: LTDCEN - name: LTDCEN - - bit_offset: 4 - bit_size: 3 - description: Dither Blue Width - name: DBW - - bit_offset: 8 - bit_size: 3 - description: Dither Green Width - name: DGW - - bit_offset: 12 - bit_size: 3 - description: Dither Red Width - name: DRW - - bit_offset: 16 - bit_size: 1 - description: Dither Enable - enum: DEN - name: DEN - - bit_offset: 28 - bit_size: 1 - description: Pixel Clock Polarity - enum: PCPOL - name: PCPOL - - bit_offset: 29 - bit_size: 1 - description: Data Enable Polarity - enum: DEPOL - name: DEPOL - - bit_offset: 30 - bit_size: 1 - description: Vertical Synchronization Polarity - enum: VSPOL - name: VSPOL - - bit_offset: 31 - bit_size: 1 - description: Horizontal Synchronization Polarity - enum: HSPOL - name: HSPOL + - name: LTDCEN + description: LCD-TFT controller enable bit + bit_offset: 0 + bit_size: 1 + enum: LTDCEN + - name: DBW + description: Dither Blue Width + bit_offset: 4 + bit_size: 3 + - name: DGW + description: Dither Green Width + bit_offset: 8 + bit_size: 3 + - name: DRW + description: Dither Red Width + bit_offset: 12 + bit_size: 3 + - name: DEN + description: Dither Enable + bit_offset: 16 + bit_size: 1 + enum: DEN + - name: PCPOL + description: Pixel Clock Polarity + bit_offset: 28 + bit_size: 1 + enum: PCPOL + - name: DEPOL + description: Data Enable Polarity + bit_offset: 29 + bit_size: 1 + enum: DEPOL + - name: VSPOL + description: Vertical Synchronization Polarity + bit_offset: 30 + bit_size: 1 + enum: VSPOL + - name: HSPOL + description: Horizontal Synchronization Polarity + bit_offset: 31 + bit_size: 1 + enum: HSPOL fieldset/ICR: description: Interrupt Clear Register fields: - - bit_offset: 0 - bit_size: 1 - description: Clears the Line Interrupt Flag - enum: CLIF - name: CLIF - - bit_offset: 1 - bit_size: 1 - description: Clears the FIFO Underrun Interrupt flag - enum: CFUIF - name: CFUIF - - bit_offset: 2 - bit_size: 1 - description: Clears the Transfer Error Interrupt Flag - enum: CTERRIF - name: CTERRIF - - bit_offset: 3 - bit_size: 1 - description: Clears Register Reload Interrupt Flag - enum: CRRIF - name: CRRIF + - name: CLIF + description: Clears the Line Interrupt Flag + bit_offset: 0 + bit_size: 1 + enum: CLIF + - name: CFUIF + description: Clears the FIFO Underrun Interrupt flag + bit_offset: 1 + bit_size: 1 + enum: CFUIF + - name: CTERRIF + description: Clears the Transfer Error Interrupt Flag + bit_offset: 2 + bit_size: 1 + enum: CTERRIF + - name: CRRIF + description: Clears Register Reload Interrupt Flag + bit_offset: 3 + bit_size: 1 + enum: CRRIF fieldset/IER: description: Interrupt Enable Register fields: - - bit_offset: 0 - bit_size: 1 - description: Line Interrupt Enable - enum: LIE - name: LIE - - bit_offset: 1 - bit_size: 1 - description: FIFO Underrun Interrupt Enable - enum: FUIE - name: FUIE - - bit_offset: 2 - bit_size: 1 - description: Transfer Error Interrupt Enable - enum: TERRIE - name: TERRIE - - bit_offset: 3 - bit_size: 1 - description: Register Reload interrupt enable - enum: RRIE - name: RRIE + - name: LIE + description: Line Interrupt Enable + bit_offset: 0 + bit_size: 1 + enum: LIE + - name: FUIE + description: FIFO Underrun Interrupt Enable + bit_offset: 1 + bit_size: 1 + enum: FUIE + - name: TERRIE + description: Transfer Error Interrupt Enable + bit_offset: 2 + bit_size: 1 + enum: TERRIE + - name: RRIE + description: Register Reload interrupt enable + bit_offset: 3 + bit_size: 1 + enum: RRIE fieldset/ISR: description: Interrupt Status Register fields: - - bit_offset: 0 - bit_size: 1 - description: Line Interrupt flag - enum: LIF - name: LIF - - bit_offset: 1 - bit_size: 1 - description: FIFO Underrun Interrupt flag - enum: FUIF - name: FUIF - - bit_offset: 2 - bit_size: 1 - description: Transfer Error interrupt flag - enum: TERRIF - name: TERRIF - - bit_offset: 3 - bit_size: 1 - description: Register Reload Interrupt Flag - enum: RRIF - name: RRIF + - name: LIF + description: Line Interrupt flag + bit_offset: 0 + bit_size: 1 + enum: LIF + - name: FUIF + description: FIFO Underrun Interrupt flag + bit_offset: 1 + bit_size: 1 + enum: FUIF + - name: TERRIF + description: Transfer Error interrupt flag + bit_offset: 2 + bit_size: 1 + enum: TERRIF + - name: RRIF + description: Register Reload Interrupt Flag + bit_offset: 3 + bit_size: 1 + enum: RRIF fieldset/LIPCR: description: Line Interrupt Position Configuration Register fields: - - bit_offset: 0 - bit_size: 11 - description: Line Interrupt Position - name: LIPOS + - name: LIPOS + description: Line Interrupt Position + bit_offset: 0 + bit_size: 11 fieldset/PFCR: description: Layerx Pixel Format Configuration Register fields: - - bit_offset: 0 - bit_size: 3 - description: Pixel Format - enum: PF - name: PF + - name: PF + description: Pixel Format + bit_offset: 0 + bit_size: 3 + enum: PF fieldset/SRCR: description: Shadow Reload Configuration Register fields: - - bit_offset: 0 - bit_size: 1 - description: Immediate Reload - enum: IMR - name: IMR - - bit_offset: 1 - bit_size: 1 - description: Vertical Blanking Reload - enum: VBR - name: VBR + - name: IMR + description: Immediate Reload + bit_offset: 0 + bit_size: 1 + enum: IMR + - name: VBR + description: Vertical Blanking Reload + bit_offset: 1 + bit_size: 1 + enum: VBR fieldset/SSCR: description: Synchronization Size Configuration Register fields: - - bit_offset: 0 - bit_size: 11 - description: Vertical Synchronization Height (in units of horizontal scan line) - name: VSH - - bit_offset: 16 - bit_size: 12 - description: Horizontal Synchronization Width (in units of pixel clock period) - name: HSW + - name: VSH + description: Vertical Synchronization Height (in units of horizontal scan line) + bit_offset: 0 + bit_size: 11 + - name: HSW + description: Horizontal Synchronization Width (in units of pixel clock period) + bit_offset: 16 + bit_size: 12 fieldset/TWCR: description: Total Width Configuration Register fields: - - bit_offset: 0 - bit_size: 11 - description: Total Height (in units of horizontal scan line) - name: TOTALH - - bit_offset: 16 - bit_size: 12 - description: Total Width (in units of pixel clock period) - name: TOTALW + - name: TOTALH + description: Total Height (in units of horizontal scan line) + bit_offset: 0 + bit_size: 11 + - name: TOTALW + description: Total Width (in units of pixel clock period) + bit_offset: 16 + bit_size: 12 fieldset/WHPCR: description: Layerx Window Horizontal Position Configuration Register fields: - - bit_offset: 0 - bit_size: 12 - description: Window Horizontal Start Position - name: WHSTPOS - - bit_offset: 16 - bit_size: 12 - description: Window Horizontal Stop Position - name: WHSPPOS + - name: WHSTPOS + description: Window Horizontal Start Position + bit_offset: 0 + bit_size: 12 + - name: WHSPPOS + description: Window Horizontal Stop Position + bit_offset: 16 + bit_size: 12 fieldset/WVPCR: description: Layerx Window Vertical Position Configuration Register fields: - - bit_offset: 0 - bit_size: 11 - description: Window Vertical Start Position - name: WVSTPOS - - bit_offset: 16 - bit_size: 11 - description: Window Vertical Stop Position - name: WVSPPOS + - name: WVSTPOS + description: Window Vertical Start Position + bit_offset: 0 + bit_size: 11 + - name: WVSPPOS + description: Window Vertical Stop Position + bit_offset: 16 + bit_size: 11 +enum/BF1: + bit_size: 3 + variants: + - name: Constant + description: BF1 = constant alpha + value: 4 + - name: Pixel + description: BF1 = pixel alpha * constant alpha + value: 6 +enum/BF2: + bit_size: 3 + variants: + - name: Constant + description: BF2 = 1 - constant alpha + value: 5 + - name: Pixel + description: BF2 = 1 - pixel alpha * constant alpha + value: 7 +enum/CFUIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the FUIF flag in the ISR register + value: 1 +enum/CLIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the LIF flag in the ISR register + value: 1 +enum/CLUTEN: + bit_size: 1 + variants: + - name: Disabled + description: Color look-up table disabled + value: 0 + - name: Enabled + description: Color look-up table enabled + value: 1 +enum/COLKEN: + bit_size: 1 + variants: + - name: Disabled + description: Color keying disabled + value: 0 + - name: Enabled + description: Color keying enabled + value: 1 +enum/CRRIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the RRIF flag in the ISR register + value: 1 +enum/CTERRIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the TERRIF flag in the ISR register + value: 1 +enum/DEN: + bit_size: 1 + variants: + - name: Disabled + description: Dither disabled + value: 0 + - name: Enabled + description: Dither enabled + value: 1 +enum/DEPOL: + bit_size: 1 + variants: + - name: ActiveLow + description: Data enable polarity is active low + value: 0 + - name: ActiveHigh + description: Data enable polarity is active high + value: 1 +enum/FUIE: + bit_size: 1 + variants: + - name: Disabled + description: FIFO underrun interrupt disabled + value: 0 + - name: Enabled + description: FIFO underrun interrupt enabled + value: 1 +enum/FUIF: + bit_size: 1 + variants: + - name: NoUnderrun + description: No FIFO underrun + value: 0 + - name: Underrun + description: "FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO" + value: 1 +enum/HDES: + bit_size: 1 + variants: + - name: NotActive + description: Currently not in horizontal Data Enable phase + value: 0 + - name: Active + description: Currently in horizontal Data Enable phase + value: 1 +enum/HSPOL: + bit_size: 1 + variants: + - name: ActiveLow + description: Horizontal synchronization polarity is active low + value: 0 + - name: ActiveHigh + description: Horizontal synchronization polarity is active high + value: 1 +enum/HSYNCS: + bit_size: 1 + variants: + - name: NotActive + description: Currently not in HSYNC phase + value: 0 + - name: Active + description: Currently in HSYNC phase + value: 1 +enum/IMR: + bit_size: 1 + variants: + - name: NoEffect + description: This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) + value: 0 + - name: Reload + description: The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload + value: 1 +enum/LEN: + bit_size: 1 + variants: + - name: Disabled + description: Layer disabled + value: 0 + - name: Enabled + description: Layer enabled + value: 1 +enum/LIE: + bit_size: 1 + variants: + - name: Disabled + description: Line interrupt disabled + value: 0 + - name: Enabled + description: Line interrupt enabled + value: 1 +enum/LIF: + bit_size: 1 + variants: + - name: NotReached + description: Programmed line not reached + value: 0 + - name: Reached + description: Line interrupt generated when a programmed line is reached + value: 1 +enum/LTDCEN: + bit_size: 1 + variants: + - name: Disabled + description: LCD-TFT controller disabled + value: 0 + - name: Enabled + description: LCD-TFT controller enabled + value: 1 +enum/PCPOL: + bit_size: 1 + variants: + - name: RisingEdge + description: Pixel clock on rising edge + value: 0 + - name: FallingEdge + description: Pixel clock on falling edge + value: 1 +enum/PF: + bit_size: 3 + variants: + - name: ARGB8888 + description: ARGB8888 + value: 0 + - name: RGB888 + description: RGB888 + value: 1 + - name: RGB565 + description: RGB565 + value: 2 + - name: ARGB1555 + description: ARGB1555 + value: 3 + - name: ARGB4444 + description: ARGB4444 + value: 4 + - name: L8 + description: L8 (8-bit luminance) + value: 5 + - name: AL44 + description: "AL44 (4-bit alpha, 4-bit luminance)" + value: 6 + - name: AL88 + description: "AL88 (8-bit alpha, 8-bit luminance)" + value: 7 +enum/RRIE: + bit_size: 1 + variants: + - name: Disabled + description: Register reload interrupt disabled + value: 0 + - name: Enabled + description: Register reload interrupt enabled + value: 1 +enum/RRIF: + bit_size: 1 + variants: + - name: NoReload + description: No register reload + value: 0 + - name: Reload + description: Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) + value: 1 +enum/TERRIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer error interrupt disabled + value: 0 + - name: Enabled + description: Transfer error interrupt enabled + value: 1 +enum/TERRIF: + bit_size: 1 + variants: + - name: NoError + description: No transfer error + value: 0 + - name: Error + description: Transfer error interrupt generated when a bus error occurs + value: 1 +enum/VBR: + bit_size: 1 + variants: + - name: NoEffect + description: This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) + value: 0 + - name: Reload + description: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). + value: 1 +enum/VDES: + bit_size: 1 + variants: + - name: NotActive + description: Currently not in vertical Data Enable phase + value: 0 + - name: Active + description: Currently in vertical Data Enable phase + value: 1 +enum/VSPOL: + bit_size: 1 + variants: + - name: ActiveLow + description: Vertical synchronization polarity is active low + value: 0 + - name: ActiveHigh + description: Vertical synchronization polarity is active high + value: 1 +enum/VSYNCS: + bit_size: 1 + variants: + - name: NotActive + description: Currently not in VSYNC phase + value: 0 + - name: Active + description: Currently in VSYNC phase + value: 1 diff --git a/data/registers/mdios_v1.yaml b/data/registers/mdios_v1.yaml index f456733..23d33f1 100644 --- a/data/registers/mdios_v1.yaml +++ b/data/registers/mdios_v1.yaml @@ -2,1192 +2,1192 @@ block/MDIOS: description: Management data input/output slave items: - - byte_offset: 0 - description: MDIOS configuration register - fieldset: MDIOS_CR - name: MDIOS_CR - - byte_offset: 0 - description: MDIOS configuration register - fieldset: CR - name: CR - - access: Read - byte_offset: 4 - description: MDIOS write flag register - fieldset: MDIOS_WRFR - name: MDIOS_WRFR - - access: Read - byte_offset: 4 - description: MDIOS write flag register - fieldset: WRFR - name: WRFR - - byte_offset: 8 - description: MDIOS clear write flag register - fieldset: MDIOS_CWRFR - name: MDIOS_CWRFR - - byte_offset: 8 - description: MDIOS clear write flag register - fieldset: CWRFR - name: CWRFR - - access: Read - byte_offset: 12 - description: MDIOS read flag register - fieldset: MDIOS_RDFR - name: MDIOS_RDFR - - access: Read - byte_offset: 12 - description: MDIOS read flag register - fieldset: RDFR - name: RDFR - - byte_offset: 16 - description: MDIOS clear read flag register - fieldset: MDIOS_CRDFR - name: MDIOS_CRDFR - - byte_offset: 16 - description: MDIOS clear read flag register - fieldset: CRDFR - name: CRDFR - - access: Read - byte_offset: 20 - description: MDIOS status register - fieldset: MDIOS_SR - name: MDIOS_SR - - access: Read - byte_offset: 20 - description: MDIOS status register - fieldset: SR - name: SR - - byte_offset: 24 - description: MDIOS clear flag register - fieldset: MDIOS_CLRFR - name: MDIOS_CLRFR - - byte_offset: 24 - description: MDIOS clear flag register - fieldset: CLRFR - name: CLRFR - - access: Read - byte_offset: 28 - description: MDIOS input data register 0 - fieldset: MDIOS_DINR0 - name: MDIOS_DINR0 - - access: Read - array: - len: 32 - stride: 4 - byte_offset: 28 - description: MDIOS input data register %s - fieldset: DINR - name: DINR - - access: Read - byte_offset: 32 - description: MDIOS input data register 1 - fieldset: MDIOS_DINR1 - name: MDIOS_DINR1 - - access: Read - byte_offset: 36 - description: MDIOS input data register 2 - fieldset: MDIOS_DINR2 - name: MDIOS_DINR2 - - access: Read - byte_offset: 40 - description: MDIOS input data register 3 - fieldset: MDIOS_DINR3 - name: MDIOS_DINR3 - - access: Read - byte_offset: 44 - description: MDIOS input data register 4 - fieldset: MDIOS_DINR4 - name: MDIOS_DINR4 - - access: Read - byte_offset: 48 - description: MDIOS input data register 5 - fieldset: MDIOS_DINR5 - name: MDIOS_DINR5 - - access: Read - byte_offset: 52 - description: MDIOS input data register 6 - fieldset: MDIOS_DINR6 - name: MDIOS_DINR6 - - access: Read - byte_offset: 56 - description: MDIOS input data register 7 - fieldset: MDIOS_DINR7 - name: MDIOS_DINR7 - - access: Read - byte_offset: 60 - description: MDIOS input data register 8 - fieldset: MDIOS_DINR8 - name: MDIOS_DINR8 - - access: Read - byte_offset: 64 - description: MDIOS input data register 9 - fieldset: MDIOS_DINR9 - name: MDIOS_DINR9 - - access: Read - byte_offset: 68 - description: MDIOS input data register 10 - fieldset: MDIOS_DINR10 - name: MDIOS_DINR10 - - access: Read - byte_offset: 72 - description: MDIOS input data register 11 - fieldset: MDIOS_DINR11 - name: MDIOS_DINR11 - - access: Read - byte_offset: 76 - description: MDIOS input data register 12 - fieldset: MDIOS_DINR12 - name: MDIOS_DINR12 - - access: Read - byte_offset: 80 - description: MDIOS input data register 13 - fieldset: MDIOS_DINR13 - name: MDIOS_DINR13 - - access: Read - byte_offset: 84 - description: MDIOS input data register 14 - fieldset: MDIOS_DINR14 - name: MDIOS_DINR14 - - access: Read - byte_offset: 88 - description: MDIOS input data register 15 - fieldset: MDIOS_DINR15 - name: MDIOS_DINR15 - - access: Read - byte_offset: 92 - description: MDIOS input data register 16 - fieldset: MDIOS_DINR16 - name: MDIOS_DINR16 - - access: Read - byte_offset: 96 - description: MDIOS input data register 17 - fieldset: MDIOS_DINR17 - name: MDIOS_DINR17 - - access: Read - byte_offset: 100 - description: MDIOS input data register 18 - fieldset: MDIOS_DINR18 - name: MDIOS_DINR18 - - access: Read - byte_offset: 104 - description: MDIOS input data register 19 - fieldset: MDIOS_DINR19 - name: MDIOS_DINR19 - - access: Read - byte_offset: 108 - description: MDIOS input data register 20 - fieldset: MDIOS_DINR20 - name: MDIOS_DINR20 - - access: Read - byte_offset: 112 - description: MDIOS input data register 21 - fieldset: MDIOS_DINR21 - name: MDIOS_DINR21 - - access: Read - byte_offset: 116 - description: MDIOS input data register 22 - fieldset: MDIOS_DINR22 - name: MDIOS_DINR22 - - access: Read - byte_offset: 120 - description: MDIOS input data register 23 - fieldset: MDIOS_DINR23 - name: MDIOS_DINR23 - - access: Read - byte_offset: 124 - description: MDIOS input data register 24 - fieldset: MDIOS_DINR24 - name: MDIOS_DINR24 - - access: Read - byte_offset: 128 - description: MDIOS input data register 25 - fieldset: MDIOS_DINR25 - name: MDIOS_DINR25 - - access: Read - byte_offset: 132 - description: MDIOS input data register 26 - fieldset: MDIOS_DINR26 - name: MDIOS_DINR26 - - access: Read - byte_offset: 136 - description: MDIOS input data register 27 - fieldset: MDIOS_DINR27 - name: MDIOS_DINR27 - - access: Read - byte_offset: 140 - description: MDIOS input data register 28 - fieldset: MDIOS_DINR28 - name: MDIOS_DINR28 - - access: Read - byte_offset: 144 - description: MDIOS input data register 29 - fieldset: MDIOS_DINR29 - name: MDIOS_DINR29 - - access: Read - byte_offset: 148 - description: MDIOS input data register 30 - fieldset: MDIOS_DINR30 - name: MDIOS_DINR30 - - access: Read - byte_offset: 152 - description: MDIOS input data register 31 - fieldset: MDIOS_DINR31 - name: MDIOS_DINR31 - - byte_offset: 156 - description: MDIOS output data register 0 - fieldset: MDIOS_DOUTR0 - name: MDIOS_DOUTR0 - - array: - len: 32 - stride: 4 - byte_offset: 156 - description: MDIOS output data register %s - fieldset: DOUTR - name: DOUTR - - byte_offset: 160 - description: MDIOS output data register 1 - fieldset: MDIOS_DOUTR1 - name: MDIOS_DOUTR1 - - byte_offset: 164 - description: MDIOS output data register 2 - fieldset: MDIOS_DOUTR2 - name: MDIOS_DOUTR2 - - byte_offset: 168 - description: MDIOS output data register 3 - fieldset: MDIOS_DOUTR3 - name: MDIOS_DOUTR3 - - byte_offset: 172 - description: MDIOS output data register 4 - fieldset: MDIOS_DOUTR4 - name: MDIOS_DOUTR4 - - byte_offset: 176 - description: MDIOS output data register 5 - fieldset: MDIOS_DOUTR5 - name: MDIOS_DOUTR5 - - byte_offset: 180 - description: MDIOS output data register 6 - fieldset: MDIOS_DOUTR6 - name: MDIOS_DOUTR6 - - byte_offset: 184 - description: MDIOS output data register 7 - fieldset: MDIOS_DOUTR7 - name: MDIOS_DOUTR7 - - byte_offset: 188 - description: MDIOS output data register 8 - fieldset: MDIOS_DOUTR8 - name: MDIOS_DOUTR8 - - byte_offset: 192 - description: MDIOS output data register 9 - fieldset: MDIOS_DOUTR9 - name: MDIOS_DOUTR9 - - byte_offset: 196 - description: MDIOS output data register 10 - fieldset: MDIOS_DOUTR10 - name: MDIOS_DOUTR10 - - byte_offset: 200 - description: MDIOS output data register 11 - fieldset: MDIOS_DOUTR11 - name: MDIOS_DOUTR11 - - byte_offset: 204 - description: MDIOS output data register 12 - fieldset: MDIOS_DOUTR12 - name: MDIOS_DOUTR12 - - byte_offset: 208 - description: MDIOS output data register 13 - fieldset: MDIOS_DOUTR13 - name: MDIOS_DOUTR13 - - byte_offset: 212 - description: MDIOS output data register 14 - fieldset: MDIOS_DOUTR14 - name: MDIOS_DOUTR14 - - byte_offset: 216 - description: MDIOS output data register 15 - fieldset: MDIOS_DOUTR15 - name: MDIOS_DOUTR15 - - byte_offset: 220 - description: MDIOS output data register 16 - fieldset: MDIOS_DOUTR16 - name: MDIOS_DOUTR16 - - byte_offset: 224 - description: MDIOS output data register 17 - fieldset: MDIOS_DOUTR17 - name: MDIOS_DOUTR17 - - byte_offset: 228 - description: MDIOS output data register 18 - fieldset: MDIOS_DOUTR18 - name: MDIOS_DOUTR18 - - byte_offset: 232 - description: MDIOS output data register 19 - fieldset: MDIOS_DOUTR19 - name: MDIOS_DOUTR19 - - byte_offset: 236 - description: MDIOS output data register 20 - fieldset: MDIOS_DOUTR20 - name: MDIOS_DOUTR20 - - byte_offset: 240 - description: MDIOS output data register 21 - fieldset: MDIOS_DOUTR21 - name: MDIOS_DOUTR21 - - byte_offset: 244 - description: MDIOS output data register 22 - fieldset: MDIOS_DOUTR22 - name: MDIOS_DOUTR22 - - byte_offset: 248 - description: MDIOS output data register 23 - fieldset: MDIOS_DOUTR23 - name: MDIOS_DOUTR23 - - byte_offset: 252 - description: MDIOS output data register 24 - fieldset: MDIOS_DOUTR24 - name: MDIOS_DOUTR24 - - byte_offset: 256 - description: MDIOS output data register 25 - fieldset: MDIOS_DOUTR25 - name: MDIOS_DOUTR25 - - byte_offset: 260 - description: MDIOS output data register 26 - fieldset: MDIOS_DOUTR26 - name: MDIOS_DOUTR26 - - byte_offset: 264 - description: MDIOS output data register 27 - fieldset: MDIOS_DOUTR27 - name: MDIOS_DOUTR27 - - byte_offset: 268 - description: MDIOS output data register 28 - fieldset: MDIOS_DOUTR28 - name: MDIOS_DOUTR28 - - byte_offset: 272 - description: MDIOS output data register 29 - fieldset: MDIOS_DOUTR29 - name: MDIOS_DOUTR29 - - byte_offset: 276 - description: MDIOS output data register 30 - fieldset: MDIOS_DOUTR30 - name: MDIOS_DOUTR30 - - byte_offset: 280 - description: MDIOS output data register 31 - fieldset: MDIOS_DOUTR31 - name: MDIOS_DOUTR31 + - name: MDIOS_CR + description: MDIOS configuration register + byte_offset: 0 + fieldset: MDIOS_CR + - name: CR + description: MDIOS configuration register + byte_offset: 0 + fieldset: CR + - name: MDIOS_WRFR + description: MDIOS write flag register + byte_offset: 4 + access: Read + fieldset: MDIOS_WRFR + - name: WRFR + description: MDIOS write flag register + byte_offset: 4 + access: Read + fieldset: WRFR + - name: MDIOS_CWRFR + description: MDIOS clear write flag register + byte_offset: 8 + fieldset: MDIOS_CWRFR + - name: CWRFR + description: MDIOS clear write flag register + byte_offset: 8 + fieldset: CWRFR + - name: MDIOS_RDFR + description: MDIOS read flag register + byte_offset: 12 + access: Read + fieldset: MDIOS_RDFR + - name: RDFR + description: MDIOS read flag register + byte_offset: 12 + access: Read + fieldset: RDFR + - name: MDIOS_CRDFR + description: MDIOS clear read flag register + byte_offset: 16 + fieldset: MDIOS_CRDFR + - name: CRDFR + description: MDIOS clear read flag register + byte_offset: 16 + fieldset: CRDFR + - name: MDIOS_SR + description: MDIOS status register + byte_offset: 20 + access: Read + fieldset: MDIOS_SR + - name: SR + description: MDIOS status register + byte_offset: 20 + access: Read + fieldset: SR + - name: MDIOS_CLRFR + description: MDIOS clear flag register + byte_offset: 24 + fieldset: MDIOS_CLRFR + - name: CLRFR + description: MDIOS clear flag register + byte_offset: 24 + fieldset: CLRFR + - name: MDIOS_DINR0 + description: MDIOS input data register 0 + byte_offset: 28 + access: Read + fieldset: MDIOS_DINR0 + - name: DINR + description: MDIOS input data register %s + array: + len: 32 + stride: 4 + byte_offset: 28 + access: Read + fieldset: DINR + - name: MDIOS_DINR1 + description: MDIOS input data register 1 + byte_offset: 32 + access: Read + fieldset: MDIOS_DINR1 + - name: MDIOS_DINR2 + description: MDIOS input data register 2 + byte_offset: 36 + access: Read + fieldset: MDIOS_DINR2 + - name: MDIOS_DINR3 + description: MDIOS input data register 3 + byte_offset: 40 + access: Read + fieldset: MDIOS_DINR3 + - name: MDIOS_DINR4 + description: MDIOS input data register 4 + byte_offset: 44 + access: Read + fieldset: MDIOS_DINR4 + - name: MDIOS_DINR5 + description: MDIOS input data register 5 + byte_offset: 48 + access: Read + fieldset: MDIOS_DINR5 + - name: MDIOS_DINR6 + description: MDIOS input data register 6 + byte_offset: 52 + access: Read + fieldset: MDIOS_DINR6 + - name: MDIOS_DINR7 + description: MDIOS input data register 7 + byte_offset: 56 + access: Read + fieldset: MDIOS_DINR7 + - name: MDIOS_DINR8 + description: MDIOS input data register 8 + byte_offset: 60 + access: Read + fieldset: MDIOS_DINR8 + - name: MDIOS_DINR9 + description: MDIOS input data register 9 + byte_offset: 64 + access: Read + fieldset: MDIOS_DINR9 + - name: MDIOS_DINR10 + description: MDIOS input data register 10 + byte_offset: 68 + access: Read + fieldset: MDIOS_DINR10 + - name: MDIOS_DINR11 + description: MDIOS input data register 11 + byte_offset: 72 + access: Read + fieldset: MDIOS_DINR11 + - name: MDIOS_DINR12 + description: MDIOS input data register 12 + byte_offset: 76 + access: Read + fieldset: MDIOS_DINR12 + - name: MDIOS_DINR13 + description: MDIOS input data register 13 + byte_offset: 80 + access: Read + fieldset: MDIOS_DINR13 + - name: MDIOS_DINR14 + description: MDIOS input data register 14 + byte_offset: 84 + access: Read + fieldset: MDIOS_DINR14 + - name: MDIOS_DINR15 + description: MDIOS input data register 15 + byte_offset: 88 + access: Read + fieldset: MDIOS_DINR15 + - name: MDIOS_DINR16 + description: MDIOS input data register 16 + byte_offset: 92 + access: Read + fieldset: MDIOS_DINR16 + - name: MDIOS_DINR17 + description: MDIOS input data register 17 + byte_offset: 96 + access: Read + fieldset: MDIOS_DINR17 + - name: MDIOS_DINR18 + description: MDIOS input data register 18 + byte_offset: 100 + access: Read + fieldset: MDIOS_DINR18 + - name: MDIOS_DINR19 + description: MDIOS input data register 19 + byte_offset: 104 + access: Read + fieldset: MDIOS_DINR19 + - name: MDIOS_DINR20 + description: MDIOS input data register 20 + byte_offset: 108 + access: Read + fieldset: MDIOS_DINR20 + - name: MDIOS_DINR21 + description: MDIOS input data register 21 + byte_offset: 112 + access: Read + fieldset: MDIOS_DINR21 + - name: MDIOS_DINR22 + description: MDIOS input data register 22 + byte_offset: 116 + access: Read + fieldset: MDIOS_DINR22 + - name: MDIOS_DINR23 + description: MDIOS input data register 23 + byte_offset: 120 + access: Read + fieldset: MDIOS_DINR23 + - name: MDIOS_DINR24 + description: MDIOS input data register 24 + byte_offset: 124 + access: Read + fieldset: MDIOS_DINR24 + - name: MDIOS_DINR25 + description: MDIOS input data register 25 + byte_offset: 128 + access: Read + fieldset: MDIOS_DINR25 + - name: MDIOS_DINR26 + description: MDIOS input data register 26 + byte_offset: 132 + access: Read + fieldset: MDIOS_DINR26 + - name: MDIOS_DINR27 + description: MDIOS input data register 27 + byte_offset: 136 + access: Read + fieldset: MDIOS_DINR27 + - name: MDIOS_DINR28 + description: MDIOS input data register 28 + byte_offset: 140 + access: Read + fieldset: MDIOS_DINR28 + - name: MDIOS_DINR29 + description: MDIOS input data register 29 + byte_offset: 144 + access: Read + fieldset: MDIOS_DINR29 + - name: MDIOS_DINR30 + description: MDIOS input data register 30 + byte_offset: 148 + access: Read + fieldset: MDIOS_DINR30 + - name: MDIOS_DINR31 + description: MDIOS input data register 31 + byte_offset: 152 + access: Read + fieldset: MDIOS_DINR31 + - name: MDIOS_DOUTR0 + description: MDIOS output data register 0 + byte_offset: 156 + fieldset: MDIOS_DOUTR0 + - name: DOUTR + description: MDIOS output data register %s + array: + len: 32 + stride: 4 + byte_offset: 156 + fieldset: DOUTR + - name: MDIOS_DOUTR1 + description: MDIOS output data register 1 + byte_offset: 160 + fieldset: MDIOS_DOUTR1 + - name: MDIOS_DOUTR2 + description: MDIOS output data register 2 + byte_offset: 164 + fieldset: MDIOS_DOUTR2 + - name: MDIOS_DOUTR3 + description: MDIOS output data register 3 + byte_offset: 168 + fieldset: MDIOS_DOUTR3 + - name: MDIOS_DOUTR4 + description: MDIOS output data register 4 + byte_offset: 172 + fieldset: MDIOS_DOUTR4 + - name: MDIOS_DOUTR5 + description: MDIOS output data register 5 + byte_offset: 176 + fieldset: MDIOS_DOUTR5 + - name: MDIOS_DOUTR6 + description: MDIOS output data register 6 + byte_offset: 180 + fieldset: MDIOS_DOUTR6 + - name: MDIOS_DOUTR7 + description: MDIOS output data register 7 + byte_offset: 184 + fieldset: MDIOS_DOUTR7 + - name: MDIOS_DOUTR8 + description: MDIOS output data register 8 + byte_offset: 188 + fieldset: MDIOS_DOUTR8 + - name: MDIOS_DOUTR9 + description: MDIOS output data register 9 + byte_offset: 192 + fieldset: MDIOS_DOUTR9 + - name: MDIOS_DOUTR10 + description: MDIOS output data register 10 + byte_offset: 196 + fieldset: MDIOS_DOUTR10 + - name: MDIOS_DOUTR11 + description: MDIOS output data register 11 + byte_offset: 200 + fieldset: MDIOS_DOUTR11 + - name: MDIOS_DOUTR12 + description: MDIOS output data register 12 + byte_offset: 204 + fieldset: MDIOS_DOUTR12 + - name: MDIOS_DOUTR13 + description: MDIOS output data register 13 + byte_offset: 208 + fieldset: MDIOS_DOUTR13 + - name: MDIOS_DOUTR14 + description: MDIOS output data register 14 + byte_offset: 212 + fieldset: MDIOS_DOUTR14 + - name: MDIOS_DOUTR15 + description: MDIOS output data register 15 + byte_offset: 216 + fieldset: MDIOS_DOUTR15 + - name: MDIOS_DOUTR16 + description: MDIOS output data register 16 + byte_offset: 220 + fieldset: MDIOS_DOUTR16 + - name: MDIOS_DOUTR17 + description: MDIOS output data register 17 + byte_offset: 224 + fieldset: MDIOS_DOUTR17 + - name: MDIOS_DOUTR18 + description: MDIOS output data register 18 + byte_offset: 228 + fieldset: MDIOS_DOUTR18 + - name: MDIOS_DOUTR19 + description: MDIOS output data register 19 + byte_offset: 232 + fieldset: MDIOS_DOUTR19 + - name: MDIOS_DOUTR20 + description: MDIOS output data register 20 + byte_offset: 236 + fieldset: MDIOS_DOUTR20 + - name: MDIOS_DOUTR21 + description: MDIOS output data register 21 + byte_offset: 240 + fieldset: MDIOS_DOUTR21 + - name: MDIOS_DOUTR22 + description: MDIOS output data register 22 + byte_offset: 244 + fieldset: MDIOS_DOUTR22 + - name: MDIOS_DOUTR23 + description: MDIOS output data register 23 + byte_offset: 248 + fieldset: MDIOS_DOUTR23 + - name: MDIOS_DOUTR24 + description: MDIOS output data register 24 + byte_offset: 252 + fieldset: MDIOS_DOUTR24 + - name: MDIOS_DOUTR25 + description: MDIOS output data register 25 + byte_offset: 256 + fieldset: MDIOS_DOUTR25 + - name: MDIOS_DOUTR26 + description: MDIOS output data register 26 + byte_offset: 260 + fieldset: MDIOS_DOUTR26 + - name: MDIOS_DOUTR27 + description: MDIOS output data register 27 + byte_offset: 264 + fieldset: MDIOS_DOUTR27 + - name: MDIOS_DOUTR28 + description: MDIOS output data register 28 + byte_offset: 268 + fieldset: MDIOS_DOUTR28 + - name: MDIOS_DOUTR29 + description: MDIOS output data register 29 + byte_offset: 272 + fieldset: MDIOS_DOUTR29 + - name: MDIOS_DOUTR30 + description: MDIOS output data register 30 + byte_offset: 276 + fieldset: MDIOS_DOUTR30 + - name: MDIOS_DOUTR31 + description: MDIOS output data register 31 + byte_offset: 280 + fieldset: MDIOS_DOUTR31 fieldset/CLRFR: description: MDIOS clear flag register fields: - - bit_offset: 0 - bit_size: 1 - description: Clear the preamble error flag - name: CPERF - - bit_offset: 1 - bit_size: 1 - description: Clear the start error flag - name: CSERF - - bit_offset: 2 - bit_size: 1 - description: Clear the turnaround error flag - name: CTERF + - name: CPERF + description: Clear the preamble error flag + bit_offset: 0 + bit_size: 1 + - name: CSERF + description: Clear the start error flag + bit_offset: 1 + bit_size: 1 + - name: CTERF + description: Clear the turnaround error flag + bit_offset: 2 + bit_size: 1 fieldset/CR: description: MDIOS configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: Peripheral enable - name: EN - - bit_offset: 1 - bit_size: 1 - description: Register write interrupt enable - name: WRIE - - bit_offset: 2 - bit_size: 1 - description: Register Read Interrupt Enable - name: RDIE - - bit_offset: 3 - bit_size: 1 - description: Error interrupt enable - name: EIE - - bit_offset: 7 - bit_size: 1 - description: Disable Preamble Check - name: DPC - - bit_offset: 8 - bit_size: 5 - description: Slaves's address - name: PORT_ADDRESS + - name: EN + description: Peripheral enable + bit_offset: 0 + bit_size: 1 + - name: WRIE + description: Register write interrupt enable + bit_offset: 1 + bit_size: 1 + - name: RDIE + description: Register Read Interrupt Enable + bit_offset: 2 + bit_size: 1 + - name: EIE + description: Error interrupt enable + bit_offset: 3 + bit_size: 1 + - name: DPC + description: Disable Preamble Check + bit_offset: 7 + bit_size: 1 + - name: PORT_ADDRESS + description: "Slaves's address" + bit_offset: 8 + bit_size: 5 fieldset/CRDFR: description: MDIOS clear read flag register fields: - - bit_offset: 0 - bit_size: 32 - description: Clear the read flag - name: CRDF + - name: CRDF + description: Clear the read flag + bit_offset: 0 + bit_size: 32 fieldset/CWRFR: description: MDIOS clear write flag register fields: - - bit_offset: 0 - bit_size: 32 - description: Clear the write flag - name: CWRF + - name: CWRF + description: Clear the write flag + bit_offset: 0 + bit_size: 32 fieldset/DINR: description: MDIOS input data register %s fields: - - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 fieldset/DOUTR: description: MDIOS output data register %s fields: - - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 fieldset/MDIOS_CLRFR: description: MDIOS clear flag register fields: - - bit_offset: 0 - bit_size: 1 - description: Clear the preamble error flag - name: CPERF - - bit_offset: 1 - bit_size: 1 - description: Clear the start error flag - name: CSERF - - bit_offset: 2 - bit_size: 1 - description: Clear the turnaround error flag - name: CTERF + - name: CPERF + description: Clear the preamble error flag + bit_offset: 0 + bit_size: 1 + - name: CSERF + description: Clear the start error flag + bit_offset: 1 + bit_size: 1 + - name: CTERF + description: Clear the turnaround error flag + bit_offset: 2 + bit_size: 1 fieldset/MDIOS_CR: description: MDIOS configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: Peripheral enable - name: EN - - bit_offset: 1 - bit_size: 1 - description: Register write interrupt enable - name: WRIE - - bit_offset: 2 - bit_size: 1 - description: Register Read Interrupt Enable - name: RDIE - - bit_offset: 3 - bit_size: 1 - description: Error interrupt enable - name: EIE - - bit_offset: 7 - bit_size: 1 - description: Disable Preamble Check - name: DPC - - bit_offset: 8 - bit_size: 5 - description: Slaves's address - name: PORT_ADDRESS + - name: EN + description: Peripheral enable + bit_offset: 0 + bit_size: 1 + - name: WRIE + description: Register write interrupt enable + bit_offset: 1 + bit_size: 1 + - name: RDIE + description: Register Read Interrupt Enable + bit_offset: 2 + bit_size: 1 + - name: EIE + description: Error interrupt enable + bit_offset: 3 + bit_size: 1 + - name: DPC + description: Disable Preamble Check + bit_offset: 7 + bit_size: 1 + - name: PORT_ADDRESS + description: "Slaves's address" + bit_offset: 8 + bit_size: 5 fieldset/MDIOS_CRDFR: description: MDIOS clear read flag register fields: - - bit_offset: 0 - bit_size: 32 - description: Clear the read flag - name: CRDF + - name: CRDF + description: Clear the read flag + bit_offset: 0 + bit_size: 32 fieldset/MDIOS_CWRFR: description: MDIOS clear write flag register fields: - - bit_offset: 0 - bit_size: 32 - description: Clear the write flag - name: CWRF + - name: CWRF + description: Clear the write flag + bit_offset: 0 + bit_size: 32 fieldset/MDIOS_DINR0: description: MDIOS input data register 0 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR1: description: MDIOS input data register 1 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR10: description: MDIOS input data register 10 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR11: description: MDIOS input data register 11 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR12: description: MDIOS input data register 12 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR13: description: MDIOS input data register 13 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR14: description: MDIOS input data register 14 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR15: description: MDIOS input data register 15 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR16: description: MDIOS input data register 16 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR17: description: MDIOS input data register 17 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR18: description: MDIOS input data register 18 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR19: description: MDIOS input data register 19 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR2: description: MDIOS input data register 2 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR20: description: MDIOS input data register 20 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR21: description: MDIOS input data register 21 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR22: description: MDIOS input data register 22 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR23: description: MDIOS input data register 23 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR24: description: MDIOS input data register 24 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR25: description: MDIOS input data register 25 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR26: description: MDIOS input data register 26 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR27: description: MDIOS input data register 27 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR28: description: MDIOS input data register 28 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR29: description: MDIOS input data register 29 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR3: description: MDIOS input data register 3 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR30: description: MDIOS input data register 30 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR31: description: MDIOS input data register 31 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR4: description: MDIOS input data register 4 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR5: description: MDIOS input data register 5 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR6: description: MDIOS input data register 6 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR7: description: MDIOS input data register 7 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR8: description: MDIOS input data register 8 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DINR9: description: MDIOS input data register 9 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Input data received from MDIO Master during write frames - name: DIN + - name: DIN + description: Input data received from MDIO Master during write frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR0: description: MDIOS output data register 0 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR1: description: MDIOS output data register 1 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR10: description: MDIOS output data register 10 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR11: description: MDIOS output data register 11 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR12: description: MDIOS output data register 12 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR13: description: MDIOS output data register 13 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR14: description: MDIOS output data register 14 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR15: description: MDIOS output data register 15 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR16: description: MDIOS output data register 16 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR17: description: MDIOS output data register 17 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR18: description: MDIOS output data register 18 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR19: description: MDIOS output data register 19 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR2: description: MDIOS output data register 2 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR20: description: MDIOS output data register 20 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR21: description: MDIOS output data register 21 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR22: description: MDIOS output data register 22 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR23: description: MDIOS output data register 23 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR24: description: MDIOS output data register 24 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR25: description: MDIOS output data register 25 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR26: description: MDIOS output data register 26 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR27: description: MDIOS output data register 27 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR28: description: MDIOS output data register 28 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR29: description: MDIOS output data register 29 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR3: description: MDIOS output data register 3 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR30: description: MDIOS output data register 30 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR31: description: MDIOS output data register 31 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR4: description: MDIOS output data register 4 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR5: description: MDIOS output data register 5 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR6: description: MDIOS output data register 6 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR7: description: MDIOS output data register 7 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR8: description: MDIOS output data register 8 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_DOUTR9: description: MDIOS output data register 9 fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 16 - description: Output data sent to MDIO Master during read frames - name: DOUT + - name: DOUT + description: Output data sent to MDIO Master during read frames + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 fieldset/MDIOS_RDFR: description: MDIOS read flag register fields: - - bit_offset: 0 - bit_size: 32 - description: Read flags for MDIO registers 0 to 31 - name: RDF + - name: RDF + description: Read flags for MDIO registers 0 to 31 + bit_offset: 0 + bit_size: 32 fieldset/MDIOS_SR: description: MDIOS status register fields: - - bit_offset: 0 - bit_size: 1 - description: Preamble error flag - name: PERF - - bit_offset: 1 - bit_size: 1 - description: Start error flag - name: SERF - - bit_offset: 2 - bit_size: 1 - description: Turnaround error flag - name: TERF + - name: PERF + description: Preamble error flag + bit_offset: 0 + bit_size: 1 + - name: SERF + description: Start error flag + bit_offset: 1 + bit_size: 1 + - name: TERF + description: Turnaround error flag + bit_offset: 2 + bit_size: 1 fieldset/MDIOS_WRFR: description: MDIOS write flag register fields: - - bit_offset: 0 - bit_size: 32 - description: Write flags for MDIO registers 0 to 31 - name: WRF + - name: WRF + description: Write flags for MDIO registers 0 to 31 + bit_offset: 0 + bit_size: 32 fieldset/RDFR: description: MDIOS read flag register fields: - - bit_offset: 0 - bit_size: 32 - description: Read flags for MDIO registers 0 to 31 - name: RDF + - name: RDF + description: Read flags for MDIO registers 0 to 31 + bit_offset: 0 + bit_size: 32 fieldset/SR: description: MDIOS status register fields: - - bit_offset: 0 - bit_size: 1 - description: Preamble error flag - name: PERF - - bit_offset: 1 - bit_size: 1 - description: Start error flag - name: SERF - - bit_offset: 2 - bit_size: 1 - description: Turnaround error flag - name: TERF + - name: PERF + description: Preamble error flag + bit_offset: 0 + bit_size: 1 + - name: SERF + description: Start error flag + bit_offset: 1 + bit_size: 1 + - name: TERF + description: Turnaround error flag + bit_offset: 2 + bit_size: 1 fieldset/WRFR: description: MDIOS write flag register fields: - - bit_offset: 0 - bit_size: 32 - description: Write flags for MDIO registers 0 to 31 - name: WRF + - name: WRF + description: Write flags for MDIO registers 0 to 31 + bit_offset: 0 + bit_size: 32 diff --git a/data/registers/otgfs_v1.yaml b/data/registers/otgfs_v1.yaml index 08fd267..a5f339f 100644 --- a/data/registers/otgfs_v1.yaml +++ b/data/registers/otgfs_v1.yaml @@ -2,935 +2,933 @@ block/OTG_FS: description: USB on the go full speed items: - - byte_offset: 0 - description: OTG_FS control and status register (OTG_FS_GOTGCTL) - fieldset: OTG_FS_GOTGCTL - name: OTG_FS_GOTGCTL - - byte_offset: 4 - description: OTG_FS interrupt register (OTG_FS_GOTGINT) - fieldset: OTG_FS_GOTGINT - name: OTG_FS_GOTGINT - - byte_offset: 8 - description: OTG_FS AHB configuration register (OTG_FS_GAHBCFG) - fieldset: OTG_FS_GAHBCFG - name: OTG_FS_GAHBCFG - - byte_offset: 12 - description: OTG_FS USB configuration register (OTG_FS_GUSBCFG) - fieldset: OTG_FS_GUSBCFG - name: OTG_FS_GUSBCFG - - byte_offset: 16 - description: OTG_FS reset register (OTG_FS_GRSTCTL) - fieldset: OTG_FS_GRSTCTL - name: OTG_FS_GRSTCTL - - byte_offset: 20 - description: OTG_FS core interrupt register (OTG_FS_GINTSTS) - fieldset: OTG_FS_GINTSTS - name: OTG_FS_GINTSTS - - byte_offset: 24 - description: OTG_FS interrupt mask register (OTG_FS_GINTMSK) - fieldset: OTG_FS_GINTMSK - name: OTG_FS_GINTMSK - - access: Read - byte_offset: 28 - description: OTG_FS Receive status debug read(Device mode) - fieldset: OTG_FS_GRXSTSR_Device - name: OTG_FS_GRXSTSR_Device - - access: Read - byte_offset: 28 - description: OTG_FS Receive status debug read(Host mode) - fieldset: OTG_FS_GRXSTSR_Host - name: OTG_FS_GRXSTSR_Host - - access: Read - byte_offset: 32 - description: OTG status read and pop register (Device mode) - fieldset: OTG_FS_GRXSTSP_Device - name: OTG_FS_GRXSTSP_Device - - access: Read - byte_offset: 32 - description: OTG status read and pop register (Host mode) - fieldset: OTG_FS_GRXSTSP_Host - name: OTG_FS_GRXSTSP_Host - - byte_offset: 36 - description: OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) - fieldset: OTG_FS_GRXFSIZ - name: OTG_FS_GRXFSIZ - - byte_offset: 40 - description: OTG_FS Endpoint 0 Transmit FIFO size - fieldset: OTG_FS_DIEPTXF0_Device - name: OTG_FS_DIEPTXF0_Device - - byte_offset: 40 - description: OTG_FS Host non-periodic transmit FIFO size register - fieldset: OTG_FS_HNPTXFSIZ_Host - name: OTG_FS_HNPTXFSIZ_Host - - access: Read - byte_offset: 44 - description: OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) - fieldset: OTG_FS_HNPTXSTS - name: OTG_FS_HNPTXSTS - - byte_offset: 48 - description: OTG I2C access register - fieldset: OTG_FS_GI2CCTL - name: OTG_FS_GI2CCTL - - byte_offset: 56 - description: OTG_FS general core configuration register (OTG_FS_GCCFG) - fieldset: OTG_FS_GCCFG - name: OTG_FS_GCCFG - - byte_offset: 60 - description: core ID register - fieldset: OTG_FS_CID - name: OTG_FS_CID - - byte_offset: 84 - description: OTG core LPM configuration register - fieldset: OTG_FS_GLPMCFG - name: OTG_FS_GLPMCFG - - byte_offset: 88 - description: OTG power down register - fieldset: OTG_FS_GPWRDN - name: OTG_FS_GPWRDN - - byte_offset: 96 - description: OTG ADP timer, control and status register - fieldset: OTG_FS_GADPCTL - name: OTG_FS_GADPCTL - - byte_offset: 256 - description: OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) - fieldset: OTG_FS_HPTXFSIZ - name: OTG_FS_HPTXFSIZ - - byte_offset: 260 - description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF1) - fieldset: OTG_FS_DIEPTXF1 - name: OTG_FS_DIEPTXF1 - - byte_offset: 264 - description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) - fieldset: OTG_FS_DIEPTXF2 - name: OTG_FS_DIEPTXF2 - - byte_offset: 268 - description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3) - fieldset: OTG_FS_DIEPTXF3 - name: OTG_FS_DIEPTXF3 - - byte_offset: 272 - description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4) - fieldset: OTG_FS_DIEPTXF4 - name: OTG_FS_DIEPTXF4 - - byte_offset: 276 - description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF5) - fieldset: OTG_FS_DIEPTXF5 - name: OTG_FS_DIEPTXF5 + - name: OTG_FS_GOTGCTL + description: OTG_FS control and status register (OTG_FS_GOTGCTL) + byte_offset: 0 + fieldset: OTG_FS_GOTGCTL + - name: OTG_FS_GOTGINT + description: OTG_FS interrupt register (OTG_FS_GOTGINT) + byte_offset: 4 + fieldset: OTG_FS_GOTGINT + - name: OTG_FS_GAHBCFG + description: OTG_FS AHB configuration register (OTG_FS_GAHBCFG) + byte_offset: 8 + fieldset: OTG_FS_GAHBCFG + - name: OTG_FS_GUSBCFG + description: OTG_FS USB configuration register (OTG_FS_GUSBCFG) + byte_offset: 12 + fieldset: OTG_FS_GUSBCFG + - name: OTG_FS_GRSTCTL + description: OTG_FS reset register (OTG_FS_GRSTCTL) + byte_offset: 16 + fieldset: OTG_FS_GRSTCTL + - name: OTG_FS_GINTSTS + description: OTG_FS core interrupt register (OTG_FS_GINTSTS) + byte_offset: 20 + fieldset: OTG_FS_GINTSTS + - name: OTG_FS_GINTMSK + description: OTG_FS interrupt mask register (OTG_FS_GINTMSK) + byte_offset: 24 + fieldset: OTG_FS_GINTMSK + - name: OTG_FS_GRXSTSR_Device + description: OTG_FS Receive status debug read(Device mode) + byte_offset: 28 + access: Read + fieldset: OTG_FS_GRXSTSR_Device + - name: OTG_FS_GRXSTSR_Host + description: OTG_FS Receive status debug read(Host mode) + byte_offset: 28 + access: Read + fieldset: OTG_FS_GRXSTSR_Host + - name: OTG_FS_GRXSTSP_Device + description: OTG status read and pop register (Device mode) + byte_offset: 32 + access: Read + fieldset: OTG_FS_GRXSTSP_Device + - name: OTG_FS_GRXSTSP_Host + description: OTG status read and pop register (Host mode) + byte_offset: 32 + access: Read + fieldset: OTG_FS_GRXSTSP_Host + - name: OTG_FS_GRXFSIZ + description: OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) + byte_offset: 36 + fieldset: OTG_FS_GRXFSIZ + - name: OTG_FS_DIEPTXF0_Device + description: OTG_FS Endpoint 0 Transmit FIFO size + byte_offset: 40 + fieldset: OTG_FS_DIEPTXF0_Device + - name: OTG_FS_HNPTXFSIZ_Host + description: OTG_FS Host non-periodic transmit FIFO size register + byte_offset: 40 + fieldset: OTG_FS_HNPTXFSIZ_Host + - name: OTG_FS_HNPTXSTS + description: OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) + byte_offset: 44 + access: Read + fieldset: OTG_FS_HNPTXSTS + - name: OTG_FS_GI2CCTL + description: OTG I2C access register + byte_offset: 48 + fieldset: OTG_FS_GI2CCTL + - name: OTG_FS_GCCFG + description: OTG_FS general core configuration register (OTG_FS_GCCFG) + byte_offset: 56 + fieldset: OTG_FS_GCCFG + - name: OTG_FS_CID + description: core ID register + byte_offset: 60 + fieldset: OTG_FS_CID + - name: OTG_FS_GLPMCFG + description: OTG core LPM configuration register + byte_offset: 84 + fieldset: OTG_FS_GLPMCFG + - name: OTG_FS_GPWRDN + description: OTG power down register + byte_offset: 88 + fieldset: OTG_FS_GPWRDN + - name: OTG_FS_GADPCTL + description: "OTG ADP timer, control and status register" + byte_offset: 96 + fieldset: OTG_FS_GADPCTL + - name: OTG_FS_HPTXFSIZ + description: OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) + byte_offset: 256 + fieldset: OTG_FS_HPTXFSIZ + - name: OTG_FS_DIEPTXF1 + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF1) + byte_offset: 260 + fieldset: OTG_FS_DIEPTXF1 + - name: OTG_FS_DIEPTXF2 + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) + byte_offset: 264 + fieldset: OTG_FS_DIEPTXF2 + - name: OTG_FS_DIEPTXF3 + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3) + byte_offset: 268 + fieldset: OTG_FS_DIEPTXF3 + - name: OTG_FS_DIEPTXF4 + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4) + byte_offset: 272 + fieldset: OTG_FS_DIEPTXF4 + - name: OTG_FS_DIEPTXF5 + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF5) + byte_offset: 276 + fieldset: OTG_FS_DIEPTXF5 fieldset/OTG_FS_CID: description: core ID register fields: - - bit_offset: 0 - bit_size: 32 - description: Product ID field - name: PRODUCT_ID + - name: PRODUCT_ID + description: Product ID field + bit_offset: 0 + bit_size: 32 fieldset/OTG_FS_DIEPTXF0_Device: description: OTG_FS Endpoint 0 Transmit FIFO size fields: - - bit_offset: 0 - bit_size: 16 - description: Endpoint 0 transmit RAM start address - name: TX0FSA - - bit_offset: 16 - bit_size: 16 - description: Endpoint 0 TxFIFO depth - name: TX0FD + - name: TX0FSA + description: Endpoint 0 transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: TX0FD + description: Endpoint 0 TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_FS_DIEPTXF1: description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF1) fields: - - bit_offset: 0 - bit_size: 16 - description: IN endpoint FIFO2 transmit RAM start address - name: INEPTXSA - - bit_offset: 16 - bit_size: 16 - description: IN endpoint TxFIFO depth - name: INEPTXFD + - name: INEPTXSA + description: IN endpoint FIFO2 transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: INEPTXFD + description: IN endpoint TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_FS_DIEPTXF2: description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) fields: - - bit_offset: 0 - bit_size: 16 - description: IN endpoint FIFO3 transmit RAM start address - name: INEPTXSA - - bit_offset: 16 - bit_size: 16 - description: IN endpoint TxFIFO depth - name: INEPTXFD + - name: INEPTXSA + description: IN endpoint FIFO3 transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: INEPTXFD + description: IN endpoint TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_FS_DIEPTXF3: description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3) fields: - - bit_offset: 0 - bit_size: 16 - description: IN endpoint FIFO4 transmit RAM start address - name: INEPTXSA - - bit_offset: 16 - bit_size: 16 - description: IN endpoint TxFIFO depth - name: INEPTXFD + - name: INEPTXSA + description: IN endpoint FIFO4 transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: INEPTXFD + description: IN endpoint TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_FS_DIEPTXF4: description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4) fields: - - bit_offset: 0 - bit_size: 16 - description: IN endpoint FIFOx transmit RAM start address - name: INEPTXSA - - bit_offset: 16 - bit_size: 16 - description: IN endpoint Tx FIFO depth - name: INEPTXFD + - name: INEPTXSA + description: IN endpoint FIFOx transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: INEPTXFD + description: IN endpoint Tx FIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_FS_DIEPTXF5: description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF5) fields: - - bit_offset: 0 - bit_size: 16 - description: IN endpoint FIFOx transmit RAM start address - name: INEPTXSA - - bit_offset: 16 - bit_size: 16 - description: IN endpoint Tx FIFO depth - name: INEPTXFD + - name: INEPTXSA + description: IN endpoint FIFOx transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: INEPTXFD + description: IN endpoint Tx FIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_FS_GADPCTL: - description: OTG ADP timer, control and status register + description: "OTG ADP timer, control and status register" fields: - - bit_offset: 0 - bit_size: 2 - description: Probe discharge - name: PRBDSCHG - - bit_offset: 2 - bit_size: 2 - description: Probe delta - name: PRBDELTA - - bit_offset: 4 - bit_size: 2 - description: Probe period - name: PRBPER - - bit_offset: 6 - bit_size: 11 - description: Ramp time - name: RTIM - - bit_offset: 17 - bit_size: 1 - description: Enable probe - name: ENAPRB - - bit_offset: 18 - bit_size: 1 - description: Enable sense - name: ENASNS - - bit_offset: 19 - bit_size: 1 - description: ADP reset - name: ADPRST - - bit_offset: 20 - bit_size: 1 - description: ADP enable - name: ADPEN - - bit_offset: 21 - bit_size: 1 - description: ADP probe interrupt flag - name: ADPPRBIF - - bit_offset: 22 - bit_size: 1 - description: ADP sense interrupt flag - name: ADPSNSIF - - bit_offset: 23 - bit_size: 1 - description: ADP timeout interrupt flag - name: ADPTOIF - - bit_offset: 24 - bit_size: 1 - description: ADP probe interrupt mask - name: ADPPRBIM - - bit_offset: 25 - bit_size: 1 - description: ADP sense interrupt mask - name: ADPSNSIM - - bit_offset: 26 - bit_size: 1 - description: ADP timeout interrupt mask - name: ADPTOIM - - bit_offset: 27 - bit_size: 2 - description: Access request - name: AR + - name: PRBDSCHG + description: Probe discharge + bit_offset: 0 + bit_size: 2 + - name: PRBDELTA + description: Probe delta + bit_offset: 2 + bit_size: 2 + - name: PRBPER + description: Probe period + bit_offset: 4 + bit_size: 2 + - name: RTIM + description: Ramp time + bit_offset: 6 + bit_size: 11 + - name: ENAPRB + description: Enable probe + bit_offset: 17 + bit_size: 1 + - name: ENASNS + description: Enable sense + bit_offset: 18 + bit_size: 1 + - name: ADPRST + description: ADP reset + bit_offset: 19 + bit_size: 1 + - name: ADPEN + description: ADP enable + bit_offset: 20 + bit_size: 1 + - name: ADPPRBIF + description: ADP probe interrupt flag + bit_offset: 21 + bit_size: 1 + - name: ADPSNSIF + description: ADP sense interrupt flag + bit_offset: 22 + bit_size: 1 + - name: ADPTOIF + description: ADP timeout interrupt flag + bit_offset: 23 + bit_size: 1 + - name: ADPPRBIM + description: ADP probe interrupt mask + bit_offset: 24 + bit_size: 1 + - name: ADPSNSIM + description: ADP sense interrupt mask + bit_offset: 25 + bit_size: 1 + - name: ADPTOIM + description: ADP timeout interrupt mask + bit_offset: 26 + bit_size: 1 + - name: AR + description: Access request + bit_offset: 27 + bit_size: 2 fieldset/OTG_FS_GAHBCFG: description: OTG_FS AHB configuration register (OTG_FS_GAHBCFG) fields: - - bit_offset: 0 - bit_size: 1 - description: Global interrupt mask - name: GINT - - bit_offset: 7 - bit_size: 1 - description: TxFIFO empty level - name: TXFELVL - - bit_offset: 8 - bit_size: 1 - description: Periodic TxFIFO empty level - name: PTXFELVL + - name: GINT + description: Global interrupt mask + bit_offset: 0 + bit_size: 1 + - name: TXFELVL + description: TxFIFO empty level + bit_offset: 7 + bit_size: 1 + - name: PTXFELVL + description: Periodic TxFIFO empty level + bit_offset: 8 + bit_size: 1 fieldset/OTG_FS_GCCFG: description: OTG_FS general core configuration register (OTG_FS_GCCFG) fields: - - bit_offset: 0 - bit_size: 1 - description: Data contact detection (DCD) status - name: DCDET - - bit_offset: 1 - bit_size: 1 - description: Primary detection (PD) status - name: PDET - - bit_offset: 2 - bit_size: 1 - description: Secondary detection (SD) status - name: SDET - - bit_offset: 3 - bit_size: 1 - description: DM pull-up detection status - name: PS2DET - - bit_offset: 16 - bit_size: 1 - description: Power down - name: PWRDWN - - bit_offset: 17 - bit_size: 1 - description: Battery charging detector (BCD) enable - name: BCDEN - - bit_offset: 18 - bit_size: 1 - description: Data contact detection (DCD) mode enable - name: DCDEN - - bit_offset: 19 - bit_size: 1 - description: Primary detection (PD) mode enable - name: PDEN - - bit_offset: 20 - bit_size: 1 - description: Secondary detection (SD) mode enable - name: SDEN - - bit_offset: 21 - bit_size: 1 - description: USB VBUS detection enable - name: VBDEN + - name: DCDET + description: Data contact detection (DCD) status + bit_offset: 0 + bit_size: 1 + - name: PDET + description: Primary detection (PD) status + bit_offset: 1 + bit_size: 1 + - name: SDET + description: Secondary detection (SD) status + bit_offset: 2 + bit_size: 1 + - name: PS2DET + description: DM pull-up detection status + bit_offset: 3 + bit_size: 1 + - name: PWRDWN + description: Power down + bit_offset: 16 + bit_size: 1 + - name: BCDEN + description: Battery charging detector (BCD) enable + bit_offset: 17 + bit_size: 1 + - name: DCDEN + description: Data contact detection (DCD) mode enable + bit_offset: 18 + bit_size: 1 + - name: PDEN + description: Primary detection (PD) mode enable + bit_offset: 19 + bit_size: 1 + - name: SDEN + description: Secondary detection (SD) mode enable + bit_offset: 20 + bit_size: 1 + - name: VBDEN + description: USB VBUS detection enable + bit_offset: 21 + bit_size: 1 fieldset/OTG_FS_GI2CCTL: description: OTG I2C access register fields: - - bit_offset: 0 - bit_size: 8 - description: I2C Read/Write Data - name: RWDATA - - bit_offset: 8 - bit_size: 8 - description: I2C Register Address - name: REGADDR - - bit_offset: 16 - bit_size: 7 - description: I2C Address - name: ADDR - - bit_offset: 23 - bit_size: 1 - description: I2C Enable - name: I2CEN - - bit_offset: 24 - bit_size: 1 - description: I2C ACK - name: ACK - - bit_offset: 26 - bit_size: 2 - description: I2C Device Address - name: I2CDEVADR - - bit_offset: 28 - bit_size: 1 - description: I2C DatSe0 USB mode - name: I2CDATSE0 - - bit_offset: 30 - bit_size: 1 - description: Read/Write Indicator - name: RW - - bit_offset: 31 - bit_size: 1 - description: I2C Busy/Done - name: BSYDNE + - name: RWDATA + description: I2C Read/Write Data + bit_offset: 0 + bit_size: 8 + - name: REGADDR + description: I2C Register Address + bit_offset: 8 + bit_size: 8 + - name: ADDR + description: I2C Address + bit_offset: 16 + bit_size: 7 + - name: I2CEN + description: I2C Enable + bit_offset: 23 + bit_size: 1 + - name: ACK + description: I2C ACK + bit_offset: 24 + bit_size: 1 + - name: I2CDEVADR + description: I2C Device Address + bit_offset: 26 + bit_size: 2 + - name: I2CDATSE0 + description: I2C DatSe0 USB mode + bit_offset: 28 + bit_size: 1 + - name: RW + description: Read/Write Indicator + bit_offset: 30 + bit_size: 1 + - name: BSYDNE + description: I2C Busy/Done + bit_offset: 31 + bit_size: 1 fieldset/OTG_FS_GINTMSK: description: OTG_FS interrupt mask register (OTG_FS_GINTMSK) fields: - - bit_offset: 1 - bit_size: 1 - description: Mode mismatch interrupt mask - name: MMISM - - bit_offset: 2 - bit_size: 1 - description: OTG interrupt mask - name: OTGINT - - bit_offset: 3 - bit_size: 1 - description: Start of frame mask - name: SOFM - - bit_offset: 4 - bit_size: 1 - description: Receive FIFO non-empty mask - name: RXFLVLM - - bit_offset: 5 - bit_size: 1 - description: Non-periodic TxFIFO empty mask - name: NPTXFEM - - bit_offset: 6 - bit_size: 1 - description: Global non-periodic IN NAK effective mask - name: GINAKEFFM - - bit_offset: 7 - bit_size: 1 - description: Global OUT NAK effective mask - name: GONAKEFFM - - bit_offset: 10 - bit_size: 1 - description: Early suspend mask - name: ESUSPM - - bit_offset: 11 - bit_size: 1 - description: USB suspend mask - name: USBSUSPM - - bit_offset: 12 - bit_size: 1 - description: USB reset mask - name: USBRST - - bit_offset: 13 - bit_size: 1 - description: Enumeration done mask - name: ENUMDNEM - - bit_offset: 14 - bit_size: 1 - description: Isochronous OUT packet dropped interrupt mask - name: ISOODRPM - - bit_offset: 15 - bit_size: 1 - description: End of periodic frame interrupt mask - name: EOPFM - - bit_offset: 18 - bit_size: 1 - description: IN endpoints interrupt mask - name: IEPINT - - bit_offset: 19 - bit_size: 1 - description: OUT endpoints interrupt mask - name: OEPINT - - bit_offset: 20 - bit_size: 1 - description: Incomplete isochronous IN transfer mask - name: IISOIXFRM - - bit_offset: 21 - bit_size: 1 - description: Incomplete periodic transfer mask(Host mode)/Incomplete isochronous - OUT transfer mask(Device mode) - name: IPXFRM_IISOOXFRM - - bit_offset: 23 - bit_size: 1 - description: Reset detected interrupt mask - name: RSTDETM - - bit_offset: 24 - bit_size: 1 - description: Host port interrupt mask - name: PRTIM - - bit_offset: 25 - bit_size: 1 - description: Host channels interrupt mask - name: HCIM - - bit_offset: 26 - bit_size: 1 - description: Periodic TxFIFO empty mask - name: PTXFEM - - bit_offset: 27 - bit_size: 1 - description: LPM interrupt mask - name: LPMIN - - bit_offset: 28 - bit_size: 1 - description: Connector ID status change mask - name: CIDSCHGM - - bit_offset: 29 - bit_size: 1 - description: Disconnect detected interrupt mask - name: DISCINT - - bit_offset: 30 - bit_size: 1 - description: Session request/new session detected interrupt mask - name: SRQIM - - bit_offset: 31 - bit_size: 1 - description: Resume/remote wakeup detected interrupt mask - name: WUIM + - name: MMISM + description: Mode mismatch interrupt mask + bit_offset: 1 + bit_size: 1 + - name: OTGINT + description: OTG interrupt mask + bit_offset: 2 + bit_size: 1 + - name: SOFM + description: Start of frame mask + bit_offset: 3 + bit_size: 1 + - name: RXFLVLM + description: Receive FIFO non-empty mask + bit_offset: 4 + bit_size: 1 + - name: NPTXFEM + description: Non-periodic TxFIFO empty mask + bit_offset: 5 + bit_size: 1 + - name: GINAKEFFM + description: Global non-periodic IN NAK effective mask + bit_offset: 6 + bit_size: 1 + - name: GONAKEFFM + description: Global OUT NAK effective mask + bit_offset: 7 + bit_size: 1 + - name: ESUSPM + description: Early suspend mask + bit_offset: 10 + bit_size: 1 + - name: USBSUSPM + description: USB suspend mask + bit_offset: 11 + bit_size: 1 + - name: USBRST + description: USB reset mask + bit_offset: 12 + bit_size: 1 + - name: ENUMDNEM + description: Enumeration done mask + bit_offset: 13 + bit_size: 1 + - name: ISOODRPM + description: Isochronous OUT packet dropped interrupt mask + bit_offset: 14 + bit_size: 1 + - name: EOPFM + description: End of periodic frame interrupt mask + bit_offset: 15 + bit_size: 1 + - name: IEPINT + description: IN endpoints interrupt mask + bit_offset: 18 + bit_size: 1 + - name: OEPINT + description: OUT endpoints interrupt mask + bit_offset: 19 + bit_size: 1 + - name: IISOIXFRM + description: Incomplete isochronous IN transfer mask + bit_offset: 20 + bit_size: 1 + - name: IPXFRM_IISOOXFRM + description: Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) + bit_offset: 21 + bit_size: 1 + - name: RSTDETM + description: Reset detected interrupt mask + bit_offset: 23 + bit_size: 1 + - name: PRTIM + description: Host port interrupt mask + bit_offset: 24 + bit_size: 1 + - name: HCIM + description: Host channels interrupt mask + bit_offset: 25 + bit_size: 1 + - name: PTXFEM + description: Periodic TxFIFO empty mask + bit_offset: 26 + bit_size: 1 + - name: LPMIN + description: LPM interrupt mask + bit_offset: 27 + bit_size: 1 + - name: CIDSCHGM + description: Connector ID status change mask + bit_offset: 28 + bit_size: 1 + - name: DISCINT + description: Disconnect detected interrupt mask + bit_offset: 29 + bit_size: 1 + - name: SRQIM + description: Session request/new session detected interrupt mask + bit_offset: 30 + bit_size: 1 + - name: WUIM + description: Resume/remote wakeup detected interrupt mask + bit_offset: 31 + bit_size: 1 fieldset/OTG_FS_GINTSTS: description: OTG_FS core interrupt register (OTG_FS_GINTSTS) fields: - - bit_offset: 0 - bit_size: 1 - description: Current mode of operation - name: CMOD - - bit_offset: 1 - bit_size: 1 - description: Mode mismatch interrupt - name: MMIS - - bit_offset: 2 - bit_size: 1 - description: OTG interrupt - name: OTGINT - - bit_offset: 3 - bit_size: 1 - description: Start of frame - name: SOF - - bit_offset: 4 - bit_size: 1 - description: RxFIFO non-empty - name: RXFLVL - - bit_offset: 5 - bit_size: 1 - description: Non-periodic TxFIFO empty - name: NPTXFE - - bit_offset: 6 - bit_size: 1 - description: Global IN non-periodic NAK effective - name: GINAKEFF - - bit_offset: 7 - bit_size: 1 - description: Global OUT NAK effective - name: GOUTNAKEFF - - bit_offset: 10 - bit_size: 1 - description: Early suspend - name: ESUSP - - bit_offset: 11 - bit_size: 1 - description: USB suspend - name: USBSUSP - - bit_offset: 12 - bit_size: 1 - description: USB reset - name: USBRST - - bit_offset: 13 - bit_size: 1 - description: Enumeration done - name: ENUMDNE - - bit_offset: 14 - bit_size: 1 - description: Isochronous OUT packet dropped interrupt - name: ISOODRP - - bit_offset: 15 - bit_size: 1 - description: End of periodic frame interrupt - name: EOPF - - bit_offset: 18 - bit_size: 1 - description: IN endpoint interrupt - name: IEPINT - - bit_offset: 19 - bit_size: 1 - description: OUT endpoint interrupt - name: OEPINT - - bit_offset: 20 - bit_size: 1 - description: Incomplete isochronous IN transfer - name: IISOIXFR - - bit_offset: 21 - bit_size: 1 - description: Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT - transfer(Device mode) - name: IPXFR_INCOMPISOOUT - - bit_offset: 23 - bit_size: 1 - description: Reset detected interrupt - name: RSTDET - - bit_offset: 24 - bit_size: 1 - description: Host port interrupt - name: HPRTINT - - bit_offset: 25 - bit_size: 1 - description: Host channels interrupt - name: HCINT - - bit_offset: 26 - bit_size: 1 - description: Periodic TxFIFO empty - name: PTXFE - - bit_offset: 28 - bit_size: 1 - description: Connector ID status change - name: CIDSCHG - - bit_offset: 29 - bit_size: 1 - description: Disconnect detected interrupt - name: DISCINT - - bit_offset: 30 - bit_size: 1 - description: Session request/new session detected interrupt - name: SRQINT - - bit_offset: 31 - bit_size: 1 - description: Resume/remote wakeup detected interrupt - name: WKUPINT + - name: CMOD + description: Current mode of operation + bit_offset: 0 + bit_size: 1 + - name: MMIS + description: Mode mismatch interrupt + bit_offset: 1 + bit_size: 1 + - name: OTGINT + description: OTG interrupt + bit_offset: 2 + bit_size: 1 + - name: SOF + description: Start of frame + bit_offset: 3 + bit_size: 1 + - name: RXFLVL + description: RxFIFO non-empty + bit_offset: 4 + bit_size: 1 + - name: NPTXFE + description: Non-periodic TxFIFO empty + bit_offset: 5 + bit_size: 1 + - name: GINAKEFF + description: Global IN non-periodic NAK effective + bit_offset: 6 + bit_size: 1 + - name: GOUTNAKEFF + description: Global OUT NAK effective + bit_offset: 7 + bit_size: 1 + - name: ESUSP + description: Early suspend + bit_offset: 10 + bit_size: 1 + - name: USBSUSP + description: USB suspend + bit_offset: 11 + bit_size: 1 + - name: USBRST + description: USB reset + bit_offset: 12 + bit_size: 1 + - name: ENUMDNE + description: Enumeration done + bit_offset: 13 + bit_size: 1 + - name: ISOODRP + description: Isochronous OUT packet dropped interrupt + bit_offset: 14 + bit_size: 1 + - name: EOPF + description: End of periodic frame interrupt + bit_offset: 15 + bit_size: 1 + - name: IEPINT + description: IN endpoint interrupt + bit_offset: 18 + bit_size: 1 + - name: OEPINT + description: OUT endpoint interrupt + bit_offset: 19 + bit_size: 1 + - name: IISOIXFR + description: Incomplete isochronous IN transfer + bit_offset: 20 + bit_size: 1 + - name: IPXFR_INCOMPISOOUT + description: Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) + bit_offset: 21 + bit_size: 1 + - name: RSTDET + description: Reset detected interrupt + bit_offset: 23 + bit_size: 1 + - name: HPRTINT + description: Host port interrupt + bit_offset: 24 + bit_size: 1 + - name: HCINT + description: Host channels interrupt + bit_offset: 25 + bit_size: 1 + - name: PTXFE + description: Periodic TxFIFO empty + bit_offset: 26 + bit_size: 1 + - name: CIDSCHG + description: Connector ID status change + bit_offset: 28 + bit_size: 1 + - name: DISCINT + description: Disconnect detected interrupt + bit_offset: 29 + bit_size: 1 + - name: SRQINT + description: Session request/new session detected interrupt + bit_offset: 30 + bit_size: 1 + - name: WKUPINT + description: Resume/remote wakeup detected interrupt + bit_offset: 31 + bit_size: 1 fieldset/OTG_FS_GLPMCFG: description: OTG core LPM configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: LPM support enable - name: LPMEN - - bit_offset: 1 - bit_size: 1 - description: LPM token acknowledge enable - name: LPMACK - - bit_offset: 2 - bit_size: 4 - description: Best effort service latency - name: BESL - - bit_offset: 6 - bit_size: 1 - description: bRemoteWake value - name: REMWAKE - - bit_offset: 7 - bit_size: 1 - description: L1 Shallow Sleep enable - name: L1SSEN - - bit_offset: 8 - bit_size: 4 - description: BESL threshold - name: BESLTHRS - - bit_offset: 12 - bit_size: 1 - description: L1 deep sleep enable - name: L1DSEN - - bit_offset: 13 - bit_size: 2 - description: LPM response - name: LPMRST - - bit_offset: 15 - bit_size: 1 - description: Port sleep status - name: SLPSTS - - bit_offset: 16 - bit_size: 1 - description: Sleep State Resume OK - name: L1RSMOK - - bit_offset: 17 - bit_size: 4 - description: LPM Channel Index - name: LPMCHIDX - - bit_offset: 21 - bit_size: 3 - description: LPM retry count - name: LPMRCNT - - bit_offset: 24 - bit_size: 1 - description: Send LPM transaction - name: SNDLPM - - bit_offset: 25 - bit_size: 3 - description: LPM retry count status - name: LPMRCNTSTS - - bit_offset: 28 - bit_size: 1 - description: Enable best effort service latency - name: ENBESL + - name: LPMEN + description: LPM support enable + bit_offset: 0 + bit_size: 1 + - name: LPMACK + description: LPM token acknowledge enable + bit_offset: 1 + bit_size: 1 + - name: BESL + description: Best effort service latency + bit_offset: 2 + bit_size: 4 + - name: REMWAKE + description: bRemoteWake value + bit_offset: 6 + bit_size: 1 + - name: L1SSEN + description: L1 Shallow Sleep enable + bit_offset: 7 + bit_size: 1 + - name: BESLTHRS + description: BESL threshold + bit_offset: 8 + bit_size: 4 + - name: L1DSEN + description: L1 deep sleep enable + bit_offset: 12 + bit_size: 1 + - name: LPMRST + description: LPM response + bit_offset: 13 + bit_size: 2 + - name: SLPSTS + description: Port sleep status + bit_offset: 15 + bit_size: 1 + - name: L1RSMOK + description: Sleep State Resume OK + bit_offset: 16 + bit_size: 1 + - name: LPMCHIDX + description: LPM Channel Index + bit_offset: 17 + bit_size: 4 + - name: LPMRCNT + description: LPM retry count + bit_offset: 21 + bit_size: 3 + - name: SNDLPM + description: Send LPM transaction + bit_offset: 24 + bit_size: 1 + - name: LPMRCNTSTS + description: LPM retry count status + bit_offset: 25 + bit_size: 3 + - name: ENBESL + description: Enable best effort service latency + bit_offset: 28 + bit_size: 1 fieldset/OTG_FS_GOTGCTL: description: OTG_FS control and status register (OTG_FS_GOTGCTL) fields: - - bit_offset: 0 - bit_size: 1 - description: Session request success - name: SRQSCS - - bit_offset: 1 - bit_size: 1 - description: Session request - name: SRQ - - bit_offset: 2 - bit_size: 1 - description: VBUS valid override enable - name: VBVALOEN - - bit_offset: 3 - bit_size: 1 - description: VBUS valid override value - name: VBVALOVAL - - bit_offset: 4 - bit_size: 1 - description: A-peripheral session valid override enable - name: AVALOEN - - bit_offset: 5 - bit_size: 1 - description: A-peripheral session valid override value - name: AVALOVAL - - bit_offset: 6 - bit_size: 1 - description: B-peripheral session valid override enable - name: BVALOEN - - bit_offset: 7 - bit_size: 1 - description: B-peripheral session valid override value - name: BVALOVAL - - bit_offset: 8 - bit_size: 1 - description: Host negotiation success - name: HNGSCS - - bit_offset: 9 - bit_size: 1 - description: HNP request - name: HNPRQ - - bit_offset: 10 - bit_size: 1 - description: Host set HNP enable - name: HSHNPEN - - bit_offset: 11 - bit_size: 1 - description: Device HNP enabled - name: DHNPEN - - bit_offset: 12 - bit_size: 1 - description: Embedded host enable - name: EHEN - - bit_offset: 16 - bit_size: 1 - description: Connector ID status - name: CIDSTS - - bit_offset: 17 - bit_size: 1 - description: Long/short debounce time - name: DBCT - - bit_offset: 18 - bit_size: 1 - description: A-session valid - name: ASVLD - - bit_offset: 19 - bit_size: 1 - description: B-session valid - name: BSVLD - - bit_offset: 20 - bit_size: 1 - description: OTG version - name: OTGVER + - name: SRQSCS + description: Session request success + bit_offset: 0 + bit_size: 1 + - name: SRQ + description: Session request + bit_offset: 1 + bit_size: 1 + - name: VBVALOEN + description: VBUS valid override enable + bit_offset: 2 + bit_size: 1 + - name: VBVALOVAL + description: VBUS valid override value + bit_offset: 3 + bit_size: 1 + - name: AVALOEN + description: A-peripheral session valid override enable + bit_offset: 4 + bit_size: 1 + - name: AVALOVAL + description: A-peripheral session valid override value + bit_offset: 5 + bit_size: 1 + - name: BVALOEN + description: B-peripheral session valid override enable + bit_offset: 6 + bit_size: 1 + - name: BVALOVAL + description: B-peripheral session valid override value + bit_offset: 7 + bit_size: 1 + - name: HNGSCS + description: Host negotiation success + bit_offset: 8 + bit_size: 1 + - name: HNPRQ + description: HNP request + bit_offset: 9 + bit_size: 1 + - name: HSHNPEN + description: Host set HNP enable + bit_offset: 10 + bit_size: 1 + - name: DHNPEN + description: Device HNP enabled + bit_offset: 11 + bit_size: 1 + - name: EHEN + description: Embedded host enable + bit_offset: 12 + bit_size: 1 + - name: CIDSTS + description: Connector ID status + bit_offset: 16 + bit_size: 1 + - name: DBCT + description: Long/short debounce time + bit_offset: 17 + bit_size: 1 + - name: ASVLD + description: A-session valid + bit_offset: 18 + bit_size: 1 + - name: BSVLD + description: B-session valid + bit_offset: 19 + bit_size: 1 + - name: OTGVER + description: OTG version + bit_offset: 20 + bit_size: 1 fieldset/OTG_FS_GOTGINT: description: OTG_FS interrupt register (OTG_FS_GOTGINT) fields: - - bit_offset: 2 - bit_size: 1 - description: Session end detected - name: SEDET - - bit_offset: 8 - bit_size: 1 - description: Session request success status change - name: SRSSCHG - - bit_offset: 9 - bit_size: 1 - description: Host negotiation success status change - name: HNSSCHG - - bit_offset: 17 - bit_size: 1 - description: Host negotiation detected - name: HNGDET - - bit_offset: 18 - bit_size: 1 - description: A-device timeout change - name: ADTOCHG - - bit_offset: 19 - bit_size: 1 - description: Debounce done - name: DBCDNE - - bit_offset: 20 - bit_size: 1 - description: ID input pin changed - name: IDCHNG + - name: SEDET + description: Session end detected + bit_offset: 2 + bit_size: 1 + - name: SRSSCHG + description: Session request success status change + bit_offset: 8 + bit_size: 1 + - name: HNSSCHG + description: Host negotiation success status change + bit_offset: 9 + bit_size: 1 + - name: HNGDET + description: Host negotiation detected + bit_offset: 17 + bit_size: 1 + - name: ADTOCHG + description: A-device timeout change + bit_offset: 18 + bit_size: 1 + - name: DBCDNE + description: Debounce done + bit_offset: 19 + bit_size: 1 + - name: IDCHNG + description: ID input pin changed + bit_offset: 20 + bit_size: 1 fieldset/OTG_FS_GPWRDN: description: OTG power down register fields: - - bit_offset: 0 - bit_size: 1 - description: ADP module enable - name: ADPMEN - - bit_offset: 23 - bit_size: 1 - description: ADP interrupt flag - name: ADPIF + - name: ADPMEN + description: ADP module enable + bit_offset: 0 + bit_size: 1 + - name: ADPIF + description: ADP interrupt flag + bit_offset: 23 + bit_size: 1 fieldset/OTG_FS_GRSTCTL: description: OTG_FS reset register (OTG_FS_GRSTCTL) fields: - - bit_offset: 0 - bit_size: 1 - description: Core soft reset - name: CSRST - - bit_offset: 1 - bit_size: 1 - description: HCLK soft reset - name: HSRST - - bit_offset: 2 - bit_size: 1 - description: Host frame counter reset - name: FCRST - - bit_offset: 4 - bit_size: 1 - description: RxFIFO flush - name: RXFFLSH - - bit_offset: 5 - bit_size: 1 - description: TxFIFO flush - name: TXFFLSH - - bit_offset: 6 - bit_size: 5 - description: TxFIFO number - name: TXFNUM - - bit_offset: 31 - bit_size: 1 - description: AHB master idle - name: AHBIDL + - name: CSRST + description: Core soft reset + bit_offset: 0 + bit_size: 1 + - name: HSRST + description: HCLK soft reset + bit_offset: 1 + bit_size: 1 + - name: FCRST + description: Host frame counter reset + bit_offset: 2 + bit_size: 1 + - name: RXFFLSH + description: RxFIFO flush + bit_offset: 4 + bit_size: 1 + - name: TXFFLSH + description: TxFIFO flush + bit_offset: 5 + bit_size: 1 + - name: TXFNUM + description: TxFIFO number + bit_offset: 6 + bit_size: 5 + - name: AHBIDL + description: AHB master idle + bit_offset: 31 + bit_size: 1 fieldset/OTG_FS_GRXFSIZ: description: OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) fields: - - bit_offset: 0 - bit_size: 16 - description: RxFIFO depth - name: RXFD + - name: RXFD + description: RxFIFO depth + bit_offset: 0 + bit_size: 16 fieldset/OTG_FS_GRXSTSP_Device: description: OTG status read and pop register (Device mode) fields: - - bit_offset: 0 - bit_size: 4 - description: Endpoint number - name: EPNUM - - bit_offset: 4 - bit_size: 11 - description: Byte count - name: BCNT - - bit_offset: 15 - bit_size: 2 - description: Data PID - name: DPID - - bit_offset: 17 - bit_size: 4 - description: Packet status - name: PKTSTS - - bit_offset: 21 - bit_size: 4 - description: Frame number - name: FRMNUM + - name: EPNUM + description: Endpoint number + bit_offset: 0 + bit_size: 4 + - name: BCNT + description: Byte count + bit_offset: 4 + bit_size: 11 + - name: DPID + description: Data PID + bit_offset: 15 + bit_size: 2 + - name: PKTSTS + description: Packet status + bit_offset: 17 + bit_size: 4 + - name: FRMNUM + description: Frame number + bit_offset: 21 + bit_size: 4 fieldset/OTG_FS_GRXSTSP_Host: description: OTG status read and pop register (Host mode) fields: - - bit_offset: 0 - bit_size: 4 - description: Channel number - name: CHNUM - - bit_offset: 4 - bit_size: 11 - description: Byte count - name: BCNT - - bit_offset: 15 - bit_size: 2 - description: Data PID - name: DPID - - bit_offset: 17 - bit_size: 4 - description: Packet status - name: PKTSTS + - name: CHNUM + description: Channel number + bit_offset: 0 + bit_size: 4 + - name: BCNT + description: Byte count + bit_offset: 4 + bit_size: 11 + - name: DPID + description: Data PID + bit_offset: 15 + bit_size: 2 + - name: PKTSTS + description: Packet status + bit_offset: 17 + bit_size: 4 fieldset/OTG_FS_GRXSTSR_Device: description: OTG_FS Receive status debug read(Device mode) fields: - - bit_offset: 0 - bit_size: 4 - description: Endpoint number - name: EPNUM - - bit_offset: 4 - bit_size: 11 - description: Byte count - name: BCNT - - bit_offset: 15 - bit_size: 2 - description: Data PID - name: DPID - - bit_offset: 17 - bit_size: 4 - description: Packet status - name: PKTSTS - - bit_offset: 21 - bit_size: 4 - description: Frame number - name: FRMNUM + - name: EPNUM + description: Endpoint number + bit_offset: 0 + bit_size: 4 + - name: BCNT + description: Byte count + bit_offset: 4 + bit_size: 11 + - name: DPID + description: Data PID + bit_offset: 15 + bit_size: 2 + - name: PKTSTS + description: Packet status + bit_offset: 17 + bit_size: 4 + - name: FRMNUM + description: Frame number + bit_offset: 21 + bit_size: 4 fieldset/OTG_FS_GRXSTSR_Host: description: OTG_FS Receive status debug read(Host mode) fields: - - bit_offset: 0 - bit_size: 4 - description: Endpoint number - name: CHNUM - - bit_offset: 4 - bit_size: 11 - description: Byte count - name: BCNT - - bit_offset: 15 - bit_size: 2 - description: Data PID - name: DPID - - bit_offset: 17 - bit_size: 4 - description: Packet status - name: PKTSTS + - name: CHNUM + description: Endpoint number + bit_offset: 0 + bit_size: 4 + - name: BCNT + description: Byte count + bit_offset: 4 + bit_size: 11 + - name: DPID + description: Data PID + bit_offset: 15 + bit_size: 2 + - name: PKTSTS + description: Packet status + bit_offset: 17 + bit_size: 4 fieldset/OTG_FS_GUSBCFG: description: OTG_FS USB configuration register (OTG_FS_GUSBCFG) fields: - - bit_offset: 0 - bit_size: 3 - description: FS timeout calibration - name: TOCAL - - bit_offset: 6 - bit_size: 1 - description: Full Speed serial transceiver select - name: PHYSEL - - bit_offset: 8 - bit_size: 1 - description: SRP-capable - name: SRPCAP - - bit_offset: 9 - bit_size: 1 - description: HNP-capable - name: HNPCAP - - bit_offset: 10 - bit_size: 4 - description: USB turnaround time - name: TRDT - - bit_offset: 29 - bit_size: 1 - description: Force host mode - name: FHMOD - - bit_offset: 30 - bit_size: 1 - description: Force device mode - name: FDMOD + - name: TOCAL + description: FS timeout calibration + bit_offset: 0 + bit_size: 3 + - name: PHYSEL + description: Full Speed serial transceiver select + bit_offset: 6 + bit_size: 1 + - name: SRPCAP + description: SRP-capable + bit_offset: 8 + bit_size: 1 + - name: HNPCAP + description: HNP-capable + bit_offset: 9 + bit_size: 1 + - name: TRDT + description: USB turnaround time + bit_offset: 10 + bit_size: 4 + - name: FHMOD + description: Force host mode + bit_offset: 29 + bit_size: 1 + - name: FDMOD + description: Force device mode + bit_offset: 30 + bit_size: 1 fieldset/OTG_FS_HNPTXFSIZ_Host: description: OTG_FS Host non-periodic transmit FIFO size register fields: - - bit_offset: 0 - bit_size: 16 - description: Non-periodic transmit RAM start address - name: NPTXFSA - - bit_offset: 16 - bit_size: 16 - description: Non-periodic TxFIFO depth - name: NPTXFD + - name: NPTXFSA + description: Non-periodic transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: NPTXFD + description: Non-periodic TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_FS_HNPTXSTS: description: OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) fields: - - bit_offset: 0 - bit_size: 16 - description: Non-periodic TxFIFO space available - name: NPTXFSAV - - bit_offset: 16 - bit_size: 8 - description: Non-periodic transmit request queue space available - name: NPTQXSAV - - bit_offset: 24 - bit_size: 7 - description: Top of the non-periodic transmit request queue - name: NPTXQTOP + - name: NPTXFSAV + description: Non-periodic TxFIFO space available + bit_offset: 0 + bit_size: 16 + - name: NPTQXSAV + description: Non-periodic transmit request queue space available + bit_offset: 16 + bit_size: 8 + - name: NPTXQTOP + description: Top of the non-periodic transmit request queue + bit_offset: 24 + bit_size: 7 fieldset/OTG_FS_HPTXFSIZ: description: OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) fields: - - bit_offset: 0 - bit_size: 16 - description: Host periodic TxFIFO start address - name: PTXSA - - bit_offset: 16 - bit_size: 16 - description: Host periodic TxFIFO depth - name: PTXFSIZ + - name: PTXSA + description: Host periodic TxFIFO start address + bit_offset: 0 + bit_size: 16 + - name: PTXFSIZ + description: Host periodic TxFIFO depth + bit_offset: 16 + bit_size: 16 diff --git a/data/registers/otghs_v1.yaml b/data/registers/otghs_v1.yaml index 23d8fd9..b1adb8e 100644 --- a/data/registers/otghs_v1.yaml +++ b/data/registers/otghs_v1.yaml @@ -2,930 +2,929 @@ block/OTG_HS: description: USB on the go high speed items: - - byte_offset: 0 - description: OTG_HS control and status register - fieldset: OTG_HS_GOTGCTL - name: OTG_HS_GOTGCTL - - byte_offset: 4 - description: OTG_HS interrupt register - fieldset: OTG_HS_GOTGINT - name: OTG_HS_GOTGINT - - byte_offset: 8 - description: OTG_HS AHB configuration register - fieldset: OTG_HS_GAHBCFG - name: OTG_HS_GAHBCFG - - byte_offset: 12 - description: OTG_HS USB configuration register - fieldset: OTG_HS_GUSBCFG - name: OTG_HS_GUSBCFG - - byte_offset: 16 - description: OTG_HS reset register - fieldset: OTG_HS_GRSTCTL - name: OTG_HS_GRSTCTL - - byte_offset: 20 - description: OTG_HS core interrupt register - fieldset: OTG_HS_GINTSTS - name: OTG_HS_GINTSTS - - byte_offset: 24 - description: OTG_HS interrupt mask register - fieldset: OTG_HS_GINTMSK - name: OTG_HS_GINTMSK - - access: Read - byte_offset: 28 - description: OTG_HS Receive status debug read register (peripheral mode mode) - fieldset: OTG_HS_GRXSTSR_Device - name: OTG_HS_GRXSTSR_Device - - access: Read - byte_offset: 28 - description: OTG_HS Receive status debug read register (host mode) - fieldset: OTG_HS_GRXSTSR_Host - name: OTG_HS_GRXSTSR_Host - - access: Read - byte_offset: 32 - description: OTG_HS status read and pop register (peripheral mode) - fieldset: OTG_HS_GRXSTSP_Device - name: OTG_HS_GRXSTSP_Device - - access: Read - byte_offset: 32 - description: OTG_HS status read and pop register (host mode) - fieldset: OTG_HS_GRXSTSP_Host - name: OTG_HS_GRXSTSP_Host - - byte_offset: 36 - description: OTG_HS Receive FIFO size register - fieldset: OTG_HS_GRXFSIZ - name: OTG_HS_GRXFSIZ - - byte_offset: 40 - description: Endpoint 0 transmit FIFO size (peripheral mode) - fieldset: OTG_HS_DIEPTXF0_Device - name: OTG_HS_DIEPTXF0_Device - - byte_offset: 40 - description: OTG_HS nonperiodic transmit FIFO size register (host mode) - fieldset: OTG_HS_HNPTXFSIZ_Host - name: OTG_HS_HNPTXFSIZ_Host - - access: Read - byte_offset: 44 - description: OTG_HS nonperiodic transmit FIFO/queue status register - fieldset: OTG_HS_HNPTXSTS - name: OTG_HS_HNPTXSTS - - access: Read - byte_offset: 44 - description: OTG_HS nonperiodic transmit FIFO/queue status register - fieldset: OTG_HS_GNPTXSTS - name: OTG_HS_GNPTXSTS - - byte_offset: 48 - description: OTG I2C access register - fieldset: OTG_HS_GI2CCTL - name: OTG_HS_GI2CCTL - - byte_offset: 56 - description: OTG_HS general core configuration register - fieldset: OTG_HS_GCCFG - name: OTG_HS_GCCFG - - byte_offset: 60 - description: OTG_HS core ID register - fieldset: OTG_HS_CID - name: OTG_HS_CID - - byte_offset: 84 - description: OTG core LPM configuration register - fieldset: OTG_HS_GLPMCFG - name: OTG_HS_GLPMCFG - - byte_offset: 256 - description: OTG_HS Host periodic transmit FIFO size register - fieldset: OTG_HS_HPTXFSIZ - name: OTG_HS_HPTXFSIZ - - byte_offset: 260 - description: OTG_HS device IN endpoint transmit FIFO size register - fieldset: OTG_HS_DIEPTXF1 - name: OTG_HS_DIEPTXF1 - - byte_offset: 264 - description: OTG_HS device IN endpoint transmit FIFO size register - fieldset: OTG_HS_DIEPTXF2 - name: OTG_HS_DIEPTXF2 - - byte_offset: 268 - description: OTG_HS device IN endpoint transmit FIFO size register - fieldset: OTG_HS_DIEPTXF3 - name: OTG_HS_DIEPTXF3 - - byte_offset: 272 - description: OTG_HS device IN endpoint transmit FIFO size register - fieldset: OTG_HS_DIEPTXF4 - name: OTG_HS_DIEPTXF4 - - byte_offset: 276 - description: OTG_HS device IN endpoint transmit FIFO size register - fieldset: OTG_HS_DIEPTXF5 - name: OTG_HS_DIEPTXF5 - - byte_offset: 280 - description: OTG_HS device IN endpoint transmit FIFO size register - fieldset: OTG_HS_DIEPTXF6 - name: OTG_HS_DIEPTXF6 - - byte_offset: 284 - description: OTG_HS device IN endpoint transmit FIFO size register - fieldset: OTG_HS_DIEPTXF7 - name: OTG_HS_DIEPTXF7 + - name: OTG_HS_GOTGCTL + description: OTG_HS control and status register + byte_offset: 0 + fieldset: OTG_HS_GOTGCTL + - name: OTG_HS_GOTGINT + description: OTG_HS interrupt register + byte_offset: 4 + fieldset: OTG_HS_GOTGINT + - name: OTG_HS_GAHBCFG + description: OTG_HS AHB configuration register + byte_offset: 8 + fieldset: OTG_HS_GAHBCFG + - name: OTG_HS_GUSBCFG + description: OTG_HS USB configuration register + byte_offset: 12 + fieldset: OTG_HS_GUSBCFG + - name: OTG_HS_GRSTCTL + description: OTG_HS reset register + byte_offset: 16 + fieldset: OTG_HS_GRSTCTL + - name: OTG_HS_GINTSTS + description: OTG_HS core interrupt register + byte_offset: 20 + fieldset: OTG_HS_GINTSTS + - name: OTG_HS_GINTMSK + description: OTG_HS interrupt mask register + byte_offset: 24 + fieldset: OTG_HS_GINTMSK + - name: OTG_HS_GRXSTSR_Device + description: OTG_HS Receive status debug read register (peripheral mode mode) + byte_offset: 28 + access: Read + fieldset: OTG_HS_GRXSTSR_Device + - name: OTG_HS_GRXSTSR_Host + description: OTG_HS Receive status debug read register (host mode) + byte_offset: 28 + access: Read + fieldset: OTG_HS_GRXSTSR_Host + - name: OTG_HS_GRXSTSP_Device + description: OTG_HS status read and pop register (peripheral mode) + byte_offset: 32 + access: Read + fieldset: OTG_HS_GRXSTSP_Device + - name: OTG_HS_GRXSTSP_Host + description: OTG_HS status read and pop register (host mode) + byte_offset: 32 + access: Read + fieldset: OTG_HS_GRXSTSP_Host + - name: OTG_HS_GRXFSIZ + description: OTG_HS Receive FIFO size register + byte_offset: 36 + fieldset: OTG_HS_GRXFSIZ + - name: OTG_HS_DIEPTXF0_Device + description: Endpoint 0 transmit FIFO size (peripheral mode) + byte_offset: 40 + fieldset: OTG_HS_DIEPTXF0_Device + - name: OTG_HS_HNPTXFSIZ_Host + description: OTG_HS nonperiodic transmit FIFO size register (host mode) + byte_offset: 40 + fieldset: OTG_HS_HNPTXFSIZ_Host + - name: OTG_HS_HNPTXSTS + description: OTG_HS nonperiodic transmit FIFO/queue status register + byte_offset: 44 + access: Read + fieldset: OTG_HS_HNPTXSTS + - name: OTG_HS_GNPTXSTS + description: OTG_HS nonperiodic transmit FIFO/queue status register + byte_offset: 44 + access: Read + fieldset: OTG_HS_GNPTXSTS + - name: OTG_HS_GI2CCTL + description: OTG I2C access register + byte_offset: 48 + fieldset: OTG_HS_GI2CCTL + - name: OTG_HS_GCCFG + description: OTG_HS general core configuration register + byte_offset: 56 + fieldset: OTG_HS_GCCFG + - name: OTG_HS_CID + description: OTG_HS core ID register + byte_offset: 60 + fieldset: OTG_HS_CID + - name: OTG_HS_GLPMCFG + description: OTG core LPM configuration register + byte_offset: 84 + fieldset: OTG_HS_GLPMCFG + - name: OTG_HS_HPTXFSIZ + description: OTG_HS Host periodic transmit FIFO size register + byte_offset: 256 + fieldset: OTG_HS_HPTXFSIZ + - name: OTG_HS_DIEPTXF1 + description: OTG_HS device IN endpoint transmit FIFO size register + byte_offset: 260 + fieldset: OTG_HS_DIEPTXF1 + - name: OTG_HS_DIEPTXF2 + description: OTG_HS device IN endpoint transmit FIFO size register + byte_offset: 264 + fieldset: OTG_HS_DIEPTXF2 + - name: OTG_HS_DIEPTXF3 + description: OTG_HS device IN endpoint transmit FIFO size register + byte_offset: 268 + fieldset: OTG_HS_DIEPTXF3 + - name: OTG_HS_DIEPTXF4 + description: OTG_HS device IN endpoint transmit FIFO size register + byte_offset: 272 + fieldset: OTG_HS_DIEPTXF4 + - name: OTG_HS_DIEPTXF5 + description: OTG_HS device IN endpoint transmit FIFO size register + byte_offset: 276 + fieldset: OTG_HS_DIEPTXF5 + - name: OTG_HS_DIEPTXF6 + description: OTG_HS device IN endpoint transmit FIFO size register + byte_offset: 280 + fieldset: OTG_HS_DIEPTXF6 + - name: OTG_HS_DIEPTXF7 + description: OTG_HS device IN endpoint transmit FIFO size register + byte_offset: 284 + fieldset: OTG_HS_DIEPTXF7 fieldset/OTG_HS_CID: description: OTG_HS core ID register fields: - - bit_offset: 0 - bit_size: 32 - description: Product ID field - name: PRODUCT_ID + - name: PRODUCT_ID + description: Product ID field + bit_offset: 0 + bit_size: 32 fieldset/OTG_HS_DIEPTXF0_Device: description: Endpoint 0 transmit FIFO size (peripheral mode) fields: - - bit_offset: 0 - bit_size: 16 - description: Endpoint 0 transmit RAM start address - name: TX0FSA - - bit_offset: 16 - bit_size: 16 - description: Endpoint 0 TxFIFO depth - name: TX0FD + - name: TX0FSA + description: Endpoint 0 transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: TX0FD + description: Endpoint 0 TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_HS_DIEPTXF1: description: OTG_HS device IN endpoint transmit FIFO size register fields: - - bit_offset: 0 - bit_size: 16 - description: IN endpoint FIFOx transmit RAM start address - name: INEPTXSA - - bit_offset: 16 - bit_size: 16 - description: IN endpoint TxFIFO depth - name: INEPTXFD + - name: INEPTXSA + description: IN endpoint FIFOx transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: INEPTXFD + description: IN endpoint TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_HS_DIEPTXF2: description: OTG_HS device IN endpoint transmit FIFO size register fields: - - bit_offset: 0 - bit_size: 16 - description: IN endpoint FIFOx transmit RAM start address - name: INEPTXSA - - bit_offset: 16 - bit_size: 16 - description: IN endpoint TxFIFO depth - name: INEPTXFD + - name: INEPTXSA + description: IN endpoint FIFOx transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: INEPTXFD + description: IN endpoint TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_HS_DIEPTXF3: description: OTG_HS device IN endpoint transmit FIFO size register fields: - - bit_offset: 0 - bit_size: 16 - description: IN endpoint FIFOx transmit RAM start address - name: INEPTXSA - - bit_offset: 16 - bit_size: 16 - description: IN endpoint TxFIFO depth - name: INEPTXFD + - name: INEPTXSA + description: IN endpoint FIFOx transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: INEPTXFD + description: IN endpoint TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_HS_DIEPTXF4: description: OTG_HS device IN endpoint transmit FIFO size register fields: - - bit_offset: 0 - bit_size: 16 - description: IN endpoint FIFOx transmit RAM start address - name: INEPTXSA - - bit_offset: 16 - bit_size: 16 - description: IN endpoint TxFIFO depth - name: INEPTXFD + - name: INEPTXSA + description: IN endpoint FIFOx transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: INEPTXFD + description: IN endpoint TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_HS_DIEPTXF5: description: OTG_HS device IN endpoint transmit FIFO size register fields: - - bit_offset: 0 - bit_size: 16 - description: IN endpoint FIFOx transmit RAM start address - name: INEPTXSA - - bit_offset: 16 - bit_size: 16 - description: IN endpoint TxFIFO depth - name: INEPTXFD + - name: INEPTXSA + description: IN endpoint FIFOx transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: INEPTXFD + description: IN endpoint TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_HS_DIEPTXF6: description: OTG_HS device IN endpoint transmit FIFO size register fields: - - bit_offset: 0 - bit_size: 16 - description: IN endpoint FIFOx transmit RAM start address - name: INEPTXSA - - bit_offset: 16 - bit_size: 16 - description: IN endpoint TxFIFO depth - name: INEPTXFD + - name: INEPTXSA + description: IN endpoint FIFOx transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: INEPTXFD + description: IN endpoint TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_HS_DIEPTXF7: description: OTG_HS device IN endpoint transmit FIFO size register fields: - - bit_offset: 0 - bit_size: 16 - description: IN endpoint FIFOx transmit RAM start address - name: INEPTXSA - - bit_offset: 16 - bit_size: 16 - description: IN endpoint TxFIFO depth - name: INEPTXFD + - name: INEPTXSA + description: IN endpoint FIFOx transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: INEPTXFD + description: IN endpoint TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_HS_GAHBCFG: description: OTG_HS AHB configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: Global interrupt mask - name: GINT - - bit_offset: 1 - bit_size: 4 - description: Burst length/type - name: HBSTLEN - - bit_offset: 5 - bit_size: 1 - description: DMA enable - name: DMAEN - - bit_offset: 7 - bit_size: 1 - description: TxFIFO empty level - name: TXFELVL - - bit_offset: 8 - bit_size: 1 - description: Periodic TxFIFO empty level - name: PTXFELVL + - name: GINT + description: Global interrupt mask + bit_offset: 0 + bit_size: 1 + - name: HBSTLEN + description: Burst length/type + bit_offset: 1 + bit_size: 4 + - name: DMAEN + description: DMA enable + bit_offset: 5 + bit_size: 1 + - name: TXFELVL + description: TxFIFO empty level + bit_offset: 7 + bit_size: 1 + - name: PTXFELVL + description: Periodic TxFIFO empty level + bit_offset: 8 + bit_size: 1 fieldset/OTG_HS_GCCFG: description: OTG_HS general core configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: Data contact detection (DCD) status - name: DCDET - - bit_offset: 1 - bit_size: 1 - description: Primary detection (PD) status - name: PDET - - bit_offset: 2 - bit_size: 1 - description: Secondary detection (SD) status - name: SDET - - bit_offset: 3 - bit_size: 1 - description: DM pull-up detection status - name: PS2DET - - bit_offset: 16 - bit_size: 1 - description: Power down - name: PWRDWN - - bit_offset: 17 - bit_size: 1 - description: Battery charging detector (BCD) enable - name: BCDEN - - bit_offset: 18 - bit_size: 1 - description: Data contact detection (DCD) mode enable - name: DCDEN - - bit_offset: 19 - bit_size: 1 - description: Primary detection (PD) mode enable - name: PDEN - - bit_offset: 20 - bit_size: 1 - description: Secondary detection (SD) mode enable - name: SDEN - - bit_offset: 21 - bit_size: 1 - description: USB VBUS detection enable - name: VBDEN + - name: DCDET + description: Data contact detection (DCD) status + bit_offset: 0 + bit_size: 1 + - name: PDET + description: Primary detection (PD) status + bit_offset: 1 + bit_size: 1 + - name: SDET + description: Secondary detection (SD) status + bit_offset: 2 + bit_size: 1 + - name: PS2DET + description: DM pull-up detection status + bit_offset: 3 + bit_size: 1 + - name: PWRDWN + description: Power down + bit_offset: 16 + bit_size: 1 + - name: BCDEN + description: Battery charging detector (BCD) enable + bit_offset: 17 + bit_size: 1 + - name: DCDEN + description: Data contact detection (DCD) mode enable + bit_offset: 18 + bit_size: 1 + - name: PDEN + description: Primary detection (PD) mode enable + bit_offset: 19 + bit_size: 1 + - name: SDEN + description: Secondary detection (SD) mode enable + bit_offset: 20 + bit_size: 1 + - name: VBDEN + description: USB VBUS detection enable + bit_offset: 21 + bit_size: 1 fieldset/OTG_HS_GI2CCTL: description: OTG I2C access register fields: - - bit_offset: 0 - bit_size: 8 - description: I2C Read/Write Data - name: RWDATA - - bit_offset: 8 - bit_size: 8 - description: I2C Register Address - name: REGADDR - - bit_offset: 16 - bit_size: 7 - description: I2C Address - name: ADDR - - bit_offset: 23 - bit_size: 1 - description: I2C Enable - name: I2CEN - - bit_offset: 24 - bit_size: 1 - description: I2C ACK - name: ACK - - bit_offset: 26 - bit_size: 2 - description: I2C Device Address - name: I2CDEVADR - - bit_offset: 28 - bit_size: 1 - description: I2C DatSe0 USB mode - name: I2CDATSE0 - - bit_offset: 30 - bit_size: 1 - description: Read/Write Indicator - name: RW - - bit_offset: 31 - bit_size: 1 - description: I2C Busy/Done - name: BSYDNE + - name: RWDATA + description: I2C Read/Write Data + bit_offset: 0 + bit_size: 8 + - name: REGADDR + description: I2C Register Address + bit_offset: 8 + bit_size: 8 + - name: ADDR + description: I2C Address + bit_offset: 16 + bit_size: 7 + - name: I2CEN + description: I2C Enable + bit_offset: 23 + bit_size: 1 + - name: ACK + description: I2C ACK + bit_offset: 24 + bit_size: 1 + - name: I2CDEVADR + description: I2C Device Address + bit_offset: 26 + bit_size: 2 + - name: I2CDATSE0 + description: I2C DatSe0 USB mode + bit_offset: 28 + bit_size: 1 + - name: RW + description: Read/Write Indicator + bit_offset: 30 + bit_size: 1 + - name: BSYDNE + description: I2C Busy/Done + bit_offset: 31 + bit_size: 1 fieldset/OTG_HS_GINTMSK: description: OTG_HS interrupt mask register fields: - - bit_offset: 1 - bit_size: 1 - description: Mode mismatch interrupt mask - name: MMISM - - bit_offset: 2 - bit_size: 1 - description: OTG interrupt mask - name: OTGINT - - bit_offset: 3 - bit_size: 1 - description: Start of frame mask - name: SOFM - - bit_offset: 4 - bit_size: 1 - description: Receive FIFO nonempty mask - name: RXFLVLM - - bit_offset: 5 - bit_size: 1 - description: Nonperiodic TxFIFO empty mask - name: NPTXFEM - - bit_offset: 6 - bit_size: 1 - description: Global nonperiodic IN NAK effective mask - name: GINAKEFFM - - bit_offset: 7 - bit_size: 1 - description: Global OUT NAK effective mask - name: GONAKEFFM - - bit_offset: 10 - bit_size: 1 - description: Early suspend mask - name: ESUSPM - - bit_offset: 11 - bit_size: 1 - description: USB suspend mask - name: USBSUSPM - - bit_offset: 12 - bit_size: 1 - description: USB reset mask - name: USBRST - - bit_offset: 13 - bit_size: 1 - description: Enumeration done mask - name: ENUMDNEM - - bit_offset: 14 - bit_size: 1 - description: Isochronous OUT packet dropped interrupt mask - name: ISOODRPM - - bit_offset: 15 - bit_size: 1 - description: End of periodic frame interrupt mask - name: EOPFM - - bit_offset: 18 - bit_size: 1 - description: IN endpoints interrupt mask - name: IEPINT - - bit_offset: 19 - bit_size: 1 - description: OUT endpoints interrupt mask - name: OEPINT - - bit_offset: 20 - bit_size: 1 - description: Incomplete isochronous IN transfer mask - name: IISOIXFRM - - bit_offset: 21 - bit_size: 1 - description: Incomplete periodic transfer mask - name: PXFRM_IISOOXFRM - - bit_offset: 22 - bit_size: 1 - description: Data fetch suspended mask - name: FSUSPM - - bit_offset: 23 - bit_size: 1 - description: Reset detected interrupt mask - name: RSTDE - - bit_offset: 24 - bit_size: 1 - description: Host port interrupt mask - name: PRTIM - - bit_offset: 25 - bit_size: 1 - description: Host channels interrupt mask - name: HCIM - - bit_offset: 26 - bit_size: 1 - description: Periodic TxFIFO empty mask - name: PTXFEM - - bit_offset: 27 - bit_size: 1 - description: LPM interrupt mask - name: LPMINTM - - bit_offset: 28 - bit_size: 1 - description: Connector ID status change mask - name: CIDSCHGM - - bit_offset: 29 - bit_size: 1 - description: Disconnect detected interrupt mask - name: DISCINT - - bit_offset: 30 - bit_size: 1 - description: Session request/new session detected interrupt mask - name: SRQIM - - bit_offset: 31 - bit_size: 1 - description: Resume/remote wakeup detected interrupt mask - name: WUIM + - name: MMISM + description: Mode mismatch interrupt mask + bit_offset: 1 + bit_size: 1 + - name: OTGINT + description: OTG interrupt mask + bit_offset: 2 + bit_size: 1 + - name: SOFM + description: Start of frame mask + bit_offset: 3 + bit_size: 1 + - name: RXFLVLM + description: Receive FIFO nonempty mask + bit_offset: 4 + bit_size: 1 + - name: NPTXFEM + description: Nonperiodic TxFIFO empty mask + bit_offset: 5 + bit_size: 1 + - name: GINAKEFFM + description: Global nonperiodic IN NAK effective mask + bit_offset: 6 + bit_size: 1 + - name: GONAKEFFM + description: Global OUT NAK effective mask + bit_offset: 7 + bit_size: 1 + - name: ESUSPM + description: Early suspend mask + bit_offset: 10 + bit_size: 1 + - name: USBSUSPM + description: USB suspend mask + bit_offset: 11 + bit_size: 1 + - name: USBRST + description: USB reset mask + bit_offset: 12 + bit_size: 1 + - name: ENUMDNEM + description: Enumeration done mask + bit_offset: 13 + bit_size: 1 + - name: ISOODRPM + description: Isochronous OUT packet dropped interrupt mask + bit_offset: 14 + bit_size: 1 + - name: EOPFM + description: End of periodic frame interrupt mask + bit_offset: 15 + bit_size: 1 + - name: IEPINT + description: IN endpoints interrupt mask + bit_offset: 18 + bit_size: 1 + - name: OEPINT + description: OUT endpoints interrupt mask + bit_offset: 19 + bit_size: 1 + - name: IISOIXFRM + description: Incomplete isochronous IN transfer mask + bit_offset: 20 + bit_size: 1 + - name: PXFRM_IISOOXFRM + description: Incomplete periodic transfer mask + bit_offset: 21 + bit_size: 1 + - name: FSUSPM + description: Data fetch suspended mask + bit_offset: 22 + bit_size: 1 + - name: RSTDE + description: Reset detected interrupt mask + bit_offset: 23 + bit_size: 1 + - name: PRTIM + description: Host port interrupt mask + bit_offset: 24 + bit_size: 1 + - name: HCIM + description: Host channels interrupt mask + bit_offset: 25 + bit_size: 1 + - name: PTXFEM + description: Periodic TxFIFO empty mask + bit_offset: 26 + bit_size: 1 + - name: LPMINTM + description: LPM interrupt mask + bit_offset: 27 + bit_size: 1 + - name: CIDSCHGM + description: Connector ID status change mask + bit_offset: 28 + bit_size: 1 + - name: DISCINT + description: Disconnect detected interrupt mask + bit_offset: 29 + bit_size: 1 + - name: SRQIM + description: Session request/new session detected interrupt mask + bit_offset: 30 + bit_size: 1 + - name: WUIM + description: Resume/remote wakeup detected interrupt mask + bit_offset: 31 + bit_size: 1 fieldset/OTG_HS_GINTSTS: description: OTG_HS core interrupt register fields: - - bit_offset: 0 - bit_size: 1 - description: Current mode of operation - name: CMOD - - bit_offset: 1 - bit_size: 1 - description: Mode mismatch interrupt - name: MMIS - - bit_offset: 2 - bit_size: 1 - description: OTG interrupt - name: OTGINT - - bit_offset: 3 - bit_size: 1 - description: Start of frame - name: SOF - - bit_offset: 4 - bit_size: 1 - description: RxFIFO nonempty - name: RXFLVL - - bit_offset: 5 - bit_size: 1 - description: Nonperiodic TxFIFO empty - name: NPTXFE - - bit_offset: 6 - bit_size: 1 - description: Global IN nonperiodic NAK effective - name: GINAKEFF - - bit_offset: 7 - bit_size: 1 - description: Global OUT NAK effective - name: BOUTNAKEFF - - bit_offset: 10 - bit_size: 1 - description: Early suspend - name: ESUSP - - bit_offset: 11 - bit_size: 1 - description: USB suspend - name: USBSUSP - - bit_offset: 12 - bit_size: 1 - description: USB reset - name: USBRST - - bit_offset: 13 - bit_size: 1 - description: Enumeration done - name: ENUMDNE - - bit_offset: 14 - bit_size: 1 - description: Isochronous OUT packet dropped interrupt - name: ISOODRP - - bit_offset: 15 - bit_size: 1 - description: End of periodic frame interrupt - name: EOPF - - bit_offset: 18 - bit_size: 1 - description: IN endpoint interrupt - name: IEPINT - - bit_offset: 19 - bit_size: 1 - description: OUT endpoint interrupt - name: OEPINT - - bit_offset: 20 - bit_size: 1 - description: Incomplete isochronous IN transfer - name: IISOIXFR - - bit_offset: 21 - bit_size: 1 - description: Incomplete periodic transfer - name: PXFR_INCOMPISOOUT - - bit_offset: 22 - bit_size: 1 - description: Data fetch suspended - name: DATAFSUSP - - bit_offset: 24 - bit_size: 1 - description: Host port interrupt - name: HPRTINT - - bit_offset: 25 - bit_size: 1 - description: Host channels interrupt - name: HCINT - - bit_offset: 26 - bit_size: 1 - description: Periodic TxFIFO empty - name: PTXFE - - bit_offset: 28 - bit_size: 1 - description: Connector ID status change - name: CIDSCHG - - bit_offset: 29 - bit_size: 1 - description: Disconnect detected interrupt - name: DISCINT - - bit_offset: 30 - bit_size: 1 - description: Session request/new session detected interrupt - name: SRQINT - - bit_offset: 31 - bit_size: 1 - description: Resume/remote wakeup detected interrupt - name: WKUINT + - name: CMOD + description: Current mode of operation + bit_offset: 0 + bit_size: 1 + - name: MMIS + description: Mode mismatch interrupt + bit_offset: 1 + bit_size: 1 + - name: OTGINT + description: OTG interrupt + bit_offset: 2 + bit_size: 1 + - name: SOF + description: Start of frame + bit_offset: 3 + bit_size: 1 + - name: RXFLVL + description: RxFIFO nonempty + bit_offset: 4 + bit_size: 1 + - name: NPTXFE + description: Nonperiodic TxFIFO empty + bit_offset: 5 + bit_size: 1 + - name: GINAKEFF + description: Global IN nonperiodic NAK effective + bit_offset: 6 + bit_size: 1 + - name: BOUTNAKEFF + description: Global OUT NAK effective + bit_offset: 7 + bit_size: 1 + - name: ESUSP + description: Early suspend + bit_offset: 10 + bit_size: 1 + - name: USBSUSP + description: USB suspend + bit_offset: 11 + bit_size: 1 + - name: USBRST + description: USB reset + bit_offset: 12 + bit_size: 1 + - name: ENUMDNE + description: Enumeration done + bit_offset: 13 + bit_size: 1 + - name: ISOODRP + description: Isochronous OUT packet dropped interrupt + bit_offset: 14 + bit_size: 1 + - name: EOPF + description: End of periodic frame interrupt + bit_offset: 15 + bit_size: 1 + - name: IEPINT + description: IN endpoint interrupt + bit_offset: 18 + bit_size: 1 + - name: OEPINT + description: OUT endpoint interrupt + bit_offset: 19 + bit_size: 1 + - name: IISOIXFR + description: Incomplete isochronous IN transfer + bit_offset: 20 + bit_size: 1 + - name: PXFR_INCOMPISOOUT + description: Incomplete periodic transfer + bit_offset: 21 + bit_size: 1 + - name: DATAFSUSP + description: Data fetch suspended + bit_offset: 22 + bit_size: 1 + - name: HPRTINT + description: Host port interrupt + bit_offset: 24 + bit_size: 1 + - name: HCINT + description: Host channels interrupt + bit_offset: 25 + bit_size: 1 + - name: PTXFE + description: Periodic TxFIFO empty + bit_offset: 26 + bit_size: 1 + - name: CIDSCHG + description: Connector ID status change + bit_offset: 28 + bit_size: 1 + - name: DISCINT + description: Disconnect detected interrupt + bit_offset: 29 + bit_size: 1 + - name: SRQINT + description: Session request/new session detected interrupt + bit_offset: 30 + bit_size: 1 + - name: WKUINT + description: Resume/remote wakeup detected interrupt + bit_offset: 31 + bit_size: 1 fieldset/OTG_HS_GLPMCFG: description: OTG core LPM configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: LPM support enable - name: LPMEN - - bit_offset: 1 - bit_size: 1 - description: LPM token acknowledge enable - name: LPMACK - - bit_offset: 2 - bit_size: 4 - description: Best effort service latency - name: BESL - - bit_offset: 6 - bit_size: 1 - description: bRemoteWake value - name: REMWAKE - - bit_offset: 7 - bit_size: 1 - description: L1 Shallow Sleep enable - name: L1SSEN - - bit_offset: 8 - bit_size: 4 - description: BESL threshold - name: BESLTHRS - - bit_offset: 12 - bit_size: 1 - description: L1 deep sleep enable - name: L1DSEN - - bit_offset: 13 - bit_size: 2 - description: LPM response - name: LPMRST - - bit_offset: 15 - bit_size: 1 - description: Port sleep status - name: SLPSTS - - bit_offset: 16 - bit_size: 1 - description: Sleep State Resume OK - name: L1RSMOK - - bit_offset: 17 - bit_size: 4 - description: LPM Channel Index - name: LPMCHIDX - - bit_offset: 21 - bit_size: 3 - description: LPM retry count - name: LPMRCNT - - bit_offset: 24 - bit_size: 1 - description: Send LPM transaction - name: SNDLPM - - bit_offset: 25 - bit_size: 3 - description: LPM retry count status - name: LPMRCNTSTS - - bit_offset: 28 - bit_size: 1 - description: Enable best effort service latency - name: ENBESL + - name: LPMEN + description: LPM support enable + bit_offset: 0 + bit_size: 1 + - name: LPMACK + description: LPM token acknowledge enable + bit_offset: 1 + bit_size: 1 + - name: BESL + description: Best effort service latency + bit_offset: 2 + bit_size: 4 + - name: REMWAKE + description: bRemoteWake value + bit_offset: 6 + bit_size: 1 + - name: L1SSEN + description: L1 Shallow Sleep enable + bit_offset: 7 + bit_size: 1 + - name: BESLTHRS + description: BESL threshold + bit_offset: 8 + bit_size: 4 + - name: L1DSEN + description: L1 deep sleep enable + bit_offset: 12 + bit_size: 1 + - name: LPMRST + description: LPM response + bit_offset: 13 + bit_size: 2 + - name: SLPSTS + description: Port sleep status + bit_offset: 15 + bit_size: 1 + - name: L1RSMOK + description: Sleep State Resume OK + bit_offset: 16 + bit_size: 1 + - name: LPMCHIDX + description: LPM Channel Index + bit_offset: 17 + bit_size: 4 + - name: LPMRCNT + description: LPM retry count + bit_offset: 21 + bit_size: 3 + - name: SNDLPM + description: Send LPM transaction + bit_offset: 24 + bit_size: 1 + - name: LPMRCNTSTS + description: LPM retry count status + bit_offset: 25 + bit_size: 3 + - name: ENBESL + description: Enable best effort service latency + bit_offset: 28 + bit_size: 1 fieldset/OTG_HS_GNPTXSTS: description: OTG_HS nonperiodic transmit FIFO/queue status register fields: - - bit_offset: 0 - bit_size: 16 - description: Nonperiodic TxFIFO space available - name: NPTXFSAV - - bit_offset: 16 - bit_size: 8 - description: Nonperiodic transmit request queue space available - name: NPTQXSAV - - bit_offset: 24 - bit_size: 7 - description: Top of the nonperiodic transmit request queue - name: NPTXQTOP + - name: NPTXFSAV + description: Nonperiodic TxFIFO space available + bit_offset: 0 + bit_size: 16 + - name: NPTQXSAV + description: Nonperiodic transmit request queue space available + bit_offset: 16 + bit_size: 8 + - name: NPTXQTOP + description: Top of the nonperiodic transmit request queue + bit_offset: 24 + bit_size: 7 fieldset/OTG_HS_GOTGCTL: description: OTG_HS control and status register fields: - - bit_offset: 0 - bit_size: 1 - description: Session request success - name: SRQSCS - - bit_offset: 1 - bit_size: 1 - description: Session request - name: SRQ - - bit_offset: 8 - bit_size: 1 - description: Host negotiation success - name: HNGSCS - - bit_offset: 9 - bit_size: 1 - description: HNP request - name: HNPRQ - - bit_offset: 10 - bit_size: 1 - description: Host set HNP enable - name: HSHNPEN - - bit_offset: 11 - bit_size: 1 - description: Device HNP enabled - name: DHNPEN - - bit_offset: 12 - bit_size: 1 - description: Embedded host enable - name: EHEN - - bit_offset: 16 - bit_size: 1 - description: Connector ID status - name: CIDSTS - - bit_offset: 17 - bit_size: 1 - description: Long/short debounce time - name: DBCT - - bit_offset: 18 - bit_size: 1 - description: A-session valid - name: ASVLD - - bit_offset: 19 - bit_size: 1 - description: B-session valid - name: BSVLD + - name: SRQSCS + description: Session request success + bit_offset: 0 + bit_size: 1 + - name: SRQ + description: Session request + bit_offset: 1 + bit_size: 1 + - name: HNGSCS + description: Host negotiation success + bit_offset: 8 + bit_size: 1 + - name: HNPRQ + description: HNP request + bit_offset: 9 + bit_size: 1 + - name: HSHNPEN + description: Host set HNP enable + bit_offset: 10 + bit_size: 1 + - name: DHNPEN + description: Device HNP enabled + bit_offset: 11 + bit_size: 1 + - name: EHEN + description: Embedded host enable + bit_offset: 12 + bit_size: 1 + - name: CIDSTS + description: Connector ID status + bit_offset: 16 + bit_size: 1 + - name: DBCT + description: Long/short debounce time + bit_offset: 17 + bit_size: 1 + - name: ASVLD + description: A-session valid + bit_offset: 18 + bit_size: 1 + - name: BSVLD + description: B-session valid + bit_offset: 19 + bit_size: 1 fieldset/OTG_HS_GOTGINT: description: OTG_HS interrupt register fields: - - bit_offset: 2 - bit_size: 1 - description: Session end detected - name: SEDET - - bit_offset: 8 - bit_size: 1 - description: Session request success status change - name: SRSSCHG - - bit_offset: 9 - bit_size: 1 - description: Host negotiation success status change - name: HNSSCHG - - bit_offset: 17 - bit_size: 1 - description: Host negotiation detected - name: HNGDET - - bit_offset: 18 - bit_size: 1 - description: A-device timeout change - name: ADTOCHG - - bit_offset: 19 - bit_size: 1 - description: Debounce done - name: DBCDNE - - bit_offset: 20 - bit_size: 1 - description: ID input pin changed - name: IDCHNG + - name: SEDET + description: Session end detected + bit_offset: 2 + bit_size: 1 + - name: SRSSCHG + description: Session request success status change + bit_offset: 8 + bit_size: 1 + - name: HNSSCHG + description: Host negotiation success status change + bit_offset: 9 + bit_size: 1 + - name: HNGDET + description: Host negotiation detected + bit_offset: 17 + bit_size: 1 + - name: ADTOCHG + description: A-device timeout change + bit_offset: 18 + bit_size: 1 + - name: DBCDNE + description: Debounce done + bit_offset: 19 + bit_size: 1 + - name: IDCHNG + description: ID input pin changed + bit_offset: 20 + bit_size: 1 fieldset/OTG_HS_GRSTCTL: description: OTG_HS reset register fields: - - bit_offset: 0 - bit_size: 1 - description: Core soft reset - name: CSRST - - bit_offset: 1 - bit_size: 1 - description: HCLK soft reset - name: HSRST - - bit_offset: 2 - bit_size: 1 - description: Host frame counter reset - name: FCRST - - bit_offset: 4 - bit_size: 1 - description: RxFIFO flush - name: RXFFLSH - - bit_offset: 5 - bit_size: 1 - description: TxFIFO flush - name: TXFFLSH - - bit_offset: 6 - bit_size: 5 - description: TxFIFO number - name: TXFNUM - - bit_offset: 30 - bit_size: 1 - description: DMA request signal enabled for USB OTG HS - name: DMAREQ - - bit_offset: 31 - bit_size: 1 - description: AHB master idle - name: AHBIDL + - name: CSRST + description: Core soft reset + bit_offset: 0 + bit_size: 1 + - name: HSRST + description: HCLK soft reset + bit_offset: 1 + bit_size: 1 + - name: FCRST + description: Host frame counter reset + bit_offset: 2 + bit_size: 1 + - name: RXFFLSH + description: RxFIFO flush + bit_offset: 4 + bit_size: 1 + - name: TXFFLSH + description: TxFIFO flush + bit_offset: 5 + bit_size: 1 + - name: TXFNUM + description: TxFIFO number + bit_offset: 6 + bit_size: 5 + - name: DMAREQ + description: DMA request signal enabled for USB OTG HS + bit_offset: 30 + bit_size: 1 + - name: AHBIDL + description: AHB master idle + bit_offset: 31 + bit_size: 1 fieldset/OTG_HS_GRXFSIZ: description: OTG_HS Receive FIFO size register fields: - - bit_offset: 0 - bit_size: 16 - description: RxFIFO depth - name: RXFD + - name: RXFD + description: RxFIFO depth + bit_offset: 0 + bit_size: 16 fieldset/OTG_HS_GRXSTSP_Device: description: OTG_HS status read and pop register (peripheral mode) fields: - - bit_offset: 0 - bit_size: 4 - description: Endpoint number - name: EPNUM - - bit_offset: 4 - bit_size: 11 - description: Byte count - name: BCNT - - bit_offset: 15 - bit_size: 2 - description: Data PID - name: DPID - - bit_offset: 17 - bit_size: 4 - description: Packet status - name: PKTSTS - - bit_offset: 21 - bit_size: 4 - description: Frame number - name: FRMNUM + - name: EPNUM + description: Endpoint number + bit_offset: 0 + bit_size: 4 + - name: BCNT + description: Byte count + bit_offset: 4 + bit_size: 11 + - name: DPID + description: Data PID + bit_offset: 15 + bit_size: 2 + - name: PKTSTS + description: Packet status + bit_offset: 17 + bit_size: 4 + - name: FRMNUM + description: Frame number + bit_offset: 21 + bit_size: 4 fieldset/OTG_HS_GRXSTSP_Host: description: OTG_HS status read and pop register (host mode) fields: - - bit_offset: 0 - bit_size: 4 - description: Channel number - name: CHNUM - - bit_offset: 4 - bit_size: 11 - description: Byte count - name: BCNT - - bit_offset: 15 - bit_size: 2 - description: Data PID - name: DPID - - bit_offset: 17 - bit_size: 4 - description: Packet status - name: PKTSTS + - name: CHNUM + description: Channel number + bit_offset: 0 + bit_size: 4 + - name: BCNT + description: Byte count + bit_offset: 4 + bit_size: 11 + - name: DPID + description: Data PID + bit_offset: 15 + bit_size: 2 + - name: PKTSTS + description: Packet status + bit_offset: 17 + bit_size: 4 fieldset/OTG_HS_GRXSTSR_Device: description: OTG_HS Receive status debug read register (peripheral mode mode) fields: - - bit_offset: 0 - bit_size: 4 - description: Endpoint number - name: EPNUM - - bit_offset: 4 - bit_size: 11 - description: Byte count - name: BCNT - - bit_offset: 15 - bit_size: 2 - description: Data PID - name: DPID - - bit_offset: 17 - bit_size: 4 - description: Packet status - name: PKTSTS - - bit_offset: 21 - bit_size: 4 - description: Frame number - name: FRMNUM + - name: EPNUM + description: Endpoint number + bit_offset: 0 + bit_size: 4 + - name: BCNT + description: Byte count + bit_offset: 4 + bit_size: 11 + - name: DPID + description: Data PID + bit_offset: 15 + bit_size: 2 + - name: PKTSTS + description: Packet status + bit_offset: 17 + bit_size: 4 + - name: FRMNUM + description: Frame number + bit_offset: 21 + bit_size: 4 fieldset/OTG_HS_GRXSTSR_Host: description: OTG_HS Receive status debug read register (host mode) fields: - - bit_offset: 0 - bit_size: 4 - description: Channel number - name: CHNUM - - bit_offset: 4 - bit_size: 11 - description: Byte count - name: BCNT - - bit_offset: 15 - bit_size: 2 - description: Data PID - name: DPID - - bit_offset: 17 - bit_size: 4 - description: Packet status - name: PKTSTS + - name: CHNUM + description: Channel number + bit_offset: 0 + bit_size: 4 + - name: BCNT + description: Byte count + bit_offset: 4 + bit_size: 11 + - name: DPID + description: Data PID + bit_offset: 15 + bit_size: 2 + - name: PKTSTS + description: Packet status + bit_offset: 17 + bit_size: 4 fieldset/OTG_HS_GUSBCFG: description: OTG_HS USB configuration register fields: - - bit_offset: 0 - bit_size: 3 - description: FS timeout calibration - name: TOCAL - - bit_offset: 6 - bit_size: 1 - description: USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver - select - name: PHYSEL - - bit_offset: 8 - bit_size: 1 - description: SRP-capable - name: SRPCAP - - bit_offset: 9 - bit_size: 1 - description: HNP-capable - name: HNPCAP - - bit_offset: 10 - bit_size: 4 - description: USB turnaround time - name: TRDT - - bit_offset: 15 - bit_size: 1 - description: PHY Low-power clock select - name: PHYLPCS - - bit_offset: 17 - bit_size: 1 - description: ULPI FS/LS select - name: ULPIFSLS - - bit_offset: 18 - bit_size: 1 - description: ULPI Auto-resume - name: ULPIAR - - bit_offset: 19 - bit_size: 1 - description: ULPI Clock SuspendM - name: ULPICSM - - bit_offset: 20 - bit_size: 1 - description: ULPI External VBUS Drive - name: ULPIEVBUSD - - bit_offset: 21 - bit_size: 1 - description: ULPI external VBUS indicator - name: ULPIEVBUSI - - bit_offset: 22 - bit_size: 1 - description: TermSel DLine pulsing selection - name: TSDPS - - bit_offset: 23 - bit_size: 1 - description: Indicator complement - name: PCCI - - bit_offset: 24 - bit_size: 1 - description: Indicator pass through - name: PTCI - - bit_offset: 25 - bit_size: 1 - description: ULPI interface protect disable - name: ULPIIPD - - bit_offset: 29 - bit_size: 1 - description: Forced host mode - name: FHMOD - - bit_offset: 30 - bit_size: 1 - description: Forced peripheral mode - name: FDMOD + - name: TOCAL + description: FS timeout calibration + bit_offset: 0 + bit_size: 3 + - name: PHYSEL + description: USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select + bit_offset: 6 + bit_size: 1 + - name: SRPCAP + description: SRP-capable + bit_offset: 8 + bit_size: 1 + - name: HNPCAP + description: HNP-capable + bit_offset: 9 + bit_size: 1 + - name: TRDT + description: USB turnaround time + bit_offset: 10 + bit_size: 4 + - name: PHYLPCS + description: PHY Low-power clock select + bit_offset: 15 + bit_size: 1 + - name: ULPIFSLS + description: ULPI FS/LS select + bit_offset: 17 + bit_size: 1 + - name: ULPIAR + description: ULPI Auto-resume + bit_offset: 18 + bit_size: 1 + - name: ULPICSM + description: ULPI Clock SuspendM + bit_offset: 19 + bit_size: 1 + - name: ULPIEVBUSD + description: ULPI External VBUS Drive + bit_offset: 20 + bit_size: 1 + - name: ULPIEVBUSI + description: ULPI external VBUS indicator + bit_offset: 21 + bit_size: 1 + - name: TSDPS + description: TermSel DLine pulsing selection + bit_offset: 22 + bit_size: 1 + - name: PCCI + description: Indicator complement + bit_offset: 23 + bit_size: 1 + - name: PTCI + description: Indicator pass through + bit_offset: 24 + bit_size: 1 + - name: ULPIIPD + description: ULPI interface protect disable + bit_offset: 25 + bit_size: 1 + - name: FHMOD + description: Forced host mode + bit_offset: 29 + bit_size: 1 + - name: FDMOD + description: Forced peripheral mode + bit_offset: 30 + bit_size: 1 fieldset/OTG_HS_HNPTXFSIZ_Host: description: OTG_HS nonperiodic transmit FIFO size register (host mode) fields: - - bit_offset: 0 - bit_size: 16 - description: Nonperiodic transmit RAM start address - name: NPTXFSA - - bit_offset: 16 - bit_size: 16 - description: Nonperiodic TxFIFO depth - name: NPTXFD + - name: NPTXFSA + description: Nonperiodic transmit RAM start address + bit_offset: 0 + bit_size: 16 + - name: NPTXFD + description: Nonperiodic TxFIFO depth + bit_offset: 16 + bit_size: 16 fieldset/OTG_HS_HNPTXSTS: description: OTG_HS nonperiodic transmit FIFO/queue status register fields: - - bit_offset: 0 - bit_size: 16 - description: Nonperiodic TxFIFO space available - name: NPTXFSAV - - bit_offset: 16 - bit_size: 8 - description: Nonperiodic transmit request queue space available - name: NPTQXSAV - - bit_offset: 24 - bit_size: 7 - description: Top of the nonperiodic transmit request queue - name: NPTXQTOP + - name: NPTXFSAV + description: Nonperiodic TxFIFO space available + bit_offset: 0 + bit_size: 16 + - name: NPTQXSAV + description: Nonperiodic transmit request queue space available + bit_offset: 16 + bit_size: 8 + - name: NPTXQTOP + description: Top of the nonperiodic transmit request queue + bit_offset: 24 + bit_size: 7 fieldset/OTG_HS_HPTXFSIZ: description: OTG_HS Host periodic transmit FIFO size register fields: - - bit_offset: 0 - bit_size: 16 - description: Host periodic TxFIFO start address - name: PTXSA - - bit_offset: 16 - bit_size: 16 - description: Host periodic TxFIFO depth - name: PTXFD + - name: PTXSA + description: Host periodic TxFIFO start address + bit_offset: 0 + bit_size: 16 + - name: PTXFD + description: Host periodic TxFIFO depth + bit_offset: 16 + bit_size: 16 diff --git a/data/registers/pwr_f7.yaml b/data/registers/pwr_f7.yaml index fc96a97..e3efcbb 100644 --- a/data/registers/pwr_f7.yaml +++ b/data/registers/pwr_f7.yaml @@ -2,181 +2,181 @@ block/PWR: description: Power control items: - - byte_offset: 0 - description: power control register - fieldset: CR1 - name: CR1 - - byte_offset: 4 - description: power control/status register - fieldset: CSR1 - name: CSR1 - - byte_offset: 8 - description: power control register - fieldset: CR2 - name: CR2 - - byte_offset: 12 - description: power control/status register - fieldset: CSR2 - name: CSR2 -enum/PDDS: - bit_size: 1 - variants: - - description: Enter Stop mode when the CPU enters deepsleep - name: STOP_MODE - value: 0 - - description: Enter Standby mode when the CPU enters deepsleep - name: STANDBY_MODE - value: 1 -enum/VOS: - bit_size: 2 - variants: - - description: Scale 3 mode - name: SCALE3 - value: 1 - - description: Scale 2 mode - name: SCALE2 - value: 2 - - description: Scale 1 mode (reset value) - name: SCALE1 - value: 3 + - name: CR1 + description: power control register + byte_offset: 0 + fieldset: CR1 + - name: CSR1 + description: power control/status register + byte_offset: 4 + fieldset: CSR1 + - name: CR2 + description: power control register + byte_offset: 8 + fieldset: CR2 + - name: CSR2 + description: power control/status register + byte_offset: 12 + fieldset: CSR2 fieldset/CR1: description: power control register fields: - - bit_offset: 0 - bit_size: 1 - description: Low-power deep sleep - name: LPDS - - bit_offset: 1 - bit_size: 1 - description: Power down deepsleep - enum: PDDS - name: PDDS - - bit_offset: 3 - bit_size: 1 - description: Clear standby flag - name: CSBF - - bit_offset: 4 - bit_size: 1 - description: Power voltage detector enable - name: PVDE - - bit_offset: 5 - bit_size: 3 - description: PVD level selection - name: PLS - - bit_offset: 8 - bit_size: 1 - description: Disable backup domain write protection - name: DBP - - bit_offset: 9 - bit_size: 1 - description: Flash power down in Stop mode - name: FPDS - - bit_offset: 10 - bit_size: 1 - description: Low-power regulator in deepsleep under-drive mode - name: LPUDS - - bit_offset: 11 - bit_size: 1 - description: Main regulator in deepsleep under-drive mode - name: MRUDS - - array: - len: 1 - stride: 0 - bit_offset: 13 - bit_size: 1 - description: ADCDC1 - name: ADCDC - - bit_offset: 14 - bit_size: 2 - description: Regulator voltage scaling output selection - enum: VOS - name: VOS - - bit_offset: 16 - bit_size: 1 - description: Over-drive enable - name: ODEN - - bit_offset: 17 - bit_size: 1 - description: Over-drive switching enabled - name: ODSWEN - - bit_offset: 18 - bit_size: 2 - description: Under-drive enable in stop mode - name: UDEN + - name: LPDS + description: Low-power deep sleep + bit_offset: 0 + bit_size: 1 + - name: PDDS + description: Power down deepsleep + bit_offset: 1 + bit_size: 1 + enum: PDDS + - name: CSBF + description: Clear standby flag + bit_offset: 3 + bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: PVD level selection + bit_offset: 5 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: FPDS + description: Flash power down in Stop mode + bit_offset: 9 + bit_size: 1 + - name: LPUDS + description: Low-power regulator in deepsleep under-drive mode + bit_offset: 10 + bit_size: 1 + - name: MRUDS + description: Main regulator in deepsleep under-drive mode + bit_offset: 11 + bit_size: 1 + - name: ADCDC + description: ADCDC1 + bit_offset: 13 + bit_size: 1 + array: + len: 1 + stride: 0 + - name: VOS + description: Regulator voltage scaling output selection + bit_offset: 14 + bit_size: 2 + enum: VOS + - name: ODEN + description: Over-drive enable + bit_offset: 16 + bit_size: 1 + - name: ODSWEN + description: Over-drive switching enabled + bit_offset: 17 + bit_size: 1 + - name: UDEN + description: Under-drive enable in stop mode + bit_offset: 18 + bit_size: 2 fieldset/CR2: description: power control register fields: - - array: - len: 6 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: Clear Wakeup Pin flag for PA0 - name: CWUPF - - array: - len: 6 - stride: 1 - bit_offset: 8 - bit_size: 1 - description: Wakeup pin polarity bit for PA0 - name: WUPP + - name: CWUPF + description: Clear Wakeup Pin flag for PA0 + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: WUPP + description: Wakeup pin polarity bit for PA0 + bit_offset: 8 + bit_size: 1 + array: + len: 6 + stride: 1 fieldset/CSR1: description: power control/status register fields: - - bit_offset: 0 - bit_size: 1 - description: Wakeup internal flag - name: WUIF - - bit_offset: 1 - bit_size: 1 - description: Standby flag - name: SBF - - bit_offset: 2 - bit_size: 1 - description: PVD output - name: PVDO - - bit_offset: 3 - bit_size: 1 - description: Backup regulator ready - name: BRR - - bit_offset: 8 - bit_size: 1 - description: Enable internal wakeup - name: EIWUP - - bit_offset: 9 - bit_size: 1 - description: Backup regulator enable - name: BRE - - bit_offset: 14 - bit_size: 1 - description: Regulator voltage scaling output selection ready bit - name: VOSRDY - - bit_offset: 16 - bit_size: 1 - description: Over-drive mode ready - name: ODRDY - - bit_offset: 17 - bit_size: 1 - description: Over-drive mode switching ready - name: ODSWRDY - - bit_offset: 18 - bit_size: 2 - description: Under-drive ready flag - name: UDRDY + - name: WUIF + description: Wakeup internal flag + bit_offset: 0 + bit_size: 1 + - name: SBF + description: Standby flag + bit_offset: 1 + bit_size: 1 + - name: PVDO + description: PVD output + bit_offset: 2 + bit_size: 1 + - name: BRR + description: Backup regulator ready + bit_offset: 3 + bit_size: 1 + - name: EIWUP + description: Enable internal wakeup + bit_offset: 8 + bit_size: 1 + - name: BRE + description: Backup regulator enable + bit_offset: 9 + bit_size: 1 + - name: VOSRDY + description: Regulator voltage scaling output selection ready bit + bit_offset: 14 + bit_size: 1 + - name: ODRDY + description: Over-drive mode ready + bit_offset: 16 + bit_size: 1 + - name: ODSWRDY + description: Over-drive mode switching ready + bit_offset: 17 + bit_size: 1 + - name: UDRDY + description: Under-drive ready flag + bit_offset: 18 + bit_size: 2 fieldset/CSR2: description: power control/status register fields: - - array: - len: 6 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: Wakeup Pin flag for PA0 - name: WUPF - - array: - len: 6 - stride: 1 - bit_offset: 8 - bit_size: 1 - description: Enable Wakeup pin for PA0 - name: EWUP + - name: WUPF + description: Wakeup Pin flag for PA0 + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: EWUP + description: Enable Wakeup pin for PA0 + bit_offset: 8 + bit_size: 1 + array: + len: 6 + stride: 1 +enum/PDDS: + bit_size: 1 + variants: + - name: STOP_MODE + description: Enter Stop mode when the CPU enters deepsleep + value: 0 + - name: STANDBY_MODE + description: Enter Standby mode when the CPU enters deepsleep + value: 1 +enum/VOS: + bit_size: 2 + variants: + - name: SCALE3 + description: Scale 3 mode + value: 1 + - name: SCALE2 + description: Scale 2 mode + value: 2 + - name: SCALE1 + description: Scale 1 mode (reset value) + value: 3 diff --git a/data/registers/quadspi_v1.yaml b/data/registers/quadspi_v1.yaml index 46d8e60..23c9011 100644 --- a/data/registers/quadspi_v1.yaml +++ b/data/registers/quadspi_v1.yaml @@ -2,295 +2,295 @@ block/QUADSPI: description: QuadSPI interface items: - - byte_offset: 0 - description: control register - fieldset: CR - name: CR - - byte_offset: 4 - description: device configuration register - fieldset: DCR - name: DCR - - access: Read - byte_offset: 8 - description: status register - fieldset: SR - name: SR - - byte_offset: 12 - description: flag clear register - fieldset: FCR - name: FCR - - byte_offset: 16 - description: data length register - fieldset: DLR - name: DLR - - byte_offset: 20 - description: communication configuration register - fieldset: CCR - name: CCR - - byte_offset: 24 - description: address register - fieldset: AR - name: AR - - byte_offset: 28 - description: ABR - fieldset: ABR - name: ABR - - byte_offset: 32 - description: data register - fieldset: DR - name: DR - - byte_offset: 36 - description: polling status mask register - fieldset: PSMKR - name: PSMKR - - byte_offset: 40 - description: polling status match register - fieldset: PSMAR - name: PSMAR - - byte_offset: 44 - description: polling interval register - fieldset: PIR - name: PIR - - byte_offset: 48 - description: low-power timeout register - fieldset: LPTR - name: LPTR + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: DCR + description: device configuration register + byte_offset: 4 + fieldset: DCR + - name: SR + description: status register + byte_offset: 8 + access: Read + fieldset: SR + - name: FCR + description: flag clear register + byte_offset: 12 + fieldset: FCR + - name: DLR + description: data length register + byte_offset: 16 + fieldset: DLR + - name: CCR + description: communication configuration register + byte_offset: 20 + fieldset: CCR + - name: AR + description: address register + byte_offset: 24 + fieldset: AR + - name: ABR + description: ABR + byte_offset: 28 + fieldset: ABR + - name: DR + description: data register + byte_offset: 32 + fieldset: DR + - name: PSMKR + description: polling status mask register + byte_offset: 36 + fieldset: PSMKR + - name: PSMAR + description: polling status match register + byte_offset: 40 + fieldset: PSMAR + - name: PIR + description: polling interval register + byte_offset: 44 + fieldset: PIR + - name: LPTR + description: low-power timeout register + byte_offset: 48 + fieldset: LPTR fieldset/ABR: description: ABR fields: - - bit_offset: 0 - bit_size: 32 - description: ALTERNATE - name: ALTERNATE + - name: ALTERNATE + description: ALTERNATE + bit_offset: 0 + bit_size: 32 fieldset/AR: description: address register fields: - - bit_offset: 0 - bit_size: 32 - description: Address - name: ADDRESS + - name: ADDRESS + description: Address + bit_offset: 0 + bit_size: 32 fieldset/CCR: description: communication configuration register fields: - - bit_offset: 0 - bit_size: 8 - description: Instruction - name: INSTRUCTION - - bit_offset: 8 - bit_size: 2 - description: Instruction mode - name: IMODE - - bit_offset: 10 - bit_size: 2 - description: Address mode - name: ADMODE - - bit_offset: 12 - bit_size: 2 - description: Address size - name: ADSIZE - - bit_offset: 14 - bit_size: 2 - description: Alternate bytes mode - name: ABMODE - - bit_offset: 16 - bit_size: 2 - description: Alternate bytes size - name: ABSIZE - - bit_offset: 18 - bit_size: 5 - description: Number of dummy cycles - name: DCYC - - bit_offset: 24 - bit_size: 2 - description: Data mode - name: DMODE - - bit_offset: 26 - bit_size: 2 - description: Functional mode - name: FMODE - - bit_offset: 28 - bit_size: 1 - description: Send instruction only once mode - name: SIOO - - bit_offset: 30 - bit_size: 1 - description: DDR hold half cycle - name: DHHC - - bit_offset: 31 - bit_size: 1 - description: Double data rate mode - name: DDRM + - name: INSTRUCTION + description: Instruction + bit_offset: 0 + bit_size: 8 + - name: IMODE + description: Instruction mode + bit_offset: 8 + bit_size: 2 + - name: ADMODE + description: Address mode + bit_offset: 10 + bit_size: 2 + - name: ADSIZE + description: Address size + bit_offset: 12 + bit_size: 2 + - name: ABMODE + description: Alternate bytes mode + bit_offset: 14 + bit_size: 2 + - name: ABSIZE + description: Alternate bytes size + bit_offset: 16 + bit_size: 2 + - name: DCYC + description: Number of dummy cycles + bit_offset: 18 + bit_size: 5 + - name: DMODE + description: Data mode + bit_offset: 24 + bit_size: 2 + - name: FMODE + description: Functional mode + bit_offset: 26 + bit_size: 2 + - name: SIOO + description: Send instruction only once mode + bit_offset: 28 + bit_size: 1 + - name: DHHC + description: DDR hold half cycle + bit_offset: 30 + bit_size: 1 + - name: DDRM + description: Double data rate mode + bit_offset: 31 + bit_size: 1 fieldset/CR: description: control register fields: - - bit_offset: 0 - bit_size: 1 - description: Enable - name: EN - - bit_offset: 1 - bit_size: 1 - description: Abort request - name: ABORT - - bit_offset: 2 - bit_size: 1 - description: DMA enable - name: DMAEN - - bit_offset: 3 - bit_size: 1 - description: Timeout counter enable - name: TCEN - - bit_offset: 4 - bit_size: 1 - description: Sample shift - name: SSHIFT - - bit_offset: 6 - bit_size: 1 - description: Dual-flash mode - name: DFM - - bit_offset: 7 - bit_size: 1 - description: FLASH memory selection - name: FSEL - - bit_offset: 8 - bit_size: 5 - description: IFO threshold level - name: FTHRES - - bit_offset: 16 - bit_size: 1 - description: Transfer error interrupt enable - name: TEIE - - bit_offset: 17 - bit_size: 1 - description: Transfer complete interrupt enable - name: TCIE - - bit_offset: 18 - bit_size: 1 - description: FIFO threshold interrupt enable - name: FTIE - - bit_offset: 19 - bit_size: 1 - description: Status match interrupt enable - name: SMIE - - bit_offset: 20 - bit_size: 1 - description: TimeOut interrupt enable - name: TOIE - - bit_offset: 22 - bit_size: 1 - description: Automatic poll mode stop - name: APMS - - bit_offset: 23 - bit_size: 1 - description: Polling match mode - name: PMM - - bit_offset: 24 - bit_size: 8 - description: Clock prescaler - name: PRESCALER + - name: EN + description: Enable + bit_offset: 0 + bit_size: 1 + - name: ABORT + description: Abort request + bit_offset: 1 + bit_size: 1 + - name: DMAEN + description: DMA enable + bit_offset: 2 + bit_size: 1 + - name: TCEN + description: Timeout counter enable + bit_offset: 3 + bit_size: 1 + - name: SSHIFT + description: Sample shift + bit_offset: 4 + bit_size: 1 + - name: DFM + description: Dual-flash mode + bit_offset: 6 + bit_size: 1 + - name: FSEL + description: FLASH memory selection + bit_offset: 7 + bit_size: 1 + - name: FTHRES + description: IFO threshold level + bit_offset: 8 + bit_size: 5 + - name: TEIE + description: Transfer error interrupt enable + bit_offset: 16 + bit_size: 1 + - name: TCIE + description: Transfer complete interrupt enable + bit_offset: 17 + bit_size: 1 + - name: FTIE + description: FIFO threshold interrupt enable + bit_offset: 18 + bit_size: 1 + - name: SMIE + description: Status match interrupt enable + bit_offset: 19 + bit_size: 1 + - name: TOIE + description: TimeOut interrupt enable + bit_offset: 20 + bit_size: 1 + - name: APMS + description: Automatic poll mode stop + bit_offset: 22 + bit_size: 1 + - name: PMM + description: Polling match mode + bit_offset: 23 + bit_size: 1 + - name: PRESCALER + description: Clock prescaler + bit_offset: 24 + bit_size: 8 fieldset/DCR: description: device configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: Mode 0 / mode 3 - name: CKMODE - - bit_offset: 8 - bit_size: 3 - description: Chip select high time - name: CSHT - - bit_offset: 16 - bit_size: 5 - description: FLASH memory size - name: FSIZE + - name: CKMODE + description: Mode 0 / mode 3 + bit_offset: 0 + bit_size: 1 + - name: CSHT + description: Chip select high time + bit_offset: 8 + bit_size: 3 + - name: FSIZE + description: FLASH memory size + bit_offset: 16 + bit_size: 5 fieldset/DLR: description: data length register fields: - - bit_offset: 0 - bit_size: 32 - description: Data length - name: DL + - name: DL + description: Data length + bit_offset: 0 + bit_size: 32 fieldset/DR: description: data register fields: - - bit_offset: 0 - bit_size: 32 - description: Data - name: DATA + - name: DATA + description: Data + bit_offset: 0 + bit_size: 32 fieldset/FCR: description: flag clear register fields: - - bit_offset: 0 - bit_size: 1 - description: Clear transfer error flag - name: CTEF - - bit_offset: 1 - bit_size: 1 - description: Clear transfer complete flag - name: CTCF - - bit_offset: 3 - bit_size: 1 - description: Clear status match flag - name: CSMF - - bit_offset: 4 - bit_size: 1 - description: Clear timeout flag - name: CTOF + - name: CTEF + description: Clear transfer error flag + bit_offset: 0 + bit_size: 1 + - name: CTCF + description: Clear transfer complete flag + bit_offset: 1 + bit_size: 1 + - name: CSMF + description: Clear status match flag + bit_offset: 3 + bit_size: 1 + - name: CTOF + description: Clear timeout flag + bit_offset: 4 + bit_size: 1 fieldset/LPTR: description: low-power timeout register fields: - - bit_offset: 0 - bit_size: 16 - description: Timeout period - name: TIMEOUT + - name: TIMEOUT + description: Timeout period + bit_offset: 0 + bit_size: 16 fieldset/PIR: description: polling interval register fields: - - bit_offset: 0 - bit_size: 16 - description: Polling interval - name: INTERVAL + - name: INTERVAL + description: Polling interval + bit_offset: 0 + bit_size: 16 fieldset/PSMAR: description: polling status match register fields: - - bit_offset: 0 - bit_size: 32 - description: Status match - name: MATCH + - name: MATCH + description: Status match + bit_offset: 0 + bit_size: 32 fieldset/PSMKR: description: polling status mask register fields: - - bit_offset: 0 - bit_size: 32 - description: Status mask - name: MASK + - name: MASK + description: Status mask + bit_offset: 0 + bit_size: 32 fieldset/SR: description: status register fields: - - bit_offset: 0 - bit_size: 1 - description: Transfer error flag - name: TEF - - bit_offset: 1 - bit_size: 1 - description: Transfer complete flag - name: TCF - - bit_offset: 2 - bit_size: 1 - description: FIFO threshold flag - name: FTF - - bit_offset: 3 - bit_size: 1 - description: Status match flag - name: SMF - - bit_offset: 4 - bit_size: 1 - description: Timeout flag - name: TOF - - bit_offset: 5 - bit_size: 1 - description: Busy - name: BUSY - - bit_offset: 8 - bit_size: 7 - description: FIFO level - name: FLEVEL + - name: TEF + description: Transfer error flag + bit_offset: 0 + bit_size: 1 + - name: TCF + description: Transfer complete flag + bit_offset: 1 + bit_size: 1 + - name: FTF + description: FIFO threshold flag + bit_offset: 2 + bit_size: 1 + - name: SMF + description: Status match flag + bit_offset: 3 + bit_size: 1 + - name: TOF + description: Timeout flag + bit_offset: 4 + bit_size: 1 + - name: BUSY + description: Busy + bit_offset: 5 + bit_size: 1 + - name: FLEVEL + description: FIFO level + bit_offset: 8 + bit_size: 7 diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index dd27e52..cc34396 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -1,1125 +1,1126 @@ +--- block/RCC: description: Reset and clock control items: - - byte_offset: 0 - description: Clock control register - fieldset: CR - name: CR - - byte_offset: 4 - description: Clock configuration register (RCC_CFGR) - fieldset: CFGR - name: CFGR - - byte_offset: 8 - description: Clock interrupt register (RCC_CIR) - fieldset: CIR - name: CIR - - byte_offset: 12 - description: APB2 peripheral reset register (RCC_APB2RSTR) - fieldset: APB2RSTR - name: APB2RSTR - - byte_offset: 16 - description: APB1 peripheral reset register (RCC_APB1RSTR) - fieldset: APB1RSTR - name: APB1RSTR - - byte_offset: 20 - description: AHB Peripheral Clock enable register (RCC_AHBENR) - fieldset: AHBENR - name: AHBENR - - byte_offset: 24 - description: APB2 peripheral clock enable register (RCC_APB2ENR) - fieldset: APB2ENR - name: APB2ENR - - byte_offset: 28 - description: APB1 peripheral clock enable register (RCC_APB1ENR) - fieldset: APB1ENR - name: APB1ENR - - byte_offset: 32 - description: Backup domain control register (RCC_BDCR) - fieldset: BDCR - name: BDCR - - byte_offset: 36 - description: Control/status register (RCC_CSR) - fieldset: CSR - name: CSR - - byte_offset: 40 - description: AHB peripheral clock reset register (RCC_AHBRSTR) - fieldset: AHBRSTR - name: AHBRSTR - - byte_offset: 44 - description: Clock configuration register 2 - fieldset: CFGR2 - name: CFGR2 -enum/ADCPRE: - bit_size: 2 - variants: - - description: PCLK2 divided by 2 - name: Div2 - value: 0 - - description: PCLK2 divided by 4 - name: Div4 - value: 1 - - description: PCLK2 divided by 8 - name: Div6 - value: 2 - - description: PCLK2 divided by 16 - name: Div8 - value: 3 -enum/HPRE: - bit_size: 4 - variants: - - description: SYSCLK not divided - name: Div1 - value: 0 - - description: SYSCLK divided by 2 - name: Div2 - value: 8 - - description: SYSCLK divided by 4 - name: Div4 - value: 9 - - description: SYSCLK divided by 8 - name: Div8 - value: 10 - - description: SYSCLK divided by 16 - name: Div16 - value: 11 - - description: SYSCLK divided by 64 - name: Div64 - value: 12 - - description: SYSCLK divided by 128 - name: Div128 - value: 13 - - description: SYSCLK divided by 256 - name: Div256 - value: 14 - - description: SYSCLK divided by 512 - name: Div512 - value: 15 -enum/I2S2SRC: - bit_size: 1 - variants: - - description: System clock (SYSCLK) selected as I2S clock entry - name: SYSCLK - value: 0 - - description: PLL3 VCO clock selected as I2S clock entry - name: PLL3 - value: 1 -enum/MCO: - bit_size: 4 - variants: - - description: MCO output disabled, no clock on MCO - name: NoMCO - value: 0 - - description: System clock selected - name: SYSCLK - value: 4 - - description: HSI oscillator clock selected - name: HSI - value: 5 - - description: HSE oscillator clock selected - name: HSE - value: 6 - - description: PLL clock selected (divided by 1 or 2, depending en PLLNODIV) - name: PLL - value: 7 -enum/OTGFSPRE: - bit_size: 1 - variants: - - description: PLL clock is divided by 1.5 - name: DIV1_5 - value: 0 - - description: PLL clock is not divided - name: DIV1 - value: 1 -enum/PLL2MUL: - bit_size: 4 - variants: - - description: PLL clock entry x8 - name: Mul8 - value: 6 - - description: PLL clock entry x9 - name: Mul9 - value: 7 - - description: PLL clock entry x10 - name: Mul10 - value: 8 - - description: PLL clock entry x11 - name: Mul11 - value: 9 - - description: PLL clock entry x12 - name: Mul12 - value: 10 - - description: PLL clock entry x13 - name: Mul13 - value: 11 - - description: PLL clock entry x14 - name: Mul14 - value: 12 - - description: PLL clock entry x16 - name: Mul16 - value: 14 - - description: PLL clock entry x20 - name: Mul20 - value: 15 -enum/PLLMUL: - bit_size: 4 - variants: - - description: PLL input clock x2 - name: Mul2 - value: 0 - - description: PLL input clock x3 - name: Mul3 - value: 1 - - description: PLL input clock x4 - name: Mul4 - value: 2 - - description: PLL input clock x5 - name: Mul5 - value: 3 - - description: PLL input clock x6 - name: Mul6 - value: 4 - - description: PLL input clock x7 - name: Mul7 - value: 5 - - description: PLL input clock x8 - name: Mul8 - value: 6 - - description: PLL input clock x9 - name: Mul9 - value: 7 - - description: PLL input clock x10 - name: Mul10 - value: 8 - - description: PLL input clock x11 - name: Mul11 - value: 9 - - description: PLL input clock x12 - name: Mul12 - value: 10 - - description: PLL input clock x13 - name: Mul13 - value: 11 - - description: PLL input clock x14 - name: Mul14 - value: 12 - - description: PLL input clock x15 - name: Mul15 - value: 13 - - description: PLL input clock x16 - name: Mul16 - value: 14 - - description: PLL input clock x16 - name: Mul16x - value: 15 -enum/PLLSRC: - bit_size: 1 - variants: - - description: HSI divided by 2 selected as PLL input clock - name: HSI_Div2 - value: 0 - - description: HSE divided by PREDIV selected as PLL input clock - name: HSE_Div_PREDIV - value: 1 -enum/PLLXTPRE: - bit_size: 1 - variants: - - description: HSE clock not divided - name: Div1 - value: 0 - - description: HSE clock divided by 2 - name: Div2 - value: 1 -enum/PPRE1: - bit_size: 3 - variants: - - description: HCLK not divided - name: Div1 - value: 0 - - description: HCLK divided by 2 - name: Div2 - value: 4 - - description: HCLK divided by 4 - name: Div4 - value: 5 - - description: HCLK divided by 8 - name: Div8 - value: 6 - - description: HCLK divided by 16 - name: Div16 - value: 7 -enum/PREDIV1: - bit_size: 4 - variants: - - description: PREDIV input clock not divided - name: Div1 - value: 0 - - description: PREDIV input clock divided by 2 - name: Div2 - value: 1 - - description: PREDIV input clock divided by 3 - name: Div3 - value: 2 - - description: PREDIV input clock divided by 4 - name: Div4 - value: 3 - - description: PREDIV input clock divided by 5 - name: Div5 - value: 4 - - description: PREDIV input clock divided by 6 - name: Div6 - value: 5 - - description: PREDIV input clock divided by 7 - name: Div7 - value: 6 - - description: PREDIV input clock divided by 8 - name: Div8 - value: 7 - - description: PREDIV input clock divided by 9 - name: Div9 - value: 8 - - description: PREDIV input clock divided by 10 - name: Div10 - value: 9 - - description: PREDIV input clock divided by 11 - name: Div11 - value: 10 - - description: PREDIV input clock divided by 12 - name: Div12 - value: 11 - - description: PREDIV input clock divided by 13 - name: Div13 - value: 12 - - description: PREDIV input clock divided by 14 - name: Div14 - value: 13 - - description: PREDIV input clock divided by 15 - name: Div15 - value: 14 - - description: PREDIV input clock divided by 16 - name: Div16 - value: 15 -enum/PREDIV1SRC: - bit_size: 1 - variants: - - description: HSE oscillator clock selected as PREDIV1 clock entry - name: HSE - value: 0 - - description: PLL2 selected as PREDIV1 clock entry - name: PLL2 - value: 1 -enum/RTCSEL: - bit_size: 2 - variants: - - description: No clock - name: NoClock - value: 0 - - description: LSE oscillator clock used as RTC clock - name: LSE - value: 1 - - description: LSI oscillator clock used as RTC clock - name: LSI - value: 2 - - description: HSE oscillator clock divided by a prescaler used as RTC clock - name: HSE - value: 3 -enum/SW: - bit_size: 2 - variants: - - description: HSI selected as system clock - name: HSI - value: 0 - - description: HSE selected as system clock - name: HSE - value: 1 - - description: PLL selected as system clock - name: PLL - value: 2 -enum/SWSR: - bit_size: 2 - variants: - - description: HSI oscillator used as system clock - name: HSI - value: 0 - - description: HSE oscillator used as system clock - name: HSE - value: 1 - - description: PLL used as system clock - name: PLL - value: 2 -enum/USBPRE: - bit_size: 1 - variants: - - description: PLL clock is divided by 1.5 - name: DIV1_5 - value: 0 - - description: PLL clock is not divided - name: DIV1 - value: 1 + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: AHBRSTR + description: AHB peripheral clock reset register (RCC_AHBRSTR) + byte_offset: 40 + fieldset: AHBRSTR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 fieldset/AHBENR: description: AHB Peripheral Clock enable register (RCC_AHBENR) fields: - - bit_offset: 0 - bit_size: 1 - description: DMA1 clock enable - name: DMA1EN - - bit_offset: 1 - bit_size: 1 - description: DMA2 clock enable - name: DMA2EN - - bit_offset: 2 - bit_size: 1 - description: SRAM interface clock enable - name: SRAMEN - - bit_offset: 4 - bit_size: 1 - description: FLITF clock enable - name: FLITFEN - - bit_offset: 6 - bit_size: 1 - description: CRC clock enable - name: CRCEN - - bit_offset: 8 - bit_size: 1 - description: FSMC clock enable - name: FSMCEN - - bit_offset: 10 - bit_size: 1 - description: SDIO clock enable - name: SDIOEN - - bit_offset: 12 - bit_size: 1 - description: USB OTG FS clock enable - name: OTGFSEN - - bit_offset: 14 - bit_size: 1 - description: Ethernet MAC clock enable - name: ETHMACEN - - bit_offset: 15 - bit_size: 1 - description: Ethernet MAC TX clock enable - name: ETHMACTXEN - - bit_offset: 16 - bit_size: 1 - description: Ethernet MAC RX clock enable - name: ETHMACRXEN + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLITFEN + description: FLITF clock enable + bit_offset: 4 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: FSMCEN + description: FSMC clock enable + bit_offset: 8 + bit_size: 1 + - name: SDIOEN + description: SDIO clock enable + bit_offset: 10 + bit_size: 1 + - name: OTGFSEN + description: USB OTG FS clock enable + bit_offset: 12 + bit_size: 1 + - name: ETHMACEN + description: Ethernet MAC clock enable + bit_offset: 14 + bit_size: 1 + - name: ETHMACTXEN + description: Ethernet MAC TX clock enable + bit_offset: 15 + bit_size: 1 + - name: ETHMACRXEN + description: Ethernet MAC RX clock enable + bit_offset: 16 + bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral clock reset register (RCC_AHBRSTR) fields: - - bit_offset: 12 - bit_size: 1 - description: USB OTG FS reset - name: OTGFSRST - - bit_offset: 14 - bit_size: 1 - description: Ethernet MAC reset - name: ETHMACRST + - name: OTGFSRST + description: USB OTG FS reset + bit_offset: 12 + bit_size: 1 + - name: ETHMACRST + description: Ethernet MAC reset + bit_offset: 14 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register (RCC_APB1ENR) fields: - - bit_offset: 0 - bit_size: 1 - description: Timer 2 clock enable - name: TIM2EN - - bit_offset: 1 - bit_size: 1 - description: Timer 3 clock enable - name: TIM3EN - - bit_offset: 2 - bit_size: 1 - description: Timer 4 clock enable - name: TIM4EN - - bit_offset: 3 - bit_size: 1 - description: Timer 5 clock enable - name: TIM5EN - - bit_offset: 4 - bit_size: 1 - description: Timer 6 clock enable - name: TIM6EN - - bit_offset: 5 - bit_size: 1 - description: Timer 7 clock enable - name: TIM7EN - - bit_offset: 6 - bit_size: 1 - description: Timer 12 clock enable - name: TIM12EN - - bit_offset: 7 - bit_size: 1 - description: Timer 13 clock enable - name: TIM13EN - - bit_offset: 8 - bit_size: 1 - description: Timer 14 clock enable - name: TIM14EN - - bit_offset: 11 - bit_size: 1 - description: Window watchdog clock enable - name: WWDGEN - - bit_offset: 14 - bit_size: 1 - description: SPI 2 clock enable - name: SPI2EN - - bit_offset: 15 - bit_size: 1 - description: SPI 3 clock enable - name: SPI3EN - - bit_offset: 17 - bit_size: 1 - description: USART 2 clock enable - name: USART2EN - - bit_offset: 18 - bit_size: 1 - description: USART 3 clock enable - name: USART3EN - - bit_offset: 19 - bit_size: 1 - description: UART 4 clock enable - name: UART4EN - - bit_offset: 20 - bit_size: 1 - description: UART 5 clock enable - name: UART5EN - - bit_offset: 21 - bit_size: 1 - description: I2C 1 clock enable - name: I2C1EN - - bit_offset: 22 - bit_size: 1 - description: I2C 2 clock enable - name: I2C2EN - - bit_offset: 23 - bit_size: 1 - description: USB clock enable - name: USBEN - - bit_offset: 25 - bit_size: 1 - description: CAN clock enable - name: CANEN - - bit_offset: 25 - bit_size: 1 - description: CAN1 clock enable - name: CAN1EN - - bit_offset: 26 - bit_size: 1 - description: CAN2 clock enable - name: CAN2EN - - bit_offset: 27 - bit_size: 1 - description: Backup interface clock enable - name: BKPEN - - bit_offset: 28 - bit_size: 1 - description: Power interface clock enable - name: PWREN - - bit_offset: 29 - bit_size: 1 - description: DAC interface clock enable - name: DACEN - - bit_offset: 30 - bit_size: 1 - description: CEC clock enable - name: CECEN + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: Timer 5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: Timer 12 clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: Timer 13 clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: Timer 14 clock enable + bit_offset: 8 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI 3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART 4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART 5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB clock enable + bit_offset: 23 + bit_size: 1 + - name: CANEN + description: CAN clock enable + bit_offset: 25 + bit_size: 1 + - name: CAN1EN + description: CAN1 clock enable + bit_offset: 25 + bit_size: 1 + - name: CAN2EN + description: CAN2 clock enable + bit_offset: 26 + bit_size: 1 + - name: BKPEN + description: Backup interface clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: CECEN + description: CEC clock enable + bit_offset: 30 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register (RCC_APB1RSTR) fields: - - bit_offset: 0 - bit_size: 1 - description: Timer 2 reset - name: TIM2RST - - bit_offset: 1 - bit_size: 1 - description: Timer 3 reset - name: TIM3RST - - bit_offset: 2 - bit_size: 1 - description: Timer 4 reset - name: TIM4RST - - bit_offset: 3 - bit_size: 1 - description: Timer 5 reset - name: TIM5RST - - bit_offset: 4 - bit_size: 1 - description: Timer 6 reset - name: TIM6RST - - bit_offset: 5 - bit_size: 1 - description: Timer 7 reset - name: TIM7RST - - bit_offset: 6 - bit_size: 1 - description: Timer 12 reset - name: TIM12RST - - bit_offset: 7 - bit_size: 1 - description: Timer 13 reset - name: TIM13RST - - bit_offset: 8 - bit_size: 1 - description: Timer 14 reset - name: TIM14RST - - bit_offset: 11 - bit_size: 1 - description: Window watchdog reset - name: WWDGRST - - bit_offset: 14 - bit_size: 1 - description: SPI2 reset - name: SPI2RST - - bit_offset: 15 - bit_size: 1 - description: SPI3 reset - name: SPI3RST - - bit_offset: 17 - bit_size: 1 - description: USART 2 reset - name: USART2RST - - bit_offset: 18 - bit_size: 1 - description: USART 3 reset - name: USART3RST - - bit_offset: 19 - bit_size: 1 - description: USART 4 reset - name: UART4RST - - bit_offset: 20 - bit_size: 1 - description: USART 5 reset - name: UART5RST - - bit_offset: 21 - bit_size: 1 - description: I2C1 reset - name: I2C1RST - - bit_offset: 22 - bit_size: 1 - description: I2C2 reset - name: I2C2RST - - bit_offset: 23 - bit_size: 1 - description: USB reset - name: USBRST - - bit_offset: 25 - bit_size: 1 - description: CAN reset - name: CANRST - - bit_offset: 25 - bit_size: 1 - description: CAN1 reset - name: CAN1RST - - bit_offset: 26 - bit_size: 1 - description: CAN2 reset - name: CAN2RST - - bit_offset: 27 - bit_size: 1 - description: Backup interface reset - name: BKPRST - - bit_offset: 28 - bit_size: 1 - description: Power interface reset - name: PWRRST - - bit_offset: 29 - bit_size: 1 - description: DAC interface reset - name: DACRST - - bit_offset: 30 - bit_size: 1 - description: CEC reset - name: CECRST + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: Timer 4 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: Timer 5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: Timer 12 reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: Timer 13 reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: Timer 14 reset + bit_offset: 8 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART 3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: USART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: USART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USB reset + bit_offset: 23 + bit_size: 1 + - name: CANRST + description: CAN reset + bit_offset: 25 + bit_size: 1 + - name: CAN1RST + description: CAN1 reset + bit_offset: 25 + bit_size: 1 + - name: CAN2RST + description: CAN2 reset + bit_offset: 26 + bit_size: 1 + - name: BKPRST + description: Backup interface reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + - name: CECRST + description: CEC reset + bit_offset: 30 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register (RCC_APB2ENR) fields: - - bit_offset: 0 - bit_size: 1 - description: Alternate function I/O clock enable - name: AFIOEN - - bit_offset: 2 - bit_size: 1 - description: I/O port A clock enable - name: GPIOAEN - - bit_offset: 3 - bit_size: 1 - description: I/O port B clock enable - name: GPIOBEN - - bit_offset: 4 - bit_size: 1 - description: I/O port C clock enable - name: GPIOCEN - - bit_offset: 5 - bit_size: 1 - description: I/O port D clock enable - name: GPIODEN - - bit_offset: 6 - bit_size: 1 - description: I/O port E clock enable - name: GPIOEEN - - bit_offset: 7 - bit_size: 1 - description: I/O port F clock enable - name: GPIOFEN - - bit_offset: 8 - bit_size: 1 - description: I/O port G clock enable - name: GPIOGEN - - bit_offset: 9 - bit_size: 1 - description: ADC 1 interface clock enable - name: ADC1EN - - bit_offset: 10 - bit_size: 1 - description: ADC 2 interface clock enable - name: ADC2EN - - bit_offset: 11 - bit_size: 1 - description: TIM1 Timer clock enable - name: TIM1EN - - bit_offset: 12 - bit_size: 1 - description: SPI 1 clock enable - name: SPI1EN - - bit_offset: 13 - bit_size: 1 - description: TIM8 Timer clock enable - name: TIM8EN - - bit_offset: 14 - bit_size: 1 - description: USART1 clock enable - name: USART1EN - - bit_offset: 15 - bit_size: 1 - description: ADC3 interface clock enable - name: ADC3EN - - bit_offset: 16 - bit_size: 1 - description: TIM15 Timer clock enable - name: TIM15EN - - bit_offset: 17 - bit_size: 1 - description: TIM16 Timer clock enable - name: TIM16EN - - bit_offset: 18 - bit_size: 1 - description: TIM17 Timer clock enable - name: TIM17EN - - bit_offset: 19 - bit_size: 1 - description: TIM9 Timer clock enable - name: TIM9EN - - bit_offset: 20 - bit_size: 1 - description: TIM10 Timer clock enable - name: TIM10EN - - bit_offset: 21 - bit_size: 1 - description: TIM11 Timer clock enable - name: TIM11EN + - name: AFIOEN + description: Alternate function I/O clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOEEN + description: I/O port E clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOFEN + description: I/O port F clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOGEN + description: I/O port G clock enable + bit_offset: 8 + bit_size: 1 + - name: ADC1EN + description: ADC 1 interface clock enable + bit_offset: 9 + bit_size: 1 + - name: ADC2EN + description: ADC 2 interface clock enable + bit_offset: 10 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: TIM8 Timer clock enable + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: ADC3EN + description: ADC3 interface clock enable + bit_offset: 15 + bit_size: 1 + - name: TIM15EN + description: TIM15 Timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 Timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 Timer clock enable + bit_offset: 18 + bit_size: 1 + - name: TIM9EN + description: TIM9 Timer clock enable + bit_offset: 19 + bit_size: 1 + - name: TIM10EN + description: TIM10 Timer clock enable + bit_offset: 20 + bit_size: 1 + - name: TIM11EN + description: TIM11 Timer clock enable + bit_offset: 21 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register (RCC_APB2RSTR) fields: - - bit_offset: 0 - bit_size: 1 - description: Alternate function I/O reset - name: AFIORST - - bit_offset: 2 - bit_size: 1 - description: IO port A reset - name: GPIOARST - - bit_offset: 3 - bit_size: 1 - description: IO port B reset - name: GPIOBRST - - bit_offset: 4 - bit_size: 1 - description: IO port C reset - name: GPIOCRST - - bit_offset: 5 - bit_size: 1 - description: IO port D reset - name: GPIODRST - - bit_offset: 6 - bit_size: 1 - description: IO port E reset - name: GPIOERST - - bit_offset: 7 - bit_size: 1 - description: IO port F reset - name: GPIOFRST - - bit_offset: 8 - bit_size: 1 - description: IO port G reset - name: GPIOGRST - - bit_offset: 9 - bit_size: 1 - description: ADC 1 interface reset - name: ADC1RST - - bit_offset: 10 - bit_size: 1 - description: ADC 2 interface reset - name: ADC2RST - - bit_offset: 11 - bit_size: 1 - description: TIM1 timer reset - name: TIM1RST - - bit_offset: 12 - bit_size: 1 - description: SPI 1 reset - name: SPI1RST - - bit_offset: 13 - bit_size: 1 - description: TIM8 timer reset - name: TIM8RST - - bit_offset: 14 - bit_size: 1 - description: USART1 reset - name: USART1RST - - bit_offset: 15 - bit_size: 1 - description: ADC 3 interface reset - name: ADC3RST - - bit_offset: 16 - bit_size: 1 - description: TIM15 timer reset - name: TIM15RST - - bit_offset: 17 - bit_size: 1 - description: TIM16 timer reset - name: TIM16RST - - bit_offset: 18 - bit_size: 1 - description: TIM17 timer reset - name: TIM17RST - - bit_offset: 19 - bit_size: 1 - description: TIM9 timer reset - name: TIM9RST - - bit_offset: 20 - bit_size: 1 - description: TIM10 timer reset - name: TIM10RST - - bit_offset: 21 - bit_size: 1 - description: TIM11 timer reset - name: TIM11RST + - name: AFIORST + description: Alternate function I/O reset + bit_offset: 0 + bit_size: 1 + - name: GPIOARST + description: IO port A reset + bit_offset: 2 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 3 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 4 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 5 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 6 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 7 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 8 + bit_size: 1 + - name: ADC1RST + description: ADC 1 interface reset + bit_offset: 9 + bit_size: 1 + - name: ADC2RST + description: ADC 2 interface reset + bit_offset: 10 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: TIM8 timer reset + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: ADC3RST + description: ADC 3 interface reset + bit_offset: 15 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: TIM9RST + description: TIM9 timer reset + bit_offset: 19 + bit_size: 1 + - name: TIM10RST + description: TIM10 timer reset + bit_offset: 20 + bit_size: 1 + - name: TIM11RST + description: TIM11 timer reset + bit_offset: 21 + bit_size: 1 fieldset/BDCR: description: Backup domain control register (RCC_BDCR) fields: - - bit_offset: 0 - bit_size: 1 - description: External Low Speed oscillator enable - name: LSEON - - bit_offset: 1 - bit_size: 1 - description: External Low Speed oscillator ready - name: LSERDY - - bit_offset: 2 - bit_size: 1 - description: External Low Speed oscillator bypass - name: LSEBYP - - bit_offset: 8 - bit_size: 2 - description: RTC clock source selection - enum: RTCSEL - name: RTCSEL - - bit_offset: 15 - bit_size: 1 - description: RTC clock enable - name: RTCEN - - bit_offset: 16 - bit_size: 1 - description: Backup domain software reset - name: BDRST + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 fieldset/CFGR: description: Clock configuration register (RCC_CFGR) fields: - - bit_offset: 0 - bit_size: 2 - description: System clock Switch - enum: SW - name: SW - - bit_offset: 2 - bit_size: 2 - description: System Clock Switch Status - enum_read: SWSR - name: SWS - - bit_offset: 4 - bit_size: 4 - description: AHB prescaler - enum: HPRE - name: HPRE - - bit_offset: 8 - bit_size: 3 - description: APB Low speed prescaler (APB1) - enum: PPRE1 - name: PPRE1 - - bit_offset: 11 - bit_size: 3 - description: APB High speed prescaler (APB2) - enum: PPRE1 - name: PPRE2 - - bit_offset: 14 - bit_size: 2 - description: ADC prescaler - enum: ADCPRE - name: ADCPRE - - bit_offset: 16 - bit_size: 1 - description: PLL entry clock source - enum: PLLSRC - name: PLLSRC - - bit_offset: 17 - bit_size: 1 - description: HSE divider for PLL entry - enum: PLLXTPRE - name: PLLXTPRE - - bit_offset: 18 - bit_size: 4 - description: PLL Multiplication Factor - enum: PLLMUL - name: PLLMUL - - bit_offset: 22 - bit_size: 1 - description: USB prescaler - enum: USBPRE - name: USBPRE - - bit_offset: 22 - bit_size: 1 - description: USB OTG FS prescaler - enum: OTGFSPRE - name: OTGFSPRE - - bit_offset: 24 - bit_size: 3 - description: Microcontroller clock output - enum: MCO - name: MCO + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum_read: SWSR + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE1 + - name: PPRE2 + description: APB High speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE1 + - name: ADCPRE + description: ADC prescaler + bit_offset: 14 + bit_size: 2 + enum: ADCPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLXTPRE + description: HSE divider for PLL entry + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: USBPRE + description: USB prescaler + bit_offset: 22 + bit_size: 1 + enum: USBPRE + - name: OTGFSPRE + description: USB OTG FS prescaler + bit_offset: 22 + bit_size: 1 + enum: OTGFSPRE + - name: MCO + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCO fieldset/CFGR2: description: Clock configuration register2 (RCC_CFGR2) fields: - - bit_offset: 0 - bit_size: 4 - description: PREDIV1 division factor - enum: PREDIV1 - name: PREDIV1 - - bit_offset: 4 - bit_size: 4 - description: PREDIV2 division factor - enum: PREDIV1 - name: PREDIV2 - - bit_offset: 8 - bit_size: 4 - description: PLL2 Multiplication Factor - enum: PLL2MUL - name: PLL2MUL - - bit_offset: 12 - bit_size: 4 - description: PLL3 Multiplication Factor - enum: PLL2MUL - name: PLL3MUL - - bit_offset: 16 - bit_size: 1 - description: PREDIV1 entry clock source - enum: PREDIV1SRC - name: PREDIV1SRC - - bit_offset: 17 - bit_size: 1 - description: I2S2 clock source - enum: I2S2SRC - name: I2S2SRC - - bit_offset: 18 - bit_size: 1 - description: I2S3 clock source - enum: I2S2SRC - name: I2S3SRC + - name: PREDIV1 + description: PREDIV1 division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV1 + - name: PREDIV2 + description: PREDIV2 division factor + bit_offset: 4 + bit_size: 4 + enum: PREDIV1 + - name: PLL2MUL + description: PLL2 Multiplication Factor + bit_offset: 8 + bit_size: 4 + enum: PLL2MUL + - name: PLL3MUL + description: PLL3 Multiplication Factor + bit_offset: 12 + bit_size: 4 + enum: PLL2MUL + - name: PREDIV1SRC + description: PREDIV1 entry clock source + bit_offset: 16 + bit_size: 1 + enum: PREDIV1SRC + - name: I2S2SRC + description: I2S2 clock source + bit_offset: 17 + bit_size: 1 + enum: I2S2SRC + - name: I2S3SRC + description: I2S3 clock source + bit_offset: 18 + bit_size: 1 + enum: I2S2SRC fieldset/CIR: description: Clock interrupt register (RCC_CIR) fields: - - bit_offset: 0 - bit_size: 1 - description: LSI Ready Interrupt flag - name: LSIRDYF - - bit_offset: 1 - bit_size: 1 - description: LSE Ready Interrupt flag - name: LSERDYF - - bit_offset: 2 - bit_size: 1 - description: HSI Ready Interrupt flag - name: HSIRDYF - - bit_offset: 3 - bit_size: 1 - description: HSE Ready Interrupt flag - name: HSERDYF - - bit_offset: 4 - bit_size: 1 - description: PLL Ready Interrupt flag - name: PLLRDYF - - bit_offset: 5 - bit_size: 1 - description: PLL2 Ready Interrupt flag - name: PLL2RDYF - - bit_offset: 6 - bit_size: 1 - description: PLL3 Ready Interrupt flag - name: PLL3RDYF - - bit_offset: 7 - bit_size: 1 - description: Clock Security System Interrupt flag - name: CSSF - - bit_offset: 8 - bit_size: 1 - description: LSI Ready Interrupt Enable - name: LSIRDYIE - - bit_offset: 9 - bit_size: 1 - description: LSE Ready Interrupt Enable - name: LSERDYIE - - bit_offset: 10 - bit_size: 1 - description: HSI Ready Interrupt Enable - name: HSIRDYIE - - bit_offset: 11 - bit_size: 1 - description: HSE Ready Interrupt Enable - name: HSERDYIE - - bit_offset: 12 - bit_size: 1 - description: PLL Ready Interrupt Enable - name: PLLRDYIE - - bit_offset: 13 - bit_size: 1 - description: PLL2 Ready Interrupt Enable - name: PLL2RDYIE - - bit_offset: 14 - bit_size: 1 - description: PLL3 Ready Interrupt Enable - name: PLL3RDYIE - - bit_offset: 16 - bit_size: 1 - description: LSI Ready Interrupt Clear - name: LSIRDYC - - bit_offset: 17 - bit_size: 1 - description: LSE Ready Interrupt Clear - name: LSERDYC - - bit_offset: 18 - bit_size: 1 - description: HSI Ready Interrupt Clear - name: HSIRDYC - - bit_offset: 19 - bit_size: 1 - description: HSE Ready Interrupt Clear - name: HSERDYC - - bit_offset: 20 - bit_size: 1 - description: PLL Ready Interrupt Clear - name: PLLRDYC - - bit_offset: 21 - bit_size: 1 - description: PLL2 Ready Interrupt Clear - name: PLL2RDYC - - bit_offset: 22 - bit_size: 1 - description: PLL3 Ready Interrupt Clear - name: PLL3RDYC - - bit_offset: 23 - bit_size: 1 - description: Clock security system interrupt clear - name: CSSC + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLL2RDYF + description: PLL2 Ready Interrupt flag + bit_offset: 5 + bit_size: 1 + - name: PLL3RDYF + description: PLL3 Ready Interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + - name: PLL2RDYIE + description: PLL2 Ready Interrupt Enable + bit_offset: 13 + bit_size: 1 + - name: PLL3RDYIE + description: PLL3 Ready Interrupt Enable + bit_offset: 14 + bit_size: 1 + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + - name: PLL2RDYC + description: PLL2 Ready Interrupt Clear + bit_offset: 21 + bit_size: 1 + - name: PLL3RDYC + description: PLL3 Ready Interrupt Clear + bit_offset: 22 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - bit_offset: 0 - bit_size: 1 - description: Internal High Speed clock enable - name: HSION - - bit_offset: 1 - bit_size: 1 - description: Internal High Speed clock ready flag - name: HSIRDY - - bit_offset: 3 - bit_size: 5 - description: Internal High Speed clock trimming - name: HSITRIM - - bit_offset: 8 - bit_size: 8 - description: Internal High Speed clock Calibration - name: HSICAL - - bit_offset: 16 - bit_size: 1 - description: External High Speed clock enable - name: HSEON - - bit_offset: 17 - bit_size: 1 - description: External High Speed clock ready flag - name: HSERDY - - bit_offset: 18 - bit_size: 1 - description: External High Speed clock Bypass - name: HSEBYP - - bit_offset: 19 - bit_size: 1 - description: Clock Security System enable - name: CSSON - - bit_offset: 24 - bit_size: 1 - description: PLL enable - name: PLLON - - bit_offset: 25 - bit_size: 1 - description: PLL clock ready flag - name: PLLRDY - - bit_offset: 26 - bit_size: 1 - description: PLL2 enable - name: PLL2ON - - bit_offset: 27 - bit_size: 1 - description: PLL2 clock ready flag - name: PLL2RDY - - bit_offset: 28 - bit_size: 1 - description: PLL3 enable - name: PLL3ON - - bit_offset: 29 - bit_size: 1 - description: PLL3 clock ready flag - name: PLL3RDY + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 + - name: PLL2ON + description: PLL2 enable + bit_offset: 26 + bit_size: 1 + - name: PLL2RDY + description: PLL2 clock ready flag + bit_offset: 27 + bit_size: 1 + - name: PLL3ON + description: PLL3 enable + bit_offset: 28 + bit_size: 1 + - name: PLL3RDY + description: PLL3 clock ready flag + bit_offset: 29 + bit_size: 1 fieldset/CSR: description: Control/status register (RCC_CSR) fields: - - bit_offset: 0 - bit_size: 1 - description: Internal low speed oscillator enable - name: LSION - - bit_offset: 1 - bit_size: 1 - description: Internal low speed oscillator ready - name: LSIRDY - - bit_offset: 24 - bit_size: 1 - description: Remove reset flag - name: RMVF - - bit_offset: 26 - bit_size: 1 - description: PIN reset flag - name: PINRSTF - - bit_offset: 27 - bit_size: 1 - description: POR/PDR reset flag - name: PORRSTF - - bit_offset: 28 - bit_size: 1 - description: Software reset flag - name: SFTRSTF - - bit_offset: 29 - bit_size: 1 - description: Independent watchdog reset flag - name: IWDGRSTF - - bit_offset: 30 - bit_size: 1 - description: Window watchdog reset flag - name: WWDGRSTF - - bit_offset: 31 - bit_size: 1 - description: Low-power reset flag - name: LPWRRSTF + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 +enum/ADCPRE: + bit_size: 2 + variants: + - name: Div2 + description: PCLK2 divided by 2 + value: 0 + - name: Div4 + description: PCLK2 divided by 4 + value: 1 + - name: Div6 + description: PCLK2 divided by 8 + value: 2 + - name: Div8 + description: PCLK2 divided by 16 + value: 3 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/I2S2SRC: + bit_size: 1 + variants: + - name: SYSCLK + description: System clock (SYSCLK) selected as I2S clock entry + value: 0 + - name: PLL3 + description: PLL3 VCO clock selected as I2S clock entry + value: 1 +enum/MCO: + bit_size: 4 + variants: + - name: NoMCO + description: "MCO output disabled, no clock on MCO" + value: 0 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: HSI oscillator clock selected + value: 5 + - name: HSE + description: HSE oscillator clock selected + value: 6 + - name: PLL + description: "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)" + value: 7 +enum/OTGFSPRE: + bit_size: 1 + variants: + - name: DIV1_5 + description: PLL clock is divided by 1.5 + value: 0 + - name: DIV1 + description: PLL clock is not divided + value: 1 +enum/PLL2MUL: + bit_size: 4 + variants: + - name: Mul8 + description: PLL clock entry x8 + value: 6 + - name: Mul9 + description: PLL clock entry x9 + value: 7 + - name: Mul10 + description: PLL clock entry x10 + value: 8 + - name: Mul11 + description: PLL clock entry x11 + value: 9 + - name: Mul12 + description: PLL clock entry x12 + value: 10 + - name: Mul13 + description: PLL clock entry x13 + value: 11 + - name: Mul14 + description: PLL clock entry x14 + value: 12 + - name: Mul16 + description: PLL clock entry x16 + value: 14 + - name: Mul20 + description: PLL clock entry x20 + value: 15 +enum/PLLMUL: + bit_size: 4 + variants: + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 + - name: Mul16x + description: PLL input clock x16 + value: 15 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 1 +enum/PLLXTPRE: + bit_size: 1 + variants: + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 +enum/PPRE1: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/PREDIV1: + bit_size: 4 + variants: + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 +enum/PREDIV1SRC: + bit_size: 1 + variants: + - name: HSE + description: HSE oscillator clock selected as PREDIV1 clock entry + value: 0 + - name: PLL2 + description: PLL2 selected as PREDIV1 clock entry + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLL + description: PLL selected as system clock + value: 2 +enum/SWSR: + bit_size: 2 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 +enum/USBPRE: + bit_size: 1 + variants: + - name: DIV1_5 + description: PLL clock is divided by 1.5 + value: 0 + - name: DIV1 + description: PLL clock is not divided + value: 1 diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 91d8ce1..49e0bd0 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -1,2735 +1,2729 @@ +--- block/RCC: description: Reset and clock control items: - - byte_offset: 0 - description: clock control register - fieldset: CR - name: CR - - byte_offset: 4 - description: PLL configuration register - fieldset: PLLCFGR - name: PLLCFGR - - byte_offset: 8 - description: clock configuration register - fieldset: CFGR - name: CFGR - - byte_offset: 12 - description: clock interrupt register - fieldset: CIR - name: CIR - - byte_offset: 16 - description: AHB1 peripheral reset register - fieldset: AHB1RSTR - name: AHB1RSTR - - byte_offset: 20 - description: AHB2 peripheral reset register - fieldset: AHB2RSTR - name: AHB2RSTR - - byte_offset: 32 - description: APB1 peripheral reset register - fieldset: APB1RSTR - name: APB1RSTR - - byte_offset: 36 - description: APB2 peripheral reset register - fieldset: APB2RSTR - name: APB2RSTR - - byte_offset: 48 - description: AHB1 peripheral clock register - fieldset: AHB1ENR - name: AHB1ENR - - byte_offset: 52 - description: AHB2 peripheral clock enable register - fieldset: AHB2ENR - name: AHB2ENR - - byte_offset: 64 - description: APB1 peripheral clock enable register - fieldset: APB1ENR - name: APB1ENR - - byte_offset: 68 - description: APB2 peripheral clock enable register - fieldset: APB2ENR - name: APB2ENR - - byte_offset: 80 - description: AHB1 peripheral clock enable in low power mode register - fieldset: AHB1LPENR - name: AHB1LPENR - - byte_offset: 84 - description: AHB2 peripheral clock enable in low power mode register - fieldset: AHB2LPENR - name: AHB2LPENR - - byte_offset: 96 - description: APB1 peripheral clock enable in low power mode register - fieldset: APB1LPENR - name: APB1LPENR - - byte_offset: 100 - description: APB2 peripheral clock enabled in low power mode register - fieldset: APB2LPENR - name: APB2LPENR - - byte_offset: 112 - description: Backup domain control register - fieldset: BDCR - name: BDCR - - byte_offset: 116 - description: clock control & status register - fieldset: CSR - name: CSR - - byte_offset: 128 - description: spread spectrum clock generation register - fieldset: SSCGR - name: SSCGR - - byte_offset: 132 - description: PLLI2S configuration register - fieldset: PLLI2SCFGR - name: PLLI2SCFGR - - byte_offset: 140 - description: RCC Dedicated Clock Configuration Register - fieldset: DCKCFGR - name: DCKCFGR - - byte_offset: 24 - description: AHB3 peripheral reset register - fieldset: AHB3RSTR - name: AHB3RSTR - - byte_offset: 56 - description: AHB3 peripheral clock enable register - fieldset: AHB3ENR - name: AHB3ENR - - byte_offset: 88 - description: AHB3 peripheral clock enable in low power mode register - fieldset: AHB3LPENR - name: AHB3LPENR - - byte_offset: 148 - description: DCKCFGR2 register - fieldset: DCKCFGR2 - name: DCKCFGR2 - - byte_offset: 144 - description: Clocks gated enable register - fieldset: CKGATENR - name: CKGATENR - - byte_offset: 136 - description: RCC PLL configuration register - fieldset: PLLSAICFGR - name: PLLSAICFGR -enum/CECSEL: - bit_size: 1 - variants: - - description: LSE clock is selected as HDMI-CEC clock - name: LSE - value: 0 - - description: HSI divided by 488 clock is selected as HDMI-CEC clock - name: HSI_Div488 - value: 1 -enum/CKDFSDMASEL: - bit_size: 1 - variants: - - description: CK_I2S_APB1 selected as audio clock - name: I2S1 - value: 0 - - description: CK_I2S_APB2 selected as audio clock - name: I2S2 - value: 1 -enum/CKDFSDMSEL: - bit_size: 1 - variants: - - description: APB2 clock used as Kernel clock - name: APB2 - value: 0 - - description: System clock used as Kernel clock - name: SYSCLK - value: 1 -enum/CKMSEL: - bit_size: 1 - variants: - - description: 48MHz clock from PLL is selected - name: PLL - value: 0 - - description: 48MHz clock from PLLSAI is selected - name: PLLSAI - value: 1 -enum/CSSCW: - bit_size: 1 - variants: - - description: Clear CSSF flag - name: Clear - value: 1 -enum/CSSFR: - bit_size: 1 - variants: - - description: No clock security interrupt caused by HSE clock failure - name: NotInterrupted - value: 0 - - description: Clock security interrupt caused by HSE clock failure - name: Interrupted - value: 1 -enum/DSISEL: - bit_size: 1 - variants: - - description: DSI-PHY used as DSI byte lane clock source (usual case) - name: DSI_PHY - value: 0 - - description: PLLR used as DSI byte lane clock source, used in case DSI PLL and - DSI-PHY are off (low power mode) - name: PLLR - value: 1 -enum/FMPICSEL: - bit_size: 2 - variants: - - description: APB clock selected as I2C clock - name: APB - value: 0 - - description: System clock selected as I2C clock - name: SYSCLK - value: 1 - - description: HSI clock selected as I2C clock - name: HSI - value: 2 -enum/HPRE: - bit_size: 4 - variants: - - description: SYSCLK not divided - name: Div1 - value: 0 - - description: SYSCLK divided by 2 - name: Div2 - value: 8 - - description: SYSCLK divided by 4 - name: Div4 - value: 9 - - description: SYSCLK divided by 8 - name: Div8 - value: 10 - - description: SYSCLK divided by 16 - name: Div16 - value: 11 - - description: SYSCLK divided by 64 - name: Div64 - value: 12 - - description: SYSCLK divided by 128 - name: Div128 - value: 13 - - description: SYSCLK divided by 256 - name: Div256 - value: 14 - - description: SYSCLK divided by 512 - name: Div512 - value: 15 -enum/HSEBYP: - bit_size: 1 - variants: - - description: HSE crystal oscillator not bypassed - name: NotBypassed - value: 0 - - description: HSE crystal oscillator bypassed with external clock - name: Bypassed - value: 1 -enum/HSIRDYR: - bit_size: 1 - variants: - - description: Clock not ready - name: NotReady - value: 0 - - description: Clock ready - name: Ready - value: 1 -enum/I2S1SRC: - bit_size: 2 - variants: - - description: I2Sx clock frequency = f(PLLI2S_R) - name: PLLI2SR - value: 0 - - description: I2Sx clock frequency = I2S_CKIN Alternate function input frequency - name: I2S_CKIN - value: 1 - - description: I2Sx clock frequency = f(PLL_R) - name: PLLR - value: 2 - - description: I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22]) - name: HSI_HSE - value: 3 -enum/I2SSRC: - bit_size: 1 - variants: - - description: PLLI2S clock used as I2S clock source - name: PLLI2S - value: 0 - - description: External clock mapped on the I2S_CKIN pin used as I2S clock source - name: CKIN - value: 1 -enum/ISSRC: - bit_size: 1 - variants: - - description: PLLI2S clock used as I2S clock source - name: PLLI2S - value: 0 - - description: External clock mapped on the I2S_CKIN pin used as I2S clock source - name: CKIN - value: 1 -enum/LPTIMSEL: - bit_size: 2 - variants: - - description: APB1 clock (PCLK1) selected as LPTILM1 clock - name: APB1 - value: 0 - - description: LSI clock is selected as LPTILM1 clock - name: LSI - value: 1 - - description: HSI clock is selected as LPTILM1 clock - name: HSI - value: 2 - - description: LSE clock is selected as LPTILM1 clock - name: LSE - value: 3 -enum/LPWRRSTFR: - bit_size: 1 - variants: - - description: No reset has occured - name: NoReset - value: 0 - - description: A reset has occured - name: Reset - value: 1 -enum/LSEBYP: - bit_size: 1 - variants: - - description: LSE crystal oscillator not bypassed - name: NotBypassed - value: 0 - - description: LSE crystal oscillator bypassed with external clock - name: Bypassed - value: 1 -enum/LSEMOD: - bit_size: 1 - variants: - - description: LSE oscillator low power mode selection - name: Low - value: 0 - - description: LSE oscillator high drive mode selection - name: High - value: 1 -enum/LSERDYR: - bit_size: 1 - variants: - - description: LSE oscillator not ready - name: NotReady - value: 0 - - description: LSE oscillator ready - name: Ready - value: 1 -enum/LSIRDYR: - bit_size: 1 - variants: - - description: LSI oscillator not ready - name: NotReady - value: 0 - - description: LSI oscillator ready - name: Ready - value: 1 -enum/MCO1: - bit_size: 2 - variants: - - description: HSI clock selected - name: HSI - value: 0 - - description: LSE oscillator selected - name: LSE - value: 1 - - description: HSE oscillator clock selected - name: HSE - value: 2 - - description: PLL clock selected - name: PLL - value: 3 -enum/MCO2: - bit_size: 2 - variants: - - description: System clock (SYSCLK) selected - name: SYSCLK - value: 0 - - description: PLLI2S clock selected - name: PLLI2S - value: 1 - - description: HSE oscillator clock selected - name: HSE - value: 2 - - description: PLL clock selected - name: PLL - value: 3 -enum/MCOPRE: - bit_size: 3 - variants: - - description: No division - name: Div1 - value: 0 - - description: Division by 2 - name: Div2 - value: 4 - - description: Division by 3 - name: Div3 - value: 5 - - description: Division by 4 - name: Div4 - value: 6 - - description: Division by 5 - name: Div5 - value: 7 -enum/PLLDIVR: - bit_size: 5 - variants: - - description: PLLSAIDIVQ = /1 - name: Div1 - value: 0 - - description: PLLSAIDIVQ = /2 - name: Div2 - value: 1 - - description: PLLSAIDIVQ = /3 - name: Div3 - value: 2 - - description: PLLSAIDIVQ = /4 - name: Div4 - value: 3 - - description: PLLSAIDIVQ = /5 - name: Div5 - value: 4 - - description: PLLSAIDIVQ = /6 - name: Div6 - value: 5 - - description: PLLSAIDIVQ = /7 - name: Div7 - value: 6 - - description: PLLSAIDIVQ = /8 - name: Div8 - value: 7 - - description: PLLSAIDIVQ = /9 - name: Div9 - value: 8 - - description: PLLSAIDIVQ = /10 - name: Div10 - value: 9 - - description: PLLSAIDIVQ = /11 - name: Div11 - value: 10 - - description: PLLSAIDIVQ = /12 - name: Div12 - value: 11 - - description: PLLSAIDIVQ = /13 - name: Div13 - value: 12 - - description: PLLSAIDIVQ = /14 - name: Div14 - value: 13 - - description: PLLSAIDIVQ = /15 - name: Div15 - value: 14 - - description: PLLSAIDIVQ = /16 - name: Div16 - value: 15 - - description: PLLSAIDIVQ = /17 - name: Div17 - value: 16 - - description: PLLSAIDIVQ = /18 - name: Div18 - value: 17 - - description: PLLSAIDIVQ = /19 - name: Div19 - value: 18 - - description: PLLSAIDIVQ = /20 - name: Div20 - value: 19 - - description: PLLSAIDIVQ = /21 - name: Div21 - value: 20 - - description: PLLSAIDIVQ = /22 - name: Div22 - value: 21 - - description: PLLSAIDIVQ = /23 - name: Div23 - value: 22 - - description: PLLSAIDIVQ = /24 - name: Div24 - value: 23 - - description: PLLSAIDIVQ = /25 - name: Div25 - value: 24 - - description: PLLSAIDIVQ = /26 - name: Div26 - value: 25 - - description: PLLSAIDIVQ = /27 - name: Div27 - value: 26 - - description: PLLSAIDIVQ = /28 - name: Div28 - value: 27 - - description: PLLSAIDIVQ = /29 - name: Div29 - value: 28 - - description: PLLSAIDIVQ = /30 - name: Div30 - value: 29 - - description: PLLSAIDIVQ = /31 - name: Div31 - value: 30 - - description: PLLSAIDIVQ = /32 - name: Div32 - value: 31 -enum/PLLISDIVQ: - bit_size: 5 - variants: - - description: PLLI2SDIVQ = /1 - name: Div1 - value: 0 - - description: PLLI2SDIVQ = /2 - name: Div2 - value: 1 - - description: PLLI2SDIVQ = /3 - name: Div3 - value: 2 - - description: PLLI2SDIVQ = /4 - name: Div4 - value: 3 - - description: PLLI2SDIVQ = /5 - name: Div5 - value: 4 - - description: PLLI2SDIVQ = /6 - name: Div6 - value: 5 - - description: PLLI2SDIVQ = /7 - name: Div7 - value: 6 - - description: PLLI2SDIVQ = /8 - name: Div8 - value: 7 - - description: PLLI2SDIVQ = /9 - name: Div9 - value: 8 - - description: PLLI2SDIVQ = /10 - name: Div10 - value: 9 - - description: PLLI2SDIVQ = /11 - name: Div11 - value: 10 - - description: PLLI2SDIVQ = /12 - name: Div12 - value: 11 - - description: PLLI2SDIVQ = /13 - name: Div13 - value: 12 - - description: PLLI2SDIVQ = /14 - name: Div14 - value: 13 - - description: PLLI2SDIVQ = /15 - name: Div15 - value: 14 - - description: PLLI2SDIVQ = /16 - name: Div16 - value: 15 - - description: PLLI2SDIVQ = /17 - name: Div17 - value: 16 - - description: PLLI2SDIVQ = /18 - name: Div18 - value: 17 - - description: PLLI2SDIVQ = /19 - name: Div19 - value: 18 - - description: PLLI2SDIVQ = /20 - name: Div20 - value: 19 - - description: PLLI2SDIVQ = /21 - name: Div21 - value: 20 - - description: PLLI2SDIVQ = /22 - name: Div22 - value: 21 - - description: PLLI2SDIVQ = /23 - name: Div23 - value: 22 - - description: PLLI2SDIVQ = /24 - name: Div24 - value: 23 - - description: PLLI2SDIVQ = /25 - name: Div25 - value: 24 - - description: PLLI2SDIVQ = /26 - name: Div26 - value: 25 - - description: PLLI2SDIVQ = /27 - name: Div27 - value: 26 - - description: PLLI2SDIVQ = /28 - name: Div28 - value: 27 - - description: PLLI2SDIVQ = /29 - name: Div29 - value: 28 - - description: PLLI2SDIVQ = /30 - name: Div30 - value: 29 - - description: PLLI2SDIVQ = /31 - name: Div31 - value: 30 - - description: PLLI2SDIVQ = /32 - name: Div32 - value: 31 -enum/PLLISDIVR: - bit_size: 5 - variants: - - description: PLLI2SDIVQ = /1 - name: Div1 - value: 0 - - description: PLLI2SDIVQ = /2 - name: Div2 - value: 1 - - description: PLLI2SDIVQ = /3 - name: Div3 - value: 2 - - description: PLLI2SDIVQ = /4 - name: Div4 - value: 3 - - description: PLLI2SDIVQ = /5 - name: Div5 - value: 4 - - description: PLLI2SDIVQ = /6 - name: Div6 - value: 5 - - description: PLLI2SDIVQ = /7 - name: Div7 - value: 6 - - description: PLLI2SDIVQ = /8 - name: Div8 - value: 7 - - description: PLLI2SDIVQ = /9 - name: Div9 - value: 8 - - description: PLLI2SDIVQ = /10 - name: Div10 - value: 9 - - description: PLLI2SDIVQ = /11 - name: Div11 - value: 10 - - description: PLLI2SDIVQ = /12 - name: Div12 - value: 11 - - description: PLLI2SDIVQ = /13 - name: Div13 - value: 12 - - description: PLLI2SDIVQ = /14 - name: Div14 - value: 13 - - description: PLLI2SDIVQ = /15 - name: Div15 - value: 14 - - description: PLLI2SDIVQ = /16 - name: Div16 - value: 15 - - description: PLLI2SDIVQ = /17 - name: Div17 - value: 16 - - description: PLLI2SDIVQ = /18 - name: Div18 - value: 17 - - description: PLLI2SDIVQ = /19 - name: Div19 - value: 18 - - description: PLLI2SDIVQ = /20 - name: Div20 - value: 19 - - description: PLLI2SDIVQ = /21 - name: Div21 - value: 20 - - description: PLLI2SDIVQ = /22 - name: Div22 - value: 21 - - description: PLLI2SDIVQ = /23 - name: Div23 - value: 22 - - description: PLLI2SDIVQ = /24 - name: Div24 - value: 23 - - description: PLLI2SDIVQ = /25 - name: Div25 - value: 24 - - description: PLLI2SDIVQ = /26 - name: Div26 - value: 25 - - description: PLLI2SDIVQ = /27 - name: Div27 - value: 26 - - description: PLLI2SDIVQ = /28 - name: Div28 - value: 27 - - description: PLLI2SDIVQ = /29 - name: Div29 - value: 28 - - description: PLLI2SDIVQ = /30 - name: Div30 - value: 29 - - description: PLLI2SDIVQ = /31 - name: Div31 - value: 30 - - description: PLLI2SDIVQ = /32 - name: Div32 - value: 31 -enum/PLLISP: - bit_size: 2 - variants: - - description: PLL*P=2 - name: Div2 - value: 0 - - description: PLL*P=4 - name: Div4 - value: 1 - - description: PLL*P=6 - name: Div6 - value: 2 - - description: PLL*P=8 - name: Div8 - value: 3 -enum/PLLISRDYCW: - bit_size: 1 - variants: - - description: Clear interrupt flag - name: Clear - value: 1 -enum/PLLISRDYFR: - bit_size: 1 - variants: - - description: No clock ready interrupt - name: NotInterrupted - value: 0 - - description: Clock ready interrupt - name: Interrupted - value: 1 -enum/PLLISRDYIE: - bit_size: 1 - variants: - - description: Interrupt disabled - name: Disabled - value: 0 - - description: Interrupt enabled - name: Enabled - value: 1 -enum/PLLISRDYR: - bit_size: 1 - variants: - - description: Clock not ready - name: NotReady - value: 0 - - description: Clock ready - name: Ready - value: 1 -enum/PLLISSRC: - bit_size: 1 - variants: - - description: HSE or HSI depending on PLLSRC of PLLCFGR - name: HSE_HSI - value: 0 - - description: External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry - name: External - value: 1 -enum/PLLP: - bit_size: 2 - variants: - - description: PLLP=2 - name: Div2 - value: 0 - - description: PLLP=4 - name: Div4 - value: 1 - - description: PLLP=6 - name: Div6 - value: 2 - - description: PLLP=8 - name: Div8 - value: 3 -enum/PLLSAIDIVQ: - bit_size: 5 - variants: - - description: PLLSAIDIVQ = /1 - name: Div1 - value: 0 - - description: PLLSAIDIVQ = /2 - name: Div2 - value: 1 - - description: PLLSAIDIVQ = /3 - name: Div3 - value: 2 - - description: PLLSAIDIVQ = /4 - name: Div4 - value: 3 - - description: PLLSAIDIVQ = /5 - name: Div5 - value: 4 - - description: PLLSAIDIVQ = /6 - name: Div6 - value: 5 - - description: PLLSAIDIVQ = /7 - name: Div7 - value: 6 - - description: PLLSAIDIVQ = /8 - name: Div8 - value: 7 - - description: PLLSAIDIVQ = /9 - name: Div9 - value: 8 - - description: PLLSAIDIVQ = /10 - name: Div10 - value: 9 - - description: PLLSAIDIVQ = /11 - name: Div11 - value: 10 - - description: PLLSAIDIVQ = /12 - name: Div12 - value: 11 - - description: PLLSAIDIVQ = /13 - name: Div13 - value: 12 - - description: PLLSAIDIVQ = /14 - name: Div14 - value: 13 - - description: PLLSAIDIVQ = /15 - name: Div15 - value: 14 - - description: PLLSAIDIVQ = /16 - name: Div16 - value: 15 - - description: PLLSAIDIVQ = /17 - name: Div17 - value: 16 - - description: PLLSAIDIVQ = /18 - name: Div18 - value: 17 - - description: PLLSAIDIVQ = /19 - name: Div19 - value: 18 - - description: PLLSAIDIVQ = /20 - name: Div20 - value: 19 - - description: PLLSAIDIVQ = /21 - name: Div21 - value: 20 - - description: PLLSAIDIVQ = /22 - name: Div22 - value: 21 - - description: PLLSAIDIVQ = /23 - name: Div23 - value: 22 - - description: PLLSAIDIVQ = /24 - name: Div24 - value: 23 - - description: PLLSAIDIVQ = /25 - name: Div25 - value: 24 - - description: PLLSAIDIVQ = /26 - name: Div26 - value: 25 - - description: PLLSAIDIVQ = /27 - name: Div27 - value: 26 - - description: PLLSAIDIVQ = /28 - name: Div28 - value: 27 - - description: PLLSAIDIVQ = /29 - name: Div29 - value: 28 - - description: PLLSAIDIVQ = /30 - name: Div30 - value: 29 - - description: PLLSAIDIVQ = /31 - name: Div31 - value: 30 - - description: PLLSAIDIVQ = /32 - name: Div32 - value: 31 -enum/PLLSAIDIVR: - bit_size: 2 - variants: - - description: PLLSAIDIVR = /2 - name: Div2 - value: 0 - - description: PLLSAIDIVR = /4 - name: Div4 - value: 1 - - description: PLLSAIDIVR = /8 - name: Div8 - value: 2 - - description: PLLSAIDIVR = /16 - name: Div16 - value: 3 -enum/PLLSAIP: - bit_size: 2 - variants: - - description: PLL*P=2 - name: Div2 - value: 0 - - description: PLL*P=4 - name: Div4 - value: 1 - - description: PLL*P=6 - name: Div6 - value: 2 - - description: PLL*P=8 - name: Div8 - value: 3 -enum/PLLSAIRDYCW: - bit_size: 1 - variants: - - description: Clear interrupt flag - name: Clear - value: 1 -enum/PLLSAIRDYFR: - bit_size: 1 - variants: - - description: No clock ready interrupt - name: NotInterrupted - value: 0 - - description: Clock ready interrupt - name: Interrupted - value: 1 -enum/PLLSAIRDYIE: - bit_size: 1 - variants: - - description: Interrupt disabled - name: Disabled - value: 0 - - description: Interrupt enabled - name: Enabled - value: 1 -enum/PLLSRC: - bit_size: 1 - variants: - - description: HSI clock selected as PLL and PLLI2S clock entry - name: HSI - value: 0 - - description: HSE oscillator clock selected as PLL and PLLI2S clock entry - name: HSE - value: 1 -enum/PPRE: - bit_size: 3 - variants: - - description: HCLK not divided - name: Div1 - value: 0 - - description: HCLK divided by 2 - name: Div2 - value: 4 - - description: HCLK divided by 4 - name: Div4 - value: 5 - - description: HCLK divided by 8 - name: Div8 - value: 6 - - description: HCLK divided by 16 - name: Div16 - value: 7 -enum/RMVFW: - bit_size: 1 - variants: - - description: Clears the reset flag - name: Clear - value: 1 -enum/RTCSEL: - bit_size: 2 - variants: - - description: No clock - name: NoClock - value: 0 - - description: LSE oscillator clock used as RTC clock - name: LSE - value: 1 - - description: LSI oscillator clock used as RTC clock - name: LSI - value: 2 - - description: HSE oscillator clock divided by a prescaler used as RTC clock - name: HSE - value: 3 -enum/SAI1SRC: - bit_size: 2 - variants: - - description: SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - name: PLLSAI - value: 0 - - description: SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - name: PLLI2S - value: 1 - - description: SAI1 clock frequency = f(PLL_R) - name: PLLR - value: 2 - - description: I2S_CKIN Alternate function input frequency - name: I2S_CKIN - value: 3 -enum/SAI2SRC: - bit_size: 2 - variants: - - description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - name: PLLSAI - value: 0 - - description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - name: PLLI2S - value: 1 - - description: SAI2 clock frequency = f(PLL_R) - name: PLLR - value: 2 - - description: SAI2 clock frequency = Alternate function input frequency - name: HSI_HSE - value: 3 -enum/SAIASRC: - bit_size: 2 - variants: - - description: SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - name: PLLSAI - value: 0 - - description: SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - name: PLLI2S - value: 1 - - description: SAI1-A clock frequency = Alternate function input frequency - name: I2S_CKIN - value: 2 -enum/SAIBSRC: - bit_size: 2 - variants: - - description: SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - name: PLLSAI - value: 0 - - description: SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - name: PLLI2S - value: 1 - - description: SAI1-B clock frequency = Alternate function input frequency - name: I2S_CKIN - value: 2 -enum/SDIOSEL: - bit_size: 1 - variants: - - description: 48 MHz clock is selected as SD clock - name: CK48M - value: 0 - - description: System clock is selected as SD clock - name: SYSCLK - value: 1 -enum/SPDIFRXSEL: - bit_size: 1 - variants: - - description: SPDIF-Rx clock from PLL is selected - name: PLL - value: 0 - - description: SPDIF-Rx clock from PLLI2S is selected - name: PLLI2S - value: 1 -enum/SPREADSEL: - bit_size: 1 - variants: - - description: Center spread - name: Center - value: 0 - - description: Down spread - name: Down - value: 1 -enum/SW: - bit_size: 2 - variants: - - description: HSI selected as system clock - name: HSI - value: 0 - - description: HSE selected as system clock - name: HSE - value: 1 - - description: PLL selected as system clock - name: PLL - value: 2 -enum/SWSR: - bit_size: 2 - variants: - - description: HSI oscillator used as system clock - name: HSI - value: 0 - - description: HSE oscillator used as system clock - name: HSE - value: 1 - - description: PLL used as system clock - name: PLL - value: 2 -enum/TIMPRE: - bit_size: 1 - variants: - - description: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, - TIMxCLK = 2xPCLKx - name: Mul2 - value: 0 - - description: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, - TIMxCLK = 4xPCLKx - name: Mul4 - value: 1 + - name: CR + description: clock control register + byte_offset: 0 + fieldset: CR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 4 + fieldset: PLLCFGR + - name: CFGR + description: clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: CIR + description: clock interrupt register + byte_offset: 12 + fieldset: CIR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 16 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 20 + fieldset: AHB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register + byte_offset: 32 + fieldset: APB1RSTR + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 36 + fieldset: APB2RSTR + - name: AHB1ENR + description: AHB1 peripheral clock register + byte_offset: 48 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 52 + fieldset: AHB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register + byte_offset: 64 + fieldset: APB1ENR + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 68 + fieldset: APB2ENR + - name: AHB1LPENR + description: AHB1 peripheral clock enable in low power mode register + byte_offset: 80 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: AHB2 peripheral clock enable in low power mode register + byte_offset: 84 + fieldset: AHB2LPENR + - name: APB1LPENR + description: APB1 peripheral clock enable in low power mode register + byte_offset: 96 + fieldset: APB1LPENR + - name: APB2LPENR + description: APB2 peripheral clock enabled in low power mode register + byte_offset: 100 + fieldset: APB2LPENR + - name: BDCR + description: Backup domain control register + byte_offset: 112 + fieldset: BDCR + - name: CSR + description: clock control & status register + byte_offset: 116 + fieldset: CSR + - name: SSCGR + description: spread spectrum clock generation register + byte_offset: 128 + fieldset: SSCGR + - name: PLLI2SCFGR + description: PLLI2S configuration register + byte_offset: 132 + fieldset: PLLI2SCFGR + - name: DCKCFGR + description: RCC Dedicated Clock Configuration Register + byte_offset: 140 + fieldset: DCKCFGR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 24 + fieldset: AHB3RSTR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 56 + fieldset: AHB3ENR + - name: AHB3LPENR + description: AHB3 peripheral clock enable in low power mode register + byte_offset: 88 + fieldset: AHB3LPENR + - name: DCKCFGR2 + description: DCKCFGR2 register + byte_offset: 148 + fieldset: DCKCFGR2 + - name: CKGATENR + description: Clocks gated enable register + byte_offset: 144 + fieldset: CKGATENR + - name: PLLSAICFGR + description: RCC PLL configuration register + byte_offset: 136 + fieldset: PLLSAICFGR fieldset/AHB1ENR: description: AHB1 peripheral clock register fields: - - bit_offset: 0 - bit_size: 1 - description: IO port A clock enable - name: GPIOAEN - - bit_offset: 1 - bit_size: 1 - description: IO port B clock enable - name: GPIOBEN - - bit_offset: 2 - bit_size: 1 - description: IO port C clock enable - name: GPIOCEN - - bit_offset: 3 - bit_size: 1 - description: IO port D clock enable - name: GPIODEN - - bit_offset: 4 - bit_size: 1 - description: IO port E clock enable - name: GPIOEEN - - bit_offset: 7 - bit_size: 1 - description: IO port H clock enable - name: GPIOHEN - - bit_offset: 12 - bit_size: 1 - description: CRC clock enable - name: CRCEN - - bit_offset: 21 - bit_size: 1 - description: DMA1 clock enable - name: DMA1EN - - bit_offset: 22 - bit_size: 1 - description: DMA2 clock enable - name: DMA2EN - - bit_offset: 5 - bit_size: 1 - description: IO port F clock enable - name: GPIOFEN - - bit_offset: 6 - bit_size: 1 - description: IO port G clock enable - name: GPIOGEN - - bit_offset: 8 - bit_size: 1 - description: IO port I clock enable - name: GPIOIEN - - bit_offset: 18 - bit_size: 1 - description: Backup SRAM interface clock enable - name: BKPSRAMEN - - bit_offset: 25 - bit_size: 1 - description: Ethernet MAC clock enable - name: ETHMACEN - - bit_offset: 26 - bit_size: 1 - description: Ethernet Transmission clock enable - name: ETHMACTXEN - - bit_offset: 27 - bit_size: 1 - description: Ethernet Reception clock enable - name: ETHMACRXEN - - bit_offset: 28 - bit_size: 1 - description: Ethernet PTP clock enable - name: ETHMACPTPEN - - bit_offset: 29 - bit_size: 1 - description: USB OTG HS clock enable - name: OTGHSEN - - bit_offset: 30 - bit_size: 1 - description: USB OTG HSULPI clock enable - name: OTGHSULPIEN - - bit_offset: 9 - bit_size: 1 - description: IO port J clock enable - name: GPIOJEN - - bit_offset: 10 - bit_size: 1 - description: IO port K clock enable - name: GPIOKEN - - bit_offset: 23 - bit_size: 1 - description: DMA2D clock enable - name: DMA2DEN - - bit_offset: 20 - bit_size: 1 - description: CCM data RAM clock enable - name: CCMDATARAMEN + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 7 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 21 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 22 + bit_size: 1 + - name: GPIOFEN + description: IO port F clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOIEN + description: IO port I clock enable + bit_offset: 8 + bit_size: 1 + - name: BKPSRAMEN + description: Backup SRAM interface clock enable + bit_offset: 18 + bit_size: 1 + - name: ETHMACEN + description: Ethernet MAC clock enable + bit_offset: 25 + bit_size: 1 + - name: ETHMACTXEN + description: Ethernet Transmission clock enable + bit_offset: 26 + bit_size: 1 + - name: ETHMACRXEN + description: Ethernet Reception clock enable + bit_offset: 27 + bit_size: 1 + - name: ETHMACPTPEN + description: Ethernet PTP clock enable + bit_offset: 28 + bit_size: 1 + - name: OTGHSEN + description: USB OTG HS clock enable + bit_offset: 29 + bit_size: 1 + - name: OTGHSULPIEN + description: USB OTG HSULPI clock enable + bit_offset: 30 + bit_size: 1 + - name: GPIOJEN + description: IO port J clock enable + bit_offset: 9 + bit_size: 1 + - name: GPIOKEN + description: IO port K clock enable + bit_offset: 10 + bit_size: 1 + - name: DMA2DEN + description: DMA2D clock enable + bit_offset: 23 + bit_size: 1 + - name: CCMDATARAMEN + description: CCM data RAM clock enable + bit_offset: 20 + bit_size: 1 fieldset/AHB1LPENR: description: AHB1 peripheral clock enable in low power mode register fields: - - bit_offset: 0 - bit_size: 1 - description: IO port A clock enable during sleep mode - name: GPIOALPEN - - bit_offset: 1 - bit_size: 1 - description: IO port B clock enable during Sleep mode - name: GPIOBLPEN - - bit_offset: 2 - bit_size: 1 - description: IO port C clock enable during Sleep mode - name: GPIOCLPEN - - bit_offset: 3 - bit_size: 1 - description: IO port D clock enable during Sleep mode - name: GPIODLPEN - - bit_offset: 4 - bit_size: 1 - description: IO port E clock enable during Sleep mode - name: GPIOELPEN - - bit_offset: 7 - bit_size: 1 - description: IO port H clock enable during Sleep mode - name: GPIOHLPEN - - bit_offset: 12 - bit_size: 1 - description: CRC clock enable during Sleep mode - name: CRCLPEN - - bit_offset: 15 - bit_size: 1 - description: Flash interface clock enable during Sleep mode - name: FLITFLPEN - - bit_offset: 16 - bit_size: 1 - description: SRAM 1interface clock enable during Sleep mode - name: SRAM1LPEN - - bit_offset: 21 - bit_size: 1 - description: DMA1 clock enable during Sleep mode - name: DMA1LPEN - - bit_offset: 22 - bit_size: 1 - description: DMA2 clock enable during Sleep mode - name: DMA2LPEN - - bit_offset: 5 - bit_size: 1 - description: IO port F clock enable during Sleep mode - name: GPIOFLPEN - - bit_offset: 6 - bit_size: 1 - description: IO port G clock enable during Sleep mode - name: GPIOGLPEN - - bit_offset: 8 - bit_size: 1 - description: IO port I clock enable during Sleep mode - name: GPIOILPEN - - bit_offset: 17 - bit_size: 1 - description: SRAM 2 interface clock enable during Sleep mode - name: SRAM2LPEN - - bit_offset: 18 - bit_size: 1 - description: Backup SRAM interface clock enable during Sleep mode - name: BKPSRAMLPEN - - bit_offset: 25 - bit_size: 1 - description: Ethernet MAC clock enable during Sleep mode - name: ETHMACLPEN - - bit_offset: 26 - bit_size: 1 - description: Ethernet transmission clock enable during Sleep mode - name: ETHMACTXLPEN - - bit_offset: 27 - bit_size: 1 - description: Ethernet reception clock enable during Sleep mode - name: ETHMACRXLPEN - - bit_offset: 28 - bit_size: 1 - description: Ethernet PTP clock enable during Sleep mode - name: ETHMACPTPLPEN - - bit_offset: 29 - bit_size: 1 - description: USB OTG HS clock enable during Sleep mode - name: OTGHSLPEN - - bit_offset: 30 - bit_size: 1 - description: USB OTG HS ULPI clock enable during Sleep mode - name: OTGHSULPILPEN - - bit_offset: 31 - bit_size: 1 - description: RNG clock enable during sleep mode - name: RNGLPEN - - bit_offset: 9 - bit_size: 1 - description: IO port J clock enable during Sleep mode - name: GPIOJLPEN - - bit_offset: 10 - bit_size: 1 - description: IO port K clock enable during Sleep mode - name: GPIOKLPEN - - bit_offset: 19 - bit_size: 1 - description: SRAM 3 interface clock enable during Sleep mode - name: SRAM3LPEN - - bit_offset: 23 - bit_size: 1 - description: DMA2D clock enable during Sleep mode - name: DMA2DLPEN + - name: GPIOALPEN + description: IO port A clock enable during sleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: IO port B clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: IO port C clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: IO port D clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: IO port E clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: GPIOHLPEN + description: IO port H clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: CRCLPEN + description: CRC clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: FLITFLPEN + description: Flash interface clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: SRAM1LPEN + description: SRAM 1interface clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: DMA1LPEN + description: DMA1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: GPIOFLPEN + description: IO port F clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: IO port G clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: GPIOILPEN + description: IO port I clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: SRAM2LPEN + description: SRAM 2 interface clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: BKPSRAMLPEN + description: Backup SRAM interface clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: ETHMACLPEN + description: Ethernet MAC clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: ETHMACTXLPEN + description: Ethernet transmission clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: ETHMACRXLPEN + description: Ethernet reception clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: ETHMACPTPLPEN + description: Ethernet PTP clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: OTGHSLPEN + description: USB OTG HS clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: OTGHSULPILPEN + description: USB OTG HS ULPI clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 + - name: RNGLPEN + description: RNG clock enable during sleep mode + bit_offset: 31 + bit_size: 1 + - name: GPIOJLPEN + description: IO port J clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: GPIOKLPEN + description: IO port K clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 + - name: SRAM3LPEN + description: SRAM 3 interface clock enable during Sleep mode + bit_offset: 19 + bit_size: 1 + - name: DMA2DLPEN + description: DMA2D clock enable during Sleep mode + bit_offset: 23 + bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: IO port A reset - name: GPIOARST - - bit_offset: 1 - bit_size: 1 - description: IO port B reset - name: GPIOBRST - - bit_offset: 2 - bit_size: 1 - description: IO port C reset - name: GPIOCRST - - bit_offset: 3 - bit_size: 1 - description: IO port D reset - name: GPIODRST - - bit_offset: 4 - bit_size: 1 - description: IO port E reset - name: GPIOERST - - bit_offset: 7 - bit_size: 1 - description: IO port H reset - name: GPIOHRST - - bit_offset: 12 - bit_size: 1 - description: CRC reset - name: CRCRST - - bit_offset: 21 - bit_size: 1 - description: DMA2 reset - name: DMA1RST - - bit_offset: 22 - bit_size: 1 - description: DMA2 reset - name: DMA2RST - - bit_offset: 5 - bit_size: 1 - description: IO port F reset - name: GPIOFRST - - bit_offset: 6 - bit_size: 1 - description: IO port G reset - name: GPIOGRST - - bit_offset: 8 - bit_size: 1 - description: IO port I reset - name: GPIOIRST - - bit_offset: 25 - bit_size: 1 - description: Ethernet MAC reset - name: ETHMACRST - - bit_offset: 29 - bit_size: 1 - description: USB OTG HS module reset - name: OTGHSRST - - bit_offset: 9 - bit_size: 1 - description: IO port J reset - name: GPIOJRST - - bit_offset: 10 - bit_size: 1 - description: IO port K reset - name: GPIOKRST - - bit_offset: 23 - bit_size: 1 - description: DMA2D reset - name: DMA2DRST + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: DMA1RST + description: DMA2 reset + bit_offset: 21 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 22 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 6 + bit_size: 1 + - name: GPIOIRST + description: IO port I reset + bit_offset: 8 + bit_size: 1 + - name: ETHMACRST + description: Ethernet MAC reset + bit_offset: 25 + bit_size: 1 + - name: OTGHSRST + description: USB OTG HS module reset + bit_offset: 29 + bit_size: 1 + - name: GPIOJRST + description: IO port J reset + bit_offset: 9 + bit_size: 1 + - name: GPIOKRST + description: IO port K reset + bit_offset: 10 + bit_size: 1 + - name: DMA2DRST + description: DMA2D reset + bit_offset: 23 + bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - - bit_offset: 7 - bit_size: 1 - description: USB OTG FS clock enable - name: OTGFSEN - - bit_offset: 0 - bit_size: 1 - description: Camera interface enable - name: DCMIEN - - bit_offset: 6 - bit_size: 1 - description: Random number generator clock enable - name: RNGEN - - bit_offset: 4 - bit_size: 1 - description: CRYP clock enable - name: CRYPEN - - bit_offset: 5 - bit_size: 1 - description: Hash modules clock enable - name: HASHEN + - name: OTGFSEN + description: USB OTG FS clock enable + bit_offset: 7 + bit_size: 1 + - name: DCMIEN + description: Camera interface enable + bit_offset: 0 + bit_size: 1 + - name: RNGEN + description: Random number generator clock enable + bit_offset: 6 + bit_size: 1 + - name: CRYPEN + description: CRYP clock enable + bit_offset: 4 + bit_size: 1 + - name: HASHEN + description: Hash modules clock enable + bit_offset: 5 + bit_size: 1 fieldset/AHB2LPENR: description: AHB2 peripheral clock enable in low power mode register fields: - - bit_offset: 7 - bit_size: 1 - description: USB OTG FS clock enable during Sleep mode - name: OTGFSLPEN - - bit_offset: 0 - bit_size: 1 - description: Camera interface enable during Sleep mode - name: DCMILPEN - - bit_offset: 6 - bit_size: 1 - description: Random number generator clock enable during Sleep mode - name: RNGLPEN - - bit_offset: 0 - bit_size: 1 - description: Flexible memory controller module clock enable during Sleep mode - name: FSMCLPEN - - bit_offset: 1 - bit_size: 1 - description: QUADSPI memory controller module clock enable during Sleep mode - name: QSPILPEN - - bit_offset: 4 - bit_size: 1 - description: Cryptography modules clock enable during Sleep mode - name: CRYPLPEN - - bit_offset: 5 - bit_size: 1 - description: Hash modules clock enable during Sleep mode - name: HASHLPEN + - name: OTGFSLPEN + description: USB OTG FS clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: DCMILPEN + description: Camera interface enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: RNGLPEN + description: Random number generator clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: FSMCLPEN + description: Flexible memory controller module clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: QSPILPEN + description: QUADSPI memory controller module clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: CRYPLPEN + description: Cryptography modules clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: HASHLPEN + description: Hash modules clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - - bit_offset: 7 - bit_size: 1 - description: USB OTG FS module reset - name: OTGFSRST - - bit_offset: 0 - bit_size: 1 - description: Camera interface reset - name: DCMIRST - - bit_offset: 6 - bit_size: 1 - description: Random number generator module reset - name: RNGRST - - bit_offset: 4 - bit_size: 1 - description: CRYP module reset - name: CRYPRST - - bit_offset: 5 - bit_size: 1 - description: Hash module reset - name: HSAHRST + - name: OTGFSRST + description: USB OTG FS module reset + bit_offset: 7 + bit_size: 1 + - name: DCMIRST + description: Camera interface reset + bit_offset: 0 + bit_size: 1 + - name: RNGRST + description: Random number generator module reset + bit_offset: 6 + bit_size: 1 + - name: CRYPRST + description: CRYP module reset + bit_offset: 4 + bit_size: 1 + - name: HSAHRST + description: Hash module reset + bit_offset: 5 + bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: Flexible static memory controller module clock enable - name: FSMCEN - - bit_offset: 1 - bit_size: 1 - description: QUADSPI memory controller module clock enable - name: QSPIEN - - bit_offset: 0 - bit_size: 1 - description: Flexible static memory controller module clock enable - name: FMCEN + - name: FSMCEN + description: Flexible static memory controller module clock enable + bit_offset: 0 + bit_size: 1 + - name: QSPIEN + description: QUADSPI memory controller module clock enable + bit_offset: 1 + bit_size: 1 + - name: FMCEN + description: Flexible static memory controller module clock enable + bit_offset: 0 + bit_size: 1 fieldset/AHB3LPENR: description: AHB3 peripheral clock enable in low power mode register fields: - - bit_offset: 0 - bit_size: 1 - description: Flexible static memory controller module clock enable during Sleep - mode - name: FSMCLPEN - - bit_offset: 1 - bit_size: 1 - description: QUADSPI memory controller module clock enable during Sleep mode - name: QSPILPEN - - bit_offset: 0 - bit_size: 1 - description: Flexible static memory controller module clock enable during Sleep - mode - name: FMCLPEN + - name: FSMCLPEN + description: Flexible static memory controller module clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: QSPILPEN + description: QUADSPI memory controller module clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: FMCLPEN + description: Flexible static memory controller module clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: Flexible static memory controller module reset - name: FSMCRST - - bit_offset: 1 - bit_size: 1 - description: QUADSPI module reset - name: QSPIRST - - bit_offset: 0 - bit_size: 1 - description: Flexible static memory controller module reset - name: FMCRST + - name: FSMCRST + description: Flexible static memory controller module reset + bit_offset: 0 + bit_size: 1 + - name: QSPIRST + description: QUADSPI module reset + bit_offset: 1 + bit_size: 1 + - name: FMCRST + description: Flexible static memory controller module reset + bit_offset: 0 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 clock enable - name: TIM2EN - - bit_offset: 1 - bit_size: 1 - description: TIM3 clock enable - name: TIM3EN - - bit_offset: 2 - bit_size: 1 - description: TIM4 clock enable - name: TIM4EN - - bit_offset: 3 - bit_size: 1 - description: TIM5 clock enable - name: TIM5EN - - bit_offset: 11 - bit_size: 1 - description: Window watchdog clock enable - name: WWDGEN - - bit_offset: 14 - bit_size: 1 - description: SPI2 clock enable - name: SPI2EN - - bit_offset: 15 - bit_size: 1 - description: SPI3 clock enable - name: SPI3EN - - bit_offset: 17 - bit_size: 1 - description: USART 2 clock enable - name: USART2EN - - bit_offset: 21 - bit_size: 1 - description: I2C1 clock enable - name: I2C1EN - - bit_offset: 22 - bit_size: 1 - description: I2C2 clock enable - name: I2C2EN - - bit_offset: 23 - bit_size: 1 - description: I2C3 clock enable - name: I2C3EN - - bit_offset: 28 - bit_size: 1 - description: Power interface clock enable - name: PWREN - - bit_offset: 4 - bit_size: 1 - description: TIM6 clock enable - name: TIM6EN - - bit_offset: 5 - bit_size: 1 - description: TIM7 clock enable - name: TIM7EN - - bit_offset: 6 - bit_size: 1 - description: TIM12 clock enable - name: TIM12EN - - bit_offset: 7 - bit_size: 1 - description: TIM13 clock enable - name: TIM13EN - - bit_offset: 8 - bit_size: 1 - description: TIM14 clock enable - name: TIM14EN - - bit_offset: 18 - bit_size: 1 - description: USART3 clock enable - name: USART3EN - - bit_offset: 19 - bit_size: 1 - description: UART4 clock enable - name: UART4EN - - bit_offset: 20 - bit_size: 1 - description: UART5 clock enable - name: UART5EN - - bit_offset: 25 - bit_size: 1 - description: CAN 1 clock enable - name: CAN1EN - - bit_offset: 26 - bit_size: 1 - description: CAN 2 clock enable - name: CAN2EN - - bit_offset: 29 - bit_size: 1 - description: DAC interface clock enable - name: DACEN - - bit_offset: 9 - bit_size: 1 - description: LPTIM1 clock enable - name: LPTIM1EN - - bit_offset: 10 - bit_size: 1 - description: RTC APB clock enable - name: RTCAPBEN - - bit_offset: 24 - bit_size: 1 - description: FMPI2C1 clock enable - name: FMPI2C1EN - - bit_offset: 27 - bit_size: 1 - description: CAN 3 clock enable - name: CAN3EN - - bit_offset: 30 - bit_size: 1 - description: UART7 clock enable - name: UART7EN - - bit_offset: 31 - bit_size: 1 - description: UART8 clock enable - name: UART8EN - - bit_offset: 16 - bit_size: 1 - description: SPDIF-IN clock enable - name: SPDIFEN - - bit_offset: 27 - bit_size: 1 - description: CEC interface clock enable - name: CECEN + - name: TIM2EN + description: TIM2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM5 clock enable + bit_offset: 3 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 23 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: TIM6EN + description: TIM6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: TIM12 clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: TIM13 clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: TIM14 clock enable + bit_offset: 8 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: CAN1EN + description: CAN 1 clock enable + bit_offset: 25 + bit_size: 1 + - name: CAN2EN + description: CAN 2 clock enable + bit_offset: 26 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: LPTIM1EN + description: LPTIM1 clock enable + bit_offset: 9 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: FMPI2C1EN + description: FMPI2C1 clock enable + bit_offset: 24 + bit_size: 1 + - name: CAN3EN + description: CAN 3 clock enable + bit_offset: 27 + bit_size: 1 + - name: UART7EN + description: UART7 clock enable + bit_offset: 30 + bit_size: 1 + - name: UART8EN + description: UART8 clock enable + bit_offset: 31 + bit_size: 1 + - name: SPDIFEN + description: SPDIF-IN clock enable + bit_offset: 16 + bit_size: 1 + - name: CECEN + description: CEC interface clock enable + bit_offset: 27 + bit_size: 1 fieldset/APB1LPENR: description: APB1 peripheral clock enable in low power mode register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 clock enable during Sleep mode - name: TIM2LPEN - - bit_offset: 1 - bit_size: 1 - description: TIM3 clock enable during Sleep mode - name: TIM3LPEN - - bit_offset: 2 - bit_size: 1 - description: TIM4 clock enable during Sleep mode - name: TIM4LPEN - - bit_offset: 3 - bit_size: 1 - description: TIM5 clock enable during Sleep mode - name: TIM5LPEN - - bit_offset: 11 - bit_size: 1 - description: Window watchdog clock enable during Sleep mode - name: WWDGLPEN - - bit_offset: 14 - bit_size: 1 - description: SPI2 clock enable during Sleep mode - name: SPI2LPEN - - bit_offset: 15 - bit_size: 1 - description: SPI3 clock enable during Sleep mode - name: SPI3LPEN - - bit_offset: 17 - bit_size: 1 - description: USART2 clock enable during Sleep mode - name: USART2LPEN - - bit_offset: 21 - bit_size: 1 - description: I2C1 clock enable during Sleep mode - name: I2C1LPEN - - bit_offset: 22 - bit_size: 1 - description: I2C2 clock enable during Sleep mode - name: I2C2LPEN - - bit_offset: 23 - bit_size: 1 - description: I2C3 clock enable during Sleep mode - name: I2C3LPEN - - bit_offset: 28 - bit_size: 1 - description: Power interface clock enable during Sleep mode - name: PWRLPEN - - bit_offset: 4 - bit_size: 1 - description: TIM6 clock enable during Sleep mode - name: TIM6LPEN - - bit_offset: 5 - bit_size: 1 - description: TIM7 clock enable during Sleep mode - name: TIM7LPEN - - bit_offset: 6 - bit_size: 1 - description: TIM12 clock enable during Sleep mode - name: TIM12LPEN - - bit_offset: 7 - bit_size: 1 - description: TIM13 clock enable during Sleep mode - name: TIM13LPEN - - bit_offset: 8 - bit_size: 1 - description: TIM14 clock enable during Sleep mode - name: TIM14LPEN - - bit_offset: 18 - bit_size: 1 - description: USART3 clock enable during Sleep mode - name: USART3LPEN - - bit_offset: 19 - bit_size: 1 - description: UART4 clock enable during Sleep mode - name: UART4LPEN - - bit_offset: 20 - bit_size: 1 - description: UART5 clock enable during Sleep mode - name: UART5LPEN - - bit_offset: 25 - bit_size: 1 - description: CAN 1 clock enable during Sleep mode - name: CAN1LPEN - - bit_offset: 26 - bit_size: 1 - description: CAN 2 clock enable during Sleep mode - name: CAN2LPEN - - bit_offset: 29 - bit_size: 1 - description: DAC interface clock enable during Sleep mode - name: DACLPEN - - bit_offset: 9 - bit_size: 1 - description: LPTIM1 clock enable during sleep mode - name: LPTIM1LPEN - - bit_offset: 10 - bit_size: 1 - description: RTC APB clock enable during sleep mode - name: RTCAPBLPEN - - bit_offset: 24 - bit_size: 1 - description: FMPI2C1 clock enable during Sleep - name: FMPI2C1LPEN - - bit_offset: 27 - bit_size: 1 - description: CAN3 clock enable during Sleep mode - name: CAN3LPEN - - bit_offset: 30 - bit_size: 1 - description: UART7 clock enable during Sleep mode - name: UART7LPEN - - bit_offset: 31 - bit_size: 1 - description: UART8 clock enable during Sleep mode - name: UART8LPEN - - bit_offset: 16 - bit_size: 1 - description: SPDIF clock enable during Sleep mode - name: SPDIFLPEN - - bit_offset: 27 - bit_size: 1 - description: CEC clock enable during Sleep mode - name: CECLPEN + - name: TIM2LPEN + description: TIM2 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: TIM3 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: TIM4 clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: TIM5 clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: WWDGLPEN + description: Window watchdog clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: SPI3 clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: USART2LPEN + description: USART2 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: I2C1LPEN + description: I2C1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: I2C3LPEN + description: I2C3 clock enable during Sleep mode + bit_offset: 23 + bit_size: 1 + - name: PWRLPEN + description: Power interface clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: TIM6LPEN + description: TIM6 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: TIM7 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: TIM12LPEN + description: TIM12 clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: TIM13LPEN + description: TIM13 clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: TIM14LPEN + description: TIM14 clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: USART3LPEN + description: USART3 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: UART4 clock enable during Sleep mode + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: UART5 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: CAN1LPEN + description: CAN 1 clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: CAN2LPEN + description: CAN 2 clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: DACLPEN + description: DAC interface clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: LPTIM1LPEN + description: LPTIM1 clock enable during sleep mode + bit_offset: 9 + bit_size: 1 + - name: RTCAPBLPEN + description: RTC APB clock enable during sleep mode + bit_offset: 10 + bit_size: 1 + - name: FMPI2C1LPEN + description: FMPI2C1 clock enable during Sleep + bit_offset: 24 + bit_size: 1 + - name: CAN3LPEN + description: CAN3 clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: UART7LPEN + description: UART7 clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 + - name: UART8LPEN + description: UART8 clock enable during Sleep mode + bit_offset: 31 + bit_size: 1 + - name: SPDIFLPEN + description: SPDIF clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: CECLPEN + description: CEC clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 reset - name: TIM2RST - - bit_offset: 1 - bit_size: 1 - description: TIM3 reset - name: TIM3RST - - bit_offset: 2 - bit_size: 1 - description: TIM4 reset - name: TIM4RST - - bit_offset: 3 - bit_size: 1 - description: TIM5 reset - name: TIM5RST - - bit_offset: 11 - bit_size: 1 - description: Window watchdog reset - name: WWDGRST - - bit_offset: 14 - bit_size: 1 - description: SPI 2 reset - name: SPI2RST - - bit_offset: 15 - bit_size: 1 - description: SPI 3 reset - name: SPI3RST - - bit_offset: 17 - bit_size: 1 - description: USART 2 reset - name: USART2RST - - bit_offset: 21 - bit_size: 1 - description: I2C 1 reset - name: I2C1RST - - bit_offset: 22 - bit_size: 1 - description: I2C 2 reset - name: I2C2RST - - bit_offset: 23 - bit_size: 1 - description: I2C3 reset - name: I2C3RST - - bit_offset: 28 - bit_size: 1 - description: Power interface reset - name: PWRRST - - bit_offset: 4 - bit_size: 1 - description: TIM6 reset - name: TIM6RST - - bit_offset: 5 - bit_size: 1 - description: TIM7 reset - name: TIM7RST - - bit_offset: 6 - bit_size: 1 - description: TIM12 reset - name: TIM12RST - - bit_offset: 7 - bit_size: 1 - description: TIM13 reset - name: TIM13RST - - bit_offset: 8 - bit_size: 1 - description: TIM14 reset - name: TIM14RST - - bit_offset: 18 - bit_size: 1 - description: USART 3 reset - name: USART3RST - - bit_offset: 19 - bit_size: 1 - description: UART 4 reset - name: UART4RST - - bit_offset: 20 - bit_size: 1 - description: UART 5 reset - name: UART5RST - - bit_offset: 25 - bit_size: 1 - description: CAN1 reset - name: CAN1RST - - bit_offset: 26 - bit_size: 1 - description: CAN2 reset - name: CAN2RST - - bit_offset: 29 - bit_size: 1 - description: DAC reset - name: DACRST - - bit_offset: 9 - bit_size: 1 - description: LPTIM1 reset - name: LPTIM1RST - - bit_offset: 24 - bit_size: 1 - description: FMPI2C1 reset - name: FMPI2C1RST - - bit_offset: 27 - bit_size: 1 - description: CAN 3 reset - name: CAN3RST - - bit_offset: 30 - bit_size: 1 - description: UART 7 reset - name: UART7RST - - bit_offset: 31 - bit_size: 1 - description: UART 8 reset - name: UART8RST - - bit_offset: 16 - bit_size: 1 - description: SPDIF-IN reset - name: SPDIFRST + - name: TIM2RST + description: TIM2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM4 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM5 reset + bit_offset: 3 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI 2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI 3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: I2C1RST + description: I2C 1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C 2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: TIM6RST + description: TIM6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: TIM12 reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: TIM13 reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: TIM14 reset + bit_offset: 8 + bit_size: 1 + - name: USART3RST + description: USART 3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART 5 reset + bit_offset: 20 + bit_size: 1 + - name: CAN1RST + description: CAN1 reset + bit_offset: 25 + bit_size: 1 + - name: CAN2RST + description: CAN2 reset + bit_offset: 26 + bit_size: 1 + - name: DACRST + description: DAC reset + bit_offset: 29 + bit_size: 1 + - name: LPTIM1RST + description: LPTIM1 reset + bit_offset: 9 + bit_size: 1 + - name: FMPI2C1RST + description: FMPI2C1 reset + bit_offset: 24 + bit_size: 1 + - name: CAN3RST + description: CAN 3 reset + bit_offset: 27 + bit_size: 1 + - name: UART7RST + description: UART 7 reset + bit_offset: 30 + bit_size: 1 + - name: UART8RST + description: UART 8 reset + bit_offset: 31 + bit_size: 1 + - name: SPDIFRST + description: SPDIF-IN reset + bit_offset: 16 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM1 clock enable - name: TIM1EN - - bit_offset: 4 - bit_size: 1 - description: USART1 clock enable - name: USART1EN - - bit_offset: 5 - bit_size: 1 - description: USART6 clock enable - name: USART6EN - - bit_offset: 8 - bit_size: 1 - description: ADC1 clock enable - name: ADC1EN - - bit_offset: 11 - bit_size: 1 - description: SDIO clock enable - name: SDIOEN - - bit_offset: 12 - bit_size: 1 - description: SPI1 clock enable - name: SPI1EN - - bit_offset: 13 - bit_size: 1 - description: SPI4 clock enable - name: SPI4EN - - bit_offset: 14 - bit_size: 1 - description: System configuration controller clock enable - name: SYSCFGEN - - bit_offset: 16 - bit_size: 1 - description: TIM9 clock enable - name: TIM9EN - - bit_offset: 17 - bit_size: 1 - description: TIM10 clock enable - name: TIM10EN - - bit_offset: 18 - bit_size: 1 - description: TIM11 clock enable - name: TIM11EN - - bit_offset: 1 - bit_size: 1 - description: TIM8 clock enable - name: TIM8EN - - bit_offset: 9 - bit_size: 1 - description: ADC2 clock enable - name: ADC2EN - - bit_offset: 10 - bit_size: 1 - description: ADC3 clock enable - name: ADC3EN - - bit_offset: 15 - bit_size: 1 - description: EXTI ans external IT clock enable - name: EXTITEN - - bit_offset: 20 - bit_size: 1 - description: SPI5 clock enable - name: SPI5EN - - bit_offset: 24 - bit_size: 1 - description: DFSDMEN - name: DFSDMEN - - bit_offset: 6 - bit_size: 1 - description: UART9 clock enable - name: UART9EN - - bit_offset: 7 - bit_size: 1 - description: UART10 clock enable - name: UART10EN - - bit_offset: 22 - bit_size: 1 - description: SAI 1 clock enable - name: SAI1EN - - bit_offset: 25 - bit_size: 1 - description: DFSDM2 clock enable - name: DFSDM2EN - - bit_offset: 21 - bit_size: 1 - description: SPI6 clock enable - name: SPI6EN - - bit_offset: 26 - bit_size: 1 - description: LTDC clock enable - name: LTDCEN - - bit_offset: 23 - bit_size: 1 - description: SAI2 clock enable - name: SAI2EN - - bit_offset: 27 - bit_size: 1 - description: DSI clocks enable - name: DSIEN + - name: TIM1EN + description: TIM1 clock enable + bit_offset: 0 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 4 + bit_size: 1 + - name: USART6EN + description: USART6 clock enable + bit_offset: 5 + bit_size: 1 + - name: ADC1EN + description: ADC1 clock enable + bit_offset: 8 + bit_size: 1 + - name: SDIOEN + description: SDIO clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: SPI4EN + description: SPI4 clock enable + bit_offset: 13 + bit_size: 1 + - name: SYSCFGEN + description: System configuration controller clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM9EN + description: TIM9 clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM10EN + description: TIM10 clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM11EN + description: TIM11 clock enable + bit_offset: 18 + bit_size: 1 + - name: TIM8EN + description: TIM8 clock enable + bit_offset: 1 + bit_size: 1 + - name: ADC2EN + description: ADC2 clock enable + bit_offset: 9 + bit_size: 1 + - name: ADC3EN + description: ADC3 clock enable + bit_offset: 10 + bit_size: 1 + - name: EXTITEN + description: EXTI ans external IT clock enable + bit_offset: 15 + bit_size: 1 + - name: SPI5EN + description: SPI5 clock enable + bit_offset: 20 + bit_size: 1 + - name: DFSDMEN + description: DFSDMEN + bit_offset: 24 + bit_size: 1 + - name: UART9EN + description: UART9 clock enable + bit_offset: 6 + bit_size: 1 + - name: UART10EN + description: UART10 clock enable + bit_offset: 7 + bit_size: 1 + - name: SAI1EN + description: SAI 1 clock enable + bit_offset: 22 + bit_size: 1 + - name: DFSDM2EN + description: DFSDM2 clock enable + bit_offset: 25 + bit_size: 1 + - name: SPI6EN + description: SPI6 clock enable + bit_offset: 21 + bit_size: 1 + - name: LTDCEN + description: LTDC clock enable + bit_offset: 26 + bit_size: 1 + - name: SAI2EN + description: SAI2 clock enable + bit_offset: 23 + bit_size: 1 + - name: DSIEN + description: DSI clocks enable + bit_offset: 27 + bit_size: 1 fieldset/APB2LPENR: description: APB2 peripheral clock enabled in low power mode register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM1 clock enable during Sleep mode - name: TIM1LPEN - - bit_offset: 4 - bit_size: 1 - description: USART1 clock enable during Sleep mode - name: USART1LPEN - - bit_offset: 5 - bit_size: 1 - description: USART6 clock enable during Sleep mode - name: USART6LPEN - - bit_offset: 8 - bit_size: 1 - description: ADC1 clock enable during Sleep mode - name: ADC1LPEN - - bit_offset: 11 - bit_size: 1 - description: SDIO clock enable during Sleep mode - name: SDIOLPEN - - bit_offset: 12 - bit_size: 1 - description: SPI 1 clock enable during Sleep mode - name: SPI1LPEN - - bit_offset: 13 - bit_size: 1 - description: SPI4 clock enable during Sleep mode - name: SPI4LPEN - - bit_offset: 14 - bit_size: 1 - description: System configuration controller clock enable during Sleep mode - name: SYSCFGLPEN - - bit_offset: 16 - bit_size: 1 - description: TIM9 clock enable during sleep mode - name: TIM9LPEN - - bit_offset: 17 - bit_size: 1 - description: TIM10 clock enable during Sleep mode - name: TIM10LPEN - - bit_offset: 18 - bit_size: 1 - description: TIM11 clock enable during Sleep mode - name: TIM11LPEN - - bit_offset: 1 - bit_size: 1 - description: TIM8 clock enable during Sleep mode - name: TIM8LPEN - - bit_offset: 9 - bit_size: 1 - description: ADC2 clock enable during Sleep mode - name: ADC2LPEN - - bit_offset: 10 - bit_size: 1 - description: ADC 3 clock enable during Sleep mode - name: ADC3LPEN - - bit_offset: 15 - bit_size: 1 - description: EXTI and External IT clock enable during sleep mode - name: EXTITLPEN - - bit_offset: 20 - bit_size: 1 - description: SPI5 clock enable during Sleep mode - name: SPI5LPEN - - bit_offset: 24 - bit_size: 1 - description: DFSDMLPEN - name: DFSDMLPEN - - bit_offset: 6 - bit_size: 1 - description: UART9 clock enable during Sleep mode - name: UART9LPEN - - bit_offset: 7 - bit_size: 1 - description: UART10 clock enable during Sleep mode - name: UART10LPEN - - bit_offset: 22 - bit_size: 1 - description: SAI1 clock enable during Sleep mode - name: SAI1LPEN - - bit_offset: 25 - bit_size: 1 - description: DFSDM2 clock enable during Sleep mode - name: DFSDM2LPEN - - bit_offset: 21 - bit_size: 1 - description: SPI 6 clock enable during Sleep mode - name: SPI6LPEN - - bit_offset: 26 - bit_size: 1 - description: LTDC clock enable during Sleep mode - name: LTDCLPEN - - bit_offset: 23 - bit_size: 1 - description: SAI2 clock enable - name: SAI2LPEN - - bit_offset: 27 - bit_size: 1 - description: DSI clocks enable during Sleep mode - name: DSILPEN + - name: TIM1LPEN + description: TIM1 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: USART1LPEN + description: USART1 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: USART6LPEN + description: USART6 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: ADC1LPEN + description: ADC1 clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: SDIOLPEN + description: SDIO clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1LPEN + description: SPI 1 clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: SPI4LPEN + description: SPI4 clock enable during Sleep mode + bit_offset: 13 + bit_size: 1 + - name: SYSCFGLPEN + description: System configuration controller clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: TIM9LPEN + description: TIM9 clock enable during sleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM10LPEN + description: TIM10 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM11LPEN + description: TIM11 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: TIM8LPEN + description: TIM8 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: ADC2LPEN + description: ADC2 clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: ADC3LPEN + description: ADC 3 clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 + - name: EXTITLPEN + description: EXTI and External IT clock enable during sleep mode + bit_offset: 15 + bit_size: 1 + - name: SPI5LPEN + description: SPI5 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: DFSDMLPEN + description: DFSDMLPEN + bit_offset: 24 + bit_size: 1 + - name: UART9LPEN + description: UART9 clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: UART10LPEN + description: UART10 clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: SAI1LPEN + description: SAI1 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: DFSDM2LPEN + description: DFSDM2 clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: SPI6LPEN + description: SPI 6 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: LTDCLPEN + description: LTDC clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: SAI2LPEN + description: SAI2 clock enable + bit_offset: 23 + bit_size: 1 + - name: DSILPEN + description: DSI clocks enable during Sleep mode + bit_offset: 27 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM1 reset - name: TIM1RST - - bit_offset: 4 - bit_size: 1 - description: USART1 reset - name: USART1RST - - bit_offset: 5 - bit_size: 1 - description: USART6 reset - name: USART6RST - - bit_offset: 8 - bit_size: 1 - description: ADC interface reset (common to all ADCs) - name: ADCRST - - bit_offset: 11 - bit_size: 1 - description: SDIO reset - name: SDIORST - - bit_offset: 12 - bit_size: 1 - description: SPI 1 reset - name: SPI1RST - - bit_offset: 13 - bit_size: 1 - description: SPI4 reset - name: SPI4RST - - bit_offset: 14 - bit_size: 1 - description: System configuration controller reset - name: SYSCFGRST - - bit_offset: 16 - bit_size: 1 - description: TIM9 reset - name: TIM9RST - - bit_offset: 17 - bit_size: 1 - description: TIM10 reset - name: TIM10RST - - bit_offset: 18 - bit_size: 1 - description: TIM11 reset - name: TIM11RST - - bit_offset: 1 - bit_size: 1 - description: TIM8 reset - name: TIM8RST - - bit_offset: 20 - bit_size: 1 - description: SPI5 reset - name: SPI5RST - - bit_offset: 24 - bit_size: 1 - description: DFSDMRST - name: DFSDMRST - - bit_offset: 6 - bit_size: 1 - description: UART9 reset - name: UART9RST - - bit_offset: 7 - bit_size: 1 - description: UART10 reset - name: UART10RST - - bit_offset: 22 - bit_size: 1 - description: SAI1 reset - name: SAI1RST - - bit_offset: 25 - bit_size: 1 - description: DFSDM2 reset - name: DFSDM2RST - - bit_offset: 21 - bit_size: 1 - description: SPI6 reset - name: SPI6RST - - bit_offset: 26 - bit_size: 1 - description: LTDC reset - name: LTDCRST - - bit_offset: 23 - bit_size: 1 - description: SAI2 reset - name: SAI2RST - - bit_offset: 27 - bit_size: 1 - description: DSI host reset - name: DSIRST + - name: TIM1RST + description: TIM1 reset + bit_offset: 0 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 4 + bit_size: 1 + - name: USART6RST + description: USART6 reset + bit_offset: 5 + bit_size: 1 + - name: ADCRST + description: ADC interface reset (common to all ADCs) + bit_offset: 8 + bit_size: 1 + - name: SDIORST + description: SDIO reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: SPI4RST + description: SPI4 reset + bit_offset: 13 + bit_size: 1 + - name: SYSCFGRST + description: System configuration controller reset + bit_offset: 14 + bit_size: 1 + - name: TIM9RST + description: TIM9 reset + bit_offset: 16 + bit_size: 1 + - name: TIM10RST + description: TIM10 reset + bit_offset: 17 + bit_size: 1 + - name: TIM11RST + description: TIM11 reset + bit_offset: 18 + bit_size: 1 + - name: TIM8RST + description: TIM8 reset + bit_offset: 1 + bit_size: 1 + - name: SPI5RST + description: SPI5 reset + bit_offset: 20 + bit_size: 1 + - name: DFSDMRST + description: DFSDMRST + bit_offset: 24 + bit_size: 1 + - name: UART9RST + description: UART9 reset + bit_offset: 6 + bit_size: 1 + - name: UART10RST + description: UART10 reset + bit_offset: 7 + bit_size: 1 + - name: SAI1RST + description: SAI1 reset + bit_offset: 22 + bit_size: 1 + - name: DFSDM2RST + description: DFSDM2 reset + bit_offset: 25 + bit_size: 1 + - name: SPI6RST + description: SPI6 reset + bit_offset: 21 + bit_size: 1 + - name: LTDCRST + description: LTDC reset + bit_offset: 26 + bit_size: 1 + - name: SAI2RST + description: SAI2 reset + bit_offset: 23 + bit_size: 1 + - name: DSIRST + description: DSI host reset + bit_offset: 27 + bit_size: 1 fieldset/BDCR: description: Backup domain control register fields: - - bit_offset: 0 - bit_size: 1 - description: External low-speed oscillator enable - name: LSEON - - bit_offset: 1 - bit_size: 1 - description: External low-speed oscillator ready - enum_read: LSERDYR - name: LSERDY - - bit_offset: 2 - bit_size: 1 - description: External low-speed oscillator bypass - enum: LSEBYP - name: LSEBYP - - bit_offset: 8 - bit_size: 2 - description: RTC clock source selection - enum: RTCSEL - name: RTCSEL - - bit_offset: 15 - bit_size: 1 - description: RTC clock enable - name: RTCEN - - bit_offset: 16 - bit_size: 1 - description: Backup domain software reset - name: BDRST - - bit_offset: 3 - bit_size: 1 - description: External low-speed oscillator bypass - enum: LSEMOD - name: LSEMOD + - name: LSEON + description: External low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSERDYR + - name: LSEBYP + description: External low-speed oscillator bypass + bit_offset: 2 + bit_size: 1 + enum: LSEBYP + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 + - name: LSEMOD + description: External low-speed oscillator bypass + bit_offset: 3 + bit_size: 1 + enum: LSEMOD fieldset/CFGR: description: clock configuration register fields: - - bit_offset: 0 - bit_size: 2 - description: System clock switch - enum: SW - name: SW - - bit_offset: 2 - bit_size: 2 - description: System clock switch status - enum_read: SWSR - name: SWS - - bit_offset: 4 - bit_size: 4 - description: AHB prescaler - enum: HPRE - name: HPRE - - bit_offset: 10 - bit_size: 3 - description: APB Low speed prescaler (APB1) - enum: PPRE - name: PPRE1 - - bit_offset: 13 - bit_size: 3 - description: APB high-speed prescaler (APB2) - enum: PPRE - name: PPRE2 - - bit_offset: 16 - bit_size: 5 - description: HSE division factor for RTC clock - name: RTCPRE - - bit_offset: 21 - bit_size: 2 - description: Microcontroller clock output 1 - enum: MCO1 - name: MCO1 - - bit_offset: 23 - bit_size: 1 - description: I2S clock selection - enum: ISSRC - name: I2SSRC - - bit_offset: 24 - bit_size: 3 - description: MCO1 prescaler - enum: MCOPRE - name: MCO1PRE - - bit_offset: 27 - bit_size: 3 - description: MCO2 prescaler - enum: MCOPRE - name: MCO2PRE - - bit_offset: 30 - bit_size: 2 - description: Microcontroller clock output 2 - enum: MCO2 - name: MCO2 - - bit_offset: 8 - bit_size: 1 - description: MCO output enable - name: MCO1EN - - bit_offset: 9 - bit_size: 1 - description: MCO output enable - name: MCO2EN + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum_read: SWSR + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 10 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 13 + bit_size: 3 + enum: PPRE + - name: RTCPRE + description: HSE division factor for RTC clock + bit_offset: 16 + bit_size: 5 + - name: MCO1 + description: Microcontroller clock output 1 + bit_offset: 21 + bit_size: 2 + enum: MCO1 + - name: I2SSRC + description: I2S clock selection + bit_offset: 23 + bit_size: 1 + enum: ISSRC + - name: MCO1PRE + description: MCO1 prescaler + bit_offset: 24 + bit_size: 3 + enum: MCOPRE + - name: MCO2PRE + description: MCO2 prescaler + bit_offset: 27 + bit_size: 3 + enum: MCOPRE + - name: MCO2 + description: Microcontroller clock output 2 + bit_offset: 30 + bit_size: 2 + enum: MCO2 + - name: MCO1EN + description: MCO output enable + bit_offset: 8 + bit_size: 1 + - name: MCO2EN + description: MCO output enable + bit_offset: 9 + bit_size: 1 fieldset/CIR: description: clock interrupt register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready interrupt flag - enum_read: PLLISRDYFR - name: LSIRDYF - - bit_offset: 1 - bit_size: 1 - description: LSE ready interrupt flag - enum_read: PLLISRDYFR - name: LSERDYF - - bit_offset: 2 - bit_size: 1 - description: HSI ready interrupt flag - enum_read: PLLISRDYFR - name: HSIRDYF - - bit_offset: 3 - bit_size: 1 - description: HSE ready interrupt flag - enum_read: PLLISRDYFR - name: HSERDYF - - bit_offset: 4 - bit_size: 1 - description: Main PLL (PLL) ready interrupt flag - enum_read: PLLISRDYFR - name: PLLRDYF - - bit_offset: 5 - bit_size: 1 - description: PLLI2S ready interrupt flag - enum_read: PLLISRDYFR - name: PLLI2SRDYF - - bit_offset: 7 - bit_size: 1 - description: Clock security system interrupt flag - enum_read: CSSFR - name: CSSF - - bit_offset: 8 - bit_size: 1 - description: LSI ready interrupt enable - enum: PLLISRDYIE - name: LSIRDYIE - - bit_offset: 9 - bit_size: 1 - description: LSE ready interrupt enable - enum: PLLISRDYIE - name: LSERDYIE - - bit_offset: 10 - bit_size: 1 - description: HSI ready interrupt enable - enum: PLLISRDYIE - name: HSIRDYIE - - bit_offset: 11 - bit_size: 1 - description: HSE ready interrupt enable - enum: PLLISRDYIE - name: HSERDYIE - - bit_offset: 12 - bit_size: 1 - description: Main PLL (PLL) ready interrupt enable - enum: PLLISRDYIE - name: PLLRDYIE - - bit_offset: 13 - bit_size: 1 - description: PLLI2S ready interrupt enable - enum: PLLISRDYIE - name: PLLI2SRDYIE - - bit_offset: 16 - bit_size: 1 - description: LSI ready interrupt clear - enum_write: PLLISRDYCW - name: LSIRDYC - - bit_offset: 17 - bit_size: 1 - description: LSE ready interrupt clear - enum_write: PLLISRDYCW - name: LSERDYC - - bit_offset: 18 - bit_size: 1 - description: HSI ready interrupt clear - enum_write: PLLISRDYCW - name: HSIRDYC - - bit_offset: 19 - bit_size: 1 - description: HSE ready interrupt clear - enum_write: PLLISRDYCW - name: HSERDYC - - bit_offset: 20 - bit_size: 1 - description: Main PLL(PLL) ready interrupt clear - enum_write: PLLISRDYCW - name: PLLRDYC - - bit_offset: 21 - bit_size: 1 - description: PLLI2S ready interrupt clear - enum_write: PLLISRDYCW - name: PLLI2SRDYC - - bit_offset: 23 - bit_size: 1 - description: Clock security system interrupt clear - enum_write: CSSCW - name: CSSC - - bit_offset: 6 - bit_size: 1 - description: PLLSAI ready interrupt flag - enum_read: PLLSAIRDYFR - name: PLLSAIRDYF - - bit_offset: 14 - bit_size: 1 - description: PLLSAI Ready Interrupt Enable - enum: PLLSAIRDYIE - name: PLLSAIRDYIE - - bit_offset: 22 - bit_size: 1 - description: PLLSAI Ready Interrupt Clear - enum_write: PLLSAIRDYCW - name: PLLSAIRDYC + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + enum_read: PLLISRDYFR + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + enum_read: PLLISRDYFR + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + enum_read: PLLISRDYFR + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 3 + bit_size: 1 + enum_read: PLLISRDYFR + - name: PLLRDYF + description: Main PLL (PLL) ready interrupt flag + bit_offset: 4 + bit_size: 1 + enum_read: PLLISRDYFR + - name: PLLI2SRDYF + description: PLLI2S ready interrupt flag + bit_offset: 5 + bit_size: 1 + enum_read: PLLISRDYFR + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 7 + bit_size: 1 + enum_read: CSSFR + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 8 + bit_size: 1 + enum: PLLISRDYIE + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 9 + bit_size: 1 + enum: PLLISRDYIE + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 10 + bit_size: 1 + enum: PLLISRDYIE + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 11 + bit_size: 1 + enum: PLLISRDYIE + - name: PLLRDYIE + description: Main PLL (PLL) ready interrupt enable + bit_offset: 12 + bit_size: 1 + enum: PLLISRDYIE + - name: PLLI2SRDYIE + description: PLLI2S ready interrupt enable + bit_offset: 13 + bit_size: 1 + enum: PLLISRDYIE + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 16 + bit_size: 1 + enum_write: PLLISRDYCW + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 17 + bit_size: 1 + enum_write: PLLISRDYCW + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 18 + bit_size: 1 + enum_write: PLLISRDYCW + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 19 + bit_size: 1 + enum_write: PLLISRDYCW + - name: PLLRDYC + description: Main PLL(PLL) ready interrupt clear + bit_offset: 20 + bit_size: 1 + enum_write: PLLISRDYCW + - name: PLLI2SRDYC + description: PLLI2S ready interrupt clear + bit_offset: 21 + bit_size: 1 + enum_write: PLLISRDYCW + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 + enum_write: CSSCW + - name: PLLSAIRDYF + description: PLLSAI ready interrupt flag + bit_offset: 6 + bit_size: 1 + enum_read: PLLSAIRDYFR + - name: PLLSAIRDYIE + description: PLLSAI Ready Interrupt Enable + bit_offset: 14 + bit_size: 1 + enum: PLLSAIRDYIE + - name: PLLSAIRDYC + description: PLLSAI Ready Interrupt Clear + bit_offset: 22 + bit_size: 1 + enum_write: PLLSAIRDYCW fieldset/CKGATENR: description: clocks gated enable register fields: - - bit_offset: 0 - bit_size: 1 - description: AHB to APB1 Bridge clock enable - name: AHB2APB1_CKEN - - bit_offset: 1 - bit_size: 1 - description: AHB to APB2 Bridge clock enable - name: AHB2APB2_CKEN - - bit_offset: 2 - bit_size: 1 - description: Cortex M4 ETM clock enable - name: CM4DBG_CKEN - - bit_offset: 3 - bit_size: 1 - description: Spare clock enable - name: SPARE_CKEN - - bit_offset: 4 - bit_size: 1 - description: SRAM controller clock enable - name: SRAM_CKEN - - bit_offset: 5 - bit_size: 1 - description: Flash interface clock enable - name: FLITF_CKEN - - bit_offset: 6 - bit_size: 1 - description: RCC clock enable - name: RCC_CKEN - - bit_offset: 7 - bit_size: 1 - description: EVTCL clock enable - name: EVTCL_CKEN + - name: AHB2APB1_CKEN + description: AHB to APB1 Bridge clock enable + bit_offset: 0 + bit_size: 1 + - name: AHB2APB2_CKEN + description: AHB to APB2 Bridge clock enable + bit_offset: 1 + bit_size: 1 + - name: CM4DBG_CKEN + description: Cortex M4 ETM clock enable + bit_offset: 2 + bit_size: 1 + - name: SPARE_CKEN + description: Spare clock enable + bit_offset: 3 + bit_size: 1 + - name: SRAM_CKEN + description: SRAM controller clock enable + bit_offset: 4 + bit_size: 1 + - name: FLITF_CKEN + description: Flash interface clock enable + bit_offset: 5 + bit_size: 1 + - name: RCC_CKEN + description: RCC clock enable + bit_offset: 6 + bit_size: 1 + - name: EVTCL_CKEN + description: EVTCL clock enable + bit_offset: 7 + bit_size: 1 fieldset/CR: description: clock control register fields: - - bit_offset: 0 - bit_size: 1 - description: Internal high-speed clock enable - name: HSION - - bit_offset: 1 - bit_size: 1 - description: Internal high-speed clock ready flag - enum_read: PLLISRDYR - name: HSIRDY - - bit_offset: 3 - bit_size: 5 - description: Internal high-speed clock trimming - name: HSITRIM - - bit_offset: 8 - bit_size: 8 - description: Internal high-speed clock calibration - name: HSICAL - - bit_offset: 16 - bit_size: 1 - description: HSE clock enable - name: HSEON - - bit_offset: 17 - bit_size: 1 - description: HSE clock ready flag - enum_read: PLLISRDYR - name: HSERDY - - bit_offset: 18 - bit_size: 1 - description: HSE clock bypass - enum: HSEBYP - name: HSEBYP - - bit_offset: 19 - bit_size: 1 - description: Clock security system enable - name: CSSON - - bit_offset: 24 - bit_size: 1 - description: Main PLL (PLL) enable - name: PLLON - - bit_offset: 25 - bit_size: 1 - description: Main PLL (PLL) clock ready flag - enum_read: PLLISRDYR - name: PLLRDY - - bit_offset: 26 - bit_size: 1 - description: PLLI2S enable - name: PLLI2SON - - bit_offset: 27 - bit_size: 1 - description: PLLI2S clock ready flag - enum_read: PLLISRDYR - name: PLLI2SRDY - - bit_offset: 28 - bit_size: 1 - description: PLLSAI enable - name: PLLSAION - - bit_offset: 29 - bit_size: 1 - description: PLLSAI clock ready flag - enum_read: PLLISRDYR - name: PLLSAIRDY + - name: HSION + description: Internal high-speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal high-speed clock ready flag + bit_offset: 1 + bit_size: 1 + enum_read: PLLISRDYR + - name: HSITRIM + description: Internal high-speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal high-speed clock calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + enum_read: PLLISRDYR + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + enum: HSEBYP + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: Main PLL (PLL) enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL (PLL) clock ready flag + bit_offset: 25 + bit_size: 1 + enum_read: PLLISRDYR + - name: PLLI2SON + description: PLLI2S enable + bit_offset: 26 + bit_size: 1 + - name: PLLI2SRDY + description: PLLI2S clock ready flag + bit_offset: 27 + bit_size: 1 + enum_read: PLLISRDYR + - name: PLLSAION + description: PLLSAI enable + bit_offset: 28 + bit_size: 1 + - name: PLLSAIRDY + description: PLLSAI clock ready flag + bit_offset: 29 + bit_size: 1 + enum_read: PLLISRDYR fieldset/CSR: description: clock control & status register fields: - - bit_offset: 0 - bit_size: 1 - description: Internal low-speed oscillator enable - name: LSION - - bit_offset: 1 - bit_size: 1 - description: Internal low-speed oscillator ready - enum_read: LSIRDYR - name: LSIRDY - - bit_offset: 24 - bit_size: 1 - description: Remove reset flag - enum_write: RMVFW - name: RMVF - - bit_offset: 25 - bit_size: 1 - description: BOR reset flag - enum_read: LPWRRSTFR - name: BORRSTF - - bit_offset: 26 - bit_size: 1 - description: PIN reset flag - enum_read: LPWRRSTFR - name: PADRSTF - - bit_offset: 27 - bit_size: 1 - description: POR/PDR reset flag - enum_read: LPWRRSTFR - name: PORRSTF - - bit_offset: 28 - bit_size: 1 - description: Software reset flag - enum_read: LPWRRSTFR - name: SFTRSTF - - bit_offset: 29 - bit_size: 1 - description: Independent watchdog reset flag - enum_read: LPWRRSTFR - name: WDGRSTF - - bit_offset: 30 - bit_size: 1 - description: Window watchdog reset flag - enum_read: LPWRRSTFR - name: WWDGRSTF - - bit_offset: 31 - bit_size: 1 - description: Low-power reset flag - enum_read: LPWRRSTFR - name: LPWRRSTF + - name: LSION + description: Internal low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSIRDYR + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + enum_write: RMVFW + - name: BORRSTF + description: BOR reset flag + bit_offset: 25 + bit_size: 1 + enum_read: LPWRRSTFR + - name: PADRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + enum_read: LPWRRSTFR + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + enum_read: LPWRRSTFR + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + enum_read: LPWRRSTFR + - name: WDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + enum_read: LPWRRSTFR + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + enum_read: LPWRRSTFR + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 + enum_read: LPWRRSTFR fieldset/DCKCFGR: description: Dedicated Clock Configuration Register fields: - - bit_offset: 24 - bit_size: 1 - description: Timers clocks prescalers selection - enum: TIMPRE - name: TIMPRE - - bit_offset: 25 - bit_size: 2 - description: I2SSRC - enum: ISSRC - name: I2SSRC - - bit_offset: 15 - bit_size: 5 - description: DFSDM1 audio clock selection - enum: CKDFSDMASEL - name: CKDFSDM1ASEL - - bit_offset: 25 - bit_size: 2 - description: I2S APB1 clocks source selection (I2S2/3) - enum: I2S1SRC - name: I2S1SRC - - bit_offset: 27 - bit_size: 2 - description: I2S APB2 clocks source selection (I2S1/4/5) - enum: I2S1SRC - name: I2S2SRC - - bit_offset: 31 - bit_size: 1 - description: DFSDM1 Kernel clock selection - enum: CKDFSDMSEL - name: CKDFSDM1SEL - - bit_offset: 0 - bit_size: 5 - description: PLLI2S division factor for SAI1 A/B clock - enum: PLLISDIVR - name: PLLI2SDIVR - - bit_offset: 8 - bit_size: 5 - description: PLL division factor for SAI1 A/B clock - enum: PLLDIVR - name: PLLDIVR - - bit_offset: 14 - bit_size: 1 - description: DFSDM2 audio clock selection - enum: CKDFSDMASEL - name: CKDFSDM2ASEL - - bit_offset: 20 - bit_size: 2 - description: SAI1-A clock source selection - enum: SAIASRC - name: SAI1ASRC - - bit_offset: 22 - bit_size: 2 - description: SAI1-B clock source selection - enum: SAIBSRC - name: SAI1BSRC - - bit_offset: 0 - bit_size: 5 - description: PLLI2S division factor for SAI1 clock - enum: PLLISDIVQ - name: PLLI2SDIVQ - - bit_offset: 8 - bit_size: 5 - description: PLLSAI division factor for SAI1 clock - enum: PLLSAIDIVQ - name: PLLSAIDIVQ - - bit_offset: 16 - bit_size: 2 - description: division factor for LCD_CLK - enum: PLLSAIDIVR - name: PLLSAIDIVR - - bit_offset: 20 - bit_size: 2 - description: SAI1 clock source selection - enum: SAI1SRC - name: SAI1SRC - - bit_offset: 22 - bit_size: 2 - description: SAI2 clock source selection - enum: SAI2SRC - name: SAI2SRC - - bit_offset: 27 - bit_size: 1 - description: 48 MHz clock source selection - enum: CKMSEL - name: CK48MSEL - - bit_offset: 28 - bit_size: 1 - description: SDIO clock source selection - enum: SDIOSEL - name: SDIOSEL - - bit_offset: 29 - bit_size: 1 - description: DSI clock source selection - enum: DSISEL - name: DSISEL + - name: TIMPRE + description: Timers clocks prescalers selection + bit_offset: 24 + bit_size: 1 + enum: TIMPRE + - name: I2SSRC + description: I2SSRC + bit_offset: 25 + bit_size: 2 + enum: ISSRC + - name: CKDFSDM1ASEL + description: DFSDM1 audio clock selection + bit_offset: 15 + bit_size: 5 + enum: CKDFSDMASEL + - name: I2S1SRC + description: I2S APB1 clocks source selection (I2S2/3) + bit_offset: 25 + bit_size: 2 + enum: I2S1SRC + - name: I2S2SRC + description: I2S APB2 clocks source selection (I2S1/4/5) + bit_offset: 27 + bit_size: 2 + enum: I2S1SRC + - name: CKDFSDM1SEL + description: DFSDM1 Kernel clock selection + bit_offset: 31 + bit_size: 1 + enum: CKDFSDMSEL + - name: PLLI2SDIVR + description: PLLI2S division factor for SAI1 A/B clock + bit_offset: 0 + bit_size: 5 + enum: PLLISDIVR + - name: PLLDIVR + description: PLL division factor for SAI1 A/B clock + bit_offset: 8 + bit_size: 5 + enum: PLLDIVR + - name: CKDFSDM2ASEL + description: DFSDM2 audio clock selection + bit_offset: 14 + bit_size: 1 + enum: CKDFSDMASEL + - name: SAI1ASRC + description: SAI1-A clock source selection + bit_offset: 20 + bit_size: 2 + enum: SAIASRC + - name: SAI1BSRC + description: SAI1-B clock source selection + bit_offset: 22 + bit_size: 2 + enum: SAIBSRC + - name: PLLI2SDIVQ + description: PLLI2S division factor for SAI1 clock + bit_offset: 0 + bit_size: 5 + enum: PLLISDIVQ + - name: PLLSAIDIVQ + description: PLLSAI division factor for SAI1 clock + bit_offset: 8 + bit_size: 5 + enum: PLLSAIDIVQ + - name: PLLSAIDIVR + description: division factor for LCD_CLK + bit_offset: 16 + bit_size: 2 + enum: PLLSAIDIVR + - name: SAI1SRC + description: SAI1 clock source selection + bit_offset: 20 + bit_size: 2 + enum: SAI1SRC + - name: SAI2SRC + description: SAI2 clock source selection + bit_offset: 22 + bit_size: 2 + enum: SAI2SRC + - name: CK48MSEL + description: 48 MHz clock source selection + bit_offset: 27 + bit_size: 1 + enum: CKMSEL + - name: SDIOSEL + description: SDIO clock source selection + bit_offset: 28 + bit_size: 1 + enum: SDIOSEL + - name: DSISEL + description: DSI clock source selection + bit_offset: 29 + bit_size: 1 + enum: DSISEL fieldset/DCKCFGR2: description: dedicated clocks configuration register 2 fields: - - bit_offset: 22 - bit_size: 2 - description: FMPI2C1 kernel clock source selection - enum: FMPICSEL - name: FMPI2C1SEL - - bit_offset: 30 - bit_size: 2 - description: LPTIM1SEL - enum: LPTIMSEL - name: LPTIM1SEL - - bit_offset: 27 - bit_size: 1 - description: SDIO/USBFS clock selection - enum: CKMSEL - name: CK48MSEL - - bit_offset: 28 - bit_size: 1 - description: SDIO clock selection - enum: SDIOSEL - name: SDIOSEL - - bit_offset: 26 - bit_size: 1 - description: HDMI CEC clock source selection - enum: CECSEL - name: CECSEL - - bit_offset: 29 - bit_size: 1 - description: SPDIF clock selection - enum: SPDIFRXSEL - name: SPDIFRXSEL + - name: FMPI2C1SEL + description: FMPI2C1 kernel clock source selection + bit_offset: 22 + bit_size: 2 + enum: FMPICSEL + - name: LPTIM1SEL + description: LPTIM1SEL + bit_offset: 30 + bit_size: 2 + enum: LPTIMSEL + - name: CK48MSEL + description: SDIO/USBFS clock selection + bit_offset: 27 + bit_size: 1 + enum: CKMSEL + - name: SDIOSEL + description: SDIO clock selection + bit_offset: 28 + bit_size: 1 + enum: SDIOSEL + - name: CECSEL + description: HDMI CEC clock source selection + bit_offset: 26 + bit_size: 1 + enum: CECSEL + - name: SPDIFRXSEL + description: SPDIF clock selection + bit_offset: 29 + bit_size: 1 + enum: SPDIFRXSEL fieldset/PLLCFGR: description: PLL configuration register fields: - - bit_offset: 0 - bit_size: 6 - description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input - clock - name: PLLM - - bit_offset: 6 - bit_size: 9 - description: Main PLL (PLL) multiplication factor for VCO - name: PLLN - - bit_offset: 16 - bit_size: 2 - description: Main PLL (PLL) division factor for main system clock - enum: PLLP - name: PLLP - - bit_offset: 22 - bit_size: 1 - description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - enum: PLLSRC - name: PLLSRC - - bit_offset: 24 - bit_size: 4 - description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number - generator clocks - name: PLLQ - - bit_offset: 28 - bit_size: 3 - description: PLL division factor for I2S and System clocks - name: PLLR + - name: PLLM + description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + bit_offset: 0 + bit_size: 6 + - name: PLLN + description: Main PLL (PLL) multiplication factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLP + description: Main PLL (PLL) division factor for main system clock + bit_offset: 16 + bit_size: 2 + enum: PLLP + - name: PLLSRC + description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + bit_offset: 22 + bit_size: 1 + enum: PLLSRC + - name: PLLQ + description: "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" + bit_offset: 24 + bit_size: 4 + - name: PLLR + description: PLL division factor for I2S and System clocks + bit_offset: 28 + bit_size: 3 fieldset/PLLI2SCFGR: description: PLLI2S configuration register fields: - - bit_offset: 6 - bit_size: 9 - description: PLLI2S multiplication factor for VCO - name: PLLI2SN - - bit_offset: 28 - bit_size: 3 - description: PLLI2S division factor for I2S clocks - name: PLLI2SR - - bit_offset: 0 - bit_size: 6 - description: Division factor for the audio PLL (PLLI2S) input clock - name: PLLI2SM - - bit_offset: 22 - bit_size: 1 - description: PLLI2S entry clock source - enum: PLLISSRC - name: PLLI2SSRC - - bit_offset: 24 - bit_size: 4 - description: PLLI2S division factor for USB OTG FS/SDIO/RNG clock - name: PLLI2SQ - - bit_offset: 16 - bit_size: 2 - description: PLLI2S division factor for SPDIF-IN clock - enum: PLLISP - name: PLLI2SP + - name: PLLI2SN + description: PLLI2S multiplication factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLI2SR + description: PLLI2S division factor for I2S clocks + bit_offset: 28 + bit_size: 3 + - name: PLLI2SM + description: Division factor for the audio PLL (PLLI2S) input clock + bit_offset: 0 + bit_size: 6 + - name: PLLI2SSRC + description: PLLI2S entry clock source + bit_offset: 22 + bit_size: 1 + enum: PLLISSRC + - name: PLLI2SQ + description: PLLI2S division factor for USB OTG FS/SDIO/RNG clock + bit_offset: 24 + bit_size: 4 + - name: PLLI2SP + description: PLLI2S division factor for SPDIF-IN clock + bit_offset: 16 + bit_size: 2 + enum: PLLISP fieldset/PLLSAICFGR: description: PLL configuration register fields: - - bit_offset: 6 - bit_size: 9 - description: PLLSAI division factor for VCO - name: PLLSAIN - - bit_offset: 24 - bit_size: 4 - description: PLLSAI division factor for SAI1 clock - name: PLLSAIQ - - bit_offset: 28 - bit_size: 3 - description: PLLSAI division factor for LCD clock - name: PLLSAIR - - bit_offset: 0 - bit_size: 6 - description: Division factor for audio PLLSAI input clock - name: PLLSAIM - - bit_offset: 16 - bit_size: 2 - description: PLLSAI division factor for 48 MHz clock - enum: PLLSAIP - name: PLLSAIP + - name: PLLSAIN + description: PLLSAI division factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLSAIQ + description: PLLSAI division factor for SAI1 clock + bit_offset: 24 + bit_size: 4 + - name: PLLSAIR + description: PLLSAI division factor for LCD clock + bit_offset: 28 + bit_size: 3 + - name: PLLSAIM + description: Division factor for audio PLLSAI input clock + bit_offset: 0 + bit_size: 6 + - name: PLLSAIP + description: PLLSAI division factor for 48 MHz clock + bit_offset: 16 + bit_size: 2 + enum: PLLSAIP fieldset/SSCGR: description: spread spectrum clock generation register fields: - - bit_offset: 0 - bit_size: 13 - description: Modulation period - name: MODPER - - bit_offset: 13 - bit_size: 15 - description: Incrementation step - name: INCSTEP - - bit_offset: 30 - bit_size: 1 - description: Spread Select - enum: SPREADSEL - name: SPREADSEL - - bit_offset: 31 - bit_size: 1 - description: Spread spectrum modulation enable - name: SSCGEN + - name: MODPER + description: Modulation period + bit_offset: 0 + bit_size: 13 + - name: INCSTEP + description: Incrementation step + bit_offset: 13 + bit_size: 15 + - name: SPREADSEL + description: Spread Select + bit_offset: 30 + bit_size: 1 + enum: SPREADSEL + - name: SSCGEN + description: Spread spectrum modulation enable + bit_offset: 31 + bit_size: 1 +enum/CECSEL: + bit_size: 1 + variants: + - name: LSE + description: LSE clock is selected as HDMI-CEC clock + value: 0 + - name: HSI_Div488 + description: HSI divided by 488 clock is selected as HDMI-CEC clock + value: 1 +enum/CKDFSDMASEL: + bit_size: 1 + variants: + - name: I2S1 + description: CK_I2S_APB1 selected as audio clock + value: 0 + - name: I2S2 + description: CK_I2S_APB2 selected as audio clock + value: 1 +enum/CKDFSDMSEL: + bit_size: 1 + variants: + - name: APB2 + description: APB2 clock used as Kernel clock + value: 0 + - name: SYSCLK + description: System clock used as Kernel clock + value: 1 +enum/CKMSEL: + bit_size: 1 + variants: + - name: PLL + description: 48MHz clock from PLL is selected + value: 0 + - name: PLLSAI + description: 48MHz clock from PLLSAI is selected + value: 1 +enum/CSSCW: + bit_size: 1 + variants: + - name: Clear + description: Clear CSSF flag + value: 1 +enum/CSSFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock security interrupt caused by HSE clock failure + value: 0 + - name: Interrupted + description: Clock security interrupt caused by HSE clock failure + value: 1 +enum/DSISEL: + bit_size: 1 + variants: + - name: DSI_PHY + description: DSI-PHY used as DSI byte lane clock source (usual case) + value: 0 + - name: PLLR + description: "PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)" + value: 1 +enum/FMPICSEL: + bit_size: 2 + variants: + - name: APB + description: APB clock selected as I2C clock + value: 0 + - name: SYSCLK + description: System clock selected as I2C clock + value: 1 + - name: HSI + description: HSI clock selected as I2C clock + value: 2 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/HSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: HSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: HSE crystal oscillator bypassed with external clock + value: 1 +enum/HSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: Clock not ready + value: 0 + - name: Ready + description: Clock ready + value: 1 +enum/I2S1SRC: + bit_size: 2 + variants: + - name: PLLI2SR + description: I2Sx clock frequency = f(PLLI2S_R) + value: 0 + - name: I2S_CKIN + description: I2Sx clock frequency = I2S_CKIN Alternate function input frequency + value: 1 + - name: PLLR + description: I2Sx clock frequency = f(PLL_R) + value: 2 + - name: HSI_HSE + description: "I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])" + value: 3 +enum/I2SSRC: + bit_size: 1 + variants: + - name: PLLI2S + description: PLLI2S clock used as I2S clock source + value: 0 + - name: CKIN + description: External clock mapped on the I2S_CKIN pin used as I2S clock source + value: 1 +enum/ISSRC: + bit_size: 1 + variants: + - name: PLLI2S + description: PLLI2S clock used as I2S clock source + value: 0 + - name: CKIN + description: External clock mapped on the I2S_CKIN pin used as I2S clock source + value: 1 +enum/LPTIMSEL: + bit_size: 2 + variants: + - name: APB1 + description: APB1 clock (PCLK1) selected as LPTILM1 clock + value: 0 + - name: LSI + description: LSI clock is selected as LPTILM1 clock + value: 1 + - name: HSI + description: HSI clock is selected as LPTILM1 clock + value: 2 + - name: LSE + description: LSE clock is selected as LPTILM1 clock + value: 3 +enum/LPWRRSTFR: + bit_size: 1 + variants: + - name: NoReset + description: No reset has occured + value: 0 + - name: Reset + description: A reset has occured + value: 1 +enum/LSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: LSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: LSE crystal oscillator bypassed with external clock + value: 1 +enum/LSEMOD: + bit_size: 1 + variants: + - name: Low + description: LSE oscillator low power mode selection + value: 0 + - name: High + description: LSE oscillator high drive mode selection + value: 1 +enum/LSERDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSE oscillator not ready + value: 0 + - name: Ready + description: LSE oscillator ready + value: 1 +enum/LSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSI oscillator not ready + value: 0 + - name: Ready + description: LSI oscillator ready + value: 1 +enum/MCO1: + bit_size: 2 + variants: + - name: HSI + description: HSI clock selected + value: 0 + - name: LSE + description: LSE oscillator selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 +enum/MCO2: + bit_size: 2 + variants: + - name: SYSCLK + description: System clock (SYSCLK) selected + value: 0 + - name: PLLI2S + description: PLLI2S clock selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 4 + - name: Div3 + description: Division by 3 + value: 5 + - name: Div4 + description: Division by 4 + value: 6 + - name: Div5 + description: Division by 5 + value: 7 +enum/PLLDIVR: + bit_size: 5 + variants: + - name: Div1 + description: PLLSAIDIVQ = /1 + value: 0 + - name: Div2 + description: PLLSAIDIVQ = /2 + value: 1 + - name: Div3 + description: PLLSAIDIVQ = /3 + value: 2 + - name: Div4 + description: PLLSAIDIVQ = /4 + value: 3 + - name: Div5 + description: PLLSAIDIVQ = /5 + value: 4 + - name: Div6 + description: PLLSAIDIVQ = /6 + value: 5 + - name: Div7 + description: PLLSAIDIVQ = /7 + value: 6 + - name: Div8 + description: PLLSAIDIVQ = /8 + value: 7 + - name: Div9 + description: PLLSAIDIVQ = /9 + value: 8 + - name: Div10 + description: PLLSAIDIVQ = /10 + value: 9 + - name: Div11 + description: PLLSAIDIVQ = /11 + value: 10 + - name: Div12 + description: PLLSAIDIVQ = /12 + value: 11 + - name: Div13 + description: PLLSAIDIVQ = /13 + value: 12 + - name: Div14 + description: PLLSAIDIVQ = /14 + value: 13 + - name: Div15 + description: PLLSAIDIVQ = /15 + value: 14 + - name: Div16 + description: PLLSAIDIVQ = /16 + value: 15 + - name: Div17 + description: PLLSAIDIVQ = /17 + value: 16 + - name: Div18 + description: PLLSAIDIVQ = /18 + value: 17 + - name: Div19 + description: PLLSAIDIVQ = /19 + value: 18 + - name: Div20 + description: PLLSAIDIVQ = /20 + value: 19 + - name: Div21 + description: PLLSAIDIVQ = /21 + value: 20 + - name: Div22 + description: PLLSAIDIVQ = /22 + value: 21 + - name: Div23 + description: PLLSAIDIVQ = /23 + value: 22 + - name: Div24 + description: PLLSAIDIVQ = /24 + value: 23 + - name: Div25 + description: PLLSAIDIVQ = /25 + value: 24 + - name: Div26 + description: PLLSAIDIVQ = /26 + value: 25 + - name: Div27 + description: PLLSAIDIVQ = /27 + value: 26 + - name: Div28 + description: PLLSAIDIVQ = /28 + value: 27 + - name: Div29 + description: PLLSAIDIVQ = /29 + value: 28 + - name: Div30 + description: PLLSAIDIVQ = /30 + value: 29 + - name: Div31 + description: PLLSAIDIVQ = /31 + value: 30 + - name: Div32 + description: PLLSAIDIVQ = /32 + value: 31 +enum/PLLISDIVQ: + bit_size: 5 + variants: + - name: Div1 + description: PLLI2SDIVQ = /1 + value: 0 + - name: Div2 + description: PLLI2SDIVQ = /2 + value: 1 + - name: Div3 + description: PLLI2SDIVQ = /3 + value: 2 + - name: Div4 + description: PLLI2SDIVQ = /4 + value: 3 + - name: Div5 + description: PLLI2SDIVQ = /5 + value: 4 + - name: Div6 + description: PLLI2SDIVQ = /6 + value: 5 + - name: Div7 + description: PLLI2SDIVQ = /7 + value: 6 + - name: Div8 + description: PLLI2SDIVQ = /8 + value: 7 + - name: Div9 + description: PLLI2SDIVQ = /9 + value: 8 + - name: Div10 + description: PLLI2SDIVQ = /10 + value: 9 + - name: Div11 + description: PLLI2SDIVQ = /11 + value: 10 + - name: Div12 + description: PLLI2SDIVQ = /12 + value: 11 + - name: Div13 + description: PLLI2SDIVQ = /13 + value: 12 + - name: Div14 + description: PLLI2SDIVQ = /14 + value: 13 + - name: Div15 + description: PLLI2SDIVQ = /15 + value: 14 + - name: Div16 + description: PLLI2SDIVQ = /16 + value: 15 + - name: Div17 + description: PLLI2SDIVQ = /17 + value: 16 + - name: Div18 + description: PLLI2SDIVQ = /18 + value: 17 + - name: Div19 + description: PLLI2SDIVQ = /19 + value: 18 + - name: Div20 + description: PLLI2SDIVQ = /20 + value: 19 + - name: Div21 + description: PLLI2SDIVQ = /21 + value: 20 + - name: Div22 + description: PLLI2SDIVQ = /22 + value: 21 + - name: Div23 + description: PLLI2SDIVQ = /23 + value: 22 + - name: Div24 + description: PLLI2SDIVQ = /24 + value: 23 + - name: Div25 + description: PLLI2SDIVQ = /25 + value: 24 + - name: Div26 + description: PLLI2SDIVQ = /26 + value: 25 + - name: Div27 + description: PLLI2SDIVQ = /27 + value: 26 + - name: Div28 + description: PLLI2SDIVQ = /28 + value: 27 + - name: Div29 + description: PLLI2SDIVQ = /29 + value: 28 + - name: Div30 + description: PLLI2SDIVQ = /30 + value: 29 + - name: Div31 + description: PLLI2SDIVQ = /31 + value: 30 + - name: Div32 + description: PLLI2SDIVQ = /32 + value: 31 +enum/PLLISDIVR: + bit_size: 5 + variants: + - name: Div1 + description: PLLI2SDIVQ = /1 + value: 0 + - name: Div2 + description: PLLI2SDIVQ = /2 + value: 1 + - name: Div3 + description: PLLI2SDIVQ = /3 + value: 2 + - name: Div4 + description: PLLI2SDIVQ = /4 + value: 3 + - name: Div5 + description: PLLI2SDIVQ = /5 + value: 4 + - name: Div6 + description: PLLI2SDIVQ = /6 + value: 5 + - name: Div7 + description: PLLI2SDIVQ = /7 + value: 6 + - name: Div8 + description: PLLI2SDIVQ = /8 + value: 7 + - name: Div9 + description: PLLI2SDIVQ = /9 + value: 8 + - name: Div10 + description: PLLI2SDIVQ = /10 + value: 9 + - name: Div11 + description: PLLI2SDIVQ = /11 + value: 10 + - name: Div12 + description: PLLI2SDIVQ = /12 + value: 11 + - name: Div13 + description: PLLI2SDIVQ = /13 + value: 12 + - name: Div14 + description: PLLI2SDIVQ = /14 + value: 13 + - name: Div15 + description: PLLI2SDIVQ = /15 + value: 14 + - name: Div16 + description: PLLI2SDIVQ = /16 + value: 15 + - name: Div17 + description: PLLI2SDIVQ = /17 + value: 16 + - name: Div18 + description: PLLI2SDIVQ = /18 + value: 17 + - name: Div19 + description: PLLI2SDIVQ = /19 + value: 18 + - name: Div20 + description: PLLI2SDIVQ = /20 + value: 19 + - name: Div21 + description: PLLI2SDIVQ = /21 + value: 20 + - name: Div22 + description: PLLI2SDIVQ = /22 + value: 21 + - name: Div23 + description: PLLI2SDIVQ = /23 + value: 22 + - name: Div24 + description: PLLI2SDIVQ = /24 + value: 23 + - name: Div25 + description: PLLI2SDIVQ = /25 + value: 24 + - name: Div26 + description: PLLI2SDIVQ = /26 + value: 25 + - name: Div27 + description: PLLI2SDIVQ = /27 + value: 26 + - name: Div28 + description: PLLI2SDIVQ = /28 + value: 27 + - name: Div29 + description: PLLI2SDIVQ = /29 + value: 28 + - name: Div30 + description: PLLI2SDIVQ = /30 + value: 29 + - name: Div31 + description: PLLI2SDIVQ = /31 + value: 30 + - name: Div32 + description: PLLI2SDIVQ = /32 + value: 31 +enum/PLLISP: + bit_size: 2 + variants: + - name: Div2 + description: PLL*P=2 + value: 0 + - name: Div4 + description: PLL*P=4 + value: 1 + - name: Div6 + description: PLL*P=6 + value: 2 + - name: Div8 + description: PLL*P=8 + value: 3 +enum/PLLISRDYCW: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag + value: 1 +enum/PLLISRDYFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock ready interrupt + value: 0 + - name: Interrupted + description: Clock ready interrupt + value: 1 +enum/PLLISRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt disabled + value: 0 + - name: Enabled + description: Interrupt enabled + value: 1 +enum/PLLISRDYR: + bit_size: 1 + variants: + - name: NotReady + description: Clock not ready + value: 0 + - name: Ready + description: Clock ready + value: 1 +enum/PLLISSRC: + bit_size: 1 + variants: + - name: HSE_HSI + description: HSE or HSI depending on PLLSRC of PLLCFGR + value: 0 + - name: External + description: External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry + value: 1 +enum/PLLP: + bit_size: 2 + variants: + - name: Div2 + description: PLLP=2 + value: 0 + - name: Div4 + description: PLLP=4 + value: 1 + - name: Div6 + description: PLLP=6 + value: 2 + - name: Div8 + description: PLLP=8 + value: 3 +enum/PLLSAIDIVQ: + bit_size: 5 + variants: + - name: Div1 + description: PLLSAIDIVQ = /1 + value: 0 + - name: Div2 + description: PLLSAIDIVQ = /2 + value: 1 + - name: Div3 + description: PLLSAIDIVQ = /3 + value: 2 + - name: Div4 + description: PLLSAIDIVQ = /4 + value: 3 + - name: Div5 + description: PLLSAIDIVQ = /5 + value: 4 + - name: Div6 + description: PLLSAIDIVQ = /6 + value: 5 + - name: Div7 + description: PLLSAIDIVQ = /7 + value: 6 + - name: Div8 + description: PLLSAIDIVQ = /8 + value: 7 + - name: Div9 + description: PLLSAIDIVQ = /9 + value: 8 + - name: Div10 + description: PLLSAIDIVQ = /10 + value: 9 + - name: Div11 + description: PLLSAIDIVQ = /11 + value: 10 + - name: Div12 + description: PLLSAIDIVQ = /12 + value: 11 + - name: Div13 + description: PLLSAIDIVQ = /13 + value: 12 + - name: Div14 + description: PLLSAIDIVQ = /14 + value: 13 + - name: Div15 + description: PLLSAIDIVQ = /15 + value: 14 + - name: Div16 + description: PLLSAIDIVQ = /16 + value: 15 + - name: Div17 + description: PLLSAIDIVQ = /17 + value: 16 + - name: Div18 + description: PLLSAIDIVQ = /18 + value: 17 + - name: Div19 + description: PLLSAIDIVQ = /19 + value: 18 + - name: Div20 + description: PLLSAIDIVQ = /20 + value: 19 + - name: Div21 + description: PLLSAIDIVQ = /21 + value: 20 + - name: Div22 + description: PLLSAIDIVQ = /22 + value: 21 + - name: Div23 + description: PLLSAIDIVQ = /23 + value: 22 + - name: Div24 + description: PLLSAIDIVQ = /24 + value: 23 + - name: Div25 + description: PLLSAIDIVQ = /25 + value: 24 + - name: Div26 + description: PLLSAIDIVQ = /26 + value: 25 + - name: Div27 + description: PLLSAIDIVQ = /27 + value: 26 + - name: Div28 + description: PLLSAIDIVQ = /28 + value: 27 + - name: Div29 + description: PLLSAIDIVQ = /29 + value: 28 + - name: Div30 + description: PLLSAIDIVQ = /30 + value: 29 + - name: Div31 + description: PLLSAIDIVQ = /31 + value: 30 + - name: Div32 + description: PLLSAIDIVQ = /32 + value: 31 +enum/PLLSAIDIVR: + bit_size: 2 + variants: + - name: Div2 + description: PLLSAIDIVR = /2 + value: 0 + - name: Div4 + description: PLLSAIDIVR = /4 + value: 1 + - name: Div8 + description: PLLSAIDIVR = /8 + value: 2 + - name: Div16 + description: PLLSAIDIVR = /16 + value: 3 +enum/PLLSAIP: + bit_size: 2 + variants: + - name: Div2 + description: PLL*P=2 + value: 0 + - name: Div4 + description: PLL*P=4 + value: 1 + - name: Div6 + description: PLL*P=6 + value: 2 + - name: Div8 + description: PLL*P=8 + value: 3 +enum/PLLSAIRDYCW: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag + value: 1 +enum/PLLSAIRDYFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock ready interrupt + value: 0 + - name: Interrupted + description: Clock ready interrupt + value: 1 +enum/PLLSAIRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt disabled + value: 0 + - name: Enabled + description: Interrupt enabled + value: 1 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI + description: HSI clock selected as PLL and PLLI2S clock entry + value: 0 + - name: HSE + description: HSE oscillator clock selected as PLL and PLLI2S clock entry + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/RMVFW: + bit_size: 1 + variants: + - name: Clear + description: Clears the reset flag + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SAI1SRC: + bit_size: 2 + variants: + - name: PLLSAI + description: SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + value: 0 + - name: PLLI2S + description: SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + value: 1 + - name: PLLR + description: SAI1 clock frequency = f(PLL_R) + value: 2 + - name: I2S_CKIN + description: I2S_CKIN Alternate function input frequency + value: 3 +enum/SAI2SRC: + bit_size: 2 + variants: + - name: PLLSAI + description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + value: 0 + - name: PLLI2S + description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + value: 1 + - name: PLLR + description: SAI2 clock frequency = f(PLL_R) + value: 2 + - name: HSI_HSE + description: SAI2 clock frequency = Alternate function input frequency + value: 3 +enum/SAIASRC: + bit_size: 2 + variants: + - name: PLLSAI + description: SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + value: 0 + - name: PLLI2S + description: SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + value: 1 + - name: I2S_CKIN + description: SAI1-A clock frequency = Alternate function input frequency + value: 2 +enum/SAIBSRC: + bit_size: 2 + variants: + - name: PLLSAI + description: SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + value: 0 + - name: PLLI2S + description: SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + value: 1 + - name: I2S_CKIN + description: SAI1-B clock frequency = Alternate function input frequency + value: 2 +enum/SDIOSEL: + bit_size: 1 + variants: + - name: CK48M + description: 48 MHz clock is selected as SD clock + value: 0 + - name: SYSCLK + description: System clock is selected as SD clock + value: 1 +enum/SPDIFRXSEL: + bit_size: 1 + variants: + - name: PLL + description: SPDIF-Rx clock from PLL is selected + value: 0 + - name: PLLI2S + description: SPDIF-Rx clock from PLLI2S is selected + value: 1 +enum/SPREADSEL: + bit_size: 1 + variants: + - name: Center + description: Center spread + value: 0 + - name: Down + description: Down spread + value: 1 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLL + description: PLL selected as system clock + value: 2 +enum/SWSR: + bit_size: 2 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 +enum/TIMPRE: + bit_size: 1 + variants: + - name: Mul2 + description: "If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx" + value: 0 + - name: Mul4 + description: "If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx" + value: 1 diff --git a/data/registers/rcc_f410.yaml b/data/registers/rcc_f410.yaml index ab16d39..34e6227 100644 --- a/data/registers/rcc_f410.yaml +++ b/data/registers/rcc_f410.yaml @@ -1,3 +1,4 @@ +--- block/RCC: description: Reset and clock control items: diff --git a/data/registers/rcc_f7.yaml b/data/registers/rcc_f7.yaml index 2d5cc7a..59a9e85 100644 --- a/data/registers/rcc_f7.yaml +++ b/data/registers/rcc_f7.yaml @@ -2,2398 +2,2393 @@ block/RCC: description: Reset and clock control items: - - byte_offset: 0 - description: clock control register - fieldset: CR - name: CR - - byte_offset: 4 - description: PLL configuration register - fieldset: PLLCFGR - name: PLLCFGR - - byte_offset: 8 - description: clock configuration register - fieldset: CFGR - name: CFGR - - byte_offset: 12 - description: clock interrupt register - fieldset: CIR - name: CIR - - byte_offset: 16 - description: AHB1 peripheral reset register - fieldset: AHB1RSTR - name: AHB1RSTR - - byte_offset: 20 - description: AHB2 peripheral reset register - fieldset: AHB2RSTR - name: AHB2RSTR - - byte_offset: 24 - description: AHB3 peripheral reset register - fieldset: AHB3RSTR - name: AHB3RSTR - - byte_offset: 32 - description: APB1 peripheral reset register - fieldset: APB1RSTR - name: APB1RSTR - - byte_offset: 36 - description: APB2 peripheral reset register - fieldset: APB2RSTR - name: APB2RSTR - - byte_offset: 48 - description: AHB1 peripheral clock register - fieldset: AHB1ENR - name: AHB1ENR - - byte_offset: 52 - description: AHB2 peripheral clock enable register - fieldset: AHB2ENR - name: AHB2ENR - - byte_offset: 56 - description: AHB3 peripheral clock enable register - fieldset: AHB3ENR - name: AHB3ENR - - byte_offset: 64 - description: APB1 peripheral clock enable register - fieldset: APB1ENR - name: APB1ENR - - byte_offset: 68 - description: APB2 peripheral clock enable register - fieldset: APB2ENR - name: APB2ENR - - byte_offset: 80 - description: AHB1 peripheral clock enable in low power mode register - fieldset: AHB1LPENR - name: AHB1LPENR - - byte_offset: 84 - description: AHB2 peripheral clock enable in low power mode register - fieldset: AHB2LPENR - name: AHB2LPENR - - byte_offset: 88 - description: AHB3 peripheral clock enable in low power mode register - fieldset: AHB3LPENR - name: AHB3LPENR - - byte_offset: 96 - description: APB1 peripheral clock enable in low power mode register - fieldset: APB1LPENR - name: APB1LPENR - - byte_offset: 100 - description: APB2 peripheral clock enabled in low power mode register - fieldset: APB2LPENR - name: APB2LPENR - - byte_offset: 112 - description: Backup domain control register - fieldset: BDCR - name: BDCR - - byte_offset: 116 - description: clock control & status register - fieldset: CSR - name: CSR - - byte_offset: 128 - description: spread spectrum clock generation register - fieldset: SSCGR - name: SSCGR - - byte_offset: 132 - description: PLLI2S configuration register - fieldset: PLLI2SCFGR - name: PLLI2SCFGR - - byte_offset: 136 - description: PLL configuration register - fieldset: PLLSAICFGR - name: PLLSAICFGR - - byte_offset: 140 - description: dedicated clocks configuration register - fieldset: DCKCFGR1 - name: DCKCFGR1 - - byte_offset: 144 - description: dedicated clocks configuration register - fieldset: DCKCFGR2 - name: DCKCFGR2 -enum/ADFSDMSEL: - bit_size: 1 - variants: - - description: SAI1 clock selected as DFSDM1 Audio clock source - name: SAI1 - value: 0 - - description: SAI2 clock selected as DFSDM1 Audio clock source - name: SAI2 - value: 1 -enum/BORRSTFR: - bit_size: 1 - variants: - - description: No reset has occured - name: NoReset - value: 0 - - description: A reset has occured - name: Reset - value: 1 -enum/CECSEL: - bit_size: 1 - variants: - - description: LSE clock is selected as HDMI-CEC clock - name: LSE - value: 0 - - description: HSI divided by 488 clock is selected as HDMI-CEC clock - name: HSI_Div488 - value: 1 -enum/CKMSEL: - bit_size: 1 - variants: - - description: 48MHz clock from PLL is selected - name: PLL - value: 0 - - description: 48MHz clock from PLLSAI is selected - name: PLLSAI - value: 1 -enum/CSSCW: - bit_size: 1 - variants: - - description: Clear CSSF flag - name: Clear - value: 1 -enum/CSSFR: - bit_size: 1 - variants: - - description: No clock security interrupt caused by HSE clock failure - name: NotInterrupted - value: 0 - - description: Clock security interrupt caused by HSE clock failure - name: Interrupted - value: 1 -enum/DFSDMSEL: - bit_size: 1 - variants: - - description: APB2 clock (PCLK2) selected as DFSDM1 Kernel clock source - name: APB2 - value: 0 - - description: System clock (SYSCLK) clock selected as DFSDM1 Kernel clock source - name: SYSCLK - value: 1 -enum/DSISEL: - bit_size: 1 - variants: - - description: DSI-PHY used as DSI byte lane clock source (usual case) - name: DSI_PHY - value: 0 - - description: PLLR used as DSI byte lane clock source, used in case DSI PLL and - DSI-PHY are off (low power mode) - name: PLLR - value: 1 -enum/HPRE: - bit_size: 4 - variants: - - description: SYSCLK not divided - name: Div1 - value: 0 - - description: SYSCLK divided by 2 - name: Div2 - value: 8 - - description: SYSCLK divided by 4 - name: Div4 - value: 9 - - description: SYSCLK divided by 8 - name: Div8 - value: 10 - - description: SYSCLK divided by 16 - name: Div16 - value: 11 - - description: SYSCLK divided by 64 - name: Div64 - value: 12 - - description: SYSCLK divided by 128 - name: Div128 - value: 13 - - description: SYSCLK divided by 256 - name: Div256 - value: 14 - - description: SYSCLK divided by 512 - name: Div512 - value: 15 -enum/HSEBYP: - bit_size: 1 - variants: - - description: HSE crystal oscillator not bypassed - name: NotBypassed - value: 0 - - description: HSE crystal oscillator bypassed with external clock - name: Bypassed - value: 1 -enum/HSIRDYR: - bit_size: 1 - variants: - - description: Clock not ready - name: NotReady - value: 0 - - description: Clock ready - name: Ready - value: 1 -enum/ICSEL: - bit_size: 2 - variants: - - description: APB clock selected as I2C clock - name: APB - value: 0 - - description: System clock selected as I2C clock - name: SYSCLK - value: 1 - - description: HSI clock selected as I2C clock - name: HSI - value: 2 -enum/ISSRC: - bit_size: 1 - variants: - - description: PLLI2S clock used as I2S clock source - name: PLLI2S - value: 0 - - description: External clock mapped on the I2S_CKIN pin used as I2S clock source - name: CKIN - value: 1 -enum/LPTIMSEL: - bit_size: 2 - variants: - - description: APB1 clock (PCLK1) selected as LPTILM1 clock - name: APB1 - value: 0 - - description: LSI clock is selected as LPTILM1 clock - name: LSI - value: 1 - - description: HSI clock is selected as LPTILM1 clock - name: HSI - value: 2 - - description: LSE clock is selected as LPTILM1 clock - name: LSE - value: 3 -enum/LSEBYP: - bit_size: 1 - variants: - - description: LSE crystal oscillator not bypassed - name: NotBypassed - value: 0 - - description: LSE crystal oscillator bypassed with external clock - name: Bypassed - value: 1 -enum/LSEDRV: - bit_size: 2 - variants: - - description: Low drive capacity - name: Low - value: 0 - - description: Medium-high drive capacity - name: MediumHigh - value: 1 - - description: Medium-low drive capacity - name: MediumLow - value: 2 - - description: High drive capacity - name: High - value: 3 -enum/LSERDYR: - bit_size: 1 - variants: - - description: LSE oscillator not ready - name: NotReady - value: 0 - - description: LSE oscillator ready - name: Ready - value: 1 -enum/LSIRDYCW: - bit_size: 1 - variants: - - description: Clear interrupt flag - name: Clear - value: 1 -enum/LSIRDYFR: - bit_size: 1 - variants: - - description: No clock ready interrupt - name: NotInterrupted - value: 0 - - description: Clock ready interrupt - name: Interrupted - value: 1 -enum/LSIRDYIE: - bit_size: 1 - variants: - - description: Interrupt disabled - name: Disabled - value: 0 - - description: Interrupt enabled - name: Enabled - value: 1 -enum/LSIRDYR: - bit_size: 1 - variants: - - description: LSI oscillator not ready - name: NotReady - value: 0 - - description: LSI oscillator ready - name: Ready - value: 1 -enum/MCO1: - bit_size: 2 - variants: - - description: HSI clock selected - name: HSI - value: 0 - - description: LSE oscillator selected - name: LSE - value: 1 - - description: HSE oscillator clock selected - name: HSE - value: 2 - - description: PLL clock selected - name: PLL - value: 3 -enum/MCO2: - bit_size: 2 - variants: - - description: System clock (SYSCLK) selected - name: SYSCLK - value: 0 - - description: PLLI2S clock selected - name: PLLI2S - value: 1 - - description: HSE oscillator clock selected - name: HSE - value: 2 - - description: PLL clock selected - name: PLL - value: 3 -enum/MCOPRE: - bit_size: 3 - variants: - - description: No division - name: Div1 - value: 0 - - description: Division by 2 - name: Div2 - value: 4 - - description: Division by 3 - name: Div3 - value: 5 - - description: Division by 4 - name: Div4 - value: 6 - - description: Division by 5 - name: Div5 - value: 7 -enum/PLLISDIVQ: - bit_size: 5 - variants: - - description: PLLI2SDIVQ = /1 - name: Div1 - value: 0 - - description: PLLI2SDIVQ = /2 - name: Div2 - value: 1 - - description: PLLI2SDIVQ = /3 - name: Div3 - value: 2 - - description: PLLI2SDIVQ = /4 - name: Div4 - value: 3 - - description: PLLI2SDIVQ = /5 - name: Div5 - value: 4 - - description: PLLI2SDIVQ = /6 - name: Div6 - value: 5 - - description: PLLI2SDIVQ = /7 - name: Div7 - value: 6 - - description: PLLI2SDIVQ = /8 - name: Div8 - value: 7 - - description: PLLI2SDIVQ = /9 - name: Div9 - value: 8 - - description: PLLI2SDIVQ = /10 - name: Div10 - value: 9 - - description: PLLI2SDIVQ = /11 - name: Div11 - value: 10 - - description: PLLI2SDIVQ = /12 - name: Div12 - value: 11 - - description: PLLI2SDIVQ = /13 - name: Div13 - value: 12 - - description: PLLI2SDIVQ = /14 - name: Div14 - value: 13 - - description: PLLI2SDIVQ = /15 - name: Div15 - value: 14 - - description: PLLI2SDIVQ = /16 - name: Div16 - value: 15 - - description: PLLI2SDIVQ = /17 - name: Div17 - value: 16 - - description: PLLI2SDIVQ = /18 - name: Div18 - value: 17 - - description: PLLI2SDIVQ = /19 - name: Div19 - value: 18 - - description: PLLI2SDIVQ = /20 - name: Div20 - value: 19 - - description: PLLI2SDIVQ = /21 - name: Div21 - value: 20 - - description: PLLI2SDIVQ = /22 - name: Div22 - value: 21 - - description: PLLI2SDIVQ = /23 - name: Div23 - value: 22 - - description: PLLI2SDIVQ = /24 - name: Div24 - value: 23 - - description: PLLI2SDIVQ = /25 - name: Div25 - value: 24 - - description: PLLI2SDIVQ = /26 - name: Div26 - value: 25 - - description: PLLI2SDIVQ = /27 - name: Div27 - value: 26 - - description: PLLI2SDIVQ = /28 - name: Div28 - value: 27 - - description: PLLI2SDIVQ = /29 - name: Div29 - value: 28 - - description: PLLI2SDIVQ = /30 - name: Div30 - value: 29 - - description: PLLI2SDIVQ = /31 - name: Div31 - value: 30 - - description: PLLI2SDIVQ = /32 - name: Div32 - value: 31 -enum/PLLISP: - bit_size: 2 - variants: - - description: PLL*P=2 - name: Div2 - value: 0 - - description: PLL*P=4 - name: Div4 - value: 1 - - description: PLL*P=6 - name: Div6 - value: 2 - - description: PLL*P=8 - name: Div8 - value: 3 -enum/PLLP: - bit_size: 2 - variants: - - description: PLLP=2 - name: Div2 - value: 0 - - description: PLLP=4 - name: Div4 - value: 1 - - description: PLLP=6 - name: Div6 - value: 2 - - description: PLLP=8 - name: Div8 - value: 3 -enum/PLLSAIDIVQ: - bit_size: 5 - variants: - - description: PLLSAIDIVQ = /1 - name: Div1 - value: 0 - - description: PLLSAIDIVQ = /2 - name: Div2 - value: 1 - - description: PLLSAIDIVQ = /3 - name: Div3 - value: 2 - - description: PLLSAIDIVQ = /4 - name: Div4 - value: 3 - - description: PLLSAIDIVQ = /5 - name: Div5 - value: 4 - - description: PLLSAIDIVQ = /6 - name: Div6 - value: 5 - - description: PLLSAIDIVQ = /7 - name: Div7 - value: 6 - - description: PLLSAIDIVQ = /8 - name: Div8 - value: 7 - - description: PLLSAIDIVQ = /9 - name: Div9 - value: 8 - - description: PLLSAIDIVQ = /10 - name: Div10 - value: 9 - - description: PLLSAIDIVQ = /11 - name: Div11 - value: 10 - - description: PLLSAIDIVQ = /12 - name: Div12 - value: 11 - - description: PLLSAIDIVQ = /13 - name: Div13 - value: 12 - - description: PLLSAIDIVQ = /14 - name: Div14 - value: 13 - - description: PLLSAIDIVQ = /15 - name: Div15 - value: 14 - - description: PLLSAIDIVQ = /16 - name: Div16 - value: 15 - - description: PLLSAIDIVQ = /17 - name: Div17 - value: 16 - - description: PLLSAIDIVQ = /18 - name: Div18 - value: 17 - - description: PLLSAIDIVQ = /19 - name: Div19 - value: 18 - - description: PLLSAIDIVQ = /20 - name: Div20 - value: 19 - - description: PLLSAIDIVQ = /21 - name: Div21 - value: 20 - - description: PLLSAIDIVQ = /22 - name: Div22 - value: 21 - - description: PLLSAIDIVQ = /23 - name: Div23 - value: 22 - - description: PLLSAIDIVQ = /24 - name: Div24 - value: 23 - - description: PLLSAIDIVQ = /25 - name: Div25 - value: 24 - - description: PLLSAIDIVQ = /26 - name: Div26 - value: 25 - - description: PLLSAIDIVQ = /27 - name: Div27 - value: 26 - - description: PLLSAIDIVQ = /28 - name: Div28 - value: 27 - - description: PLLSAIDIVQ = /29 - name: Div29 - value: 28 - - description: PLLSAIDIVQ = /30 - name: Div30 - value: 29 - - description: PLLSAIDIVQ = /31 - name: Div31 - value: 30 - - description: PLLSAIDIVQ = /32 - name: Div32 - value: 31 -enum/PLLSAIDIVR: - bit_size: 2 - variants: - - description: PLLSAIDIVR = /2 - name: Div2 - value: 0 - - description: PLLSAIDIVR = /4 - name: Div4 - value: 1 - - description: PLLSAIDIVR = /8 - name: Div8 - value: 2 - - description: PLLSAIDIVR = /16 - name: Div16 - value: 3 -enum/PLLSAIP: - bit_size: 2 - variants: - - description: PLL*P=2 - name: Div2 - value: 0 - - description: PLL*P=4 - name: Div4 - value: 1 - - description: PLL*P=6 - name: Div6 - value: 2 - - description: PLL*P=8 - name: Div8 - value: 3 -enum/PLLSRC: - bit_size: 1 - variants: - - description: HSI clock selected as PLL and PLLI2S clock entry - name: HSI - value: 0 - - description: HSE oscillator clock selected as PLL and PLLI2S clock entry - name: HSE - value: 1 -enum/PPRE: - bit_size: 3 - variants: - - description: HCLK not divided - name: Div1 - value: 0 - - description: HCLK divided by 2 - name: Div2 - value: 4 - - description: HCLK divided by 4 - name: Div4 - value: 5 - - description: HCLK divided by 8 - name: Div8 - value: 6 - - description: HCLK divided by 16 - name: Div16 - value: 7 -enum/RMVFW: - bit_size: 1 - variants: - - description: Clears the reset flag - name: Clear - value: 1 -enum/RTCSEL: - bit_size: 2 - variants: - - description: No clock - name: NoClock - value: 0 - - description: LSE oscillator clock used as RTC clock - name: LSE - value: 1 - - description: LSI oscillator clock used as RTC clock - name: LSI - value: 2 - - description: HSE oscillator clock divided by a prescaler used as RTC clock - name: HSE - value: 3 -enum/SAISEL: - bit_size: 2 - variants: - - description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - name: PLLSAI - value: 0 - - description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - name: PLLI2S - value: 1 - - description: SAI2 clock frequency = Alternate function input frequency - name: AFIF - value: 2 - - description: SAI2 clock frequency = HSI or HSE - name: HSI_HSE - value: 3 -enum/SDMMCSEL: - bit_size: 1 - variants: - - description: 48 MHz clock is selected as SD clock - name: CK48M - value: 0 - - description: System clock is selected as SD clock - name: SYSCLK - value: 1 -enum/SPREADSEL: - bit_size: 1 - variants: - - description: Center spread - name: Center - value: 0 - - description: Down spread - name: Down - value: 1 -enum/SW: - bit_size: 2 - variants: - - description: HSI selected as system clock - name: HSI - value: 0 - - description: HSE selected as system clock - name: HSE - value: 1 - - description: PLL selected as system clock - name: PLL - value: 2 -enum/SWSR: - bit_size: 2 - variants: - - description: HSI oscillator used as system clock - name: HSI - value: 0 - - description: HSE oscillator used as system clock - name: HSE - value: 1 - - description: PLL used as system clock - name: PLL - value: 2 -enum/TIMPRE: - bit_size: 1 - variants: - - description: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, - TIMxCLK = 2xPCLKx - name: Mul2 - value: 0 - - description: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, - TIMxCLK = 4xPCLKx - name: Mul4 - value: 1 -enum/USART1SEL: - bit_size: 2 - variants: - - description: APB2 clock (PCLK2) is selected as USART clock - name: APB2 - value: 0 - - description: System clock is selected as USART clock - name: SYSCLK - value: 1 - - description: HSI clock is selected as USART clock - name: HSI - value: 2 - - description: LSE clock is selected as USART clock - name: LSE - value: 3 -enum/USART2SEL: - bit_size: 2 - variants: - - description: APB1 clock (PCLK1) is selected as USART clock - name: APB1 - value: 0 - - description: System clock is selected as USART clock - name: SYSCLK - value: 1 - - description: HSI clock is selected as USART clock - name: HSI - value: 2 - - description: LSE clock is selected as USART clock - name: LSE - value: 3 + - name: CR + description: clock control register + byte_offset: 0 + fieldset: CR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 4 + fieldset: PLLCFGR + - name: CFGR + description: clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: CIR + description: clock interrupt register + byte_offset: 12 + fieldset: CIR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 16 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 20 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 24 + fieldset: AHB3RSTR + - name: APB1RSTR + description: APB1 peripheral reset register + byte_offset: 32 + fieldset: APB1RSTR + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 36 + fieldset: APB2RSTR + - name: AHB1ENR + description: AHB1 peripheral clock register + byte_offset: 48 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 52 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 56 + fieldset: AHB3ENR + - name: APB1ENR + description: APB1 peripheral clock enable register + byte_offset: 64 + fieldset: APB1ENR + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 68 + fieldset: APB2ENR + - name: AHB1LPENR + description: AHB1 peripheral clock enable in low power mode register + byte_offset: 80 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: AHB2 peripheral clock enable in low power mode register + byte_offset: 84 + fieldset: AHB2LPENR + - name: AHB3LPENR + description: AHB3 peripheral clock enable in low power mode register + byte_offset: 88 + fieldset: AHB3LPENR + - name: APB1LPENR + description: APB1 peripheral clock enable in low power mode register + byte_offset: 96 + fieldset: APB1LPENR + - name: APB2LPENR + description: APB2 peripheral clock enabled in low power mode register + byte_offset: 100 + fieldset: APB2LPENR + - name: BDCR + description: Backup domain control register + byte_offset: 112 + fieldset: BDCR + - name: CSR + description: clock control & status register + byte_offset: 116 + fieldset: CSR + - name: SSCGR + description: spread spectrum clock generation register + byte_offset: 128 + fieldset: SSCGR + - name: PLLI2SCFGR + description: PLLI2S configuration register + byte_offset: 132 + fieldset: PLLI2SCFGR + - name: PLLSAICFGR + description: PLL configuration register + byte_offset: 136 + fieldset: PLLSAICFGR + - name: DCKCFGR1 + description: dedicated clocks configuration register + byte_offset: 140 + fieldset: DCKCFGR1 + - name: DCKCFGR2 + description: dedicated clocks configuration register + byte_offset: 144 + fieldset: DCKCFGR2 fieldset/AHB1ENR: description: AHB1 peripheral clock register fields: - - bit_offset: 0 - bit_size: 1 - description: IO port A clock enable - name: GPIOAEN - - bit_offset: 1 - bit_size: 1 - description: IO port B clock enable - name: GPIOBEN - - bit_offset: 2 - bit_size: 1 - description: IO port C clock enable - name: GPIOCEN - - bit_offset: 3 - bit_size: 1 - description: IO port D clock enable - name: GPIODEN - - bit_offset: 4 - bit_size: 1 - description: IO port E clock enable - name: GPIOEEN - - bit_offset: 5 - bit_size: 1 - description: IO port F clock enable - name: GPIOFEN - - bit_offset: 6 - bit_size: 1 - description: IO port G clock enable - name: GPIOGEN - - bit_offset: 7 - bit_size: 1 - description: IO port H clock enable - name: GPIOHEN - - bit_offset: 8 - bit_size: 1 - description: IO port I clock enable - name: GPIOIEN - - bit_offset: 9 - bit_size: 1 - description: IO port J clock enable - name: GPIOJEN - - bit_offset: 10 - bit_size: 1 - description: IO port K clock enable - name: GPIOKEN - - bit_offset: 12 - bit_size: 1 - description: CRC clock enable - name: CRCEN - - bit_offset: 18 - bit_size: 1 - description: Backup SRAM interface clock enable - name: BKPSRAMEN - - bit_offset: 20 - bit_size: 1 - description: CCM data RAM clock enable - name: DTCMRAMEN - - bit_offset: 21 - bit_size: 1 - description: DMA1 clock enable - name: DMA1EN - - bit_offset: 22 - bit_size: 1 - description: DMA2 clock enable - name: DMA2EN - - bit_offset: 23 - bit_size: 1 - description: DMA2D clock enable - name: DMA2DEN - - bit_offset: 25 - bit_size: 1 - description: Ethernet MAC clock enable - name: ETHEN - - bit_offset: 26 - bit_size: 1 - description: Ethernet Transmission clock enable - name: ETHTXEN - - bit_offset: 27 - bit_size: 1 - description: Ethernet Reception clock enable - name: ETHRXEN - - bit_offset: 28 - bit_size: 1 - description: Ethernet PTP clock enable - name: ETHPTPEN - - bit_offset: 29 - bit_size: 1 - description: USB OTG HS clock enable - name: USB_OTG_HSEN - - bit_offset: 30 - bit_size: 1 - description: USB OTG HSULPI clock enable - name: USB_OTG_HSULPIEN + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: IO port F clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: IO port I clock enable + bit_offset: 8 + bit_size: 1 + - name: GPIOJEN + description: IO port J clock enable + bit_offset: 9 + bit_size: 1 + - name: GPIOKEN + description: IO port K clock enable + bit_offset: 10 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: BKPSRAMEN + description: Backup SRAM interface clock enable + bit_offset: 18 + bit_size: 1 + - name: DTCMRAMEN + description: CCM data RAM clock enable + bit_offset: 20 + bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 21 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 22 + bit_size: 1 + - name: DMA2DEN + description: DMA2D clock enable + bit_offset: 23 + bit_size: 1 + - name: ETHEN + description: Ethernet MAC clock enable + bit_offset: 25 + bit_size: 1 + - name: ETHTXEN + description: Ethernet Transmission clock enable + bit_offset: 26 + bit_size: 1 + - name: ETHRXEN + description: Ethernet Reception clock enable + bit_offset: 27 + bit_size: 1 + - name: ETHPTPEN + description: Ethernet PTP clock enable + bit_offset: 28 + bit_size: 1 + - name: USB_OTG_HSEN + description: USB OTG HS clock enable + bit_offset: 29 + bit_size: 1 + - name: USB_OTG_HSULPIEN + description: USB OTG HSULPI clock enable + bit_offset: 30 + bit_size: 1 fieldset/AHB1LPENR: description: AHB1 peripheral clock enable in low power mode register fields: - - bit_offset: 0 - bit_size: 1 - description: IO port A clock enable during sleep mode - name: GPIOALPEN - - bit_offset: 1 - bit_size: 1 - description: IO port B clock enable during Sleep mode - name: GPIOBLPEN - - bit_offset: 2 - bit_size: 1 - description: IO port C clock enable during Sleep mode - name: GPIOCLPEN - - bit_offset: 3 - bit_size: 1 - description: IO port D clock enable during Sleep mode - name: GPIODLPEN - - bit_offset: 4 - bit_size: 1 - description: IO port E clock enable during Sleep mode - name: GPIOELPEN - - bit_offset: 5 - bit_size: 1 - description: IO port F clock enable during Sleep mode - name: GPIOFLPEN - - bit_offset: 6 - bit_size: 1 - description: IO port G clock enable during Sleep mode - name: GPIOGLPEN - - bit_offset: 7 - bit_size: 1 - description: IO port H clock enable during Sleep mode - name: GPIOHLPEN - - bit_offset: 8 - bit_size: 1 - description: IO port I clock enable during Sleep mode - name: GPIOILPEN - - bit_offset: 9 - bit_size: 1 - description: IO port J clock enable during Sleep mode - name: GPIOJLPEN - - bit_offset: 10 - bit_size: 1 - description: IO port K clock enable during Sleep mode - name: GPIOKLPEN - - bit_offset: 12 - bit_size: 1 - description: CRC clock enable during Sleep mode - name: CRCLPEN - - bit_offset: 13 - bit_size: 1 - description: AXI to AHB bridge clock enable during Sleep mode - name: AXILPEN - - bit_offset: 15 - bit_size: 1 - description: Flash interface clock enable during Sleep mode - name: FLITFLPEN - - bit_offset: 16 - bit_size: 1 - description: SRAM 1interface clock enable during Sleep mode - name: SRAM1LPEN - - bit_offset: 17 - bit_size: 1 - description: SRAM 2 interface clock enable during Sleep mode - name: SRAM2LPEN - - bit_offset: 18 - bit_size: 1 - description: Backup SRAM interface clock enable during Sleep mode - name: BKPSRAMLPEN - - bit_offset: 19 - bit_size: 1 - description: SRAM 3 interface clock enable during Sleep mode - name: SRAM3LPEN - - bit_offset: 20 - bit_size: 1 - description: DTCM RAM interface clock enable during Sleep mode - name: DTCMLPEN - - bit_offset: 21 - bit_size: 1 - description: DMA1 clock enable during Sleep mode - name: DMA1LPEN - - bit_offset: 22 - bit_size: 1 - description: DMA2 clock enable during Sleep mode - name: DMA2LPEN - - bit_offset: 23 - bit_size: 1 - description: DMA2D clock enable during Sleep mode - name: DMA2DLPEN - - bit_offset: 25 - bit_size: 1 - description: Ethernet MAC clock enable during Sleep mode - name: ETHLPEN - - bit_offset: 26 - bit_size: 1 - description: Ethernet transmission clock enable during Sleep mode - name: ETHTXLPEN - - bit_offset: 27 - bit_size: 1 - description: Ethernet reception clock enable during Sleep mode - name: ETHRXLPEN - - bit_offset: 28 - bit_size: 1 - description: Ethernet PTP clock enable during Sleep mode - name: ETHPTPLPEN - - bit_offset: 29 - bit_size: 1 - description: USB OTG HS clock enable during Sleep mode - name: USB_OTG_HSLPEN - - bit_offset: 30 - bit_size: 1 - description: USB OTG HS ULPI clock enable during Sleep mode - name: USB_OTG_HSULPILPEN + - name: GPIOALPEN + description: IO port A clock enable during sleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: IO port B clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: IO port C clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: IO port D clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: IO port E clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: GPIOFLPEN + description: IO port F clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: IO port G clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: GPIOHLPEN + description: IO port H clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: GPIOILPEN + description: IO port I clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: GPIOJLPEN + description: IO port J clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: GPIOKLPEN + description: IO port K clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 + - name: CRCLPEN + description: CRC clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: AXILPEN + description: AXI to AHB bridge clock enable during Sleep mode + bit_offset: 13 + bit_size: 1 + - name: FLITFLPEN + description: Flash interface clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: SRAM1LPEN + description: SRAM 1interface clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: SRAM2LPEN + description: SRAM 2 interface clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: BKPSRAMLPEN + description: Backup SRAM interface clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: SRAM3LPEN + description: SRAM 3 interface clock enable during Sleep mode + bit_offset: 19 + bit_size: 1 + - name: DTCMLPEN + description: DTCM RAM interface clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: DMA1LPEN + description: DMA1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: DMA2DLPEN + description: DMA2D clock enable during Sleep mode + bit_offset: 23 + bit_size: 1 + - name: ETHLPEN + description: Ethernet MAC clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: ETHTXLPEN + description: Ethernet transmission clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: ETHRXLPEN + description: Ethernet reception clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: ETHPTPLPEN + description: Ethernet PTP clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: USB_OTG_HSLPEN + description: USB OTG HS clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: USB_OTG_HSULPILPEN + description: USB OTG HS ULPI clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: IO port A reset - name: GPIOARST - - bit_offset: 1 - bit_size: 1 - description: IO port B reset - name: GPIOBRST - - bit_offset: 2 - bit_size: 1 - description: IO port C reset - name: GPIOCRST - - bit_offset: 3 - bit_size: 1 - description: IO port D reset - name: GPIODRST - - bit_offset: 4 - bit_size: 1 - description: IO port E reset - name: GPIOERST - - bit_offset: 5 - bit_size: 1 - description: IO port F reset - name: GPIOFRST - - bit_offset: 6 - bit_size: 1 - description: IO port G reset - name: GPIOGRST - - bit_offset: 7 - bit_size: 1 - description: IO port H reset - name: GPIOHRST - - bit_offset: 8 - bit_size: 1 - description: IO port I reset - name: GPIOIRST - - bit_offset: 9 - bit_size: 1 - description: IO port J reset - name: GPIOJRST - - bit_offset: 10 - bit_size: 1 - description: IO port K reset - name: GPIOKRST - - bit_offset: 12 - bit_size: 1 - description: CRC reset - name: CRCRST - - bit_offset: 21 - bit_size: 1 - description: DMA2 reset - name: DMA1RST - - bit_offset: 22 - bit_size: 1 - description: DMA2 reset - name: DMA2RST - - bit_offset: 23 - bit_size: 1 - description: DMA2D reset - name: DMA2DRST - - bit_offset: 25 - bit_size: 1 - description: Ethernet MAC reset - name: ETHRST - - bit_offset: 29 - bit_size: 1 - description: USB OTG HS module reset - name: USB_OTG_HSRST + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 + - name: GPIOIRST + description: IO port I reset + bit_offset: 8 + bit_size: 1 + - name: GPIOJRST + description: IO port J reset + bit_offset: 9 + bit_size: 1 + - name: GPIOKRST + description: IO port K reset + bit_offset: 10 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: DMA1RST + description: DMA2 reset + bit_offset: 21 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 22 + bit_size: 1 + - name: DMA2DRST + description: DMA2D reset + bit_offset: 23 + bit_size: 1 + - name: ETHRST + description: Ethernet MAC reset + bit_offset: 25 + bit_size: 1 + - name: USB_OTG_HSRST + description: USB OTG HS module reset + bit_offset: 29 + bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: Camera interface enable - name: DCMIEN - - bit_offset: 1 - bit_size: 1 - description: JPEG enable - name: JPEGEN - - bit_offset: 4 - bit_size: 1 - description: AES module clock enable - name: AESEN - - bit_offset: 4 - bit_size: 1 - description: Cryptographic modules clock enable - name: CRYPEN - - bit_offset: 5 - bit_size: 1 - description: Hash modules clock enable - name: HASHEN - - bit_offset: 6 - bit_size: 1 - description: Random number generator clock enable - name: RNGEN - - bit_offset: 7 - bit_size: 1 - description: USB OTG FS clock enable - name: USB_OTG_FSEN + - name: DCMIEN + description: Camera interface enable + bit_offset: 0 + bit_size: 1 + - name: JPEGEN + description: JPEG enable + bit_offset: 1 + bit_size: 1 + - name: AESEN + description: AES module clock enable + bit_offset: 4 + bit_size: 1 + - name: CRYPEN + description: Cryptographic modules clock enable + bit_offset: 4 + bit_size: 1 + - name: HASHEN + description: Hash modules clock enable + bit_offset: 5 + bit_size: 1 + - name: RNGEN + description: Random number generator clock enable + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSEN + description: USB OTG FS clock enable + bit_offset: 7 + bit_size: 1 fieldset/AHB2LPENR: description: AHB2 peripheral clock enable in low power mode register fields: - - bit_offset: 0 - bit_size: 1 - description: Camera interface enable during Sleep mode - name: DCMILPEN - - bit_offset: 1 - bit_size: 1 - description: JPEG module enabled during Sleep mode - name: JPEGLPEN - - bit_offset: 4 - bit_size: 1 - description: AES module clock enable during Sleep mode - name: AESLPEN - - bit_offset: 4 - bit_size: 1 - description: Cryptography modules clock enable during Sleep mode - name: CRYPLPEN - - bit_offset: 5 - bit_size: 1 - description: Hash modules clock enable during Sleep mode - name: HASHLPEN - - bit_offset: 6 - bit_size: 1 - description: Random number generator clock enable during Sleep mode - name: RNGLPEN - - bit_offset: 7 - bit_size: 1 - description: USB OTG FS clock enable during Sleep mode - name: USB_OTG_FSLPEN + - name: DCMILPEN + description: Camera interface enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: JPEGLPEN + description: JPEG module enabled during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: AESLPEN + description: AES module clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: CRYPLPEN + description: Cryptography modules clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: HASHLPEN + description: Hash modules clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: RNGLPEN + description: Random number generator clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSLPEN + description: USB OTG FS clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: Camera interface reset - name: DCMIRST - - bit_offset: 4 - bit_size: 1 - description: AES module reset - name: AESRST - - bit_offset: 4 - bit_size: 1 - description: Cryptographic module reset - name: CRYPRST - - bit_offset: 5 - bit_size: 1 - description: Hash module reset - name: HSAHRST - - bit_offset: 6 - bit_size: 1 - description: Random number generator module reset - name: RNGRST - - bit_offset: 7 - bit_size: 1 - description: USB OTG FS module reset - name: USB_OTG_FSRST + - name: DCMIRST + description: Camera interface reset + bit_offset: 0 + bit_size: 1 + - name: AESRST + description: AES module reset + bit_offset: 4 + bit_size: 1 + - name: CRYPRST + description: Cryptographic module reset + bit_offset: 4 + bit_size: 1 + - name: HSAHRST + description: Hash module reset + bit_offset: 5 + bit_size: 1 + - name: RNGRST + description: Random number generator module reset + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSRST + description: USB OTG FS module reset + bit_offset: 7 + bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: Flexible memory controller module clock enable - name: FMCEN - - bit_offset: 1 - bit_size: 1 - description: Quad SPI memory controller clock enable - name: QUADSPIEN + - name: FMCEN + description: Flexible memory controller module clock enable + bit_offset: 0 + bit_size: 1 + - name: QUADSPIEN + description: Quad SPI memory controller clock enable + bit_offset: 1 + bit_size: 1 fieldset/AHB3LPENR: description: AHB3 peripheral clock enable in low power mode register fields: - - bit_offset: 0 - bit_size: 1 - description: Flexible memory controller module clock enable during Sleep mode - name: FMCLPEN - - bit_offset: 1 - bit_size: 1 - description: Quand SPI memory controller clock enable during Sleep mode - name: QUADSPILPEN + - name: FMCLPEN + description: Flexible memory controller module clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: QUADSPILPEN + description: Quand SPI memory controller clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: Flexible memory controller module reset - name: FMCRST - - bit_offset: 1 - bit_size: 1 - description: Quad SPI memory controller reset - name: QUADSPIRST + - name: FMCRST + description: Flexible memory controller module reset + bit_offset: 0 + bit_size: 1 + - name: QUADSPIRST + description: Quad SPI memory controller reset + bit_offset: 1 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 clock enable - name: TIM2EN - - bit_offset: 1 - bit_size: 1 - description: TIM3 clock enable - name: TIM3EN - - bit_offset: 2 - bit_size: 1 - description: TIM4 clock enable - name: TIM4EN - - bit_offset: 3 - bit_size: 1 - description: TIM5 clock enable - name: TIM5EN - - bit_offset: 4 - bit_size: 1 - description: TIM6 clock enable - name: TIM6EN - - bit_offset: 5 - bit_size: 1 - description: TIM7 clock enable - name: TIM7EN - - bit_offset: 6 - bit_size: 1 - description: TIM12 clock enable - name: TIM12EN - - bit_offset: 7 - bit_size: 1 - description: TIM13 clock enable - name: TIM13EN - - bit_offset: 8 - bit_size: 1 - description: TIM14 clock enable - name: TIM14EN - - bit_offset: 9 - bit_size: 1 - description: Low power timer 1 clock enable - name: LPTIM1EN - - bit_offset: 10 - bit_size: 1 - description: RTCAPB clock enable - name: RTCEN - - bit_offset: 11 - bit_size: 1 - description: Window watchdog clock enable - name: WWDGEN - - bit_offset: 13 - bit_size: 1 - description: CAN 3 enable - name: CAN3EN - - bit_offset: 14 - bit_size: 1 - description: SPI2 clock enable - name: SPI2EN - - bit_offset: 15 - bit_size: 1 - description: SPI3 clock enable - name: SPI3EN - - bit_offset: 16 - bit_size: 1 - description: SPDIF-RX clock enable - name: SPDIFRXEN - - bit_offset: 17 - bit_size: 1 - description: USART 2 clock enable - name: USART2EN - - bit_offset: 18 - bit_size: 1 - description: USART3 clock enable - name: USART3EN - - bit_offset: 19 - bit_size: 1 - description: UART4 clock enable - name: UART4EN - - bit_offset: 20 - bit_size: 1 - description: UART5 clock enable - name: UART5EN - - bit_offset: 21 - bit_size: 1 - description: I2C1 clock enable - name: I2C1EN - - bit_offset: 22 - bit_size: 1 - description: I2C2 clock enable - name: I2C2EN - - bit_offset: 23 - bit_size: 1 - description: I2C3 clock enable - name: I2C3EN - - bit_offset: 24 - bit_size: 1 - description: I2C4 clock enable - name: I2C4EN - - bit_offset: 25 - bit_size: 1 - description: CAN 1 clock enable - name: CAN1EN - - bit_offset: 26 - bit_size: 1 - description: CAN 2 clock enable - name: CAN2EN - - bit_offset: 27 - bit_size: 1 - description: HDMI-CEN clock enable - name: CECEN - - bit_offset: 28 - bit_size: 1 - description: Power interface clock enable - name: PWREN - - bit_offset: 29 - bit_size: 1 - description: DAC interface clock enable - name: DACEN - - bit_offset: 30 - bit_size: 1 - description: UART7 clock enable - name: UART7EN - - bit_offset: 31 - bit_size: 1 - description: UART8 clock enable - name: UART8EN + - name: TIM2EN + description: TIM2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: TIM12 clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: TIM13 clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: TIM14 clock enable + bit_offset: 8 + bit_size: 1 + - name: LPTIM1EN + description: Low power timer 1 clock enable + bit_offset: 9 + bit_size: 1 + - name: RTCEN + description: RTCAPB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: CAN3EN + description: CAN 3 enable + bit_offset: 13 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 clock enable + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXEN + description: SPDIF-RX clock enable + bit_offset: 16 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 23 + bit_size: 1 + - name: I2C4EN + description: I2C4 clock enable + bit_offset: 24 + bit_size: 1 + - name: CAN1EN + description: CAN 1 clock enable + bit_offset: 25 + bit_size: 1 + - name: CAN2EN + description: CAN 2 clock enable + bit_offset: 26 + bit_size: 1 + - name: CECEN + description: HDMI-CEN clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: UART7EN + description: UART7 clock enable + bit_offset: 30 + bit_size: 1 + - name: UART8EN + description: UART8 clock enable + bit_offset: 31 + bit_size: 1 fieldset/APB1LPENR: description: APB1 peripheral clock enable in low power mode register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 clock enable during Sleep mode - name: TIM2LPEN - - bit_offset: 1 - bit_size: 1 - description: TIM3 clock enable during Sleep mode - name: TIM3LPEN - - bit_offset: 2 - bit_size: 1 - description: TIM4 clock enable during Sleep mode - name: TIM4LPEN - - bit_offset: 3 - bit_size: 1 - description: TIM5 clock enable during Sleep mode - name: TIM5LPEN - - bit_offset: 4 - bit_size: 1 - description: TIM6 clock enable during Sleep mode - name: TIM6LPEN - - bit_offset: 5 - bit_size: 1 - description: TIM7 clock enable during Sleep mode - name: TIM7LPEN - - bit_offset: 6 - bit_size: 1 - description: TIM12 clock enable during Sleep mode - name: TIM12LPEN - - bit_offset: 7 - bit_size: 1 - description: TIM13 clock enable during Sleep mode - name: TIM13LPEN - - bit_offset: 8 - bit_size: 1 - description: TIM14 clock enable during Sleep mode - name: TIM14LPEN - - bit_offset: 9 - bit_size: 1 - description: low power timer 1 clock enable during Sleep mode - name: LPTIM1LPEN - - bit_offset: 10 - bit_size: 1 - description: RTCAPB clock enable during Sleep mode - name: RTCLPEN - - bit_offset: 11 - bit_size: 1 - description: Window watchdog clock enable during Sleep mode - name: WWDGLPEN - - bit_offset: 13 - bit_size: 1 - description: CAN 3 clock enable during Sleep mode - name: CAN3LPEN - - bit_offset: 14 - bit_size: 1 - description: SPI2 clock enable during Sleep mode - name: SPI2LPEN - - bit_offset: 15 - bit_size: 1 - description: SPI3 clock enable during Sleep mode - name: SPI3LPEN - - bit_offset: 16 - bit_size: 1 - description: SPDIF-RX clock enable during sleep mode - name: SPDIFRXLPEN - - bit_offset: 17 - bit_size: 1 - description: USART2 clock enable during Sleep mode - name: USART2LPEN - - bit_offset: 18 - bit_size: 1 - description: USART3 clock enable during Sleep mode - name: USART3LPEN - - bit_offset: 19 - bit_size: 1 - description: UART4 clock enable during Sleep mode - name: UART4LPEN - - bit_offset: 20 - bit_size: 1 - description: UART5 clock enable during Sleep mode - name: UART5LPEN - - bit_offset: 21 - bit_size: 1 - description: I2C1 clock enable during Sleep mode - name: I2C1LPEN - - bit_offset: 22 - bit_size: 1 - description: I2C2 clock enable during Sleep mode - name: I2C2LPEN - - bit_offset: 23 - bit_size: 1 - description: I2C3 clock enable during Sleep mode - name: I2C3LPEN - - bit_offset: 24 - bit_size: 1 - description: I2C4 clock enable during Sleep mode - name: I2C4LPEN - - bit_offset: 25 - bit_size: 1 - description: CAN 1 clock enable during Sleep mode - name: CAN1LPEN - - bit_offset: 26 - bit_size: 1 - description: CAN 2 clock enable during Sleep mode - name: CAN2LPEN - - bit_offset: 27 - bit_size: 1 - description: HDMI-CEN clock enable during Sleep mode - name: CECLPEN - - bit_offset: 28 - bit_size: 1 - description: Power interface clock enable during Sleep mode - name: PWRLPEN - - bit_offset: 29 - bit_size: 1 - description: DAC interface clock enable during Sleep mode - name: DACLPEN - - bit_offset: 30 - bit_size: 1 - description: UART7 clock enable during Sleep mode - name: UART7LPEN - - bit_offset: 31 - bit_size: 1 - description: UART8 clock enable during Sleep mode - name: UART8LPEN + - name: TIM2LPEN + description: TIM2 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: TIM3 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: TIM4 clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: TIM5 clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: TIM6 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: TIM7 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: TIM12LPEN + description: TIM12 clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: TIM13LPEN + description: TIM13 clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: TIM14LPEN + description: TIM14 clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: LPTIM1LPEN + description: low power timer 1 clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: RTCLPEN + description: RTCAPB clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 + - name: WWDGLPEN + description: Window watchdog clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: CAN3LPEN + description: CAN 3 clock enable during Sleep mode + bit_offset: 13 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: SPI3 clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXLPEN + description: SPDIF-RX clock enable during sleep mode + bit_offset: 16 + bit_size: 1 + - name: USART2LPEN + description: USART2 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: USART3 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: UART4 clock enable during Sleep mode + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: UART5 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: I2C1LPEN + description: I2C1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: I2C3LPEN + description: I2C3 clock enable during Sleep mode + bit_offset: 23 + bit_size: 1 + - name: I2C4LPEN + description: I2C4 clock enable during Sleep mode + bit_offset: 24 + bit_size: 1 + - name: CAN1LPEN + description: CAN 1 clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: CAN2LPEN + description: CAN 2 clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: CECLPEN + description: HDMI-CEN clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: PWRLPEN + description: Power interface clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: DACLPEN + description: DAC interface clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: UART7LPEN + description: UART7 clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 + - name: UART8LPEN + description: UART8 clock enable during Sleep mode + bit_offset: 31 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 reset - name: TIM2RST - - bit_offset: 1 - bit_size: 1 - description: TIM3 reset - name: TIM3RST - - bit_offset: 2 - bit_size: 1 - description: TIM4 reset - name: TIM4RST - - bit_offset: 3 - bit_size: 1 - description: TIM5 reset - name: TIM5RST - - bit_offset: 4 - bit_size: 1 - description: TIM6 reset - name: TIM6RST - - bit_offset: 5 - bit_size: 1 - description: TIM7 reset - name: TIM7RST - - bit_offset: 6 - bit_size: 1 - description: TIM12 reset - name: TIM12RST - - bit_offset: 7 - bit_size: 1 - description: TIM13 reset - name: TIM13RST - - bit_offset: 8 - bit_size: 1 - description: TIM14 reset - name: TIM14RST - - bit_offset: 9 - bit_size: 1 - description: Low power timer 1 reset - name: LPTIM1RST - - bit_offset: 11 - bit_size: 1 - description: Window watchdog reset - name: WWDGRST - - bit_offset: 13 - bit_size: 1 - description: CAN 3 reset - name: CAN3RST - - bit_offset: 14 - bit_size: 1 - description: SPI 2 reset - name: SPI2RST - - bit_offset: 15 - bit_size: 1 - description: SPI 3 reset - name: SPI3RST - - bit_offset: 16 - bit_size: 1 - description: SPDIF-RX reset - name: SPDIFRXRST - - bit_offset: 17 - bit_size: 1 - description: USART 2 reset - name: USART2RST - - bit_offset: 18 - bit_size: 1 - description: USART 3 reset - name: USART3RST - - bit_offset: 19 - bit_size: 1 - description: USART 4 reset - name: UART4RST - - bit_offset: 20 - bit_size: 1 - description: USART 5 reset - name: UART5RST - - bit_offset: 21 - bit_size: 1 - description: I2C 1 reset - name: I2C1RST - - bit_offset: 22 - bit_size: 1 - description: I2C 2 reset - name: I2C2RST - - bit_offset: 23 - bit_size: 1 - description: I2C3 reset - name: I2C3RST - - bit_offset: 24 - bit_size: 1 - description: I2C 4 reset - name: I2C4RST - - bit_offset: 25 - bit_size: 1 - description: CAN1 reset - name: CAN1RST - - bit_offset: 26 - bit_size: 1 - description: CAN2 reset - name: CAN2RST - - bit_offset: 27 - bit_size: 1 - description: HDMI-CEC reset - name: CECRST - - bit_offset: 28 - bit_size: 1 - description: Power interface reset - name: PWRRST - - bit_offset: 29 - bit_size: 1 - description: DAC reset - name: DACRST - - bit_offset: 30 - bit_size: 1 - description: UART7 reset - name: UART7RST - - bit_offset: 31 - bit_size: 1 - description: UART8 reset - name: UART8RST + - name: TIM2RST + description: TIM2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM4 reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: TIM12 reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: TIM13 reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: TIM14 reset + bit_offset: 8 + bit_size: 1 + - name: LPTIM1RST + description: Low power timer 1 reset + bit_offset: 9 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: CAN3RST + description: CAN 3 reset + bit_offset: 13 + bit_size: 1 + - name: SPI2RST + description: SPI 2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI 3 reset + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXRST + description: SPDIF-RX reset + bit_offset: 16 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART 3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: USART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: USART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C 1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C 2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: I2C4RST + description: I2C 4 reset + bit_offset: 24 + bit_size: 1 + - name: CAN1RST + description: CAN1 reset + bit_offset: 25 + bit_size: 1 + - name: CAN2RST + description: CAN2 reset + bit_offset: 26 + bit_size: 1 + - name: CECRST + description: HDMI-CEC reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC reset + bit_offset: 29 + bit_size: 1 + - name: UART7RST + description: UART7 reset + bit_offset: 30 + bit_size: 1 + - name: UART8RST + description: UART8 reset + bit_offset: 31 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM1 clock enable - name: TIM1EN - - bit_offset: 1 - bit_size: 1 - description: TIM8 clock enable - name: TIM8EN - - bit_offset: 4 - bit_size: 1 - description: USART1 clock enable - name: USART1EN - - bit_offset: 5 - bit_size: 1 - description: USART6 clock enable - name: USART6EN - - bit_offset: 7 - bit_size: 1 - description: SDMMC2 clock enable - name: SDMMC2EN - - bit_offset: 8 - bit_size: 1 - description: ADC1 clock enable - name: ADC1EN - - bit_offset: 9 - bit_size: 1 - description: ADC2 clock enable - name: ADC2EN - - bit_offset: 10 - bit_size: 1 - description: ADC3 clock enable - name: ADC3EN - - bit_offset: 11 - bit_size: 1 - description: SDMMC1 clock enable - name: SDMMC1EN - - bit_offset: 12 - bit_size: 1 - description: SPI1 clock enable - name: SPI1EN - - bit_offset: 13 - bit_size: 1 - description: SPI4 clock enable - name: SPI4EN - - bit_offset: 14 - bit_size: 1 - description: System configuration controller clock enable - name: SYSCFGEN - - bit_offset: 16 - bit_size: 1 - description: TIM9 clock enable - name: TIM9EN - - bit_offset: 17 - bit_size: 1 - description: TIM10 clock enable - name: TIM10EN - - bit_offset: 18 - bit_size: 1 - description: TIM11 clock enable - name: TIM11EN - - bit_offset: 20 - bit_size: 1 - description: SPI5 clock enable - name: SPI5EN - - bit_offset: 21 - bit_size: 1 - description: SPI6 clock enable - name: SPI6EN - - bit_offset: 22 - bit_size: 1 - description: SAI1 clock enable - name: SAI1EN - - bit_offset: 23 - bit_size: 1 - description: SAI2 clock enable - name: SAI2EN - - bit_offset: 26 - bit_size: 1 - description: LTDC clock enable - name: LTDCEN - - bit_offset: 27 - bit_size: 1 - description: DSI clock enable - name: DSIEN - - bit_offset: 29 - bit_size: 1 - description: DFSDM1 clock enable - name: DFSDM1EN - - bit_offset: 30 - bit_size: 1 - description: MDIO clock enable - name: MDIOSEN - - bit_offset: 31 - bit_size: 1 - description: USB OTG HS PHY controller clock enable - name: USBPHYCEN + - name: TIM1EN + description: TIM1 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM8EN + description: TIM8 clock enable + bit_offset: 1 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 4 + bit_size: 1 + - name: USART6EN + description: USART6 clock enable + bit_offset: 5 + bit_size: 1 + - name: SDMMC2EN + description: SDMMC2 clock enable + bit_offset: 7 + bit_size: 1 + - name: ADC1EN + description: ADC1 clock enable + bit_offset: 8 + bit_size: 1 + - name: ADC2EN + description: ADC2 clock enable + bit_offset: 9 + bit_size: 1 + - name: ADC3EN + description: ADC3 clock enable + bit_offset: 10 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: SPI4EN + description: SPI4 clock enable + bit_offset: 13 + bit_size: 1 + - name: SYSCFGEN + description: System configuration controller clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM9EN + description: TIM9 clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM10EN + description: TIM10 clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM11EN + description: TIM11 clock enable + bit_offset: 18 + bit_size: 1 + - name: SPI5EN + description: SPI5 clock enable + bit_offset: 20 + bit_size: 1 + - name: SPI6EN + description: SPI6 clock enable + bit_offset: 21 + bit_size: 1 + - name: SAI1EN + description: SAI1 clock enable + bit_offset: 22 + bit_size: 1 + - name: SAI2EN + description: SAI2 clock enable + bit_offset: 23 + bit_size: 1 + - name: LTDCEN + description: LTDC clock enable + bit_offset: 26 + bit_size: 1 + - name: DSIEN + description: DSI clock enable + bit_offset: 27 + bit_size: 1 + - name: DFSDM1EN + description: DFSDM1 clock enable + bit_offset: 29 + bit_size: 1 + - name: MDIOSEN + description: MDIO clock enable + bit_offset: 30 + bit_size: 1 + - name: USBPHYCEN + description: USB OTG HS PHY controller clock enable + bit_offset: 31 + bit_size: 1 fieldset/APB2LPENR: description: APB2 peripheral clock enabled in low power mode register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM1 clock enable during Sleep mode - name: TIM1LPEN - - bit_offset: 1 - bit_size: 1 - description: TIM8 clock enable during Sleep mode - name: TIM8LPEN - - bit_offset: 4 - bit_size: 1 - description: USART1 clock enable during Sleep mode - name: USART1LPEN - - bit_offset: 5 - bit_size: 1 - description: USART6 clock enable during Sleep mode - name: USART6LPEN - - bit_offset: 7 - bit_size: 1 - description: SDMMC2 clock enable during Sleep mode - name: SDMMC2LPEN - - bit_offset: 8 - bit_size: 1 - description: ADC1 clock enable during Sleep mode - name: ADC1LPEN - - bit_offset: 9 - bit_size: 1 - description: ADC2 clock enable during Sleep mode - name: ADC2LPEN - - bit_offset: 10 - bit_size: 1 - description: ADC 3 clock enable during Sleep mode - name: ADC3LPEN - - bit_offset: 11 - bit_size: 1 - description: SDMMC1 clock enable during Sleep mode - name: SDMMC1LPEN - - bit_offset: 12 - bit_size: 1 - description: SPI 1 clock enable during Sleep mode - name: SPI1LPEN - - bit_offset: 13 - bit_size: 1 - description: SPI 4 clock enable during Sleep mode - name: SPI4LPEN - - bit_offset: 14 - bit_size: 1 - description: System configuration controller clock enable during Sleep mode - name: SYSCFGLPEN - - bit_offset: 16 - bit_size: 1 - description: TIM9 clock enable during sleep mode - name: TIM9LPEN - - bit_offset: 17 - bit_size: 1 - description: TIM10 clock enable during Sleep mode - name: TIM10LPEN - - bit_offset: 18 - bit_size: 1 - description: TIM11 clock enable during Sleep mode - name: TIM11LPEN - - bit_offset: 20 - bit_size: 1 - description: SPI 5 clock enable during Sleep mode - name: SPI5LPEN - - bit_offset: 21 - bit_size: 1 - description: SPI 6 clock enable during Sleep mode - name: SPI6LPEN - - bit_offset: 22 - bit_size: 1 - description: SAI1 clock enable during sleep mode - name: SAI1LPEN - - bit_offset: 23 - bit_size: 1 - description: SAI2 clock enable during sleep mode - name: SAI2LPEN - - bit_offset: 26 - bit_size: 1 - description: LTDC clock enable during sleep mode - name: LTDCLPEN - - bit_offset: 27 - bit_size: 1 - description: DSI clock enable during Sleep mode - name: DSILPEN - - bit_offset: 29 - bit_size: 1 - description: DFSDM1 clock enable during Sleep mode - name: DFSDM1LPEN - - bit_offset: 30 - bit_size: 1 - description: MDIO clock enable during Sleep mode - name: MDIOSLPEN + - name: TIM1LPEN + description: TIM1 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM8LPEN + description: TIM8 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: USART1LPEN + description: USART1 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: USART6LPEN + description: USART6 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: SDMMC2LPEN + description: SDMMC2 clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: ADC1LPEN + description: ADC1 clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: ADC2LPEN + description: ADC2 clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: ADC3LPEN + description: ADC 3 clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 + - name: SDMMC1LPEN + description: SDMMC1 clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1LPEN + description: SPI 1 clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: SPI4LPEN + description: SPI 4 clock enable during Sleep mode + bit_offset: 13 + bit_size: 1 + - name: SYSCFGLPEN + description: System configuration controller clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: TIM9LPEN + description: TIM9 clock enable during sleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM10LPEN + description: TIM10 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM11LPEN + description: TIM11 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: SPI5LPEN + description: SPI 5 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: SPI6LPEN + description: SPI 6 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: SAI1LPEN + description: SAI1 clock enable during sleep mode + bit_offset: 22 + bit_size: 1 + - name: SAI2LPEN + description: SAI2 clock enable during sleep mode + bit_offset: 23 + bit_size: 1 + - name: LTDCLPEN + description: LTDC clock enable during sleep mode + bit_offset: 26 + bit_size: 1 + - name: DSILPEN + description: DSI clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: DFSDM1LPEN + description: DFSDM1 clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: MDIOSLPEN + description: MDIO clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM1 reset - name: TIM1RST - - bit_offset: 1 - bit_size: 1 - description: TIM8 reset - name: TIM8RST - - bit_offset: 4 - bit_size: 1 - description: USART1 reset - name: USART1RST - - bit_offset: 5 - bit_size: 1 - description: USART6 reset - name: USART6RST - - bit_offset: 7 - bit_size: 1 - description: SDMMC2 reset - name: SDMMC2RST - - bit_offset: 8 - bit_size: 1 - description: ADC interface reset (common to all ADCs) - name: ADCRST - - bit_offset: 11 - bit_size: 1 - description: SDMMC1 reset - name: SDMMC1RST - - bit_offset: 12 - bit_size: 1 - description: SPI 1 reset - name: SPI1RST - - bit_offset: 13 - bit_size: 1 - description: SPI4 reset - name: SPI4RST - - bit_offset: 14 - bit_size: 1 - description: System configuration controller reset - name: SYSCFGRST - - bit_offset: 16 - bit_size: 1 - description: TIM9 reset - name: TIM9RST - - bit_offset: 17 - bit_size: 1 - description: TIM10 reset - name: TIM10RST - - bit_offset: 18 - bit_size: 1 - description: TIM11 reset - name: TIM11RST - - bit_offset: 20 - bit_size: 1 - description: SPI5 reset - name: SPI5RST - - bit_offset: 21 - bit_size: 1 - description: SPI6 reset - name: SPI6RST - - bit_offset: 22 - bit_size: 1 - description: SAI1 reset - name: SAI1RST - - bit_offset: 23 - bit_size: 1 - description: SAI2 reset - name: SAI2RST - - bit_offset: 26 - bit_size: 1 - description: LTDC reset - name: LTDCRST - - bit_offset: 27 - bit_size: 1 - description: DSI reset - name: DSIRST - - bit_offset: 29 - bit_size: 1 - description: DFSDM 1 reset - name: DFSDM1RST - - bit_offset: 30 - bit_size: 1 - description: MDIOS reset - name: MDIOSRST - - bit_offset: 31 - bit_size: 1 - description: USB OTG HS PHY controller reset - name: USBPHYCRST + - name: TIM1RST + description: TIM1 reset + bit_offset: 0 + bit_size: 1 + - name: TIM8RST + description: TIM8 reset + bit_offset: 1 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 4 + bit_size: 1 + - name: USART6RST + description: USART6 reset + bit_offset: 5 + bit_size: 1 + - name: SDMMC2RST + description: SDMMC2 reset + bit_offset: 7 + bit_size: 1 + - name: ADCRST + description: ADC interface reset (common to all ADCs) + bit_offset: 8 + bit_size: 1 + - name: SDMMC1RST + description: SDMMC1 reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: SPI4RST + description: SPI4 reset + bit_offset: 13 + bit_size: 1 + - name: SYSCFGRST + description: System configuration controller reset + bit_offset: 14 + bit_size: 1 + - name: TIM9RST + description: TIM9 reset + bit_offset: 16 + bit_size: 1 + - name: TIM10RST + description: TIM10 reset + bit_offset: 17 + bit_size: 1 + - name: TIM11RST + description: TIM11 reset + bit_offset: 18 + bit_size: 1 + - name: SPI5RST + description: SPI5 reset + bit_offset: 20 + bit_size: 1 + - name: SPI6RST + description: SPI6 reset + bit_offset: 21 + bit_size: 1 + - name: SAI1RST + description: SAI1 reset + bit_offset: 22 + bit_size: 1 + - name: SAI2RST + description: SAI2 reset + bit_offset: 23 + bit_size: 1 + - name: LTDCRST + description: LTDC reset + bit_offset: 26 + bit_size: 1 + - name: DSIRST + description: DSI reset + bit_offset: 27 + bit_size: 1 + - name: DFSDM1RST + description: DFSDM 1 reset + bit_offset: 29 + bit_size: 1 + - name: MDIOSRST + description: MDIOS reset + bit_offset: 30 + bit_size: 1 + - name: USBPHYCRST + description: USB OTG HS PHY controller reset + bit_offset: 31 + bit_size: 1 fieldset/BDCR: description: Backup domain control register fields: - - bit_offset: 0 - bit_size: 1 - description: External low-speed oscillator enable - name: LSEON - - bit_offset: 1 - bit_size: 1 - description: External low-speed oscillator ready - enum_read: LSERDYR - name: LSERDY - - bit_offset: 2 - bit_size: 1 - description: External low-speed oscillator bypass - enum: LSEBYP - name: LSEBYP - - bit_offset: 3 - bit_size: 2 - description: LSE oscillator drive capability - enum: LSEDRV - name: LSEDRV - - bit_offset: 8 - bit_size: 2 - description: RTC clock source selection - enum: RTCSEL - name: RTCSEL - - bit_offset: 15 - bit_size: 1 - description: RTC clock enable - name: RTCEN - - bit_offset: 16 - bit_size: 1 - description: Backup domain software reset - name: BDRST + - name: LSEON + description: External low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSERDYR + - name: LSEBYP + description: External low-speed oscillator bypass + bit_offset: 2 + bit_size: 1 + enum: LSEBYP + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 fieldset/CFGR: description: clock configuration register fields: - - bit_offset: 0 - bit_size: 2 - description: System clock switch - enum: SW - name: SW - - bit_offset: 2 - bit_size: 2 - description: System clock switch status - enum_read: SWSR - name: SWS - - bit_offset: 4 - bit_size: 4 - description: AHB prescaler - enum: HPRE - name: HPRE - - bit_offset: 10 - bit_size: 3 - description: APB Low speed prescaler (APB1) - enum: PPRE - name: PPRE1 - - bit_offset: 13 - bit_size: 3 - description: APB high-speed prescaler (APB2) - enum: PPRE - name: PPRE2 - - bit_offset: 16 - bit_size: 5 - description: HSE division factor for RTC clock - name: RTCPRE - - bit_offset: 21 - bit_size: 2 - description: Microcontroller clock output 1 - enum: MCO1 - name: MCO1 - - bit_offset: 23 - bit_size: 1 - description: I2S clock selection - enum: ISSRC - name: I2SSRC - - bit_offset: 24 - bit_size: 3 - description: MCO1 prescaler - enum: MCOPRE - name: MCO1PRE - - bit_offset: 27 - bit_size: 3 - description: MCO2 prescaler - enum: MCOPRE - name: MCO2PRE - - bit_offset: 30 - bit_size: 2 - description: Microcontroller clock output 2 - enum: MCO2 - name: MCO2 + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum_read: SWSR + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 10 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 13 + bit_size: 3 + enum: PPRE + - name: RTCPRE + description: HSE division factor for RTC clock + bit_offset: 16 + bit_size: 5 + - name: MCO1 + description: Microcontroller clock output 1 + bit_offset: 21 + bit_size: 2 + enum: MCO1 + - name: I2SSRC + description: I2S clock selection + bit_offset: 23 + bit_size: 1 + enum: ISSRC + - name: MCO1PRE + description: MCO1 prescaler + bit_offset: 24 + bit_size: 3 + enum: MCOPRE + - name: MCO2PRE + description: MCO2 prescaler + bit_offset: 27 + bit_size: 3 + enum: MCOPRE + - name: MCO2 + description: Microcontroller clock output 2 + bit_offset: 30 + bit_size: 2 + enum: MCO2 fieldset/CIR: description: clock interrupt register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready interrupt flag - enum_read: LSIRDYFR - name: LSIRDYF - - bit_offset: 1 - bit_size: 1 - description: LSE ready interrupt flag - enum_read: LSIRDYFR - name: LSERDYF - - bit_offset: 2 - bit_size: 1 - description: HSI ready interrupt flag - enum_read: LSIRDYFR - name: HSIRDYF - - bit_offset: 3 - bit_size: 1 - description: HSE ready interrupt flag - enum_read: LSIRDYFR - name: HSERDYF - - bit_offset: 4 - bit_size: 1 - description: Main PLL (PLL) ready interrupt flag - enum_read: LSIRDYFR - name: PLLRDYF - - bit_offset: 5 - bit_size: 1 - description: PLLI2S ready interrupt flag - enum_read: LSIRDYFR - name: PLLI2SRDYF - - bit_offset: 6 - bit_size: 1 - description: PLLSAI ready interrupt flag - enum_read: LSIRDYFR - name: PLLSAIRDYF - - bit_offset: 7 - bit_size: 1 - description: Clock security system interrupt flag - enum_read: CSSFR - name: CSSF - - bit_offset: 8 - bit_size: 1 - description: LSI ready interrupt enable - enum: LSIRDYIE - name: LSIRDYIE - - bit_offset: 9 - bit_size: 1 - description: LSE ready interrupt enable - enum: LSIRDYIE - name: LSERDYIE - - bit_offset: 10 - bit_size: 1 - description: HSI ready interrupt enable - enum: LSIRDYIE - name: HSIRDYIE - - bit_offset: 11 - bit_size: 1 - description: HSE ready interrupt enable - enum: LSIRDYIE - name: HSERDYIE - - bit_offset: 12 - bit_size: 1 - description: Main PLL (PLL) ready interrupt enable - enum: LSIRDYIE - name: PLLRDYIE - - bit_offset: 13 - bit_size: 1 - description: PLLI2S ready interrupt enable - enum: LSIRDYIE - name: PLLI2SRDYIE - - bit_offset: 14 - bit_size: 1 - description: PLLSAI Ready Interrupt Enable - enum: LSIRDYIE - name: PLLSAIRDYIE - - bit_offset: 16 - bit_size: 1 - description: LSI ready interrupt clear - enum_write: LSIRDYCW - name: LSIRDYC - - bit_offset: 17 - bit_size: 1 - description: LSE ready interrupt clear - enum_write: LSIRDYCW - name: LSERDYC - - bit_offset: 18 - bit_size: 1 - description: HSI ready interrupt clear - enum_write: LSIRDYCW - name: HSIRDYC - - bit_offset: 19 - bit_size: 1 - description: HSE ready interrupt clear - enum_write: LSIRDYCW - name: HSERDYC - - bit_offset: 20 - bit_size: 1 - description: Main PLL(PLL) ready interrupt clear - enum_write: LSIRDYCW - name: PLLRDYC - - bit_offset: 21 - bit_size: 1 - description: PLLI2S ready interrupt clear - enum_write: LSIRDYCW - name: PLLI2SRDYC - - bit_offset: 22 - bit_size: 1 - description: PLLSAI Ready Interrupt Clear - enum_write: LSIRDYCW - name: PLLSAIRDYC - - bit_offset: 23 - bit_size: 1 - description: Clock security system interrupt clear - enum_write: CSSCW - name: CSSC + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + enum_read: LSIRDYFR + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + enum_read: LSIRDYFR + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + enum_read: LSIRDYFR + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 3 + bit_size: 1 + enum_read: LSIRDYFR + - name: PLLRDYF + description: Main PLL (PLL) ready interrupt flag + bit_offset: 4 + bit_size: 1 + enum_read: LSIRDYFR + - name: PLLI2SRDYF + description: PLLI2S ready interrupt flag + bit_offset: 5 + bit_size: 1 + enum_read: LSIRDYFR + - name: PLLSAIRDYF + description: PLLSAI ready interrupt flag + bit_offset: 6 + bit_size: 1 + enum_read: LSIRDYFR + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 7 + bit_size: 1 + enum_read: CSSFR + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 8 + bit_size: 1 + enum: LSIRDYIE + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 9 + bit_size: 1 + enum: LSIRDYIE + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 10 + bit_size: 1 + enum: LSIRDYIE + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 11 + bit_size: 1 + enum: LSIRDYIE + - name: PLLRDYIE + description: Main PLL (PLL) ready interrupt enable + bit_offset: 12 + bit_size: 1 + enum: LSIRDYIE + - name: PLLI2SRDYIE + description: PLLI2S ready interrupt enable + bit_offset: 13 + bit_size: 1 + enum: LSIRDYIE + - name: PLLSAIRDYIE + description: PLLSAI Ready Interrupt Enable + bit_offset: 14 + bit_size: 1 + enum: LSIRDYIE + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 16 + bit_size: 1 + enum_write: LSIRDYCW + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 17 + bit_size: 1 + enum_write: LSIRDYCW + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 18 + bit_size: 1 + enum_write: LSIRDYCW + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 19 + bit_size: 1 + enum_write: LSIRDYCW + - name: PLLRDYC + description: Main PLL(PLL) ready interrupt clear + bit_offset: 20 + bit_size: 1 + enum_write: LSIRDYCW + - name: PLLI2SRDYC + description: PLLI2S ready interrupt clear + bit_offset: 21 + bit_size: 1 + enum_write: LSIRDYCW + - name: PLLSAIRDYC + description: PLLSAI Ready Interrupt Clear + bit_offset: 22 + bit_size: 1 + enum_write: LSIRDYCW + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 + enum_write: CSSCW fieldset/CR: description: clock control register fields: - - bit_offset: 0 - bit_size: 1 - description: Internal high-speed clock enable - name: HSION - - bit_offset: 1 - bit_size: 1 - description: Internal high-speed clock ready flag - enum_read: HSIRDYR - name: HSIRDY - - bit_offset: 3 - bit_size: 5 - description: Internal high-speed clock trimming - name: HSITRIM - - bit_offset: 8 - bit_size: 8 - description: Internal high-speed clock calibration - name: HSICAL - - bit_offset: 16 - bit_size: 1 - description: HSE clock enable - name: HSEON - - bit_offset: 17 - bit_size: 1 - description: HSE clock ready flag - enum_read: HSIRDYR - name: HSERDY - - bit_offset: 18 - bit_size: 1 - description: HSE clock bypass - enum: HSEBYP - name: HSEBYP - - bit_offset: 19 - bit_size: 1 - description: Clock security system enable - name: CSSON - - bit_offset: 24 - bit_size: 1 - description: Main PLL (PLL) enable - name: PLLON - - bit_offset: 25 - bit_size: 1 - description: Main PLL (PLL) clock ready flag - enum_read: HSIRDYR - name: PLLRDY - - bit_offset: 26 - bit_size: 1 - description: PLLI2S enable - name: PLLI2SON - - bit_offset: 27 - bit_size: 1 - description: PLLI2S clock ready flag - enum_read: HSIRDYR - name: PLLI2SRDY - - bit_offset: 28 - bit_size: 1 - description: PLLSAI enable - name: PLLSAION - - bit_offset: 29 - bit_size: 1 - description: PLLSAI clock ready flag - enum_read: HSIRDYR - name: PLLSAIRDY + - name: HSION + description: Internal high-speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal high-speed clock ready flag + bit_offset: 1 + bit_size: 1 + enum_read: HSIRDYR + - name: HSITRIM + description: Internal high-speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal high-speed clock calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + enum_read: HSIRDYR + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + enum: HSEBYP + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: Main PLL (PLL) enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL (PLL) clock ready flag + bit_offset: 25 + bit_size: 1 + enum_read: HSIRDYR + - name: PLLI2SON + description: PLLI2S enable + bit_offset: 26 + bit_size: 1 + - name: PLLI2SRDY + description: PLLI2S clock ready flag + bit_offset: 27 + bit_size: 1 + enum_read: HSIRDYR + - name: PLLSAION + description: PLLSAI enable + bit_offset: 28 + bit_size: 1 + - name: PLLSAIRDY + description: PLLSAI clock ready flag + bit_offset: 29 + bit_size: 1 + enum_read: HSIRDYR fieldset/CSR: description: clock control & status register fields: - - bit_offset: 0 - bit_size: 1 - description: Internal low-speed oscillator enable - name: LSION - - bit_offset: 1 - bit_size: 1 - description: Internal low-speed oscillator ready - enum_read: LSIRDYR - name: LSIRDY - - bit_offset: 24 - bit_size: 1 - description: Remove reset flag - enum_write: RMVFW - name: RMVF - - bit_offset: 25 - bit_size: 1 - description: BOR reset flag - enum_read: BORRSTFR - name: BORRSTF - - bit_offset: 26 - bit_size: 1 - description: PIN reset flag - enum_read: BORRSTFR - name: PADRSTF - - bit_offset: 27 - bit_size: 1 - description: POR/PDR reset flag - enum_read: BORRSTFR - name: PORRSTF - - bit_offset: 28 - bit_size: 1 - description: Software reset flag - enum_read: BORRSTFR - name: SFTRSTF - - bit_offset: 29 - bit_size: 1 - description: Independent watchdog reset flag - enum_read: BORRSTFR - name: WDGRSTF - - bit_offset: 30 - bit_size: 1 - description: Window watchdog reset flag - enum_read: BORRSTFR - name: WWDGRSTF - - bit_offset: 31 - bit_size: 1 - description: Low-power reset flag - enum_read: BORRSTFR - name: LPWRRSTF + - name: LSION + description: Internal low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSIRDYR + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + enum_write: RMVFW + - name: BORRSTF + description: BOR reset flag + bit_offset: 25 + bit_size: 1 + enum_read: BORRSTFR + - name: PADRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + enum_read: BORRSTFR + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + enum_read: BORRSTFR + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + enum_read: BORRSTFR + - name: WDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + enum_read: BORRSTFR + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + enum_read: BORRSTFR + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 + enum_read: BORRSTFR fieldset/DCKCFGR1: description: dedicated clocks configuration register fields: - - bit_offset: 0 - bit_size: 5 - description: PLLI2S division factor for SAI1 clock - enum: PLLISDIVQ - name: PLLI2SDIVQ - - bit_offset: 8 - bit_size: 5 - description: PLLSAI division factor for SAI1 clock - enum: PLLSAIDIVQ - name: PLLSAIDIVQ - - bit_offset: 16 - bit_size: 2 - description: division factor for LCD_CLK - enum: PLLSAIDIVR - name: PLLSAIDIVR - - bit_offset: 20 - bit_size: 2 - description: SAI1 clock source selection - enum: SAISEL - name: SAI1SEL - - bit_offset: 22 - bit_size: 2 - description: SAI2 clock source selection - enum: SAISEL - name: SAI2SEL - - bit_offset: 24 - bit_size: 1 - description: Timers clocks prescalers selection - enum: TIMPRE - name: TIMPRE - - bit_offset: 25 - bit_size: 1 - description: DFSDM1 clock source selection - enum: DFSDMSEL - name: DFSDM1SEL - - bit_offset: 26 - bit_size: 1 - description: DFSDM1 AUDIO clock source selection - enum: ADFSDMSEL - name: ADFSDM1SEL + - name: PLLI2SDIVQ + description: PLLI2S division factor for SAI1 clock + bit_offset: 0 + bit_size: 5 + enum: PLLISDIVQ + - name: PLLSAIDIVQ + description: PLLSAI division factor for SAI1 clock + bit_offset: 8 + bit_size: 5 + enum: PLLSAIDIVQ + - name: PLLSAIDIVR + description: division factor for LCD_CLK + bit_offset: 16 + bit_size: 2 + enum: PLLSAIDIVR + - name: SAI1SEL + description: SAI1 clock source selection + bit_offset: 20 + bit_size: 2 + enum: SAISEL + - name: SAI2SEL + description: SAI2 clock source selection + bit_offset: 22 + bit_size: 2 + enum: SAISEL + - name: TIMPRE + description: Timers clocks prescalers selection + bit_offset: 24 + bit_size: 1 + enum: TIMPRE + - name: DFSDM1SEL + description: DFSDM1 clock source selection + bit_offset: 25 + bit_size: 1 + enum: DFSDMSEL + - name: ADFSDM1SEL + description: DFSDM1 AUDIO clock source selection + bit_offset: 26 + bit_size: 1 + enum: ADFSDMSEL fieldset/DCKCFGR2: description: dedicated clocks configuration register fields: - - bit_offset: 0 - bit_size: 2 - description: USART 1 clock source selection - enum: USART1SEL - name: USART1SEL - - bit_offset: 2 - bit_size: 2 - description: USART 2 clock source selection - enum: USART2SEL - name: USART2SEL - - bit_offset: 4 - bit_size: 2 - description: USART 3 clock source selection - enum: USART2SEL - name: USART3SEL - - bit_offset: 6 - bit_size: 2 - description: UART 4 clock source selection - enum: USART2SEL - name: UART4SEL - - bit_offset: 8 - bit_size: 2 - description: UART 5 clock source selection - enum: USART2SEL - name: UART5SEL - - bit_offset: 10 - bit_size: 2 - description: USART 6 clock source selection - enum: USART1SEL - name: USART6SEL - - bit_offset: 12 - bit_size: 2 - description: UART 7 clock source selection - enum: USART2SEL - name: UART7SEL - - bit_offset: 14 - bit_size: 2 - description: UART 8 clock source selection - enum: USART2SEL - name: UART8SEL - - bit_offset: 16 - bit_size: 2 - description: I2C1 clock source selection - enum: ICSEL - name: I2C1SEL - - bit_offset: 18 - bit_size: 2 - description: I2C2 clock source selection - enum: ICSEL - name: I2C2SEL - - bit_offset: 20 - bit_size: 2 - description: I2C3 clock source selection - enum: ICSEL - name: I2C3SEL - - bit_offset: 22 - bit_size: 2 - description: I2C4 clock source selection - enum: ICSEL - name: I2C4SEL - - bit_offset: 24 - bit_size: 2 - description: Low power timer 1 clock source selection - enum: LPTIMSEL - name: LPTIM1SEL - - bit_offset: 26 - bit_size: 1 - description: HDMI-CEC clock source selection - enum: CECSEL - name: CECSEL - - bit_offset: 27 - bit_size: 1 - description: 48MHz clock source selection - enum: CKMSEL - name: CK48MSEL - - bit_offset: 28 - bit_size: 1 - description: SDMMC1 clock source selection - enum: SDMMCSEL - name: SDMMC1SEL - - bit_offset: 29 - bit_size: 1 - description: SDMMC2 clock source selection - enum: SDMMCSEL - name: SDMMC2SEL - - bit_offset: 30 - bit_size: 1 - description: DSI clock source selection - enum: DSISEL - name: DSISEL + - name: USART1SEL + description: USART 1 clock source selection + bit_offset: 0 + bit_size: 2 + enum: USART1SEL + - name: USART2SEL + description: USART 2 clock source selection + bit_offset: 2 + bit_size: 2 + enum: USART2SEL + - name: USART3SEL + description: USART 3 clock source selection + bit_offset: 4 + bit_size: 2 + enum: USART2SEL + - name: UART4SEL + description: UART 4 clock source selection + bit_offset: 6 + bit_size: 2 + enum: USART2SEL + - name: UART5SEL + description: UART 5 clock source selection + bit_offset: 8 + bit_size: 2 + enum: USART2SEL + - name: USART6SEL + description: USART 6 clock source selection + bit_offset: 10 + bit_size: 2 + enum: USART1SEL + - name: UART7SEL + description: UART 7 clock source selection + bit_offset: 12 + bit_size: 2 + enum: USART2SEL + - name: UART8SEL + description: UART 8 clock source selection + bit_offset: 14 + bit_size: 2 + enum: USART2SEL + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 16 + bit_size: 2 + enum: ICSEL + - name: I2C2SEL + description: I2C2 clock source selection + bit_offset: 18 + bit_size: 2 + enum: ICSEL + - name: I2C3SEL + description: I2C3 clock source selection + bit_offset: 20 + bit_size: 2 + enum: ICSEL + - name: I2C4SEL + description: I2C4 clock source selection + bit_offset: 22 + bit_size: 2 + enum: ICSEL + - name: LPTIM1SEL + description: Low power timer 1 clock source selection + bit_offset: 24 + bit_size: 2 + enum: LPTIMSEL + - name: CECSEL + description: HDMI-CEC clock source selection + bit_offset: 26 + bit_size: 1 + enum: CECSEL + - name: CK48MSEL + description: 48MHz clock source selection + bit_offset: 27 + bit_size: 1 + enum: CKMSEL + - name: SDMMC1SEL + description: SDMMC1 clock source selection + bit_offset: 28 + bit_size: 1 + enum: SDMMCSEL + - name: SDMMC2SEL + description: SDMMC2 clock source selection + bit_offset: 29 + bit_size: 1 + enum: SDMMCSEL + - name: DSISEL + description: DSI clock source selection + bit_offset: 30 + bit_size: 1 + enum: DSISEL fieldset/PLLCFGR: description: PLL configuration register fields: - - bit_offset: 0 - bit_size: 6 - description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input - clock - name: PLLM - - bit_offset: 6 - bit_size: 9 - description: Main PLL (PLL) multiplication factor for VCO - name: PLLN - - bit_offset: 16 - bit_size: 2 - description: Main PLL (PLL) division factor for main system clock - enum: PLLP - name: PLLP - - bit_offset: 22 - bit_size: 1 - description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - enum: PLLSRC - name: PLLSRC - - bit_offset: 24 - bit_size: 4 - description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number - generator clocks - name: PLLQ - - bit_offset: 28 - bit_size: 3 - description: PLL division factor for DSI clock - name: PLLR + - name: PLLM + description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + bit_offset: 0 + bit_size: 6 + - name: PLLN + description: Main PLL (PLL) multiplication factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLP + description: Main PLL (PLL) division factor for main system clock + bit_offset: 16 + bit_size: 2 + enum: PLLP + - name: PLLSRC + description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + bit_offset: 22 + bit_size: 1 + enum: PLLSRC + - name: PLLQ + description: "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" + bit_offset: 24 + bit_size: 4 + - name: PLLR + description: PLL division factor for DSI clock + bit_offset: 28 + bit_size: 3 fieldset/PLLI2SCFGR: description: PLLI2S configuration register fields: - - bit_offset: 6 - bit_size: 9 - description: PLLI2S multiplication factor for VCO - name: PLLI2SN - - bit_offset: 16 - bit_size: 2 - description: PLLI2S division factor for SPDIFRX clock - enum: PLLISP - name: PLLI2SP - - bit_offset: 24 - bit_size: 4 - description: PLLI2S division factor for SAI1 clock - name: PLLI2SQ - - bit_offset: 28 - bit_size: 3 - description: PLLI2S division factor for I2S clocks - name: PLLI2SR + - name: PLLI2SN + description: PLLI2S multiplication factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLI2SP + description: PLLI2S division factor for SPDIFRX clock + bit_offset: 16 + bit_size: 2 + enum: PLLISP + - name: PLLI2SQ + description: PLLI2S division factor for SAI1 clock + bit_offset: 24 + bit_size: 4 + - name: PLLI2SR + description: PLLI2S division factor for I2S clocks + bit_offset: 28 + bit_size: 3 fieldset/PLLSAICFGR: description: PLL configuration register fields: - - bit_offset: 6 - bit_size: 9 - description: PLLSAI division factor for VCO - name: PLLSAIN - - bit_offset: 16 - bit_size: 2 - description: PLLSAI division factor for 48MHz clock - enum: PLLSAIP - name: PLLSAIP - - bit_offset: 24 - bit_size: 4 - description: PLLSAI division factor for SAI clock - name: PLLSAIQ - - bit_offset: 28 - bit_size: 3 - description: PLLSAI division factor for LCD clock - name: PLLSAIR + - name: PLLSAIN + description: PLLSAI division factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLSAIP + description: PLLSAI division factor for 48MHz clock + bit_offset: 16 + bit_size: 2 + enum: PLLSAIP + - name: PLLSAIQ + description: PLLSAI division factor for SAI clock + bit_offset: 24 + bit_size: 4 + - name: PLLSAIR + description: PLLSAI division factor for LCD clock + bit_offset: 28 + bit_size: 3 fieldset/SSCGR: description: spread spectrum clock generation register fields: - - bit_offset: 0 - bit_size: 13 - description: Modulation period - name: MODPER - - bit_offset: 13 - bit_size: 15 - description: Incrementation step - name: INCSTEP - - bit_offset: 30 - bit_size: 1 - description: Spread Select - enum: SPREADSEL - name: SPREADSEL - - bit_offset: 31 - bit_size: 1 - description: Spread spectrum modulation enable - name: SSCGEN + - name: MODPER + description: Modulation period + bit_offset: 0 + bit_size: 13 + - name: INCSTEP + description: Incrementation step + bit_offset: 13 + bit_size: 15 + - name: SPREADSEL + description: Spread Select + bit_offset: 30 + bit_size: 1 + enum: SPREADSEL + - name: SSCGEN + description: Spread spectrum modulation enable + bit_offset: 31 + bit_size: 1 +enum/ADFSDMSEL: + bit_size: 1 + variants: + - name: SAI1 + description: SAI1 clock selected as DFSDM1 Audio clock source + value: 0 + - name: SAI2 + description: SAI2 clock selected as DFSDM1 Audio clock source + value: 1 +enum/BORRSTFR: + bit_size: 1 + variants: + - name: NoReset + description: No reset has occured + value: 0 + - name: Reset + description: A reset has occured + value: 1 +enum/CECSEL: + bit_size: 1 + variants: + - name: LSE + description: LSE clock is selected as HDMI-CEC clock + value: 0 + - name: HSI_Div488 + description: HSI divided by 488 clock is selected as HDMI-CEC clock + value: 1 +enum/CKMSEL: + bit_size: 1 + variants: + - name: PLL + description: 48MHz clock from PLL is selected + value: 0 + - name: PLLSAI + description: 48MHz clock from PLLSAI is selected + value: 1 +enum/CSSCW: + bit_size: 1 + variants: + - name: Clear + description: Clear CSSF flag + value: 1 +enum/CSSFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock security interrupt caused by HSE clock failure + value: 0 + - name: Interrupted + description: Clock security interrupt caused by HSE clock failure + value: 1 +enum/DFSDMSEL: + bit_size: 1 + variants: + - name: APB2 + description: APB2 clock (PCLK2) selected as DFSDM1 Kernel clock source + value: 0 + - name: SYSCLK + description: System clock (SYSCLK) clock selected as DFSDM1 Kernel clock source + value: 1 +enum/DSISEL: + bit_size: 1 + variants: + - name: DSI_PHY + description: DSI-PHY used as DSI byte lane clock source (usual case) + value: 0 + - name: PLLR + description: "PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)" + value: 1 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/HSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: HSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: HSE crystal oscillator bypassed with external clock + value: 1 +enum/HSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: Clock not ready + value: 0 + - name: Ready + description: Clock ready + value: 1 +enum/ICSEL: + bit_size: 2 + variants: + - name: APB + description: APB clock selected as I2C clock + value: 0 + - name: SYSCLK + description: System clock selected as I2C clock + value: 1 + - name: HSI + description: HSI clock selected as I2C clock + value: 2 +enum/ISSRC: + bit_size: 1 + variants: + - name: PLLI2S + description: PLLI2S clock used as I2S clock source + value: 0 + - name: CKIN + description: External clock mapped on the I2S_CKIN pin used as I2S clock source + value: 1 +enum/LPTIMSEL: + bit_size: 2 + variants: + - name: APB1 + description: APB1 clock (PCLK1) selected as LPTILM1 clock + value: 0 + - name: LSI + description: LSI clock is selected as LPTILM1 clock + value: 1 + - name: HSI + description: HSI clock is selected as LPTILM1 clock + value: 2 + - name: LSE + description: LSE clock is selected as LPTILM1 clock + value: 3 +enum/LSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: LSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: LSE crystal oscillator bypassed with external clock + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Low drive capacity + value: 0 + - name: MediumHigh + description: Medium-high drive capacity + value: 1 + - name: MediumLow + description: Medium-low drive capacity + value: 2 + - name: High + description: High drive capacity + value: 3 +enum/LSERDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSE oscillator not ready + value: 0 + - name: Ready + description: LSE oscillator ready + value: 1 +enum/LSIRDYCW: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag + value: 1 +enum/LSIRDYFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock ready interrupt + value: 0 + - name: Interrupted + description: Clock ready interrupt + value: 1 +enum/LSIRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt disabled + value: 0 + - name: Enabled + description: Interrupt enabled + value: 1 +enum/LSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSI oscillator not ready + value: 0 + - name: Ready + description: LSI oscillator ready + value: 1 +enum/MCO1: + bit_size: 2 + variants: + - name: HSI + description: HSI clock selected + value: 0 + - name: LSE + description: LSE oscillator selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 +enum/MCO2: + bit_size: 2 + variants: + - name: SYSCLK + description: System clock (SYSCLK) selected + value: 0 + - name: PLLI2S + description: PLLI2S clock selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 4 + - name: Div3 + description: Division by 3 + value: 5 + - name: Div4 + description: Division by 4 + value: 6 + - name: Div5 + description: Division by 5 + value: 7 +enum/PLLISDIVQ: + bit_size: 5 + variants: + - name: Div1 + description: PLLI2SDIVQ = /1 + value: 0 + - name: Div2 + description: PLLI2SDIVQ = /2 + value: 1 + - name: Div3 + description: PLLI2SDIVQ = /3 + value: 2 + - name: Div4 + description: PLLI2SDIVQ = /4 + value: 3 + - name: Div5 + description: PLLI2SDIVQ = /5 + value: 4 + - name: Div6 + description: PLLI2SDIVQ = /6 + value: 5 + - name: Div7 + description: PLLI2SDIVQ = /7 + value: 6 + - name: Div8 + description: PLLI2SDIVQ = /8 + value: 7 + - name: Div9 + description: PLLI2SDIVQ = /9 + value: 8 + - name: Div10 + description: PLLI2SDIVQ = /10 + value: 9 + - name: Div11 + description: PLLI2SDIVQ = /11 + value: 10 + - name: Div12 + description: PLLI2SDIVQ = /12 + value: 11 + - name: Div13 + description: PLLI2SDIVQ = /13 + value: 12 + - name: Div14 + description: PLLI2SDIVQ = /14 + value: 13 + - name: Div15 + description: PLLI2SDIVQ = /15 + value: 14 + - name: Div16 + description: PLLI2SDIVQ = /16 + value: 15 + - name: Div17 + description: PLLI2SDIVQ = /17 + value: 16 + - name: Div18 + description: PLLI2SDIVQ = /18 + value: 17 + - name: Div19 + description: PLLI2SDIVQ = /19 + value: 18 + - name: Div20 + description: PLLI2SDIVQ = /20 + value: 19 + - name: Div21 + description: PLLI2SDIVQ = /21 + value: 20 + - name: Div22 + description: PLLI2SDIVQ = /22 + value: 21 + - name: Div23 + description: PLLI2SDIVQ = /23 + value: 22 + - name: Div24 + description: PLLI2SDIVQ = /24 + value: 23 + - name: Div25 + description: PLLI2SDIVQ = /25 + value: 24 + - name: Div26 + description: PLLI2SDIVQ = /26 + value: 25 + - name: Div27 + description: PLLI2SDIVQ = /27 + value: 26 + - name: Div28 + description: PLLI2SDIVQ = /28 + value: 27 + - name: Div29 + description: PLLI2SDIVQ = /29 + value: 28 + - name: Div30 + description: PLLI2SDIVQ = /30 + value: 29 + - name: Div31 + description: PLLI2SDIVQ = /31 + value: 30 + - name: Div32 + description: PLLI2SDIVQ = /32 + value: 31 +enum/PLLISP: + bit_size: 2 + variants: + - name: Div2 + description: PLL*P=2 + value: 0 + - name: Div4 + description: PLL*P=4 + value: 1 + - name: Div6 + description: PLL*P=6 + value: 2 + - name: Div8 + description: PLL*P=8 + value: 3 +enum/PLLP: + bit_size: 2 + variants: + - name: Div2 + description: PLLP=2 + value: 0 + - name: Div4 + description: PLLP=4 + value: 1 + - name: Div6 + description: PLLP=6 + value: 2 + - name: Div8 + description: PLLP=8 + value: 3 +enum/PLLSAIDIVQ: + bit_size: 5 + variants: + - name: Div1 + description: PLLSAIDIVQ = /1 + value: 0 + - name: Div2 + description: PLLSAIDIVQ = /2 + value: 1 + - name: Div3 + description: PLLSAIDIVQ = /3 + value: 2 + - name: Div4 + description: PLLSAIDIVQ = /4 + value: 3 + - name: Div5 + description: PLLSAIDIVQ = /5 + value: 4 + - name: Div6 + description: PLLSAIDIVQ = /6 + value: 5 + - name: Div7 + description: PLLSAIDIVQ = /7 + value: 6 + - name: Div8 + description: PLLSAIDIVQ = /8 + value: 7 + - name: Div9 + description: PLLSAIDIVQ = /9 + value: 8 + - name: Div10 + description: PLLSAIDIVQ = /10 + value: 9 + - name: Div11 + description: PLLSAIDIVQ = /11 + value: 10 + - name: Div12 + description: PLLSAIDIVQ = /12 + value: 11 + - name: Div13 + description: PLLSAIDIVQ = /13 + value: 12 + - name: Div14 + description: PLLSAIDIVQ = /14 + value: 13 + - name: Div15 + description: PLLSAIDIVQ = /15 + value: 14 + - name: Div16 + description: PLLSAIDIVQ = /16 + value: 15 + - name: Div17 + description: PLLSAIDIVQ = /17 + value: 16 + - name: Div18 + description: PLLSAIDIVQ = /18 + value: 17 + - name: Div19 + description: PLLSAIDIVQ = /19 + value: 18 + - name: Div20 + description: PLLSAIDIVQ = /20 + value: 19 + - name: Div21 + description: PLLSAIDIVQ = /21 + value: 20 + - name: Div22 + description: PLLSAIDIVQ = /22 + value: 21 + - name: Div23 + description: PLLSAIDIVQ = /23 + value: 22 + - name: Div24 + description: PLLSAIDIVQ = /24 + value: 23 + - name: Div25 + description: PLLSAIDIVQ = /25 + value: 24 + - name: Div26 + description: PLLSAIDIVQ = /26 + value: 25 + - name: Div27 + description: PLLSAIDIVQ = /27 + value: 26 + - name: Div28 + description: PLLSAIDIVQ = /28 + value: 27 + - name: Div29 + description: PLLSAIDIVQ = /29 + value: 28 + - name: Div30 + description: PLLSAIDIVQ = /30 + value: 29 + - name: Div31 + description: PLLSAIDIVQ = /31 + value: 30 + - name: Div32 + description: PLLSAIDIVQ = /32 + value: 31 +enum/PLLSAIDIVR: + bit_size: 2 + variants: + - name: Div2 + description: PLLSAIDIVR = /2 + value: 0 + - name: Div4 + description: PLLSAIDIVR = /4 + value: 1 + - name: Div8 + description: PLLSAIDIVR = /8 + value: 2 + - name: Div16 + description: PLLSAIDIVR = /16 + value: 3 +enum/PLLSAIP: + bit_size: 2 + variants: + - name: Div2 + description: PLL*P=2 + value: 0 + - name: Div4 + description: PLL*P=4 + value: 1 + - name: Div6 + description: PLL*P=6 + value: 2 + - name: Div8 + description: PLL*P=8 + value: 3 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI + description: HSI clock selected as PLL and PLLI2S clock entry + value: 0 + - name: HSE + description: HSE oscillator clock selected as PLL and PLLI2S clock entry + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/RMVFW: + bit_size: 1 + variants: + - name: Clear + description: Clears the reset flag + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SAISEL: + bit_size: 2 + variants: + - name: PLLSAI + description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + value: 0 + - name: PLLI2S + description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + value: 1 + - name: AFIF + description: SAI2 clock frequency = Alternate function input frequency + value: 2 + - name: HSI_HSE + description: SAI2 clock frequency = HSI or HSE + value: 3 +enum/SDMMCSEL: + bit_size: 1 + variants: + - name: CK48M + description: 48 MHz clock is selected as SD clock + value: 0 + - name: SYSCLK + description: System clock is selected as SD clock + value: 1 +enum/SPREADSEL: + bit_size: 1 + variants: + - name: Center + description: Center spread + value: 0 + - name: Down + description: Down spread + value: 1 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLL + description: PLL selected as system clock + value: 2 +enum/SWSR: + bit_size: 2 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 +enum/TIMPRE: + bit_size: 1 + variants: + - name: Mul2 + description: "If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx" + value: 0 + - name: Mul4 + description: "If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx" + value: 1 +enum/USART1SEL: + bit_size: 2 + variants: + - name: APB2 + description: APB2 clock (PCLK2) is selected as USART clock + value: 0 + - name: SYSCLK + description: System clock is selected as USART clock + value: 1 + - name: HSI + description: HSI clock is selected as USART clock + value: 2 + - name: LSE + description: LSE clock is selected as USART clock + value: 3 +enum/USART2SEL: + bit_size: 2 + variants: + - name: APB1 + description: APB1 clock (PCLK1) is selected as USART clock + value: 0 + - name: SYSCLK + description: System clock is selected as USART clock + value: 1 + - name: HSI + description: HSI clock is selected as USART clock + value: 2 + - name: LSE + description: LSE clock is selected as USART clock + value: 3 diff --git a/data/registers/rcc_g0.yaml b/data/registers/rcc_g0.yaml index f6a50fa..d1e7d2b 100644 --- a/data/registers/rcc_g0.yaml +++ b/data/registers/rcc_g0.yaml @@ -1,955 +1,956 @@ +--- block/RCC: description: Reset and clock control items: - - byte_offset: 0 - description: Clock control register - fieldset: CR - name: CR - - byte_offset: 4 - description: Internal clock sources calibration register - fieldset: ICSCR - name: ICSCR - - byte_offset: 8 - description: Clock configuration register - fieldset: CFGR - name: CFGR - - byte_offset: 12 - description: PLL configuration register - fieldset: PLLSYSCFGR - name: PLLSYSCFGR - - byte_offset: 24 - description: Clock interrupt enable register - fieldset: CIER - name: CIER - - access: Read - byte_offset: 28 - description: Clock interrupt flag register - fieldset: CIFR - name: CIFR - - access: Write - byte_offset: 32 - description: Clock interrupt clear register - fieldset: CICR - name: CICR - - byte_offset: 36 - description: GPIO reset register - fieldset: IOPRSTR - name: IOPRSTR - - byte_offset: 40 - description: AHB peripheral reset register - fieldset: AHBRSTR - name: AHBRSTR - - byte_offset: 44 - description: APB peripheral reset register 1 - fieldset: APBRSTR1 - name: APBRSTR1 - - byte_offset: 48 - description: APB peripheral reset register 2 - fieldset: APBRSTR2 - name: APBRSTR2 - - byte_offset: 52 - description: GPIO clock enable register - fieldset: IOPENR - name: IOPENR - - byte_offset: 56 - description: AHB peripheral clock enable register - fieldset: AHBENR - name: AHBENR - - byte_offset: 60 - description: APB peripheral clock enable register 1 - fieldset: APBENR1 - name: APBENR1 - - byte_offset: 64 - description: APB peripheral clock enable register 2 - fieldset: APBENR2 - name: APBENR2 - - byte_offset: 68 - description: GPIO in Sleep mode clock enable register - fieldset: IOPSMENR - name: IOPSMENR - - byte_offset: 72 - description: AHB peripheral clock enable in Sleep mode register - fieldset: AHBSMENR - name: AHBSMENR - - byte_offset: 76 - description: APB peripheral clock enable in Sleep mode register 1 - fieldset: APBSMENR1 - name: APBSMENR1 - - byte_offset: 80 - description: APB peripheral clock enable in Sleep mode register 2 - fieldset: APBSMENR2 - name: APBSMENR2 - - byte_offset: 84 - description: Peripherals independent clock configuration register - fieldset: CCIPR - name: CCIPR - - byte_offset: 92 - description: RTC domain control register - fieldset: BDCR - name: BDCR - - byte_offset: 96 - description: Control/status register - fieldset: CSR - name: CSR + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: PLLSYSCFGR + description: PLL configuration register + byte_offset: 12 + fieldset: PLLSYSCFGR + - name: CIER + description: Clock interrupt enable register + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 28 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 32 + access: Write + fieldset: CICR + - name: IOPRSTR + description: GPIO reset register + byte_offset: 36 + fieldset: IOPRSTR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 40 + fieldset: AHBRSTR + - name: APBRSTR1 + description: APB peripheral reset register 1 + byte_offset: 44 + fieldset: APBRSTR1 + - name: APBRSTR2 + description: APB peripheral reset register 2 + byte_offset: 48 + fieldset: APBRSTR2 + - name: IOPENR + description: GPIO clock enable register + byte_offset: 52 + fieldset: IOPENR + - name: AHBENR + description: AHB peripheral clock enable register + byte_offset: 56 + fieldset: AHBENR + - name: APBENR1 + description: APB peripheral clock enable register 1 + byte_offset: 60 + fieldset: APBENR1 + - name: APBENR2 + description: APB peripheral clock enable register 2 + byte_offset: 64 + fieldset: APBENR2 + - name: IOPSMENR + description: GPIO in Sleep mode clock enable register + byte_offset: 68 + fieldset: IOPSMENR + - name: AHBSMENR + description: AHB peripheral clock enable in Sleep mode register + byte_offset: 72 + fieldset: AHBSMENR + - name: APBSMENR1 + description: APB peripheral clock enable in Sleep mode register 1 + byte_offset: 76 + fieldset: APBSMENR1 + - name: APBSMENR2 + description: APB peripheral clock enable in Sleep mode register 2 + byte_offset: 80 + fieldset: APBSMENR2 + - name: CCIPR + description: Peripherals independent clock configuration register + byte_offset: 84 + fieldset: CCIPR + - name: BDCR + description: RTC domain control register + byte_offset: 92 + fieldset: BDCR + - name: CSR + description: Control/status register + byte_offset: 96 + fieldset: CSR fieldset/AHBENR: description: AHB peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA clock enable - name: DMAEN - - bit_offset: 8 - bit_size: 1 - description: Flash memory interface clock enable - name: FLASHEN - - bit_offset: 12 - bit_size: 1 - description: CRC clock enable - name: CRCEN - - bit_offset: 16 - bit_size: 1 - description: AES hardware accelerator - name: AESEN - - bit_offset: 18 - bit_size: 1 - description: Random number generator clock enable - name: RNGEN + - name: DMAEN + description: DMA clock enable + bit_offset: 0 + bit_size: 1 + - name: FLASHEN + description: Flash memory interface clock enable + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: AESEN + description: AES hardware accelerator + bit_offset: 16 + bit_size: 1 + - name: RNGEN + description: Random number generator clock enable + bit_offset: 18 + bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA1 reset - name: DMARST - - bit_offset: 8 - bit_size: 1 - description: FLITF reset - name: FLASHRST - - bit_offset: 12 - bit_size: 1 - description: CRC reset - name: CRCRST - - bit_offset: 16 - bit_size: 1 - description: AES hardware accelerator reset - name: AESRST - - bit_offset: 18 - bit_size: 1 - description: Random number generator reset - name: RNGRST + - name: DMARST + description: DMA1 reset + bit_offset: 0 + bit_size: 1 + - name: FLASHRST + description: FLITF reset + bit_offset: 8 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: AESRST + description: AES hardware accelerator reset + bit_offset: 16 + bit_size: 1 + - name: RNGRST + description: Random number generator reset + bit_offset: 18 + bit_size: 1 fieldset/AHBSMENR: description: AHB peripheral clock enable in Sleep mode register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA clock enable during Sleep mode - name: DMASMEN - - bit_offset: 8 - bit_size: 1 - description: Flash memory interface clock enable during Sleep mode - name: FLASHSMEN - - bit_offset: 9 - bit_size: 1 - description: SRAM clock enable during Sleep mode - name: SRAMSMEN - - bit_offset: 12 - bit_size: 1 - description: CRC clock enable during Sleep mode - name: CRCSMEN - - bit_offset: 16 - bit_size: 1 - description: AES hardware accelerator clock enable during Sleep mode - name: AESSMEN - - bit_offset: 18 - bit_size: 1 - description: Random number generator clock enable during Sleep mode - name: RNGSMEN + - name: DMASMEN + description: DMA clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: FLASHSMEN + description: Flash memory interface clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: SRAMSMEN + description: SRAM clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: CRCSMEN + description: CRC clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: AESSMEN + description: AES hardware accelerator clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: RNGSMEN + description: Random number generator clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 fieldset/APBENR1: description: APB peripheral clock enable register 1 fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 timer clock enable - name: TIM2EN - - bit_offset: 1 - bit_size: 1 - description: TIM3 timer clock enable - name: TIM3EN - - bit_offset: 4 - bit_size: 1 - description: TIM6 timer clock enable - name: TIM6EN - - bit_offset: 5 - bit_size: 1 - description: TIM7 timer clock enable - name: TIM7EN - - bit_offset: 10 - bit_size: 1 - description: RTC APB clock enable - name: RTCAPBEN - - bit_offset: 11 - bit_size: 1 - description: WWDG clock enable - name: WWDGEN - - bit_offset: 14 - bit_size: 1 - description: SPI2 clock enable - name: SPI2EN - - bit_offset: 17 - bit_size: 1 - description: USART2 clock enable - name: USART2EN - - bit_offset: 18 - bit_size: 1 - description: USART3 clock enable - name: USART3EN - - bit_offset: 19 - bit_size: 1 - description: USART4 clock enable - name: USART4EN - - bit_offset: 20 - bit_size: 1 - description: LPUART1 clock enable - name: LPUART1EN - - bit_offset: 21 - bit_size: 1 - description: I2C1 clock enable - name: I2C1EN - - bit_offset: 22 - bit_size: 1 - description: I2C2 clock enable - name: I2C2EN - - bit_offset: 24 - bit_size: 1 - description: HDMI CEC clock enable - name: CECEN - - bit_offset: 25 - bit_size: 1 - description: UCPD1 clock enable - name: UCPD1EN - - bit_offset: 26 - bit_size: 1 - description: UCPD2 clock enable - name: UCPD2EN - - bit_offset: 27 - bit_size: 1 - description: Debug support clock enable - name: DBGEN - - bit_offset: 28 - bit_size: 1 - description: Power interface clock enable - name: PWREN - - bit_offset: 29 - bit_size: 1 - description: DAC1 interface clock enable - name: DAC1EN - - bit_offset: 30 - bit_size: 1 - description: LPTIM2 clock enable - name: LPTIM2EN - - bit_offset: 31 - bit_size: 1 - description: LPTIM1 clock enable - name: LPTIM1EN + - name: TIM2EN + description: TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 timer clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM6EN + description: TIM6 timer clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 timer clock enable + bit_offset: 5 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: WWDG clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: USART4EN + description: USART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: LPUART1EN + description: LPUART1 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: CECEN + description: HDMI CEC clock enable + bit_offset: 24 + bit_size: 1 + - name: UCPD1EN + description: UCPD1 clock enable + bit_offset: 25 + bit_size: 1 + - name: UCPD2EN + description: UCPD2 clock enable + bit_offset: 26 + bit_size: 1 + - name: DBGEN + description: Debug support clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DAC1EN + description: DAC1 interface clock enable + bit_offset: 29 + bit_size: 1 + - name: LPTIM2EN + description: LPTIM2 clock enable + bit_offset: 30 + bit_size: 1 + - name: LPTIM1EN + description: LPTIM1 clock enable + bit_offset: 31 + bit_size: 1 fieldset/APBENR2: description: APB peripheral clock enable register 2 fields: - - bit_offset: 0 - bit_size: 1 - description: SYSCFG, COMP and VREFBUF clock enable - name: SYSCFGEN - - bit_offset: 11 - bit_size: 1 - description: TIM1 timer clock enable - name: TIM1EN - - bit_offset: 12 - bit_size: 1 - description: SPI1 clock enable - name: SPI1EN - - bit_offset: 14 - bit_size: 1 - description: USART1 clock enable - name: USART1EN - - bit_offset: 15 - bit_size: 1 - description: TIM14 timer clock enable - name: TIM14EN - - bit_offset: 16 - bit_size: 1 - description: TIM15 timer clock enable - name: TIM15EN - - bit_offset: 17 - bit_size: 1 - description: TIM16 timer clock enable - name: TIM16EN - - bit_offset: 18 - bit_size: 1 - description: TIM16 timer clock enable - name: TIM17EN - - bit_offset: 20 - bit_size: 1 - description: ADC clock enable - name: ADCEN + - name: SYSCFGEN + description: "SYSCFG, COMP and VREFBUF clock enable" + bit_offset: 0 + bit_size: 1 + - name: TIM1EN + description: TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM14EN + description: TIM14 timer clock enable + bit_offset: 15 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM16 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: ADCEN + description: ADC clock enable + bit_offset: 20 + bit_size: 1 fieldset/APBRSTR1: description: APB peripheral reset register 1 fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 timer reset - name: TIM2RST - - bit_offset: 1 - bit_size: 1 - description: TIM3 timer reset - name: TIM3RST - - bit_offset: 4 - bit_size: 1 - description: TIM6 timer reset - name: TIM6RST - - bit_offset: 5 - bit_size: 1 - description: TIM7 timer reset - name: TIM7RST - - bit_offset: 14 - bit_size: 1 - description: SPI2 reset - name: SPI2RST - - bit_offset: 17 - bit_size: 1 - description: USART2 reset - name: USART2RST - - bit_offset: 18 - bit_size: 1 - description: USART3 reset - name: USART3RST - - bit_offset: 19 - bit_size: 1 - description: USART4 reset - name: USART4RST - - bit_offset: 20 - bit_size: 1 - description: LPUART1 reset - name: LPUART1RST - - bit_offset: 21 - bit_size: 1 - description: I2C1 reset - name: I2C1RST - - bit_offset: 22 - bit_size: 1 - description: I2C2 reset - name: I2C2RST - - bit_offset: 24 - bit_size: 1 - description: HDMI CEC reset - name: CECRST - - bit_offset: 25 - bit_size: 1 - description: UCPD1 reset - name: UCPD1RST - - bit_offset: 26 - bit_size: 1 - description: UCPD2 reset - name: UCPD2RST - - bit_offset: 27 - bit_size: 1 - description: Debug support reset - name: DBGRST - - bit_offset: 28 - bit_size: 1 - description: Power interface reset - name: PWRRST - - bit_offset: 29 - bit_size: 1 - description: DAC1 interface reset - name: DAC1RST - - bit_offset: 30 - bit_size: 1 - description: Low Power Timer 2 reset - name: LPTIM2RST - - bit_offset: 31 - bit_size: 1 - description: Low Power Timer 1 reset - name: LPTIM1RST + - name: TIM2RST + description: TIM2 timer reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 timer reset + bit_offset: 1 + bit_size: 1 + - name: TIM6RST + description: TIM6 timer reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 timer reset + bit_offset: 5 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: USART4RST + description: USART4 reset + bit_offset: 19 + bit_size: 1 + - name: LPUART1RST + description: LPUART1 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: CECRST + description: HDMI CEC reset + bit_offset: 24 + bit_size: 1 + - name: UCPD1RST + description: UCPD1 reset + bit_offset: 25 + bit_size: 1 + - name: UCPD2RST + description: UCPD2 reset + bit_offset: 26 + bit_size: 1 + - name: DBGRST + description: Debug support reset + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DAC1RST + description: DAC1 interface reset + bit_offset: 29 + bit_size: 1 + - name: LPTIM2RST + description: Low Power Timer 2 reset + bit_offset: 30 + bit_size: 1 + - name: LPTIM1RST + description: Low Power Timer 1 reset + bit_offset: 31 + bit_size: 1 fieldset/APBRSTR2: description: APB peripheral reset register 2 fields: - - bit_offset: 0 - bit_size: 1 - description: SYSCFG, COMP and VREFBUF reset - name: SYSCFGRST - - bit_offset: 11 - bit_size: 1 - description: TIM1 timer reset - name: TIM1RST - - bit_offset: 12 - bit_size: 1 - description: SPI1 reset - name: SPI1RST - - bit_offset: 14 - bit_size: 1 - description: USART1 reset - name: USART1RST - - bit_offset: 15 - bit_size: 1 - description: TIM14 timer reset - name: TIM14RST - - bit_offset: 16 - bit_size: 1 - description: TIM15 timer reset - name: TIM15RST - - bit_offset: 17 - bit_size: 1 - description: TIM16 timer reset - name: TIM16RST - - bit_offset: 18 - bit_size: 1 - description: TIM17 timer reset - name: TIM17RST - - bit_offset: 20 - bit_size: 1 - description: ADC reset - name: ADCRST + - name: SYSCFGRST + description: "SYSCFG, COMP and VREFBUF reset" + bit_offset: 0 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM14RST + description: TIM14 timer reset + bit_offset: 15 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: ADCRST + description: ADC reset + bit_offset: 20 + bit_size: 1 fieldset/APBSMENR1: description: APB peripheral clock enable in Sleep mode register 1 fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 timer clock enable during Sleep mode - name: TIM2SMEN - - bit_offset: 1 - bit_size: 1 - description: TIM3 timer clock enable during Sleep mode - name: TIM3SMEN - - bit_offset: 4 - bit_size: 1 - description: TIM6 timer clock enable during Sleep mode - name: TIM6SMEN - - bit_offset: 5 - bit_size: 1 - description: TIM7 timer clock enable during Sleep mode - name: TIM7SMEN - - bit_offset: 10 - bit_size: 1 - description: RTC APB clock enable during Sleep mode - name: RTCAPBSMEN - - bit_offset: 11 - bit_size: 1 - description: WWDG clock enable during Sleep mode - name: WWDGSMEN - - bit_offset: 14 - bit_size: 1 - description: SPI2 clock enable during Sleep mode - name: SPI2SMEN - - bit_offset: 17 - bit_size: 1 - description: USART2 clock enable during Sleep mode - name: USART2SMEN - - bit_offset: 18 - bit_size: 1 - description: USART3 clock enable during Sleep mode - name: USART3SMEN - - bit_offset: 19 - bit_size: 1 - description: USART4 clock enable during Sleep mode - name: USART4SMEN - - bit_offset: 20 - bit_size: 1 - description: LPUART1 clock enable during Sleep mode - name: LPUART1SMEN - - bit_offset: 21 - bit_size: 1 - description: I2C1 clock enable during Sleep mode - name: I2C1SMEN - - bit_offset: 22 - bit_size: 1 - description: I2C2 clock enable during Sleep mode - name: I2C2SMEN - - bit_offset: 24 - bit_size: 1 - description: HDMI CEC clock enable during Sleep mode - name: CECSMEN - - bit_offset: 25 - bit_size: 1 - description: UCPD1 clock enable during Sleep mode - name: UCPD1SMEN - - bit_offset: 26 - bit_size: 1 - description: UCPD2 clock enable during Sleep mode - name: UCPD2SMEN - - bit_offset: 27 - bit_size: 1 - description: Debug support clock enable during Sleep mode - name: DBGSMEN - - bit_offset: 28 - bit_size: 1 - description: Power interface clock enable during Sleep mode - name: PWRSMEN - - bit_offset: 29 - bit_size: 1 - description: DAC1 interface clock enable during Sleep mode - name: DAC1SMEN - - bit_offset: 30 - bit_size: 1 - description: Low Power Timer 2 clock enable during Sleep mode - name: LPTIM2SMEN - - bit_offset: 31 - bit_size: 1 - description: Low Power Timer 1 clock enable during Sleep mode - name: LPTIM1SMEN + - name: TIM2SMEN + description: TIM2 timer clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: TIM3 timer clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM6SMEN + description: TIM6 timer clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7SMEN + description: TIM7 timer clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC APB clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: WWDG clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: USART2SMEN + description: USART2 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: USART3SMEN + description: USART3 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: USART4SMEN + description: USART4 clock enable during Sleep mode + bit_offset: 19 + bit_size: 1 + - name: LPUART1SMEN + description: LPUART1 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: CECSMEN + description: HDMI CEC clock enable during Sleep mode + bit_offset: 24 + bit_size: 1 + - name: UCPD1SMEN + description: UCPD1 clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: UCPD2SMEN + description: UCPD2 clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 + - name: DBGSMEN + description: Debug support clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: PWRSMEN + description: Power interface clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: DAC1SMEN + description: DAC1 interface clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: LPTIM2SMEN + description: Low Power Timer 2 clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 + - name: LPTIM1SMEN + description: Low Power Timer 1 clock enable during Sleep mode + bit_offset: 31 + bit_size: 1 fieldset/APBSMENR2: description: APB peripheral clock enable in Sleep mode register 2 fields: - - bit_offset: 0 - bit_size: 1 - description: SYSCFG, COMP and VREFBUF clock enable during Sleep mode - name: SYSCFGSMEN - - bit_offset: 11 - bit_size: 1 - description: TIM1 timer clock enable during Sleep mode - name: TIM1SMEN - - bit_offset: 12 - bit_size: 1 - description: SPI1 clock enable during Sleep mode - name: SPI1SMEN - - bit_offset: 14 - bit_size: 1 - description: USART1 clock enable during Sleep mode - name: USART1SMEN - - bit_offset: 15 - bit_size: 1 - description: TIM14 timer clock enable during Sleep mode - name: TIM14SMEN - - bit_offset: 16 - bit_size: 1 - description: TIM15 timer clock enable during Sleep mode - name: TIM15SMEN - - bit_offset: 17 - bit_size: 1 - description: TIM16 timer clock enable during Sleep mode - name: TIM16SMEN - - bit_offset: 18 - bit_size: 1 - description: TIM16 timer clock enable during Sleep mode - name: TIM17SMEN - - bit_offset: 20 - bit_size: 1 - description: ADC clock enable during Sleep mode - name: ADCSMEN + - name: SYSCFGSMEN + description: "SYSCFG, COMP and VREFBUF clock enable during Sleep mode" + bit_offset: 0 + bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: USART1 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: TIM14SMEN + description: TIM14 timer clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: TIM15SMEN + description: TIM15 timer clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM16 timer clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: ADCSMEN + description: ADC clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 fieldset/BDCR: description: RTC domain control register fields: - - bit_offset: 0 - bit_size: 1 - description: LSE oscillator enable - name: LSEON - - bit_offset: 1 - bit_size: 1 - description: LSE oscillator ready - name: LSERDY - - bit_offset: 2 - bit_size: 1 - description: LSE oscillator bypass - name: LSEBYP - - bit_offset: 3 - bit_size: 2 - description: LSE oscillator drive capability - name: LSEDRV - - bit_offset: 5 - bit_size: 1 - description: CSS on LSE enable - name: LSECSSON - - bit_offset: 6 - bit_size: 1 - description: CSS on LSE failure Detection - name: LSECSSD - - bit_offset: 8 - bit_size: 2 - description: RTC clock source selection - name: RTCSEL - - bit_offset: 15 - bit_size: 1 - description: RTC clock enable - name: RTCEN - - bit_offset: 16 - bit_size: 1 - description: RTC domain software reset - name: BDRST - - bit_offset: 24 - bit_size: 1 - description: Low-speed clock output (LSCO) enable - name: LSCOEN - - bit_offset: 25 - bit_size: 1 - description: Low-speed clock output selection - name: LSCOSEL + - name: LSEON + description: LSE oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + - name: LSECSSON + description: CSS on LSE enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: CSS on LSE failure Detection + bit_offset: 6 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: RTC domain software reset + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: Low-speed clock output (LSCO) enable + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: Low-speed clock output selection + bit_offset: 25 + bit_size: 1 fieldset/CCIPR: description: Peripherals independent clock configuration register fields: - - bit_offset: 0 - bit_size: 2 - description: USART1 clock source selection - name: USART1SEL - - bit_offset: 2 - bit_size: 2 - description: USART2 clock source selection - name: USART2SEL - - bit_offset: 6 - bit_size: 1 - description: HDMI CEC clock source selection - name: CECSEL - - bit_offset: 10 - bit_size: 2 - description: LPUART1 clock source selection - name: LPUART1SEL - - bit_offset: 12 - bit_size: 2 - description: I2C1 clock source selection - name: I2C1SEL - - bit_offset: 14 - bit_size: 2 - description: I2S1 clock source selection - name: I2S2SEL - - bit_offset: 18 - bit_size: 2 - description: LPTIM1 clock source selection - name: LPTIM1SEL - - bit_offset: 20 - bit_size: 2 - description: LPTIM2 clock source selection - name: LPTIM2SEL - - bit_offset: 22 - bit_size: 1 - description: TIM1 clock source selection - name: TIM1SEL - - bit_offset: 24 - bit_size: 1 - description: TIM15 clock source selection - name: TIM15SEL - - bit_offset: 26 - bit_size: 2 - description: RNG clock source selection - name: RNGSEL - - bit_offset: 28 - bit_size: 2 - description: Division factor of RNG clock divider - name: RNGDIV - - bit_offset: 30 - bit_size: 2 - description: ADCs clock source selection - name: ADCSEL + - name: USART1SEL + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + - name: USART2SEL + description: USART2 clock source selection + bit_offset: 2 + bit_size: 2 + - name: CECSEL + description: HDMI CEC clock source selection + bit_offset: 6 + bit_size: 1 + - name: LPUART1SEL + description: LPUART1 clock source selection + bit_offset: 10 + bit_size: 2 + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 12 + bit_size: 2 + - name: I2S2SEL + description: I2S1 clock source selection + bit_offset: 14 + bit_size: 2 + - name: LPTIM1SEL + description: LPTIM1 clock source selection + bit_offset: 18 + bit_size: 2 + - name: LPTIM2SEL + description: LPTIM2 clock source selection + bit_offset: 20 + bit_size: 2 + - name: TIM1SEL + description: TIM1 clock source selection + bit_offset: 22 + bit_size: 1 + - name: TIM15SEL + description: TIM15 clock source selection + bit_offset: 24 + bit_size: 1 + - name: RNGSEL + description: RNG clock source selection + bit_offset: 26 + bit_size: 2 + - name: RNGDIV + description: Division factor of RNG clock divider + bit_offset: 28 + bit_size: 2 + - name: ADCSEL + description: ADCs clock source selection + bit_offset: 30 + bit_size: 2 fieldset/CFGR: description: Clock configuration register fields: - - bit_offset: 0 - bit_size: 3 - description: System clock switch - name: SW - - bit_offset: 3 - bit_size: 3 - description: System clock switch status - name: SWS - - bit_offset: 8 - bit_size: 4 - description: AHB prescaler - name: HPRE - - bit_offset: 12 - bit_size: 3 - description: APB prescaler - name: PPRE - - bit_offset: 24 - bit_size: 3 - description: Microcontroller clock output - name: MCOSEL - - bit_offset: 28 - bit_size: 3 - description: Microcontroller clock output prescaler - name: MCOPRE + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 3 + - name: SWS + description: System clock switch status + bit_offset: 3 + bit_size: 3 + - name: HPRE + description: AHB prescaler + bit_offset: 8 + bit_size: 4 + - name: PPRE + description: APB prescaler + bit_offset: 12 + bit_size: 3 + - name: MCOSEL + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 fieldset/CICR: description: Clock interrupt clear register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready interrupt clear - name: LSIRDYC - - bit_offset: 1 - bit_size: 1 - description: LSE ready interrupt clear - name: LSERDYC - - bit_offset: 3 - bit_size: 1 - description: HSI ready interrupt clear - name: HSIRDYC - - bit_offset: 4 - bit_size: 1 - description: HSE ready interrupt clear - name: HSERDYC - - bit_offset: 5 - bit_size: 1 - description: PLL ready interrupt clear - name: PLLSYSRDYC - - bit_offset: 8 - bit_size: 1 - description: Clock security system interrupt clear - name: CSSC - - bit_offset: 9 - bit_size: 1 - description: LSE Clock security system interrupt clear - name: LSECSSC + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 1 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 4 + bit_size: 1 + - name: PLLSYSRDYC + description: PLL ready interrupt clear + bit_offset: 5 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: LSE Clock security system interrupt clear + bit_offset: 9 + bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready interrupt enable - name: LSIRDYIE - - bit_offset: 1 - bit_size: 1 - description: LSE ready interrupt enable - name: LSERDYIE - - bit_offset: 3 - bit_size: 1 - description: HSI ready interrupt enable - name: HSIRDYIE - - bit_offset: 4 - bit_size: 1 - description: HSE ready interrupt enable - name: HSERDYIE - - bit_offset: 5 - bit_size: 1 - description: PLL ready interrupt enable - name: PLLSYSRDYIE + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 1 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PLLSYSRDYIE + description: PLL ready interrupt enable + bit_offset: 5 + bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready interrupt flag - name: LSIRDYF - - bit_offset: 1 - bit_size: 1 - description: LSE ready interrupt flag - name: LSERDYF - - bit_offset: 3 - bit_size: 1 - description: HSI ready interrupt flag - name: HSIRDYF - - bit_offset: 4 - bit_size: 1 - description: HSE ready interrupt flag - name: HSERDYF - - bit_offset: 5 - bit_size: 1 - description: PLL ready interrupt flag - name: PLLSYSRDYF - - bit_offset: 8 - bit_size: 1 - description: Clock security system interrupt flag - name: CSSF - - bit_offset: 9 - bit_size: 1 - description: LSE Clock security system interrupt flag - name: LSECSSF + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLSYSRDYF + description: PLL ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: LSE Clock security system interrupt flag + bit_offset: 9 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - bit_offset: 8 - bit_size: 1 - description: HSI16 clock enable - name: HSION - - bit_offset: 9 - bit_size: 1 - description: HSI16 always enable for peripheral kernels - name: HSIKERON - - bit_offset: 10 - bit_size: 1 - description: HSI16 clock ready flag - name: HSIRDY - - bit_offset: 11 - bit_size: 3 - description: HSI16 clock division factor - name: HSIDIV - - bit_offset: 16 - bit_size: 1 - description: HSE clock enable - name: HSEON - - bit_offset: 17 - bit_size: 1 - description: HSE clock ready flag - name: HSERDY - - bit_offset: 18 - bit_size: 1 - description: HSE crystal oscillator bypass - name: HSEBYP - - bit_offset: 19 - bit_size: 1 - description: Clock security system enable - name: CSSON - - bit_offset: 24 - bit_size: 1 - description: PLL enable - name: PLLON - - bit_offset: 25 - bit_size: 1 - description: PLL clock ready flag - name: PLLRDY + - name: HSION + description: HSI16 clock enable + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: HSI16 always enable for peripheral kernels + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: HSI16 clock ready flag + bit_offset: 10 + bit_size: 1 + - name: HSIDIV + description: HSI16 clock division factor + bit_offset: 11 + bit_size: 3 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE crystal oscillator bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 fieldset/CSR: description: Control/status register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI oscillator enable - name: LSION - - bit_offset: 1 - bit_size: 1 - description: LSI oscillator ready - name: LSIRDY - - bit_offset: 23 - bit_size: 1 - description: Remove reset flags - name: RMVF - - bit_offset: 25 - bit_size: 1 - description: Option byte loader reset flag - name: OBLRSTF - - bit_offset: 26 - bit_size: 1 - description: Pin reset flag - name: PINRSTF - - bit_offset: 27 - bit_size: 1 - description: BOR or POR/PDR flag - name: PWRRSTF - - bit_offset: 28 - bit_size: 1 - description: Software reset flag - name: SFTRSTF - - bit_offset: 29 - bit_size: 1 - description: Independent window watchdog reset flag - name: IWDGRSTF - - bit_offset: 30 - bit_size: 1 - description: Window watchdog reset flag - name: WWDGRSTF - - bit_offset: 31 - bit_size: 1 - description: Low-power reset flag - name: LPWRRSTF + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flags + bit_offset: 23 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: Pin reset flag + bit_offset: 26 + bit_size: 1 + - name: PWRRSTF + description: BOR or POR/PDR flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent window watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - - bit_offset: 0 - bit_size: 8 - description: HSI16 clock calibration - name: HSICAL - - bit_offset: 8 - bit_size: 7 - description: HSI16 clock trimming - name: HSITRIM + - name: HSICAL + description: HSI16 clock calibration + bit_offset: 0 + bit_size: 8 + - name: HSITRIM + description: HSI16 clock trimming + bit_offset: 8 + bit_size: 7 fieldset/IOPENR: description: GPIO clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: I/O port A clock enable - name: GPIOAEN - - bit_offset: 1 - bit_size: 1 - description: I/O port B clock enable - name: GPIOBEN - - bit_offset: 2 - bit_size: 1 - description: I/O port C clock enable - name: GPIOCEN - - bit_offset: 3 - bit_size: 1 - description: I/O port D clock enable - name: GPIODEN - - bit_offset: 5 - bit_size: 1 - description: I/O port F clock enable - name: GPIOFEN + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOFEN + description: I/O port F clock enable + bit_offset: 5 + bit_size: 1 fieldset/IOPRSTR: description: GPIO reset register fields: - - bit_offset: 0 - bit_size: 1 - description: I/O port A reset - name: GPIOARST - - bit_offset: 1 - bit_size: 1 - description: I/O port B reset - name: GPIOBRST - - bit_offset: 2 - bit_size: 1 - description: I/O port C reset - name: GPIOCRST - - bit_offset: 3 - bit_size: 1 - description: I/O port D reset - name: GPIODRST - - bit_offset: 5 - bit_size: 1 - description: I/O port F reset - name: GPIOFRST + - name: GPIOARST + description: I/O port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: I/O port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: I/O port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: I/O port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOFRST + description: I/O port F reset + bit_offset: 5 + bit_size: 1 fieldset/IOPSMENR: description: GPIO in Sleep mode clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: I/O port A clock enable during Sleep mode - name: IOPASMEN - - bit_offset: 1 - bit_size: 1 - description: I/O port B clock enable during Sleep mode - name: IOPBSMEN - - bit_offset: 2 - bit_size: 1 - description: I/O port C clock enable during Sleep mode - name: IOPCSMEN - - bit_offset: 3 - bit_size: 1 - description: I/O port D clock enable during Sleep mode - name: IOPDSMEN - - bit_offset: 5 - bit_size: 1 - description: I/O port F clock enable during Sleep mode - name: IOPFSMEN + - name: IOPASMEN + description: I/O port A clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: IOPBSMEN + description: I/O port B clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: IOPCSMEN + description: I/O port C clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: IOPDSMEN + description: I/O port D clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: IOPFSMEN + description: I/O port F clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 fieldset/PLLSYSCFGR: description: PLL configuration register fields: - - bit_offset: 0 - bit_size: 2 - description: PLL input clock source - name: PLLSRC - - bit_offset: 4 - bit_size: 3 - description: Division factor M of the PLL input clock divider - name: PLLM - - bit_offset: 8 - bit_size: 7 - description: PLL frequency multiplication factor N - name: PLLN - - bit_offset: 16 - bit_size: 1 - description: PLLPCLK clock output enable - name: PLLPEN - - bit_offset: 17 - bit_size: 5 - description: PLL VCO division factor P for PLLPCLK clock output - name: PLLP - - bit_offset: 24 - bit_size: 1 - description: PLLQCLK clock output enable - name: PLLQEN - - bit_offset: 25 - bit_size: 3 - description: PLL VCO division factor Q for PLLQCLK clock output - name: PLLQ - - bit_offset: 28 - bit_size: 1 - description: PLLRCLK clock output enable - name: PLLREN - - bit_offset: 29 - bit_size: 3 - description: PLL VCO division factor R for PLLRCLK clock output - name: PLLR + - name: PLLSRC + description: PLL input clock source + bit_offset: 0 + bit_size: 2 + - name: PLLM + description: Division factor M of the PLL input clock divider + bit_offset: 4 + bit_size: 3 + - name: PLLN + description: PLL frequency multiplication factor N + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: PLLPCLK clock output enable + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: PLL VCO division factor P for PLLPCLK clock output + bit_offset: 17 + bit_size: 5 + - name: PLLQEN + description: PLLQCLK clock output enable + bit_offset: 24 + bit_size: 1 + - name: PLLQ + description: PLL VCO division factor Q for PLLQCLK clock output + bit_offset: 25 + bit_size: 3 + - name: PLLREN + description: PLLRCLK clock output enable + bit_offset: 28 + bit_size: 1 + - name: PLLR + description: PLL VCO division factor R for PLLRCLK clock output + bit_offset: 29 + bit_size: 3 diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index c1be37c..1d1af97 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -1,4493 +1,4494 @@ +--- block/RCC: description: Reset and clock control items: - - byte_offset: 0 - description: clock control register - fieldset: CR - name: CR - - byte_offset: 4 - description: RCC HSI configuration register - fieldset: HSICFGR - name: HSICFGR - - access: Read - byte_offset: 8 - description: RCC Clock Recovery RC Register - fieldset: CRRCR - name: CRRCR - - byte_offset: 12 - description: RCC CSI configuration register - fieldset: CSICFGR - name: CSICFGR - - byte_offset: 16 - description: RCC Clock Configuration Register - fieldset: CFGR - name: CFGR - - byte_offset: 24 - description: RCC Domain 1 Clock Configuration Register - fieldset: D1CFGR - name: D1CFGR - - byte_offset: 28 - description: RCC Domain 2 Clock Configuration Register - fieldset: D2CFGR - name: D2CFGR - - byte_offset: 32 - description: RCC Domain 3 Clock Configuration Register - fieldset: D3CFGR - name: D3CFGR - - byte_offset: 40 - description: RCC PLLs Clock Source Selection Register - fieldset: PLLCKSELR - name: PLLCKSELR - - byte_offset: 44 - description: RCC PLLs Configuration Register - fieldset: PLLCFGR - name: PLLCFGR - - array: - len: 3 - stride: 8 - byte_offset: 48 - description: RCC PLL1 Dividers Configuration Register - fieldset: PLL1DIVR - name: PLLDIVR - - array: - len: 3 - stride: 8 - byte_offset: 52 - description: RCC PLL1 Fractional Divider Register - fieldset: PLL1FRACR - name: PLLFRACR - - byte_offset: 76 - description: RCC Domain 1 Kernel Clock Configuration Register - fieldset: D1CCIPR - name: D1CCIPR - - byte_offset: 80 - description: RCC Domain 2 Kernel Clock Configuration Register - fieldset: D2CCIP1R - name: D2CCIP1R - - byte_offset: 84 - description: RCC Domain 2 Kernel Clock Configuration Register - fieldset: D2CCIP2R - name: D2CCIP2R - - byte_offset: 88 - description: RCC Domain 3 Kernel Clock Configuration Register - fieldset: D3CCIPR - name: D3CCIPR - - byte_offset: 96 - description: RCC Clock Source Interrupt Enable Register - fieldset: CIER - name: CIER - - access: Read - byte_offset: 100 - description: RCC Clock Source Interrupt Flag Register - fieldset: CIFR - name: CIFR - - byte_offset: 104 - description: RCC Clock Source Interrupt Clear Register - fieldset: CICR - name: CICR - - byte_offset: 112 - description: RCC Backup Domain Control Register - fieldset: BDCR - name: BDCR - - byte_offset: 116 - description: RCC Clock Control and Status Register - fieldset: CSR - name: CSR - - byte_offset: 124 - description: RCC AHB3 Reset Register - fieldset: AHB3RSTR - name: AHB3RSTR - - byte_offset: 128 - description: RCC AHB1 Peripheral Reset Register - fieldset: AHB1RSTR - name: AHB1RSTR - - byte_offset: 132 - description: RCC AHB2 Peripheral Reset Register - fieldset: AHB2RSTR - name: AHB2RSTR - - byte_offset: 136 - description: RCC AHB4 Peripheral Reset Register - fieldset: AHB4RSTR - name: AHB4RSTR - - byte_offset: 140 - description: RCC APB3 Peripheral Reset Register - fieldset: APB3RSTR - name: APB3RSTR - - byte_offset: 144 - description: RCC APB1 Peripheral Reset Register - fieldset: APB1LRSTR - name: APB1LRSTR - - byte_offset: 148 - description: RCC APB1 Peripheral Reset Register - fieldset: APB1HRSTR - name: APB1HRSTR - - byte_offset: 152 - description: RCC APB2 Peripheral Reset Register - fieldset: APB2RSTR - name: APB2RSTR - - byte_offset: 156 - description: RCC APB4 Peripheral Reset Register - fieldset: APB4RSTR - name: APB4RSTR - - byte_offset: 160 - description: RCC Global Control Register - fieldset: GCR - name: GCR - - byte_offset: 168 - description: RCC D3 Autonomous mode Register - fieldset: D3AMR - name: D3AMR - - byte_offset: 208 - description: RCC Reset Status Register - fieldset: RSR - name: RSR - - byte_offset: 212 - description: RCC AHB3 Clock Register - fieldset: AHB3ENR - name: AHB3ENR - - byte_offset: 216 - description: RCC AHB1 Clock Register - fieldset: AHB1ENR - name: AHB1ENR - - byte_offset: 220 - description: RCC AHB2 Clock Register - fieldset: AHB2ENR - name: AHB2ENR - - byte_offset: 224 - description: RCC AHB4 Clock Register - fieldset: AHB4ENR - name: AHB4ENR - - byte_offset: 228 - description: RCC APB3 Clock Register - fieldset: APB3ENR - name: APB3ENR - - byte_offset: 232 - description: RCC APB1 Clock Register - fieldset: APB1LENR - name: APB1LENR - - byte_offset: 236 - description: RCC APB1 Clock Register - fieldset: APB1HENR - name: APB1HENR - - byte_offset: 240 - description: RCC APB2 Clock Register - fieldset: APB2ENR - name: APB2ENR - - byte_offset: 244 - description: RCC APB4 Clock Register - fieldset: APB4ENR - name: APB4ENR - - byte_offset: 252 - description: RCC AHB3 Sleep Clock Register - fieldset: AHB3LPENR - name: AHB3LPENR - - byte_offset: 256 - description: RCC AHB1 Sleep Clock Register - fieldset: AHB1LPENR - name: AHB1LPENR - - byte_offset: 260 - description: RCC AHB2 Sleep Clock Register - fieldset: AHB2LPENR - name: AHB2LPENR - - byte_offset: 264 - description: RCC AHB4 Sleep Clock Register - fieldset: AHB4LPENR - name: AHB4LPENR - - byte_offset: 268 - description: RCC APB3 Sleep Clock Register - fieldset: APB3LPENR - name: APB3LPENR - - byte_offset: 272 - description: RCC APB1 Low Sleep Clock Register - fieldset: APB1LLPENR - name: APB1LLPENR - - byte_offset: 276 - description: RCC APB1 High Sleep Clock Register - fieldset: APB1HLPENR - name: APB1HLPENR - - byte_offset: 280 - description: RCC APB2 Sleep Clock Register - fieldset: APB2LPENR - name: APB2LPENR - - byte_offset: 284 - description: RCC APB4 Sleep Clock Register - fieldset: APB4LPENR - name: APB4LPENR - - byte_offset: 304 - description: RCC Reset Status Register - fieldset: C1_RSR - name: C1_RSR - - byte_offset: 308 - description: RCC AHB3 Clock Register - fieldset: C1_AHB3ENR - name: C1_AHB3ENR - - byte_offset: 312 - description: RCC AHB1 Clock Register - fieldset: C1_AHB1ENR - name: C1_AHB1ENR - - byte_offset: 316 - description: RCC AHB2 Clock Register - fieldset: C1_AHB2ENR - name: C1_AHB2ENR - - byte_offset: 320 - description: RCC AHB4 Clock Register - fieldset: C1_AHB4ENR - name: C1_AHB4ENR - - byte_offset: 324 - description: RCC APB3 Clock Register - fieldset: C1_APB3ENR - name: C1_APB3ENR - - byte_offset: 328 - description: RCC APB1 Clock Register - fieldset: C1_APB1LENR - name: C1_APB1LENR - - byte_offset: 332 - description: RCC APB1 Clock Register - fieldset: C1_APB1HENR - name: C1_APB1HENR - - byte_offset: 336 - description: RCC APB2 Clock Register - fieldset: C1_APB2ENR - name: C1_APB2ENR - - byte_offset: 340 - description: RCC APB4 Clock Register - fieldset: C1_APB4ENR - name: C1_APB4ENR - - byte_offset: 348 - description: RCC AHB3 Sleep Clock Register - fieldset: C1_AHB3LPENR - name: C1_AHB3LPENR - - byte_offset: 352 - description: RCC AHB1 Sleep Clock Register - fieldset: C1_AHB1LPENR - name: C1_AHB1LPENR - - byte_offset: 356 - description: RCC AHB2 Sleep Clock Register - fieldset: C1_AHB2LPENR - name: C1_AHB2LPENR - - byte_offset: 360 - description: RCC AHB4 Sleep Clock Register - fieldset: C1_AHB4LPENR - name: C1_AHB4LPENR - - byte_offset: 364 - description: RCC APB3 Sleep Clock Register - fieldset: C1_APB3LPENR - name: C1_APB3LPENR - - byte_offset: 368 - description: RCC APB1 Low Sleep Clock Register - fieldset: C1_APB1LLPENR - name: C1_APB1LLPENR - - byte_offset: 372 - description: RCC APB1 High Sleep Clock Register - fieldset: C1_APB1HLPENR - name: C1_APB1HLPENR - - byte_offset: 376 - description: RCC APB2 Sleep Clock Register - fieldset: C1_APB2LPENR - name: C1_APB2LPENR - - byte_offset: 380 - description: RCC APB4 Sleep Clock Register - fieldset: C1_APB4LPENR - name: C1_APB4LPENR -enum/ADCSEL: - bit_size: 2 - variants: - - description: pll2_p selected as peripheral clock - name: PLL2_P - value: 0 - - description: pll3_r selected as peripheral clock - name: PLL3_R - value: 1 - - description: PER selected as peripheral clock - name: PER - value: 2 -enum/CECSEL: - bit_size: 2 - variants: - - description: LSE selected as peripheral clock - name: LSE - value: 0 - - description: LSI selected as peripheral clock - name: LSI - value: 1 - - description: csi_ker selected as peripheral clock - name: CSI_KER - value: 2 -enum/CKPERSEL: - bit_size: 2 - variants: - - description: HSI selected as peripheral clock - name: HSI - value: 0 - - description: CSI selected as peripheral clock - name: CSI - value: 1 - - description: HSE selected as peripheral clock - name: HSE - value: 2 -enum/C_RSR_CPURSTFR: - bit_size: 1 - variants: - - description: No reset occoured for block - name: NoResetOccoured - value: 0 - - description: Reset occoured for block - name: ResetOccourred - value: 1 -enum/C_RSR_RMVF: - bit_size: 1 - variants: - - description: Not clearing the the reset flags - name: NotActive - value: 0 - - description: Clear the reset flags - name: Clear - value: 1 -enum/DFSDMSEL: - bit_size: 1 - variants: - - description: rcc_pclk2 selected as peripheral clock - name: RCC_PCLK2 - value: 0 - - description: System clock selected as peripheral clock - name: SYS - value: 1 -enum/DIVP: - bit_size: 7 - variants: - - description: pll_p_ck = vco_ck - name: Div1 - value: 0 - - description: pll_p_ck = vco_ck / 2 - name: Div2 - value: 1 - - description: pll_p_ck = vco_ck / 4 - name: Div4 - value: 3 - - description: pll_p_ck = vco_ck / 6 - name: Div6 - value: 5 - - description: pll_p_ck = vco_ck / 8 - name: Div8 - value: 7 - - description: pll_p_ck = vco_ck / 10 - name: Div10 - value: 9 - - description: pll_p_ck = vco_ck / 12 - name: Div12 - value: 11 - - description: pll_p_ck = vco_ck / 14 - name: Div14 - value: 13 - - description: pll_p_ck = vco_ck / 16 - name: Div16 - value: 15 - - description: pll_p_ck = vco_ck / 18 - name: Div18 - value: 17 - - description: pll_p_ck = vco_ck / 20 - name: Div20 - value: 19 - - description: pll_p_ck = vco_ck / 22 - name: Div22 - value: 21 - - description: pll_p_ck = vco_ck / 24 - name: Div24 - value: 23 - - description: pll_p_ck = vco_ck / 26 - name: Div26 - value: 25 - - description: pll_p_ck = vco_ck / 28 - name: Div28 - value: 27 - - description: pll_p_ck = vco_ck / 30 - name: Div30 - value: 29 - - description: pll_p_ck = vco_ck / 32 - name: Div32 - value: 31 - - description: pll_p_ck = vco_ck / 34 - name: Div34 - value: 33 - - description: pll_p_ck = vco_ck / 36 - name: Div36 - value: 35 - - description: pll_p_ck = vco_ck / 38 - name: Div38 - value: 37 - - description: pll_p_ck = vco_ck / 40 - name: Div40 - value: 39 - - description: pll_p_ck = vco_ck / 42 - name: Div42 - value: 41 - - description: pll_p_ck = vco_ck / 44 - name: Div44 - value: 43 - - description: pll_p_ck = vco_ck / 46 - name: Div46 - value: 45 - - description: pll_p_ck = vco_ck / 48 - name: Div48 - value: 47 - - description: pll_p_ck = vco_ck / 50 - name: Div50 - value: 49 - - description: pll_p_ck = vco_ck / 52 - name: Div52 - value: 51 - - description: pll_p_ck = vco_ck / 54 - name: Div54 - value: 53 - - description: pll_p_ck = vco_ck / 56 - name: Div56 - value: 55 - - description: pll_p_ck = vco_ck / 58 - name: Div58 - value: 57 - - description: pll_p_ck = vco_ck / 60 - name: Div60 - value: 59 - - description: pll_p_ck = vco_ck / 62 - name: Div62 - value: 61 - - description: pll_p_ck = vco_ck / 64 - name: Div64 - value: 63 - - description: pll_p_ck = vco_ck / 66 - name: Div66 - value: 65 - - description: pll_p_ck = vco_ck / 68 - name: Div68 - value: 67 - - description: pll_p_ck = vco_ck / 70 - name: Div70 - value: 69 - - description: pll_p_ck = vco_ck / 72 - name: Div72 - value: 71 - - description: pll_p_ck = vco_ck / 74 - name: Div74 - value: 73 - - description: pll_p_ck = vco_ck / 76 - name: Div76 - value: 75 - - description: pll_p_ck = vco_ck / 78 - name: Div78 - value: 77 - - description: pll_p_ck = vco_ck / 80 - name: Div80 - value: 79 - - description: pll_p_ck = vco_ck / 82 - name: Div82 - value: 81 - - description: pll_p_ck = vco_ck / 84 - name: Div84 - value: 83 - - description: pll_p_ck = vco_ck / 86 - name: Div86 - value: 85 - - description: pll_p_ck = vco_ck / 88 - name: Div88 - value: 87 - - description: pll_p_ck = vco_ck / 90 - name: Div90 - value: 89 - - description: pll_p_ck = vco_ck / 92 - name: Div92 - value: 91 - - description: pll_p_ck = vco_ck / 94 - name: Div94 - value: 93 - - description: pll_p_ck = vco_ck / 96 - name: Div96 - value: 95 - - description: pll_p_ck = vco_ck / 98 - name: Div98 - value: 97 - - description: pll_p_ck = vco_ck / 100 - name: Div100 - value: 99 - - description: pll_p_ck = vco_ck / 102 - name: Div102 - value: 101 - - description: pll_p_ck = vco_ck / 104 - name: Div104 - value: 103 - - description: pll_p_ck = vco_ck / 106 - name: Div106 - value: 105 - - description: pll_p_ck = vco_ck / 108 - name: Div108 - value: 107 - - description: pll_p_ck = vco_ck / 110 - name: Div110 - value: 109 - - description: pll_p_ck = vco_ck / 112 - name: Div112 - value: 111 - - description: pll_p_ck = vco_ck / 114 - name: Div114 - value: 113 - - description: pll_p_ck = vco_ck / 116 - name: Div116 - value: 115 - - description: pll_p_ck = vco_ck / 118 - name: Div118 - value: 117 - - description: pll_p_ck = vco_ck / 120 - name: Div120 - value: 119 - - description: pll_p_ck = vco_ck / 122 - name: Div122 - value: 121 - - description: pll_p_ck = vco_ck / 124 - name: Div124 - value: 123 - - description: pll_p_ck = vco_ck / 126 - name: Div126 - value: 125 - - description: pll_p_ck = vco_ck / 128 - name: Div128 - value: 127 -enum/DPPRE: - bit_size: 3 - variants: - - description: rcc_hclk not divided - name: Div1 - value: 0 - - description: rcc_hclk divided by 2 - name: Div2 - value: 4 - - description: rcc_hclk divided by 4 - name: Div4 - value: 5 - - description: rcc_hclk divided by 8 - name: Div8 - value: 6 - - description: rcc_hclk divided by 16 - name: Div16 - value: 7 -enum/FDCANSEL: - bit_size: 2 - variants: - - description: HSE selected as peripheral clock - name: HSE - value: 0 - - description: pll1_q selected as peripheral clock - name: PLL1_Q - value: 1 - - description: pll2_q selected as peripheral clock - name: PLL2_Q - value: 2 -enum/FMCSEL: - bit_size: 2 - variants: - - description: rcc_hclk3 selected as peripheral clock - name: RCC_HCLK3 - value: 0 - - description: pll1_q selected as peripheral clock - name: PLL1_Q - value: 1 - - description: pll2_r selected as peripheral clock - name: PLL2_R - value: 2 - - description: PER selected as peripheral clock - name: PER - value: 3 -enum/HPRE: - bit_size: 4 - variants: - - description: sys_ck not divided - name: Div1 - value: 0 - - description: sys_ck divided by 2 - name: Div2 - value: 8 - - description: sys_ck divided by 4 - name: Div4 - value: 9 - - description: sys_ck divided by 8 - name: Div8 - value: 10 - - description: sys_ck divided by 16 - name: Div16 - value: 11 - - description: sys_ck divided by 64 - name: Div64 - value: 12 - - description: sys_ck divided by 128 - name: Div128 - value: 13 - - description: sys_ck divided by 256 - name: Div256 - value: 14 - - description: sys_ck divided by 512 - name: Div512 - value: 15 -enum/HRTIMSEL: - bit_size: 1 - variants: - - description: The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) - name: TIMY_KER - value: 0 - - description: The HRTIM prescaler clock source is the CPU clock (c_ck) - name: C_CK - value: 1 -enum/HSEBYP: - bit_size: 1 - variants: - - description: HSE crystal oscillator not bypassed - name: NotBypassed - value: 0 - - description: HSE crystal oscillator bypassed with external clock - name: Bypassed - value: 1 -enum/HSIDIV: - bit_size: 2 - variants: - - description: No division - name: Div1 - value: 0 - - description: Division by 2 - name: Div2 - value: 1 - - description: Division by 4 - name: Div4 - value: 2 - - description: Division by 8 - name: Div8 - value: 3 -enum/HSIDIVFR: - bit_size: 1 - variants: - - description: New HSIDIV ratio has not yet propagated to hsi_ck - name: NotPropagated - value: 0 - - description: HSIDIV ratio has propagated to hsi_ck - name: Propagated - value: 1 -enum/HSIRDYR: - bit_size: 1 - variants: - - description: Clock not ready - name: NotReady - value: 0 - - description: Clock ready - name: Ready - value: 1 -enum/I2C1235SEL: - bit_size: 2 - variants: - - description: rcc_pclk1 selected as peripheral clock - name: RCC_PCLK1 - value: 0 - - description: pll3_r selected as peripheral clock - name: PLL3_R - value: 1 - - description: hsi_ker selected as peripheral clock - name: HSI_KER - value: 2 - - description: csi_ker selected as peripheral clock - name: CSI_KER - value: 3 -enum/I2C4SEL: - bit_size: 2 - variants: - - description: rcc_pclk4 selected as peripheral clock - name: RCC_PCLK4 - value: 0 - - description: pll3_r selected as peripheral clock - name: PLL3_R - value: 1 - - description: hsi_ker selected as peripheral clock - name: HSI_KER - value: 2 - - description: csi_ker selected as peripheral clock - name: CSI_KER - value: 3 -enum/LPTIM1SEL: - bit_size: 3 - variants: - - description: rcc_pclk1 selected as peripheral clock - name: RCC_PCLK1 - value: 0 - - description: pll2_p selected as peripheral clock - name: PLL2_P - value: 1 - - description: pll3_r selected as peripheral clock - name: PLL3_R - value: 2 - - description: LSE selected as peripheral clock - name: LSE - value: 3 - - description: LSI selected as peripheral clock - name: LSI - value: 4 - - description: PER selected as peripheral clock - name: PER - value: 5 -enum/LPTIM2SEL: - bit_size: 3 - variants: - - description: rcc_pclk4 selected as peripheral clock - name: RCC_PCLK4 - value: 0 - - description: pll2_p selected as peripheral clock - name: PLL2_P - value: 1 - - description: pll3_r selected as peripheral clock - name: PLL3_R - value: 2 - - description: LSE selected as peripheral clock - name: LSE - value: 3 - - description: LSI selected as peripheral clock - name: LSI - value: 4 - - description: PER selected as peripheral clock - name: PER - value: 5 -enum/LPUARTSEL: - bit_size: 3 - variants: - - description: rcc_pclk_d3 selected as peripheral clock - name: RCC_PCLK_D3 - value: 0 - - description: pll2_q selected as peripheral clock - name: PLL2_Q - value: 1 - - description: pll3_q selected as peripheral clock - name: PLL3_Q - value: 2 - - description: hsi_ker selected as peripheral clock - name: HSI_KER - value: 3 - - description: csi_ker selected as peripheral clock - name: CSI_KER - value: 4 - - description: LSE selected as peripheral clock - name: LSE - value: 5 -enum/LSEBYP: - bit_size: 1 - variants: - - description: LSE crystal oscillator not bypassed - name: NotBypassed - value: 0 - - description: LSE crystal oscillator bypassed with external clock - name: Bypassed - value: 1 -enum/LSECSSDR: - bit_size: 1 - variants: - - description: No failure detected on 32 kHz oscillator - name: NoFailure - value: 0 - - description: Failure detected on 32 kHz oscillator - name: Failure - value: 1 -enum/LSEDRV: - bit_size: 2 - variants: - - description: Lowest LSE oscillator driving capability - name: Lowest - value: 0 - - description: Medium low LSE oscillator driving capability - name: MediumLow - value: 1 - - description: Medium high LSE oscillator driving capability - name: MediumHigh - value: 2 - - description: Highest LSE oscillator driving capability - name: Highest - value: 3 -enum/LSERDYR: - bit_size: 1 - variants: - - description: LSE oscillator not ready - name: NotReady - value: 0 - - description: LSE oscillator ready - name: Ready - value: 1 -enum/LSIRDYC: - bit_size: 1 - variants: - - description: Clear interrupt flag - name: Clear - value: 1 -enum/LSIRDYIE: - bit_size: 1 - variants: - - description: Interrupt disabled - name: Disabled - value: 0 - - description: Interrupt enabled - name: Enabled - value: 1 -enum/LSIRDYR: - bit_size: 1 - variants: - - description: LSI oscillator not ready - name: NotReady - value: 0 - - description: LSI oscillator ready - name: Ready - value: 1 -enum/MCO1: - bit_size: 3 - variants: - - description: HSI selected for micro-controller clock output - name: HSI - value: 0 - - description: LSE selected for micro-controller clock output - name: LSE - value: 1 - - description: HSE selected for micro-controller clock output - name: HSE - value: 2 - - description: pll1_q selected for micro-controller clock output - name: PLL1_Q - value: 3 - - description: HSI48 selected for micro-controller clock output - name: HSI48 - value: 4 -enum/MCO2: - bit_size: 3 - variants: - - description: System clock selected for micro-controller clock output - name: SYSCLK - value: 0 - - description: pll2_p selected for micro-controller clock output - name: PLL2_P - value: 1 - - description: HSE selected for micro-controller clock output - name: HSE - value: 2 - - description: pll1_p selected for micro-controller clock output - name: PLL1_P - value: 3 - - description: CSI selected for micro-controller clock output - name: CSI - value: 4 - - description: LSI selected for micro-controller clock output - name: LSI - value: 5 -enum/PLLRGE: - bit_size: 2 - variants: - - description: Frequency is between 1 and 2 MHz - name: Range1 - value: 0 - - description: Frequency is between 2 and 4 MHz - name: Range2 - value: 1 - - description: Frequency is between 4 and 8 MHz - name: Range4 - value: 2 - - description: Frequency is between 8 and 16 MHz - name: Range8 - value: 3 -enum/PLLSRC: - bit_size: 2 - variants: - - description: HSI selected as PLL clock - name: HSI - value: 0 - - description: CSI selected as PLL clock - name: CSI - value: 1 - - description: HSE selected as PLL clock - name: HSE - value: 2 - - description: No clock sent to DIVMx dividers and PLLs - name: None - value: 3 -enum/PLLVCOSEL: - bit_size: 1 - variants: - - description: VCO frequency range 192 to 836 MHz - name: WideVCO - value: 0 - - description: VCO frequency range 150 to 420 MHz - name: MediumVCO - value: 1 -enum/RNGSEL: - bit_size: 2 - variants: - - description: HSI48 selected as peripheral clock - name: HSI48 - value: 0 - - description: pll1_q selected as peripheral clock - name: PLL1_Q - value: 1 - - description: LSE selected as peripheral clock - name: LSE - value: 2 - - description: LSI selected as peripheral clock - name: LSI - value: 3 -enum/RSR_CPURSTFR: - bit_size: 1 - variants: - - description: No reset occoured for block - name: NoResetOccoured - value: 0 - - description: Reset occoured for block - name: ResetOccourred - value: 1 -enum/RSR_RMVF: - bit_size: 1 - variants: - - description: Not clearing the the reset flags - name: NotActive - value: 0 - - description: Clear the reset flags - name: Clear - value: 1 -enum/RTCSEL: - bit_size: 2 - variants: - - description: No clock - name: NoClock - value: 0 - - description: LSE oscillator clock used as RTC clock - name: LSE - value: 1 - - description: LSI oscillator clock used as RTC clock - name: LSI - value: 2 - - description: HSE oscillator clock divided by a prescaler used as RTC clock - name: HSE - value: 3 -enum/SAIASEL: - bit_size: 3 - variants: - - description: pll1_q selected as peripheral clock - name: PLL1_Q - value: 0 - - description: pll2_p selected as peripheral clock - name: PLL2_P - value: 1 - - description: pll3_p selected as peripheral clock - name: PLL3_P - value: 2 - - description: i2s_ckin selected as peripheral clock - name: I2S_CKIN - value: 3 - - description: PER selected as peripheral clock - name: PER - value: 4 -enum/SAISEL: - bit_size: 3 - variants: - - description: pll1_q selected as peripheral clock - name: PLL1_Q - value: 0 - - description: pll2_p selected as peripheral clock - name: PLL2_P - value: 1 - - description: pll3_p selected as peripheral clock - name: PLL3_P - value: 2 - - description: I2S_CKIN selected as peripheral clock - name: I2S_CKIN - value: 3 - - description: PER selected as peripheral clock - name: PER - value: 4 -enum/SDMMCSEL: - bit_size: 1 - variants: - - description: pll1_q selected as peripheral clock - name: PLL1_Q - value: 0 - - description: pll2_r selected as peripheral clock - name: PLL2_R - value: 1 -enum/SPDIFSEL: - bit_size: 2 - variants: - - description: pll1_q selected as peripheral clock - name: PLL1_Q - value: 0 - - description: pll2_r selected as peripheral clock - name: PLL2_R - value: 1 - - description: pll3_r selected as peripheral clock - name: PLL3_R - value: 2 - - description: hsi_ker selected as peripheral clock - name: HSI_KER - value: 3 -enum/SPI45SEL: - bit_size: 3 - variants: - - description: APB clock selected as peripheral clock - name: APB - value: 0 - - description: pll2_q selected as peripheral clock - name: PLL2_Q - value: 1 - - description: pll3_q selected as peripheral clock - name: PLL3_Q - value: 2 - - description: hsi_ker selected as peripheral clock - name: HSI_KER - value: 3 - - description: csi_ker selected as peripheral clock - name: CSI_KER - value: 4 - - description: HSE selected as peripheral clock - name: HSE - value: 5 -enum/SPI6SEL: - bit_size: 3 - variants: - - description: rcc_pclk4 selected as peripheral clock - name: RCC_PCLK4 - value: 0 - - description: pll2_q selected as peripheral clock - name: PLL2_Q - value: 1 - - description: pll3_q selected as peripheral clock - name: PLL3_Q - value: 2 - - description: hsi_ker selected as peripheral clock - name: HSI_KER - value: 3 - - description: csi_ker selected as peripheral clock - name: CSI_KER - value: 4 - - description: HSE selected as peripheral clock - name: HSE - value: 5 -enum/STOPWUCK: - bit_size: 1 - variants: - - description: HSI selected as wake up clock from system Stop - name: HSI - value: 0 - - description: CSI selected as wake up clock from system Stop - name: CSI - value: 1 -enum/SW: - bit_size: 3 - variants: - - description: HSI selected as system clock - name: HSI - value: 0 - - description: CSI selected as system clock - name: CSI - value: 1 - - description: HSE selected as system clock - name: HSE - value: 2 - - description: PLL1 selected as system clock - name: PLL1 - value: 3 -enum/SWPSEL: - bit_size: 1 - variants: - - description: pclk selected as peripheral clock - name: PCLK - value: 0 - - description: hsi_ker selected as peripheral clock - name: HSI_KER - value: 1 -enum/SWSR: - bit_size: 3 - variants: - - description: HSI oscillator used as system clock - name: HSI - value: 0 - - description: CSI oscillator used as system clock - name: CSI - value: 1 - - description: HSE oscillator used as system clock - name: HSE - value: 2 - - description: PLL1 used as system clock - name: PLL1 - value: 3 -enum/TIMPRE: - bit_size: 1 - variants: - - description: Timer kernel clock equal to 2x pclk by default - name: DefaultX2 - value: 0 - - description: Timer kernel clock equal to 4x pclk by default - name: DefaultX4 - value: 1 -enum/USART16910SEL: - bit_size: 3 - variants: - - description: rcc_pclk2 selected as peripheral clock - name: RCC_PCLK2 - value: 0 - - description: pll2_q selected as peripheral clock - name: PLL2_Q - value: 1 - - description: pll3_q selected as peripheral clock - name: PLL3_Q - value: 2 - - description: hsi_ker selected as peripheral clock - name: HSI_KER - value: 3 - - description: csi_ker selected as peripheral clock - name: CSI_KER - value: 4 - - description: LSE selected as peripheral clock - name: LSE - value: 5 -enum/USART234578SEL: - bit_size: 3 - variants: - - description: rcc_pclk1 selected as peripheral clock - name: RCC_PCLK1 - value: 0 - - description: pll2_q selected as peripheral clock - name: PLL2_Q - value: 1 - - description: pll3_q selected as peripheral clock - name: PLL3_Q - value: 2 - - description: hsi_ker selected as peripheral clock - name: HSI_KER - value: 3 - - description: csi_ker selected as peripheral clock - name: CSI_KER - value: 4 - - description: LSE selected as peripheral clock - name: LSE - value: 5 -enum/USBSEL: - bit_size: 2 - variants: - - description: Disable the kernel clock - name: DISABLE - value: 0 - - description: pll1_q selected as peripheral clock - name: PLL1_Q - value: 1 - - description: pll3_q selected as peripheral clock - name: PLL3_Q - value: 2 - - description: HSI48 selected as peripheral clock - name: HSI48 - value: 3 -enum/WWRSC: - bit_size: 1 - variants: - - description: Clear WWDG1 scope control - name: Clear - value: 0 - - description: Set WWDG1 scope control - name: Set - value: 1 + - name: CR + description: clock control register + byte_offset: 0 + fieldset: CR + - name: HSICFGR + description: RCC HSI configuration register + byte_offset: 4 + fieldset: HSICFGR + - name: CRRCR + description: RCC Clock Recovery RC Register + byte_offset: 8 + access: Read + fieldset: CRRCR + - name: CSICFGR + description: RCC CSI configuration register + byte_offset: 12 + fieldset: CSICFGR + - name: CFGR + description: RCC Clock Configuration Register + byte_offset: 16 + fieldset: CFGR + - name: D1CFGR + description: RCC Domain 1 Clock Configuration Register + byte_offset: 24 + fieldset: D1CFGR + - name: D2CFGR + description: RCC Domain 2 Clock Configuration Register + byte_offset: 28 + fieldset: D2CFGR + - name: D3CFGR + description: RCC Domain 3 Clock Configuration Register + byte_offset: 32 + fieldset: D3CFGR + - name: PLLCKSELR + description: RCC PLLs Clock Source Selection Register + byte_offset: 40 + fieldset: PLLCKSELR + - name: PLLCFGR + description: RCC PLLs Configuration Register + byte_offset: 44 + fieldset: PLLCFGR + - name: PLLDIVR + description: RCC PLL1 Dividers Configuration Register + array: + len: 3 + stride: 8 + byte_offset: 48 + fieldset: PLL1DIVR + - name: PLLFRACR + description: RCC PLL1 Fractional Divider Register + array: + len: 3 + stride: 8 + byte_offset: 52 + fieldset: PLL1FRACR + - name: D1CCIPR + description: RCC Domain 1 Kernel Clock Configuration Register + byte_offset: 76 + fieldset: D1CCIPR + - name: D2CCIP1R + description: RCC Domain 2 Kernel Clock Configuration Register + byte_offset: 80 + fieldset: D2CCIP1R + - name: D2CCIP2R + description: RCC Domain 2 Kernel Clock Configuration Register + byte_offset: 84 + fieldset: D2CCIP2R + - name: D3CCIPR + description: RCC Domain 3 Kernel Clock Configuration Register + byte_offset: 88 + fieldset: D3CCIPR + - name: CIER + description: RCC Clock Source Interrupt Enable Register + byte_offset: 96 + fieldset: CIER + - name: CIFR + description: RCC Clock Source Interrupt Flag Register + byte_offset: 100 + access: Read + fieldset: CIFR + - name: CICR + description: RCC Clock Source Interrupt Clear Register + byte_offset: 104 + fieldset: CICR + - name: BDCR + description: RCC Backup Domain Control Register + byte_offset: 112 + fieldset: BDCR + - name: CSR + description: RCC Clock Control and Status Register + byte_offset: 116 + fieldset: CSR + - name: AHB3RSTR + description: RCC AHB3 Reset Register + byte_offset: 124 + fieldset: AHB3RSTR + - name: AHB1RSTR + description: RCC AHB1 Peripheral Reset Register + byte_offset: 128 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: RCC AHB2 Peripheral Reset Register + byte_offset: 132 + fieldset: AHB2RSTR + - name: AHB4RSTR + description: RCC AHB4 Peripheral Reset Register + byte_offset: 136 + fieldset: AHB4RSTR + - name: APB3RSTR + description: RCC APB3 Peripheral Reset Register + byte_offset: 140 + fieldset: APB3RSTR + - name: APB1LRSTR + description: RCC APB1 Peripheral Reset Register + byte_offset: 144 + fieldset: APB1LRSTR + - name: APB1HRSTR + description: RCC APB1 Peripheral Reset Register + byte_offset: 148 + fieldset: APB1HRSTR + - name: APB2RSTR + description: RCC APB2 Peripheral Reset Register + byte_offset: 152 + fieldset: APB2RSTR + - name: APB4RSTR + description: RCC APB4 Peripheral Reset Register + byte_offset: 156 + fieldset: APB4RSTR + - name: GCR + description: RCC Global Control Register + byte_offset: 160 + fieldset: GCR + - name: D3AMR + description: RCC D3 Autonomous mode Register + byte_offset: 168 + fieldset: D3AMR + - name: RSR + description: RCC Reset Status Register + byte_offset: 208 + fieldset: RSR + - name: AHB3ENR + description: RCC AHB3 Clock Register + byte_offset: 212 + fieldset: AHB3ENR + - name: AHB1ENR + description: RCC AHB1 Clock Register + byte_offset: 216 + fieldset: AHB1ENR + - name: AHB2ENR + description: RCC AHB2 Clock Register + byte_offset: 220 + fieldset: AHB2ENR + - name: AHB4ENR + description: RCC AHB4 Clock Register + byte_offset: 224 + fieldset: AHB4ENR + - name: APB3ENR + description: RCC APB3 Clock Register + byte_offset: 228 + fieldset: APB3ENR + - name: APB1LENR + description: RCC APB1 Clock Register + byte_offset: 232 + fieldset: APB1LENR + - name: APB1HENR + description: RCC APB1 Clock Register + byte_offset: 236 + fieldset: APB1HENR + - name: APB2ENR + description: RCC APB2 Clock Register + byte_offset: 240 + fieldset: APB2ENR + - name: APB4ENR + description: RCC APB4 Clock Register + byte_offset: 244 + fieldset: APB4ENR + - name: AHB3LPENR + description: RCC AHB3 Sleep Clock Register + byte_offset: 252 + fieldset: AHB3LPENR + - name: AHB1LPENR + description: RCC AHB1 Sleep Clock Register + byte_offset: 256 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: RCC AHB2 Sleep Clock Register + byte_offset: 260 + fieldset: AHB2LPENR + - name: AHB4LPENR + description: RCC AHB4 Sleep Clock Register + byte_offset: 264 + fieldset: AHB4LPENR + - name: APB3LPENR + description: RCC APB3 Sleep Clock Register + byte_offset: 268 + fieldset: APB3LPENR + - name: APB1LLPENR + description: RCC APB1 Low Sleep Clock Register + byte_offset: 272 + fieldset: APB1LLPENR + - name: APB1HLPENR + description: RCC APB1 High Sleep Clock Register + byte_offset: 276 + fieldset: APB1HLPENR + - name: APB2LPENR + description: RCC APB2 Sleep Clock Register + byte_offset: 280 + fieldset: APB2LPENR + - name: APB4LPENR + description: RCC APB4 Sleep Clock Register + byte_offset: 284 + fieldset: APB4LPENR + - name: C1_RSR + description: RCC Reset Status Register + byte_offset: 304 + fieldset: C1_RSR + - name: C1_AHB3ENR + description: RCC AHB3 Clock Register + byte_offset: 308 + fieldset: C1_AHB3ENR + - name: C1_AHB1ENR + description: RCC AHB1 Clock Register + byte_offset: 312 + fieldset: C1_AHB1ENR + - name: C1_AHB2ENR + description: RCC AHB2 Clock Register + byte_offset: 316 + fieldset: C1_AHB2ENR + - name: C1_AHB4ENR + description: RCC AHB4 Clock Register + byte_offset: 320 + fieldset: C1_AHB4ENR + - name: C1_APB3ENR + description: RCC APB3 Clock Register + byte_offset: 324 + fieldset: C1_APB3ENR + - name: C1_APB1LENR + description: RCC APB1 Clock Register + byte_offset: 328 + fieldset: C1_APB1LENR + - name: C1_APB1HENR + description: RCC APB1 Clock Register + byte_offset: 332 + fieldset: C1_APB1HENR + - name: C1_APB2ENR + description: RCC APB2 Clock Register + byte_offset: 336 + fieldset: C1_APB2ENR + - name: C1_APB4ENR + description: RCC APB4 Clock Register + byte_offset: 340 + fieldset: C1_APB4ENR + - name: C1_AHB3LPENR + description: RCC AHB3 Sleep Clock Register + byte_offset: 348 + fieldset: C1_AHB3LPENR + - name: C1_AHB1LPENR + description: RCC AHB1 Sleep Clock Register + byte_offset: 352 + fieldset: C1_AHB1LPENR + - name: C1_AHB2LPENR + description: RCC AHB2 Sleep Clock Register + byte_offset: 356 + fieldset: C1_AHB2LPENR + - name: C1_AHB4LPENR + description: RCC AHB4 Sleep Clock Register + byte_offset: 360 + fieldset: C1_AHB4LPENR + - name: C1_APB3LPENR + description: RCC APB3 Sleep Clock Register + byte_offset: 364 + fieldset: C1_APB3LPENR + - name: C1_APB1LLPENR + description: RCC APB1 Low Sleep Clock Register + byte_offset: 368 + fieldset: C1_APB1LLPENR + - name: C1_APB1HLPENR + description: RCC APB1 High Sleep Clock Register + byte_offset: 372 + fieldset: C1_APB1HLPENR + - name: C1_APB2LPENR + description: RCC APB2 Sleep Clock Register + byte_offset: 376 + fieldset: C1_APB2LPENR + - name: C1_APB4LPENR + description: RCC APB4 Sleep Clock Register + byte_offset: 380 + fieldset: C1_APB4LPENR fieldset/AHB1ENR: description: RCC AHB1 Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA1 Clock Enable - name: DMA1EN - - bit_offset: 1 - bit_size: 1 - description: DMA2 Clock Enable - name: DMA2EN - - bit_offset: 5 - bit_size: 1 - description: ADC1/2 Peripheral Clocks Enable - name: ADC12EN - - bit_offset: 14 - bit_size: 1 - description: ART Clock Enable - name: ARTEN - - bit_offset: 15 - bit_size: 1 - description: Ethernet MAC bus interface Clock Enable - name: ETH1MACEN - - bit_offset: 16 - bit_size: 1 - description: Ethernet Transmission Clock Enable - name: ETH1TXEN - - bit_offset: 17 - bit_size: 1 - description: Ethernet Reception Clock Enable - name: ETH1RXEN - - bit_offset: 18 - bit_size: 1 - description: ' Enable USB_PHY2 clocks ' - name: USB2OTGHSULPIEN - - bit_offset: 25 - bit_size: 1 - description: USB1OTG Peripheral Clocks Enable - name: USB1OTGEN - - bit_offset: 26 - bit_size: 1 - description: USB_PHY1 Clocks Enable - name: USB1ULPIEN - - bit_offset: 27 - bit_size: 1 - description: USB2OTG Peripheral Clocks Enable - name: USB2OTGEN - - bit_offset: 28 - bit_size: 1 - description: USB_PHY2 Clocks Enable - name: USB2ULPIEN + - name: DMA1EN + description: DMA1 Clock Enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 Clock Enable + bit_offset: 1 + bit_size: 1 + - name: ADC12EN + description: ADC1/2 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: ARTEN + description: ART Clock Enable + bit_offset: 14 + bit_size: 1 + - name: ETH1MACEN + description: Ethernet MAC bus interface Clock Enable + bit_offset: 15 + bit_size: 1 + - name: ETH1TXEN + description: Ethernet Transmission Clock Enable + bit_offset: 16 + bit_size: 1 + - name: ETH1RXEN + description: Ethernet Reception Clock Enable + bit_offset: 17 + bit_size: 1 + - name: USB2OTGHSULPIEN + description: " Enable USB_PHY2 clocks " + bit_offset: 18 + bit_size: 1 + - name: USB1OTGEN + description: USB1OTG Peripheral Clocks Enable + bit_offset: 25 + bit_size: 1 + - name: USB1ULPIEN + description: USB_PHY1 Clocks Enable + bit_offset: 26 + bit_size: 1 + - name: USB2OTGEN + description: USB2OTG Peripheral Clocks Enable + bit_offset: 27 + bit_size: 1 + - name: USB2ULPIEN + description: USB_PHY2 Clocks Enable + bit_offset: 28 + bit_size: 1 fieldset/AHB1LPENR: description: RCC AHB1 Sleep Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA1 Clock Enable During CSleep Mode - name: DMA1LPEN - - bit_offset: 1 - bit_size: 1 - description: DMA2 Clock Enable During CSleep Mode - name: DMA2LPEN - - bit_offset: 5 - bit_size: 1 - description: ADC1/2 Peripheral Clocks Enable During CSleep Mode - name: ADC12LPEN - - bit_offset: 14 - bit_size: 1 - description: ART Clock Enable During CSleep Mode - name: ARTLPEN - - bit_offset: 15 - bit_size: 1 - description: Ethernet MAC bus interface Clock Enable During CSleep Mode - name: ETH1MACLPEN - - bit_offset: 16 - bit_size: 1 - description: Ethernet Transmission Clock Enable During CSleep Mode - name: ETH1TXLPEN - - bit_offset: 17 - bit_size: 1 - description: Ethernet Reception Clock Enable During CSleep Mode - name: ETH1RXLPEN - - bit_offset: 25 - bit_size: 1 - description: USB1OTG peripheral clock enable during CSleep mode - name: USB1OTGLPEN - - bit_offset: 26 - bit_size: 1 - description: USB_PHY1 clock enable during CSleep mode - name: USB1OTGHSULPILPEN - - bit_offset: 26 - bit_size: 1 - description: USB_PHY1 clock enable during CSleep mode - name: USB1ULPILPEN - - bit_offset: 27 - bit_size: 1 - description: USB2OTG peripheral clock enable during CSleep mode - name: USB2OTGLPEN - - bit_offset: 28 - bit_size: 1 - description: USB_PHY2 clocks enable during CSleep mode - name: USB2OTGHSULPILPEN - - bit_offset: 28 - bit_size: 1 - description: USB_PHY2 clocks enable during CSleep mode - name: USB2ULPILPEN + - name: DMA1LPEN + description: DMA1 Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 Clock Enable During CSleep Mode + bit_offset: 1 + bit_size: 1 + - name: ADC12LPEN + description: ADC1/2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: ARTLPEN + description: ART Clock Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: ETH1MACLPEN + description: Ethernet MAC bus interface Clock Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + - name: ETH1TXLPEN + description: Ethernet Transmission Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: ETH1RXLPEN + description: Ethernet Reception Clock Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: USB1OTGLPEN + description: USB1OTG peripheral clock enable during CSleep mode + bit_offset: 25 + bit_size: 1 + - name: USB1OTGHSULPILPEN + description: USB_PHY1 clock enable during CSleep mode + bit_offset: 26 + bit_size: 1 + - name: USB1ULPILPEN + description: USB_PHY1 clock enable during CSleep mode + bit_offset: 26 + bit_size: 1 + - name: USB2OTGLPEN + description: USB2OTG peripheral clock enable during CSleep mode + bit_offset: 27 + bit_size: 1 + - name: USB2OTGHSULPILPEN + description: USB_PHY2 clocks enable during CSleep mode + bit_offset: 28 + bit_size: 1 + - name: USB2ULPILPEN + description: USB_PHY2 clocks enable during CSleep mode + bit_offset: 28 + bit_size: 1 fieldset/AHB1RSTR: description: RCC AHB1 Peripheral Reset Register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA1 block reset - name: DMA1RST - - bit_offset: 1 - bit_size: 1 - description: DMA2 block reset - name: DMA2RST - - bit_offset: 5 - bit_size: 1 - description: ADC1&2 block reset - name: ADC12RST - - bit_offset: 14 - bit_size: 1 - description: ART block reset - name: ARTRST - - bit_offset: 15 - bit_size: 1 - description: ETH1MAC block reset - name: ETH1MACRST - - bit_offset: 25 - bit_size: 1 - description: USB1OTG block reset - name: USB1OTGRST - - bit_offset: 27 - bit_size: 1 - description: USB2OTG block reset - name: USB2OTGRST + - name: DMA1RST + description: DMA1 block reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 block reset + bit_offset: 1 + bit_size: 1 + - name: ADC12RST + description: ADC1&2 block reset + bit_offset: 5 + bit_size: 1 + - name: ARTRST + description: ART block reset + bit_offset: 14 + bit_size: 1 + - name: ETH1MACRST + description: ETH1MAC block reset + bit_offset: 15 + bit_size: 1 + - name: USB1OTGRST + description: USB1OTG block reset + bit_offset: 25 + bit_size: 1 + - name: USB2OTGRST + description: USB2OTG block reset + bit_offset: 27 + bit_size: 1 fieldset/AHB2ENR: description: RCC AHB2 Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: DCMI peripheral clock - name: DCMIEN - - bit_offset: 4 - bit_size: 1 - description: CRYPT peripheral clock enable - name: CRYPTEN - - bit_offset: 5 - bit_size: 1 - description: HASH peripheral clock enable - name: HASHEN - - bit_offset: 6 - bit_size: 1 - description: RNG peripheral clocks enable - name: RNGEN - - bit_offset: 9 - bit_size: 1 - description: SDMMC2 and SDMMC2 delay clock enable - name: SDMMC2EN - - bit_offset: 16 - bit_size: 1 - description: FMAC enable - name: FMACEN - - bit_offset: 17 - bit_size: 1 - description: CORDIC enable - name: CORDICEN - - bit_offset: 29 - bit_size: 1 - description: SRAM1 block enable - name: SRAM1EN - - bit_offset: 30 - bit_size: 1 - description: SRAM2 block enable - name: SRAM2EN - - bit_offset: 31 - bit_size: 1 - description: SRAM3 block enable - name: SRAM3EN + - name: DCMIEN + description: DCMI peripheral clock + bit_offset: 0 + bit_size: 1 + - name: CRYPTEN + description: CRYPT peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: HASHEN + description: HASH peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: RNGEN + description: RNG peripheral clocks enable + bit_offset: 6 + bit_size: 1 + - name: SDMMC2EN + description: SDMMC2 and SDMMC2 delay clock enable + bit_offset: 9 + bit_size: 1 + - name: FMACEN + description: FMAC enable + bit_offset: 16 + bit_size: 1 + - name: CORDICEN + description: CORDIC enable + bit_offset: 17 + bit_size: 1 + - name: SRAM1EN + description: SRAM1 block enable + bit_offset: 29 + bit_size: 1 + - name: SRAM2EN + description: SRAM2 block enable + bit_offset: 30 + bit_size: 1 + - name: SRAM3EN + description: SRAM3 block enable + bit_offset: 31 + bit_size: 1 fieldset/AHB2LPENR: description: RCC AHB2 Sleep Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: DCMI peripheral clock enable during csleep mode - name: DCMILPEN - - bit_offset: 4 - bit_size: 1 - description: CRYPT peripheral clock enable during CSleep mode - name: CRYPTLPEN - - bit_offset: 5 - bit_size: 1 - description: HASH peripheral clock enable during CSleep mode - name: HASHLPEN - - bit_offset: 6 - bit_size: 1 - description: RNG peripheral clock enable during CSleep mode - name: RNGLPEN - - bit_offset: 9 - bit_size: 1 - description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - name: SDMMC2LPEN - - bit_offset: 16 - bit_size: 1 - description: FMAC enable during CSleep Mode - name: FMACLPEN - - bit_offset: 17 - bit_size: 1 - description: CORDIC enable during CSleep Mode - name: CORDICLPEN - - bit_offset: 29 - bit_size: 1 - description: SRAM1 Clock Enable During CSleep Mode - name: SRAM1LPEN - - bit_offset: 30 - bit_size: 1 - description: SRAM2 Clock Enable During CSleep Mode - name: SRAM2LPEN - - bit_offset: 31 - bit_size: 1 - description: SRAM3 Clock Enable During CSleep Mode - name: SRAM3LPEN + - name: DCMILPEN + description: DCMI peripheral clock enable during csleep mode + bit_offset: 0 + bit_size: 1 + - name: CRYPTLPEN + description: CRYPT peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: HASHLPEN + description: HASH peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: RNGLPEN + description: RNG peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: SDMMC2LPEN + description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: FMACLPEN + description: FMAC enable during CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: CORDICLPEN + description: CORDIC enable during CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: SRAM1LPEN + description: SRAM1 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 + - name: SRAM2LPEN + description: SRAM2 Clock Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + - name: SRAM3LPEN + description: SRAM3 Clock Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 fieldset/AHB2RSTR: description: RCC AHB2 Peripheral Reset Register fields: - - bit_offset: 0 - bit_size: 1 - description: DCMI block reset - name: DCMIRST - - bit_offset: 4 - bit_size: 1 - description: Cryptography block reset - name: CRYPTRST - - bit_offset: 5 - bit_size: 1 - description: Hash block reset - name: HASHRST - - bit_offset: 6 - bit_size: 1 - description: Random Number Generator block reset - name: RNGRST - - bit_offset: 9 - bit_size: 1 - description: SDMMC2 and SDMMC2 Delay block reset - name: SDMMC2RST - - bit_offset: 16 - bit_size: 1 - description: FMAC reset - name: FMACRST - - bit_offset: 17 - bit_size: 1 - description: CORDIC reset - name: CORDICRST + - name: DCMIRST + description: DCMI block reset + bit_offset: 0 + bit_size: 1 + - name: CRYPTRST + description: Cryptography block reset + bit_offset: 4 + bit_size: 1 + - name: HASHRST + description: Hash block reset + bit_offset: 5 + bit_size: 1 + - name: RNGRST + description: Random Number Generator block reset + bit_offset: 6 + bit_size: 1 + - name: SDMMC2RST + description: SDMMC2 and SDMMC2 Delay block reset + bit_offset: 9 + bit_size: 1 + - name: FMACRST + description: FMAC reset + bit_offset: 16 + bit_size: 1 + - name: CORDICRST + description: CORDIC reset + bit_offset: 17 + bit_size: 1 fieldset/AHB3ENR: description: RCC AHB3 Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: MDMA Peripheral Clock Enable - name: MDMAEN - - bit_offset: 4 - bit_size: 1 - description: DMA2D Peripheral Clock Enable - name: DMA2DEN - - bit_offset: 5 - bit_size: 1 - description: JPGDEC Peripheral Clock Enable - name: JPGDECEN - - bit_offset: 12 - bit_size: 1 - description: FMC Peripheral Clocks Enable - name: FMCEN - - bit_offset: 14 - bit_size: 1 - description: QUADSPI and QUADSPI Delay Clock Enable - name: QSPIEN - - bit_offset: 16 - bit_size: 1 - description: SDMMC1 and SDMMC1 Delay Clock Enable - name: SDMMC1EN - - bit_offset: 19 - bit_size: 1 - description: OCTOSPI2 and OCTOSPI2 delay block enable - name: OCTOSPI2EN - - bit_offset: 21 - bit_size: 1 - description: OCTOSPI IO manager enable - name: IOMNGREN - - bit_offset: 22 - bit_size: 1 - description: OTFDEC1 enable - name: OTFD1EN - - bit_offset: 23 - bit_size: 1 - description: OTFDEC2 enable - name: OTFD2EN - - bit_offset: 28 - bit_size: 1 - description: D1 DTCM1 block enable - name: DTCM1EN - - bit_offset: 29 - bit_size: 1 - description: D1 DTCM2 block enable - name: DTCM2EN - - bit_offset: 30 - bit_size: 1 - description: D1 ITCM block enable - name: ITCM1EN - - bit_offset: 31 - bit_size: 1 - description: AXISRAM block enable - name: AXISRAMEN + - name: MDMAEN + description: MDMA Peripheral Clock Enable + bit_offset: 0 + bit_size: 1 + - name: DMA2DEN + description: DMA2D Peripheral Clock Enable + bit_offset: 4 + bit_size: 1 + - name: JPGDECEN + description: JPGDEC Peripheral Clock Enable + bit_offset: 5 + bit_size: 1 + - name: FMCEN + description: FMC Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: QSPIEN + description: QUADSPI and QUADSPI Delay Clock Enable + bit_offset: 14 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 and SDMMC1 Delay Clock Enable + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI2EN + description: OCTOSPI2 and OCTOSPI2 delay block enable + bit_offset: 19 + bit_size: 1 + - name: IOMNGREN + description: OCTOSPI IO manager enable + bit_offset: 21 + bit_size: 1 + - name: OTFD1EN + description: OTFDEC1 enable + bit_offset: 22 + bit_size: 1 + - name: OTFD2EN + description: OTFDEC2 enable + bit_offset: 23 + bit_size: 1 + - name: DTCM1EN + description: D1 DTCM1 block enable + bit_offset: 28 + bit_size: 1 + - name: DTCM2EN + description: D1 DTCM2 block enable + bit_offset: 29 + bit_size: 1 + - name: ITCM1EN + description: D1 ITCM block enable + bit_offset: 30 + bit_size: 1 + - name: AXISRAMEN + description: AXISRAM block enable + bit_offset: 31 + bit_size: 1 fieldset/AHB3LPENR: description: RCC AHB3 Sleep Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: MDMA Clock Enable During CSleep Mode - name: MDMALPEN - - bit_offset: 4 - bit_size: 1 - description: DMA2D Clock Enable During CSleep Mode - name: DMA2DLPEN - - bit_offset: 5 - bit_size: 1 - description: JPGDEC Clock Enable During CSleep Mode - name: JPGDECLPEN - - bit_offset: 8 - bit_size: 1 - description: FLITF Clock Enable During CSleep Mode - name: FLASHLPEN - - bit_offset: 8 - bit_size: 1 - description: FLITF Clock Enable During CSleep Mode - name: FLITFLPEN - - bit_offset: 12 - bit_size: 1 - description: FMC Peripheral Clocks Enable During CSleep Mode - name: FMCLPEN - - bit_offset: 14 - bit_size: 1 - description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode - name: QSPILPEN - - bit_offset: 16 - bit_size: 1 - description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - name: SDMMC1LPEN - - bit_offset: 19 - bit_size: 1 - description: OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode - name: OCTOSPI2LPEN - - bit_offset: 21 - bit_size: 1 - description: OCTOSPI IO manager enable during CSleep Mode - name: IOMNGRLPEN - - bit_offset: 22 - bit_size: 1 - description: OTFDEC1 enable during CSleep Mode - name: OTFD1LPEN - - bit_offset: 23 - bit_size: 1 - description: OTFDEC2 enable during CSleep Mode - name: OTFD2LPEN - - bit_offset: 28 - bit_size: 1 - description: D1DTCM1 Block Clock Enable During CSleep mode - name: D1DTCM1LPEN - - bit_offset: 29 - bit_size: 1 - description: D1 DTCM2 Block Clock Enable During CSleep mode - name: DTCM2LPEN - - bit_offset: 30 - bit_size: 1 - description: D1ITCM Block Clock Enable During CSleep mode - name: ITCMLPEN - - bit_offset: 31 - bit_size: 1 - description: AXISRAM Block Clock Enable During CSleep mode - name: AXISRAMLPEN + - name: MDMALPEN + description: MDMA Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + - name: DMA2DLPEN + description: DMA2D Clock Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: JPGDECLPEN + description: JPGDEC Clock Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: FLASHLPEN + description: FLITF Clock Enable During CSleep Mode + bit_offset: 8 + bit_size: 1 + - name: FLITFLPEN + description: FLITF Clock Enable During CSleep Mode + bit_offset: 8 + bit_size: 1 + - name: FMCLPEN + description: FMC Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: QSPILPEN + description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: SDMMC1LPEN + description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI2LPEN + description: OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode + bit_offset: 19 + bit_size: 1 + - name: IOMNGRLPEN + description: OCTOSPI IO manager enable during CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: OTFD1LPEN + description: OTFDEC1 enable during CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: OTFD2LPEN + description: OTFDEC2 enable during CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: D1DTCM1LPEN + description: D1DTCM1 Block Clock Enable During CSleep mode + bit_offset: 28 + bit_size: 1 + - name: DTCM2LPEN + description: D1 DTCM2 Block Clock Enable During CSleep mode + bit_offset: 29 + bit_size: 1 + - name: ITCMLPEN + description: D1ITCM Block Clock Enable During CSleep mode + bit_offset: 30 + bit_size: 1 + - name: AXISRAMLPEN + description: AXISRAM Block Clock Enable During CSleep mode + bit_offset: 31 + bit_size: 1 fieldset/AHB3RSTR: description: RCC AHB3 Reset Register fields: - - bit_offset: 0 - bit_size: 1 - description: MDMA block reset - name: MDMARST - - bit_offset: 4 - bit_size: 1 - description: DMA2D block reset - name: DMA2DRST - - bit_offset: 5 - bit_size: 1 - description: JPGDEC block reset - name: JPGDECRST - - bit_offset: 12 - bit_size: 1 - description: FMC block reset - name: FMCRST - - bit_offset: 14 - bit_size: 1 - description: QUADSPI and QUADSPI delay block reset - name: QSPIRST - - bit_offset: 16 - bit_size: 1 - description: SDMMC1 and SDMMC1 delay block reset - name: SDMMC1RST - - bit_offset: 19 - bit_size: 1 - description: OCTOSPI2 and OCTOSPI2 delay block reset - name: OCTOSPI2RST - - bit_offset: 21 - bit_size: 1 - description: OCTOSPI IO manager reset - name: IOMNGRRST - - bit_offset: 22 - bit_size: 1 - description: OTFDEC1 reset - name: OTFD1RST - - bit_offset: 23 - bit_size: 1 - description: OTFDEC2 reset - name: OTFD2RST - - bit_offset: 31 - bit_size: 1 - description: CPU reset - name: CPURST + - name: MDMARST + description: MDMA block reset + bit_offset: 0 + bit_size: 1 + - name: DMA2DRST + description: DMA2D block reset + bit_offset: 4 + bit_size: 1 + - name: JPGDECRST + description: JPGDEC block reset + bit_offset: 5 + bit_size: 1 + - name: FMCRST + description: FMC block reset + bit_offset: 12 + bit_size: 1 + - name: QSPIRST + description: QUADSPI and QUADSPI delay block reset + bit_offset: 14 + bit_size: 1 + - name: SDMMC1RST + description: SDMMC1 and SDMMC1 delay block reset + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI2RST + description: OCTOSPI2 and OCTOSPI2 delay block reset + bit_offset: 19 + bit_size: 1 + - name: IOMNGRRST + description: OCTOSPI IO manager reset + bit_offset: 21 + bit_size: 1 + - name: OTFD1RST + description: OTFDEC1 reset + bit_offset: 22 + bit_size: 1 + - name: OTFD2RST + description: OTFDEC2 reset + bit_offset: 23 + bit_size: 1 + - name: CPURST + description: CPU reset + bit_offset: 31 + bit_size: 1 fieldset/AHB4ENR: description: RCC AHB4 Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOAEN - - bit_offset: 1 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOBEN - - bit_offset: 2 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOCEN - - bit_offset: 3 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIODEN - - bit_offset: 4 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOEEN - - bit_offset: 5 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOFEN - - bit_offset: 6 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOGEN - - bit_offset: 7 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOHEN - - bit_offset: 8 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOIEN - - bit_offset: 9 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOJEN - - bit_offset: 10 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOKEN - - bit_offset: 19 - bit_size: 1 - description: CRC peripheral clock enable - name: CRCEN - - bit_offset: 21 - bit_size: 1 - description: BDMA and DMAMUX2 Clock Enable - name: BDMAEN - - bit_offset: 24 - bit_size: 1 - description: ADC3 Peripheral Clocks Enable - name: ADC3EN - - bit_offset: 25 - bit_size: 1 - description: HSEM peripheral clock enable - name: HSEMEN - - bit_offset: 28 - bit_size: 1 - description: Backup RAM Clock Enable - name: BKPRAMEN + - name: GPIOAEN + description: 0GPIO peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: 0GPIO peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: 0GPIO peripheral clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: 0GPIO peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: 0GPIO peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: 0GPIO peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: 0GPIO peripheral clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: 0GPIO peripheral clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: 0GPIO peripheral clock enable + bit_offset: 8 + bit_size: 1 + - name: GPIOJEN + description: 0GPIO peripheral clock enable + bit_offset: 9 + bit_size: 1 + - name: GPIOKEN + description: 0GPIO peripheral clock enable + bit_offset: 10 + bit_size: 1 + - name: CRCEN + description: CRC peripheral clock enable + bit_offset: 19 + bit_size: 1 + - name: BDMAEN + description: BDMA and DMAMUX2 Clock Enable + bit_offset: 21 + bit_size: 1 + - name: ADC3EN + description: ADC3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + - name: HSEMEN + description: HSEM peripheral clock enable + bit_offset: 25 + bit_size: 1 + - name: BKPRAMEN + description: Backup RAM Clock Enable + bit_offset: 28 + bit_size: 1 fieldset/AHB4LPENR: description: RCC AHB4 Sleep Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOALPEN - - bit_offset: 1 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOBLPEN - - bit_offset: 2 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOCLPEN - - bit_offset: 3 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIODLPEN - - bit_offset: 4 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOELPEN - - bit_offset: 5 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOFLPEN - - bit_offset: 6 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOGLPEN - - bit_offset: 7 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOHLPEN - - bit_offset: 8 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOILPEN - - bit_offset: 9 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOJLPEN - - bit_offset: 10 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOKLPEN - - bit_offset: 19 - bit_size: 1 - description: CRC peripheral clock enable during CSleep mode - name: CRCLPEN - - bit_offset: 21 - bit_size: 1 - description: BDMA Clock Enable During CSleep Mode - name: BDMALPEN - - bit_offset: 24 - bit_size: 1 - description: ADC3 Peripheral Clocks Enable During CSleep Mode - name: ADC3LPEN - - bit_offset: 28 - bit_size: 1 - description: Backup RAM Clock Enable During CSleep Mode - name: BKPRAMLPEN - - bit_offset: 29 - bit_size: 1 - description: SRAM4 Clock Enable During CSleep Mode - name: SRAM4LPEN + - name: GPIOALPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: GPIOFLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: GPIOHLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + - name: GPIOILPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + - name: GPIOJLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 9 + bit_size: 1 + - name: GPIOKLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 10 + bit_size: 1 + - name: CRCLPEN + description: CRC peripheral clock enable during CSleep mode + bit_offset: 19 + bit_size: 1 + - name: BDMALPEN + description: BDMA Clock Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: ADC3LPEN + description: ADC3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: BKPRAMLPEN + description: Backup RAM Clock Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + - name: SRAM4LPEN + description: SRAM4 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 fieldset/AHB4RSTR: description: RCC AHB4 Peripheral Reset Register fields: - - bit_offset: 0 - bit_size: 1 - description: GPIO block reset - name: GPIOARST - - bit_offset: 1 - bit_size: 1 - description: GPIO block reset - name: GPIOBRST - - bit_offset: 2 - bit_size: 1 - description: GPIO block reset - name: GPIOCRST - - bit_offset: 3 - bit_size: 1 - description: GPIO block reset - name: GPIODRST - - bit_offset: 4 - bit_size: 1 - description: GPIO block reset - name: GPIOERST - - bit_offset: 5 - bit_size: 1 - description: GPIO block reset - name: GPIOFRST - - bit_offset: 6 - bit_size: 1 - description: GPIO block reset - name: GPIOGRST - - bit_offset: 7 - bit_size: 1 - description: GPIO block reset - name: GPIOHRST - - bit_offset: 8 - bit_size: 1 - description: GPIO block reset - name: GPIOIRST - - bit_offset: 9 - bit_size: 1 - description: GPIO block reset - name: GPIOJRST - - bit_offset: 10 - bit_size: 1 - description: GPIO block reset - name: GPIOKRST - - bit_offset: 19 - bit_size: 1 - description: CRC block reset - name: CRCRST - - bit_offset: 21 - bit_size: 1 - description: BDMA block reset - name: BDMARST - - bit_offset: 24 - bit_size: 1 - description: ADC3 block reset - name: ADC3RST - - bit_offset: 25 - bit_size: 1 - description: HSEM block reset - name: HSEMRST + - name: GPIOARST + description: GPIO block reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: GPIO block reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: GPIO block reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: GPIO block reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: GPIO block reset + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: GPIO block reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: GPIO block reset + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: GPIO block reset + bit_offset: 7 + bit_size: 1 + - name: GPIOIRST + description: GPIO block reset + bit_offset: 8 + bit_size: 1 + - name: GPIOJRST + description: GPIO block reset + bit_offset: 9 + bit_size: 1 + - name: GPIOKRST + description: GPIO block reset + bit_offset: 10 + bit_size: 1 + - name: CRCRST + description: CRC block reset + bit_offset: 19 + bit_size: 1 + - name: BDMARST + description: BDMA block reset + bit_offset: 21 + bit_size: 1 + - name: ADC3RST + description: ADC3 block reset + bit_offset: 24 + bit_size: 1 + - name: HSEMRST + description: HSEM block reset + bit_offset: 25 + bit_size: 1 fieldset/APB1HENR: description: RCC APB1 Clock Register fields: - - bit_offset: 1 - bit_size: 1 - description: Clock Recovery System peripheral clock enable - name: CRSEN - - bit_offset: 2 - bit_size: 1 - description: SWPMI Peripheral Clocks Enable - name: SWPEN - - bit_offset: 4 - bit_size: 1 - description: OPAMP peripheral clock enable - name: OPAMPEN - - bit_offset: 5 - bit_size: 1 - description: MDIOS peripheral clock enable - name: MDIOSEN - - bit_offset: 8 - bit_size: 1 - description: FDCAN Peripheral Clocks Enable - name: FDCANEN - - bit_offset: 24 - bit_size: 1 - description: TIM23 block enable - name: TIM23EN - - bit_offset: 25 - bit_size: 1 - description: TIM24 block enable - name: TIM24EN + - name: CRSEN + description: Clock Recovery System peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: SWPEN + description: SWPMI Peripheral Clocks Enable + bit_offset: 2 + bit_size: 1 + - name: OPAMPEN + description: OPAMP peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: MDIOSEN + description: MDIOS peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: FDCANEN + description: FDCAN Peripheral Clocks Enable + bit_offset: 8 + bit_size: 1 + - name: TIM23EN + description: TIM23 block enable + bit_offset: 24 + bit_size: 1 + - name: TIM24EN + description: TIM24 block enable + bit_offset: 25 + bit_size: 1 fieldset/APB1HLPENR: description: RCC APB1 High Sleep Clock Register fields: - - bit_offset: 1 - bit_size: 1 - description: Clock Recovery System peripheral clock enable during CSleep mode - name: CRSLPEN - - bit_offset: 2 - bit_size: 1 - description: SWPMI Peripheral Clocks Enable During CSleep Mode - name: SWPLPEN - - bit_offset: 4 - bit_size: 1 - description: OPAMP peripheral clock enable during CSleep mode - name: OPAMPLPEN - - bit_offset: 5 - bit_size: 1 - description: MDIOS peripheral clock enable during CSleep mode - name: MDIOSLPEN - - bit_offset: 8 - bit_size: 1 - description: FDCAN Peripheral Clocks Enable During CSleep Mode - name: FDCANLPEN - - bit_offset: 24 - bit_size: 1 - description: TIM23 block enable during CSleep Mode - name: TIM23LPEN - - bit_offset: 25 - bit_size: 1 - description: TIM24 block enable during CSleep Mode - name: TIM24LPEN + - name: CRSLPEN + description: Clock Recovery System peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: SWPLPEN + description: SWPMI Peripheral Clocks Enable During CSleep Mode + bit_offset: 2 + bit_size: 1 + - name: OPAMPLPEN + description: OPAMP peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: MDIOSLPEN + description: MDIOS peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: FDCANLPEN + description: FDCAN Peripheral Clocks Enable During CSleep Mode + bit_offset: 8 + bit_size: 1 + - name: TIM23LPEN + description: TIM23 block enable during CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: TIM24LPEN + description: TIM24 block enable during CSleep Mode + bit_offset: 25 + bit_size: 1 fieldset/APB1HRSTR: description: RCC APB1 Peripheral Reset Register fields: - - bit_offset: 1 - bit_size: 1 - description: Clock Recovery System reset - name: CRSRST - - bit_offset: 2 - bit_size: 1 - description: SWPMI block reset - name: SWPRST - - bit_offset: 4 - bit_size: 1 - description: OPAMP block reset - name: OPAMPRST - - bit_offset: 5 - bit_size: 1 - description: MDIOS block reset - name: MDIOSRST - - bit_offset: 8 - bit_size: 1 - description: FDCAN block reset - name: FDCANRST - - bit_offset: 24 - bit_size: 1 - description: TIM23 block reset - name: TIM23RST - - bit_offset: 25 - bit_size: 1 - description: TIM24 block reset - name: TIM24RST + - name: CRSRST + description: Clock Recovery System reset + bit_offset: 1 + bit_size: 1 + - name: SWPRST + description: SWPMI block reset + bit_offset: 2 + bit_size: 1 + - name: OPAMPRST + description: OPAMP block reset + bit_offset: 4 + bit_size: 1 + - name: MDIOSRST + description: MDIOS block reset + bit_offset: 5 + bit_size: 1 + - name: FDCANRST + description: FDCAN block reset + bit_offset: 8 + bit_size: 1 + - name: TIM23RST + description: TIM23 block reset + bit_offset: 24 + bit_size: 1 + - name: TIM24RST + description: TIM24 block reset + bit_offset: 25 + bit_size: 1 fieldset/APB1LENR: description: RCC APB1 Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM2EN - - bit_offset: 1 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM3EN - - bit_offset: 2 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM4EN - - bit_offset: 3 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM5EN - - bit_offset: 4 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM6EN - - bit_offset: 5 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM7EN - - bit_offset: 6 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM12EN - - bit_offset: 7 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM13EN - - bit_offset: 8 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM14EN - - bit_offset: 9 - bit_size: 1 - description: LPTIM1 Peripheral Clocks Enable - name: LPTIM1EN - - bit_offset: 11 - bit_size: 1 - description: WWDG2 peripheral clock enable - name: WWDG2EN - - bit_offset: 14 - bit_size: 1 - description: SPI2 Peripheral Clocks Enable - name: SPI2EN - - bit_offset: 15 - bit_size: 1 - description: SPI3 Peripheral Clocks Enable - name: SPI3EN - - bit_offset: 16 - bit_size: 1 - description: SPDIFRX Peripheral Clocks Enable - name: SPDIFRXEN - - bit_offset: 17 - bit_size: 1 - description: USART2 Peripheral Clocks Enable - name: USART2EN - - bit_offset: 18 - bit_size: 1 - description: USART3 Peripheral Clocks Enable - name: USART3EN - - bit_offset: 19 - bit_size: 1 - description: UART4 Peripheral Clocks Enable - name: UART4EN - - bit_offset: 20 - bit_size: 1 - description: UART5 Peripheral Clocks Enable - name: UART5EN - - bit_offset: 21 - bit_size: 1 - description: I2C1 Peripheral Clocks Enable - name: I2C1EN - - bit_offset: 22 - bit_size: 1 - description: I2C2 Peripheral Clocks Enable - name: I2C2EN - - bit_offset: 23 - bit_size: 1 - description: I2C3 Peripheral Clocks Enable - name: I2C3EN - - bit_offset: 25 - bit_size: 1 - description: "I2C5 Peripheral Clocks\r Enable" - name: I2C5EN - - bit_offset: 27 - bit_size: 1 - description: HDMI-CEC peripheral clock enable - name: CECEN - - bit_offset: 29 - bit_size: 1 - description: DAC1&2 peripheral clock enable - name: DAC12EN - - bit_offset: 30 - bit_size: 1 - description: UART7 Peripheral Clocks Enable - name: UART7EN - - bit_offset: 31 - bit_size: 1 - description: UART8 Peripheral Clocks Enable - name: UART8EN + - name: TIM2EN + description: TIM peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM peripheral clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: TIM peripheral clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: TIM peripheral clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: TIM peripheral clock enable + bit_offset: 8 + bit_size: 1 + - name: LPTIM1EN + description: LPTIM1 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + - name: WWDG2EN + description: WWDG2 peripheral clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 Peripheral Clocks Enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 Peripheral Clocks Enable + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXEN + description: SPDIFRX Peripheral Clocks Enable + bit_offset: 16 + bit_size: 1 + - name: USART2EN + description: USART2 Peripheral Clocks Enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 Peripheral Clocks Enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 Peripheral Clocks Enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + - name: I2C5EN + description: "I2C5 Peripheral Clocks\r Enable" + bit_offset: 25 + bit_size: 1 + - name: CECEN + description: HDMI-CEC peripheral clock enable + bit_offset: 27 + bit_size: 1 + - name: DAC12EN + description: DAC1&2 peripheral clock enable + bit_offset: 29 + bit_size: 1 + - name: UART7EN + description: UART7 Peripheral Clocks Enable + bit_offset: 30 + bit_size: 1 + - name: UART8EN + description: UART8 Peripheral Clocks Enable + bit_offset: 31 + bit_size: 1 fieldset/APB1LLPENR: description: RCC APB1 Low Sleep Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 peripheral clock enable during CSleep mode - name: TIM2LPEN - - bit_offset: 1 - bit_size: 1 - description: TIM3 peripheral clock enable during CSleep mode - name: TIM3LPEN - - bit_offset: 2 - bit_size: 1 - description: TIM4 peripheral clock enable during CSleep mode - name: TIM4LPEN - - bit_offset: 3 - bit_size: 1 - description: TIM5 peripheral clock enable during CSleep mode - name: TIM5LPEN - - bit_offset: 4 - bit_size: 1 - description: TIM6 peripheral clock enable during CSleep mode - name: TIM6LPEN - - bit_offset: 5 - bit_size: 1 - description: TIM7 peripheral clock enable during CSleep mode - name: TIM7LPEN - - bit_offset: 6 - bit_size: 1 - description: TIM12 peripheral clock enable during CSleep mode - name: TIM12LPEN - - bit_offset: 7 - bit_size: 1 - description: TIM13 peripheral clock enable during CSleep mode - name: TIM13LPEN - - bit_offset: 8 - bit_size: 1 - description: TIM14 peripheral clock enable during CSleep mode - name: TIM14LPEN - - bit_offset: 9 - bit_size: 1 - description: LPTIM1 Peripheral Clocks Enable During CSleep Mode - name: LPTIM1LPEN - - bit_offset: 11 - bit_size: 1 - description: WWDG2 peripheral Clocks Enable During CSleep Mode - name: WWDG2LPEN - - bit_offset: 14 - bit_size: 1 - description: SPI2 Peripheral Clocks Enable During CSleep Mode - name: SPI2LPEN - - bit_offset: 15 - bit_size: 1 - description: SPI3 Peripheral Clocks Enable During CSleep Mode - name: SPI3LPEN - - bit_offset: 16 - bit_size: 1 - description: SPDIFRX Peripheral Clocks Enable During CSleep Mode - name: SPDIFRXLPEN - - bit_offset: 17 - bit_size: 1 - description: USART2 Peripheral Clocks Enable During CSleep Mode - name: USART2LPEN - - bit_offset: 18 - bit_size: 1 - description: USART3 Peripheral Clocks Enable During CSleep Mode - name: USART3LPEN - - bit_offset: 19 - bit_size: 1 - description: UART4 Peripheral Clocks Enable During CSleep Mode - name: UART4LPEN - - bit_offset: 20 - bit_size: 1 - description: UART5 Peripheral Clocks Enable During CSleep Mode - name: UART5LPEN - - bit_offset: 21 - bit_size: 1 - description: I2C1 Peripheral Clocks Enable During CSleep Mode - name: I2C1LPEN - - bit_offset: 22 - bit_size: 1 - description: I2C2 Peripheral Clocks Enable During CSleep Mode - name: I2C2LPEN - - bit_offset: 23 - bit_size: 1 - description: I2C3 Peripheral Clocks Enable During CSleep Mode - name: I2C3LPEN - - bit_offset: 25 - bit_size: 1 - description: I2C5 block enable during CSleep Mode - name: I2C5LPEN - - bit_offset: 27 - bit_size: 1 - description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode - name: CECLPEN - - bit_offset: 29 - bit_size: 1 - description: DAC1/2 peripheral clock enable during CSleep mode - name: DAC12LPEN - - bit_offset: 30 - bit_size: 1 - description: UART7 Peripheral Clocks Enable During CSleep Mode - name: UART7LPEN - - bit_offset: 31 - bit_size: 1 - description: UART8 Peripheral Clocks Enable During CSleep Mode - name: UART8LPEN + - name: TIM2LPEN + description: TIM2 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: TIM3 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: TIM4 peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: TIM5 peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: TIM6 peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: TIM7 peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: TIM12LPEN + description: TIM12 peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: TIM13LPEN + description: TIM13 peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + - name: TIM14LPEN + description: TIM14 peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + - name: LPTIM1LPEN + description: LPTIM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: WWDG2LPEN + description: WWDG2 peripheral Clocks Enable During CSleep Mode + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: SPI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXLPEN + description: SPDIFRX Peripheral Clocks Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: USART2LPEN + description: USART2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: USART3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: UART4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: UART5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + - name: I2C1LPEN + description: I2C1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: I2C3LPEN + description: I2C3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: I2C5LPEN + description: I2C5 block enable during CSleep Mode + bit_offset: 25 + bit_size: 1 + - name: CECLPEN + description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode + bit_offset: 27 + bit_size: 1 + - name: DAC12LPEN + description: DAC1/2 peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 + - name: UART7LPEN + description: UART7 Peripheral Clocks Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + - name: UART8LPEN + description: UART8 Peripheral Clocks Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 fieldset/APB1LRSTR: description: RCC APB1 Peripheral Reset Register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM block reset - name: TIM2RST - - bit_offset: 1 - bit_size: 1 - description: TIM block reset - name: TIM3RST - - bit_offset: 2 - bit_size: 1 - description: TIM block reset - name: TIM4RST - - bit_offset: 3 - bit_size: 1 - description: TIM block reset - name: TIM5RST - - bit_offset: 4 - bit_size: 1 - description: TIM block reset - name: TIM6RST - - bit_offset: 5 - bit_size: 1 - description: TIM block reset - name: TIM7RST - - bit_offset: 6 - bit_size: 1 - description: TIM block reset - name: TIM12RST - - bit_offset: 7 - bit_size: 1 - description: TIM block reset - name: TIM13RST - - bit_offset: 8 - bit_size: 1 - description: TIM block reset - name: TIM14RST - - bit_offset: 9 - bit_size: 1 - description: TIM block reset - name: LPTIM1RST - - bit_offset: 14 - bit_size: 1 - description: SPI2 block reset - name: SPI2RST - - bit_offset: 15 - bit_size: 1 - description: SPI3 block reset - name: SPI3RST - - bit_offset: 16 - bit_size: 1 - description: SPDIFRX block reset - name: SPDIFRXRST - - bit_offset: 17 - bit_size: 1 - description: USART2 block reset - name: USART2RST - - bit_offset: 18 - bit_size: 1 - description: USART3 block reset - name: USART3RST - - bit_offset: 19 - bit_size: 1 - description: UART4 block reset - name: UART4RST - - bit_offset: 20 - bit_size: 1 - description: UART5 block reset - name: UART5RST - - bit_offset: 21 - bit_size: 1 - description: I2C1 block reset - name: I2C1RST - - bit_offset: 22 - bit_size: 1 - description: I2C2 block reset - name: I2C2RST - - bit_offset: 23 - bit_size: 1 - description: I2C3 block reset - name: I2C3RST - - bit_offset: 25 - bit_size: 1 - description: I2C5 block reset - name: I2C5RST - - bit_offset: 27 - bit_size: 1 - description: HDMI-CEC block reset - name: CECRST - - bit_offset: 29 - bit_size: 1 - description: DAC1 and 2 Blocks Reset - name: DAC12RST - - bit_offset: 30 - bit_size: 1 - description: UART7 block reset - name: UART7RST - - bit_offset: 31 - bit_size: 1 - description: UART8 block reset - name: UART8RST + - name: TIM2RST + description: TIM block reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM block reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM block reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM block reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM block reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM block reset + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: TIM block reset + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: TIM block reset + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: TIM block reset + bit_offset: 8 + bit_size: 1 + - name: LPTIM1RST + description: TIM block reset + bit_offset: 9 + bit_size: 1 + - name: SPI2RST + description: SPI2 block reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 block reset + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXRST + description: SPDIFRX block reset + bit_offset: 16 + bit_size: 1 + - name: USART2RST + description: USART2 block reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 block reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART4 block reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART5 block reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 block reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 block reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 block reset + bit_offset: 23 + bit_size: 1 + - name: I2C5RST + description: I2C5 block reset + bit_offset: 25 + bit_size: 1 + - name: CECRST + description: HDMI-CEC block reset + bit_offset: 27 + bit_size: 1 + - name: DAC12RST + description: DAC1 and 2 Blocks Reset + bit_offset: 29 + bit_size: 1 + - name: UART7RST + description: UART7 block reset + bit_offset: 30 + bit_size: 1 + - name: UART8RST + description: UART8 block reset + bit_offset: 31 + bit_size: 1 fieldset/APB2ENR: description: RCC APB2 Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM1 peripheral clock enable - name: TIM1EN - - bit_offset: 1 - bit_size: 1 - description: TIM8 peripheral clock enable - name: TIM8EN - - bit_offset: 4 - bit_size: 1 - description: USART1 Peripheral Clocks Enable - name: USART1EN - - bit_offset: 5 - bit_size: 1 - description: USART6 Peripheral Clocks Enable - name: USART6EN - - bit_offset: 6 - bit_size: 1 - description: "UART9 Peripheral Clocks\r Enable" - name: UART9EN - - bit_offset: 7 - bit_size: 1 - description: "USART10 Peripheral Clocks\r Enable" - name: USART10EN - - bit_offset: 12 - bit_size: 1 - description: SPI1 Peripheral Clocks Enable - name: SPI1EN - - bit_offset: 13 - bit_size: 1 - description: SPI4 Peripheral Clocks Enable - name: SPI4EN - - bit_offset: 16 - bit_size: 1 - description: TIM15 peripheral clock enable - name: TIM15EN - - bit_offset: 17 - bit_size: 1 - description: TIM16 peripheral clock enable - name: TIM16EN - - bit_offset: 18 - bit_size: 1 - description: TIM17 peripheral clock enable - name: TIM17EN - - bit_offset: 20 - bit_size: 1 - description: SPI5 Peripheral Clocks Enable - name: SPI5EN - - bit_offset: 22 - bit_size: 1 - description: SAI1 Peripheral Clocks Enable - name: SAI1EN - - bit_offset: 23 - bit_size: 1 - description: SAI2 Peripheral Clocks Enable - name: SAI2EN - - bit_offset: 24 - bit_size: 1 - description: SAI3 Peripheral Clocks Enable - name: SAI3EN - - bit_offset: 28 - bit_size: 1 - description: DFSDM1 Peripheral Clocks Enable - name: DFSDM1EN - - bit_offset: 29 - bit_size: 1 - description: HRTIM peripheral clock enable - name: HRTIMEN + - name: TIM1EN + description: TIM1 peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM8EN + description: TIM8 peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: USART1EN + description: USART1 Peripheral Clocks Enable + bit_offset: 4 + bit_size: 1 + - name: USART6EN + description: USART6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: UART9EN + description: "UART9 Peripheral Clocks\r Enable" + bit_offset: 6 + bit_size: 1 + - name: USART10EN + description: "USART10 Peripheral Clocks\r Enable" + bit_offset: 7 + bit_size: 1 + - name: SPI1EN + description: SPI1 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: SPI4EN + description: SPI4 Peripheral Clocks Enable + bit_offset: 13 + bit_size: 1 + - name: TIM15EN + description: TIM15 peripheral clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 peripheral clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 peripheral clock enable + bit_offset: 18 + bit_size: 1 + - name: SPI5EN + description: SPI5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + - name: SAI1EN + description: SAI1 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + - name: SAI2EN + description: SAI2 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + - name: SAI3EN + description: SAI3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + - name: DFSDM1EN + description: DFSDM1 Peripheral Clocks Enable + bit_offset: 28 + bit_size: 1 + - name: HRTIMEN + description: HRTIM peripheral clock enable + bit_offset: 29 + bit_size: 1 fieldset/APB2LPENR: description: RCC APB2 Sleep Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM1 peripheral clock enable during CSleep mode - name: TIM1LPEN - - bit_offset: 1 - bit_size: 1 - description: TIM8 peripheral clock enable during CSleep mode - name: TIM8LPEN - - bit_offset: 4 - bit_size: 1 - description: USART1 Peripheral Clocks Enable During CSleep Mode - name: USART1LPEN - - bit_offset: 5 - bit_size: 1 - description: USART6 Peripheral Clocks Enable During CSleep Mode - name: USART6LPEN - - bit_offset: 12 - bit_size: 1 - description: SPI1 Peripheral Clocks Enable During CSleep Mode - name: SPI1LPEN - - bit_offset: 13 - bit_size: 1 - description: SPI4 Peripheral Clocks Enable During CSleep Mode - name: SPI4LPEN - - bit_offset: 16 - bit_size: 1 - description: TIM15 peripheral clock enable during CSleep mode - name: TIM15LPEN - - bit_offset: 17 - bit_size: 1 - description: TIM16 peripheral clock enable during CSleep mode - name: TIM16LPEN - - bit_offset: 18 - bit_size: 1 - description: TIM17 peripheral clock enable during CSleep mode - name: TIM17LPEN - - bit_offset: 20 - bit_size: 1 - description: SPI5 Peripheral Clocks Enable During CSleep Mode - name: SPI5LPEN - - bit_offset: 22 - bit_size: 1 - description: SAI1 Peripheral Clocks Enable During CSleep Mode - name: SAI1LPEN - - bit_offset: 23 - bit_size: 1 - description: SAI2 Peripheral Clocks Enable During CSleep Mode - name: SAI2LPEN - - bit_offset: 24 - bit_size: 1 - description: SAI3 Peripheral Clocks Enable During CSleep Mode - name: SAI3LPEN - - bit_offset: 28 - bit_size: 1 - description: DFSDM1 Peripheral Clocks Enable During CSleep Mode - name: DFSDM1LPEN - - bit_offset: 29 - bit_size: 1 - description: HRTIM peripheral clock enable during CSleep mode - name: HRTIMLPEN + - name: TIM1LPEN + description: TIM1 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM8LPEN + description: TIM8 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: USART1LPEN + description: USART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: USART6LPEN + description: USART6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: SPI1LPEN + description: SPI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: SPI4LPEN + description: SPI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 13 + bit_size: 1 + - name: TIM15LPEN + description: TIM15 peripheral clock enable during CSleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM16LPEN + description: TIM16 peripheral clock enable during CSleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM17LPEN + description: TIM17 peripheral clock enable during CSleep mode + bit_offset: 18 + bit_size: 1 + - name: SPI5LPEN + description: SPI5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + - name: SAI1LPEN + description: SAI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: SAI2LPEN + description: SAI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: SAI3LPEN + description: SAI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: DFSDM1LPEN + description: DFSDM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + - name: HRTIMLPEN + description: HRTIM peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 fieldset/APB2RSTR: description: RCC APB2 Peripheral Reset Register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM1 block reset - name: TIM1RST - - bit_offset: 1 - bit_size: 1 - description: TIM8 block reset - name: TIM8RST - - bit_offset: 4 - bit_size: 1 - description: USART1 block reset - name: USART1RST - - bit_offset: 5 - bit_size: 1 - description: USART6 block reset - name: USART6RST - - bit_offset: 6 - bit_size: 1 - description: UART9 block reset - name: UART9RST - - bit_offset: 7 - bit_size: 1 - description: USART10 block reset - name: USART10RST - - bit_offset: 12 - bit_size: 1 - description: SPI1 block reset - name: SPI1RST - - bit_offset: 13 - bit_size: 1 - description: SPI4 block reset - name: SPI4RST - - bit_offset: 16 - bit_size: 1 - description: TIM15 block reset - name: TIM15RST - - bit_offset: 17 - bit_size: 1 - description: TIM16 block reset - name: TIM16RST - - bit_offset: 18 - bit_size: 1 - description: TIM17 block reset - name: TIM17RST - - bit_offset: 20 - bit_size: 1 - description: SPI5 block reset - name: SPI5RST - - bit_offset: 22 - bit_size: 1 - description: SAI1 block reset - name: SAI1RST - - bit_offset: 23 - bit_size: 1 - description: SAI2 block reset - name: SAI2RST - - bit_offset: 24 - bit_size: 1 - description: SAI3 block reset - name: SAI3RST - - bit_offset: 28 - bit_size: 1 - description: DFSDM1 block reset - name: DFSDM1RST - - bit_offset: 29 - bit_size: 1 - description: HRTIM block reset - name: HRTIMRST + - name: TIM1RST + description: TIM1 block reset + bit_offset: 0 + bit_size: 1 + - name: TIM8RST + description: TIM8 block reset + bit_offset: 1 + bit_size: 1 + - name: USART1RST + description: USART1 block reset + bit_offset: 4 + bit_size: 1 + - name: USART6RST + description: USART6 block reset + bit_offset: 5 + bit_size: 1 + - name: UART9RST + description: UART9 block reset + bit_offset: 6 + bit_size: 1 + - name: USART10RST + description: USART10 block reset + bit_offset: 7 + bit_size: 1 + - name: SPI1RST + description: SPI1 block reset + bit_offset: 12 + bit_size: 1 + - name: SPI4RST + description: SPI4 block reset + bit_offset: 13 + bit_size: 1 + - name: TIM15RST + description: TIM15 block reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 block reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 block reset + bit_offset: 18 + bit_size: 1 + - name: SPI5RST + description: SPI5 block reset + bit_offset: 20 + bit_size: 1 + - name: SAI1RST + description: SAI1 block reset + bit_offset: 22 + bit_size: 1 + - name: SAI2RST + description: SAI2 block reset + bit_offset: 23 + bit_size: 1 + - name: SAI3RST + description: SAI3 block reset + bit_offset: 24 + bit_size: 1 + - name: DFSDM1RST + description: DFSDM1 block reset + bit_offset: 28 + bit_size: 1 + - name: HRTIMRST + description: HRTIM block reset + bit_offset: 29 + bit_size: 1 fieldset/APB3ENR: description: RCC APB3 Clock Register fields: - - bit_offset: 3 - bit_size: 1 - description: LTDC peripheral clock enable - name: LTDCEN - - bit_offset: 4 - bit_size: 1 - description: DSI Peripheral clocks enable - name: DSIEN - - bit_offset: 6 - bit_size: 1 - description: WWDG1 Clock Enable - name: WWDG1EN + - name: LTDCEN + description: LTDC peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: DSIEN + description: DSI Peripheral clocks enable + bit_offset: 4 + bit_size: 1 + - name: WWDG1EN + description: WWDG1 Clock Enable + bit_offset: 6 + bit_size: 1 fieldset/APB3LPENR: description: RCC APB3 Sleep Clock Register fields: - - bit_offset: 3 - bit_size: 1 - description: LTDC peripheral clock enable during CSleep mode - name: LTDCLPEN - - bit_offset: 4 - bit_size: 1 - description: DSI Peripheral Clock Enable During CSleep Mode - name: DSILPEN - - bit_offset: 6 - bit_size: 1 - description: WWDG1 Clock Enable During CSleep Mode - name: WWDG1LPEN + - name: LTDCLPEN + description: LTDC peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: DSILPEN + description: DSI Peripheral Clock Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: WWDG1LPEN + description: WWDG1 Clock Enable During CSleep Mode + bit_offset: 6 + bit_size: 1 fieldset/APB3RSTR: description: RCC APB3 Peripheral Reset Register fields: - - bit_offset: 3 - bit_size: 1 - description: LTDC block reset - name: LTDCRST - - bit_offset: 4 - bit_size: 1 - description: DSI block reset - name: DSIRST + - name: LTDCRST + description: LTDC block reset + bit_offset: 3 + bit_size: 1 + - name: DSIRST + description: DSI block reset + bit_offset: 4 + bit_size: 1 fieldset/APB4ENR: description: RCC APB4 Clock Register fields: - - bit_offset: 1 - bit_size: 1 - description: SYSCFG peripheral clock enable - name: SYSCFGEN - - bit_offset: 3 - bit_size: 1 - description: LPUART1 Peripheral Clocks Enable - name: LPUART1EN - - bit_offset: 5 - bit_size: 1 - description: SPI6 Peripheral Clocks Enable - name: SPI6EN - - bit_offset: 7 - bit_size: 1 - description: I2C4 Peripheral Clocks Enable - name: I2C4EN - - bit_offset: 9 - bit_size: 1 - description: LPTIM2 Peripheral Clocks Enable - name: LPTIM2EN - - bit_offset: 10 - bit_size: 1 - description: LPTIM3 Peripheral Clocks Enable - name: LPTIM3EN - - bit_offset: 11 - bit_size: 1 - description: LPTIM4 Peripheral Clocks Enable - name: LPTIM4EN - - bit_offset: 12 - bit_size: 1 - description: LPTIM5 Peripheral Clocks Enable - name: LPTIM5EN - - bit_offset: 14 - bit_size: 1 - description: COMP1/2 peripheral clock enable - name: COMP12EN - - bit_offset: 15 - bit_size: 1 - description: VREF peripheral clock enable - name: VREFEN - - bit_offset: 16 - bit_size: 1 - description: RTC APB Clock Enable - name: RTCAPBEN - - bit_offset: 21 - bit_size: 1 - description: SAI4 Peripheral Clocks Enable - name: SAI4EN - - bit_offset: 26 - bit_size: 1 - description: Digital temperature sensor block enable - name: DTSEN + - name: SYSCFGEN + description: SYSCFG peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: LPUART1EN + description: LPUART1 Peripheral Clocks Enable + bit_offset: 3 + bit_size: 1 + - name: SPI6EN + description: SPI6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: I2C4EN + description: I2C4 Peripheral Clocks Enable + bit_offset: 7 + bit_size: 1 + - name: LPTIM2EN + description: LPTIM2 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + - name: LPTIM3EN + description: LPTIM3 Peripheral Clocks Enable + bit_offset: 10 + bit_size: 1 + - name: LPTIM4EN + description: LPTIM4 Peripheral Clocks Enable + bit_offset: 11 + bit_size: 1 + - name: LPTIM5EN + description: LPTIM5 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: COMP12EN + description: COMP1/2 peripheral clock enable + bit_offset: 14 + bit_size: 1 + - name: VREFEN + description: VREF peripheral clock enable + bit_offset: 15 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB Clock Enable + bit_offset: 16 + bit_size: 1 + - name: SAI4EN + description: SAI4 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 + - name: DTSEN + description: Digital temperature sensor block enable + bit_offset: 26 + bit_size: 1 fieldset/APB4LPENR: description: RCC APB4 Sleep Clock Register fields: - - bit_offset: 1 - bit_size: 1 - description: SYSCFG peripheral clock enable during CSleep mode - name: SYSCFGLPEN - - bit_offset: 3 - bit_size: 1 - description: LPUART1 Peripheral Clocks Enable During CSleep Mode - name: LPUART1LPEN - - bit_offset: 5 - bit_size: 1 - description: SPI6 Peripheral Clocks Enable During CSleep Mode - name: SPI6LPEN - - bit_offset: 7 - bit_size: 1 - description: I2C4 Peripheral Clocks Enable During CSleep Mode - name: I2C4LPEN - - bit_offset: 9 - bit_size: 1 - description: LPTIM2 Peripheral Clocks Enable During CSleep Mode - name: LPTIM2LPEN - - bit_offset: 10 - bit_size: 1 - description: LPTIM3 Peripheral Clocks Enable During CSleep Mode - name: LPTIM3LPEN - - bit_offset: 11 - bit_size: 1 - description: LPTIM4 Peripheral Clocks Enable During CSleep Mode - name: LPTIM4LPEN - - bit_offset: 12 - bit_size: 1 - description: LPTIM5 Peripheral Clocks Enable During CSleep Mode - name: LPTIM5LPEN - - bit_offset: 14 - bit_size: 1 - description: COMP1/2 peripheral clock enable during CSleep mode - name: COMP12LPEN - - bit_offset: 15 - bit_size: 1 - description: VREF peripheral clock enable during CSleep mode - name: VREFLPEN - - bit_offset: 16 - bit_size: 1 - description: RTC APB Clock Enable During CSleep Mode - name: RTCAPBLPEN - - bit_offset: 21 - bit_size: 1 - description: SAI4 Peripheral Clocks Enable During CSleep Mode - name: SAI4LPEN - - bit_offset: 26 - bit_size: 1 - description: Digital temperature sensor block enable during CSleep Mode - name: DTSLPEN + - name: SYSCFGLPEN + description: SYSCFG peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: LPUART1LPEN + description: LPUART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 3 + bit_size: 1 + - name: SPI6LPEN + description: SPI6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: I2C4LPEN + description: I2C4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 7 + bit_size: 1 + - name: LPTIM2LPEN + description: LPTIM2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: LPTIM3LPEN + description: LPTIM3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 10 + bit_size: 1 + - name: LPTIM4LPEN + description: LPTIM4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 11 + bit_size: 1 + - name: LPTIM5LPEN + description: LPTIM5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: COMP12LPEN + description: COMP1/2 peripheral clock enable during CSleep mode + bit_offset: 14 + bit_size: 1 + - name: VREFLPEN + description: VREF peripheral clock enable during CSleep mode + bit_offset: 15 + bit_size: 1 + - name: RTCAPBLPEN + description: RTC APB Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: SAI4LPEN + description: SAI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: DTSLPEN + description: Digital temperature sensor block enable during CSleep Mode + bit_offset: 26 + bit_size: 1 fieldset/APB4RSTR: description: RCC APB4 Peripheral Reset Register fields: - - bit_offset: 1 - bit_size: 1 - description: SYSCFG block reset - name: SYSCFGRST - - bit_offset: 3 - bit_size: 1 - description: LPUART1 block reset - name: LPUART1RST - - bit_offset: 5 - bit_size: 1 - description: SPI6 block reset - name: SPI6RST - - bit_offset: 7 - bit_size: 1 - description: I2C4 block reset - name: I2C4RST - - bit_offset: 9 - bit_size: 1 - description: LPTIM2 block reset - name: LPTIM2RST - - bit_offset: 10 - bit_size: 1 - description: LPTIM3 block reset - name: LPTIM3RST - - bit_offset: 11 - bit_size: 1 - description: LPTIM4 block reset - name: LPTIM4RST - - bit_offset: 12 - bit_size: 1 - description: LPTIM5 block reset - name: LPTIM5RST - - bit_offset: 14 - bit_size: 1 - description: COMP12 Blocks Reset - name: COMP12RST - - bit_offset: 15 - bit_size: 1 - description: VREF block reset - name: VREFRST - - bit_offset: 21 - bit_size: 1 - description: SAI4 block reset - name: SAI4RST - - bit_offset: 26 - bit_size: 1 - description: Digital temperature sensor block reset - name: DTSRST + - name: SYSCFGRST + description: SYSCFG block reset + bit_offset: 1 + bit_size: 1 + - name: LPUART1RST + description: LPUART1 block reset + bit_offset: 3 + bit_size: 1 + - name: SPI6RST + description: SPI6 block reset + bit_offset: 5 + bit_size: 1 + - name: I2C4RST + description: I2C4 block reset + bit_offset: 7 + bit_size: 1 + - name: LPTIM2RST + description: LPTIM2 block reset + bit_offset: 9 + bit_size: 1 + - name: LPTIM3RST + description: LPTIM3 block reset + bit_offset: 10 + bit_size: 1 + - name: LPTIM4RST + description: LPTIM4 block reset + bit_offset: 11 + bit_size: 1 + - name: LPTIM5RST + description: LPTIM5 block reset + bit_offset: 12 + bit_size: 1 + - name: COMP12RST + description: COMP12 Blocks Reset + bit_offset: 14 + bit_size: 1 + - name: VREFRST + description: VREF block reset + bit_offset: 15 + bit_size: 1 + - name: SAI4RST + description: SAI4 block reset + bit_offset: 21 + bit_size: 1 + - name: DTSRST + description: Digital temperature sensor block reset + bit_offset: 26 + bit_size: 1 fieldset/BDCR: description: RCC Backup Domain Control Register fields: - - bit_offset: 0 - bit_size: 1 - description: LSE oscillator enabled - name: LSEON - - bit_offset: 1 - bit_size: 1 - description: LSE oscillator ready - enum_read: LSERDYR - name: LSERDY - - bit_offset: 2 - bit_size: 1 - description: LSE oscillator bypass - enum: LSEBYP - name: LSEBYP - - bit_offset: 3 - bit_size: 2 - description: LSE oscillator driving capability - enum: LSEDRV - name: LSEDRV - - bit_offset: 5 - bit_size: 1 - description: LSE clock security system enable - name: LSECSSON - - bit_offset: 6 - bit_size: 1 - description: LSE clock security system failure detection - enum_read: LSECSSDR - name: LSECSSD - - bit_offset: 8 - bit_size: 2 - description: RTC clock source selection - enum: RTCSEL - name: RTCSEL - - bit_offset: 15 - bit_size: 1 - description: RTC clock enable - name: RTCEN - - bit_offset: 16 - bit_size: 1 - description: VSwitch domain software reset - name: BDRST + - name: LSEON + description: LSE oscillator enabled + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSERDYR + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + enum: LSEBYP + - name: LSEDRV + description: LSE oscillator driving capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: LSE clock security system enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: LSE clock security system failure detection + bit_offset: 6 + bit_size: 1 + enum_read: LSECSSDR + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: VSwitch domain software reset + bit_offset: 16 + bit_size: 1 fieldset/C1_AHB1ENR: description: RCC AHB1 Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA1 Clock Enable - name: DMA1EN - - bit_offset: 1 - bit_size: 1 - description: DMA2 Clock Enable - name: DMA2EN - - bit_offset: 5 - bit_size: 1 - description: ADC1/2 Peripheral Clocks Enable - name: ADC12EN - - bit_offset: 14 - bit_size: 1 - description: ART Clock Enable - name: ARTEN - - bit_offset: 15 - bit_size: 1 - description: Ethernet MAC bus interface Clock Enable - name: ETH1MACEN - - bit_offset: 16 - bit_size: 1 - description: Ethernet Transmission Clock Enable - name: ETH1TXEN - - bit_offset: 17 - bit_size: 1 - description: Ethernet Reception Clock Enable - name: ETH1RXEN - - bit_offset: 25 - bit_size: 1 - description: USB1OTG Peripheral Clocks Enable - name: USB1OTGEN - - bit_offset: 26 - bit_size: 1 - description: USB_PHY1 Clocks Enable - name: USB1ULPIEN - - bit_offset: 27 - bit_size: 1 - description: USB2OTG Peripheral Clocks Enable - name: USB2OTGEN - - bit_offset: 28 - bit_size: 1 - description: USB_PHY2 Clocks Enable - name: USB2ULPIEN + - name: DMA1EN + description: DMA1 Clock Enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 Clock Enable + bit_offset: 1 + bit_size: 1 + - name: ADC12EN + description: ADC1/2 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: ARTEN + description: ART Clock Enable + bit_offset: 14 + bit_size: 1 + - name: ETH1MACEN + description: Ethernet MAC bus interface Clock Enable + bit_offset: 15 + bit_size: 1 + - name: ETH1TXEN + description: Ethernet Transmission Clock Enable + bit_offset: 16 + bit_size: 1 + - name: ETH1RXEN + description: Ethernet Reception Clock Enable + bit_offset: 17 + bit_size: 1 + - name: USB1OTGEN + description: USB1OTG Peripheral Clocks Enable + bit_offset: 25 + bit_size: 1 + - name: USB1ULPIEN + description: USB_PHY1 Clocks Enable + bit_offset: 26 + bit_size: 1 + - name: USB2OTGEN + description: USB2OTG Peripheral Clocks Enable + bit_offset: 27 + bit_size: 1 + - name: USB2ULPIEN + description: USB_PHY2 Clocks Enable + bit_offset: 28 + bit_size: 1 fieldset/C1_AHB1LPENR: description: RCC AHB1 Sleep Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA1 Clock Enable During CSleep Mode - name: DMA1LPEN - - bit_offset: 1 - bit_size: 1 - description: DMA2 Clock Enable During CSleep Mode - name: DMA2LPEN - - bit_offset: 5 - bit_size: 1 - description: ADC1/2 Peripheral Clocks Enable During CSleep Mode - name: ADC12LPEN - - bit_offset: 14 - bit_size: 1 - description: ART Clock Enable During CSleep Mode - name: ARTLPEN - - bit_offset: 15 - bit_size: 1 - description: Ethernet MAC bus interface Clock Enable During CSleep Mode - name: ETH1MACLPEN - - bit_offset: 16 - bit_size: 1 - description: Ethernet Transmission Clock Enable During CSleep Mode - name: ETH1TXLPEN - - bit_offset: 17 - bit_size: 1 - description: Ethernet Reception Clock Enable During CSleep Mode - name: ETH1RXLPEN - - bit_offset: 25 - bit_size: 1 - description: USB1OTG peripheral clock enable during CSleep mode - name: USB1OTGLPEN - - bit_offset: 26 - bit_size: 1 - description: USB_PHY1 clock enable during CSleep mode - name: USB1ULPILPEN - - bit_offset: 27 - bit_size: 1 - description: USB2OTG peripheral clock enable during CSleep mode - name: USB2OTGLPEN - - bit_offset: 28 - bit_size: 1 - description: USB_PHY2 clocks enable during CSleep mode - name: USB2ULPILPEN + - name: DMA1LPEN + description: DMA1 Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 Clock Enable During CSleep Mode + bit_offset: 1 + bit_size: 1 + - name: ADC12LPEN + description: ADC1/2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: ARTLPEN + description: ART Clock Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: ETH1MACLPEN + description: Ethernet MAC bus interface Clock Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + - name: ETH1TXLPEN + description: Ethernet Transmission Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: ETH1RXLPEN + description: Ethernet Reception Clock Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: USB1OTGLPEN + description: USB1OTG peripheral clock enable during CSleep mode + bit_offset: 25 + bit_size: 1 + - name: USB1ULPILPEN + description: USB_PHY1 clock enable during CSleep mode + bit_offset: 26 + bit_size: 1 + - name: USB2OTGLPEN + description: USB2OTG peripheral clock enable during CSleep mode + bit_offset: 27 + bit_size: 1 + - name: USB2ULPILPEN + description: USB_PHY2 clocks enable during CSleep mode + bit_offset: 28 + bit_size: 1 fieldset/C1_AHB2ENR: description: RCC AHB2 Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: DCMI peripheral clock - name: DCMIEN - - bit_offset: 4 - bit_size: 1 - description: CRYPT peripheral clock enable - name: CRYPTEN - - bit_offset: 5 - bit_size: 1 - description: HASH peripheral clock enable - name: HASHEN - - bit_offset: 6 - bit_size: 1 - description: RNG peripheral clocks enable - name: RNGEN - - bit_offset: 9 - bit_size: 1 - description: SDMMC2 and SDMMC2 delay clock enable - name: SDMMC2EN - - bit_offset: 29 - bit_size: 1 - description: SRAM1 block enable - name: SRAM1EN - - bit_offset: 30 - bit_size: 1 - description: SRAM2 block enable - name: SRAM2EN - - bit_offset: 31 - bit_size: 1 - description: SRAM3 block enable - name: SRAM3EN + - name: DCMIEN + description: DCMI peripheral clock + bit_offset: 0 + bit_size: 1 + - name: CRYPTEN + description: CRYPT peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: HASHEN + description: HASH peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: RNGEN + description: RNG peripheral clocks enable + bit_offset: 6 + bit_size: 1 + - name: SDMMC2EN + description: SDMMC2 and SDMMC2 delay clock enable + bit_offset: 9 + bit_size: 1 + - name: SRAM1EN + description: SRAM1 block enable + bit_offset: 29 + bit_size: 1 + - name: SRAM2EN + description: SRAM2 block enable + bit_offset: 30 + bit_size: 1 + - name: SRAM3EN + description: SRAM3 block enable + bit_offset: 31 + bit_size: 1 fieldset/C1_AHB2LPENR: description: RCC AHB2 Sleep Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: DCMI peripheral clock enable during csleep mode - name: DCMILPEN - - bit_offset: 4 - bit_size: 1 - description: CRYPT peripheral clock enable during CSleep mode - name: CRYPTLPEN - - bit_offset: 5 - bit_size: 1 - description: HASH peripheral clock enable during CSleep mode - name: HASHLPEN - - bit_offset: 6 - bit_size: 1 - description: RNG peripheral clock enable during CSleep mode - name: RNGLPEN - - bit_offset: 9 - bit_size: 1 - description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - name: SDMMC2LPEN - - bit_offset: 16 - bit_size: 1 - description: FMAC enable during CSleep Mode - name: FMACLPEN - - bit_offset: 17 - bit_size: 1 - description: CORDIC enable during CSleep Mode - name: CORDICLPEN - - bit_offset: 29 - bit_size: 1 - description: SRAM1 Clock Enable During CSleep Mode - name: SRAM1LPEN - - bit_offset: 30 - bit_size: 1 - description: SRAM2 Clock Enable During CSleep Mode - name: SRAM2LPEN - - bit_offset: 31 - bit_size: 1 - description: SRAM3 Clock Enable During CSleep Mode - name: SRAM3LPEN + - name: DCMILPEN + description: DCMI peripheral clock enable during csleep mode + bit_offset: 0 + bit_size: 1 + - name: CRYPTLPEN + description: CRYPT peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: HASHLPEN + description: HASH peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: RNGLPEN + description: RNG peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: SDMMC2LPEN + description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: FMACLPEN + description: FMAC enable during CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: CORDICLPEN + description: CORDIC enable during CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: SRAM1LPEN + description: SRAM1 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 + - name: SRAM2LPEN + description: SRAM2 Clock Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + - name: SRAM3LPEN + description: SRAM3 Clock Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 fieldset/C1_AHB3ENR: description: RCC AHB3 Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: MDMA Peripheral Clock Enable - name: MDMAEN - - bit_offset: 4 - bit_size: 1 - description: DMA2D Peripheral Clock Enable - name: DMA2DEN - - bit_offset: 5 - bit_size: 1 - description: JPGDEC Peripheral Clock Enable - name: JPGDECEN - - bit_offset: 12 - bit_size: 1 - description: FMC Peripheral Clocks Enable - name: FMCEN - - bit_offset: 14 - bit_size: 1 - description: QUADSPI and QUADSPI Delay Clock Enable - name: QSPIEN - - bit_offset: 16 - bit_size: 1 - description: SDMMC1 and SDMMC1 Delay Clock Enable - name: SDMMC1EN + - name: MDMAEN + description: MDMA Peripheral Clock Enable + bit_offset: 0 + bit_size: 1 + - name: DMA2DEN + description: DMA2D Peripheral Clock Enable + bit_offset: 4 + bit_size: 1 + - name: JPGDECEN + description: JPGDEC Peripheral Clock Enable + bit_offset: 5 + bit_size: 1 + - name: FMCEN + description: FMC Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: QSPIEN + description: QUADSPI and QUADSPI Delay Clock Enable + bit_offset: 14 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 and SDMMC1 Delay Clock Enable + bit_offset: 16 + bit_size: 1 fieldset/C1_AHB3LPENR: description: RCC AHB3 Sleep Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: MDMA Clock Enable During CSleep Mode - name: MDMALPEN - - bit_offset: 4 - bit_size: 1 - description: DMA2D Clock Enable During CSleep Mode - name: DMA2DLPEN - - bit_offset: 5 - bit_size: 1 - description: JPGDEC Clock Enable During CSleep Mode - name: JPGDECLPEN - - bit_offset: 8 - bit_size: 1 - description: Flash interface clock enable during csleep mode - name: FLASHPREN - - bit_offset: 12 - bit_size: 1 - description: FMC Peripheral Clocks Enable During CSleep Mode - name: FMCLPEN - - bit_offset: 14 - bit_size: 1 - description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode - name: QSPILPEN - - bit_offset: 16 - bit_size: 1 - description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - name: SDMMC1LPEN - - bit_offset: 19 - bit_size: 1 - description: OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode - name: OCTOSPI2LPEN - - bit_offset: 21 - bit_size: 1 - description: OCTOSPI IO manager enable during CSleep Mode - name: IOMNGRLPEN - - bit_offset: 22 - bit_size: 1 - description: OTFDEC1 enable during CSleep Mode - name: OTFD1LPEN - - bit_offset: 23 - bit_size: 1 - description: OTFDEC2 enable during CSleep Mode - name: OTFD2LPEN - - bit_offset: 28 - bit_size: 1 - description: D1DTCM1 Block Clock Enable During CSleep mode - name: D1DTCM1LPEN - - bit_offset: 29 - bit_size: 1 - description: D1 DTCM2 Block Clock Enable During CSleep mode - name: DTCM2LPEN - - bit_offset: 30 - bit_size: 1 - description: D1ITCM Block Clock Enable During CSleep mode - name: ITCMLPEN - - bit_offset: 31 - bit_size: 1 - description: AXISRAM Block Clock Enable During CSleep mode - name: AXISRAMLPEN + - name: MDMALPEN + description: MDMA Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + - name: DMA2DLPEN + description: DMA2D Clock Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: JPGDECLPEN + description: JPGDEC Clock Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: FLASHPREN + description: Flash interface clock enable during csleep mode + bit_offset: 8 + bit_size: 1 + - name: FMCLPEN + description: FMC Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: QSPILPEN + description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: SDMMC1LPEN + description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: OCTOSPI2LPEN + description: OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode + bit_offset: 19 + bit_size: 1 + - name: IOMNGRLPEN + description: OCTOSPI IO manager enable during CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: OTFD1LPEN + description: OTFDEC1 enable during CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: OTFD2LPEN + description: OTFDEC2 enable during CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: D1DTCM1LPEN + description: D1DTCM1 Block Clock Enable During CSleep mode + bit_offset: 28 + bit_size: 1 + - name: DTCM2LPEN + description: D1 DTCM2 Block Clock Enable During CSleep mode + bit_offset: 29 + bit_size: 1 + - name: ITCMLPEN + description: D1ITCM Block Clock Enable During CSleep mode + bit_offset: 30 + bit_size: 1 + - name: AXISRAMLPEN + description: AXISRAM Block Clock Enable During CSleep mode + bit_offset: 31 + bit_size: 1 fieldset/C1_AHB4ENR: description: RCC AHB4 Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOAEN - - bit_offset: 1 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOBEN - - bit_offset: 2 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOCEN - - bit_offset: 3 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIODEN - - bit_offset: 4 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOEEN - - bit_offset: 5 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOFEN - - bit_offset: 6 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOGEN - - bit_offset: 7 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOHEN - - bit_offset: 8 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOIEN - - bit_offset: 9 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOJEN - - bit_offset: 10 - bit_size: 1 - description: 0GPIO peripheral clock enable - name: GPIOKEN - - bit_offset: 19 - bit_size: 1 - description: CRC peripheral clock enable - name: CRCEN - - bit_offset: 21 - bit_size: 1 - description: BDMA and DMAMUX2 Clock Enable - name: BDMAEN - - bit_offset: 24 - bit_size: 1 - description: ADC3 Peripheral Clocks Enable - name: ADC3EN - - bit_offset: 25 - bit_size: 1 - description: HSEM peripheral clock enable - name: HSEMEN - - bit_offset: 28 - bit_size: 1 - description: Backup RAM Clock Enable - name: BKPRAMEN + - name: GPIOAEN + description: 0GPIO peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: 0GPIO peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: 0GPIO peripheral clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: 0GPIO peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: 0GPIO peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: 0GPIO peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: 0GPIO peripheral clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: 0GPIO peripheral clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: 0GPIO peripheral clock enable + bit_offset: 8 + bit_size: 1 + - name: GPIOJEN + description: 0GPIO peripheral clock enable + bit_offset: 9 + bit_size: 1 + - name: GPIOKEN + description: 0GPIO peripheral clock enable + bit_offset: 10 + bit_size: 1 + - name: CRCEN + description: CRC peripheral clock enable + bit_offset: 19 + bit_size: 1 + - name: BDMAEN + description: BDMA and DMAMUX2 Clock Enable + bit_offset: 21 + bit_size: 1 + - name: ADC3EN + description: ADC3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + - name: HSEMEN + description: HSEM peripheral clock enable + bit_offset: 25 + bit_size: 1 + - name: BKPRAMEN + description: Backup RAM Clock Enable + bit_offset: 28 + bit_size: 1 fieldset/C1_AHB4LPENR: description: RCC AHB4 Sleep Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOALPEN - - bit_offset: 1 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOBLPEN - - bit_offset: 2 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOCLPEN - - bit_offset: 3 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIODLPEN - - bit_offset: 4 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOELPEN - - bit_offset: 5 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOFLPEN - - bit_offset: 6 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOGLPEN - - bit_offset: 7 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOHLPEN - - bit_offset: 8 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOILPEN - - bit_offset: 9 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOJLPEN - - bit_offset: 10 - bit_size: 1 - description: GPIO peripheral clock enable during CSleep mode - name: GPIOKLPEN - - bit_offset: 19 - bit_size: 1 - description: CRC peripheral clock enable during CSleep mode - name: CRCLPEN - - bit_offset: 21 - bit_size: 1 - description: BDMA Clock Enable During CSleep Mode - name: BDMALPEN - - bit_offset: 24 - bit_size: 1 - description: ADC3 Peripheral Clocks Enable During CSleep Mode - name: ADC3LPEN - - bit_offset: 28 - bit_size: 1 - description: Backup RAM Clock Enable During CSleep Mode - name: BKPRAMLPEN - - bit_offset: 29 - bit_size: 1 - description: SRAM4 Clock Enable During CSleep Mode - name: SRAM4LPEN + - name: GPIOALPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: GPIOFLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: GPIOHLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + - name: GPIOILPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + - name: GPIOJLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 9 + bit_size: 1 + - name: GPIOKLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 10 + bit_size: 1 + - name: CRCLPEN + description: CRC peripheral clock enable during CSleep mode + bit_offset: 19 + bit_size: 1 + - name: BDMALPEN + description: BDMA Clock Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: ADC3LPEN + description: ADC3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: BKPRAMLPEN + description: Backup RAM Clock Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + - name: SRAM4LPEN + description: SRAM4 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 fieldset/C1_APB1HENR: description: RCC APB1 Clock Register fields: - - bit_offset: 1 - bit_size: 1 - description: Clock Recovery System peripheral clock enable - name: CRSEN - - bit_offset: 2 - bit_size: 1 - description: SWPMI Peripheral Clocks Enable - name: SWPEN - - bit_offset: 4 - bit_size: 1 - description: OPAMP peripheral clock enable - name: OPAMPEN - - bit_offset: 5 - bit_size: 1 - description: MDIOS peripheral clock enable - name: MDIOSEN - - bit_offset: 8 - bit_size: 1 - description: FDCAN Peripheral Clocks Enable - name: FDCANEN + - name: CRSEN + description: Clock Recovery System peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: SWPEN + description: SWPMI Peripheral Clocks Enable + bit_offset: 2 + bit_size: 1 + - name: OPAMPEN + description: OPAMP peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: MDIOSEN + description: MDIOS peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: FDCANEN + description: FDCAN Peripheral Clocks Enable + bit_offset: 8 + bit_size: 1 fieldset/C1_APB1HLPENR: description: RCC APB1 High Sleep Clock Register fields: - - bit_offset: 1 - bit_size: 1 - description: Clock Recovery System peripheral clock enable during CSleep mode - name: CRSLPEN - - bit_offset: 2 - bit_size: 1 - description: SWPMI Peripheral Clocks Enable During CSleep Mode - name: SWPLPEN - - bit_offset: 4 - bit_size: 1 - description: OPAMP peripheral clock enable during CSleep mode - name: OPAMPLPEN - - bit_offset: 5 - bit_size: 1 - description: MDIOS peripheral clock enable during CSleep mode - name: MDIOSLPEN - - bit_offset: 8 - bit_size: 1 - description: FDCAN Peripheral Clocks Enable During CSleep Mode - name: FDCANLPEN - - bit_offset: 24 - bit_size: 1 - description: TIM23 block enable during CSleep Mode - name: TIM23LPEN - - bit_offset: 25 - bit_size: 1 - description: TIM24 block enable during CSleep Mode - name: TIM24LPEN + - name: CRSLPEN + description: Clock Recovery System peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: SWPLPEN + description: SWPMI Peripheral Clocks Enable During CSleep Mode + bit_offset: 2 + bit_size: 1 + - name: OPAMPLPEN + description: OPAMP peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: MDIOSLPEN + description: MDIOS peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: FDCANLPEN + description: FDCAN Peripheral Clocks Enable During CSleep Mode + bit_offset: 8 + bit_size: 1 + - name: TIM23LPEN + description: TIM23 block enable during CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: TIM24LPEN + description: TIM24 block enable during CSleep Mode + bit_offset: 25 + bit_size: 1 fieldset/C1_APB1LENR: description: RCC APB1 Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM2EN - - bit_offset: 1 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM3EN - - bit_offset: 2 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM4EN - - bit_offset: 3 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM5EN - - bit_offset: 4 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM6EN - - bit_offset: 5 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM7EN - - bit_offset: 6 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM12EN - - bit_offset: 7 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM13EN - - bit_offset: 8 - bit_size: 1 - description: TIM peripheral clock enable - name: TIM14EN - - bit_offset: 9 - bit_size: 1 - description: LPTIM1 Peripheral Clocks Enable - name: LPTIM1EN - - bit_offset: 11 - bit_size: 1 - description: WWDG2 peripheral clock enable - name: WWDG2EN - - bit_offset: 14 - bit_size: 1 - description: SPI2 Peripheral Clocks Enable - name: SPI2EN - - bit_offset: 15 - bit_size: 1 - description: SPI3 Peripheral Clocks Enable - name: SPI3EN - - bit_offset: 16 - bit_size: 1 - description: SPDIFRX Peripheral Clocks Enable - name: SPDIFRXEN - - bit_offset: 17 - bit_size: 1 - description: USART2 Peripheral Clocks Enable - name: USART2EN - - bit_offset: 18 - bit_size: 1 - description: USART3 Peripheral Clocks Enable - name: USART3EN - - bit_offset: 19 - bit_size: 1 - description: UART4 Peripheral Clocks Enable - name: UART4EN - - bit_offset: 20 - bit_size: 1 - description: UART5 Peripheral Clocks Enable - name: UART5EN - - bit_offset: 21 - bit_size: 1 - description: I2C1 Peripheral Clocks Enable - name: I2C1EN - - bit_offset: 22 - bit_size: 1 - description: I2C2 Peripheral Clocks Enable - name: I2C2EN - - bit_offset: 23 - bit_size: 1 - description: I2C3 Peripheral Clocks Enable - name: I2C3EN - - bit_offset: 25 - bit_size: 1 - description: "I2C5 Peripheral Clocks\r Enable" - name: I2C5EN - - bit_offset: 27 - bit_size: 1 - description: HDMI-CEC peripheral clock enable - name: CECEN - - bit_offset: 29 - bit_size: 1 - description: DAC1&2 peripheral clock enable - name: DAC12EN - - bit_offset: 30 - bit_size: 1 - description: UART7 Peripheral Clocks Enable - name: UART7EN - - bit_offset: 31 - bit_size: 1 - description: UART8 Peripheral Clocks Enable - name: UART8EN + - name: TIM2EN + description: TIM peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM peripheral clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM peripheral clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM peripheral clock enable + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: TIM peripheral clock enable + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: TIM peripheral clock enable + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: TIM peripheral clock enable + bit_offset: 8 + bit_size: 1 + - name: LPTIM1EN + description: LPTIM1 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + - name: WWDG2EN + description: WWDG2 peripheral clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 Peripheral Clocks Enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 Peripheral Clocks Enable + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXEN + description: SPDIFRX Peripheral Clocks Enable + bit_offset: 16 + bit_size: 1 + - name: USART2EN + description: USART2 Peripheral Clocks Enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 Peripheral Clocks Enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 Peripheral Clocks Enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + - name: I2C5EN + description: "I2C5 Peripheral Clocks\r Enable" + bit_offset: 25 + bit_size: 1 + - name: CECEN + description: HDMI-CEC peripheral clock enable + bit_offset: 27 + bit_size: 1 + - name: DAC12EN + description: DAC1&2 peripheral clock enable + bit_offset: 29 + bit_size: 1 + - name: UART7EN + description: UART7 Peripheral Clocks Enable + bit_offset: 30 + bit_size: 1 + - name: UART8EN + description: UART8 Peripheral Clocks Enable + bit_offset: 31 + bit_size: 1 fieldset/C1_APB1LLPENR: description: RCC APB1 Low Sleep Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 peripheral clock enable during CSleep mode - name: TIM2LPEN - - bit_offset: 1 - bit_size: 1 - description: TIM3 peripheral clock enable during CSleep mode - name: TIM3LPEN - - bit_offset: 2 - bit_size: 1 - description: TIM4 peripheral clock enable during CSleep mode - name: TIM4LPEN - - bit_offset: 3 - bit_size: 1 - description: TIM5 peripheral clock enable during CSleep mode - name: TIM5LPEN - - bit_offset: 4 - bit_size: 1 - description: TIM6 peripheral clock enable during CSleep mode - name: TIM6LPEN - - bit_offset: 5 - bit_size: 1 - description: TIM7 peripheral clock enable during CSleep mode - name: TIM7LPEN - - bit_offset: 6 - bit_size: 1 - description: TIM12 peripheral clock enable during CSleep mode - name: TIM12LPEN - - bit_offset: 7 - bit_size: 1 - description: TIM13 peripheral clock enable during CSleep mode - name: TIM13LPEN - - bit_offset: 8 - bit_size: 1 - description: TIM14 peripheral clock enable during CSleep mode - name: TIM14LPEN - - bit_offset: 9 - bit_size: 1 - description: LPTIM1 Peripheral Clocks Enable During CSleep Mode - name: LPTIM1LPEN - - bit_offset: 11 - bit_size: 1 - description: WWDG2 peripheral Clocks Enable During CSleep Mode - name: WWDG2LPEN - - bit_offset: 14 - bit_size: 1 - description: SPI2 Peripheral Clocks Enable During CSleep Mode - name: SPI2LPEN - - bit_offset: 15 - bit_size: 1 - description: SPI3 Peripheral Clocks Enable During CSleep Mode - name: SPI3LPEN - - bit_offset: 16 - bit_size: 1 - description: SPDIFRX Peripheral Clocks Enable During CSleep Mode - name: SPDIFRXLPEN - - bit_offset: 17 - bit_size: 1 - description: USART2 Peripheral Clocks Enable During CSleep Mode - name: USART2LPEN - - bit_offset: 18 - bit_size: 1 - description: USART3 Peripheral Clocks Enable During CSleep Mode - name: USART3LPEN - - bit_offset: 19 - bit_size: 1 - description: UART4 Peripheral Clocks Enable During CSleep Mode - name: UART4LPEN - - bit_offset: 20 - bit_size: 1 - description: UART5 Peripheral Clocks Enable During CSleep Mode - name: UART5LPEN - - bit_offset: 21 - bit_size: 1 - description: I2C1 Peripheral Clocks Enable During CSleep Mode - name: I2C1LPEN - - bit_offset: 22 - bit_size: 1 - description: I2C2 Peripheral Clocks Enable During CSleep Mode - name: I2C2LPEN - - bit_offset: 23 - bit_size: 1 - description: I2C3 Peripheral Clocks Enable During CSleep Mode - name: I2C3LPEN - - bit_offset: 25 - bit_size: 1 - description: I2C5 block enable during CSleep Mode - name: I2C5LPEN - - bit_offset: 27 - bit_size: 1 - description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode - name: CECLPEN - - bit_offset: 29 - bit_size: 1 - description: DAC1/2 peripheral clock enable during CSleep mode - name: DAC12LPEN - - bit_offset: 30 - bit_size: 1 - description: UART7 Peripheral Clocks Enable During CSleep Mode - name: UART7LPEN - - bit_offset: 31 - bit_size: 1 - description: UART8 Peripheral Clocks Enable During CSleep Mode - name: UART8LPEN + - name: TIM2LPEN + description: TIM2 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: TIM3 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: TIM4 peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: TIM5 peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: TIM6 peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: TIM7 peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + - name: TIM12LPEN + description: TIM12 peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + - name: TIM13LPEN + description: TIM13 peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + - name: TIM14LPEN + description: TIM14 peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + - name: LPTIM1LPEN + description: LPTIM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: WWDG2LPEN + description: WWDG2 peripheral Clocks Enable During CSleep Mode + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: SPI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXLPEN + description: SPDIFRX Peripheral Clocks Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: USART2LPEN + description: USART2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: USART3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: UART4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: UART5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + - name: I2C1LPEN + description: I2C1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: I2C3LPEN + description: I2C3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: I2C5LPEN + description: I2C5 block enable during CSleep Mode + bit_offset: 25 + bit_size: 1 + - name: CECLPEN + description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode + bit_offset: 27 + bit_size: 1 + - name: DAC12LPEN + description: DAC1/2 peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 + - name: UART7LPEN + description: UART7 Peripheral Clocks Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + - name: UART8LPEN + description: UART8 Peripheral Clocks Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 fieldset/C1_APB2ENR: description: RCC APB2 Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM1 peripheral clock enable - name: TIM1EN - - bit_offset: 1 - bit_size: 1 - description: TIM8 peripheral clock enable - name: TIM8EN - - bit_offset: 4 - bit_size: 1 - description: USART1 Peripheral Clocks Enable - name: USART1EN - - bit_offset: 5 - bit_size: 1 - description: USART6 Peripheral Clocks Enable - name: USART6EN - - bit_offset: 6 - bit_size: 1 - description: "UART9 Peripheral Clocks\r Enable" - name: UART9EN - - bit_offset: 7 - bit_size: 1 - description: "USART10 Peripheral Clocks\r Enable" - name: USART10EN - - bit_offset: 12 - bit_size: 1 - description: SPI1 Peripheral Clocks Enable - name: SPI1EN - - bit_offset: 13 - bit_size: 1 - description: SPI4 Peripheral Clocks Enable - name: SPI4EN - - bit_offset: 16 - bit_size: 1 - description: TIM15 peripheral clock enable - name: TIM15EN - - bit_offset: 17 - bit_size: 1 - description: TIM16 peripheral clock enable - name: TIM16EN - - bit_offset: 18 - bit_size: 1 - description: TIM17 peripheral clock enable - name: TIM17EN - - bit_offset: 20 - bit_size: 1 - description: SPI5 Peripheral Clocks Enable - name: SPI5EN - - bit_offset: 22 - bit_size: 1 - description: SAI1 Peripheral Clocks Enable - name: SAI1EN - - bit_offset: 23 - bit_size: 1 - description: SAI2 Peripheral Clocks Enable - name: SAI2EN - - bit_offset: 24 - bit_size: 1 - description: SAI3 Peripheral Clocks Enable - name: SAI3EN - - bit_offset: 28 - bit_size: 1 - description: DFSDM1 Peripheral Clocks Enable - name: DFSDM1EN - - bit_offset: 29 - bit_size: 1 - description: HRTIM peripheral clock enable - name: HRTIMEN + - name: TIM1EN + description: TIM1 peripheral clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM8EN + description: TIM8 peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: USART1EN + description: USART1 Peripheral Clocks Enable + bit_offset: 4 + bit_size: 1 + - name: USART6EN + description: USART6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: UART9EN + description: "UART9 Peripheral Clocks\r Enable" + bit_offset: 6 + bit_size: 1 + - name: USART10EN + description: "USART10 Peripheral Clocks\r Enable" + bit_offset: 7 + bit_size: 1 + - name: SPI1EN + description: SPI1 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: SPI4EN + description: SPI4 Peripheral Clocks Enable + bit_offset: 13 + bit_size: 1 + - name: TIM15EN + description: TIM15 peripheral clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 peripheral clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 peripheral clock enable + bit_offset: 18 + bit_size: 1 + - name: SPI5EN + description: SPI5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + - name: SAI1EN + description: SAI1 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + - name: SAI2EN + description: SAI2 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + - name: SAI3EN + description: SAI3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + - name: DFSDM1EN + description: DFSDM1 Peripheral Clocks Enable + bit_offset: 28 + bit_size: 1 + - name: HRTIMEN + description: HRTIM peripheral clock enable + bit_offset: 29 + bit_size: 1 fieldset/C1_APB2LPENR: description: RCC APB2 Sleep Clock Register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM1 peripheral clock enable during CSleep mode - name: TIM1LPEN - - bit_offset: 1 - bit_size: 1 - description: TIM8 peripheral clock enable during CSleep mode - name: TIM8LPEN - - bit_offset: 4 - bit_size: 1 - description: USART1 Peripheral Clocks Enable During CSleep Mode - name: USART1LPEN - - bit_offset: 5 - bit_size: 1 - description: USART6 Peripheral Clocks Enable During CSleep Mode - name: USART6LPEN - - bit_offset: 12 - bit_size: 1 - description: SPI1 Peripheral Clocks Enable During CSleep Mode - name: SPI1LPEN - - bit_offset: 13 - bit_size: 1 - description: SPI4 Peripheral Clocks Enable During CSleep Mode - name: SPI4LPEN - - bit_offset: 16 - bit_size: 1 - description: TIM15 peripheral clock enable during CSleep mode - name: TIM15LPEN - - bit_offset: 17 - bit_size: 1 - description: TIM16 peripheral clock enable during CSleep mode - name: TIM16LPEN - - bit_offset: 18 - bit_size: 1 - description: TIM17 peripheral clock enable during CSleep mode - name: TIM17LPEN - - bit_offset: 20 - bit_size: 1 - description: SPI5 Peripheral Clocks Enable During CSleep Mode - name: SPI5LPEN - - bit_offset: 22 - bit_size: 1 - description: SAI1 Peripheral Clocks Enable During CSleep Mode - name: SAI1LPEN - - bit_offset: 23 - bit_size: 1 - description: SAI2 Peripheral Clocks Enable During CSleep Mode - name: SAI2LPEN - - bit_offset: 24 - bit_size: 1 - description: SAI3 Peripheral Clocks Enable During CSleep Mode - name: SAI3LPEN - - bit_offset: 28 - bit_size: 1 - description: DFSDM1 Peripheral Clocks Enable During CSleep Mode - name: DFSDM1LPEN - - bit_offset: 29 - bit_size: 1 - description: HRTIM peripheral clock enable during CSleep mode - name: HRTIMLPEN + - name: TIM1LPEN + description: TIM1 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM8LPEN + description: TIM8 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: USART1LPEN + description: USART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: USART6LPEN + description: USART6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: SPI1LPEN + description: SPI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: SPI4LPEN + description: SPI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 13 + bit_size: 1 + - name: TIM15LPEN + description: TIM15 peripheral clock enable during CSleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM16LPEN + description: TIM16 peripheral clock enable during CSleep mode + bit_offset: 17 + bit_size: 1 + - name: TIM17LPEN + description: TIM17 peripheral clock enable during CSleep mode + bit_offset: 18 + bit_size: 1 + - name: SPI5LPEN + description: SPI5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + - name: SAI1LPEN + description: SAI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + - name: SAI2LPEN + description: SAI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + - name: SAI3LPEN + description: SAI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + - name: DFSDM1LPEN + description: DFSDM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + - name: HRTIMLPEN + description: HRTIM peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 fieldset/C1_APB3ENR: description: RCC APB3 Clock Register fields: - - bit_offset: 3 - bit_size: 1 - description: LTDC peripheral clock enable - name: LTDCEN - - bit_offset: 4 - bit_size: 1 - description: DSI Peripheral clocks enable - name: DSIEN - - bit_offset: 6 - bit_size: 1 - description: WWDG1 Clock Enable - name: WWDG1EN + - name: LTDCEN + description: LTDC peripheral clock enable + bit_offset: 3 + bit_size: 1 + - name: DSIEN + description: DSI Peripheral clocks enable + bit_offset: 4 + bit_size: 1 + - name: WWDG1EN + description: WWDG1 Clock Enable + bit_offset: 6 + bit_size: 1 fieldset/C1_APB3LPENR: description: RCC APB3 Sleep Clock Register fields: - - bit_offset: 3 - bit_size: 1 - description: LTDC peripheral clock enable during CSleep mode - name: LTDCLPEN - - bit_offset: 4 - bit_size: 1 - description: DSI Peripheral Clock Enable During CSleep Mode - name: DSILPEN - - bit_offset: 6 - bit_size: 1 - description: WWDG1 Clock Enable During CSleep Mode - name: WWDG1LPEN + - name: LTDCLPEN + description: LTDC peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + - name: DSILPEN + description: DSI Peripheral Clock Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + - name: WWDG1LPEN + description: WWDG1 Clock Enable During CSleep Mode + bit_offset: 6 + bit_size: 1 fieldset/C1_APB4ENR: description: RCC APB4 Clock Register fields: - - bit_offset: 1 - bit_size: 1 - description: SYSCFG peripheral clock enable - name: SYSCFGEN - - bit_offset: 3 - bit_size: 1 - description: LPUART1 Peripheral Clocks Enable - name: LPUART1EN - - bit_offset: 5 - bit_size: 1 - description: SPI6 Peripheral Clocks Enable - name: SPI6EN - - bit_offset: 7 - bit_size: 1 - description: I2C4 Peripheral Clocks Enable - name: I2C4EN - - bit_offset: 9 - bit_size: 1 - description: LPTIM2 Peripheral Clocks Enable - name: LPTIM2EN - - bit_offset: 10 - bit_size: 1 - description: LPTIM3 Peripheral Clocks Enable - name: LPTIM3EN - - bit_offset: 11 - bit_size: 1 - description: LPTIM4 Peripheral Clocks Enable - name: LPTIM4EN - - bit_offset: 12 - bit_size: 1 - description: LPTIM5 Peripheral Clocks Enable - name: LPTIM5EN - - bit_offset: 14 - bit_size: 1 - description: COMP1/2 peripheral clock enable - name: COMP12EN - - bit_offset: 15 - bit_size: 1 - description: VREF peripheral clock enable - name: VREFEN - - bit_offset: 16 - bit_size: 1 - description: RTC APB Clock Enable - name: RTCAPBEN - - bit_offset: 21 - bit_size: 1 - description: SAI4 Peripheral Clocks Enable - name: SAI4EN + - name: SYSCFGEN + description: SYSCFG peripheral clock enable + bit_offset: 1 + bit_size: 1 + - name: LPUART1EN + description: LPUART1 Peripheral Clocks Enable + bit_offset: 3 + bit_size: 1 + - name: SPI6EN + description: SPI6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + - name: I2C4EN + description: I2C4 Peripheral Clocks Enable + bit_offset: 7 + bit_size: 1 + - name: LPTIM2EN + description: LPTIM2 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + - name: LPTIM3EN + description: LPTIM3 Peripheral Clocks Enable + bit_offset: 10 + bit_size: 1 + - name: LPTIM4EN + description: LPTIM4 Peripheral Clocks Enable + bit_offset: 11 + bit_size: 1 + - name: LPTIM5EN + description: LPTIM5 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + - name: COMP12EN + description: COMP1/2 peripheral clock enable + bit_offset: 14 + bit_size: 1 + - name: VREFEN + description: VREF peripheral clock enable + bit_offset: 15 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB Clock Enable + bit_offset: 16 + bit_size: 1 + - name: SAI4EN + description: SAI4 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 fieldset/C1_APB4LPENR: description: RCC APB4 Sleep Clock Register fields: - - bit_offset: 1 - bit_size: 1 - description: SYSCFG peripheral clock enable during CSleep mode - name: SYSCFGLPEN - - bit_offset: 3 - bit_size: 1 - description: LPUART1 Peripheral Clocks Enable During CSleep Mode - name: LPUART1LPEN - - bit_offset: 5 - bit_size: 1 - description: SPI6 Peripheral Clocks Enable During CSleep Mode - name: SPI6LPEN - - bit_offset: 7 - bit_size: 1 - description: I2C4 Peripheral Clocks Enable During CSleep Mode - name: I2C4LPEN - - bit_offset: 9 - bit_size: 1 - description: LPTIM2 Peripheral Clocks Enable During CSleep Mode - name: LPTIM2LPEN - - bit_offset: 10 - bit_size: 1 - description: LPTIM3 Peripheral Clocks Enable During CSleep Mode - name: LPTIM3LPEN - - bit_offset: 11 - bit_size: 1 - description: LPTIM4 Peripheral Clocks Enable During CSleep Mode - name: LPTIM4LPEN - - bit_offset: 12 - bit_size: 1 - description: LPTIM5 Peripheral Clocks Enable During CSleep Mode - name: LPTIM5LPEN - - bit_offset: 14 - bit_size: 1 - description: COMP1/2 peripheral clock enable during CSleep mode - name: COMP12LPEN - - bit_offset: 15 - bit_size: 1 - description: VREF peripheral clock enable during CSleep mode - name: VREFLPEN - - bit_offset: 16 - bit_size: 1 - description: RTC APB Clock Enable During CSleep Mode - name: RTCAPBLPEN - - bit_offset: 21 - bit_size: 1 - description: SAI4 Peripheral Clocks Enable During CSleep Mode - name: SAI4LPEN - - bit_offset: 26 - bit_size: 1 - description: Digital temperature sensor block enable during CSleep Mode - name: DTSLPEN + - name: SYSCFGLPEN + description: SYSCFG peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + - name: LPUART1LPEN + description: LPUART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 3 + bit_size: 1 + - name: SPI6LPEN + description: SPI6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + - name: I2C4LPEN + description: I2C4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 7 + bit_size: 1 + - name: LPTIM2LPEN + description: LPTIM2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + - name: LPTIM3LPEN + description: LPTIM3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 10 + bit_size: 1 + - name: LPTIM4LPEN + description: LPTIM4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 11 + bit_size: 1 + - name: LPTIM5LPEN + description: LPTIM5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + - name: COMP12LPEN + description: COMP1/2 peripheral clock enable during CSleep mode + bit_offset: 14 + bit_size: 1 + - name: VREFLPEN + description: VREF peripheral clock enable during CSleep mode + bit_offset: 15 + bit_size: 1 + - name: RTCAPBLPEN + description: RTC APB Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + - name: SAI4LPEN + description: SAI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + - name: DTSLPEN + description: Digital temperature sensor block enable during CSleep Mode + bit_offset: 26 + bit_size: 1 fieldset/C1_RSR: description: RCC Reset Status Register fields: - - bit_offset: 16 - bit_size: 1 - description: Remove reset flag - enum: C_RSR_RMVF - name: RMVF - - bit_offset: 17 - bit_size: 1 - description: CPU reset flag - enum_read: C_RSR_CPURSTFR - name: CPURSTF - - bit_offset: 19 - bit_size: 1 - description: D1 domain power switch reset flag - enum_read: C_RSR_CPURSTFR - name: D1RSTF - - bit_offset: 20 - bit_size: 1 - description: D2 domain power switch reset flag - enum_read: C_RSR_CPURSTFR - name: D2RSTF - - bit_offset: 21 - bit_size: 1 - description: BOR reset flag - enum_read: C_RSR_CPURSTFR - name: BORRSTF - - bit_offset: 22 - bit_size: 1 - description: Pin reset flag (NRST) - enum_read: C_RSR_CPURSTFR - name: PINRSTF - - bit_offset: 23 - bit_size: 1 - description: POR/PDR reset flag - enum_read: C_RSR_CPURSTFR - name: PORRSTF - - bit_offset: 24 - bit_size: 1 - description: System reset from CPU reset flag - enum_read: C_RSR_CPURSTFR - name: SFTRSTF - - bit_offset: 26 - bit_size: 1 - description: Independent Watchdog reset flag - enum_read: C_RSR_CPURSTFR - name: IWDG1RSTF - - bit_offset: 28 - bit_size: 1 - description: Window Watchdog reset flag - enum_read: C_RSR_CPURSTFR - name: WWDG1RSTF - - bit_offset: 30 - bit_size: 1 - description: Reset due to illegal D1 DStandby or CPU CStop flag - enum_read: C_RSR_CPURSTFR - name: LPWRRSTF + - name: RMVF + description: Remove reset flag + bit_offset: 16 + bit_size: 1 + enum: C_RSR_RMVF + - name: CPURSTF + description: CPU reset flag + bit_offset: 17 + bit_size: 1 + enum_read: C_RSR_CPURSTFR + - name: D1RSTF + description: D1 domain power switch reset flag + bit_offset: 19 + bit_size: 1 + enum_read: C_RSR_CPURSTFR + - name: D2RSTF + description: D2 domain power switch reset flag + bit_offset: 20 + bit_size: 1 + enum_read: C_RSR_CPURSTFR + - name: BORRSTF + description: BOR reset flag + bit_offset: 21 + bit_size: 1 + enum_read: C_RSR_CPURSTFR + - name: PINRSTF + description: Pin reset flag (NRST) + bit_offset: 22 + bit_size: 1 + enum_read: C_RSR_CPURSTFR + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 23 + bit_size: 1 + enum_read: C_RSR_CPURSTFR + - name: SFTRSTF + description: System reset from CPU reset flag + bit_offset: 24 + bit_size: 1 + enum_read: C_RSR_CPURSTFR + - name: IWDG1RSTF + description: Independent Watchdog reset flag + bit_offset: 26 + bit_size: 1 + enum_read: C_RSR_CPURSTFR + - name: WWDG1RSTF + description: Window Watchdog reset flag + bit_offset: 28 + bit_size: 1 + enum_read: C_RSR_CPURSTFR + - name: LPWRRSTF + description: Reset due to illegal D1 DStandby or CPU CStop flag + bit_offset: 30 + bit_size: 1 + enum_read: C_RSR_CPURSTFR fieldset/CFGR: description: RCC Clock Configuration Register fields: - - bit_offset: 0 - bit_size: 3 - description: System clock switch - enum: SW - name: SW - - bit_offset: 3 - bit_size: 3 - description: System clock switch status - enum_read: SWSR - name: SWS - - bit_offset: 6 - bit_size: 1 - description: System clock selection after a wake up from system Stop - enum: STOPWUCK - name: STOPWUCK - - bit_offset: 7 - bit_size: 1 - description: Kernel clock selection after a wake up from system Stop - enum: STOPWUCK - name: STOPKERWUCK - - bit_offset: 8 - bit_size: 6 - description: HSE division factor for RTC clock - name: RTCPRE - - bit_offset: 14 - bit_size: 1 - description: High Resolution Timer clock prescaler selection - enum: HRTIMSEL - name: HRTIMSEL - - bit_offset: 15 - bit_size: 1 - description: Timers clocks prescaler selection - enum: TIMPRE - name: TIMPRE - - bit_offset: 18 - bit_size: 4 - description: MCO1 prescaler - name: MCO1PRE - - bit_offset: 22 - bit_size: 3 - description: Micro-controller clock output 1 - enum: MCO1 - name: MCO1 - - bit_offset: 25 - bit_size: 4 - description: MCO2 prescaler - name: MCO2PRE - - bit_offset: 29 - bit_size: 3 - description: Micro-controller clock output 2 - enum: MCO2 - name: MCO2 + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 3 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 3 + bit_size: 3 + enum_read: SWSR + - name: STOPWUCK + description: System clock selection after a wake up from system Stop + bit_offset: 6 + bit_size: 1 + enum: STOPWUCK + - name: STOPKERWUCK + description: Kernel clock selection after a wake up from system Stop + bit_offset: 7 + bit_size: 1 + enum: STOPWUCK + - name: RTCPRE + description: HSE division factor for RTC clock + bit_offset: 8 + bit_size: 6 + - name: HRTIMSEL + description: High Resolution Timer clock prescaler selection + bit_offset: 14 + bit_size: 1 + enum: HRTIMSEL + - name: TIMPRE + description: Timers clocks prescaler selection + bit_offset: 15 + bit_size: 1 + enum: TIMPRE + - name: MCO1PRE + description: MCO1 prescaler + bit_offset: 18 + bit_size: 4 + - name: MCO1 + description: Micro-controller clock output 1 + bit_offset: 22 + bit_size: 3 + enum: MCO1 + - name: MCO2PRE + description: MCO2 prescaler + bit_offset: 25 + bit_size: 4 + - name: MCO2 + description: Micro-controller clock output 2 + bit_offset: 29 + bit_size: 3 + enum: MCO2 fieldset/CICR: description: RCC Clock Source Interrupt Clear Register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready Interrupt Clear - enum: LSIRDYC - name: LSIRDYC - - bit_offset: 1 - bit_size: 1 - description: LSE ready Interrupt Clear - enum: LSIRDYC - name: LSERDYC - - bit_offset: 2 - bit_size: 1 - description: HSI ready Interrupt Clear - enum: LSIRDYC - name: HSIRDYC - - bit_offset: 3 - bit_size: 1 - description: HSE ready Interrupt Clear - enum: LSIRDYC - name: HSERDYC - - bit_offset: 4 - bit_size: 1 - description: CSI ready Interrupt Clear - name: HSE_ready_Interrupt_Clear - - bit_offset: 5 - bit_size: 1 - description: RC48 ready Interrupt Clear - enum: LSIRDYC - name: HSI48RDYC - - array: - len: 3 - stride: 1 - bit_offset: 6 - bit_size: 1 - description: PLL1 ready Interrupt Clear - enum: LSIRDYC - name: PLLRDYC - - bit_offset: 9 - bit_size: 1 - description: LSE clock security system Interrupt Clear - enum: LSIRDYC - name: LSECSSC - - bit_offset: 10 - bit_size: 1 - description: HSE clock security system Interrupt Clear - enum: LSIRDYC - name: HSECSSC + - name: LSIRDYC + description: LSI ready Interrupt Clear + bit_offset: 0 + bit_size: 1 + enum: LSIRDYC + - name: LSERDYC + description: LSE ready Interrupt Clear + bit_offset: 1 + bit_size: 1 + enum: LSIRDYC + - name: HSIRDYC + description: HSI ready Interrupt Clear + bit_offset: 2 + bit_size: 1 + enum: LSIRDYC + - name: HSERDYC + description: HSE ready Interrupt Clear + bit_offset: 3 + bit_size: 1 + enum: LSIRDYC + - name: HSE_ready_Interrupt_Clear + description: CSI ready Interrupt Clear + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYC + description: RC48 ready Interrupt Clear + bit_offset: 5 + bit_size: 1 + enum: LSIRDYC + - name: PLLRDYC + description: PLL1 ready Interrupt Clear + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: LSIRDYC + - name: LSECSSC + description: LSE clock security system Interrupt Clear + bit_offset: 9 + bit_size: 1 + enum: LSIRDYC + - name: HSECSSC + description: HSE clock security system Interrupt Clear + bit_offset: 10 + bit_size: 1 + enum: LSIRDYC fieldset/CIER: description: RCC Clock Source Interrupt Enable Register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready Interrupt Enable - enum: LSIRDYIE - name: LSIRDYIE - - bit_offset: 1 - bit_size: 1 - description: LSE ready Interrupt Enable - enum: LSIRDYIE - name: LSERDYIE - - bit_offset: 2 - bit_size: 1 - description: HSI ready Interrupt Enable - enum: LSIRDYIE - name: HSIRDYIE - - bit_offset: 3 - bit_size: 1 - description: HSE ready Interrupt Enable - enum: LSIRDYIE - name: HSERDYIE - - bit_offset: 4 - bit_size: 1 - description: CSI ready Interrupt Enable - enum: LSIRDYIE - name: CSIRDYIE - - bit_offset: 5 - bit_size: 1 - description: RC48 ready Interrupt Enable - enum: LSIRDYIE - name: HSI48RDYIE - - array: - len: 3 - stride: 1 - bit_offset: 6 - bit_size: 1 - description: PLL1 ready Interrupt Enable - enum: LSIRDYIE - name: PLLRDYIE - - bit_offset: 9 - bit_size: 1 - description: LSE clock security system Interrupt Enable - enum: LSIRDYIE - name: LSECSSIE + - name: LSIRDYIE + description: LSI ready Interrupt Enable + bit_offset: 0 + bit_size: 1 + enum: LSIRDYIE + - name: LSERDYIE + description: LSE ready Interrupt Enable + bit_offset: 1 + bit_size: 1 + enum: LSIRDYIE + - name: HSIRDYIE + description: HSI ready Interrupt Enable + bit_offset: 2 + bit_size: 1 + enum: LSIRDYIE + - name: HSERDYIE + description: HSE ready Interrupt Enable + bit_offset: 3 + bit_size: 1 + enum: LSIRDYIE + - name: CSIRDYIE + description: CSI ready Interrupt Enable + bit_offset: 4 + bit_size: 1 + enum: LSIRDYIE + - name: HSI48RDYIE + description: RC48 ready Interrupt Enable + bit_offset: 5 + bit_size: 1 + enum: LSIRDYIE + - name: PLLRDYIE + description: PLL1 ready Interrupt Enable + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: LSIRDYIE + - name: LSECSSIE + description: LSE clock security system Interrupt Enable + bit_offset: 9 + bit_size: 1 + enum: LSIRDYIE fieldset/CIFR: description: RCC Clock Source Interrupt Flag Register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready Interrupt Flag - name: LSIRDYF - - bit_offset: 1 - bit_size: 1 - description: LSE ready Interrupt Flag - name: LSERDYF - - bit_offset: 2 - bit_size: 1 - description: HSI ready Interrupt Flag - name: HSIRDYF - - bit_offset: 3 - bit_size: 1 - description: HSE ready Interrupt Flag - name: HSERDYF - - bit_offset: 4 - bit_size: 1 - description: CSI ready Interrupt Flag - name: CSIRDY - - bit_offset: 5 - bit_size: 1 - description: RC48 ready Interrupt Flag - name: HSI48RDYF - - array: - len: 3 - stride: 1 - bit_offset: 6 - bit_size: 1 - description: PLL1 ready Interrupt Flag - name: PLLRDYF - - bit_offset: 9 - bit_size: 1 - description: LSE clock security system Interrupt Flag - name: LSECSSF - - bit_offset: 10 - bit_size: 1 - description: HSE clock security system Interrupt Flag - name: HSECSSF + - name: LSIRDYF + description: LSI ready Interrupt Flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready Interrupt Flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI ready Interrupt Flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE ready Interrupt Flag + bit_offset: 3 + bit_size: 1 + - name: CSIRDY + description: CSI ready Interrupt Flag + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYF + description: RC48 ready Interrupt Flag + bit_offset: 5 + bit_size: 1 + - name: PLLRDYF + description: PLL1 ready Interrupt Flag + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: LSECSSF + description: LSE clock security system Interrupt Flag + bit_offset: 9 + bit_size: 1 + - name: HSECSSF + description: HSE clock security system Interrupt Flag + bit_offset: 10 + bit_size: 1 fieldset/CR: description: clock control register fields: - - bit_offset: 0 - bit_size: 1 - description: Internal high-speed clock enable - name: HSION - - bit_offset: 1 - bit_size: 1 - description: High Speed Internal clock enable in Stop mode - name: HSIKERON - - bit_offset: 2 - bit_size: 1 - description: HSI clock ready flag - enum_read: HSIRDYR - name: HSIRDY - - bit_offset: 3 - bit_size: 2 - description: HSI clock divider - enum: HSIDIV - name: HSIDIV - - bit_offset: 5 - bit_size: 1 - description: HSI divider flag - enum_read: HSIDIVFR - name: HSIDIVF - - bit_offset: 7 - bit_size: 1 - description: CSI clock enable - name: CSION - - bit_offset: 8 - bit_size: 1 - description: CSI clock ready flag - enum_read: HSIRDYR - name: CSIRDY - - bit_offset: 9 - bit_size: 1 - description: CSI clock enable in Stop mode - name: CSIKERON - - bit_offset: 12 - bit_size: 1 - description: RC48 clock enable - name: HSI48ON - - bit_offset: 13 - bit_size: 1 - description: RC48 clock ready flag - enum_read: HSIRDYR - name: HSI48RDY - - bit_offset: 14 - bit_size: 1 - description: D1 domain clocks ready flag - enum_read: HSIRDYR - name: D1CKRDY - - bit_offset: 15 - bit_size: 1 - description: D2 domain clocks ready flag - enum_read: HSIRDYR - name: D2CKRDY - - bit_offset: 16 - bit_size: 1 - description: HSE clock enable - name: HSEON - - bit_offset: 17 - bit_size: 1 - description: HSE clock ready flag - enum_read: HSIRDYR - name: HSERDY - - bit_offset: 18 - bit_size: 1 - description: HSE clock bypass - enum: HSEBYP - name: HSEBYP - - bit_offset: 19 - bit_size: 1 - description: HSE Clock Security System enable - name: HSECSSON - - array: - len: 3 - stride: 2 - bit_offset: 24 - bit_size: 1 - description: PLL1 enable - name: PLLON - - array: - len: 3 - stride: 2 - bit_offset: 25 - bit_size: 1 - description: PLL1 clock ready flag - enum_read: HSIRDYR - name: PLLRDY + - name: HSION + description: Internal high-speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIKERON + description: High Speed Internal clock enable in Stop mode + bit_offset: 1 + bit_size: 1 + - name: HSIRDY + description: HSI clock ready flag + bit_offset: 2 + bit_size: 1 + enum_read: HSIRDYR + - name: HSIDIV + description: HSI clock divider + bit_offset: 3 + bit_size: 2 + enum: HSIDIV + - name: HSIDIVF + description: HSI divider flag + bit_offset: 5 + bit_size: 1 + enum_read: HSIDIVFR + - name: CSION + description: CSI clock enable + bit_offset: 7 + bit_size: 1 + - name: CSIRDY + description: CSI clock ready flag + bit_offset: 8 + bit_size: 1 + enum_read: HSIRDYR + - name: CSIKERON + description: CSI clock enable in Stop mode + bit_offset: 9 + bit_size: 1 + - name: HSI48ON + description: RC48 clock enable + bit_offset: 12 + bit_size: 1 + - name: HSI48RDY + description: RC48 clock ready flag + bit_offset: 13 + bit_size: 1 + enum_read: HSIRDYR + - name: D1CKRDY + description: D1 domain clocks ready flag + bit_offset: 14 + bit_size: 1 + enum_read: HSIRDYR + - name: D2CKRDY + description: D2 domain clocks ready flag + bit_offset: 15 + bit_size: 1 + enum_read: HSIRDYR + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + enum_read: HSIRDYR + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + enum: HSEBYP + - name: HSECSSON + description: HSE Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL1 enable + bit_offset: 24 + bit_size: 1 + array: + len: 3 + stride: 2 + - name: PLLRDY + description: PLL1 clock ready flag + bit_offset: 25 + bit_size: 1 + array: + len: 3 + stride: 2 + enum_read: HSIRDYR fieldset/CRRCR: description: RCC Clock Recovery RC Register fields: - - bit_offset: 0 - bit_size: 10 - description: Internal RC 48 MHz clock calibration - name: HSI48CAL + - name: HSI48CAL + description: Internal RC 48 MHz clock calibration + bit_offset: 0 + bit_size: 10 fieldset/CSICFGR: description: RCC CSI configuration register fields: - - bit_offset: 0 - bit_size: 9 - description: CSI clock calibration - name: CSICAL - - bit_offset: 24 - bit_size: 6 - description: CSI clock trimming - name: CSITRIM + - name: CSICAL + description: CSI clock calibration + bit_offset: 0 + bit_size: 9 + - name: CSITRIM + description: CSI clock trimming + bit_offset: 24 + bit_size: 6 fieldset/CSR: description: RCC Clock Control and Status Register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI oscillator enable - name: LSION - - bit_offset: 1 - bit_size: 1 - description: LSI oscillator ready - enum_read: LSIRDYR - name: LSIRDY + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSIRDYR fieldset/D1CCIPR: description: RCC Domain 1 Kernel Clock Configuration Register fields: - - bit_offset: 0 - bit_size: 2 - description: FMC kernel clock source selection - enum: FMCSEL - name: FMCSEL - - bit_offset: 4 - bit_size: 2 - description: QUADSPI kernel clock source selection - enum: FMCSEL - name: QSPISEL - - bit_offset: 8 - bit_size: 1 - description: kernel clock source selection - name: DSISEL - - bit_offset: 16 - bit_size: 1 - description: SDMMC kernel clock source selection - enum: SDMMCSEL - name: SDMMCSEL - - bit_offset: 28 - bit_size: 2 - description: per_ck clock source selection - enum: CKPERSEL - name: CKPERSEL + - name: FMCSEL + description: FMC kernel clock source selection + bit_offset: 0 + bit_size: 2 + enum: FMCSEL + - name: QSPISEL + description: QUADSPI kernel clock source selection + bit_offset: 4 + bit_size: 2 + enum: FMCSEL + - name: DSISEL + description: kernel clock source selection + bit_offset: 8 + bit_size: 1 + - name: SDMMCSEL + description: SDMMC kernel clock source selection + bit_offset: 16 + bit_size: 1 + enum: SDMMCSEL + - name: CKPERSEL + description: per_ck clock source selection + bit_offset: 28 + bit_size: 2 + enum: CKPERSEL fieldset/D1CFGR: description: RCC Domain 1 Clock Configuration Register fields: - - bit_offset: 0 - bit_size: 4 - description: D1 domain AHB prescaler - enum: HPRE - name: HPRE - - bit_offset: 4 - bit_size: 3 - description: D1 domain APB3 prescaler - enum: DPPRE - name: D1PPRE - - bit_offset: 8 - bit_size: 4 - description: D1 domain Core prescaler - enum: HPRE - name: D1CPRE + - name: HPRE + description: D1 domain AHB prescaler + bit_offset: 0 + bit_size: 4 + enum: HPRE + - name: D1PPRE + description: D1 domain APB3 prescaler + bit_offset: 4 + bit_size: 3 + enum: DPPRE + - name: D1CPRE + description: D1 domain Core prescaler + bit_offset: 8 + bit_size: 4 + enum: HPRE fieldset/D2CCIP1R: description: RCC Domain 2 Kernel Clock Configuration Register fields: - - bit_offset: 0 - bit_size: 3 - description: SAI1 and DFSDM1 kernel Aclk clock source selection - enum: SAISEL - name: SAI1SEL - - bit_offset: 6 - bit_size: 3 - description: SAI2 and SAI3 kernel clock source selection - enum: SAISEL - name: SAI23SEL - - bit_offset: 12 - bit_size: 3 - description: SPI/I2S1,2 and 3 kernel clock source selection - enum: SAISEL - name: SPI123SEL - - bit_offset: 16 - bit_size: 3 - description: SPI4 and 5 kernel clock source selection - enum: SPI45SEL - name: SPI45SEL - - bit_offset: 20 - bit_size: 2 - description: SPDIFRX kernel clock source selection - enum: SPDIFSEL - name: SPDIFSEL - - bit_offset: 24 - bit_size: 1 - description: DFSDM1 kernel Clk clock source selection - enum: DFSDMSEL - name: DFSDM1SEL - - bit_offset: 28 - bit_size: 2 - description: FDCAN kernel clock source selection - enum: FDCANSEL - name: FDCANSEL - - bit_offset: 31 - bit_size: 1 - description: SWPMI kernel clock source selection - enum: SWPSEL - name: SWPSEL + - name: SAI1SEL + description: SAI1 and DFSDM1 kernel Aclk clock source selection + bit_offset: 0 + bit_size: 3 + enum: SAISEL + - name: SAI23SEL + description: SAI2 and SAI3 kernel clock source selection + bit_offset: 6 + bit_size: 3 + enum: SAISEL + - name: SPI123SEL + description: "SPI/I2S1,2 and 3 kernel clock source selection" + bit_offset: 12 + bit_size: 3 + enum: SAISEL + - name: SPI45SEL + description: SPI4 and 5 kernel clock source selection + bit_offset: 16 + bit_size: 3 + enum: SPI45SEL + - name: SPDIFSEL + description: SPDIFRX kernel clock source selection + bit_offset: 20 + bit_size: 2 + enum: SPDIFSEL + - name: DFSDM1SEL + description: DFSDM1 kernel Clk clock source selection + bit_offset: 24 + bit_size: 1 + enum: DFSDMSEL + - name: FDCANSEL + description: FDCAN kernel clock source selection + bit_offset: 28 + bit_size: 2 + enum: FDCANSEL + - name: SWPSEL + description: SWPMI kernel clock source selection + bit_offset: 31 + bit_size: 1 + enum: SWPSEL fieldset/D2CCIP2R: description: RCC Domain 2 Kernel Clock Configuration Register fields: - - bit_offset: 0 - bit_size: 3 - description: USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection - enum: USART234578SEL - name: USART234578SEL - - bit_offset: 3 - bit_size: 3 - description: USART1 and 6 kernel clock source selection - enum: USART16910SEL - name: USART16910SEL - - bit_offset: 8 - bit_size: 2 - description: RNG kernel clock source selection - enum: RNGSEL - name: RNGSEL - - bit_offset: 12 - bit_size: 2 - description: I2C1,2,3 kernel clock source selection - enum: I2C1235SEL - name: I2C1235SEL - - bit_offset: 20 - bit_size: 2 - description: USBOTG 1 and 2 kernel clock source selection - enum: USBSEL - name: USBSEL - - bit_offset: 22 - bit_size: 2 - description: HDMI-CEC kernel clock source selection - enum: CECSEL - name: CECSEL - - bit_offset: 28 - bit_size: 3 - description: LPTIM1 kernel clock source selection - enum: LPTIM1SEL - name: LPTIM1SEL + - name: USART234578SEL + description: "USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection" + bit_offset: 0 + bit_size: 3 + enum: USART234578SEL + - name: USART16910SEL + description: USART1 and 6 kernel clock source selection + bit_offset: 3 + bit_size: 3 + enum: USART16910SEL + - name: RNGSEL + description: RNG kernel clock source selection + bit_offset: 8 + bit_size: 2 + enum: RNGSEL + - name: I2C1235SEL + description: "I2C1,2,3 kernel clock source selection" + bit_offset: 12 + bit_size: 2 + enum: I2C1235SEL + - name: USBSEL + description: USBOTG 1 and 2 kernel clock source selection + bit_offset: 20 + bit_size: 2 + enum: USBSEL + - name: CECSEL + description: HDMI-CEC kernel clock source selection + bit_offset: 22 + bit_size: 2 + enum: CECSEL + - name: LPTIM1SEL + description: LPTIM1 kernel clock source selection + bit_offset: 28 + bit_size: 3 + enum: LPTIM1SEL fieldset/D2CFGR: description: RCC Domain 2 Clock Configuration Register fields: - - bit_offset: 4 - bit_size: 3 - description: D2 domain APB1 prescaler - enum: DPPRE - name: D2PPRE1 - - bit_offset: 8 - bit_size: 3 - description: D2 domain APB2 prescaler - enum: DPPRE - name: D2PPRE2 + - name: D2PPRE1 + description: D2 domain APB1 prescaler + bit_offset: 4 + bit_size: 3 + enum: DPPRE + - name: D2PPRE2 + description: D2 domain APB2 prescaler + bit_offset: 8 + bit_size: 3 + enum: DPPRE fieldset/D3AMR: description: RCC D3 Autonomous mode Register fields: - - bit_offset: 0 - bit_size: 1 - description: BDMA and DMAMUX Autonomous mode enable - name: BDMAAMEN - - bit_offset: 3 - bit_size: 1 - description: LPUART1 Autonomous mode enable - name: LPUART1AMEN - - bit_offset: 5 - bit_size: 1 - description: SPI6 Autonomous mode enable - name: SPI6AMEN - - bit_offset: 7 - bit_size: 1 - description: I2C4 Autonomous mode enable - name: I2C4AMEN - - bit_offset: 9 - bit_size: 1 - description: LPTIM2 Autonomous mode enable - name: LPTIM2AMEN - - bit_offset: 10 - bit_size: 1 - description: LPTIM3 Autonomous mode enable - name: LPTIM3AMEN - - bit_offset: 11 - bit_size: 1 - description: LPTIM4 Autonomous mode enable - name: LPTIM4AMEN - - bit_offset: 12 - bit_size: 1 - description: LPTIM5 Autonomous mode enable - name: LPTIM5AMEN - - bit_offset: 14 - bit_size: 1 - description: COMP12 Autonomous mode enable - name: COMP12AMEN - - bit_offset: 15 - bit_size: 1 - description: VREF Autonomous mode enable - name: VREFAMEN - - bit_offset: 16 - bit_size: 1 - description: RTC Autonomous mode enable - name: RTCAMEN - - bit_offset: 19 - bit_size: 1 - description: CRC Autonomous mode enable - name: CRCAMEN - - bit_offset: 21 - bit_size: 1 - description: SAI4 Autonomous mode enable - name: SAI4AMEN - - bit_offset: 24 - bit_size: 1 - description: ADC3 Autonomous mode enable - name: ADC3AMEN - - bit_offset: 26 - bit_size: 1 - description: Digital temperature sensor Autonomous mode enable - name: DTSAMEN - - bit_offset: 28 - bit_size: 1 - description: Backup RAM Autonomous mode enable - name: BKPRAMAMEN - - bit_offset: 28 - bit_size: 1 - description: Backup RAM Autonomous mode enable - name: BKPSRAMAMEN - - bit_offset: 29 - bit_size: 1 - description: SRAM4 Autonomous mode enable - name: SRAM4AMEN + - name: BDMAAMEN + description: BDMA and DMAMUX Autonomous mode enable + bit_offset: 0 + bit_size: 1 + - name: LPUART1AMEN + description: LPUART1 Autonomous mode enable + bit_offset: 3 + bit_size: 1 + - name: SPI6AMEN + description: SPI6 Autonomous mode enable + bit_offset: 5 + bit_size: 1 + - name: I2C4AMEN + description: I2C4 Autonomous mode enable + bit_offset: 7 + bit_size: 1 + - name: LPTIM2AMEN + description: LPTIM2 Autonomous mode enable + bit_offset: 9 + bit_size: 1 + - name: LPTIM3AMEN + description: LPTIM3 Autonomous mode enable + bit_offset: 10 + bit_size: 1 + - name: LPTIM4AMEN + description: LPTIM4 Autonomous mode enable + bit_offset: 11 + bit_size: 1 + - name: LPTIM5AMEN + description: LPTIM5 Autonomous mode enable + bit_offset: 12 + bit_size: 1 + - name: COMP12AMEN + description: COMP12 Autonomous mode enable + bit_offset: 14 + bit_size: 1 + - name: VREFAMEN + description: VREF Autonomous mode enable + bit_offset: 15 + bit_size: 1 + - name: RTCAMEN + description: RTC Autonomous mode enable + bit_offset: 16 + bit_size: 1 + - name: CRCAMEN + description: CRC Autonomous mode enable + bit_offset: 19 + bit_size: 1 + - name: SAI4AMEN + description: SAI4 Autonomous mode enable + bit_offset: 21 + bit_size: 1 + - name: ADC3AMEN + description: ADC3 Autonomous mode enable + bit_offset: 24 + bit_size: 1 + - name: DTSAMEN + description: Digital temperature sensor Autonomous mode enable + bit_offset: 26 + bit_size: 1 + - name: BKPRAMAMEN + description: Backup RAM Autonomous mode enable + bit_offset: 28 + bit_size: 1 + - name: BKPSRAMAMEN + description: Backup RAM Autonomous mode enable + bit_offset: 28 + bit_size: 1 + - name: SRAM4AMEN + description: SRAM4 Autonomous mode enable + bit_offset: 29 + bit_size: 1 fieldset/D3CCIPR: description: RCC Domain 3 Kernel Clock Configuration Register fields: - - bit_offset: 0 - bit_size: 3 - description: LPUART1 kernel clock source selection - enum: LPUARTSEL - name: LPUART1SEL - - bit_offset: 8 - bit_size: 2 - description: I2C4 kernel clock source selection - enum: I2C4SEL - name: I2C4SEL - - bit_offset: 10 - bit_size: 3 - description: LPTIM2 kernel clock source selection - enum: LPTIM2SEL - name: LPTIM2SEL - - bit_offset: 13 - bit_size: 3 - description: LPTIM3,4,5 kernel clock source selection - enum: LPTIM2SEL - name: LPTIM345SEL - - bit_offset: 16 - bit_size: 2 - description: SAR ADC kernel clock source selection - enum: ADCSEL - name: ADCSEL - - bit_offset: 21 - bit_size: 3 - description: Sub-Block A of SAI4 kernel clock source selection - enum: SAIASEL - name: SAI4ASEL - - bit_offset: 24 - bit_size: 3 - description: Sub-Block B of SAI4 kernel clock source selection - enum: SAIASEL - name: SAI4BSEL - - bit_offset: 28 - bit_size: 3 - description: SPI6 kernel clock source selection - enum: SPI6SEL - name: SPI6SEL + - name: LPUART1SEL + description: LPUART1 kernel clock source selection + bit_offset: 0 + bit_size: 3 + enum: LPUARTSEL + - name: I2C4SEL + description: I2C4 kernel clock source selection + bit_offset: 8 + bit_size: 2 + enum: I2C4SEL + - name: LPTIM2SEL + description: LPTIM2 kernel clock source selection + bit_offset: 10 + bit_size: 3 + enum: LPTIM2SEL + - name: LPTIM345SEL + description: "LPTIM3,4,5 kernel clock source selection" + bit_offset: 13 + bit_size: 3 + enum: LPTIM2SEL + - name: ADCSEL + description: SAR ADC kernel clock source selection + bit_offset: 16 + bit_size: 2 + enum: ADCSEL + - name: SAI4ASEL + description: Sub-Block A of SAI4 kernel clock source selection + bit_offset: 21 + bit_size: 3 + enum: SAIASEL + - name: SAI4BSEL + description: Sub-Block B of SAI4 kernel clock source selection + bit_offset: 24 + bit_size: 3 + enum: SAIASEL + - name: SPI6SEL + description: SPI6 kernel clock source selection + bit_offset: 28 + bit_size: 3 + enum: SPI6SEL fieldset/D3CFGR: description: RCC Domain 3 Clock Configuration Register fields: - - bit_offset: 4 - bit_size: 3 - description: D3 domain APB4 prescaler - enum: DPPRE - name: D3PPRE + - name: D3PPRE + description: D3 domain APB4 prescaler + bit_offset: 4 + bit_size: 3 + enum: DPPRE fieldset/GCR: description: RCC Global Control Register fields: - - bit_offset: 0 - bit_size: 1 - description: WWDG1 reset scope control - enum: WWRSC - name: WW1RSC - - bit_offset: 1 - bit_size: 1 - description: WWDG2 reset scope control - name: WW2RSC - - bit_offset: 2 - bit_size: 1 - description: Force allow CPU1 to boot - name: BOOT_C1 - - bit_offset: 3 - bit_size: 1 - description: Force allow CPU2 to boot - name: BOOT_C2 + - name: WW1RSC + description: WWDG1 reset scope control + bit_offset: 0 + bit_size: 1 + enum: WWRSC + - name: WW2RSC + description: WWDG2 reset scope control + bit_offset: 1 + bit_size: 1 + - name: BOOT_C1 + description: Force allow CPU1 to boot + bit_offset: 2 + bit_size: 1 + - name: BOOT_C2 + description: Force allow CPU2 to boot + bit_offset: 3 + bit_size: 1 fieldset/HSICFGR: description: RCC HSI configuration register fields: - - bit_offset: 0 - bit_size: 12 - description: HSI clock calibration - name: HSICAL - - bit_offset: 24 - bit_size: 7 - description: HSI clock trimming - name: HSITRIM + - name: HSICAL + description: HSI clock calibration + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: HSI clock trimming + bit_offset: 24 + bit_size: 7 fieldset/ICSCR: description: RCC Internal Clock Source Calibration Register fields: - - bit_offset: 0 - bit_size: 12 - description: HSI clock calibration - name: HSICAL - - bit_offset: 12 - bit_size: 6 - description: HSI clock trimming - name: HSITRIM - - bit_offset: 18 - bit_size: 8 - description: CSI clock calibration - name: CSICAL - - bit_offset: 26 - bit_size: 5 - description: CSI clock trimming - name: CSITRIM + - name: HSICAL + description: HSI clock calibration + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: HSI clock trimming + bit_offset: 12 + bit_size: 6 + - name: CSICAL + description: CSI clock calibration + bit_offset: 18 + bit_size: 8 + - name: CSITRIM + description: CSI clock trimming + bit_offset: 26 + bit_size: 5 fieldset/PLL1DIVR: description: RCC PLL1 Dividers Configuration Register fields: - - bit_offset: 0 - bit_size: 9 - description: Multiplication factor for PLL1 VCO - name: DIVN1 - - bit_offset: 9 - bit_size: 7 - description: PLL1 DIVP division factor - enum: DIVP - name: DIVP1 - - bit_offset: 16 - bit_size: 7 - description: PLL1 DIVQ division factor - name: DIVQ1 - - bit_offset: 24 - bit_size: 7 - description: PLL1 DIVR division factor - name: DIVR1 + - name: DIVN1 + description: Multiplication factor for PLL1 VCO + bit_offset: 0 + bit_size: 9 + - name: DIVP1 + description: PLL1 DIVP division factor + bit_offset: 9 + bit_size: 7 + enum: DIVP + - name: DIVQ1 + description: PLL1 DIVQ division factor + bit_offset: 16 + bit_size: 7 + - name: DIVR1 + description: PLL1 DIVR division factor + bit_offset: 24 + bit_size: 7 fieldset/PLL1FRACR: description: RCC PLL1 Fractional Divider Register fields: - - bit_offset: 3 - bit_size: 13 - description: Fractional part of the multiplication factor for PLL1 VCO - name: FRACN1 + - name: FRACN1 + description: Fractional part of the multiplication factor for PLL1 VCO + bit_offset: 3 + bit_size: 13 fieldset/PLL2DIVR: description: RCC PLL2 Dividers Configuration Register fields: - - bit_offset: 0 - bit_size: 9 - description: Multiplication factor for PLL1 VCO - name: DIVN2 - - bit_offset: 9 - bit_size: 7 - description: PLL1 DIVP division factor - name: DIVP2 - - bit_offset: 16 - bit_size: 7 - description: PLL1 DIVQ division factor - name: DIVQ2 - - bit_offset: 24 - bit_size: 7 - description: PLL1 DIVR division factor - name: DIVR2 + - name: DIVN2 + description: Multiplication factor for PLL1 VCO + bit_offset: 0 + bit_size: 9 + - name: DIVP2 + description: PLL1 DIVP division factor + bit_offset: 9 + bit_size: 7 + - name: DIVQ2 + description: PLL1 DIVQ division factor + bit_offset: 16 + bit_size: 7 + - name: DIVR2 + description: PLL1 DIVR division factor + bit_offset: 24 + bit_size: 7 fieldset/PLL2FRACR: description: RCC PLL2 Fractional Divider Register fields: - - bit_offset: 3 - bit_size: 13 - description: Fractional part of the multiplication factor for PLL VCO - name: FRACN2 + - name: FRACN2 + description: Fractional part of the multiplication factor for PLL VCO + bit_offset: 3 + bit_size: 13 fieldset/PLL3DIVR: description: RCC PLL3 Dividers Configuration Register fields: - - bit_offset: 0 - bit_size: 9 - description: Multiplication factor for PLL1 VCO - name: DIVN3 - - bit_offset: 9 - bit_size: 7 - description: PLL DIVP division factor - name: DIVP3 - - bit_offset: 16 - bit_size: 7 - description: PLL DIVQ division factor - name: DIVQ3 - - bit_offset: 24 - bit_size: 7 - description: PLL DIVR division factor - name: DIVR3 + - name: DIVN3 + description: Multiplication factor for PLL1 VCO + bit_offset: 0 + bit_size: 9 + - name: DIVP3 + description: PLL DIVP division factor + bit_offset: 9 + bit_size: 7 + - name: DIVQ3 + description: PLL DIVQ division factor + bit_offset: 16 + bit_size: 7 + - name: DIVR3 + description: PLL DIVR division factor + bit_offset: 24 + bit_size: 7 fieldset/PLL3FRACR: description: RCC PLL3 Fractional Divider Register fields: - - bit_offset: 3 - bit_size: 13 - description: Fractional part of the multiplication factor for PLL3 VCO - name: FRACN3 + - name: FRACN3 + description: Fractional part of the multiplication factor for PLL3 VCO + bit_offset: 3 + bit_size: 13 fieldset/PLLCFGR: description: RCC PLLs Configuration Register fields: - - array: - len: 3 - stride: 4 - bit_offset: 0 - bit_size: 1 - description: PLL1 fractional latch enable - name: PLLFRACEN - - array: - len: 3 - stride: 4 - bit_offset: 1 - bit_size: 1 - description: PLL1 VCO selection - enum: PLLVCOSEL - name: PLLVCOSEL - - array: - len: 3 - stride: 4 - bit_offset: 2 - bit_size: 2 - description: PLL1 input frequency range - enum: PLLRGE - name: PLLRGE - - array: - len: 3 - stride: 3 - bit_offset: 16 - bit_size: 1 - description: PLL1 DIVP divider output enable - name: DIVPEN - - array: - len: 3 - stride: 3 - bit_offset: 17 - bit_size: 1 - description: PLL1 DIVQ divider output enable - name: DIVQEN - - array: - len: 3 - stride: 3 - bit_offset: 18 - bit_size: 1 - description: PLL1 DIVR divider output enable - name: DIVREN + - name: PLLFRACEN + description: PLL1 fractional latch enable + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 4 + - name: PLLVCOSEL + description: PLL1 VCO selection + bit_offset: 1 + bit_size: 1 + array: + len: 3 + stride: 4 + enum: PLLVCOSEL + - name: PLLRGE + description: PLL1 input frequency range + bit_offset: 2 + bit_size: 2 + array: + len: 3 + stride: 4 + enum: PLLRGE + - name: DIVPEN + description: PLL1 DIVP divider output enable + bit_offset: 16 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: DIVQEN + description: PLL1 DIVQ divider output enable + bit_offset: 17 + bit_size: 1 + array: + len: 3 + stride: 3 + - name: DIVREN + description: PLL1 DIVR divider output enable + bit_offset: 18 + bit_size: 1 + array: + len: 3 + stride: 3 fieldset/PLLCKSELR: description: RCC PLLs Clock Source Selection Register fields: - - bit_offset: 0 - bit_size: 2 - description: DIVMx and PLLs clock source selection - enum: PLLSRC - name: PLLSRC - - array: - len: 3 - stride: 8 - bit_offset: 4 - bit_size: 6 - description: Prescaler for PLL1 - name: DIVM + - name: PLLSRC + description: DIVMx and PLLs clock source selection + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: DIVM + description: Prescaler for PLL1 + bit_offset: 4 + bit_size: 6 + array: + len: 3 + stride: 8 fieldset/RSR: description: RCC Reset Status Register fields: - - bit_offset: 16 - bit_size: 1 - description: Remove reset flag - enum: RSR_RMVF - name: RMVF - - bit_offset: 17 - bit_size: 1 - description: CPU reset flag - enum_read: RSR_CPURSTFR - name: CPURSTF - - bit_offset: 19 - bit_size: 1 - description: D1 domain power switch reset flag - enum_read: RSR_CPURSTFR - name: D1RSTF - - bit_offset: 20 - bit_size: 1 - description: D2 domain power switch reset flag - enum_read: RSR_CPURSTFR - name: D2RSTF - - bit_offset: 21 - bit_size: 1 - description: BOR reset flag - enum_read: RSR_CPURSTFR - name: BORRSTF - - bit_offset: 22 - bit_size: 1 - description: Pin reset flag (NRST) - enum_read: RSR_CPURSTFR - name: PINRSTF - - bit_offset: 23 - bit_size: 1 - description: POR/PDR reset flag - enum_read: RSR_CPURSTFR - name: PORRSTF - - bit_offset: 24 - bit_size: 1 - description: System reset from CPU reset flag - enum_read: RSR_CPURSTFR - name: SFTRSTF - - bit_offset: 26 - bit_size: 1 - description: Independent Watchdog reset flag - enum_read: RSR_CPURSTFR - name: IWDG1RSTF - - bit_offset: 28 - bit_size: 1 - description: Window Watchdog reset flag - enum_read: RSR_CPURSTFR - name: WWDG1RSTF - - bit_offset: 30 - bit_size: 1 - description: Reset due to illegal D1 DStandby or CPU CStop flag - enum_read: RSR_CPURSTFR - name: LPWRRSTF + - name: RMVF + description: Remove reset flag + bit_offset: 16 + bit_size: 1 + enum: RSR_RMVF + - name: CPURSTF + description: CPU reset flag + bit_offset: 17 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: D1RSTF + description: D1 domain power switch reset flag + bit_offset: 19 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: D2RSTF + description: D2 domain power switch reset flag + bit_offset: 20 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: BORRSTF + description: BOR reset flag + bit_offset: 21 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: PINRSTF + description: Pin reset flag (NRST) + bit_offset: 22 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 23 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: SFTRSTF + description: System reset from CPU reset flag + bit_offset: 24 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: IWDG1RSTF + description: Independent Watchdog reset flag + bit_offset: 26 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: WWDG1RSTF + description: Window Watchdog reset flag + bit_offset: 28 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: LPWRRSTF + description: Reset due to illegal D1 DStandby or CPU CStop flag + bit_offset: 30 + bit_size: 1 + enum_read: RSR_CPURSTFR +enum/ADCSEL: + bit_size: 2 + variants: + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: PER + description: PER selected as peripheral clock + value: 2 +enum/CECSEL: + bit_size: 2 + variants: + - name: LSE + description: LSE selected as peripheral clock + value: 0 + - name: LSI + description: LSI selected as peripheral clock + value: 1 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 2 +enum/CKPERSEL: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as peripheral clock + value: 0 + - name: CSI + description: CSI selected as peripheral clock + value: 1 + - name: HSE + description: HSE selected as peripheral clock + value: 2 +enum/C_RSR_CPURSTFR: + bit_size: 1 + variants: + - name: NoResetOccoured + description: No reset occoured for block + value: 0 + - name: ResetOccourred + description: Reset occoured for block + value: 1 +enum/C_RSR_RMVF: + bit_size: 1 + variants: + - name: NotActive + description: Not clearing the the reset flags + value: 0 + - name: Clear + description: Clear the reset flags + value: 1 +enum/DFSDMSEL: + bit_size: 1 + variants: + - name: RCC_PCLK2 + description: rcc_pclk2 selected as peripheral clock + value: 0 + - name: SYS + description: System clock selected as peripheral clock + value: 1 +enum/DIVP: + bit_size: 7 + variants: + - name: Div1 + description: pll_p_ck = vco_ck + value: 0 + - name: Div2 + description: pll_p_ck = vco_ck / 2 + value: 1 + - name: Div4 + description: pll_p_ck = vco_ck / 4 + value: 3 + - name: Div6 + description: pll_p_ck = vco_ck / 6 + value: 5 + - name: Div8 + description: pll_p_ck = vco_ck / 8 + value: 7 + - name: Div10 + description: pll_p_ck = vco_ck / 10 + value: 9 + - name: Div12 + description: pll_p_ck = vco_ck / 12 + value: 11 + - name: Div14 + description: pll_p_ck = vco_ck / 14 + value: 13 + - name: Div16 + description: pll_p_ck = vco_ck / 16 + value: 15 + - name: Div18 + description: pll_p_ck = vco_ck / 18 + value: 17 + - name: Div20 + description: pll_p_ck = vco_ck / 20 + value: 19 + - name: Div22 + description: pll_p_ck = vco_ck / 22 + value: 21 + - name: Div24 + description: pll_p_ck = vco_ck / 24 + value: 23 + - name: Div26 + description: pll_p_ck = vco_ck / 26 + value: 25 + - name: Div28 + description: pll_p_ck = vco_ck / 28 + value: 27 + - name: Div30 + description: pll_p_ck = vco_ck / 30 + value: 29 + - name: Div32 + description: pll_p_ck = vco_ck / 32 + value: 31 + - name: Div34 + description: pll_p_ck = vco_ck / 34 + value: 33 + - name: Div36 + description: pll_p_ck = vco_ck / 36 + value: 35 + - name: Div38 + description: pll_p_ck = vco_ck / 38 + value: 37 + - name: Div40 + description: pll_p_ck = vco_ck / 40 + value: 39 + - name: Div42 + description: pll_p_ck = vco_ck / 42 + value: 41 + - name: Div44 + description: pll_p_ck = vco_ck / 44 + value: 43 + - name: Div46 + description: pll_p_ck = vco_ck / 46 + value: 45 + - name: Div48 + description: pll_p_ck = vco_ck / 48 + value: 47 + - name: Div50 + description: pll_p_ck = vco_ck / 50 + value: 49 + - name: Div52 + description: pll_p_ck = vco_ck / 52 + value: 51 + - name: Div54 + description: pll_p_ck = vco_ck / 54 + value: 53 + - name: Div56 + description: pll_p_ck = vco_ck / 56 + value: 55 + - name: Div58 + description: pll_p_ck = vco_ck / 58 + value: 57 + - name: Div60 + description: pll_p_ck = vco_ck / 60 + value: 59 + - name: Div62 + description: pll_p_ck = vco_ck / 62 + value: 61 + - name: Div64 + description: pll_p_ck = vco_ck / 64 + value: 63 + - name: Div66 + description: pll_p_ck = vco_ck / 66 + value: 65 + - name: Div68 + description: pll_p_ck = vco_ck / 68 + value: 67 + - name: Div70 + description: pll_p_ck = vco_ck / 70 + value: 69 + - name: Div72 + description: pll_p_ck = vco_ck / 72 + value: 71 + - name: Div74 + description: pll_p_ck = vco_ck / 74 + value: 73 + - name: Div76 + description: pll_p_ck = vco_ck / 76 + value: 75 + - name: Div78 + description: pll_p_ck = vco_ck / 78 + value: 77 + - name: Div80 + description: pll_p_ck = vco_ck / 80 + value: 79 + - name: Div82 + description: pll_p_ck = vco_ck / 82 + value: 81 + - name: Div84 + description: pll_p_ck = vco_ck / 84 + value: 83 + - name: Div86 + description: pll_p_ck = vco_ck / 86 + value: 85 + - name: Div88 + description: pll_p_ck = vco_ck / 88 + value: 87 + - name: Div90 + description: pll_p_ck = vco_ck / 90 + value: 89 + - name: Div92 + description: pll_p_ck = vco_ck / 92 + value: 91 + - name: Div94 + description: pll_p_ck = vco_ck / 94 + value: 93 + - name: Div96 + description: pll_p_ck = vco_ck / 96 + value: 95 + - name: Div98 + description: pll_p_ck = vco_ck / 98 + value: 97 + - name: Div100 + description: pll_p_ck = vco_ck / 100 + value: 99 + - name: Div102 + description: pll_p_ck = vco_ck / 102 + value: 101 + - name: Div104 + description: pll_p_ck = vco_ck / 104 + value: 103 + - name: Div106 + description: pll_p_ck = vco_ck / 106 + value: 105 + - name: Div108 + description: pll_p_ck = vco_ck / 108 + value: 107 + - name: Div110 + description: pll_p_ck = vco_ck / 110 + value: 109 + - name: Div112 + description: pll_p_ck = vco_ck / 112 + value: 111 + - name: Div114 + description: pll_p_ck = vco_ck / 114 + value: 113 + - name: Div116 + description: pll_p_ck = vco_ck / 116 + value: 115 + - name: Div118 + description: pll_p_ck = vco_ck / 118 + value: 117 + - name: Div120 + description: pll_p_ck = vco_ck / 120 + value: 119 + - name: Div122 + description: pll_p_ck = vco_ck / 122 + value: 121 + - name: Div124 + description: pll_p_ck = vco_ck / 124 + value: 123 + - name: Div126 + description: pll_p_ck = vco_ck / 126 + value: 125 + - name: Div128 + description: pll_p_ck = vco_ck / 128 + value: 127 +enum/DPPRE: + bit_size: 3 + variants: + - name: Div1 + description: rcc_hclk not divided + value: 0 + - name: Div2 + description: rcc_hclk divided by 2 + value: 4 + - name: Div4 + description: rcc_hclk divided by 4 + value: 5 + - name: Div8 + description: rcc_hclk divided by 8 + value: 6 + - name: Div16 + description: rcc_hclk divided by 16 + value: 7 +enum/FDCANSEL: + bit_size: 2 + variants: + - name: HSE + description: HSE selected as peripheral clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 2 +enum/FMCSEL: + bit_size: 2 + variants: + - name: RCC_HCLK3 + description: rcc_hclk3 selected as peripheral clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL2_R + description: pll2_r selected as peripheral clock + value: 2 + - name: PER + description: PER selected as peripheral clock + value: 3 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: sys_ck not divided + value: 0 + - name: Div2 + description: sys_ck divided by 2 + value: 8 + - name: Div4 + description: sys_ck divided by 4 + value: 9 + - name: Div8 + description: sys_ck divided by 8 + value: 10 + - name: Div16 + description: sys_ck divided by 16 + value: 11 + - name: Div64 + description: sys_ck divided by 64 + value: 12 + - name: Div128 + description: sys_ck divided by 128 + value: 13 + - name: Div256 + description: sys_ck divided by 256 + value: 14 + - name: Div512 + description: sys_ck divided by 512 + value: 15 +enum/HRTIMSEL: + bit_size: 1 + variants: + - name: TIMY_KER + description: The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) + value: 0 + - name: C_CK + description: The HRTIM prescaler clock source is the CPU clock (c_ck) + value: 1 +enum/HSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: HSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: HSE crystal oscillator bypassed with external clock + value: 1 +enum/HSIDIV: + bit_size: 2 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 +enum/HSIDIVFR: + bit_size: 1 + variants: + - name: NotPropagated + description: New HSIDIV ratio has not yet propagated to hsi_ck + value: 0 + - name: Propagated + description: HSIDIV ratio has propagated to hsi_ck + value: 1 +enum/HSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: Clock not ready + value: 0 + - name: Ready + description: Clock ready + value: 1 +enum/I2C1235SEL: + bit_size: 2 + variants: + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 3 +enum/I2C4SEL: + bit_size: 2 + variants: + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 3 +enum/LPTIM1SEL: + bit_size: 3 + variants: + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 +enum/LPTIM2SEL: + bit_size: 3 + variants: + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 +enum/LPUARTSEL: + bit_size: 3 + variants: + - name: RCC_PCLK_D3 + description: rcc_pclk_d3 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 +enum/LSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: LSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: LSE crystal oscillator bypassed with external clock + value: 1 +enum/LSECSSDR: + bit_size: 1 + variants: + - name: NoFailure + description: No failure detected on 32 kHz oscillator + value: 0 + - name: Failure + description: Failure detected on 32 kHz oscillator + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Lowest + description: Lowest LSE oscillator driving capability + value: 0 + - name: MediumLow + description: Medium low LSE oscillator driving capability + value: 1 + - name: MediumHigh + description: Medium high LSE oscillator driving capability + value: 2 + - name: Highest + description: Highest LSE oscillator driving capability + value: 3 +enum/LSERDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSE oscillator not ready + value: 0 + - name: Ready + description: LSE oscillator ready + value: 1 +enum/LSIRDYC: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag + value: 1 +enum/LSIRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt disabled + value: 0 + - name: Enabled + description: Interrupt enabled + value: 1 +enum/LSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSI oscillator not ready + value: 0 + - name: Ready + description: LSI oscillator ready + value: 1 +enum/MCO1: + bit_size: 3 + variants: + - name: HSI + description: HSI selected for micro-controller clock output + value: 0 + - name: LSE + description: LSE selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_Q + description: pll1_q selected for micro-controller clock output + value: 3 + - name: HSI48 + description: HSI48 selected for micro-controller clock output + value: 4 +enum/MCO2: + bit_size: 3 + variants: + - name: SYSCLK + description: System clock selected for micro-controller clock output + value: 0 + - name: PLL2_P + description: pll2_p selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_P + description: pll1_p selected for micro-controller clock output + value: 3 + - name: CSI + description: CSI selected for micro-controller clock output + value: 4 + - name: LSI + description: LSI selected for micro-controller clock output + value: 5 +enum/PLLRGE: + bit_size: 2 + variants: + - name: Range1 + description: Frequency is between 1 and 2 MHz + value: 0 + - name: Range2 + description: Frequency is between 2 and 4 MHz + value: 1 + - name: Range4 + description: Frequency is between 4 and 8 MHz + value: 2 + - name: Range8 + description: Frequency is between 8 and 16 MHz + value: 3 +enum/PLLSRC: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as PLL clock + value: 0 + - name: CSI + description: CSI selected as PLL clock + value: 1 + - name: HSE + description: HSE selected as PLL clock + value: 2 + - name: None + description: No clock sent to DIVMx dividers and PLLs + value: 3 +enum/PLLVCOSEL: + bit_size: 1 + variants: + - name: WideVCO + description: VCO frequency range 192 to 836 MHz + value: 0 + - name: MediumVCO + description: VCO frequency range 150 to 420 MHz + value: 1 +enum/RNGSEL: + bit_size: 2 + variants: + - name: HSI48 + description: HSI48 selected as peripheral clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: LSE + description: LSE selected as peripheral clock + value: 2 + - name: LSI + description: LSI selected as peripheral clock + value: 3 +enum/RSR_CPURSTFR: + bit_size: 1 + variants: + - name: NoResetOccoured + description: No reset occoured for block + value: 0 + - name: ResetOccourred + description: Reset occoured for block + value: 1 +enum/RSR_RMVF: + bit_size: 1 + variants: + - name: NotActive + description: Not clearing the the reset flags + value: 0 + - name: Clear + description: Clear the reset flags + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SAIASEL: + bit_size: 3 + variants: + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_P + description: pll3_p selected as peripheral clock + value: 2 + - name: I2S_CKIN + description: i2s_ckin selected as peripheral clock + value: 3 + - name: PER + description: PER selected as peripheral clock + value: 4 +enum/SAISEL: + bit_size: 3 + variants: + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_P + description: pll3_p selected as peripheral clock + value: 2 + - name: I2S_CKIN + description: I2S_CKIN selected as peripheral clock + value: 3 + - name: PER + description: PER selected as peripheral clock + value: 4 +enum/SDMMCSEL: + bit_size: 1 + variants: + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_R + description: pll2_r selected as peripheral clock + value: 1 +enum/SPDIFSEL: + bit_size: 2 + variants: + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_R + description: pll2_r selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 +enum/SPI45SEL: + bit_size: 3 + variants: + - name: APB + description: APB clock selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 +enum/SPI6SEL: + bit_size: 3 + variants: + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 +enum/STOPWUCK: + bit_size: 1 + variants: + - name: HSI + description: HSI selected as wake up clock from system Stop + value: 0 + - name: CSI + description: CSI selected as wake up clock from system Stop + value: 1 +enum/SW: + bit_size: 3 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: CSI + description: CSI selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL1 + description: PLL1 selected as system clock + value: 3 +enum/SWPSEL: + bit_size: 1 + variants: + - name: PCLK + description: pclk selected as peripheral clock + value: 0 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 1 +enum/SWSR: + bit_size: 3 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: CSI + description: CSI oscillator used as system clock + value: 1 + - name: HSE + description: HSE oscillator used as system clock + value: 2 + - name: PLL1 + description: PLL1 used as system clock + value: 3 +enum/TIMPRE: + bit_size: 1 + variants: + - name: DefaultX2 + description: Timer kernel clock equal to 2x pclk by default + value: 0 + - name: DefaultX4 + description: Timer kernel clock equal to 4x pclk by default + value: 1 +enum/USART16910SEL: + bit_size: 3 + variants: + - name: RCC_PCLK2 + description: rcc_pclk2 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 +enum/USART234578SEL: + bit_size: 3 + variants: + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 +enum/USBSEL: + bit_size: 2 + variants: + - name: DISABLE + description: Disable the kernel clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI48 + description: HSI48 selected as peripheral clock + value: 3 +enum/WWRSC: + bit_size: 1 + variants: + - name: Clear + description: Clear WWDG1 scope control + value: 0 + - name: Set + description: Set WWDG1 scope control + value: 1 diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index 2ddf8cc..0faa3cc 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -1,1563 +1,1560 @@ +--- block/RCC: description: Reset and clock control items: - - byte_offset: 0 - description: Clock control register - fieldset: CR - name: CR - - byte_offset: 4 - description: Internal clock sources calibration register - fieldset: ICSCR - name: ICSCR - - byte_offset: 12 - description: Clock configuration register - fieldset: CFGR - name: CFGR - - access: Read - byte_offset: 16 - description: Clock interrupt enable register - fieldset: CIER - name: CIER - - access: Read - byte_offset: 20 - description: Clock interrupt flag register - fieldset: CIFR - name: CIFR - - access: Read - byte_offset: 24 - description: Clock interrupt clear register - fieldset: CICR - name: CICR - - byte_offset: 28 - description: GPIO reset register - fieldset: IOPRSTR - name: IOPRSTR - - byte_offset: 32 - description: AHB peripheral reset register - fieldset: AHBRSTR - name: AHBRSTR - - byte_offset: 36 - description: APB2 peripheral reset register - fieldset: APB2RSTR - name: APB2RSTR - - byte_offset: 40 - description: APB1 peripheral reset register - fieldset: APB1RSTR - name: APB1RSTR - - byte_offset: 44 - description: GPIO clock enable register - fieldset: IOPENR - name: IOPENR - - byte_offset: 48 - description: AHB peripheral clock enable register - fieldset: AHBENR - name: AHBENR - - byte_offset: 52 - description: APB2 peripheral clock enable register - fieldset: APB2ENR - name: APB2ENR - - byte_offset: 56 - description: APB1 peripheral clock enable register - fieldset: APB1ENR - name: APB1ENR - - byte_offset: 60 - description: GPIO clock enable in sleep mode register - fieldset: IOPSMEN - name: IOPSMEN - - byte_offset: 64 - description: AHB peripheral clock enable in sleep mode register - fieldset: AHBSMENR - name: AHBSMENR - - byte_offset: 68 - description: APB2 peripheral clock enable in sleep mode register - fieldset: APB2SMENR - name: APB2SMENR - - byte_offset: 72 - description: APB1 peripheral clock enable in sleep mode register - fieldset: APB1SMENR - name: APB1SMENR - - byte_offset: 76 - description: Clock configuration register - fieldset: CCIPR - name: CCIPR - - byte_offset: 80 - description: Control and status register - fieldset: CSR - name: CSR - - byte_offset: 8 - description: Clock recovery RC register - fieldset: CRRCR - name: CRRCR -enum/CRYPRSTW: - bit_size: 1 - variants: - - description: Reset the module - name: Reset - value: 1 -enum/CSSHSECW: - bit_size: 1 - variants: - - description: Clear interrupt flag - name: Clear - value: 1 -enum/CSSHSEF: - bit_size: 1 - variants: - - description: No clock security interrupt caused by HSE clock failure - name: NoClock - value: 0 - - description: Clock security interrupt caused by HSE clock failure - name: Clock - value: 1 -enum/CSSLSE: - bit_size: 1 - variants: - - description: LSE CSS interrupt disabled - name: Disabled - value: 0 - - description: LSE CSS interrupt enabled - name: Enabled - value: 1 -enum/CSSLSED: - bit_size: 1 - variants: - - description: No failure detected on LSE (32 kHz oscillator) - name: NoFailure - value: 0 - - description: Failure detected on LSE (32 kHz oscillator) - name: Failure - value: 1 -enum/CSSLSEF: - bit_size: 1 - variants: - - description: No failure detected on LSE clock failure - name: NoFailure - value: 0 - - description: Failure detected on LSE clock failure - name: Failure - value: 1 -enum/DBGRSTW: - bit_size: 1 - variants: - - description: Reset the module - name: Reset - value: 1 -enum/HPRE: - bit_size: 4 - variants: - - description: system clock not divided - name: Div1 - value: 0 - - description: system clock divided by 2 - name: Div2 - value: 8 - - description: system clock divided by 4 - name: Div4 - value: 9 - - description: system clock divided by 8 - name: Div8 - value: 10 - - description: system clock divided by 16 - name: Div16 - value: 11 - - description: system clock divided by 64 - name: Div64 - value: 12 - - description: system clock divided by 128 - name: Div128 - value: 13 - - description: system clock divided by 256 - name: Div256 - value: 14 - - description: system clock divided by 512 - name: Div512 - value: 15 -enum/HSEBYP: - bit_size: 1 - variants: - - description: HSE oscillator not bypassed - name: NotBypassed - value: 0 - - description: HSE oscillator bypassed - name: Bypassed - value: 1 -enum/HSERDYR: - bit_size: 1 - variants: - - description: Oscillator is not stable - name: NotReady - value: 0 - - description: Oscillator is stable - name: Ready - value: 1 -enum/HSI16RDYFR: - bit_size: 1 - variants: - - description: HSI 16 MHz oscillator not ready - name: NotReady - value: 0 - - description: HSI 16 MHz oscillator ready - name: Ready - value: 1 -enum/HSI48RDYFR: - bit_size: 1 - variants: - - description: No clock ready interrupt - name: NotInterrupted - value: 0 - - description: Clock ready interrupt - name: Interrupted - value: 1 -enum/HSIDIVFR: - bit_size: 1 - variants: - - description: 16 MHz HSI clock not divided - name: NotDivided - value: 0 - - description: 16 MHz HSI clock divided by 4 - name: Div4 - value: 1 -enum/HSIRDYFR: - bit_size: 1 - variants: - - description: HSI 16 MHz oscillator not ready - name: NotReady - value: 0 - - description: HSI 16 MHz oscillator ready - name: Ready - value: 1 -enum/HSIRDYIE: - bit_size: 1 - variants: - - description: Ready interrupt disabled - name: Disabled - value: 0 - - description: Ready interrupt enabled - name: Enabled - value: 1 -enum/ICSEL: - bit_size: 2 - variants: - - description: APB clock selected as peripheral clock - name: APB - value: 0 - - description: System clock selected as peripheral clock - name: SYSTEM - value: 1 - - description: HSI16 clock selected as peripheral clock - name: HSI16 - value: 2 -enum/LPTIMRSTW: - bit_size: 1 - variants: - - description: Reset the module - name: Reset - value: 1 -enum/LPTIMSEL: - bit_size: 2 - variants: - - description: APB clock selected as Timer clock - name: APB - value: 0 - - description: LSI clock selected as Timer clock - name: LSI - value: 1 - - description: HSI16 clock selected as Timer clock - name: HSI16 - value: 2 - - description: LSE clock selected as Timer clock - name: LSE - value: 3 -enum/LPUARTSEL: - bit_size: 2 - variants: - - description: APB clock selected as peripheral clock - name: APB - value: 0 - - description: System clock selected as peripheral clock - name: SYSTEM - value: 1 - - description: HSI16 clock selected as peripheral clock - name: HSI16 - value: 2 - - description: LSE clock selected as peripheral clock - name: LSE - value: 3 -enum/LPWRRSTFR: - bit_size: 1 - variants: - - description: No reset has occured - name: NoReset - value: 0 - - description: A reset has occured - name: Reset - value: 1 -enum/LPWRSTFR: - bit_size: 1 - variants: - - description: No reset has occured - name: NoReset - value: 0 - - description: A reset has occured - name: Reset - value: 1 -enum/LSEBYP: - bit_size: 1 - variants: - - description: LSE oscillator not bypassed - name: NotBypassed - value: 0 - - description: LSE oscillator bypassed - name: Bypassed - value: 1 -enum/LSEDRV: - bit_size: 2 - variants: - - description: Lowest drive - name: Low - value: 0 - - description: Medium low drive - name: MediumLow - value: 1 - - description: Medium high drive - name: MediumHigh - value: 2 - - description: Highest drive - name: High - value: 3 -enum/LSERDY: - bit_size: 1 - variants: - - description: Oscillator not ready - name: NotReady - value: 0 - - description: Oscillator ready - name: Ready - value: 1 -enum/MCOPRE: - bit_size: 3 - variants: - - description: No division - name: Div1 - value: 0 - - description: Division by 2 - name: Div2 - value: 1 - - description: Division by 4 - name: Div4 - value: 2 - - description: Division by 8 - name: Div8 - value: 3 - - description: Division by 16 - name: Div16 - value: 4 -enum/MCOSEL: - bit_size: 4 - variants: - - description: No clock - name: NoClock - value: 0 - - description: SYSCLK clock selected - name: SYSCLK - value: 1 - - description: HSI oscillator clock selected - name: HSI16 - value: 2 - - description: MSI oscillator clock selected - name: MSI - value: 3 - - description: HSE oscillator clock selected - name: HSE - value: 4 - - description: PLL clock selected - name: PLL - value: 5 - - description: LSI oscillator clock selected - name: LSI - value: 6 - - description: LSE oscillator clock selected - name: LSE - value: 7 -enum/MSIRANGE: - bit_size: 3 - variants: - - description: range 0 around 65.536 kHz - name: Range0 - value: 0 - - description: range 1 around 131.072 kHz - name: Range1 - value: 1 - - description: range 2 around 262.144 kHz - name: Range2 - value: 2 - - description: range 3 around 524.288 kHz - name: Range3 - value: 3 - - description: range 4 around 1.048 MHz - name: Range4 - value: 4 - - description: range 5 around 2.097 MHz (reset value) - name: Range5 - value: 5 - - description: range 6 around 4.194 MHz - name: Range6 - value: 6 - - description: not allowed - name: Range7 - value: 7 -enum/MSIRDYFR: - bit_size: 1 - variants: - - description: No clock ready interrupt - name: NotInterrupted - value: 0 - - description: Clock ready interrupt - name: Interrupted - value: 1 -enum/MSIRDYIE: - bit_size: 1 - variants: - - description: Ready interrupt disabled - name: Disabled - value: 0 - - description: Ready interrupt enabled - name: Enabled - value: 1 -enum/PLLDIV: - bit_size: 2 - variants: - - description: PLLVCO / 2 - name: Div2 - value: 1 - - description: PLLVCO / 3 - name: Div3 - value: 2 - - description: PLLVCO / 4 - name: Div4 - value: 3 -enum/PLLMUL: - bit_size: 4 - variants: - - description: PLL clock entry x 3 - name: Mul3 - value: 0 - - description: PLL clock entry x 4 - name: Mul4 - value: 1 - - description: PLL clock entry x 6 - name: Mul6 - value: 2 - - description: PLL clock entry x 8 - name: Mul8 - value: 3 - - description: PLL clock entry x 12 - name: Mul12 - value: 4 - - description: PLL clock entry x 16 - name: Mul16 - value: 5 - - description: PLL clock entry x 24 - name: Mul24 - value: 6 - - description: PLL clock entry x 32 - name: Mul32 - value: 7 - - description: PLL clock entry x 48 - name: Mul48 - value: 8 -enum/PLLRDYR: - bit_size: 1 - variants: - - description: PLL unlocked - name: Unlocked - value: 0 - - description: PLL locked - name: Locked - value: 1 -enum/PLLSRC: - bit_size: 1 - variants: - - description: HSI selected as PLL input clock - name: HSI16 - value: 0 - - description: HSE selected as PLL input clock - name: HSE - value: 1 -enum/PPRE: - bit_size: 3 - variants: - - description: HCLK not divided - name: Div1 - value: 0 - - description: HCLK divided by 2 - name: Div2 - value: 4 - - description: HCLK divided by 4 - name: Div4 - value: 5 - - description: HCLK divided by 8 - name: Div8 - value: 6 - - description: HCLK divided by 16 - name: Div16 - value: 7 -enum/RMVFW: - bit_size: 1 - variants: - - description: Clears the reset flag - name: Clear - value: 1 -enum/RTCPRE: - bit_size: 2 - variants: - - description: HSE divided by 2 - name: Div2 - value: 0 - - description: HSE divided by 4 - name: Div4 - value: 1 - - description: HSE divided by 8 - name: Div8 - value: 2 - - description: HSE divided by 16 - name: Div16 - value: 3 -enum/RTCRSTW: - bit_size: 1 - variants: - - description: Resets the RTC peripheral - name: Reset - value: 1 -enum/RTCSEL: - bit_size: 2 - variants: - - description: No clock - name: NoClock - value: 0 - - description: LSE oscillator clock used as RTC clock - name: LSE - value: 1 - - description: LSI oscillator clock used as RTC clock - name: LSI - value: 2 - - description: HSE oscillator clock divided by a programmable prescaler (selection - through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used - as the RTC clock - name: HSE - value: 3 -enum/STOPWUCK: - bit_size: 1 - variants: - - description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from - Stop clock - name: MSI - value: 0 - - description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock - (or HSI16/4 if HSI16DIVEN=1) - name: HSI16 - value: 1 -enum/SW: - bit_size: 2 - variants: - - description: MSI oscillator used as system clock - name: MSI - value: 0 - - description: HSI oscillator used as system clock - name: HSI16 - value: 1 - - description: HSE oscillator used as system clock - name: HSE - value: 2 - - description: PLL used as system clock - name: PLL - value: 3 -enum/SWS: - bit_size: 2 - variants: - - description: MSI oscillator used as system clock - name: MSI - value: 0 - - description: HSI oscillator used as system clock - name: HSI16 - value: 1 - - description: HSE oscillator used as system clock - name: HSE - value: 2 - - description: PLL used as system clock - name: PLL - value: 3 + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 12 + fieldset: CFGR + - name: CIER + description: Clock interrupt enable register + byte_offset: 16 + access: Read + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 20 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 24 + access: Read + fieldset: CICR + - name: IOPRSTR + description: GPIO reset register + byte_offset: 28 + fieldset: IOPRSTR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 32 + fieldset: AHBRSTR + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 36 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register + byte_offset: 40 + fieldset: APB1RSTR + - name: IOPENR + description: GPIO clock enable register + byte_offset: 44 + fieldset: IOPENR + - name: AHBENR + description: AHB peripheral clock enable register + byte_offset: 48 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 52 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register + byte_offset: 56 + fieldset: APB1ENR + - name: IOPSMEN + description: GPIO clock enable in sleep mode register + byte_offset: 60 + fieldset: IOPSMEN + - name: AHBSMENR + description: AHB peripheral clock enable in sleep mode register + byte_offset: 64 + fieldset: AHBSMENR + - name: APB2SMENR + description: APB2 peripheral clock enable in sleep mode register + byte_offset: 68 + fieldset: APB2SMENR + - name: APB1SMENR + description: APB1 peripheral clock enable in sleep mode register + byte_offset: 72 + fieldset: APB1SMENR + - name: CCIPR + description: Clock configuration register + byte_offset: 76 + fieldset: CCIPR + - name: CSR + description: Control and status register + byte_offset: 80 + fieldset: CSR + - name: CRRCR + description: Clock recovery RC register + byte_offset: 8 + fieldset: CRRCR fieldset/AHBENR: description: AHB peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA clock enable bit - name: DMA1EN - - bit_offset: 8 - bit_size: 1 - description: NVM interface clock enable bit - name: MIFEN - - bit_offset: 12 - bit_size: 1 - description: CRC clock enable bit - name: CRCEN - - bit_offset: 24 - bit_size: 1 - description: Crypto clock enable bit - name: CRYPEN - - bit_offset: 16 - bit_size: 1 - description: Touch Sensing clock enable bit - name: TOUCHEN - - bit_offset: 20 - bit_size: 1 - description: Random Number Generator clock enable bit - name: RNGEN + - name: DMA1EN + description: DMA clock enable bit + bit_offset: 0 + bit_size: 1 + - name: MIFEN + description: NVM interface clock enable bit + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: CRC clock enable bit + bit_offset: 12 + bit_size: 1 + - name: CRYPEN + description: Crypto clock enable bit + bit_offset: 24 + bit_size: 1 + - name: TOUCHEN + description: Touch Sensing clock enable bit + bit_offset: 16 + bit_size: 1 + - name: RNGEN + description: Random Number Generator clock enable bit + bit_offset: 20 + bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA reset - enum_write: CRYPRSTW - name: DMA1RST - - bit_offset: 8 - bit_size: 1 - description: Memory interface reset - enum_write: CRYPRSTW - name: MIFRST - - bit_offset: 12 - bit_size: 1 - description: Test integration module reset - enum_write: CRYPRSTW - name: CRCRST - - bit_offset: 24 - bit_size: 1 - description: Crypto module reset - enum_write: CRYPRSTW - name: CRYPRST - - bit_offset: 16 - bit_size: 1 - description: Touch Sensing reset - enum_write: CRYPRSTW - name: TOUCHRST - - bit_offset: 20 - bit_size: 1 - description: Random Number Generator module reset - enum_write: CRYPRSTW - name: RNGRST + - name: DMA1RST + description: DMA reset + bit_offset: 0 + bit_size: 1 + enum_write: CRYPRSTW + - name: MIFRST + description: Memory interface reset + bit_offset: 8 + bit_size: 1 + enum_write: CRYPRSTW + - name: CRCRST + description: Test integration module reset + bit_offset: 12 + bit_size: 1 + enum_write: CRYPRSTW + - name: CRYPRST + description: Crypto module reset + bit_offset: 24 + bit_size: 1 + enum_write: CRYPRSTW + - name: TOUCHRST + description: Touch Sensing reset + bit_offset: 16 + bit_size: 1 + enum_write: CRYPRSTW + - name: RNGRST + description: Random Number Generator module reset + bit_offset: 20 + bit_size: 1 + enum_write: CRYPRSTW fieldset/AHBSMENR: description: AHB peripheral clock enable in sleep mode register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA clock enable during sleep mode bit - name: DMA1SMEN - - bit_offset: 8 - bit_size: 1 - description: NVM interface clock enable during sleep mode bit - name: MIFSMEN - - bit_offset: 9 - bit_size: 1 - description: SRAM interface clock enable during sleep mode bit - name: SRAMSMEN - - bit_offset: 12 - bit_size: 1 - description: CRC clock enable during sleep mode bit - name: CRCSMEN - - bit_offset: 24 - bit_size: 1 - description: Crypto clock enable during sleep mode bit - name: CRYPSMEN - - bit_offset: 16 - bit_size: 1 - description: Touch Sensing clock enable during sleep mode bit - name: TOUCHSMEN - - bit_offset: 20 - bit_size: 1 - description: Random Number Generator clock enable during sleep mode bit - name: RNGSMEN + - name: DMA1SMEN + description: DMA clock enable during sleep mode bit + bit_offset: 0 + bit_size: 1 + - name: MIFSMEN + description: NVM interface clock enable during sleep mode bit + bit_offset: 8 + bit_size: 1 + - name: SRAMSMEN + description: SRAM interface clock enable during sleep mode bit + bit_offset: 9 + bit_size: 1 + - name: CRCSMEN + description: CRC clock enable during sleep mode bit + bit_offset: 12 + bit_size: 1 + - name: CRYPSMEN + description: Crypto clock enable during sleep mode bit + bit_offset: 24 + bit_size: 1 + - name: TOUCHSMEN + description: Touch Sensing clock enable during sleep mode bit + bit_offset: 16 + bit_size: 1 + - name: RNGSMEN + description: Random Number Generator clock enable during sleep mode bit + bit_offset: 20 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: Timer2 clock enable bit - name: TIM2EN - - bit_offset: 4 - bit_size: 1 - description: Timer 6 clock enable bit - name: TIM6EN - - bit_offset: 5 - bit_size: 1 - description: Timer 7 clock enable bit - name: TIM7EN - - bit_offset: 11 - bit_size: 1 - description: Window watchdog clock enable bit - name: WWDGEN - - bit_offset: 14 - bit_size: 1 - description: SPI2 clock enable bit - name: SPI2EN - - bit_offset: 17 - bit_size: 1 - description: UART2 clock enable bit - name: USART2EN - - bit_offset: 18 - bit_size: 1 - description: LPUART1 clock enable bit - name: LPUART1EN - - bit_offset: 19 - bit_size: 1 - description: USART4 clock enable bit - name: USART4EN - - bit_offset: 20 - bit_size: 1 - description: USART5 clock enable bit - name: USART5EN - - bit_offset: 21 - bit_size: 1 - description: I2C1 clock enable bit - name: I2C1EN - - bit_offset: 22 - bit_size: 1 - description: I2C2 clock enable bit - name: I2C2EN - - bit_offset: 28 - bit_size: 1 - description: Power interface clock enable bit - name: PWREN - - bit_offset: 30 - bit_size: 1 - description: I2C3 clock enable bit - name: I2C3EN - - bit_offset: 31 - bit_size: 1 - description: Low power timer clock enable bit - name: LPTIM1EN - - bit_offset: 1 - bit_size: 1 - description: Timer 3 clock enbale bit - name: TIM3EN - - bit_offset: 23 - bit_size: 1 - description: USB clock enable bit - name: USBEN - - bit_offset: 27 - bit_size: 1 - description: Clock recovery system clock enable bit - name: CRSEN - - bit_offset: 29 - bit_size: 1 - description: DAC interface clock enable bit - name: DACEN + - name: TIM2EN + description: Timer2 clock enable bit + bit_offset: 0 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable bit + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable bit + bit_offset: 5 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable bit + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable bit + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: UART2 clock enable bit + bit_offset: 17 + bit_size: 1 + - name: LPUART1EN + description: LPUART1 clock enable bit + bit_offset: 18 + bit_size: 1 + - name: USART4EN + description: USART4 clock enable bit + bit_offset: 19 + bit_size: 1 + - name: USART5EN + description: USART5 clock enable bit + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable bit + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable bit + bit_offset: 22 + bit_size: 1 + - name: PWREN + description: Power interface clock enable bit + bit_offset: 28 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable bit + bit_offset: 30 + bit_size: 1 + - name: LPTIM1EN + description: Low power timer clock enable bit + bit_offset: 31 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enbale bit + bit_offset: 1 + bit_size: 1 + - name: USBEN + description: USB clock enable bit + bit_offset: 23 + bit_size: 1 + - name: CRSEN + description: Clock recovery system clock enable bit + bit_offset: 27 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable bit + bit_offset: 29 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: Timer 2 reset - enum_write: LPTIMRSTW - name: TIM2RST - - bit_offset: 1 - bit_size: 1 - description: Timer 3 reset - enum_write: LPTIMRSTW - name: TIM3RST - - bit_offset: 4 - bit_size: 1 - description: Timer 6 reset - enum_write: LPTIMRSTW - name: TIM6RST - - bit_offset: 5 - bit_size: 1 - description: Timer 7 reset - enum_write: LPTIMRSTW - name: TIM7RST - - bit_offset: 11 - bit_size: 1 - description: Window watchdog reset - enum_write: LPTIMRSTW - name: WWDGRST - - bit_offset: 14 - bit_size: 1 - description: SPI2 reset - enum_write: LPTIMRSTW - name: SPI2RST - - bit_offset: 17 - bit_size: 1 - description: USART2 reset - enum_write: LPTIMRSTW - name: USART2RST - - bit_offset: 18 - bit_size: 1 - description: LPUART1 reset - enum_write: LPTIMRSTW - name: LPUART1RST - - bit_offset: 19 - bit_size: 1 - description: USART4 reset - enum_write: LPTIMRSTW - name: USART4RST - - bit_offset: 20 - bit_size: 1 - description: USART5 reset - enum_write: LPTIMRSTW - name: USART5RST - - bit_offset: 21 - bit_size: 1 - description: I2C1 reset - enum_write: LPTIMRSTW - name: I2C1RST - - bit_offset: 22 - bit_size: 1 - description: I2C2 reset - enum_write: LPTIMRSTW - name: I2C2RST - - bit_offset: 28 - bit_size: 1 - description: Power interface reset - enum_write: LPTIMRSTW - name: PWRRST - - bit_offset: 31 - bit_size: 1 - description: Low power timer reset - enum_write: LPTIMRSTW - name: LPTIM1RST - - bit_offset: 30 - bit_size: 1 - description: I2C3 reset - enum_write: LPTIMRSTW - name: I2C3RST - - bit_offset: 23 - bit_size: 1 - description: USB reset - enum_write: LPTIMRSTW - name: USBRST - - bit_offset: 27 - bit_size: 1 - description: Clock recovery system reset - enum_write: LPTIMRSTW - name: CRSRST - - bit_offset: 29 - bit_size: 1 - description: DAC interface reset - enum_write: LPTIMRSTW - name: DACRST + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + enum_write: LPTIMRSTW + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + enum_write: LPTIMRSTW + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + enum_write: LPTIMRSTW + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + enum_write: LPTIMRSTW + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + enum_write: LPTIMRSTW + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + enum_write: LPTIMRSTW + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + enum_write: LPTIMRSTW + - name: LPUART1RST + description: LPUART1 reset + bit_offset: 18 + bit_size: 1 + enum_write: LPTIMRSTW + - name: USART4RST + description: USART4 reset + bit_offset: 19 + bit_size: 1 + enum_write: LPTIMRSTW + - name: USART5RST + description: USART5 reset + bit_offset: 20 + bit_size: 1 + enum_write: LPTIMRSTW + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + enum_write: LPTIMRSTW + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + enum_write: LPTIMRSTW + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + enum_write: LPTIMRSTW + - name: LPTIM1RST + description: Low power timer reset + bit_offset: 31 + bit_size: 1 + enum_write: LPTIMRSTW + - name: I2C3RST + description: I2C3 reset + bit_offset: 30 + bit_size: 1 + enum_write: LPTIMRSTW + - name: USBRST + description: USB reset + bit_offset: 23 + bit_size: 1 + enum_write: LPTIMRSTW + - name: CRSRST + description: Clock recovery system reset + bit_offset: 27 + bit_size: 1 + enum_write: LPTIMRSTW + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + enum_write: LPTIMRSTW fieldset/APB1SMENR: description: APB1 peripheral clock enable in sleep mode register fields: - - bit_offset: 0 - bit_size: 1 - description: Timer2 clock enable during sleep mode bit - name: TIM2SMEN - - bit_offset: 1 - bit_size: 1 - description: Timer 3 clock enable during sleep mode bit - name: TIM3SMEN - - bit_offset: 4 - bit_size: 1 - description: Timer 6 clock enable during sleep mode bit - name: TIM6SMEN - - bit_offset: 5 - bit_size: 1 - description: Timer 7 clock enable during sleep mode bit - name: TIM7SMEN - - bit_offset: 11 - bit_size: 1 - description: Window watchdog clock enable during sleep mode bit - name: WWDGSMEN - - bit_offset: 14 - bit_size: 1 - description: SPI2 clock enable during sleep mode bit - name: SPI2SMEN - - bit_offset: 17 - bit_size: 1 - description: UART2 clock enable during sleep mode bit - name: USART2SMEN - - bit_offset: 18 - bit_size: 1 - description: LPUART1 clock enable during sleep mode bit - name: LPUART1SMEN - - bit_offset: 19 - bit_size: 1 - description: USART4 clock enabe during sleep mode bit - name: USART4SMEN - - bit_offset: 20 - bit_size: 1 - description: USART5 clock enable during sleep mode bit - name: USART5SMEN - - bit_offset: 21 - bit_size: 1 - description: I2C1 clock enable during sleep mode bit - name: I2C1SMEN - - bit_offset: 22 - bit_size: 1 - description: I2C2 clock enable during sleep mode bit - name: I2C2SMEN - - bit_offset: 27 - bit_size: 1 - description: Clock recovery system clock enable during sleep mode bit - name: CRSSMEN - - bit_offset: 28 - bit_size: 1 - description: Power interface clock enable during sleep mode bit - name: PWRSMEN - - bit_offset: 30 - bit_size: 1 - description: I2C3 clock enable during sleep mode bit - name: I2C3SMEN - - bit_offset: 31 - bit_size: 1 - description: Low power timer clock enable during sleep mode bit - name: LPTIM1SMEN - - bit_offset: 23 - bit_size: 1 - description: USB clock enable during sleep mode bit - name: USBSMEN - - bit_offset: 29 - bit_size: 1 - description: DAC interface clock enable during sleep mode bit - name: DACSMEN + - name: TIM2SMEN + description: Timer2 clock enable during sleep mode bit + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: Timer 3 clock enable during sleep mode bit + bit_offset: 1 + bit_size: 1 + - name: TIM6SMEN + description: Timer 6 clock enable during sleep mode bit + bit_offset: 4 + bit_size: 1 + - name: TIM7SMEN + description: Timer 7 clock enable during sleep mode bit + bit_offset: 5 + bit_size: 1 + - name: WWDGSMEN + description: Window watchdog clock enable during sleep mode bit + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clock enable during sleep mode bit + bit_offset: 14 + bit_size: 1 + - name: USART2SMEN + description: UART2 clock enable during sleep mode bit + bit_offset: 17 + bit_size: 1 + - name: LPUART1SMEN + description: LPUART1 clock enable during sleep mode bit + bit_offset: 18 + bit_size: 1 + - name: USART4SMEN + description: USART4 clock enabe during sleep mode bit + bit_offset: 19 + bit_size: 1 + - name: USART5SMEN + description: USART5 clock enable during sleep mode bit + bit_offset: 20 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clock enable during sleep mode bit + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clock enable during sleep mode bit + bit_offset: 22 + bit_size: 1 + - name: CRSSMEN + description: Clock recovery system clock enable during sleep mode bit + bit_offset: 27 + bit_size: 1 + - name: PWRSMEN + description: Power interface clock enable during sleep mode bit + bit_offset: 28 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clock enable during sleep mode bit + bit_offset: 30 + bit_size: 1 + - name: LPTIM1SMEN + description: Low power timer clock enable during sleep mode bit + bit_offset: 31 + bit_size: 1 + - name: USBSMEN + description: USB clock enable during sleep mode bit + bit_offset: 23 + bit_size: 1 + - name: DACSMEN + description: DAC interface clock enable during sleep mode bit + bit_offset: 29 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: System configuration controller clock enable bit - name: SYSCFGEN - - bit_offset: 2 - bit_size: 1 - description: TIM21 timer clock enable bit - name: TIM21EN - - bit_offset: 5 - bit_size: 1 - description: TIM22 timer clock enable bit - name: TIM22EN - - bit_offset: 7 - bit_size: 1 - description: Firewall clock enable bit - name: FWEN - - bit_offset: 9 - bit_size: 1 - description: ADC clock enable bit - name: ADCEN - - bit_offset: 12 - bit_size: 1 - description: SPI1 clock enable bit - name: SPI1EN - - bit_offset: 14 - bit_size: 1 - description: USART1 clock enable bit - name: USART1EN - - bit_offset: 22 - bit_size: 1 - description: DBG clock enable bit - name: DBGEN - - bit_offset: 7 - bit_size: 1 - description: MiFaRe Firewall clock enable bit - name: MIFIEN + - name: SYSCFGEN + description: System configuration controller clock enable bit + bit_offset: 0 + bit_size: 1 + - name: TIM21EN + description: TIM21 timer clock enable bit + bit_offset: 2 + bit_size: 1 + - name: TIM22EN + description: TIM22 timer clock enable bit + bit_offset: 5 + bit_size: 1 + - name: FWEN + description: Firewall clock enable bit + bit_offset: 7 + bit_size: 1 + - name: ADCEN + description: ADC clock enable bit + bit_offset: 9 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable bit + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable bit + bit_offset: 14 + bit_size: 1 + - name: DBGEN + description: DBG clock enable bit + bit_offset: 22 + bit_size: 1 + - name: MIFIEN + description: MiFaRe Firewall clock enable bit + bit_offset: 7 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: System configuration controller reset - enum_write: DBGRSTW - name: SYSCFGRST - - bit_offset: 2 - bit_size: 1 - description: TIM21 timer reset - enum_write: DBGRSTW - name: TIM21RST - - bit_offset: 5 - bit_size: 1 - description: TIM22 timer reset - enum_write: DBGRSTW - name: TIM22RST - - bit_offset: 9 - bit_size: 1 - description: ADC interface reset - enum_write: DBGRSTW - name: ADCRST - - bit_offset: 12 - bit_size: 1 - description: SPI 1 reset - enum_write: DBGRSTW - name: SPI1RST - - bit_offset: 14 - bit_size: 1 - description: USART1 reset - enum_write: DBGRSTW - name: USART1RST - - bit_offset: 22 - bit_size: 1 - description: DBG reset - enum_write: DBGRSTW - name: DBGRST + - name: SYSCFGRST + description: System configuration controller reset + bit_offset: 0 + bit_size: 1 + enum_write: DBGRSTW + - name: TIM21RST + description: TIM21 timer reset + bit_offset: 2 + bit_size: 1 + enum_write: DBGRSTW + - name: TIM22RST + description: TIM22 timer reset + bit_offset: 5 + bit_size: 1 + enum_write: DBGRSTW + - name: ADCRST + description: ADC interface reset + bit_offset: 9 + bit_size: 1 + enum_write: DBGRSTW + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + enum_write: DBGRSTW + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + enum_write: DBGRSTW + - name: DBGRST + description: DBG reset + bit_offset: 22 + bit_size: 1 + enum_write: DBGRSTW fieldset/APB2SMENR: description: APB2 peripheral clock enable in sleep mode register fields: - - bit_offset: 0 - bit_size: 1 - description: System configuration controller clock enable during sleep mode bit - name: SYSCFGSMEN - - bit_offset: 2 - bit_size: 1 - description: TIM21 timer clock enable during sleep mode bit - name: TIM21SMEN - - bit_offset: 5 - bit_size: 1 - description: TIM22 timer clock enable during sleep mode bit - name: TIM22SMEN - - bit_offset: 9 - bit_size: 1 - description: ADC clock enable during sleep mode bit - name: ADCSMEN - - bit_offset: 12 - bit_size: 1 - description: SPI1 clock enable during sleep mode bit - name: SPI1SMEN - - bit_offset: 14 - bit_size: 1 - description: USART1 clock enable during sleep mode bit - name: USART1SMEN - - bit_offset: 22 - bit_size: 1 - description: DBG clock enable during sleep mode bit - name: DBGSMEN + - name: SYSCFGSMEN + description: System configuration controller clock enable during sleep mode bit + bit_offset: 0 + bit_size: 1 + - name: TIM21SMEN + description: TIM21 timer clock enable during sleep mode bit + bit_offset: 2 + bit_size: 1 + - name: TIM22SMEN + description: TIM22 timer clock enable during sleep mode bit + bit_offset: 5 + bit_size: 1 + - name: ADCSMEN + description: ADC clock enable during sleep mode bit + bit_offset: 9 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clock enable during sleep mode bit + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: USART1 clock enable during sleep mode bit + bit_offset: 14 + bit_size: 1 + - name: DBGSMEN + description: DBG clock enable during sleep mode bit + bit_offset: 22 + bit_size: 1 fieldset/CCIPR: description: Clock configuration register fields: - - bit_offset: 0 - bit_size: 2 - description: USART1 clock source selection bits - enum: LPUARTSEL - name: USART1SEL - - bit_offset: 2 - bit_size: 2 - description: USART2 clock source selection bits - enum: LPUARTSEL - name: USART2SEL - - bit_offset: 10 - bit_size: 2 - description: LPUART1 clock source selection bits - enum: LPUARTSEL - name: LPUART1SEL - - bit_offset: 12 - bit_size: 2 - description: I2C1 clock source selection bits - enum: ICSEL - name: I2C1SEL - - bit_offset: 16 - bit_size: 2 - description: I2C3 clock source selection bits - enum: ICSEL - name: I2C3SEL - - bit_offset: 18 - bit_size: 2 - description: Low Power Timer clock source selection bits - enum: LPTIMSEL - name: LPTIM1SEL - - bit_offset: 26 - bit_size: 1 - description: 48 MHz HSI48 clock source selection bit - name: HSI48MSEL + - name: USART1SEL + description: USART1 clock source selection bits + bit_offset: 0 + bit_size: 2 + enum: LPUARTSEL + - name: USART2SEL + description: USART2 clock source selection bits + bit_offset: 2 + bit_size: 2 + enum: LPUARTSEL + - name: LPUART1SEL + description: LPUART1 clock source selection bits + bit_offset: 10 + bit_size: 2 + enum: LPUARTSEL + - name: I2C1SEL + description: I2C1 clock source selection bits + bit_offset: 12 + bit_size: 2 + enum: ICSEL + - name: I2C3SEL + description: I2C3 clock source selection bits + bit_offset: 16 + bit_size: 2 + enum: ICSEL + - name: LPTIM1SEL + description: Low Power Timer clock source selection bits + bit_offset: 18 + bit_size: 2 + enum: LPTIMSEL + - name: HSI48MSEL + description: 48 MHz HSI48 clock source selection bit + bit_offset: 26 + bit_size: 1 fieldset/CFGR: description: Clock configuration register fields: - - bit_offset: 0 - bit_size: 2 - description: System clock switch - enum: SW - name: SW - - bit_offset: 2 - bit_size: 2 - description: System clock switch status - enum: SWS - name: SWS - - bit_offset: 4 - bit_size: 4 - description: AHB prescaler - enum: HPRE - name: HPRE - - bit_offset: 8 - bit_size: 3 - description: APB low-speed prescaler (APB1) - enum: PPRE - name: PPRE1 - - bit_offset: 11 - bit_size: 3 - description: APB high-speed prescaler (APB2) - enum: PPRE - name: PPRE2 - - bit_offset: 15 - bit_size: 1 - description: Wake-up from stop clock selection - enum: STOPWUCK - name: STOPWUCK - - bit_offset: 16 - bit_size: 1 - description: PLL entry clock source - enum: PLLSRC - name: PLLSRC - - bit_offset: 18 - bit_size: 4 - description: PLL multiplication factor - enum: PLLMUL - name: PLLMUL - - bit_offset: 22 - bit_size: 2 - description: PLL output division - enum: PLLDIV - name: PLLDIV - - bit_offset: 24 - bit_size: 3 - description: Microcontroller clock output selection - enum: MCOSEL - name: MCOSEL - - bit_offset: 28 - bit_size: 3 - description: Microcontroller clock output prescaler - enum: MCOPRE - name: MCOPRE + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum: SWS + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: STOPWUCK + description: Wake-up from stop clock selection + bit_offset: 15 + bit_size: 1 + enum: STOPWUCK + - name: PLLSRC + description: PLL entry clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLMUL + description: PLL multiplication factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: PLLDIV + description: PLL output division + bit_offset: 22 + bit_size: 2 + enum: PLLDIV + - name: MCOSEL + description: Microcontroller clock output selection + bit_offset: 24 + bit_size: 3 + enum: MCOSEL + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready Interrupt clear - enum_write: CSSHSECW - name: LSIRDYC - - bit_offset: 1 - bit_size: 1 - description: LSE ready Interrupt clear - enum_write: CSSHSECW - name: LSERDYC - - bit_offset: 2 - bit_size: 1 - description: HSI16 ready Interrupt clear - enum_write: CSSHSECW - name: HSI16RDYC - - bit_offset: 3 - bit_size: 1 - description: HSE ready Interrupt clear - enum_write: CSSHSECW - name: HSERDYC - - bit_offset: 4 - bit_size: 1 - description: PLL ready Interrupt clear - enum_write: CSSHSECW - name: PLLRDYC - - bit_offset: 5 - bit_size: 1 - description: MSI ready Interrupt clear - enum_write: CSSHSECW - name: MSIRDYC - - bit_offset: 7 - bit_size: 1 - description: LSE Clock Security System Interrupt clear - enum_write: CSSHSECW - name: CSSLSEC - - bit_offset: 8 - bit_size: 1 - description: Clock Security System Interrupt clear - enum_write: CSSHSECW - name: CSSHSEC - - bit_offset: 6 - bit_size: 1 - description: HSI48 ready Interrupt clear - enum_write: CSSHSECW - name: HSI48RDYC + - name: LSIRDYC + description: LSI ready Interrupt clear + bit_offset: 0 + bit_size: 1 + enum_write: CSSHSECW + - name: LSERDYC + description: LSE ready Interrupt clear + bit_offset: 1 + bit_size: 1 + enum_write: CSSHSECW + - name: HSI16RDYC + description: HSI16 ready Interrupt clear + bit_offset: 2 + bit_size: 1 + enum_write: CSSHSECW + - name: HSERDYC + description: HSE ready Interrupt clear + bit_offset: 3 + bit_size: 1 + enum_write: CSSHSECW + - name: PLLRDYC + description: PLL ready Interrupt clear + bit_offset: 4 + bit_size: 1 + enum_write: CSSHSECW + - name: MSIRDYC + description: MSI ready Interrupt clear + bit_offset: 5 + bit_size: 1 + enum_write: CSSHSECW + - name: CSSLSEC + description: LSE Clock Security System Interrupt clear + bit_offset: 7 + bit_size: 1 + enum_write: CSSHSECW + - name: CSSHSEC + description: Clock Security System Interrupt clear + bit_offset: 8 + bit_size: 1 + enum_write: CSSHSECW + - name: HSI48RDYC + description: HSI48 ready Interrupt clear + bit_offset: 6 + bit_size: 1 + enum_write: CSSHSECW fieldset/CIER: description: Clock interrupt enable register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready interrupt flag - enum: MSIRDYIE - name: LSIRDYIE - - bit_offset: 1 - bit_size: 1 - description: LSE ready interrupt flag - enum: MSIRDYIE - name: LSERDYIE - - bit_offset: 2 - bit_size: 1 - description: HSI16 ready interrupt flag - enum: MSIRDYIE - name: HSI16RDYIE - - bit_offset: 3 - bit_size: 1 - description: HSE ready interrupt flag - enum: MSIRDYIE - name: HSERDYIE - - bit_offset: 4 - bit_size: 1 - description: PLL ready interrupt flag - enum: MSIRDYIE - name: PLLRDYIE - - bit_offset: 5 - bit_size: 1 - description: MSI ready interrupt flag - enum: MSIRDYIE - name: MSIRDYIE - - bit_offset: 7 - bit_size: 1 - description: LSE CSS interrupt flag - enum: CSSLSE - name: CSSLSE - - bit_offset: 6 - bit_size: 1 - description: HSI48 ready interrupt flag - enum: HSIRDYIE - name: HSI48RDYIE + - name: LSIRDYIE + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + enum: MSIRDYIE + - name: LSERDYIE + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + enum: MSIRDYIE + - name: HSI16RDYIE + description: HSI16 ready interrupt flag + bit_offset: 2 + bit_size: 1 + enum: MSIRDYIE + - name: HSERDYIE + description: HSE ready interrupt flag + bit_offset: 3 + bit_size: 1 + enum: MSIRDYIE + - name: PLLRDYIE + description: PLL ready interrupt flag + bit_offset: 4 + bit_size: 1 + enum: MSIRDYIE + - name: MSIRDYIE + description: MSI ready interrupt flag + bit_offset: 5 + bit_size: 1 + enum: MSIRDYIE + - name: CSSLSE + description: LSE CSS interrupt flag + bit_offset: 7 + bit_size: 1 + enum: CSSLSE + - name: HSI48RDYIE + description: HSI48 ready interrupt flag + bit_offset: 6 + bit_size: 1 + enum: HSIRDYIE fieldset/CIFR: description: Clock interrupt flag register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready interrupt flag - enum_read: MSIRDYFR - name: LSIRDYF - - bit_offset: 1 - bit_size: 1 - description: LSE ready interrupt flag - enum_read: MSIRDYFR - name: LSERDYF - - bit_offset: 2 - bit_size: 1 - description: HSI16 ready interrupt flag - enum_read: MSIRDYFR - name: HSI16RDYF - - bit_offset: 3 - bit_size: 1 - description: HSE ready interrupt flag - enum_read: MSIRDYFR - name: HSERDYF - - bit_offset: 4 - bit_size: 1 - description: PLL ready interrupt flag - enum_read: MSIRDYFR - name: PLLRDYF - - bit_offset: 5 - bit_size: 1 - description: MSI ready interrupt flag - enum_read: MSIRDYFR - name: MSIRDYF - - bit_offset: 7 - bit_size: 1 - description: LSE Clock Security System Interrupt flag - enum: CSSLSEF - name: CSSLSEF - - bit_offset: 8 - bit_size: 1 - description: Clock Security System Interrupt flag - enum: CSSHSEF - name: CSSHSEF - - bit_offset: 6 - bit_size: 1 - description: HSI48 ready interrupt flag - enum_read: HSI48RDYFR - name: HSI48RDYF + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + enum_read: MSIRDYFR + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + enum_read: MSIRDYFR + - name: HSI16RDYF + description: HSI16 ready interrupt flag + bit_offset: 2 + bit_size: 1 + enum_read: MSIRDYFR + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 3 + bit_size: 1 + enum_read: MSIRDYFR + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 4 + bit_size: 1 + enum_read: MSIRDYFR + - name: MSIRDYF + description: MSI ready interrupt flag + bit_offset: 5 + bit_size: 1 + enum_read: MSIRDYFR + - name: CSSLSEF + description: LSE Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + enum: CSSLSEF + - name: CSSHSEF + description: Clock Security System Interrupt flag + bit_offset: 8 + bit_size: 1 + enum: CSSHSEF + - name: HSI48RDYF + description: HSI48 ready interrupt flag + bit_offset: 6 + bit_size: 1 + enum_read: HSI48RDYFR fieldset/CR: description: Clock control register fields: - - bit_offset: 0 - bit_size: 1 - description: 16 MHz high-speed internal clock enable - name: HSI16ON - - bit_offset: 1 - bit_size: 1 - description: High-speed internal clock enable bit for some IP kernels - name: HSI16KERON - - bit_offset: 2 - bit_size: 1 - description: Internal high-speed clock ready flag - enum_read: HSIRDYFR - name: HSI16RDYF - - bit_offset: 3 - bit_size: 1 - description: HSI16DIVEN - name: HSI16DIVEN - - bit_offset: 4 - bit_size: 1 - description: HSI16DIVF - enum_read: HSIDIVFR - name: HSI16DIVF - - bit_offset: 5 - bit_size: 1 - description: 16 MHz high-speed internal clock output enable - name: HSI16OUTEN - - bit_offset: 8 - bit_size: 1 - description: MSI clock enable bit - name: MSION - - bit_offset: 9 - bit_size: 1 - description: MSI clock ready flag - enum_read: HSERDYR - name: MSIRDY - - bit_offset: 16 - bit_size: 1 - description: HSE clock enable bit - name: HSEON - - bit_offset: 17 - bit_size: 1 - description: HSE clock ready flag - enum_read: HSERDYR - name: HSERDY - - bit_offset: 18 - bit_size: 1 - description: HSE clock bypass bit - enum: HSEBYP - name: HSEBYP - - bit_offset: 19 - bit_size: 1 - description: Clock security system on HSE enable bit - name: CSSHSEON - - bit_offset: 20 - bit_size: 2 - description: TC/LCD prescaler - enum: RTCPRE - name: RTCPRE - - bit_offset: 24 - bit_size: 1 - description: PLL enable bit - name: PLLON - - bit_offset: 25 - bit_size: 1 - description: PLL clock ready flag - enum_read: PLLRDYR - name: PLLRDY + - name: HSI16ON + description: 16 MHz high-speed internal clock enable + bit_offset: 0 + bit_size: 1 + - name: HSI16KERON + description: High-speed internal clock enable bit for some IP kernels + bit_offset: 1 + bit_size: 1 + - name: HSI16RDYF + description: Internal high-speed clock ready flag + bit_offset: 2 + bit_size: 1 + enum_read: HSIRDYFR + - name: HSI16DIVEN + description: HSI16DIVEN + bit_offset: 3 + bit_size: 1 + - name: HSI16DIVF + description: HSI16DIVF + bit_offset: 4 + bit_size: 1 + enum_read: HSIDIVFR + - name: HSI16OUTEN + description: 16 MHz high-speed internal clock output enable + bit_offset: 5 + bit_size: 1 + - name: MSION + description: MSI clock enable bit + bit_offset: 8 + bit_size: 1 + - name: MSIRDY + description: MSI clock ready flag + bit_offset: 9 + bit_size: 1 + enum_read: HSERDYR + - name: HSEON + description: HSE clock enable bit + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + enum_read: HSERDYR + - name: HSEBYP + description: HSE clock bypass bit + bit_offset: 18 + bit_size: 1 + enum: HSEBYP + - name: CSSHSEON + description: Clock security system on HSE enable bit + bit_offset: 19 + bit_size: 1 + - name: RTCPRE + description: TC/LCD prescaler + bit_offset: 20 + bit_size: 2 + enum: RTCPRE + - name: PLLON + description: PLL enable bit + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 + enum_read: PLLRDYR fieldset/CRRCR: description: Clock recovery RC register fields: - - bit_offset: 0 - bit_size: 1 - description: 48MHz HSI clock enable bit - name: HSI48ON - - bit_offset: 1 - bit_size: 1 - description: 48MHz HSI clock ready flag - name: HSI48RDY - - bit_offset: 2 - bit_size: 1 - description: 48 MHz HSI clock divided by 6 output enable - name: HSI48DIV6EN - - bit_offset: 8 - bit_size: 8 - description: 48 MHz HSI clock calibration - name: HSI48CAL + - name: HSI48ON + description: 48MHz HSI clock enable bit + bit_offset: 0 + bit_size: 1 + - name: HSI48RDY + description: 48MHz HSI clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSI48DIV6EN + description: 48 MHz HSI clock divided by 6 output enable + bit_offset: 2 + bit_size: 1 + - name: HSI48CAL + description: 48 MHz HSI clock calibration + bit_offset: 8 + bit_size: 8 fieldset/CSR: description: Control and status register fields: - - bit_offset: 0 - bit_size: 1 - description: Internal low-speed oscillator enable - name: LSION - - bit_offset: 1 - bit_size: 1 - description: Internal low-speed oscillator ready bit - enum: LSERDY - name: LSIRDY - - bit_offset: 8 - bit_size: 1 - description: External low-speed oscillator enable bit - name: LSEON - - bit_offset: 9 - bit_size: 1 - description: External low-speed oscillator ready bit - enum: LSERDY - name: LSERDY - - bit_offset: 10 - bit_size: 1 - description: External low-speed oscillator bypass bit - enum: LSEBYP - name: LSEBYP - - bit_offset: 11 - bit_size: 2 - description: LSEDRV - enum: LSEDRV - name: LSEDRV - - bit_offset: 13 - bit_size: 1 - description: CSSLSEON - name: CSSLSEON - - bit_offset: 14 - bit_size: 1 - description: CSS on LSE failure detection flag - enum: CSSLSED - name: CSSLSED - - bit_offset: 16 - bit_size: 2 - description: RTC and LCD clock source selection bits - enum: RTCSEL - name: RTCSEL - - bit_offset: 18 - bit_size: 1 - description: RTC clock enable bit - name: RTCEN - - bit_offset: 19 - bit_size: 1 - description: RTC software reset bit - enum_write: RTCRSTW - name: RTCRST - - bit_offset: 23 - bit_size: 1 - description: Remove reset flag - enum_write: RMVFW - name: RMVF - - bit_offset: 24 - bit_size: 1 - description: Firewall reset flag - enum_read: LPWRRSTFR - name: FWRSTF - - bit_offset: 25 - bit_size: 1 - description: OBLRSTF - enum_read: LPWRRSTFR - name: OBLRSTF - - bit_offset: 26 - bit_size: 1 - description: PIN reset flag - enum_read: LPWRRSTFR - name: PINRSTF - - bit_offset: 27 - bit_size: 1 - description: POR/PDR reset flag - enum_read: LPWRRSTFR - name: PORRSTF - - bit_offset: 28 - bit_size: 1 - description: Software reset flag - enum_read: LPWRRSTFR - name: SFTRSTF - - bit_offset: 29 - bit_size: 1 - description: Independent watchdog reset flag - enum_read: LPWRRSTFR - name: IWDGRSTF - - bit_offset: 30 - bit_size: 1 - description: Window watchdog reset flag - enum_read: LPWRRSTFR - name: WWDGRSTF - - bit_offset: 31 - bit_size: 1 - description: Low-power reset flag - enum_read: LPWRRSTFR - name: LPWRRSTF - - bit_offset: 31 - bit_size: 1 - description: Low-power reset flag - enum_read: LPWRSTFR - name: LPWRSTF + - name: LSION + description: Internal low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low-speed oscillator ready bit + bit_offset: 1 + bit_size: 1 + enum: LSERDY + - name: LSEON + description: External low-speed oscillator enable bit + bit_offset: 8 + bit_size: 1 + - name: LSERDY + description: External low-speed oscillator ready bit + bit_offset: 9 + bit_size: 1 + enum: LSERDY + - name: LSEBYP + description: External low-speed oscillator bypass bit + bit_offset: 10 + bit_size: 1 + enum: LSEBYP + - name: LSEDRV + description: LSEDRV + bit_offset: 11 + bit_size: 2 + enum: LSEDRV + - name: CSSLSEON + description: CSSLSEON + bit_offset: 13 + bit_size: 1 + - name: CSSLSED + description: CSS on LSE failure detection flag + bit_offset: 14 + bit_size: 1 + enum: CSSLSED + - name: RTCSEL + description: RTC and LCD clock source selection bits + bit_offset: 16 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable bit + bit_offset: 18 + bit_size: 1 + - name: RTCRST + description: RTC software reset bit + bit_offset: 19 + bit_size: 1 + enum_write: RTCRSTW + - name: RMVF + description: Remove reset flag + bit_offset: 23 + bit_size: 1 + enum_write: RMVFW + - name: FWRSTF + description: Firewall reset flag + bit_offset: 24 + bit_size: 1 + enum_read: LPWRRSTFR + - name: OBLRSTF + description: OBLRSTF + bit_offset: 25 + bit_size: 1 + enum_read: LPWRRSTFR + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + enum_read: LPWRRSTFR + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + enum_read: LPWRRSTFR + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + enum_read: LPWRRSTFR + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + enum_read: LPWRRSTFR + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + enum_read: LPWRRSTFR + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 + enum_read: LPWRRSTFR + - name: LPWRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 + enum_read: LPWRSTFR fieldset/ICSCR: description: Internal clock sources calibration register fields: - - bit_offset: 0 - bit_size: 8 - description: nternal high speed clock calibration - name: HSI16CAL - - bit_offset: 8 - bit_size: 5 - description: High speed internal clock trimming - name: HSI16TRIM - - bit_offset: 13 - bit_size: 3 - description: MSI clock ranges - enum: MSIRANGE - name: MSIRANGE - - bit_offset: 16 - bit_size: 8 - description: MSI clock calibration - name: MSICAL - - bit_offset: 24 - bit_size: 8 - description: MSI clock trimming - name: MSITRIM + - name: HSI16CAL + description: nternal high speed clock calibration + bit_offset: 0 + bit_size: 8 + - name: HSI16TRIM + description: High speed internal clock trimming + bit_offset: 8 + bit_size: 5 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 13 + bit_size: 3 + enum: MSIRANGE + - name: MSICAL + description: MSI clock calibration + bit_offset: 16 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 24 + bit_size: 8 fieldset/IOPENR: description: GPIO clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: IO port A clock enable bit - name: GPIOAEN - - bit_offset: 1 - bit_size: 1 - description: IO port B clock enable bit - name: GPIOBEN - - bit_offset: 2 - bit_size: 1 - description: IO port A clock enable bit - name: GPIOCEN - - bit_offset: 3 - bit_size: 1 - description: I/O port D clock enable bit - name: GPIODEN - - bit_offset: 4 - bit_size: 1 - description: IO port E clock enable bit - name: GPIOEEN - - bit_offset: 7 - bit_size: 1 - description: I/O port H clock enable bit - name: GPIOHEN + - name: GPIOAEN + description: IO port A clock enable bit + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable bit + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port A clock enable bit + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable bit + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable bit + bit_offset: 4 + bit_size: 1 + - name: GPIOHEN + description: I/O port H clock enable bit + bit_offset: 7 + bit_size: 1 fieldset/IOPRSTR: description: GPIO reset register fields: - - bit_offset: 0 - bit_size: 1 - description: I/O port A reset - name: GPIOARST - - bit_offset: 1 - bit_size: 1 - description: I/O port B reset - name: GPIOBRST - - bit_offset: 2 - bit_size: 1 - description: I/O port A reset - name: GPIOCRST - - bit_offset: 3 - bit_size: 1 - description: I/O port D reset - name: GPIODRST - - bit_offset: 4 - bit_size: 1 - description: I/O port E reset - name: GPIOERST - - bit_offset: 7 - bit_size: 1 - description: I/O port H reset - name: GPIOHRST + - name: GPIOARST + description: I/O port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: I/O port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: I/O port A reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: I/O port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: I/O port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOHRST + description: I/O port H reset + bit_offset: 7 + bit_size: 1 fieldset/IOPSMEN: description: GPIO clock enable in sleep mode register fields: - - bit_offset: 0 - bit_size: 1 - description: Port A clock enable during Sleep mode bit - name: IOPASMEN - - bit_offset: 1 - bit_size: 1 - description: Port B clock enable during Sleep mode bit - name: IOPBSMEN - - bit_offset: 2 - bit_size: 1 - description: Port C clock enable during Sleep mode bit - name: IOPCSMEN - - bit_offset: 3 - bit_size: 1 - description: Port D clock enable during Sleep mode bit - name: IOPDSMEN - - bit_offset: 4 - bit_size: 1 - description: Port E clock enable during Sleep mode bit - name: IOPESMEN - - bit_offset: 7 - bit_size: 1 - description: Port H clock enable during Sleep mode bit - name: IOPHSMEN + - name: IOPASMEN + description: Port A clock enable during Sleep mode bit + bit_offset: 0 + bit_size: 1 + - name: IOPBSMEN + description: Port B clock enable during Sleep mode bit + bit_offset: 1 + bit_size: 1 + - name: IOPCSMEN + description: Port C clock enable during Sleep mode bit + bit_offset: 2 + bit_size: 1 + - name: IOPDSMEN + description: Port D clock enable during Sleep mode bit + bit_offset: 3 + bit_size: 1 + - name: IOPESMEN + description: Port E clock enable during Sleep mode bit + bit_offset: 4 + bit_size: 1 + - name: IOPHSMEN + description: Port H clock enable during Sleep mode bit + bit_offset: 7 + bit_size: 1 +enum/CRYPRSTW: + bit_size: 1 + variants: + - name: Reset + description: Reset the module + value: 1 +enum/CSSHSECW: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag + value: 1 +enum/CSSHSEF: + bit_size: 1 + variants: + - name: NoClock + description: No clock security interrupt caused by HSE clock failure + value: 0 + - name: Clock + description: Clock security interrupt caused by HSE clock failure + value: 1 +enum/CSSLSE: + bit_size: 1 + variants: + - name: Disabled + description: LSE CSS interrupt disabled + value: 0 + - name: Enabled + description: LSE CSS interrupt enabled + value: 1 +enum/CSSLSED: + bit_size: 1 + variants: + - name: NoFailure + description: No failure detected on LSE (32 kHz oscillator) + value: 0 + - name: Failure + description: Failure detected on LSE (32 kHz oscillator) + value: 1 +enum/CSSLSEF: + bit_size: 1 + variants: + - name: NoFailure + description: No failure detected on LSE clock failure + value: 0 + - name: Failure + description: Failure detected on LSE clock failure + value: 1 +enum/DBGRSTW: + bit_size: 1 + variants: + - name: Reset + description: Reset the module + value: 1 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: system clock not divided + value: 0 + - name: Div2 + description: system clock divided by 2 + value: 8 + - name: Div4 + description: system clock divided by 4 + value: 9 + - name: Div8 + description: system clock divided by 8 + value: 10 + - name: Div16 + description: system clock divided by 16 + value: 11 + - name: Div64 + description: system clock divided by 64 + value: 12 + - name: Div128 + description: system clock divided by 128 + value: 13 + - name: Div256 + description: system clock divided by 256 + value: 14 + - name: Div512 + description: system clock divided by 512 + value: 15 +enum/HSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: HSE oscillator not bypassed + value: 0 + - name: Bypassed + description: HSE oscillator bypassed + value: 1 +enum/HSERDYR: + bit_size: 1 + variants: + - name: NotReady + description: Oscillator is not stable + value: 0 + - name: Ready + description: Oscillator is stable + value: 1 +enum/HSI16RDYFR: + bit_size: 1 + variants: + - name: NotReady + description: HSI 16 MHz oscillator not ready + value: 0 + - name: Ready + description: HSI 16 MHz oscillator ready + value: 1 +enum/HSI48RDYFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock ready interrupt + value: 0 + - name: Interrupted + description: Clock ready interrupt + value: 1 +enum/HSIDIVFR: + bit_size: 1 + variants: + - name: NotDivided + description: 16 MHz HSI clock not divided + value: 0 + - name: Div4 + description: 16 MHz HSI clock divided by 4 + value: 1 +enum/HSIRDYFR: + bit_size: 1 + variants: + - name: NotReady + description: HSI 16 MHz oscillator not ready + value: 0 + - name: Ready + description: HSI 16 MHz oscillator ready + value: 1 +enum/HSIRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Ready interrupt disabled + value: 0 + - name: Enabled + description: Ready interrupt enabled + value: 1 +enum/ICSEL: + bit_size: 2 + variants: + - name: APB + description: APB clock selected as peripheral clock + value: 0 + - name: SYSTEM + description: System clock selected as peripheral clock + value: 1 + - name: HSI16 + description: HSI16 clock selected as peripheral clock + value: 2 +enum/LPTIMRSTW: + bit_size: 1 + variants: + - name: Reset + description: Reset the module + value: 1 +enum/LPTIMSEL: + bit_size: 2 + variants: + - name: APB + description: APB clock selected as Timer clock + value: 0 + - name: LSI + description: LSI clock selected as Timer clock + value: 1 + - name: HSI16 + description: HSI16 clock selected as Timer clock + value: 2 + - name: LSE + description: LSE clock selected as Timer clock + value: 3 +enum/LPUARTSEL: + bit_size: 2 + variants: + - name: APB + description: APB clock selected as peripheral clock + value: 0 + - name: SYSTEM + description: System clock selected as peripheral clock + value: 1 + - name: HSI16 + description: HSI16 clock selected as peripheral clock + value: 2 + - name: LSE + description: LSE clock selected as peripheral clock + value: 3 +enum/LPWRRSTFR: + bit_size: 1 + variants: + - name: NoReset + description: No reset has occured + value: 0 + - name: Reset + description: A reset has occured + value: 1 +enum/LPWRSTFR: + bit_size: 1 + variants: + - name: NoReset + description: No reset has occured + value: 0 + - name: Reset + description: A reset has occured + value: 1 +enum/LSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: LSE oscillator not bypassed + value: 0 + - name: Bypassed + description: LSE oscillator bypassed + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Lowest drive + value: 0 + - name: MediumLow + description: Medium low drive + value: 1 + - name: MediumHigh + description: Medium high drive + value: 2 + - name: High + description: Highest drive + value: 3 +enum/LSERDY: + bit_size: 1 + variants: + - name: NotReady + description: Oscillator not ready + value: 0 + - name: Ready + description: Oscillator ready + value: 1 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 + - name: Div16 + description: Division by 16 + value: 4 +enum/MCOSEL: + bit_size: 4 + variants: + - name: NoClock + description: No clock + value: 0 + - name: SYSCLK + description: SYSCLK clock selected + value: 1 + - name: HSI16 + description: HSI oscillator clock selected + value: 2 + - name: MSI + description: MSI oscillator clock selected + value: 3 + - name: HSE + description: HSE oscillator clock selected + value: 4 + - name: PLL + description: PLL clock selected + value: 5 + - name: LSI + description: LSI oscillator clock selected + value: 6 + - name: LSE + description: LSE oscillator clock selected + value: 7 +enum/MSIRANGE: + bit_size: 3 + variants: + - name: Range0 + description: range 0 around 65.536 kHz + value: 0 + - name: Range1 + description: range 1 around 131.072 kHz + value: 1 + - name: Range2 + description: range 2 around 262.144 kHz + value: 2 + - name: Range3 + description: range 3 around 524.288 kHz + value: 3 + - name: Range4 + description: range 4 around 1.048 MHz + value: 4 + - name: Range5 + description: range 5 around 2.097 MHz (reset value) + value: 5 + - name: Range6 + description: range 6 around 4.194 MHz + value: 6 + - name: Range7 + description: not allowed + value: 7 +enum/MSIRDYFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock ready interrupt + value: 0 + - name: Interrupted + description: Clock ready interrupt + value: 1 +enum/MSIRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Ready interrupt disabled + value: 0 + - name: Enabled + description: Ready interrupt enabled + value: 1 +enum/PLLDIV: + bit_size: 2 + variants: + - name: Div2 + description: PLLVCO / 2 + value: 1 + - name: Div3 + description: PLLVCO / 3 + value: 2 + - name: Div4 + description: PLLVCO / 4 + value: 3 +enum/PLLMUL: + bit_size: 4 + variants: + - name: Mul3 + description: PLL clock entry x 3 + value: 0 + - name: Mul4 + description: PLL clock entry x 4 + value: 1 + - name: Mul6 + description: PLL clock entry x 6 + value: 2 + - name: Mul8 + description: PLL clock entry x 8 + value: 3 + - name: Mul12 + description: PLL clock entry x 12 + value: 4 + - name: Mul16 + description: PLL clock entry x 16 + value: 5 + - name: Mul24 + description: PLL clock entry x 24 + value: 6 + - name: Mul32 + description: PLL clock entry x 32 + value: 7 + - name: Mul48 + description: PLL clock entry x 48 + value: 8 +enum/PLLRDYR: + bit_size: 1 + variants: + - name: Unlocked + description: PLL unlocked + value: 0 + - name: Locked + description: PLL locked + value: 1 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI16 + description: HSI selected as PLL input clock + value: 0 + - name: HSE + description: HSE selected as PLL input clock + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/RMVFW: + bit_size: 1 + variants: + - name: Clear + description: Clears the reset flag + value: 1 +enum/RTCPRE: + bit_size: 2 + variants: + - name: Div2 + description: HSE divided by 2 + value: 0 + - name: Div4 + description: HSE divided by 4 + value: 1 + - name: Div8 + description: HSE divided by 8 + value: 2 + - name: Div16 + description: HSE divided by 16 + value: 3 +enum/RTCRSTW: + bit_size: 1 + variants: + - name: Reset + description: Resets the RTC peripheral + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: "HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock" + value: 3 +enum/STOPWUCK: + bit_size: 1 + variants: + - name: MSI + description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock + value: 0 + - name: HSI16 + description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1) + value: 1 +enum/SW: + bit_size: 2 + variants: + - name: MSI + description: MSI oscillator used as system clock + value: 0 + - name: HSI16 + description: HSI oscillator used as system clock + value: 1 + - name: HSE + description: HSE oscillator used as system clock + value: 2 + - name: PLL + description: PLL used as system clock + value: 3 +enum/SWS: + bit_size: 2 + variants: + - name: MSI + description: MSI oscillator used as system clock + value: 0 + - name: HSI16 + description: HSI oscillator used as system clock + value: 1 + - name: HSE + description: HSE oscillator used as system clock + value: 2 + - name: PLL + description: PLL used as system clock + value: 3 diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml index f469afd..81fb843 100644 --- a/data/registers/rcc_l4.yaml +++ b/data/registers/rcc_l4.yaml @@ -1,1742 +1,1742 @@ +--- block/RCC: description: Reset and clock control items: - - byte_offset: 0 - description: Clock control register - fieldset: CR - name: CR - - byte_offset: 4 - description: Internal clock sources calibration register - fieldset: ICSCR - name: ICSCR - - byte_offset: 8 - description: Clock configuration register - fieldset: CFGR - name: CFGR - - byte_offset: 12 - description: PLL configuration register - fieldset: PLLCFGR - name: PLLCFGR - - byte_offset: 16 - description: PLLSAI1 configuration register - fieldset: PLLSAI1CFGR - name: PLLSAI1CFGR - - byte_offset: 20 - description: PLLSAI2 configuration register - fieldset: PLLSAI2CFGR - name: PLLSAI2CFGR - - byte_offset: 24 - description: Clock interrupt enable register - fieldset: CIER - name: CIER - - access: Read - byte_offset: 28 - description: Clock interrupt flag register - fieldset: CIFR - name: CIFR - - access: Write - byte_offset: 32 - description: Clock interrupt clear register - fieldset: CICR - name: CICR - - byte_offset: 40 - description: AHB1 peripheral reset register - fieldset: AHB1RSTR - name: AHB1RSTR - - byte_offset: 44 - description: AHB2 peripheral reset register - fieldset: AHB2RSTR - name: AHB2RSTR - - byte_offset: 48 - description: AHB3 peripheral reset register - fieldset: AHB3RSTR - name: AHB3RSTR - - byte_offset: 56 - description: APB1 peripheral reset register 1 - fieldset: APB1RSTR1 - name: APB1RSTR1 - - byte_offset: 60 - description: APB1 peripheral reset register 2 - fieldset: APB1RSTR2 - name: APB1RSTR2 - - byte_offset: 64 - description: APB2 peripheral reset register - fieldset: APB2RSTR - name: APB2RSTR - - byte_offset: 72 - description: AHB1 peripheral clock enable register - fieldset: AHB1ENR - name: AHB1ENR - - byte_offset: 76 - description: AHB2 peripheral clock enable register - fieldset: AHB2ENR - name: AHB2ENR - - byte_offset: 80 - description: AHB3 peripheral clock enable register - fieldset: AHB3ENR - name: AHB3ENR - - byte_offset: 88 - description: APB1ENR1 - fieldset: APB1ENR1 - name: APB1ENR1 - - byte_offset: 92 - description: APB1 peripheral clock enable register 2 - fieldset: APB1ENR2 - name: APB1ENR2 - - byte_offset: 96 - description: APB2ENR - fieldset: APB2ENR - name: APB2ENR - - byte_offset: 104 - description: AHB1 peripheral clocks enable in Sleep and Stop modes register - fieldset: AHB1SMENR - name: AHB1SMENR - - byte_offset: 108 - description: AHB2 peripheral clocks enable in Sleep and Stop modes register - fieldset: AHB2SMENR - name: AHB2SMENR - - byte_offset: 112 - description: AHB3 peripheral clocks enable in Sleep and Stop modes register - fieldset: AHB3SMENR - name: AHB3SMENR - - byte_offset: 120 - description: APB1SMENR1 - fieldset: APB1SMENR1 - name: APB1SMENR1 - - byte_offset: 124 - description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 - fieldset: APB1SMENR2 - name: APB1SMENR2 - - byte_offset: 128 - description: APB2SMENR - fieldset: APB2SMENR - name: APB2SMENR - - byte_offset: 136 - description: CCIPR - fieldset: CCIPR - name: CCIPR - - byte_offset: 144 - description: BDCR - fieldset: BDCR - name: BDCR - - byte_offset: 148 - description: CSR - fieldset: CSR - name: CSR - - byte_offset: 152 - description: Clock recovery RC register - fieldset: CRRCR - name: CRRCR - - byte_offset: 156 - description: Peripherals independent clock configuration register - fieldset: CCIPR2 - name: CCIPR2 -enum/MSIRANGE: - bit_size: 4 - variants: - - description: range 0 around 100 kHz - name: Range100K - value: 0 - - description: range 1 around 200 kHz - name: Range200K - value: 1 - - description: range 2 around 400 kHz - name: Range400K - value: 2 - - description: range 3 around 800 kHz - name: Range800K - value: 3 - - description: range 4 around 1 MHz - name: Range1M - value: 4 - - description: range 5 around 2 MHz - name: Range2M - value: 5 - - description: range 6 around 4 MHz - name: Range4M - value: 6 - - description: range 7 around 8 MHz - name: Range8M - value: 7 - - description: range 8 around 16 MHz - name: Range16M - value: 8 - - description: range 9 around 24 MHz - name: Range24M - value: 9 - - description: range 10 around 32 MHz - name: Range32M - value: 10 - - description: range 11 around 48 MHz - name: Range48M - value: 11 + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 12 + fieldset: PLLCFGR + - name: PLLSAI1CFGR + description: PLLSAI1 configuration register + byte_offset: 16 + fieldset: PLLSAI1CFGR + - name: PLLSAI2CFGR + description: PLLSAI2 configuration register + byte_offset: 20 + fieldset: PLLSAI2CFGR + - name: CIER + description: Clock interrupt enable register + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 28 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 32 + access: Write + fieldset: CICR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 40 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 44 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 48 + fieldset: AHB3RSTR + - name: APB1RSTR1 + description: APB1 peripheral reset register 1 + byte_offset: 56 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: APB1 peripheral reset register 2 + byte_offset: 60 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 64 + fieldset: APB2RSTR + - name: AHB1ENR + description: AHB1 peripheral clock enable register + byte_offset: 72 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 76 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 80 + fieldset: AHB3ENR + - name: APB1ENR1 + description: APB1ENR1 + byte_offset: 88 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: APB1 peripheral clock enable register 2 + byte_offset: 92 + fieldset: APB1ENR2 + - name: APB2ENR + description: APB2ENR + byte_offset: 96 + fieldset: APB2ENR + - name: AHB1SMENR + description: AHB1 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 104 + fieldset: AHB1SMENR + - name: AHB2SMENR + description: AHB2 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 108 + fieldset: AHB2SMENR + - name: AHB3SMENR + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 112 + fieldset: AHB3SMENR + - name: APB1SMENR1 + description: APB1SMENR1 + byte_offset: 120 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 + byte_offset: 124 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: APB2SMENR + byte_offset: 128 + fieldset: APB2SMENR + - name: CCIPR + description: CCIPR + byte_offset: 136 + fieldset: CCIPR + - name: BDCR + description: BDCR + byte_offset: 144 + fieldset: BDCR + - name: CSR + description: CSR + byte_offset: 148 + fieldset: CSR + - name: CRRCR + description: Clock recovery RC register + byte_offset: 152 + fieldset: CRRCR + - name: CCIPR2 + description: Peripherals independent clock configuration register + byte_offset: 156 + fieldset: CCIPR2 fieldset/AHB1ENR: description: AHB1 peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA1 clock enable - name: DMA1EN - - bit_offset: 1 - bit_size: 1 - description: DMA2 clock enable - name: DMA2EN - - bit_offset: 2 - bit_size: 1 - description: DMAMUX clock enable - name: DMAMUX1EN - - bit_offset: 8 - bit_size: 1 - description: Flash memory interface clock enable - name: FLASHEN - - bit_offset: 12 - bit_size: 1 - description: CRC clock enable - name: CRCEN - - bit_offset: 16 - bit_size: 1 - description: Touch Sensing Controller clock enable - name: TSCEN - - bit_offset: 17 - bit_size: 1 - description: DMA2D clock enable - name: DMA2DEN - - bit_offset: 18 - bit_size: 1 - description: Graphic MMU clock enable - name: GFXMMUEN + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1EN + description: DMAMUX clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: Flash memory interface clock enable + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: TSCEN + description: Touch Sensing Controller clock enable + bit_offset: 16 + bit_size: 1 + - name: DMA2DEN + description: DMA2D clock enable + bit_offset: 17 + bit_size: 1 + - name: GFXMMUEN + description: Graphic MMU clock enable + bit_offset: 18 + bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA1 reset - name: DMA1RST - - bit_offset: 1 - bit_size: 1 - description: DMA2 reset - name: DMA2RST - - bit_offset: 2 - bit_size: 1 - description: DMAMUXRST - name: DMAMUX1RST - - bit_offset: 8 - bit_size: 1 - description: Flash memory interface reset - name: FLASHRST - - bit_offset: 12 - bit_size: 1 - description: CRC reset - name: CRCRST - - bit_offset: 16 - bit_size: 1 - description: Touch Sensing Controller reset - name: TSCRST - - bit_offset: 17 - bit_size: 1 - description: DMA2D reset - name: DMA2DRST - - bit_offset: 18 - bit_size: 1 - description: GFXMMU reset - name: GFXMMURST + - name: DMA1RST + description: DMA1 reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1RST + description: DMAMUXRST + bit_offset: 2 + bit_size: 1 + - name: FLASHRST + description: Flash memory interface reset + bit_offset: 8 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: TSCRST + description: Touch Sensing Controller reset + bit_offset: 16 + bit_size: 1 + - name: DMA2DRST + description: DMA2D reset + bit_offset: 17 + bit_size: 1 + - name: GFXMMURST + description: GFXMMU reset + bit_offset: 18 + bit_size: 1 fieldset/AHB1SMENR: description: AHB1 peripheral clocks enable in Sleep and Stop modes register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA1 clocks enable during Sleep and Stop modes - name: DMA1SMEN - - bit_offset: 1 - bit_size: 1 - description: DMA2 clocks enable during Sleep and Stop modes - name: DMA2SMEN - - bit_offset: 2 - bit_size: 1 - description: DMAMUX clock enable during Sleep and Stop modes - name: DMAMUX1SMEN - - bit_offset: 8 - bit_size: 1 - description: Flash memory interface clocks enable during Sleep and Stop modes - name: FLASHSMEN - - bit_offset: 9 - bit_size: 1 - description: SRAM1 interface clocks enable during Sleep and Stop modes - name: SRAM1SMEN - - bit_offset: 12 - bit_size: 1 - description: CRCSMEN - name: CRCSMEN - - bit_offset: 16 - bit_size: 1 - description: Touch Sensing Controller clocks enable during Sleep and Stop modes - name: TSCSMEN - - bit_offset: 17 - bit_size: 1 - description: DMA2D clock enable during Sleep and Stop modes - name: DMA2DSMEN - - bit_offset: 18 - bit_size: 1 - description: GFXMMU clock enable during Sleep and Stop modes - name: GFXMMUSMEN + - name: DMA1SMEN + description: DMA1 clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: DMA2 clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: DMAMUX clock enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: FLASHSMEN + description: Flash memory interface clocks enable during Sleep and Stop modes + bit_offset: 8 + bit_size: 1 + - name: SRAM1SMEN + description: SRAM1 interface clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 + - name: CRCSMEN + description: CRCSMEN + bit_offset: 12 + bit_size: 1 + - name: TSCSMEN + description: Touch Sensing Controller clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 + - name: DMA2DSMEN + description: DMA2D clock enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: GFXMMUSMEN + description: GFXMMU clock enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: IO port A clock enable - name: GPIOAEN - - bit_offset: 1 - bit_size: 1 - description: IO port B clock enable - name: GPIOBEN - - bit_offset: 2 - bit_size: 1 - description: IO port C clock enable - name: GPIOCEN - - bit_offset: 3 - bit_size: 1 - description: IO port D clock enable - name: GPIODEN - - bit_offset: 4 - bit_size: 1 - description: IO port E clock enable - name: GPIOEEN - - bit_offset: 5 - bit_size: 1 - description: IO port F clock enable - name: GPIOFEN - - bit_offset: 6 - bit_size: 1 - description: IO port G clock enable - name: GPIOGEN - - bit_offset: 7 - bit_size: 1 - description: IO port H clock enable - name: GPIOHEN - - bit_offset: 8 - bit_size: 1 - description: IO port I clock enable - name: GPIOIEN - - bit_offset: 12 - bit_size: 1 - description: OTG full speed clock enable - name: OTGFSEN - - bit_offset: 13 - bit_size: 1 - description: ADC clock enable - name: ADCEN - - bit_offset: 14 - bit_size: 1 - description: DCMI clock enable - name: DCMIEN - - bit_offset: 16 - bit_size: 1 - description: AES accelerator clock enable - name: AESEN - - bit_offset: 17 - bit_size: 1 - description: HASH clock enable - name: HASHEN - - bit_offset: 18 - bit_size: 1 - description: Random Number Generator clock enable - name: RNGEN - - bit_offset: 20 - bit_size: 1 - description: OctoSPI IO manager clock enable - name: OSPIMEN - - bit_offset: 22 - bit_size: 1 - description: SDMMC1 clock enable - name: SDMMC1EN + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: IO port F clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: IO port I clock enable + bit_offset: 8 + bit_size: 1 + - name: OTGFSEN + description: OTG full speed clock enable + bit_offset: 12 + bit_size: 1 + - name: ADCEN + description: ADC clock enable + bit_offset: 13 + bit_size: 1 + - name: DCMIEN + description: DCMI clock enable + bit_offset: 14 + bit_size: 1 + - name: AESEN + description: AES accelerator clock enable + bit_offset: 16 + bit_size: 1 + - name: HASHEN + description: HASH clock enable + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: Random Number Generator clock enable + bit_offset: 18 + bit_size: 1 + - name: OSPIMEN + description: OctoSPI IO manager clock enable + bit_offset: 20 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 clock enable + bit_offset: 22 + bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: IO port A reset - name: GPIOARST - - bit_offset: 1 - bit_size: 1 - description: IO port B reset - name: GPIOBRST - - bit_offset: 2 - bit_size: 1 - description: IO port C reset - name: GPIOCRST - - bit_offset: 3 - bit_size: 1 - description: IO port D reset - name: GPIODRST - - bit_offset: 4 - bit_size: 1 - description: IO port E reset - name: GPIOERST - - bit_offset: 5 - bit_size: 1 - description: IO port F reset - name: GPIOFRST - - bit_offset: 6 - bit_size: 1 - description: IO port G reset - name: GPIOGRST - - bit_offset: 7 - bit_size: 1 - description: IO port H reset - name: GPIOHRST - - bit_offset: 8 - bit_size: 1 - description: IO port I reset - name: GPIOIRST - - bit_offset: 12 - bit_size: 1 - description: USB OTG FS reset - name: OTGFSRST - - bit_offset: 13 - bit_size: 1 - description: ADC reset - name: ADCRST - - bit_offset: 14 - bit_size: 1 - description: Digital Camera Interface reset - name: DCMIRST - - bit_offset: 16 - bit_size: 1 - description: AES hardware accelerator reset - name: AESRST - - bit_offset: 17 - bit_size: 1 - description: Hash reset - name: HASHRST - - bit_offset: 18 - bit_size: 1 - description: Random number generator reset - name: RNGRST - - bit_offset: 20 - bit_size: 1 - description: OCTOSPI IO manager reset - name: OSPIMRST - - bit_offset: 22 - bit_size: 1 - description: SDMMC1 reset - name: SDMMC1RST + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 + - name: GPIOIRST + description: IO port I reset + bit_offset: 8 + bit_size: 1 + - name: OTGFSRST + description: USB OTG FS reset + bit_offset: 12 + bit_size: 1 + - name: ADCRST + description: ADC reset + bit_offset: 13 + bit_size: 1 + - name: DCMIRST + description: Digital Camera Interface reset + bit_offset: 14 + bit_size: 1 + - name: AESRST + description: AES hardware accelerator reset + bit_offset: 16 + bit_size: 1 + - name: HASHRST + description: Hash reset + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: Random number generator reset + bit_offset: 18 + bit_size: 1 + - name: OSPIMRST + description: OCTOSPI IO manager reset + bit_offset: 20 + bit_size: 1 + - name: SDMMC1RST + description: SDMMC1 reset + bit_offset: 22 + bit_size: 1 fieldset/AHB2SMENR: description: AHB2 peripheral clocks enable in Sleep and Stop modes register fields: - - bit_offset: 0 - bit_size: 1 - description: IO port A clocks enable during Sleep and Stop modes - name: GPIOASMEN - - bit_offset: 1 - bit_size: 1 - description: IO port B clocks enable during Sleep and Stop modes - name: GPIOBSMEN - - bit_offset: 2 - bit_size: 1 - description: IO port C clocks enable during Sleep and Stop modes - name: GPIOCSMEN - - bit_offset: 3 - bit_size: 1 - description: IO port D clocks enable during Sleep and Stop modes - name: GPIODSMEN - - bit_offset: 4 - bit_size: 1 - description: IO port E clocks enable during Sleep and Stop modes - name: GPIOESMEN - - bit_offset: 5 - bit_size: 1 - description: IO port F clocks enable during Sleep and Stop modes - name: GPIOFSMEN - - bit_offset: 6 - bit_size: 1 - description: IO port G clocks enable during Sleep and Stop modes - name: GPIOGSMEN - - bit_offset: 7 - bit_size: 1 - description: IO port H clocks enable during Sleep and Stop modes - name: GPIOHSMEN - - bit_offset: 8 - bit_size: 1 - description: IO port I clocks enable during Sleep and Stop modes - name: GPIOISMEN - - bit_offset: 9 - bit_size: 1 - description: SRAM2 interface clocks enable during Sleep and Stop modes - name: SRAM2SMEN - - bit_offset: 10 - bit_size: 1 - description: SRAM2 interface clocks enable during Sleep and Stop modes - name: SRAM3SMEN - - bit_offset: 12 - bit_size: 1 - description: OTG full speed clocks enable during Sleep and Stop modes - name: OTGFSSMEN - - bit_offset: 13 - bit_size: 1 - description: ADC clocks enable during Sleep and Stop modes - name: ADCFSSMEN - - bit_offset: 14 - bit_size: 1 - description: DCMI clock enable during Sleep and Stop modes - name: DCMISMEN - - bit_offset: 16 - bit_size: 1 - description: AES accelerator clocks enable during Sleep and Stop modes - name: AESSMEN - - bit_offset: 17 - bit_size: 1 - description: HASH clock enable during Sleep and Stop modes - name: HASHSMEN - - bit_offset: 17 - bit_size: 1 - description: HASH clock enable during Sleep and Stop modes - name: HASH1SMEN - - bit_offset: 18 - bit_size: 1 - description: Random Number Generator clocks enable during Sleep and Stop modes - name: RNGSMEN - - bit_offset: 20 - bit_size: 1 - description: OctoSPI IO manager clocks enable during Sleep and Stop modes - name: OSPIMSMEN - - bit_offset: 22 - bit_size: 1 - description: SDMMC1 clocks enable during Sleep and Stop modes - name: SDMMC1SMEN + - name: GPIOASMEN + description: IO port A clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: IO port B clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: IO port C clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: GPIODSMEN + description: IO port D clocks enable during Sleep and Stop modes + bit_offset: 3 + bit_size: 1 + - name: GPIOESMEN + description: IO port E clocks enable during Sleep and Stop modes + bit_offset: 4 + bit_size: 1 + - name: GPIOFSMEN + description: IO port F clocks enable during Sleep and Stop modes + bit_offset: 5 + bit_size: 1 + - name: GPIOGSMEN + description: IO port G clocks enable during Sleep and Stop modes + bit_offset: 6 + bit_size: 1 + - name: GPIOHSMEN + description: IO port H clocks enable during Sleep and Stop modes + bit_offset: 7 + bit_size: 1 + - name: GPIOISMEN + description: IO port I clocks enable during Sleep and Stop modes + bit_offset: 8 + bit_size: 1 + - name: SRAM2SMEN + description: SRAM2 interface clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 + - name: SRAM3SMEN + description: SRAM2 interface clocks enable during Sleep and Stop modes + bit_offset: 10 + bit_size: 1 + - name: OTGFSSMEN + description: OTG full speed clocks enable during Sleep and Stop modes + bit_offset: 12 + bit_size: 1 + - name: ADCFSSMEN + description: ADC clocks enable during Sleep and Stop modes + bit_offset: 13 + bit_size: 1 + - name: DCMISMEN + description: DCMI clock enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: AESSMEN + description: AES accelerator clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 + - name: HASHSMEN + description: HASH clock enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: HASH1SMEN + description: HASH clock enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: Random Number Generator clocks enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 + - name: OSPIMSMEN + description: OctoSPI IO manager clocks enable during Sleep and Stop modes + bit_offset: 20 + bit_size: 1 + - name: SDMMC1SMEN + description: SDMMC1 clocks enable during Sleep and Stop modes + bit_offset: 22 + bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - - bit_offset: 0 - bit_size: 1 - description: Flexible memory controller clock enable - name: FMCEN - - bit_offset: 8 - bit_size: 1 - description: QSPIEN - name: QSPIEN - - bit_offset: 9 - bit_size: 1 - description: OSPI2EN memory interface clock enable - name: OSPI2EN + - name: FMCEN + description: Flexible memory controller clock enable + bit_offset: 0 + bit_size: 1 + - name: QSPIEN + description: QSPIEN + bit_offset: 8 + bit_size: 1 + - name: OSPI2EN + description: OSPI2EN memory interface clock enable + bit_offset: 9 + bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: Flexible memory controller reset - name: FMCRST - - bit_offset: 8 - bit_size: 1 - description: Quad SPI memory interface reset - name: QSPIRST - - bit_offset: 9 - bit_size: 1 - description: OctOSPI2 memory interface reset - name: OSPI2RST + - name: FMCRST + description: Flexible memory controller reset + bit_offset: 0 + bit_size: 1 + - name: QSPIRST + description: Quad SPI memory interface reset + bit_offset: 8 + bit_size: 1 + - name: OSPI2RST + description: OctOSPI2 memory interface reset + bit_offset: 9 + bit_size: 1 fieldset/AHB3SMENR: description: AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - - bit_offset: 0 - bit_size: 1 - description: Flexible memory controller clocks enable during Sleep and Stop modes - name: FMCSMEN - - bit_offset: 8 - bit_size: 1 - description: QSPISMEN - name: QSPISMEN - - bit_offset: 9 - bit_size: 1 - description: OctoSPI2 memory interface clocks enable during Sleep and Stop modes - name: OCTOSPI2 + - name: FMCSMEN + description: Flexible memory controller clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: QSPISMEN + description: QSPISMEN + bit_offset: 8 + bit_size: 1 + - name: OCTOSPI2 + description: OctoSPI2 memory interface clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 fieldset/APB1ENR1: description: APB1ENR1 fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 timer clock enable - name: TIM2EN - - bit_offset: 1 - bit_size: 1 - description: TIM3 timer clock enable - name: TIM3EN - - bit_offset: 2 - bit_size: 1 - description: TIM4 timer clock enable - name: TIM4EN - - bit_offset: 3 - bit_size: 1 - description: TIM5 timer clock enable - name: TIM5EN - - bit_offset: 4 - bit_size: 1 - description: TIM6 timer clock enable - name: TIM6EN - - bit_offset: 5 - bit_size: 1 - description: TIM7 timer clock enable - name: TIM7EN - - bit_offset: 9 - bit_size: 1 - description: LCD clock enable - name: LCDEN - - bit_offset: 10 - bit_size: 1 - description: RTC APB clock enable - name: RTCAPBEN - - bit_offset: 11 - bit_size: 1 - description: Window watchdog clock enable - name: WWDGEN - - bit_offset: 14 - bit_size: 1 - description: SPI2 clock enable - name: SPI2EN - - bit_offset: 15 - bit_size: 1 - description: SPI3 clock enable - name: SPI3EN - - bit_offset: 17 - bit_size: 1 - description: USART2 clock enable - name: USART2EN - - bit_offset: 18 - bit_size: 1 - description: USART3 clock enable - name: USART3EN - - bit_offset: 19 - bit_size: 1 - description: UART4 clock enable - name: UART4EN - - bit_offset: 20 - bit_size: 1 - description: UART5 clock enable - name: UART5EN - - bit_offset: 21 - bit_size: 1 - description: I2C1 clock enable - name: I2C1EN - - bit_offset: 22 - bit_size: 1 - description: I2C2 clock enable - name: I2C2EN - - bit_offset: 23 - bit_size: 1 - description: I2C3 clock enable - name: I2C3EN - - bit_offset: 24 - bit_size: 1 - description: Clock Recovery System clock enable - name: CRSEN - - bit_offset: 25 - bit_size: 1 - description: CAN1 clock enable - name: CAN1EN - - bit_offset: 26 - bit_size: 1 - description: USB FS clock enable - name: USBFSEN - - bit_offset: 26 - bit_size: 1 - description: CAN2 clock enable - name: CAN2EN - - bit_offset: 28 - bit_size: 1 - description: Power interface clock enable - name: PWREN - - bit_offset: 29 - bit_size: 1 - description: DAC1 interface clock enable - name: DAC1EN - - bit_offset: 30 - bit_size: 1 - description: OPAMP interface clock enable - name: OPAMPEN - - bit_offset: 31 - bit_size: 1 - description: Low power timer 1 clock enable - name: LPTIM1EN + - name: TIM2EN + description: TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 timer clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM4 timer clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM5 timer clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM6 timer clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 timer clock enable + bit_offset: 5 + bit_size: 1 + - name: LCDEN + description: LCD clock enable + bit_offset: 9 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 23 + bit_size: 1 + - name: CRSEN + description: Clock Recovery System clock enable + bit_offset: 24 + bit_size: 1 + - name: CAN1EN + description: CAN1 clock enable + bit_offset: 25 + bit_size: 1 + - name: USBFSEN + description: USB FS clock enable + bit_offset: 26 + bit_size: 1 + - name: CAN2EN + description: CAN2 clock enable + bit_offset: 26 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DAC1EN + description: DAC1 interface clock enable + bit_offset: 29 + bit_size: 1 + - name: OPAMPEN + description: OPAMP interface clock enable + bit_offset: 30 + bit_size: 1 + - name: LPTIM1EN + description: Low power timer 1 clock enable + bit_offset: 31 + bit_size: 1 fieldset/APB1ENR2: description: APB1 peripheral clock enable register 2 fields: - - bit_offset: 0 - bit_size: 1 - description: Low power UART 1 clock enable - name: LPUART1EN - - bit_offset: 1 - bit_size: 1 - description: I2C4 clock enable - name: I2C4EN - - bit_offset: 2 - bit_size: 1 - description: Single wire protocol clock enable - name: SWPMI1EN - - bit_offset: 5 - bit_size: 1 - description: LPTIM2EN - name: LPTIM2EN - - bit_offset: 24 - bit_size: 1 - description: DFSDMEN enable - name: DFSDMEN + - name: LPUART1EN + description: Low power UART 1 clock enable + bit_offset: 0 + bit_size: 1 + - name: I2C4EN + description: I2C4 clock enable + bit_offset: 1 + bit_size: 1 + - name: SWPMI1EN + description: Single wire protocol clock enable + bit_offset: 2 + bit_size: 1 + - name: LPTIM2EN + description: LPTIM2EN + bit_offset: 5 + bit_size: 1 + - name: DFSDMEN + description: DFSDMEN enable + bit_offset: 24 + bit_size: 1 fieldset/APB1RSTR1: description: APB1 peripheral reset register 1 fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 timer reset - name: TIM2RST - - bit_offset: 1 - bit_size: 1 - description: TIM3 timer reset - name: TIM3RST - - bit_offset: 2 - bit_size: 1 - description: TIM3 timer reset - name: TIM4RST - - bit_offset: 3 - bit_size: 1 - description: TIM5 timer reset - name: TIM5RST - - bit_offset: 4 - bit_size: 1 - description: TIM6 timer reset - name: TIM6RST - - bit_offset: 5 - bit_size: 1 - description: TIM7 timer reset - name: TIM7RST - - bit_offset: 9 - bit_size: 1 - description: LCD interface reset - name: LCDRST - - bit_offset: 14 - bit_size: 1 - description: SPI2 reset - name: SPI2RST - - bit_offset: 15 - bit_size: 1 - description: SPI3 reset - name: SPI3RST - - bit_offset: 17 - bit_size: 1 - description: USART2 reset - name: USART2RST - - bit_offset: 18 - bit_size: 1 - description: USART3 reset - name: USART3RST - - bit_offset: 19 - bit_size: 1 - description: UART4 reset - name: UART4RST - - bit_offset: 20 - bit_size: 1 - description: UART5 reset - name: UART5RST - - bit_offset: 21 - bit_size: 1 - description: I2C1 reset - name: I2C1RST - - bit_offset: 22 - bit_size: 1 - description: I2C2 reset - name: I2C2RST - - bit_offset: 23 - bit_size: 1 - description: I2C3 reset - name: I2C3RST - - bit_offset: 24 - bit_size: 1 - description: CRS reset - name: CRSRST - - bit_offset: 25 - bit_size: 1 - description: CAN1 reset - name: CAN1RST - - bit_offset: 26 - bit_size: 1 - description: USB FS reset - name: USBFSRST - - bit_offset: 26 - bit_size: 1 - description: CAN2 reset - name: CAN2RST - - bit_offset: 28 - bit_size: 1 - description: Power interface reset - name: PWRRST - - bit_offset: 29 - bit_size: 1 - description: DAC1 interface reset - name: DAC1RST - - bit_offset: 30 - bit_size: 1 - description: OPAMP interface reset - name: OPAMPRST - - bit_offset: 31 - bit_size: 1 - description: Low Power Timer 1 reset - name: LPTIM1RST + - name: TIM2RST + description: TIM2 timer reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 timer reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM3 timer reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM5 timer reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM6 timer reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 timer reset + bit_offset: 5 + bit_size: 1 + - name: LCDRST + description: LCD interface reset + bit_offset: 9 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: CRSRST + description: CRS reset + bit_offset: 24 + bit_size: 1 + - name: CAN1RST + description: CAN1 reset + bit_offset: 25 + bit_size: 1 + - name: USBFSRST + description: USB FS reset + bit_offset: 26 + bit_size: 1 + - name: CAN2RST + description: CAN2 reset + bit_offset: 26 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DAC1RST + description: DAC1 interface reset + bit_offset: 29 + bit_size: 1 + - name: OPAMPRST + description: OPAMP interface reset + bit_offset: 30 + bit_size: 1 + - name: LPTIM1RST + description: Low Power Timer 1 reset + bit_offset: 31 + bit_size: 1 fieldset/APB1RSTR2: description: APB1 peripheral reset register 2 fields: - - bit_offset: 0 - bit_size: 1 - description: Low-power UART 1 reset - name: LPUART1RST - - bit_offset: 1 - bit_size: 1 - description: I2C4 reset - name: I2C4RST - - bit_offset: 2 - bit_size: 1 - description: Single wire protocol reset - name: SWPMI1RST - - bit_offset: 5 - bit_size: 1 - description: Low-power timer 2 reset - name: LPTIM2RST + - name: LPUART1RST + description: Low-power UART 1 reset + bit_offset: 0 + bit_size: 1 + - name: I2C4RST + description: I2C4 reset + bit_offset: 1 + bit_size: 1 + - name: SWPMI1RST + description: Single wire protocol reset + bit_offset: 2 + bit_size: 1 + - name: LPTIM2RST + description: Low-power timer 2 reset + bit_offset: 5 + bit_size: 1 fieldset/APB1SMENR1: description: APB1SMENR1 fields: - - bit_offset: 0 - bit_size: 1 - description: TIM2 timer clocks enable during Sleep and Stop modes - name: TIM2SMEN - - bit_offset: 1 - bit_size: 1 - description: TIM3 timer clocks enable during Sleep and Stop modes - name: TIM3SMEN - - bit_offset: 2 - bit_size: 1 - description: TIM4 timer clocks enable during Sleep and Stop modes - name: TIM4SMEN - - bit_offset: 3 - bit_size: 1 - description: TIM5 timer clocks enable during Sleep and Stop modes - name: TIM5SMEN - - bit_offset: 4 - bit_size: 1 - description: TIM6 timer clocks enable during Sleep and Stop modes - name: TIM6SMEN - - bit_offset: 5 - bit_size: 1 - description: TIM7 timer clocks enable during Sleep and Stop modes - name: TIM7SMEN - - bit_offset: 9 - bit_size: 1 - description: LCD clocks enable during Sleep and Stop modes - name: LCDSMEN - - bit_offset: 10 - bit_size: 1 - description: RTC APB clock enable during Sleep and Stop modes - name: RTCAPBSMEN - - bit_offset: 11 - bit_size: 1 - description: Window watchdog clocks enable during Sleep and Stop modes - name: WWDGSMEN - - bit_offset: 14 - bit_size: 1 - description: SPI2 clocks enable during Sleep and Stop modes - name: SPI2SMEN - - bit_offset: 15 - bit_size: 1 - description: SPI3 clocks enable during Sleep and Stop modes - name: SP3SMEN - - bit_offset: 17 - bit_size: 1 - description: USART2 clocks enable during Sleep and Stop modes - name: USART2SMEN - - bit_offset: 18 - bit_size: 1 - description: USART3 clocks enable during Sleep and Stop modes - name: USART3SMEN - - bit_offset: 19 - bit_size: 1 - description: UART4 clocks enable during Sleep and Stop modes - name: UART4SMEN - - bit_offset: 20 - bit_size: 1 - description: UART5 clocks enable during Sleep and Stop modes - name: UART5SMEN - - bit_offset: 21 - bit_size: 1 - description: I2C1 clocks enable during Sleep and Stop modes - name: I2C1SMEN - - bit_offset: 22 - bit_size: 1 - description: I2C2 clocks enable during Sleep and Stop modes - name: I2C2SMEN - - bit_offset: 23 - bit_size: 1 - description: I2C3 clocks enable during Sleep and Stop modes - name: I2C3SMEN - - bit_offset: 24 - bit_size: 1 - description: CRS clock enable during Sleep and Stop modes - name: CRSSMEN - - bit_offset: 25 - bit_size: 1 - description: CAN1 clocks enable during Sleep and Stop modes - name: CAN1SMEN - - bit_offset: 26 - bit_size: 1 - description: USB FS clock enable during Sleep and Stop modes - name: USBFSSMEN - - bit_offset: 26 - bit_size: 1 - description: CAN2 clocks enable during Sleep and Stop modes - name: CAN2SMEN - - bit_offset: 28 - bit_size: 1 - description: Power interface clocks enable during Sleep and Stop modes - name: PWRSMEN - - bit_offset: 29 - bit_size: 1 - description: DAC1 interface clocks enable during Sleep and Stop modes - name: DAC1SMEN - - bit_offset: 30 - bit_size: 1 - description: OPAMP interface clocks enable during Sleep and Stop modes - name: OPAMPSMEN - - bit_offset: 31 - bit_size: 1 - description: Low power timer 1 clocks enable during Sleep and Stop modes - name: LPTIM1SMEN + - name: TIM2SMEN + description: TIM2 timer clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: TIM3 timer clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: TIM4SMEN + description: TIM4 timer clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: TIM5SMEN + description: TIM5 timer clocks enable during Sleep and Stop modes + bit_offset: 3 + bit_size: 1 + - name: TIM6SMEN + description: TIM6 timer clocks enable during Sleep and Stop modes + bit_offset: 4 + bit_size: 1 + - name: TIM7SMEN + description: TIM7 timer clocks enable during Sleep and Stop modes + bit_offset: 5 + bit_size: 1 + - name: LCDSMEN + description: LCD clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC APB clock enable during Sleep and Stop modes + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: Window watchdog clocks enable during Sleep and Stop modes + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clocks enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: SP3SMEN + description: SPI3 clocks enable during Sleep and Stop modes + bit_offset: 15 + bit_size: 1 + - name: USART2SMEN + description: USART2 clocks enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: USART3SMEN + description: USART3 clocks enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 + - name: UART4SMEN + description: UART4 clocks enable during Sleep and Stop modes + bit_offset: 19 + bit_size: 1 + - name: UART5SMEN + description: UART5 clocks enable during Sleep and Stop modes + bit_offset: 20 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clocks enable during Sleep and Stop modes + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clocks enable during Sleep and Stop modes + bit_offset: 22 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clocks enable during Sleep and Stop modes + bit_offset: 23 + bit_size: 1 + - name: CRSSMEN + description: CRS clock enable during Sleep and Stop modes + bit_offset: 24 + bit_size: 1 + - name: CAN1SMEN + description: CAN1 clocks enable during Sleep and Stop modes + bit_offset: 25 + bit_size: 1 + - name: USBFSSMEN + description: USB FS clock enable during Sleep and Stop modes + bit_offset: 26 + bit_size: 1 + - name: CAN2SMEN + description: CAN2 clocks enable during Sleep and Stop modes + bit_offset: 26 + bit_size: 1 + - name: PWRSMEN + description: Power interface clocks enable during Sleep and Stop modes + bit_offset: 28 + bit_size: 1 + - name: DAC1SMEN + description: DAC1 interface clocks enable during Sleep and Stop modes + bit_offset: 29 + bit_size: 1 + - name: OPAMPSMEN + description: OPAMP interface clocks enable during Sleep and Stop modes + bit_offset: 30 + bit_size: 1 + - name: LPTIM1SMEN + description: Low power timer 1 clocks enable during Sleep and Stop modes + bit_offset: 31 + bit_size: 1 fieldset/APB1SMENR2: description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 fields: - - bit_offset: 0 - bit_size: 1 - description: Low power UART 1 clocks enable during Sleep and Stop modes - name: LPUART1SMEN - - bit_offset: 1 - bit_size: 1 - description: I2C4 clocks enable during Sleep and Stop modes - name: I2C4SMEN - - bit_offset: 2 - bit_size: 1 - description: Single wire protocol clocks enable during Sleep and Stop modes - name: SWPMI1SMEN - - bit_offset: 5 - bit_size: 1 - description: LPTIM2SMEN - name: LPTIM2SMEN + - name: LPUART1SMEN + description: Low power UART 1 clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: I2C4SMEN + description: I2C4 clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: SWPMI1SMEN + description: Single wire protocol clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: LPTIM2SMEN + description: LPTIM2SMEN + bit_offset: 5 + bit_size: 1 fieldset/APB2ENR: description: APB2ENR fields: - - bit_offset: 0 - bit_size: 1 - description: SYSCFG clock enable - name: SYSCFGEN - - bit_offset: 7 - bit_size: 1 - description: Firewall clock enable - name: FWEN - - bit_offset: 7 - bit_size: 1 - description: Firewall clock enable - name: FIREWALLEN - - bit_offset: 10 - bit_size: 1 - description: SDMMC clock enable - name: SDMMCEN - - bit_offset: 11 - bit_size: 1 - description: TIM1 timer clock enable - name: TIM1EN - - bit_offset: 12 - bit_size: 1 - description: SPI1 clock enable - name: SPI1EN - - bit_offset: 13 - bit_size: 1 - description: TIM8 timer clock enable - name: TIM8EN - - bit_offset: 14 - bit_size: 1 - description: USART1clock enable - name: USART1EN - - bit_offset: 16 - bit_size: 1 - description: TIM15 timer clock enable - name: TIM15EN - - bit_offset: 17 - bit_size: 1 - description: TIM16 timer clock enable - name: TIM16EN - - bit_offset: 18 - bit_size: 1 - description: TIM17 timer clock enable - name: TIM17EN - - bit_offset: 21 - bit_size: 1 - description: SAI1 clock enable - name: SAI1EN - - bit_offset: 22 - bit_size: 1 - description: SAI2 clock enable - name: SAI2EN - - bit_offset: 24 - bit_size: 1 - description: DFSDM timer clock enable - name: DFSDM1EN - - bit_offset: 24 - bit_size: 1 - description: DFSDM timer clock enable - name: DFSDMEN - - bit_offset: 26 - bit_size: 1 - description: LCD-TFT clock enable - name: LTDCEN - - bit_offset: 27 - bit_size: 1 - description: DSI clock enable - name: DSIEN + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: FWEN + description: Firewall clock enable + bit_offset: 7 + bit_size: 1 + - name: FIREWALLEN + description: Firewall clock enable + bit_offset: 7 + bit_size: 1 + - name: SDMMCEN + description: SDMMC clock enable + bit_offset: 10 + bit_size: 1 + - name: TIM1EN + description: TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: TIM8 timer clock enable + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: USART1clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: SAI1EN + description: SAI1 clock enable + bit_offset: 21 + bit_size: 1 + - name: SAI2EN + description: SAI2 clock enable + bit_offset: 22 + bit_size: 1 + - name: DFSDM1EN + description: DFSDM timer clock enable + bit_offset: 24 + bit_size: 1 + - name: DFSDMEN + description: DFSDM timer clock enable + bit_offset: 24 + bit_size: 1 + - name: LTDCEN + description: LCD-TFT clock enable + bit_offset: 26 + bit_size: 1 + - name: DSIEN + description: DSI clock enable + bit_offset: 27 + bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - - bit_offset: 0 - bit_size: 1 - description: System configuration (SYSCFG) reset - name: SYSCFGRST - - bit_offset: 10 - bit_size: 1 - description: SDMMC reset - name: SDMMCRST - - bit_offset: 11 - bit_size: 1 - description: TIM1 timer reset - name: TIM1RST - - bit_offset: 12 - bit_size: 1 - description: SPI1 reset - name: SPI1RST - - bit_offset: 13 - bit_size: 1 - description: TIM8 timer reset - name: TIM8RST - - bit_offset: 14 - bit_size: 1 - description: USART1 reset - name: USART1RST - - bit_offset: 16 - bit_size: 1 - description: TIM15 timer reset - name: TIM15RST - - bit_offset: 17 - bit_size: 1 - description: TIM16 timer reset - name: TIM16RST - - bit_offset: 18 - bit_size: 1 - description: TIM17 timer reset - name: TIM17RST - - bit_offset: 21 - bit_size: 1 - description: Serial audio interface 1 (SAI1) reset - name: SAI1RST - - bit_offset: 22 - bit_size: 1 - description: Serial audio interface 2 (SAI2) reset - name: SAI2RST - - bit_offset: 24 - bit_size: 1 - description: Digital filters for sigma-delata modulators (DFSDM) reset - name: DFSDM1RST - - bit_offset: 24 - bit_size: 1 - description: DFSDM filter reset - name: DFSDMRST - - bit_offset: 26 - bit_size: 1 - description: LCD-TFT reset - name: LTDCRST - - bit_offset: 27 - bit_size: 1 - description: DSI reset - name: DSIRST + - name: SYSCFGRST + description: System configuration (SYSCFG) reset + bit_offset: 0 + bit_size: 1 + - name: SDMMCRST + description: SDMMC reset + bit_offset: 10 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1 reset + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: TIM8 timer reset + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: SAI1RST + description: Serial audio interface 1 (SAI1) reset + bit_offset: 21 + bit_size: 1 + - name: SAI2RST + description: Serial audio interface 2 (SAI2) reset + bit_offset: 22 + bit_size: 1 + - name: DFSDM1RST + description: Digital filters for sigma-delata modulators (DFSDM) reset + bit_offset: 24 + bit_size: 1 + - name: DFSDMRST + description: DFSDM filter reset + bit_offset: 24 + bit_size: 1 + - name: LTDCRST + description: LCD-TFT reset + bit_offset: 26 + bit_size: 1 + - name: DSIRST + description: DSI reset + bit_offset: 27 + bit_size: 1 fieldset/APB2SMENR: description: APB2SMENR fields: - - bit_offset: 0 - bit_size: 1 - description: SYSCFG clocks enable during Sleep and Stop modes - name: SYSCFGSMEN - - bit_offset: 10 - bit_size: 1 - description: SDMMC clocks enable during Sleep and Stop modes - name: SDMMCSMEN - - bit_offset: 11 - bit_size: 1 - description: TIM1 timer clocks enable during Sleep and Stop modes - name: TIM1SMEN - - bit_offset: 12 - bit_size: 1 - description: SPI1 clocks enable during Sleep and Stop modes - name: SPI1SMEN - - bit_offset: 13 - bit_size: 1 - description: TIM8 timer clocks enable during Sleep and Stop modes - name: TIM8SMEN - - bit_offset: 14 - bit_size: 1 - description: USART1clocks enable during Sleep and Stop modes - name: USART1SMEN - - bit_offset: 16 - bit_size: 1 - description: TIM15 timer clocks enable during Sleep and Stop modes - name: TIM15SMEN - - bit_offset: 17 - bit_size: 1 - description: TIM16 timer clocks enable during Sleep and Stop modes - name: TIM16SMEN - - bit_offset: 18 - bit_size: 1 - description: TIM17 timer clocks enable during Sleep and Stop modes - name: TIM17SMEN - - bit_offset: 21 - bit_size: 1 - description: SAI1 clocks enable during Sleep and Stop modes - name: SAI1SMEN - - bit_offset: 22 - bit_size: 1 - description: SAI2 clocks enable during Sleep and Stop modes - name: SAI2SMEN - - bit_offset: 24 - bit_size: 1 - description: DFSDM timer clocks enable during Sleep and Stop modes - name: DFSDM1SMEN - - bit_offset: 24 - bit_size: 1 - description: DFSDM timer clocks enable during Sleep and Stop modes - name: DFSDMSMEN - - bit_offset: 26 - bit_size: 1 - description: LCD-TFT timer clocks enable during Sleep and Stop modes - name: LTDCSMEN - - bit_offset: 27 - bit_size: 1 - description: DSI clocks enable during Sleep and Stop modes - name: DSISMEN + - name: SYSCFGSMEN + description: SYSCFG clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: SDMMCSMEN + description: SDMMC clocks enable during Sleep and Stop modes + bit_offset: 10 + bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clocks enable during Sleep and Stop modes + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clocks enable during Sleep and Stop modes + bit_offset: 12 + bit_size: 1 + - name: TIM8SMEN + description: TIM8 timer clocks enable during Sleep and Stop modes + bit_offset: 13 + bit_size: 1 + - name: USART1SMEN + description: USART1clocks enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: TIM15SMEN + description: TIM15 timer clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clocks enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM17 timer clocks enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 + - name: SAI1SMEN + description: SAI1 clocks enable during Sleep and Stop modes + bit_offset: 21 + bit_size: 1 + - name: SAI2SMEN + description: SAI2 clocks enable during Sleep and Stop modes + bit_offset: 22 + bit_size: 1 + - name: DFSDM1SMEN + description: DFSDM timer clocks enable during Sleep and Stop modes + bit_offset: 24 + bit_size: 1 + - name: DFSDMSMEN + description: DFSDM timer clocks enable during Sleep and Stop modes + bit_offset: 24 + bit_size: 1 + - name: LTDCSMEN + description: LCD-TFT timer clocks enable during Sleep and Stop modes + bit_offset: 26 + bit_size: 1 + - name: DSISMEN + description: DSI clocks enable during Sleep and Stop modes + bit_offset: 27 + bit_size: 1 fieldset/BDCR: description: BDCR fields: - - bit_offset: 0 - bit_size: 1 - description: LSE oscillator enable - name: LSEON - - bit_offset: 1 - bit_size: 1 - description: LSE oscillator ready - name: LSERDY - - bit_offset: 2 - bit_size: 1 - description: LSE oscillator bypass - name: LSEBYP - - bit_offset: 3 - bit_size: 2 - description: SE oscillator drive capability - name: LSEDRV - - bit_offset: 5 - bit_size: 1 - description: LSECSSON - name: LSECSSON - - bit_offset: 6 - bit_size: 1 - description: LSECSSD - name: LSECSSD - - bit_offset: 8 - bit_size: 2 - description: RTC clock source selection - name: RTCSEL - - bit_offset: 15 - bit_size: 1 - description: RTC clock enable - name: RTCEN - - bit_offset: 16 - bit_size: 1 - description: Backup domain software reset - name: BDRST - - bit_offset: 24 - bit_size: 1 - description: Low speed clock output enable - name: LSCOEN - - bit_offset: 25 - bit_size: 1 - description: Low speed clock output selection - name: LSCOSEL + - name: LSEON + description: LSE oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: SE oscillator drive capability + bit_offset: 3 + bit_size: 2 + - name: LSECSSON + description: LSECSSON + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: LSECSSD + bit_offset: 6 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: Low speed clock output enable + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: Low speed clock output selection + bit_offset: 25 + bit_size: 1 fieldset/CCIPR: description: CCIPR fields: - - bit_offset: 0 - bit_size: 2 - description: USART1 clock source selection - name: USART1SEL - - bit_offset: 2 - bit_size: 2 - description: USART2 clock source selection - name: USART2SEL - - bit_offset: 4 - bit_size: 2 - description: USART3 clock source selection - name: USART3SEL - - bit_offset: 6 - bit_size: 2 - description: UART4 clock source selection - name: UART4SEL - - bit_offset: 8 - bit_size: 2 - description: UART5 clock source selection - name: UART5SEL - - bit_offset: 10 - bit_size: 2 - description: LPUART1 clock source selection - name: LPUART1SEL - - bit_offset: 12 - bit_size: 2 - description: I2C1 clock source selection - name: I2C1SEL - - bit_offset: 14 - bit_size: 2 - description: I2C2 clock source selection - name: I2C2SEL - - bit_offset: 16 - bit_size: 2 - description: I2C3 clock source selection - name: I2C3SEL - - bit_offset: 18 - bit_size: 2 - description: Low power timer 1 clock source selection - name: LPTIM1SEL - - bit_offset: 20 - bit_size: 2 - description: Low power timer 2 clock source selection - name: LPTIM2SEL - - bit_offset: 22 - bit_size: 2 - description: SAI1 clock source selection - name: SAI1SEL - - bit_offset: 24 - bit_size: 2 - description: SAI2 clock source selection - name: SAI2SEL - - bit_offset: 26 - bit_size: 2 - description: 48 MHz clock source selection - name: CLK48SEL - - bit_offset: 28 - bit_size: 2 - description: ADCs clock source selection - name: ADCSEL - - bit_offset: 30 - bit_size: 1 - description: SWPMI1 clock source selection - name: SWPMI1SEL - - bit_offset: 31 - bit_size: 1 - description: DFSDM clock source selection - name: DFSDMSEL + - name: USART1SEL + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + - name: USART2SEL + description: USART2 clock source selection + bit_offset: 2 + bit_size: 2 + - name: USART3SEL + description: USART3 clock source selection + bit_offset: 4 + bit_size: 2 + - name: UART4SEL + description: UART4 clock source selection + bit_offset: 6 + bit_size: 2 + - name: UART5SEL + description: UART5 clock source selection + bit_offset: 8 + bit_size: 2 + - name: LPUART1SEL + description: LPUART1 clock source selection + bit_offset: 10 + bit_size: 2 + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 12 + bit_size: 2 + - name: I2C2SEL + description: I2C2 clock source selection + bit_offset: 14 + bit_size: 2 + - name: I2C3SEL + description: I2C3 clock source selection + bit_offset: 16 + bit_size: 2 + - name: LPTIM1SEL + description: Low power timer 1 clock source selection + bit_offset: 18 + bit_size: 2 + - name: LPTIM2SEL + description: Low power timer 2 clock source selection + bit_offset: 20 + bit_size: 2 + - name: SAI1SEL + description: SAI1 clock source selection + bit_offset: 22 + bit_size: 2 + - name: SAI2SEL + description: SAI2 clock source selection + bit_offset: 24 + bit_size: 2 + - name: CLK48SEL + description: 48 MHz clock source selection + bit_offset: 26 + bit_size: 2 + - name: ADCSEL + description: ADCs clock source selection + bit_offset: 28 + bit_size: 2 + - name: SWPMI1SEL + description: SWPMI1 clock source selection + bit_offset: 30 + bit_size: 1 + - name: DFSDMSEL + description: DFSDM clock source selection + bit_offset: 31 + bit_size: 1 fieldset/CCIPR2: description: Peripherals independent clock configuration register fields: - - bit_offset: 0 - bit_size: 2 - description: I2C4 clock source selection - name: I2C4SEL - - bit_offset: 2 - bit_size: 1 - description: Digital filter for sigma delta modulator kernel clock source selection - name: DFSDMSEL - - bit_offset: 3 - bit_size: 2 - description: Digital filter for sigma delta modulator audio clock source selection - name: ADFSDMSEL - - bit_offset: 5 - bit_size: 3 - description: SAI1 clock source selection - name: SAI1SEL - - bit_offset: 8 - bit_size: 3 - description: SAI2 clock source selection - name: SAI2SEL - - bit_offset: 12 - bit_size: 1 - description: clock selection - name: DSISEL - - bit_offset: 14 - bit_size: 1 - description: SDMMC clock selection - name: SDMMCSEL - - bit_offset: 16 - bit_size: 2 - description: division factor for LTDC clock - name: PLLSAI2DIVR - - bit_offset: 20 - bit_size: 2 - description: Octospi clock source selection - name: OSPISEL + - name: I2C4SEL + description: I2C4 clock source selection + bit_offset: 0 + bit_size: 2 + - name: DFSDMSEL + description: Digital filter for sigma delta modulator kernel clock source selection + bit_offset: 2 + bit_size: 1 + - name: ADFSDMSEL + description: Digital filter for sigma delta modulator audio clock source selection + bit_offset: 3 + bit_size: 2 + - name: SAI1SEL + description: SAI1 clock source selection + bit_offset: 5 + bit_size: 3 + - name: SAI2SEL + description: SAI2 clock source selection + bit_offset: 8 + bit_size: 3 + - name: DSISEL + description: clock selection + bit_offset: 12 + bit_size: 1 + - name: SDMMCSEL + description: SDMMC clock selection + bit_offset: 14 + bit_size: 1 + - name: PLLSAI2DIVR + description: division factor for LTDC clock + bit_offset: 16 + bit_size: 2 + - name: OSPISEL + description: Octospi clock source selection + bit_offset: 20 + bit_size: 2 fieldset/CFGR: description: Clock configuration register fields: - - bit_offset: 0 - bit_size: 2 - description: System clock switch - name: SW - - bit_offset: 2 - bit_size: 2 - description: System clock switch status - name: SWS - - bit_offset: 4 - bit_size: 4 - description: AHB prescaler - name: HPRE - - bit_offset: 8 - bit_size: 3 - description: PB low-speed prescaler (APB1) - name: PPRE1 - - bit_offset: 11 - bit_size: 3 - description: APB high-speed prescaler (APB2) - name: PPRE2 - - bit_offset: 15 - bit_size: 1 - description: Wakeup from Stop and CSS backup clock selection - name: STOPWUCK - - bit_offset: 24 - bit_size: 3 - description: Microcontroller clock output - name: MCOSEL - - bit_offset: 28 - bit_size: 3 - description: Microcontroller clock output prescaler - name: MCOPRE + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + - name: PPRE1 + description: PB low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + - name: STOPWUCK + description: Wakeup from Stop and CSS backup clock selection + bit_offset: 15 + bit_size: 1 + - name: MCOSEL + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 fieldset/CICR: description: Clock interrupt clear register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready interrupt clear - name: LSIRDYC - - bit_offset: 1 - bit_size: 1 - description: LSE ready interrupt clear - name: LSERDYC - - bit_offset: 2 - bit_size: 1 - description: MSI ready interrupt clear - name: MSIRDYC - - bit_offset: 3 - bit_size: 1 - description: HSI ready interrupt clear - name: HSIRDYC - - bit_offset: 4 - bit_size: 1 - description: HSE ready interrupt clear - name: HSERDYC - - bit_offset: 5 - bit_size: 1 - description: PLL ready interrupt clear - name: PLLRDYC - - bit_offset: 6 - bit_size: 1 - description: PLLSAI1 ready interrupt clear - name: PLLSAI1RDYC - - bit_offset: 7 - bit_size: 1 - description: PLLSAI2 ready interrupt clear - name: PLLSAI2RDYC - - bit_offset: 8 - bit_size: 1 - description: Clock security system interrupt clear - name: CSSC - - bit_offset: 9 - bit_size: 1 - description: LSE Clock security system interrupt clear - name: LSECSSC - - bit_offset: 10 - bit_size: 1 - description: HSI48 oscillator ready interrupt clear - name: HSI48RDYC + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 1 + bit_size: 1 + - name: MSIRDYC + description: MSI ready interrupt clear + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 4 + bit_size: 1 + - name: PLLRDYC + description: PLL ready interrupt clear + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYC + description: PLLSAI1 ready interrupt clear + bit_offset: 6 + bit_size: 1 + - name: PLLSAI2RDYC + description: PLLSAI2 ready interrupt clear + bit_offset: 7 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: LSE Clock security system interrupt clear + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYC + description: HSI48 oscillator ready interrupt clear + bit_offset: 10 + bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready interrupt enable - name: LSIRDYIE - - bit_offset: 1 - bit_size: 1 - description: LSE ready interrupt enable - name: LSERDYIE - - bit_offset: 2 - bit_size: 1 - description: MSI ready interrupt enable - name: MSIRDYIE - - bit_offset: 3 - bit_size: 1 - description: HSI ready interrupt enable - name: HSIRDYIE - - bit_offset: 4 - bit_size: 1 - description: HSE ready interrupt enable - name: HSERDYIE - - bit_offset: 5 - bit_size: 1 - description: PLL ready interrupt enable - name: PLLRDYIE - - bit_offset: 6 - bit_size: 1 - description: PLLSAI1 ready interrupt enable - name: PLLSAI1RDYIE - - bit_offset: 7 - bit_size: 1 - description: PLLSAI2 ready interrupt enable - name: PLLSAI2RDYIE - - bit_offset: 9 - bit_size: 1 - description: LSE clock security system interrupt enable - name: LSECSSIE - - bit_offset: 10 - bit_size: 1 - description: HSI48 ready interrupt enable - name: HSI48RDYIE + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 1 + bit_size: 1 + - name: MSIRDYIE + description: MSI ready interrupt enable + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: PLL ready interrupt enable + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYIE + description: PLLSAI1 ready interrupt enable + bit_offset: 6 + bit_size: 1 + - name: PLLSAI2RDYIE + description: PLLSAI2 ready interrupt enable + bit_offset: 7 + bit_size: 1 + - name: LSECSSIE + description: LSE clock security system interrupt enable + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYIE + description: HSI48 ready interrupt enable + bit_offset: 10 + bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - - bit_offset: 0 - bit_size: 1 - description: LSI ready interrupt flag - name: LSIRDYF - - bit_offset: 1 - bit_size: 1 - description: LSE ready interrupt flag - name: LSERDYF - - bit_offset: 2 - bit_size: 1 - description: MSI ready interrupt flag - name: MSIRDYF - - bit_offset: 3 - bit_size: 1 - description: HSI ready interrupt flag - name: HSIRDYF - - bit_offset: 4 - bit_size: 1 - description: HSE ready interrupt flag - name: HSERDYF - - bit_offset: 5 - bit_size: 1 - description: PLL ready interrupt flag - name: PLLRDYF - - bit_offset: 6 - bit_size: 1 - description: PLLSAI1 ready interrupt flag - name: PLLSAI1RDYF - - bit_offset: 7 - bit_size: 1 - description: PLLSAI2 ready interrupt flag - name: PLLSAI2RDYF - - bit_offset: 8 - bit_size: 1 - description: Clock security system interrupt flag - name: CSSF - - bit_offset: 9 - bit_size: 1 - description: LSE Clock security system interrupt flag - name: LSECSSF - - bit_offset: 10 - bit_size: 1 - description: HSI48 ready interrupt flag - name: HSI48RDYF + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: MSIRDYF + description: MSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYF + description: PLLSAI1 ready interrupt flag + bit_offset: 6 + bit_size: 1 + - name: PLLSAI2RDYF + description: PLLSAI2 ready interrupt flag + bit_offset: 7 + bit_size: 1 + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: LSE Clock security system interrupt flag + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYF + description: HSI48 ready interrupt flag + bit_offset: 10 + bit_size: 1 fieldset/CR: description: Clock control register fields: - - bit_offset: 0 - bit_size: 1 - description: MSI clock enable - name: MSION - - bit_offset: 1 - bit_size: 1 - description: MSI clock ready flag - name: MSIRDY - - bit_offset: 2 - bit_size: 1 - description: MSI clock PLL enable - name: MSIPLLEN - - bit_offset: 3 - bit_size: 1 - description: MSI clock range selection - name: MSIRGSEL - - bit_offset: 4 - bit_size: 4 - description: MSI clock ranges - enum: MSIRANGE - name: MSIRANGE - - bit_offset: 8 - bit_size: 1 - description: HSI clock enable - name: HSION - - bit_offset: 9 - bit_size: 1 - description: HSI always enable for peripheral kernels - name: HSIKERON - - bit_offset: 10 - bit_size: 1 - description: HSI clock ready flag - name: HSIRDY - - bit_offset: 11 - bit_size: 1 - description: HSI automatic start from Stop - name: HSIASFS - - bit_offset: 16 - bit_size: 1 - description: HSE clock enable - name: HSEON - - bit_offset: 17 - bit_size: 1 - description: HSE clock ready flag - name: HSERDY - - bit_offset: 18 - bit_size: 1 - description: HSE crystal oscillator bypass - name: HSEBYP - - bit_offset: 19 - bit_size: 1 - description: Clock security system enable - name: CSSON - - bit_offset: 24 - bit_size: 1 - description: Main PLL enable - name: PLLON - - bit_offset: 25 - bit_size: 1 - description: Main PLL clock ready flag - name: PLLRDY - - bit_offset: 26 - bit_size: 1 - description: SAI1 PLL enable - name: PLLSAI1ON - - bit_offset: 27 - bit_size: 1 - description: SAI1 PLL clock ready flag - name: PLLSAI1RDY - - bit_offset: 28 - bit_size: 1 - description: SAI2 PLL enable - name: PLLSAI2ON - - bit_offset: 29 - bit_size: 1 - description: SAI2 PLL clock ready flag - name: PLLSAI2RDY + - name: MSION + description: MSI clock enable + bit_offset: 0 + bit_size: 1 + - name: MSIRDY + description: MSI clock ready flag + bit_offset: 1 + bit_size: 1 + - name: MSIPLLEN + description: MSI clock PLL enable + bit_offset: 2 + bit_size: 1 + - name: MSIRGSEL + description: MSI clock range selection + bit_offset: 3 + bit_size: 1 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 4 + bit_size: 4 + enum: MSIRANGE + - name: HSION + description: HSI clock enable + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: HSI always enable for peripheral kernels + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: HSI clock ready flag + bit_offset: 10 + bit_size: 1 + - name: HSIASFS + description: HSI automatic start from Stop + bit_offset: 11 + bit_size: 1 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE crystal oscillator bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: Main PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL clock ready flag + bit_offset: 25 + bit_size: 1 + - name: PLLSAI1ON + description: SAI1 PLL enable + bit_offset: 26 + bit_size: 1 + - name: PLLSAI1RDY + description: SAI1 PLL clock ready flag + bit_offset: 27 + bit_size: 1 + - name: PLLSAI2ON + description: SAI2 PLL enable + bit_offset: 28 + bit_size: 1 + - name: PLLSAI2RDY + description: SAI2 PLL clock ready flag + bit_offset: 29 + bit_size: 1 fieldset/CRRCR: description: Clock recovery RC register fields: - - bit_offset: 0 - bit_size: 1 - description: HSI48 clock enable - name: HSI48ON - - bit_offset: 1 - bit_size: 1 - description: HSI48 clock ready flag - name: HSI48RDY - - bit_offset: 7 - bit_size: 9 - description: HSI48 clock calibration - name: HSI48CAL + - name: HSI48ON + description: HSI48 clock enable + bit_offset: 0 + bit_size: 1 + - name: HSI48RDY + description: HSI48 clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSI48CAL + description: HSI48 clock calibration + bit_offset: 7 + bit_size: 9 fieldset/CSR: description: CSR fields: - - bit_offset: 0 - bit_size: 1 - description: LSI oscillator enable - name: LSION - - bit_offset: 1 - bit_size: 1 - description: LSI oscillator ready - name: LSIRDY - - bit_offset: 8 - bit_size: 4 - description: SI range after Standby mode - name: MSISRANGE - - bit_offset: 23 - bit_size: 1 - description: Remove reset flag - name: RMVF - - bit_offset: 24 - bit_size: 1 - description: Firewall reset flag - name: FWRSTF - - bit_offset: 24 - bit_size: 1 - description: Firewall reset flag - name: FIREWALLRSTF - - bit_offset: 25 - bit_size: 1 - description: Option byte loader reset flag - name: OBLRSTF - - bit_offset: 26 - bit_size: 1 - description: Pin reset flag - name: PINRSTF - - bit_offset: 27 - bit_size: 1 - description: BOR flag - name: BORRSTF - - bit_offset: 28 - bit_size: 1 - description: Software reset flag - name: SFTRSTF - - bit_offset: 29 - bit_size: 1 - description: Independent window watchdog reset flag - name: IWDGRSTF - - bit_offset: 30 - bit_size: 1 - description: Window watchdog reset flag - name: WWDGRSTF - - bit_offset: 31 - bit_size: 1 - description: Low-power reset flag - name: LPWRSTF + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + - name: MSISRANGE + description: SI range after Standby mode + bit_offset: 8 + bit_size: 4 + - name: RMVF + description: Remove reset flag + bit_offset: 23 + bit_size: 1 + - name: FWRSTF + description: Firewall reset flag + bit_offset: 24 + bit_size: 1 + - name: FIREWALLRSTF + description: Firewall reset flag + bit_offset: 24 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: Pin reset flag + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: BOR flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent window watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - - bit_offset: 0 - bit_size: 8 - description: MSI clock calibration - name: MSICAL - - bit_offset: 8 - bit_size: 8 - description: MSI clock trimming - name: MSITRIM - - bit_offset: 16 - bit_size: 8 - description: HSI clock calibration - name: HSICAL - - bit_offset: 24 - bit_size: 7 - description: HSI clock trimming - name: HSITRIM + - name: MSICAL + description: MSI clock calibration + bit_offset: 0 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 8 + bit_size: 8 + - name: HSICAL + description: HSI clock calibration + bit_offset: 16 + bit_size: 8 + - name: HSITRIM + description: HSI clock trimming + bit_offset: 24 + bit_size: 7 fieldset/PLLCFGR: description: PLL configuration register fields: - - bit_offset: 0 - bit_size: 2 - description: Main PLL, PLLSAI1 and PLLSAI2 entry clock source - name: PLLSRC - - bit_offset: 4 - bit_size: 4 - description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) - input clock - name: PLLM - - bit_offset: 8 - bit_size: 7 - description: Main PLL multiplication factor for VCO - name: PLLN - - bit_offset: 16 - bit_size: 1 - description: Main PLL PLLSAI3CLK output enable - name: PLLPEN - - bit_offset: 17 - bit_size: 1 - description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) - name: PLLP - - bit_offset: 20 - bit_size: 1 - description: Main PLL PLLUSB1CLK output enable - name: PLLQEN - - bit_offset: 21 - bit_size: 2 - description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) - name: PLLQ - - bit_offset: 24 - bit_size: 1 - description: Main PLL PLLCLK output enable - name: PLLREN - - bit_offset: 25 - bit_size: 2 - description: Main PLL division factor for PLLCLK (system clock) - name: PLLR - - bit_offset: 27 - bit_size: 5 - description: Main PLL division factor for PLLSAI2CLK - name: PLLPDIV + - name: PLLSRC + description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source" + bit_offset: 0 + bit_size: 2 + - name: PLLM + description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock + bit_offset: 4 + bit_size: 4 + - name: PLLN + description: Main PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: Main PLL PLLSAI3CLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + bit_offset: 17 + bit_size: 1 + - name: PLLQEN + description: Main PLL PLLUSB1CLK output enable + bit_offset: 20 + bit_size: 1 + - name: PLLQ + description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) + bit_offset: 21 + bit_size: 2 + - name: PLLREN + description: Main PLL PLLCLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLR + description: Main PLL division factor for PLLCLK (system clock) + bit_offset: 25 + bit_size: 2 + - name: PLLPDIV + description: Main PLL division factor for PLLSAI2CLK + bit_offset: 27 + bit_size: 5 fieldset/PLLSAI1CFGR: description: PLLSAI1 configuration register fields: - - bit_offset: 4 - bit_size: 4 - description: Division factor for PLLSAI1 input clock - name: PLLSAI1M - - bit_offset: 8 - bit_size: 7 - description: SAI1PLL multiplication factor for VCO - name: PLLSAI1N - - bit_offset: 16 - bit_size: 1 - description: SAI1PLL PLLSAI1CLK output enable - name: PLLSAI1PEN - - bit_offset: 17 - bit_size: 1 - description: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) - name: PLLSAI1P - - bit_offset: 20 - bit_size: 1 - description: SAI1PLL PLLUSB2CLK output enable - name: PLLSAI1QEN - - bit_offset: 21 - bit_size: 2 - description: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) - name: PLLSAI1Q - - bit_offset: 24 - bit_size: 1 - description: PLLSAI1 PLLADC1CLK output enable - name: PLLSAI1REN - - bit_offset: 25 - bit_size: 2 - description: PLLSAI1 division factor for PLLADC1CLK (ADC clock) - name: PLLSAI1R - - bit_offset: 27 - bit_size: 5 - description: PLLSAI1 division factor for PLLSAI1CLK - name: PLLSAI1PDIV + - name: PLLSAI1M + description: Division factor for PLLSAI1 input clock + bit_offset: 4 + bit_size: 4 + - name: PLLSAI1N + description: SAI1PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLSAI1PEN + description: SAI1PLL PLLSAI1CLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLSAI1P + description: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) + bit_offset: 17 + bit_size: 1 + - name: PLLSAI1QEN + description: SAI1PLL PLLUSB2CLK output enable + bit_offset: 20 + bit_size: 1 + - name: PLLSAI1Q + description: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) + bit_offset: 21 + bit_size: 2 + - name: PLLSAI1REN + description: PLLSAI1 PLLADC1CLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLSAI1R + description: PLLSAI1 division factor for PLLADC1CLK (ADC clock) + bit_offset: 25 + bit_size: 2 + - name: PLLSAI1PDIV + description: PLLSAI1 division factor for PLLSAI1CLK + bit_offset: 27 + bit_size: 5 fieldset/PLLSAI2CFGR: description: PLLSAI2 configuration register fields: - - bit_offset: 4 - bit_size: 4 - description: Division factor for PLLSAI2 input clock - name: PLLSAI2M - - bit_offset: 8 - bit_size: 7 - description: SAI2PLL multiplication factor for VCO - name: PLLSAI2N - - bit_offset: 16 - bit_size: 1 - description: SAI2PLL PLLSAI2CLK output enable - name: PLLSAI2PEN - - bit_offset: 17 - bit_size: 1 - description: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) - name: PLLSAI2P - - bit_offset: 20 - bit_size: 1 - description: PLLSAI2 division factor for PLLDISCLK - name: PLLSAI2QEN - - bit_offset: 21 - bit_size: 2 - description: SAI2PLL PLLSAI2CLK output enable - name: PLLSAI2Q - - bit_offset: 24 - bit_size: 1 - description: PLLSAI2 PLLADC2CLK output enable - name: PLLSAI2REN - - bit_offset: 25 - bit_size: 2 - description: PLLSAI2 division factor for PLLADC2CLK (ADC clock) - name: PLLSAI2R - - bit_offset: 27 - bit_size: 5 - description: PLLSAI2 division factor for PLLSAI2CLK - name: PLLSAI2PDIV + - name: PLLSAI2M + description: Division factor for PLLSAI2 input clock + bit_offset: 4 + bit_size: 4 + - name: PLLSAI2N + description: SAI2PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLSAI2PEN + description: SAI2PLL PLLSAI2CLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLSAI2P + description: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) + bit_offset: 17 + bit_size: 1 + - name: PLLSAI2QEN + description: PLLSAI2 division factor for PLLDISCLK + bit_offset: 20 + bit_size: 1 + - name: PLLSAI2Q + description: SAI2PLL PLLSAI2CLK output enable + bit_offset: 21 + bit_size: 2 + - name: PLLSAI2REN + description: PLLSAI2 PLLADC2CLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLSAI2R + description: PLLSAI2 division factor for PLLADC2CLK (ADC clock) + bit_offset: 25 + bit_size: 2 + - name: PLLSAI2PDIV + description: PLLSAI2 division factor for PLLSAI2CLK + bit_offset: 27 + bit_size: 5 +enum/MSIRANGE: + bit_size: 4 + variants: + - name: Range100K + description: range 0 around 100 kHz + value: 0 + - name: Range200K + description: range 1 around 200 kHz + value: 1 + - name: Range400K + description: range 2 around 400 kHz + value: 2 + - name: Range800K + description: range 3 around 800 kHz + value: 3 + - name: Range1M + description: range 4 around 1 MHz + value: 4 + - name: Range2M + description: range 5 around 2 MHz + value: 5 + - name: Range4M + description: range 6 around 4 MHz + value: 6 + - name: Range8M + description: range 7 around 8 MHz + value: 7 + - name: Range16M + description: range 8 around 16 MHz + value: 8 + - name: Range24M + description: range 9 around 24 MHz + value: 9 + - name: Range32M + description: range 10 around 32 MHz + value: 10 + - name: Range48M + description: range 11 around 48 MHz + value: 11 diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index 6996619..dec1256 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -2560,6 +2560,24 @@ enum/MSIBIAS: - name: SAMPLING description: MSI bias sampling mode (ultra-low-power mode) value: 1 +enum/MSIPLLFAST: + bit_size: 1 + variants: + - name: NORMAL + description: MSI PLL normal start-up + value: 0 + - name: FAST + description: MSI PLL fast start-up + value: 1 +enum/MSIPLLSEL: + bit_size: 1 + variants: + - name: MSIK + description: "PLL mode applied to MSIK (MSI kernel) clock output " + value: 0 + - name: MSIS + description: PLL mode applied to MSIS (MSI system) clock output + value: 1 enum/MSIRANGE: bit_size: 4 variants: @@ -2611,6 +2629,15 @@ enum/MSIRANGE: - name: RANGE_100KHZ description: "range 15 around 100 kHz " value: 15 +enum/MSIRGSEL: + bit_size: 1 + variants: + - name: RCC_CSR + description: "MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR" + value: 0 + - name: RCC_ICSCR1 + description: "MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1" + value: 1 enum/MSIXSRANGE: bit_size: 4 variants: @@ -2629,33 +2656,6 @@ enum/MSIXSRANGE: - name: RANGE_3_072MHZ description: "range 8 around 3.072 MHz " value: 8 -enum/MSIPLLFAST: - bit_size: 1 - variants: - - name: NORMAL - description: MSI PLL normal start-up - value: 0 - - name: FAST - description: MSI PLL fast start-up - value: 1 -enum/MSIPLLSEL: - bit_size: 1 - variants: - - name: MSIK - description: "PLL mode applied to MSIK (MSI kernel) clock output " - value: 0 - - name: MSIS - description: PLL mode applied to MSIS (MSI system) clock output - value: 1 -enum/MSIRGSEL: - bit_size: 1 - variants: - - name: RCC_CSR - description: "MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR" - value: 0 - - name: RCC_ICSCR1 - description: "MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1" - value: 1 enum/OCTOSPISEL: bit_size: 2 variants: @@ -2758,6 +2758,15 @@ enum/PPRE: - name: DIV16 description: HCLK divided by 16 value: 7 +enum/PRIV: + bit_size: 1 + variants: + - name: UNPRIVILEGED + description: Read and write to secure functions can be done by privileged or unprivileged access. + value: 0 + - name: PRIVILEGED + description: Read and write to secure functions can be done by privileged access only. + value: 1 enum/RNGSEL: bit_size: 2 variants: @@ -2821,6 +2830,15 @@ enum/SDMMCSEL: - name: PLL1_P description: "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) " value: 1 +enum/SECURITY: + bit_size: 1 + variants: + - name: NON_SECURE + description: non secure + value: 0 + - name: SECURE + description: secure + value: 1 enum/SPISEL: bit_size: 2 variants: @@ -2929,21 +2947,3 @@ enum/USARTSEL: - name: LSE description: LSE selected value: 3 -enum/SECURITY: - bit_size: 1 - variants: - - name: NON_SECURE - description: non secure - value: 0 - - name: SECURE - description: secure - value: 1 -enum/PRIV: - bit_size: 1 - variants: - - name: UNPRIVILEGED - description: Read and write to secure functions can be done by privileged or unprivileged access. - value: 0 - - name: PRIVILEGED - description: Read and write to secure functions can be done by privileged access only. - value: 1 diff --git a/data/registers/rtc_v2.yaml b/data/registers/rtc_v2.yaml index 708ef41..55834e7 100644 --- a/data/registers/rtc_v2.yaml +++ b/data/registers/rtc_v2.yaml @@ -2,1172 +2,1154 @@ block/RTC: description: Real-time clock items: - - byte_offset: 0 - description: time register - fieldset: TR - name: TR - - byte_offset: 4 - description: date register - fieldset: DR - name: DR - - byte_offset: 8 - description: control register - fieldset: CR - name: CR - - byte_offset: 12 - description: initialization and status register - fieldset: ISR - name: ISR - - byte_offset: 16 - description: prescaler register - fieldset: PRER - name: PRER - - byte_offset: 20 - description: wakeup timer register - fieldset: WUTR - name: WUTR - - byte_offset: 28 - description: alarm A register - fieldset: ALRMAR - name: ALRMAR - - byte_offset: 32 - description: alarm B register - fieldset: ALRMBR - name: ALRMBR - - access: Write - byte_offset: 36 - description: write protection register - fieldset: WPR - name: WPR - - access: Read - byte_offset: 40 - description: sub second register - fieldset: SSR - name: SSR - - access: Write - byte_offset: 44 - description: shift control register - fieldset: SHIFTR - name: SHIFTR - - access: Read - byte_offset: 48 - description: time stamp time register - fieldset: TSTR - name: TSTR - - access: Read - byte_offset: 52 - description: time stamp date register - fieldset: TSDR - name: TSDR - - access: Read - byte_offset: 56 - description: timestamp sub second register - fieldset: TSSSR - name: TSSSR - - byte_offset: 60 - description: calibration register - fieldset: CALR - name: CALR - - byte_offset: 64 - description: tamper configuration register - fieldset: TAMPCR - name: TAMPCR - - byte_offset: 68 - description: alarm A sub second register - fieldset: ALRMASSR - name: ALRMASSR - - byte_offset: 72 - description: alarm B sub second register - fieldset: ALRMBSSR - name: ALRMBSSR - - byte_offset: 76 - description: option register - fieldset: OR - name: OR - - array: - len: 32 - stride: 4 - byte_offset: 80 - description: backup register - fieldset: BKPR - name: BKPR -enum/ADDHW: - bit_size: 1 - variants: - - description: Adds 1 hour to the current time. This can be used for summer time - change outside initialization mode - name: Add1 - value: 1 -enum/ADDSW: - bit_size: 1 - variants: - - description: Add one second to the clock/calendar - name: Add1 - value: 1 -enum/ALRAE: - bit_size: 1 - variants: - - description: Alarm A disabled - name: Disabled - value: 0 - - description: Alarm A enabled - name: Enabled - value: 1 -enum/ALRAFR: - bit_size: 1 - variants: - - description: This flag is set by hardware when the time/date registers (RTC_TR - and RTC_DR) match the Alarm A register (RTC_ALRMAR) - name: Match - value: 1 -enum/ALRAFW: - bit_size: 1 - variants: - - description: This flag is cleared by software by writing 0 - name: Clear - value: 0 -enum/ALRAIE: - bit_size: 1 - variants: - - description: Alarm A interrupt disabled - name: Disabled - value: 0 - - description: Alarm A interrupt enabled - name: Enabled - value: 1 -enum/ALRAWFR: - bit_size: 1 - variants: - - description: Alarm update not allowed - name: UpdateNotAllowed - value: 0 - - description: Alarm update allowed - name: UpdateAllowed - value: 1 -enum/ALRBE: - bit_size: 1 - variants: - - description: Alarm B disabled - name: Disabled - value: 0 - - description: Alarm B enabled - name: Enabled - value: 1 -enum/ALRBFR: - bit_size: 1 - variants: - - description: This flag is set by hardware when the time/date registers (RTC_TR - and RTC_DR) match the Alarm B register (RTC_ALRMBR) - name: Match - value: 1 -enum/ALRBFW: - bit_size: 1 - variants: - - description: This flag is cleared by software by writing 0 - name: Clear - value: 0 -enum/ALRBIE: - bit_size: 1 - variants: - - description: Alarm B Interrupt disabled - name: Disabled - value: 0 - - description: Alarm B Interrupt enabled - name: Enabled - value: 1 -enum/ALRMAR_MSK: - bit_size: 1 - variants: - - description: Alarm set if the date/day match - name: Mask - value: 0 - - description: "Date/day don\u2019t care in Alarm comparison" - name: NotMask - value: 1 -enum/ALRMAR_PM: - bit_size: 1 - variants: - - description: AM or 24-hour format - name: AM - value: 0 - - description: PM - name: PM - value: 1 -enum/ALRMAR_WDSEL: - bit_size: 1 - variants: - - description: DU[3:0] represents the date units - name: DateUnits - value: 0 - - description: "DU[3:0] represents the week day. DT[1:0] is don\u2019t care." - name: WeekDay - value: 1 -enum/ALRMBR_MSK: - bit_size: 1 - variants: - - description: Alarm set if the date/day match - name: Mask - value: 0 - - description: "Date/day don\u2019t care in Alarm comparison" - name: NotMask - value: 1 -enum/ALRMBR_PM: - bit_size: 1 - variants: - - description: AM or 24-hour format - name: AM - value: 0 - - description: PM - name: PM - value: 1 -enum/ALRMBR_WDSEL: - bit_size: 1 - variants: - - description: DU[3:0] represents the date units - name: DateUnits - value: 0 - - description: "DU[3:0] represents the week day. DT[1:0] is don\u2019t care." - name: WeekDay - value: 1 -enum/BKP: - bit_size: 1 - variants: - - description: Daylight Saving Time change has not been performed - name: DST_Not_Changed - value: 0 - - description: Daylight Saving Time change has been performed - name: DST_Changed - value: 1 -enum/BYPSHAD: - bit_size: 1 - variants: - - description: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are - taken from the shadow registers, which are updated once every two RTCCLK cycles - name: ShadowReg - value: 0 - - description: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are - taken directly from the calendar counters - name: BypassShadowReg - value: 1 -enum/CALP: - bit_size: 1 - variants: - - description: No RTCCLK pulses are added - name: NoChange - value: 0 - - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency - increased by 488.5 ppm) - name: IncreaseFreq - value: 1 -enum/CALW16: - bit_size: 1 - variants: - - description: "When CALW16 is set to \u20181\u2019, the 16-second calibration cycle\ - \ period is selected.This bit must not be set to \u20181\u2019 if CALW8=1" - name: Sixteen_Second - value: 1 -enum/CALW8: - bit_size: 1 - variants: - - description: "When CALW8 is set to \u20181\u2019, the 8-second calibration cycle\ - \ period is selected" - name: Eight_Second - value: 1 -enum/COE: - bit_size: 1 - variants: - - description: Calibration output disabled - name: Disabled - value: 0 - - description: Calibration output enabled - name: Enabled - value: 1 -enum/COSEL: - bit_size: 1 - variants: - - description: Calibration output is 512 Hz (with default prescaler setting) - name: CalFreq_512Hz - value: 0 - - description: Calibration output is 1 Hz (with default prescaler setting) - name: CalFreq_1Hz - value: 1 -enum/FMT: - bit_size: 1 - variants: - - description: 24 hour/day format - name: Twenty_Four_Hour - value: 0 - - description: AM/PM hour format - name: AM_PM - value: 1 -enum/INIT: - bit_size: 1 - variants: - - description: Free running mode - name: FreeRunningMode - value: 0 - - description: Initialization mode used to program time and date register (RTC_TR - and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start - counting from the new value when INIT is reset. - name: InitMode - value: 1 -enum/INITFR: - bit_size: 1 - variants: - - description: Calendar registers update is not allowed - name: NotAllowed - value: 0 - - description: Calendar registers update is allowed - name: Allowed - value: 1 -enum/INITSR: - bit_size: 1 - variants: - - description: Calendar has not been initialized - name: NotInitalized - value: 0 - - description: Calendar has been initialized - name: Initalized - value: 1 -enum/OSEL: - bit_size: 2 - variants: - - description: Output disabled - name: Disabled - value: 0 - - description: Alarm A output enabled - name: AlarmA - value: 1 - - description: Alarm B output enabled - name: AlarmB - value: 2 - - description: Wakeup output enabled - name: Wakeup - value: 3 -enum/POL: - bit_size: 1 - variants: - - description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - name: High - value: 0 - - description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) - name: Low - value: 1 -enum/RECALPFR: - bit_size: 1 - variants: - - description: The RECALPF status flag is automatically set to 1 when software writes - to the RTC_CALR register, indicating that the RTC_CALR register is blocked. - When the new calibration settings are taken into account, this bit returns to - 0 - name: Pending - value: 1 -enum/REFCKON: - bit_size: 1 - variants: - - description: RTC_REFIN detection disabled - name: Disabled - value: 0 - - description: RTC_REFIN detection enabled - name: Enabled - value: 1 -enum/RSFR: - bit_size: 1 - variants: - - description: Calendar shadow registers not yet synchronized - name: NotSynced - value: 0 - - description: Calendar shadow registers synchronized - name: Synced - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - description: This flag is cleared by software by writing 0 - name: Clear - value: 0 -enum/SHPFR: - bit_size: 1 - variants: - - description: No shift operation is pending - name: NoShiftPending - value: 0 - - description: A shift operation is pending - name: ShiftPending - value: 1 -enum/SUBHW: - bit_size: 1 - variants: - - description: Subtracts 1 hour to the current time. This can be used for winter - time change outside initialization mode - name: Sub1 - value: 1 -enum/TAMPFR: - bit_size: 1 - variants: - - description: This flag is set by hardware when a tamper detection event is detected - on the RTC_TAMPx input - name: Tampered - value: 1 -enum/TAMPFW: - bit_size: 1 - variants: - - description: Flag cleared by software writing 0 - name: Clear - value: 0 -enum/TR_PM: - bit_size: 1 - variants: - - description: AM or 24-hour format - name: AM - value: 0 - - description: PM - name: PM - value: 1 -enum/TSE: - bit_size: 1 - variants: - - description: Timestamp disabled - name: Disabled - value: 0 - - description: Timestamp enabled - name: Enabled - value: 1 -enum/TSEDGE: - bit_size: 1 - variants: - - description: RTC_TS input rising edge generates a time-stamp event - name: RisingEdge - value: 0 - - description: RTC_TS input falling edge generates a time-stamp event - name: FallingEdge - value: 1 -enum/TSFR: - bit_size: 1 - variants: - - description: This flag is set by hardware when a time-stamp event occurs - name: TimestampEvent - value: 1 -enum/TSFW: - bit_size: 1 - variants: - - description: This flag is cleared by software by writing 0 - name: Clear - value: 0 -enum/TSIE: - bit_size: 1 - variants: - - description: Time-stamp Interrupt disabled - name: Disabled - value: 0 - - description: Time-stamp Interrupt enabled - name: Enabled - value: 1 -enum/TSOVFR: - bit_size: 1 - variants: - - description: This flag is set by hardware when a time-stamp event occurs while - TSF is already set - name: Overflow - value: 1 -enum/TSOVFW: - bit_size: 1 - variants: - - description: This flag is cleared by software by writing 0 - name: Clear - value: 0 -enum/WUCKSEL: - bit_size: 3 - variants: - - description: RTC/16 clock is selected - name: Div16 - value: 0 - - description: RTC/8 clock is selected - name: Div8 - value: 1 - - description: RTC/4 clock is selected - name: Div4 - value: 2 - - description: RTC/2 clock is selected - name: Div2 - value: 3 - - description: ck_spre (usually 1 Hz) clock is selected - name: ClockSpare - value: 4 - - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the - WUT counter value - name: ClockSpareWithOffset - value: 6 -enum/WUTE: - bit_size: 1 - variants: - - description: Wakeup timer disabled - name: Disabled - value: 0 - - description: Wakeup timer enabled - name: Enabled - value: 1 -enum/WUTFR: - bit_size: 1 - variants: - - description: This flag is set by hardware when the wakeup auto-reload counter - reaches 0 - name: Zero - value: 1 -enum/WUTFW: - bit_size: 1 - variants: - - description: This flag is cleared by software by writing 0 - name: Clear - value: 0 -enum/WUTIE: - bit_size: 1 - variants: - - description: Wakeup timer interrupt disabled - name: Disabled - value: 0 - - description: Wakeup timer interrupt enabled - name: Enabled - value: 1 -enum/WUTWFR: - bit_size: 1 - variants: - - description: Wakeup timer configuration update not allowed - name: UpdateNotAllowed - value: 0 - - description: Wakeup timer configuration update allowed - name: UpdateAllowed - value: 1 + - name: TR + description: time register + byte_offset: 0 + fieldset: TR + - name: DR + description: date register + byte_offset: 4 + fieldset: DR + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMAR + description: alarm A register + byte_offset: 28 + fieldset: ALRMAR + - name: ALRMBR + description: alarm B register + byte_offset: 32 + fieldset: ALRMBR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: time stamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: time stamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMASSR + description: alarm A sub second register + byte_offset: 68 + fieldset: ALRMASSR + - name: ALRMBSSR + description: alarm B sub second register + byte_offset: 72 + fieldset: ALRMBSSR + - name: OR + description: option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR fieldset/ALRMAR: description: alarm A register fields: - - bit_offset: 0 - bit_size: 4 - description: Second units in BCD format - name: SU - - bit_offset: 4 - bit_size: 3 - description: Second tens in BCD format - name: ST - - array: - len: 4 - stride: 8 - bit_offset: 7 - bit_size: 1 - description: Alarm A seconds mask - enum: ALRMAR_MSK - name: MSK - - bit_offset: 8 - bit_size: 4 - description: Minute units in BCD format - name: MNU - - bit_offset: 12 - bit_size: 3 - description: Minute tens in BCD format - name: MNT - - bit_offset: 16 - bit_size: 4 - description: Hour units in BCD format - name: HU - - bit_offset: 20 - bit_size: 2 - description: Hour tens in BCD format - name: HT - - bit_offset: 22 - bit_size: 1 - description: AM/PM notation - enum: ALRMAR_PM - name: PM - - bit_offset: 24 - bit_size: 4 - description: Date units or day in BCD format - name: DU - - bit_offset: 28 - bit_size: 2 - description: Date tens in BCD format - name: DT - - bit_offset: 30 - bit_size: 1 - description: Week day selection - enum: ALRMAR_WDSEL - name: WDSEL + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + array: + len: 4 + stride: 8 + enum: ALRMAR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMAR_PM + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMAR_WDSEL fieldset/ALRMASSR: description: alarm A sub second register fields: - - bit_offset: 0 - bit_size: 15 - description: Sub seconds value - name: SS - - bit_offset: 24 - bit_size: 4 - description: Mask the most-significant bits starting at this bit - name: MASKSS + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 fieldset/ALRMBR: description: alarm B register fields: - - bit_offset: 0 - bit_size: 4 - description: Second units in BCD format - name: SU - - bit_offset: 4 - bit_size: 3 - description: Second tens in BCD format - name: ST - - array: - len: 4 - stride: 8 - bit_offset: 7 - bit_size: 1 - description: Alarm B seconds mask - enum: ALRMBR_MSK - name: MSK - - bit_offset: 8 - bit_size: 4 - description: Minute units in BCD format - name: MNU - - bit_offset: 12 - bit_size: 3 - description: Minute tens in BCD format - name: MNT - - bit_offset: 16 - bit_size: 4 - description: Hour units in BCD format - name: HU - - bit_offset: 20 - bit_size: 2 - description: Hour tens in BCD format - name: HT - - bit_offset: 22 - bit_size: 1 - description: AM/PM notation - enum: ALRMBR_PM - name: PM - - bit_offset: 24 - bit_size: 4 - description: Date units or day in BCD format - name: DU - - bit_offset: 28 - bit_size: 2 - description: Date tens in BCD format - name: DT - - bit_offset: 30 - bit_size: 1 - description: Week day selection - enum: ALRMBR_WDSEL - name: WDSEL + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + array: + len: 4 + stride: 8 + enum: ALRMBR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMBR_PM + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMBR_WDSEL fieldset/ALRMBSSR: description: alarm B sub second register fields: - - bit_offset: 0 - bit_size: 15 - description: Sub seconds value - name: SS - - bit_offset: 24 - bit_size: 4 - description: Mask the most-significant bits starting at this bit - name: MASKSS + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 fieldset/BKPR: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/CALR: description: calibration register fields: - - bit_offset: 0 - bit_size: 9 - description: Calibration minus - name: CALM - - array: - len: 2 - stride: 1 - bit_offset: 13 - bit_size: 1 - description: Use a 16-second calibration cycle period - enum: CALW16 - name: CALW - - bit_offset: 15 - bit_size: 1 - description: Increase frequency of RTC by 488.5 ppm - enum: CALP - name: CALP + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: CALW16 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP fieldset/CR: description: control register fields: - - bit_offset: 0 - bit_size: 3 - description: Wakeup clock selection - enum: WUCKSEL - name: WUCKSEL - - bit_offset: 3 - bit_size: 1 - description: Time-stamp event active edge - enum: TSEDGE - name: TSEDGE - - bit_offset: 4 - bit_size: 1 - description: Reference clock detection enable (50 or 60 Hz) - enum: REFCKON - name: REFCKON - - bit_offset: 5 - bit_size: 1 - description: Bypass the shadow registers - enum: BYPSHAD - name: BYPSHAD - - bit_offset: 6 - bit_size: 1 - description: Hour format - enum: FMT - name: FMT - - bit_offset: 8 - bit_size: 1 - description: Alarm A enable - enum: ALRAE - name: ALRAE - - bit_offset: 9 - bit_size: 1 - description: Alarm B enable - enum: ALRBE - name: ALRBE - - bit_offset: 10 - bit_size: 1 - description: Wakeup timer enable - enum: WUTE - name: WUTE - - bit_offset: 11 - bit_size: 1 - description: Time stamp enable - enum: TSE - name: TSE - - bit_offset: 12 - bit_size: 1 - description: Alarm A interrupt enable - enum: ALRAIE - name: ALRAIE - - bit_offset: 13 - bit_size: 1 - description: Alarm B interrupt enable - enum: ALRBIE - name: ALRBIE - - bit_offset: 14 - bit_size: 1 - description: Wakeup timer interrupt enable - enum: WUTIE - name: WUTIE - - bit_offset: 15 - bit_size: 1 - description: Time-stamp interrupt enable - enum: TSIE - name: TSIE - - bit_offset: 16 - bit_size: 1 - description: Add 1 hour (summer time change) - enum_write: ADDHW - name: ADD1H - - bit_offset: 17 - bit_size: 1 - description: Subtract 1 hour (winter time change) - enum_write: SUBHW - name: SUB1H - - bit_offset: 18 - bit_size: 1 - description: Backup - enum: BKP - name: BKP - - bit_offset: 19 - bit_size: 1 - description: Calibration output selection - enum: COSEL - name: COSEL - - bit_offset: 20 - bit_size: 1 - description: Output polarity - enum: POL - name: POL - - bit_offset: 21 - bit_size: 2 - description: Output selection - enum: OSEL - name: OSEL - - bit_offset: 23 - bit_size: 1 - description: Calibration output enable - enum: COE - name: COE - - bit_offset: 24 - bit_size: 1 - description: timestamp on internal event enable - name: ITSE + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Time-stamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + enum: BYPSHAD + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRAE + description: Alarm A enable + bit_offset: 8 + bit_size: 1 + enum: ALRAE + - name: ALRBE + description: Alarm B enable + bit_offset: 9 + bit_size: 1 + enum: ALRBE + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + enum: WUTE + - name: TSE + description: Time stamp enable + bit_offset: 11 + bit_size: 1 + enum: TSE + - name: ALRAIE + description: Alarm A interrupt enable + bit_offset: 12 + bit_size: 1 + enum: ALRAIE + - name: ALRBIE + description: Alarm B interrupt enable + bit_offset: 13 + bit_size: 1 + enum: ALRBIE + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + enum: WUTIE + - name: TSIE + description: Time-stamp interrupt enable + bit_offset: 15 + bit_size: 1 + enum: TSIE + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + enum_write: ADDHW + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + enum_write: SUBHW + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + enum: BKP + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + enum: COE + - name: ITSE + description: timestamp on internal event enable + bit_offset: 24 + bit_size: 1 fieldset/DR: description: date register fields: - - bit_offset: 0 - bit_size: 4 - description: Date units in BCD format - name: DU - - bit_offset: 4 - bit_size: 2 - description: Date tens in BCD format - name: DT - - bit_offset: 8 - bit_size: 4 - description: Month units in BCD format - name: MU - - bit_offset: 12 - bit_size: 1 - description: Month tens in BCD format - name: MT - - bit_offset: 13 - bit_size: 3 - description: Week day units - name: WDU - - bit_offset: 16 - bit_size: 4 - description: Year units in BCD format - name: YU - - bit_offset: 20 - bit_size: 4 - description: Year tens in BCD format - name: YT + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ISR: description: initialization and status register fields: - - bit_offset: 0 - bit_size: 1 - description: Alarm A write flag - enum_read: ALRAWFR - name: ALRAWF - - bit_offset: 1 - bit_size: 1 - description: Alarm B write flag - enum_read: ALRAWFR - name: ALRBWF - - bit_offset: 2 - bit_size: 1 - description: Wakeup timer write flag - enum_read: WUTWFR - name: WUTWF - - bit_offset: 3 - bit_size: 1 - description: Shift operation pending - enum_read: SHPFR - name: SHPF - - bit_offset: 4 - bit_size: 1 - description: Initialization status flag - enum_read: INITSR - name: INITS - - bit_offset: 5 - bit_size: 1 - description: Registers synchronization flag - enum_read: RSFR - enum_write: RSFW - name: RSF - - bit_offset: 6 - bit_size: 1 - description: Initialization flag - enum_read: INITFR - name: INITF - - bit_offset: 7 - bit_size: 1 - description: Initialization mode - enum: INIT - name: INIT - - bit_offset: 8 - bit_size: 1 - description: Alarm A flag - enum_read: ALRAFR - enum_write: ALRAFW - name: ALRAF - - bit_offset: 9 - bit_size: 1 - description: Alarm B flag - enum_read: ALRBFR - enum_write: ALRBFW - name: ALRBF - - bit_offset: 10 - bit_size: 1 - description: Wakeup timer flag - enum_read: WUTFR - enum_write: WUTFW - name: WUTF - - bit_offset: 11 - bit_size: 1 - description: Time-stamp flag - enum_read: TSFR - enum_write: TSFW - name: TSF - - bit_offset: 12 - bit_size: 1 - description: Time-stamp overflow flag - enum_read: TSOVFR - enum_write: TSOVFW - name: TSOVF - - bit_offset: 13 - bit_size: 1 - description: Tamper detection flag - enum_read: TAMPFR - enum_write: TAMPFW - name: TAMP1F - - bit_offset: 14 - bit_size: 1 - description: RTC_TAMP2 detection flag - enum_read: TAMPFR - enum_write: TAMPFW - name: TAMP2F - - bit_offset: 15 - bit_size: 1 - description: RTC_TAMP3 detection flag - enum_read: TAMPFR - enum_write: TAMPFW - name: TAMP3F - - bit_offset: 16 - bit_size: 1 - description: Recalibration pending Flag - enum_read: RECALPFR - name: RECALPF - - bit_offset: 17 - bit_size: 1 - description: Internal tTime-stamp flag - name: ITSF + - name: ALRAWF + description: Alarm A write flag + bit_offset: 0 + bit_size: 1 + enum_read: ALRAWFR + - name: ALRBWF + description: Alarm B write flag + bit_offset: 1 + bit_size: 1 + enum_read: ALRAWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + enum_read: SHPFR + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRAF + description: Alarm A flag + bit_offset: 8 + bit_size: 1 + enum_read: ALRAFR + enum_write: ALRAFW + - name: ALRBF + description: Alarm B flag + bit_offset: 9 + bit_size: 1 + enum_read: ALRBFR + enum_write: ALRBFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Time-stamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Time-stamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMP1F + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: TAMP2F + description: RTC_TAMP2 detection flag + bit_offset: 14 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: TAMP3F + description: RTC_TAMP3 detection flag + bit_offset: 15 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR + - name: ITSF + description: Internal tTime-stamp flag + bit_offset: 17 + bit_size: 1 fieldset/OR: description: option register fields: - - bit_offset: 1 - bit_size: 1 - description: TIMESTAMP mapping - name: TSINSEL - - bit_offset: 1 - bit_size: 1 - description: RTC_OUT remap - name: RTC_OUT_RMP - - bit_offset: 3 - bit_size: 1 - description: RTC_ALARM on PC13 output type - name: RTC_ALARM_TYPE + - name: TSINSEL + description: TIMESTAMP mapping + bit_offset: 1 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_OUT remap + bit_offset: 1 + bit_size: 1 + - name: RTC_ALARM_TYPE + description: RTC_ALARM on PC13 output type + bit_offset: 3 + bit_size: 1 fieldset/PRER: description: prescaler register fields: - - bit_offset: 0 - bit_size: 15 - description: Synchronous prescaler factor - name: PREDIV_S - - bit_offset: 16 - bit_size: 7 - description: Asynchronous prescaler factor - name: PREDIV_A + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/SHIFTR: description: shift control register fields: - - bit_offset: 0 - bit_size: 15 - description: Subtract a fraction of a second - name: SUBFS - - bit_offset: 31 - bit_size: 1 - description: Add one second - enum_write: ADDSW - name: ADD1S + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 + enum_write: ADDSW fieldset/SSR: description: sub second register fields: - - bit_offset: 0 - bit_size: 16 - description: Sub second value - name: SS + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TAMPCR: description: tamper configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: Tamper 1 detection enable - name: TAMP1E - - bit_offset: 1 - bit_size: 1 - description: Active level for tamper 1 - name: TAMP1TRG - - bit_offset: 2 - bit_size: 1 - description: Tamper interrupt enable - name: TAMPIE - - bit_offset: 3 - bit_size: 1 - description: Tamper 2 detection enable - name: TAMP2E - - bit_offset: 4 - bit_size: 1 - description: Active level for tamper 2 - name: TAMP2TRG - - bit_offset: 5 - bit_size: 1 - description: Tamper 3 detection enable - name: TAMP3E - - bit_offset: 6 - bit_size: 1 - description: Active level for tamper 3 - name: TAMP3TRG - - bit_offset: 7 - bit_size: 1 - description: Activate timestamp on tamper detection event - name: TAMPTS - - bit_offset: 8 - bit_size: 3 - description: Tamper sampling frequency - name: TAMPFREQ - - bit_offset: 11 - bit_size: 2 - description: Tamper filter count - name: TAMPFLT - - bit_offset: 13 - bit_size: 2 - description: Tamper precharge duration - name: TAMPPRCH - - bit_offset: 15 - bit_size: 1 - description: TAMPER pull-up disable - name: TAMPPUDIS - - bit_offset: 16 - bit_size: 1 - description: Tamper 1 interrupt enable - name: TAMP1IE - - bit_offset: 17 - bit_size: 1 - description: Tamper 1 no erase - name: TAMP1NOERASE - - bit_offset: 18 - bit_size: 1 - description: Tamper 1 mask flag - name: TAMP1MF - - bit_offset: 19 - bit_size: 1 - description: Tamper 2 interrupt enable - name: TAMP2IE - - bit_offset: 20 - bit_size: 1 - description: Tamper 2 no erase - name: TAMP2NOERASE - - bit_offset: 21 - bit_size: 1 - description: Tamper 2 mask flag - name: TAMP2MF - - bit_offset: 22 - bit_size: 1 - description: Tamper 3 interrupt enable - name: TAMP3IE - - bit_offset: 23 - bit_size: 1 - description: Tamper 3 no erase - name: TAMP3NOERASE - - bit_offset: 24 - bit_size: 1 - description: Tamper 3 mask flag - name: TAMP3MF + - name: TAMP1E + description: Tamper 1 detection enable + bit_offset: 0 + bit_size: 1 + - name: TAMP1TRG + description: Active level for tamper 1 + bit_offset: 1 + bit_size: 1 + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMP2E + description: Tamper 2 detection enable + bit_offset: 3 + bit_size: 1 + - name: TAMP2TRG + description: Active level for tamper 2 + bit_offset: 4 + bit_size: 1 + - name: TAMP3E + description: Tamper 3 detection enable + bit_offset: 5 + bit_size: 1 + - name: TAMP3TRG + description: Active level for tamper 3 + bit_offset: 6 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + - name: TAMPPUDIS + description: TAMPER pull-up disable + bit_offset: 15 + bit_size: 1 + - name: TAMP1IE + description: Tamper 1 interrupt enable + bit_offset: 16 + bit_size: 1 + - name: TAMP1NOERASE + description: Tamper 1 no erase + bit_offset: 17 + bit_size: 1 + - name: TAMP1MF + description: Tamper 1 mask flag + bit_offset: 18 + bit_size: 1 + - name: TAMP2IE + description: Tamper 2 interrupt enable + bit_offset: 19 + bit_size: 1 + - name: TAMP2NOERASE + description: Tamper 2 no erase + bit_offset: 20 + bit_size: 1 + - name: TAMP2MF + description: Tamper 2 mask flag + bit_offset: 21 + bit_size: 1 + - name: TAMP3IE + description: Tamper 3 interrupt enable + bit_offset: 22 + bit_size: 1 + - name: TAMP3NOERASE + description: Tamper 3 no erase + bit_offset: 23 + bit_size: 1 + - name: TAMP3MF + description: Tamper 3 mask flag + bit_offset: 24 + bit_size: 1 fieldset/TR: description: time register fields: - - bit_offset: 0 - bit_size: 4 - description: Second units in BCD format - name: SU - - bit_offset: 4 - bit_size: 3 - description: Second tens in BCD format - name: ST - - bit_offset: 8 - bit_size: 4 - description: Minute units in BCD format - name: MNU - - bit_offset: 12 - bit_size: 3 - description: Minute tens in BCD format - name: MNT - - bit_offset: 16 - bit_size: 4 - description: Hour units in BCD format - name: HU - - bit_offset: 20 - bit_size: 2 - description: Hour tens in BCD format - name: HT - - bit_offset: 22 - bit_size: 1 - description: AM/PM notation - enum: TR_PM - name: PM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: TR_PM fieldset/TSDR: description: time stamp date register fields: - - bit_offset: 0 - bit_size: 4 - description: Date units in BCD format - name: DU - - bit_offset: 4 - bit_size: 2 - description: Date tens in BCD format - name: DT - - bit_offset: 8 - bit_size: 4 - description: Month units in BCD format - name: MU - - bit_offset: 12 - bit_size: 1 - description: Month tens in BCD format - name: MT - - bit_offset: 13 - bit_size: 3 - description: Week day units - name: WDU + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSSSR: description: timestamp sub second register fields: - - bit_offset: 0 - bit_size: 16 - description: Sub second value - name: SS + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TSTR: description: time stamp time register fields: - - bit_offset: 0 - bit_size: 4 - description: Second units in BCD format - name: SU - - bit_offset: 4 - bit_size: 3 - description: Second tens in BCD format - name: ST - - bit_offset: 8 - bit_size: 4 - description: Minute units in BCD format - name: MNU - - bit_offset: 12 - bit_size: 3 - description: Minute tens in BCD format - name: MNT - - bit_offset: 16 - bit_size: 4 - description: Hour units in BCD format - name: HU - - bit_offset: 20 - bit_size: 2 - description: Hour tens in BCD format - name: HT - - bit_offset: 22 - bit_size: 1 - description: AM/PM notation - name: PM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 fieldset/WPR: description: write protection register fields: - - bit_offset: 0 - bit_size: 8 - description: Write protection key - name: KEY + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 fieldset/WUTR: description: wakeup timer register fields: - - bit_offset: 0 - bit_size: 16 - description: Wakeup auto-reload value bits - name: WUT + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 +enum/ADDHW: + bit_size: 1 + variants: + - name: Add1 + description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode + value: 1 +enum/ADDSW: + bit_size: 1 + variants: + - name: Add1 + description: Add one second to the clock/calendar + value: 1 +enum/ALRAE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A disabled + value: 0 + - name: Enabled + description: Alarm A enabled + value: 1 +enum/ALRAFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRAFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRAIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A interrupt disabled + value: 0 + - name: Enabled + description: Alarm A interrupt enabled + value: 1 +enum/ALRAWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRBE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B disabled + value: 0 + - name: Enabled + description: Alarm B enabled + value: 1 +enum/ALRBFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) + value: 1 +enum/ALRBFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRBIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B Interrupt disabled + value: 0 + - name: Enabled + description: Alarm B Interrupt enabled + value: 1 +enum/ALRMAR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMAR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMAR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/ALRMBR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMBR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMBR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: DST_Not_Changed + description: Daylight Saving Time change has not been performed + value: 0 + - name: DST_Changed + description: Daylight Saving Time change has been performed + value: 1 +enum/BYPSHAD: + bit_size: 1 + variants: + - name: ShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" + value: 0 + - name: BypassShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" + value: 1 +enum/COE: + bit_size: 1 + variants: + - name: Disabled + description: Calibration output disabled + value: 0 + - name: Enabled + description: Calibration output enabled + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 0 + - name: Low + description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/SHPFR: + bit_size: 1 + variants: + - name: NoShiftPending + description: No shift operation is pending + value: 0 + - name: ShiftPending + description: A shift operation is pending + value: 1 +enum/SUBHW: + bit_size: 1 + variants: + - name: Sub1 + description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode + value: 1 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSE: + bit_size: 1 + variants: + - name: Disabled + description: Timestamp disabled + value: 0 + - name: Enabled + description: Timestamp enabled + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSIE: + bit_size: 1 + variants: + - name: Disabled + description: Time-stamp Interrupt disabled + value: 0 + - name: Enabled + description: Time-stamp Interrupt enabled + value: 1 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer disabled + value: 0 + - name: Enabled + description: Wakeup timer enabled + value: 1 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTIE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer interrupt disabled + value: 0 + - name: Enabled + description: Wakeup timer interrupt enabled + value: 1 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/sai_v1.yaml b/data/registers/sai_v1.yaml index fda1c7f..16df2f7 100644 --- a/data/registers/sai_v1.yaml +++ b/data/registers/sai_v1.yaml @@ -1,755 +1,744 @@ --- block/CH: - description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, - ?DR + description: "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR" items: - - byte_offset: 0 - description: AConfiguration register 1 - fieldset: CR1 - name: CR1 - - byte_offset: 4 - description: AConfiguration register 2 - fieldset: CR2 - name: CR2 - - byte_offset: 8 - description: AFRCR - fieldset: FRCR - name: FRCR - - byte_offset: 12 - description: ASlot register - fieldset: SLOTR - name: SLOTR - - byte_offset: 16 - description: AInterrupt mask register2 - fieldset: IM - name: IM - - access: Read - byte_offset: 20 - description: AStatus register - fieldset: SR - name: SR - - access: Write - byte_offset: 24 - description: AClear flag register - fieldset: CLRFR - name: CLRFR - - byte_offset: 28 - description: AData register - fieldset: DR - name: DR + - name: CR1 + description: AConfiguration register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: AConfiguration register 2 + byte_offset: 4 + fieldset: CR2 + - name: FRCR + description: AFRCR + byte_offset: 8 + fieldset: FRCR + - name: SLOTR + description: ASlot register + byte_offset: 12 + fieldset: SLOTR + - name: IM + description: AInterrupt mask register2 + byte_offset: 16 + fieldset: IM + - name: SR + description: AStatus register + byte_offset: 20 + access: Read + fieldset: SR + - name: CLRFR + description: AClear flag register + byte_offset: 24 + access: Write + fieldset: CLRFR + - name: DR + description: AData register + byte_offset: 28 + fieldset: DR block/SAI: description: Serial audio interface items: - - byte_offset: 0 - description: Global configuration register - fieldset: GCR - name: GCR - - array: - len: 2 - stride: 32 - block: CH - byte_offset: 4 - description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, - ?DR - name: CH -enum/AFSDETIE: - bit_size: 1 - variants: - - description: Interrupt is disabled - name: Disabled - value: 0 - - description: Interrupt is enabled - name: Enabled - value: 1 -enum/AFSDETR: - bit_size: 1 - variants: - - description: No error - name: NoError - value: 0 - - description: Frame synchronization signal is detected earlier than expected - name: EarlySync - value: 1 -enum/CAFSDETW: - bit_size: 1 - variants: - - description: Clears the AFSDET flag - name: Clear - value: 1 -enum/CCNRDYW: - bit_size: 1 - variants: - - description: Clears the CNRDY flag - name: Clear - value: 1 -enum/CKSTR: - bit_size: 1 - variants: - - description: Data strobing edge is falling edge of SCK - name: FallingEdge - value: 0 - - description: Data strobing edge is rising edge of SCK - name: RisingEdge - value: 1 -enum/CLFSDETW: - bit_size: 1 - variants: - - description: Clears the LFSDET flag - name: Clear - value: 1 -enum/CMUTEDETW: - bit_size: 1 - variants: - - description: Clears the MUTEDET flag - name: Clear - value: 1 -enum/CNRDYIE: - bit_size: 1 - variants: - - description: Interrupt is disabled - name: Disabled - value: 0 - - description: Interrupt is enabled - name: Enabled - value: 1 -enum/CNRDYR: - bit_size: 1 - variants: - - description: "External AC\u201997 Codec is ready" - name: Ready - value: 0 - - description: "External AC\u201997 Codec is not ready" - name: NotReady - value: 1 -enum/COMP: - bit_size: 2 - variants: - - description: No companding algorithm - name: NoCompanding - value: 0 - - description: "\u03BC-Law algorithm" - name: MuLaw - value: 2 - - description: A-Law algorithm - name: ALaw - value: 3 -enum/COVRUDRW: - bit_size: 1 - variants: - - description: Clears the OVRUDR flag - name: Clear - value: 1 -enum/CPL: - bit_size: 1 - variants: - - description: "1\u2019s complement representation" - name: OnesComplement - value: 0 - - description: "2\u2019s complement representation" - name: TwosComplement - value: 1 -enum/CWCKCFGW: - bit_size: 1 - variants: - - description: Clears the WCKCFG flag - name: Clear - value: 1 -enum/DMAEN: - bit_size: 1 - variants: - - description: DMA disabled - name: Disabled - value: 0 - - description: DMA enabled - name: Enabled - value: 1 -enum/DS: - bit_size: 3 - variants: - - description: 8 bits - name: Bit8 - value: 2 - - description: 10 bits - name: Bit10 - value: 3 - - description: 16 bits - name: Bit16 - value: 4 - - description: 20 bits - name: Bit20 - value: 5 - - description: 24 bits - name: Bit24 - value: 6 - - description: 32 bits - name: Bit32 - value: 7 -enum/FFLUSH: - bit_size: 1 - variants: - - description: No FIFO flush - name: NoFlush - value: 0 - - description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All - the internal FIFO pointers (read and write) are cleared - name: Flush - value: 1 -enum/FLVLR: - bit_size: 3 - variants: - - description: FIFO empty - name: Empty - value: 0 - - description: "FIFO <= 1\u20444 but not empty" - name: Quarter1 - value: 1 - - description: "1\u20444 < FIFO <= 1\u20442" - name: Quarter2 - value: 2 - - description: "1\u20442 < FIFO <= 3\u20444" - name: Quarter3 - value: 3 - - description: "3\u20444 < FIFO but not full" - name: Quarter4 - value: 4 - - description: FIFO full - name: Full - value: 5 -enum/FREQIE: - bit_size: 1 - variants: - - description: Interrupt is disabled - name: Disabled - value: 0 - - description: Interrupt is enabled - name: Enabled - value: 1 -enum/FREQR: - bit_size: 1 - variants: - - description: No FIFO request - name: NoRequest - value: 0 - - description: FIFO request to read or to write the SAI_xDR - name: Request - value: 1 -enum/FSOFF: - bit_size: 1 - variants: - - description: FS is asserted on the first bit of the slot 0 - name: OnFirst - value: 0 - - description: FS is asserted one bit before the first bit of the slot 0 - name: BeforeFirst - value: 1 -enum/FSPOL: - bit_size: 1 - variants: - - description: FS is active low (falling edge) - name: FallingEdge - value: 0 - - description: FS is active high (rising edge) - name: RisingEdge - value: 1 -enum/FTH: - bit_size: 3 - variants: - - description: FIFO empty - name: Empty - value: 0 - - description: "1\u20444 FIFO" - name: Quarter1 - value: 1 - - description: "1\u20442 FIFO" - name: Quarter2 - value: 2 - - description: "3\u20444 FIFO" - name: Quarter3 - value: 3 - - description: FIFO full - name: Full - value: 4 -enum/LFSDETIE: - bit_size: 1 - variants: - - description: Interrupt is disabled - name: Disabled - value: 0 - - description: Interrupt is enabled - name: Enabled - value: 1 -enum/LFSDETR: - bit_size: 1 - variants: - - description: No error - name: NoError - value: 0 - - description: Frame synchronization signal is not present at the right time - name: NoSync - value: 1 -enum/LSBFIRST: - bit_size: 1 - variants: - - description: Data are transferred with MSB first - name: MsbFirst - value: 0 - - description: Data are transferred with LSB first - name: LsbFirst - value: 1 -enum/MODE: - bit_size: 2 - variants: - - description: Master transmitter - name: MasterTx - value: 0 - - description: Master receiver - name: MasterRx - value: 1 - - description: Slave transmitter - name: SlaveTx - value: 2 - - description: Slave receiver - name: SlaveRx - value: 3 -enum/MONO: - bit_size: 1 - variants: - - description: Stereo mode - name: Stereo - value: 0 - - description: Mono mode - name: Mono - value: 1 -enum/MUTE: - bit_size: 1 - variants: - - description: No mute mode - name: Disabled - value: 0 - - description: Mute mode enabled - name: Enabled - value: 1 -enum/MUTEDETIE: - bit_size: 1 - variants: - - description: Interrupt is disabled - name: Disabled - value: 0 - - description: Interrupt is enabled - name: Enabled - value: 1 -enum/MUTEDETR: - bit_size: 1 - variants: - - description: No MUTE detection on the SD input line - name: NoMute - value: 0 - - description: MUTE value detected on the SD input line (0 value) for a specified - number of consecutive audio frame - name: Mute - value: 1 -enum/MUTEVAL: - bit_size: 1 - variants: - - description: Bit value 0 is sent during the mute mode - name: SendZero - value: 0 - - description: Last values are sent during the mute mode - name: SendLast - value: 1 -enum/NODIV: - bit_size: 1 - variants: - - description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 - or 512 according to the OSR value - name: MasterClock - value: 0 - - description: MCLK output enable set by the MCKEN bit (where present, else 0). - Ratio between FS and MCLK depends on FRL. - name: NoDiv - value: 1 -enum/OUTDRIV: - bit_size: 1 - variants: - - description: Audio block output driven when SAIEN is set - name: OnStart - value: 0 - - description: Audio block output driven immediately after the setting of this bit - name: Immediately - value: 1 -enum/OVRUDRIE: - bit_size: 1 - variants: - - description: Interrupt is disabled - name: Disabled - value: 0 - - description: Interrupt is enabled - name: Enabled - value: 1 -enum/OVRUDRR: - bit_size: 1 - variants: - - description: No overrun/underrun error - name: NoError - value: 0 - - description: Overrun/underrun error detection - name: Overrun - value: 1 -enum/PRTCFG: - bit_size: 2 - variants: - - description: Free protocol. Free protocol allows to use the powerful configuration - of the audio block to address a specific audio protocol - name: Free - value: 0 - - description: SPDIF protocol - name: Spdif - value: 1 - - description: "AC\u201997 protocol" - name: Ac97 - value: 2 -enum/SAIEN: - bit_size: 1 - variants: - - description: SAI audio block disabled - name: Disabled - value: 0 - - description: SAI audio block enabled - name: Enabled - value: 1 -enum/SLOTEN: - bit_size: 16 - variants: - - description: Inactive slot - name: Inactive - value: 0 - - description: Active slot - name: Active - value: 1 -enum/SLOTSZ: - bit_size: 2 - variants: - - description: The slot size is equivalent to the data size (specified in DS[3:0] - in the SAI_xCR1 register) - name: DataSize - value: 0 - - description: 16-bit - name: Bit16 - value: 1 - - description: 32-bit - name: Bit32 - value: 2 -enum/SYNCEN: - bit_size: 2 - variants: - - description: audio sub-block in asynchronous mode - name: Asynchronous - value: 0 - - description: audio sub-block is synchronous with the other internal audio sub-block. - In this case, the audio sub-block must be configured in slave mode - name: Internal - value: 1 - - description: audio sub-block is synchronous with an external SAI embedded peripheral. - In this case the audio sub-block should be configured in Slave mode - name: External - value: 2 -enum/WCKCFGIE: - bit_size: 1 - variants: - - description: Interrupt is disabled - name: Disabled - value: 0 - - description: Interrupt is enabled - name: Enabled - value: 1 -enum/WCKCFGR: - bit_size: 1 - variants: - - description: Clock configuration is correct - name: Correct - value: 0 - - description: Clock configuration does not respect the rule concerning the frame - length specification - name: Wrong - value: 1 + - name: GCR + description: Global configuration register + byte_offset: 0 + fieldset: GCR + - name: CH + description: "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR" + array: + len: 2 + stride: 32 + byte_offset: 4 + block: CH fieldset/CLRFR: description: AClear flag register fields: - - bit_offset: 0 - bit_size: 1 - description: Clear overrun / underrun - enum_write: COVRUDRW - name: COVRUDR - - bit_offset: 1 - bit_size: 1 - description: Mute detection flag - enum_write: CMUTEDETW - name: CMUTEDET - - bit_offset: 2 - bit_size: 1 - description: Clear wrong clock configuration flag - enum_write: CWCKCFGW - name: CWCKCFG - - bit_offset: 4 - bit_size: 1 - description: Clear codec not ready flag - enum_write: CCNRDYW - name: CCNRDY - - bit_offset: 5 - bit_size: 1 - description: Clear anticipated frame synchronization detection flag. - enum_write: CAFSDETW - name: CAFSDET - - bit_offset: 6 - bit_size: 1 - description: Clear late frame synchronization detection flag - enum_write: CLFSDETW - name: CLFSDET + - name: COVRUDR + description: Clear overrun / underrun + bit_offset: 0 + bit_size: 1 + enum_write: COVRUDRW + - name: CMUTEDET + description: Mute detection flag + bit_offset: 1 + bit_size: 1 + enum_write: CMUTEDETW + - name: CWCKCFG + description: Clear wrong clock configuration flag + bit_offset: 2 + bit_size: 1 + enum_write: CWCKCFGW + - name: CCNRDY + description: Clear codec not ready flag + bit_offset: 4 + bit_size: 1 + enum_write: CCNRDYW + - name: CAFSDET + description: Clear anticipated frame synchronization detection flag. + bit_offset: 5 + bit_size: 1 + enum_write: CAFSDETW + - name: CLFSDET + description: Clear late frame synchronization detection flag + bit_offset: 6 + bit_size: 1 + enum_write: CLFSDETW fieldset/CR1: description: AConfiguration register 1 fields: - - bit_offset: 0 - bit_size: 2 - description: Audio block mode - enum: MODE - name: MODE - - bit_offset: 2 - bit_size: 2 - description: Protocol configuration - enum: PRTCFG - name: PRTCFG - - bit_offset: 5 - bit_size: 3 - description: Data size - enum: DS - name: DS - - bit_offset: 8 - bit_size: 1 - description: Least significant bit first - enum: LSBFIRST - name: LSBFIRST - - bit_offset: 9 - bit_size: 1 - description: Clock strobing edge - enum: CKSTR - name: CKSTR - - bit_offset: 10 - bit_size: 2 - description: Synchronization enable - enum: SYNCEN - name: SYNCEN - - bit_offset: 12 - bit_size: 1 - description: Mono mode - enum: MONO - name: MONO - - bit_offset: 13 - bit_size: 1 - description: Output drive - enum: OUTDRIV - name: OUTDRIV - - bit_offset: 16 - bit_size: 1 - description: Audio block A enable - enum: SAIEN - name: SAIEN - - bit_offset: 17 - bit_size: 1 - description: DMA enable - enum: DMAEN - name: DMAEN - - bit_offset: 19 - bit_size: 1 - description: No divider - enum: NODIV - name: NODIV - - bit_offset: 20 - bit_size: 4 - description: Master clock divider - name: MCKDIV + - name: MODE + description: Audio block mode + bit_offset: 0 + bit_size: 2 + enum: MODE + - name: PRTCFG + description: Protocol configuration + bit_offset: 2 + bit_size: 2 + enum: PRTCFG + - name: DS + description: Data size + bit_offset: 5 + bit_size: 3 + enum: DS + - name: LSBFIRST + description: Least significant bit first + bit_offset: 8 + bit_size: 1 + enum: LSBFIRST + - name: CKSTR + description: Clock strobing edge + bit_offset: 9 + bit_size: 1 + enum: CKSTR + - name: SYNCEN + description: Synchronization enable + bit_offset: 10 + bit_size: 2 + enum: SYNCEN + - name: MONO + description: Mono mode + bit_offset: 12 + bit_size: 1 + enum: MONO + - name: OUTDRIV + description: Output drive + bit_offset: 13 + bit_size: 1 + enum: OUTDRIV + - name: SAIEN + description: Audio block A enable + bit_offset: 16 + bit_size: 1 + enum: SAIEN + - name: DMAEN + description: DMA enable + bit_offset: 17 + bit_size: 1 + enum: DMAEN + - name: NODIV + description: No divider + bit_offset: 19 + bit_size: 1 + enum: NODIV + - name: MCKDIV + description: Master clock divider + bit_offset: 20 + bit_size: 4 fieldset/CR2: description: AConfiguration register 2 fields: - - bit_offset: 0 - bit_size: 3 - description: FIFO threshold - enum: FTH - name: FTH - - bit_offset: 3 - bit_size: 1 - description: FIFO flush - enum: FFLUSH - name: FFLUSH - - bit_offset: 4 - bit_size: 1 - description: Tristate management on data line - name: TRIS - - bit_offset: 5 - bit_size: 1 - description: Mute - enum: MUTE - name: MUTE - - bit_offset: 6 - bit_size: 1 - description: Mute value - enum: MUTEVAL - name: MUTEVAL - - bit_offset: 7 - bit_size: 6 - description: Mute counter - name: MUTECN - - bit_offset: 13 - bit_size: 1 - description: Complement bit - enum: CPL - name: CPL - - bit_offset: 14 - bit_size: 2 - description: Companding mode - enum: COMP - name: COMP + - name: FTH + description: FIFO threshold + bit_offset: 0 + bit_size: 3 + enum: FTH + - name: FFLUSH + description: FIFO flush + bit_offset: 3 + bit_size: 1 + enum: FFLUSH + - name: TRIS + description: Tristate management on data line + bit_offset: 4 + bit_size: 1 + - name: MUTE + description: Mute + bit_offset: 5 + bit_size: 1 + enum: MUTE + - name: MUTEVAL + description: Mute value + bit_offset: 6 + bit_size: 1 + enum: MUTEVAL + - name: MUTECN + description: Mute counter + bit_offset: 7 + bit_size: 6 + - name: CPL + description: Complement bit + bit_offset: 13 + bit_size: 1 + enum: CPL + - name: COMP + description: Companding mode + bit_offset: 14 + bit_size: 2 + enum: COMP fieldset/DR: description: AData register fields: - - bit_offset: 0 - bit_size: 32 - description: Data - name: DATA + - name: DATA + description: Data + bit_offset: 0 + bit_size: 32 fieldset/FRCR: description: AFRCR fields: - - bit_offset: 0 - bit_size: 8 - description: Frame length - name: FRL - - bit_offset: 8 - bit_size: 7 - description: Frame synchronization active level length - name: FSALL - - bit_offset: 16 - bit_size: 1 - description: Frame synchronization definition - name: FSDEF - - bit_offset: 17 - bit_size: 1 - description: Frame synchronization polarity - enum: FSPOL - name: FSPOL - - bit_offset: 18 - bit_size: 1 - description: Frame synchronization offset - enum: FSOFF - name: FSOFF + - name: FRL + description: Frame length + bit_offset: 0 + bit_size: 8 + - name: FSALL + description: Frame synchronization active level length + bit_offset: 8 + bit_size: 7 + - name: FSDEF + description: Frame synchronization definition + bit_offset: 16 + bit_size: 1 + - name: FSPOL + description: Frame synchronization polarity + bit_offset: 17 + bit_size: 1 + enum: FSPOL + - name: FSOFF + description: Frame synchronization offset + bit_offset: 18 + bit_size: 1 + enum: FSOFF fieldset/GCR: description: Global configuration register fields: - - bit_offset: 0 - bit_size: 2 - description: Synchronization inputs - name: SYNCIN - - bit_offset: 4 - bit_size: 2 - description: Synchronization outputs - name: SYNCOUT + - name: SYNCIN + description: Synchronization inputs + bit_offset: 0 + bit_size: 2 + - name: SYNCOUT + description: Synchronization outputs + bit_offset: 4 + bit_size: 2 fieldset/IM: description: AInterrupt mask register2 fields: - - bit_offset: 0 - bit_size: 1 - description: Overrun/underrun interrupt enable - enum: OVRUDRIE - name: OVRUDRIE - - bit_offset: 1 - bit_size: 1 - description: Mute detection interrupt enable - enum: MUTEDETIE - name: MUTEDETIE - - bit_offset: 2 - bit_size: 1 - description: Wrong clock configuration interrupt enable - enum: WCKCFGIE - name: WCKCFGIE - - bit_offset: 3 - bit_size: 1 - description: FIFO request interrupt enable - enum: FREQIE - name: FREQIE - - bit_offset: 4 - bit_size: 1 - description: Codec not ready interrupt enable - enum: CNRDYIE - name: CNRDYIE - - bit_offset: 5 - bit_size: 1 - description: Anticipated frame synchronization detection interrupt enable - enum: AFSDETIE - name: AFSDETIE - - bit_offset: 6 - bit_size: 1 - description: Late frame synchronization detection interrupt enable - enum: LFSDETIE - name: LFSDETIE + - name: OVRUDRIE + description: Overrun/underrun interrupt enable + bit_offset: 0 + bit_size: 1 + enum: OVRUDRIE + - name: MUTEDETIE + description: Mute detection interrupt enable + bit_offset: 1 + bit_size: 1 + enum: MUTEDETIE + - name: WCKCFGIE + description: Wrong clock configuration interrupt enable + bit_offset: 2 + bit_size: 1 + enum: WCKCFGIE + - name: FREQIE + description: FIFO request interrupt enable + bit_offset: 3 + bit_size: 1 + enum: FREQIE + - name: CNRDYIE + description: Codec not ready interrupt enable + bit_offset: 4 + bit_size: 1 + enum: CNRDYIE + - name: AFSDETIE + description: Anticipated frame synchronization detection interrupt enable + bit_offset: 5 + bit_size: 1 + enum: AFSDETIE + - name: LFSDETIE + description: Late frame synchronization detection interrupt enable + bit_offset: 6 + bit_size: 1 + enum: LFSDETIE fieldset/SLOTR: description: ASlot register fields: - - bit_offset: 0 - bit_size: 5 - description: First bit offset - name: FBOFF - - bit_offset: 6 - bit_size: 2 - description: Slot size - enum: SLOTSZ - name: SLOTSZ - - bit_offset: 8 - bit_size: 4 - description: Number of slots in an audio frame - name: NBSLOT - - bit_offset: 16 - bit_size: 16 - description: Slot enable - enum: SLOTEN - name: SLOTEN + - name: FBOFF + description: First bit offset + bit_offset: 0 + bit_size: 5 + - name: SLOTSZ + description: Slot size + bit_offset: 6 + bit_size: 2 + enum: SLOTSZ + - name: NBSLOT + description: Number of slots in an audio frame + bit_offset: 8 + bit_size: 4 + - name: SLOTEN + description: Slot enable + bit_offset: 16 + bit_size: 16 + enum: SLOTEN fieldset/SR: description: AStatus register fields: - - bit_offset: 0 - bit_size: 1 - description: Overrun / underrun - enum_read: OVRUDRR - name: OVRUDR - - bit_offset: 1 - bit_size: 1 - description: Mute detection - enum_read: MUTEDETR - name: MUTEDET - - bit_offset: 2 - bit_size: 1 - description: Wrong clock configuration flag. This bit is read only. - enum_read: WCKCFGR - name: WCKCFG - - bit_offset: 3 - bit_size: 1 - description: FIFO request - enum_read: FREQR - name: FREQ - - bit_offset: 4 - bit_size: 1 - description: Codec not ready - enum_read: CNRDYR - name: CNRDY - - bit_offset: 5 - bit_size: 1 - description: Anticipated frame synchronization detection - enum_read: AFSDETR - name: AFSDET - - bit_offset: 6 - bit_size: 1 - description: Late frame synchronization detection - enum_read: LFSDETR - name: LFSDET - - bit_offset: 16 - bit_size: 3 - description: FIFO level threshold - enum_read: FLVLR - name: FLVL + - name: OVRUDR + description: Overrun / underrun + bit_offset: 0 + bit_size: 1 + enum_read: OVRUDRR + - name: MUTEDET + description: Mute detection + bit_offset: 1 + bit_size: 1 + enum_read: MUTEDETR + - name: WCKCFG + description: Wrong clock configuration flag. This bit is read only. + bit_offset: 2 + bit_size: 1 + enum_read: WCKCFGR + - name: FREQ + description: FIFO request + bit_offset: 3 + bit_size: 1 + enum_read: FREQR + - name: CNRDY + description: Codec not ready + bit_offset: 4 + bit_size: 1 + enum_read: CNRDYR + - name: AFSDET + description: Anticipated frame synchronization detection + bit_offset: 5 + bit_size: 1 + enum_read: AFSDETR + - name: LFSDET + description: Late frame synchronization detection + bit_offset: 6 + bit_size: 1 + enum_read: LFSDETR + - name: FLVL + description: FIFO level threshold + bit_offset: 16 + bit_size: 3 + enum_read: FLVLR +enum/AFSDETIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled + value: 0 + - name: Enabled + description: Interrupt is enabled + value: 1 +enum/AFSDETR: + bit_size: 1 + variants: + - name: NoError + description: No error + value: 0 + - name: EarlySync + description: Frame synchronization signal is detected earlier than expected + value: 1 +enum/CAFSDETW: + bit_size: 1 + variants: + - name: Clear + description: Clears the AFSDET flag + value: 1 +enum/CCNRDYW: + bit_size: 1 + variants: + - name: Clear + description: Clears the CNRDY flag + value: 1 +enum/CKSTR: + bit_size: 1 + variants: + - name: FallingEdge + description: Data strobing edge is falling edge of SCK + value: 0 + - name: RisingEdge + description: Data strobing edge is rising edge of SCK + value: 1 +enum/CLFSDETW: + bit_size: 1 + variants: + - name: Clear + description: Clears the LFSDET flag + value: 1 +enum/CMUTEDETW: + bit_size: 1 + variants: + - name: Clear + description: Clears the MUTEDET flag + value: 1 +enum/CNRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled + value: 0 + - name: Enabled + description: Interrupt is enabled + value: 1 +enum/CNRDYR: + bit_size: 1 + variants: + - name: Ready + description: External AC’97 Codec is ready + value: 0 + - name: NotReady + description: External AC’97 Codec is not ready + value: 1 +enum/COMP: + bit_size: 2 + variants: + - name: NoCompanding + description: No companding algorithm + value: 0 + - name: MuLaw + description: μ-Law algorithm + value: 2 + - name: ALaw + description: A-Law algorithm + value: 3 +enum/COVRUDRW: + bit_size: 1 + variants: + - name: Clear + description: Clears the OVRUDR flag + value: 1 +enum/CPL: + bit_size: 1 + variants: + - name: OnesComplement + description: 1’s complement representation + value: 0 + - name: TwosComplement + description: 2’s complement representation + value: 1 +enum/CWCKCFGW: + bit_size: 1 + variants: + - name: Clear + description: Clears the WCKCFG flag + value: 1 +enum/DMAEN: + bit_size: 1 + variants: + - name: Disabled + description: DMA disabled + value: 0 + - name: Enabled + description: DMA enabled + value: 1 +enum/DS: + bit_size: 3 + variants: + - name: Bit8 + description: 8 bits + value: 2 + - name: Bit10 + description: 10 bits + value: 3 + - name: Bit16 + description: 16 bits + value: 4 + - name: Bit20 + description: 20 bits + value: 5 + - name: Bit24 + description: 24 bits + value: 6 + - name: Bit32 + description: 32 bits + value: 7 +enum/FFLUSH: + bit_size: 1 + variants: + - name: NoFlush + description: No FIFO flush + value: 0 + - name: Flush + description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared + value: 1 +enum/FLVLR: + bit_size: 3 + variants: + - name: Empty + description: FIFO empty + value: 0 + - name: Quarter1 + description: FIFO <= 1⁄4 but not empty + value: 1 + - name: Quarter2 + description: 1⁄4 < FIFO <= 1⁄2 + value: 2 + - name: Quarter3 + description: 1⁄2 < FIFO <= 3⁄4 + value: 3 + - name: Quarter4 + description: 3⁄4 < FIFO but not full + value: 4 + - name: Full + description: FIFO full + value: 5 +enum/FREQIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled + value: 0 + - name: Enabled + description: Interrupt is enabled + value: 1 +enum/FREQR: + bit_size: 1 + variants: + - name: NoRequest + description: No FIFO request + value: 0 + - name: Request + description: FIFO request to read or to write the SAI_xDR + value: 1 +enum/FSOFF: + bit_size: 1 + variants: + - name: OnFirst + description: FS is asserted on the first bit of the slot 0 + value: 0 + - name: BeforeFirst + description: FS is asserted one bit before the first bit of the slot 0 + value: 1 +enum/FSPOL: + bit_size: 1 + variants: + - name: FallingEdge + description: FS is active low (falling edge) + value: 0 + - name: RisingEdge + description: FS is active high (rising edge) + value: 1 +enum/FTH: + bit_size: 3 + variants: + - name: Empty + description: FIFO empty + value: 0 + - name: Quarter1 + description: 1⁄4 FIFO + value: 1 + - name: Quarter2 + description: 1⁄2 FIFO + value: 2 + - name: Quarter3 + description: 3⁄4 FIFO + value: 3 + - name: Full + description: FIFO full + value: 4 +enum/LFSDETIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled + value: 0 + - name: Enabled + description: Interrupt is enabled + value: 1 +enum/LFSDETR: + bit_size: 1 + variants: + - name: NoError + description: No error + value: 0 + - name: NoSync + description: Frame synchronization signal is not present at the right time + value: 1 +enum/LSBFIRST: + bit_size: 1 + variants: + - name: MsbFirst + description: Data are transferred with MSB first + value: 0 + - name: LsbFirst + description: Data are transferred with LSB first + value: 1 +enum/MODE: + bit_size: 2 + variants: + - name: MasterTx + description: Master transmitter + value: 0 + - name: MasterRx + description: Master receiver + value: 1 + - name: SlaveTx + description: Slave transmitter + value: 2 + - name: SlaveRx + description: Slave receiver + value: 3 +enum/MONO: + bit_size: 1 + variants: + - name: Stereo + description: Stereo mode + value: 0 + - name: Mono + description: Mono mode + value: 1 +enum/MUTE: + bit_size: 1 + variants: + - name: Disabled + description: No mute mode + value: 0 + - name: Enabled + description: Mute mode enabled + value: 1 +enum/MUTEDETIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled + value: 0 + - name: Enabled + description: Interrupt is enabled + value: 1 +enum/MUTEDETR: + bit_size: 1 + variants: + - name: NoMute + description: No MUTE detection on the SD input line + value: 0 + - name: Mute + description: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame + value: 1 +enum/MUTEVAL: + bit_size: 1 + variants: + - name: SendZero + description: Bit value 0 is sent during the mute mode + value: 0 + - name: SendLast + description: Last values are sent during the mute mode + value: 1 +enum/NODIV: + bit_size: 1 + variants: + - name: MasterClock + description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value + value: 0 + - name: NoDiv + description: "MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL." + value: 1 +enum/OUTDRIV: + bit_size: 1 + variants: + - name: OnStart + description: Audio block output driven when SAIEN is set + value: 0 + - name: Immediately + description: Audio block output driven immediately after the setting of this bit + value: 1 +enum/OVRUDRIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled + value: 0 + - name: Enabled + description: Interrupt is enabled + value: 1 +enum/OVRUDRR: + bit_size: 1 + variants: + - name: NoError + description: No overrun/underrun error + value: 0 + - name: Overrun + description: Overrun/underrun error detection + value: 1 +enum/PRTCFG: + bit_size: 2 + variants: + - name: Free + description: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol + value: 0 + - name: Spdif + description: SPDIF protocol + value: 1 + - name: Ac97 + description: AC’97 protocol + value: 2 +enum/SAIEN: + bit_size: 1 + variants: + - name: Disabled + description: SAI audio block disabled + value: 0 + - name: Enabled + description: SAI audio block enabled + value: 1 +enum/SLOTEN: + bit_size: 16 + variants: + - name: Inactive + description: Inactive slot + value: 0 + - name: Active + description: Active slot + value: 1 +enum/SLOTSZ: + bit_size: 2 + variants: + - name: DataSize + description: "The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)" + value: 0 + - name: Bit16 + description: 16-bit + value: 1 + - name: Bit32 + description: 32-bit + value: 2 +enum/SYNCEN: + bit_size: 2 + variants: + - name: Asynchronous + description: audio sub-block in asynchronous mode + value: 0 + - name: Internal + description: "audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode" + value: 1 + - name: External + description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode + value: 2 +enum/WCKCFGIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled + value: 0 + - name: Enabled + description: Interrupt is enabled + value: 1 +enum/WCKCFGR: + bit_size: 1 + variants: + - name: Correct + description: Clock configuration is correct + value: 0 + - name: Wrong + description: Clock configuration does not respect the rule concerning the frame length specification + value: 1 diff --git a/data/registers/sdmmc_v1.yaml b/data/registers/sdmmc_v1.yaml index 81c7d32..0b61054 100644 --- a/data/registers/sdmmc_v1.yaml +++ b/data/registers/sdmmc_v1.yaml @@ -2,506 +2,505 @@ block/SDMMC: description: Secure digital input/output interface items: - - byte_offset: 0 - description: power control register - fieldset: POWER - name: POWER - - byte_offset: 4 - description: SDI clock control register - fieldset: CLKCR - name: CLKCR - - byte_offset: 8 - description: argument register - fieldset: ARG - name: ARG - - byte_offset: 12 - description: command register - fieldset: CMD - name: CMD - - access: Read - byte_offset: 16 - description: command response register - fieldset: RESPCMD - name: RESPCMD - - access: Read - byte_offset: 20 - description: response 1..4 register - fieldset: RESP1 - name: RESP1 - - access: Read - byte_offset: 24 - description: response 1..4 register - fieldset: RESP2 - name: RESP2 - - access: Read - byte_offset: 28 - description: response 1..4 register - fieldset: RESP3 - name: RESP3 - - access: Read - byte_offset: 32 - description: response 1..4 register - fieldset: RESP4 - name: RESP4 - - byte_offset: 36 - description: data timer register - fieldset: DTIMER - name: DTIMER - - byte_offset: 40 - description: data length register - fieldset: DLEN - name: DLEN - - byte_offset: 44 - description: data control register - fieldset: DCTRL - name: DCTRL - - access: Read - byte_offset: 48 - description: data counter register - fieldset: DCOUNT - name: DCOUNT - - access: Read - byte_offset: 52 - description: status register - fieldset: STA - name: STA - - byte_offset: 56 - description: interrupt clear register - fieldset: ICR - name: ICR - - byte_offset: 60 - description: mask register - fieldset: MASK - name: MASK - - access: Read - byte_offset: 72 - description: FIFO counter register - fieldset: FIFOCNT - name: FIFOCNT - - byte_offset: 128 - description: data FIFO register - fieldset: FIFO - name: FIFO + - name: POWER + description: power control register + byte_offset: 0 + fieldset: POWER + - name: CLKCR + description: SDI clock control register + byte_offset: 4 + fieldset: CLKCR + - name: ARG + description: argument register + byte_offset: 8 + fieldset: ARG + - name: CMD + description: command register + byte_offset: 12 + fieldset: CMD + - name: RESPCMD + description: command response register + byte_offset: 16 + access: Read + fieldset: RESPCMD + - name: RESP1 + description: response 1..4 register + byte_offset: 20 + access: Read + fieldset: RESP1 + - name: RESP2 + description: response 1..4 register + byte_offset: 24 + access: Read + fieldset: RESP2 + - name: RESP3 + description: response 1..4 register + byte_offset: 28 + access: Read + fieldset: RESP3 + - name: RESP4 + description: response 1..4 register + byte_offset: 32 + access: Read + fieldset: RESP4 + - name: DTIMER + description: data timer register + byte_offset: 36 + fieldset: DTIMER + - name: DLEN + description: data length register + byte_offset: 40 + fieldset: DLEN + - name: DCTRL + description: data control register + byte_offset: 44 + fieldset: DCTRL + - name: DCOUNT + description: data counter register + byte_offset: 48 + access: Read + fieldset: DCOUNT + - name: STA + description: status register + byte_offset: 52 + access: Read + fieldset: STA + - name: ICR + description: interrupt clear register + byte_offset: 56 + fieldset: ICR + - name: MASK + description: mask register + byte_offset: 60 + fieldset: MASK + - name: FIFOCNT + description: FIFO counter register + byte_offset: 72 + access: Read + fieldset: FIFOCNT + - name: FIFO + description: data FIFO register + byte_offset: 128 + fieldset: FIFO fieldset/ARG: description: argument register fields: - - bit_offset: 0 - bit_size: 32 - description: Command argument - name: CMDARG + - name: CMDARG + description: Command argument + bit_offset: 0 + bit_size: 32 fieldset/CLKCR: description: SDI clock control register fields: - - bit_offset: 0 - bit_size: 8 - description: Clock divide factor - name: CLKDIV - - bit_offset: 8 - bit_size: 1 - description: Clock enable bit - name: CLKEN - - bit_offset: 9 - bit_size: 1 - description: Power saving configuration bit - name: PWRSAV - - bit_offset: 10 - bit_size: 1 - description: Clock divider bypass enable bit - name: BYPASS - - bit_offset: 11 - bit_size: 2 - description: Wide bus mode enable bit - name: WIDBUS - - bit_offset: 13 - bit_size: 1 - description: SDIO_CK dephasing selection bit - name: NEGEDGE - - bit_offset: 14 - bit_size: 1 - description: HW Flow Control enable - name: HWFC_EN + - name: CLKDIV + description: Clock divide factor + bit_offset: 0 + bit_size: 8 + - name: CLKEN + description: Clock enable bit + bit_offset: 8 + bit_size: 1 + - name: PWRSAV + description: Power saving configuration bit + bit_offset: 9 + bit_size: 1 + - name: BYPASS + description: Clock divider bypass enable bit + bit_offset: 10 + bit_size: 1 + - name: WIDBUS + description: Wide bus mode enable bit + bit_offset: 11 + bit_size: 2 + - name: NEGEDGE + description: SDIO_CK dephasing selection bit + bit_offset: 13 + bit_size: 1 + - name: HWFC_EN + description: HW Flow Control enable + bit_offset: 14 + bit_size: 1 fieldset/CMD: description: command register fields: - - bit_offset: 0 - bit_size: 6 - description: Command index - name: CMDINDEX - - bit_offset: 6 - bit_size: 2 - description: Wait for response bits - name: WAITRESP - - bit_offset: 8 - bit_size: 1 - description: CPSM waits for interrupt request - name: WAITINT - - bit_offset: 9 - bit_size: 1 - description: CPSM Waits for ends of data transfer (CmdPend internal signal) - name: WAITPEND - - bit_offset: 10 - bit_size: 1 - description: Command path state machine (CPSM) Enable bit - name: CPSMEN - - bit_offset: 11 - bit_size: 1 - description: SD I/O suspend command - name: SDIOSuspend + - name: CMDINDEX + description: Command index + bit_offset: 0 + bit_size: 6 + - name: WAITRESP + description: Wait for response bits + bit_offset: 6 + bit_size: 2 + - name: WAITINT + description: CPSM waits for interrupt request + bit_offset: 8 + bit_size: 1 + - name: WAITPEND + description: CPSM Waits for ends of data transfer (CmdPend internal signal) + bit_offset: 9 + bit_size: 1 + - name: CPSMEN + description: Command path state machine (CPSM) Enable bit + bit_offset: 10 + bit_size: 1 + - name: SDIOSuspend + description: SD I/O suspend command + bit_offset: 11 + bit_size: 1 fieldset/DCOUNT: description: data counter register fields: - - bit_offset: 0 - bit_size: 25 - description: Data count value - name: DATACOUNT + - name: DATACOUNT + description: Data count value + bit_offset: 0 + bit_size: 25 fieldset/DCTRL: description: data control register fields: - - bit_offset: 0 - bit_size: 1 - description: DTEN - name: DTEN - - bit_offset: 1 - bit_size: 1 - description: Data transfer direction selection - name: DTDIR - - bit_offset: 2 - bit_size: 1 - description: 'Data transfer mode selection 1: Stream or SDIO multibyte data transfer' - name: DTMODE - - bit_offset: 3 - bit_size: 1 - description: DMA enable bit - name: DMAEN - - bit_offset: 4 - bit_size: 4 - description: Data block size - name: DBLOCKSIZE - - bit_offset: 8 - bit_size: 1 - description: Read wait start - name: RWSTART - - bit_offset: 9 - bit_size: 1 - description: Read wait stop - name: RWSTOP - - bit_offset: 10 - bit_size: 1 - description: Read wait mode - name: RWMOD - - bit_offset: 11 - bit_size: 1 - description: SD I/O enable functions - name: SDIOEN + - name: DTEN + description: DTEN + bit_offset: 0 + bit_size: 1 + - name: DTDIR + description: Data transfer direction selection + bit_offset: 1 + bit_size: 1 + - name: DTMODE + description: "Data transfer mode selection 1: Stream or SDIO multibyte data transfer" + bit_offset: 2 + bit_size: 1 + - name: DMAEN + description: DMA enable bit + bit_offset: 3 + bit_size: 1 + - name: DBLOCKSIZE + description: Data block size + bit_offset: 4 + bit_size: 4 + - name: RWSTART + description: Read wait start + bit_offset: 8 + bit_size: 1 + - name: RWSTOP + description: Read wait stop + bit_offset: 9 + bit_size: 1 + - name: RWMOD + description: Read wait mode + bit_offset: 10 + bit_size: 1 + - name: SDIOEN + description: SD I/O enable functions + bit_offset: 11 + bit_size: 1 fieldset/DLEN: description: data length register fields: - - bit_offset: 0 - bit_size: 25 - description: Data length value - name: DATALENGTH + - name: DATALENGTH + description: Data length value + bit_offset: 0 + bit_size: 25 fieldset/DTIMER: description: data timer register fields: - - bit_offset: 0 - bit_size: 32 - description: Data timeout period - name: DATATIME + - name: DATATIME + description: Data timeout period + bit_offset: 0 + bit_size: 32 fieldset/FIFO: description: data FIFO register fields: - - bit_offset: 0 - bit_size: 32 - description: Receive and transmit FIFO data - name: FIFOData + - name: FIFOData + description: Receive and transmit FIFO data + bit_offset: 0 + bit_size: 32 fieldset/FIFOCNT: description: FIFO counter register fields: - - bit_offset: 0 - bit_size: 24 - description: Remaining number of words to be written to or read from the FIFO - name: FIFOCOUNT + - name: FIFOCOUNT + description: Remaining number of words to be written to or read from the FIFO + bit_offset: 0 + bit_size: 24 fieldset/ICR: description: interrupt clear register fields: - - bit_offset: 0 - bit_size: 1 - description: CCRCFAIL flag clear bit - name: CCRCFAILC - - bit_offset: 1 - bit_size: 1 - description: DCRCFAIL flag clear bit - name: DCRCFAILC - - bit_offset: 2 - bit_size: 1 - description: CTIMEOUT flag clear bit - name: CTIMEOUTC - - bit_offset: 3 - bit_size: 1 - description: DTIMEOUT flag clear bit - name: DTIMEOUTC - - bit_offset: 4 - bit_size: 1 - description: TXUNDERR flag clear bit - name: TXUNDERRC - - bit_offset: 5 - bit_size: 1 - description: RXOVERR flag clear bit - name: RXOVERRC - - bit_offset: 6 - bit_size: 1 - description: CMDREND flag clear bit - name: CMDRENDC - - bit_offset: 7 - bit_size: 1 - description: CMDSENT flag clear bit - name: CMDSENTC - - bit_offset: 8 - bit_size: 1 - description: DATAEND flag clear bit - name: DATAENDC - - bit_offset: 10 - bit_size: 1 - description: DBCKEND flag clear bit - name: DBCKENDC - - bit_offset: 22 - bit_size: 1 - description: SDIOIT flag clear bit - name: SDIOITC + - name: CCRCFAILC + description: CCRCFAIL flag clear bit + bit_offset: 0 + bit_size: 1 + - name: DCRCFAILC + description: DCRCFAIL flag clear bit + bit_offset: 1 + bit_size: 1 + - name: CTIMEOUTC + description: CTIMEOUT flag clear bit + bit_offset: 2 + bit_size: 1 + - name: DTIMEOUTC + description: DTIMEOUT flag clear bit + bit_offset: 3 + bit_size: 1 + - name: TXUNDERRC + description: TXUNDERR flag clear bit + bit_offset: 4 + bit_size: 1 + - name: RXOVERRC + description: RXOVERR flag clear bit + bit_offset: 5 + bit_size: 1 + - name: CMDRENDC + description: CMDREND flag clear bit + bit_offset: 6 + bit_size: 1 + - name: CMDSENTC + description: CMDSENT flag clear bit + bit_offset: 7 + bit_size: 1 + - name: DATAENDC + description: DATAEND flag clear bit + bit_offset: 8 + bit_size: 1 + - name: DBCKENDC + description: DBCKEND flag clear bit + bit_offset: 10 + bit_size: 1 + - name: SDIOITC + description: SDIOIT flag clear bit + bit_offset: 22 + bit_size: 1 fieldset/MASK: description: mask register fields: - - bit_offset: 0 - bit_size: 1 - description: Command CRC fail interrupt enable - name: CCRCFAILIE - - bit_offset: 1 - bit_size: 1 - description: Data CRC fail interrupt enable - name: DCRCFAILIE - - bit_offset: 2 - bit_size: 1 - description: Command timeout interrupt enable - name: CTIMEOUTIE - - bit_offset: 3 - bit_size: 1 - description: Data timeout interrupt enable - name: DTIMEOUTIE - - bit_offset: 4 - bit_size: 1 - description: Tx FIFO underrun error interrupt enable - name: TXUNDERRIE - - bit_offset: 5 - bit_size: 1 - description: Rx FIFO overrun error interrupt enable - name: RXOVERRIE - - bit_offset: 6 - bit_size: 1 - description: Command response received interrupt enable - name: CMDRENDIE - - bit_offset: 7 - bit_size: 1 - description: Command sent interrupt enable - name: CMDSENTIE - - bit_offset: 8 - bit_size: 1 - description: Data end interrupt enable - name: DATAENDIE - - bit_offset: 10 - bit_size: 1 - description: Data block end interrupt enable - name: DBCKENDIE - - bit_offset: 11 - bit_size: 1 - description: Command acting interrupt enable - name: CMDACTIE - - bit_offset: 12 - bit_size: 1 - description: Data transmit acting interrupt enable - name: TXACTIE - - bit_offset: 13 - bit_size: 1 - description: Data receive acting interrupt enable - name: RXACTIE - - bit_offset: 14 - bit_size: 1 - description: Tx FIFO half empty interrupt enable - name: TXFIFOHEIE - - bit_offset: 15 - bit_size: 1 - description: Rx FIFO half full interrupt enable - name: RXFIFOHFIE - - bit_offset: 16 - bit_size: 1 - description: Tx FIFO full interrupt enable - name: TXFIFOFIE - - bit_offset: 17 - bit_size: 1 - description: Rx FIFO full interrupt enable - name: RXFIFOFIE - - bit_offset: 18 - bit_size: 1 - description: Tx FIFO empty interrupt enable - name: TXFIFOEIE - - bit_offset: 19 - bit_size: 1 - description: Rx FIFO empty interrupt enable - name: RXFIFOEIE - - bit_offset: 20 - bit_size: 1 - description: Data available in Tx FIFO interrupt enable - name: TXDAVLIE - - bit_offset: 21 - bit_size: 1 - description: Data available in Rx FIFO interrupt enable - name: RXDAVLIE - - bit_offset: 22 - bit_size: 1 - description: SDIO mode interrupt received interrupt enable - name: SDIOITIE + - name: CCRCFAILIE + description: Command CRC fail interrupt enable + bit_offset: 0 + bit_size: 1 + - name: DCRCFAILIE + description: Data CRC fail interrupt enable + bit_offset: 1 + bit_size: 1 + - name: CTIMEOUTIE + description: Command timeout interrupt enable + bit_offset: 2 + bit_size: 1 + - name: DTIMEOUTIE + description: Data timeout interrupt enable + bit_offset: 3 + bit_size: 1 + - name: TXUNDERRIE + description: Tx FIFO underrun error interrupt enable + bit_offset: 4 + bit_size: 1 + - name: RXOVERRIE + description: Rx FIFO overrun error interrupt enable + bit_offset: 5 + bit_size: 1 + - name: CMDRENDIE + description: Command response received interrupt enable + bit_offset: 6 + bit_size: 1 + - name: CMDSENTIE + description: Command sent interrupt enable + bit_offset: 7 + bit_size: 1 + - name: DATAENDIE + description: Data end interrupt enable + bit_offset: 8 + bit_size: 1 + - name: DBCKENDIE + description: Data block end interrupt enable + bit_offset: 10 + bit_size: 1 + - name: CMDACTIE + description: Command acting interrupt enable + bit_offset: 11 + bit_size: 1 + - name: TXACTIE + description: Data transmit acting interrupt enable + bit_offset: 12 + bit_size: 1 + - name: RXACTIE + description: Data receive acting interrupt enable + bit_offset: 13 + bit_size: 1 + - name: TXFIFOHEIE + description: Tx FIFO half empty interrupt enable + bit_offset: 14 + bit_size: 1 + - name: RXFIFOHFIE + description: Rx FIFO half full interrupt enable + bit_offset: 15 + bit_size: 1 + - name: TXFIFOFIE + description: Tx FIFO full interrupt enable + bit_offset: 16 + bit_size: 1 + - name: RXFIFOFIE + description: Rx FIFO full interrupt enable + bit_offset: 17 + bit_size: 1 + - name: TXFIFOEIE + description: Tx FIFO empty interrupt enable + bit_offset: 18 + bit_size: 1 + - name: RXFIFOEIE + description: Rx FIFO empty interrupt enable + bit_offset: 19 + bit_size: 1 + - name: TXDAVLIE + description: Data available in Tx FIFO interrupt enable + bit_offset: 20 + bit_size: 1 + - name: RXDAVLIE + description: Data available in Rx FIFO interrupt enable + bit_offset: 21 + bit_size: 1 + - name: SDIOITIE + description: SDIO mode interrupt received interrupt enable + bit_offset: 22 + bit_size: 1 fieldset/POWER: description: power control register fields: - - bit_offset: 0 - bit_size: 2 - description: PWRCTRL - name: PWRCTRL + - name: PWRCTRL + description: PWRCTRL + bit_offset: 0 + bit_size: 2 fieldset/RESP1: description: response 1..4 register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 32 - description: see Table 132 - name: CARDSTATUS + - name: CARDSTATUS + description: see Table 132 + bit_offset: 0 + bit_size: 32 + array: + len: 1 + stride: 0 fieldset/RESP2: description: response 1..4 register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 32 - description: see Table 132 - name: CARDSTATUS + - name: CARDSTATUS + description: see Table 132 + bit_offset: 0 + bit_size: 32 + array: + len: 1 + stride: 0 fieldset/RESP3: description: response 1..4 register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 32 - description: see Table 132 - name: CARDSTATUS + - name: CARDSTATUS + description: see Table 132 + bit_offset: 0 + bit_size: 32 + array: + len: 1 + stride: 0 fieldset/RESP4: description: response 1..4 register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 32 - description: see Table 132 - name: CARDSTATUS + - name: CARDSTATUS + description: see Table 132 + bit_offset: 0 + bit_size: 32 + array: + len: 1 + stride: 0 fieldset/RESPCMD: description: command response register fields: - - bit_offset: 0 - bit_size: 6 - description: Response command index - name: RESPCMD + - name: RESPCMD + description: Response command index + bit_offset: 0 + bit_size: 6 fieldset/STA: description: status register fields: - - bit_offset: 0 - bit_size: 1 - description: Command response received (CRC check failed) - name: CCRCFAIL - - bit_offset: 1 - bit_size: 1 - description: Data block sent/received (CRC check failed) - name: DCRCFAIL - - bit_offset: 2 - bit_size: 1 - description: Command response timeout - name: CTIMEOUT - - bit_offset: 3 - bit_size: 1 - description: Data timeout - name: DTIMEOUT - - bit_offset: 4 - bit_size: 1 - description: Transmit FIFO underrun error - name: TXUNDERR - - bit_offset: 5 - bit_size: 1 - description: Received FIFO overrun error - name: RXOVERR - - bit_offset: 6 - bit_size: 1 - description: Command response received (CRC check passed) - name: CMDREND - - bit_offset: 7 - bit_size: 1 - description: Command sent (no response required) - name: CMDSENT - - bit_offset: 8 - bit_size: 1 - description: Data end (data counter, SDIDCOUNT, is zero) - name: DATAEND - - bit_offset: 10 - bit_size: 1 - description: Data block sent/received (CRC check passed) - name: DBCKEND - - bit_offset: 11 - bit_size: 1 - description: Command transfer in progress - name: CMDACT - - bit_offset: 12 - bit_size: 1 - description: Data transmit in progress - name: TXACT - - bit_offset: 13 - bit_size: 1 - description: Data receive in progress - name: RXACT - - bit_offset: 14 - bit_size: 1 - description: 'Transmit FIFO half empty: at least 8 words can be written into the - FIFO' - name: TXFIFOHE - - bit_offset: 15 - bit_size: 1 - description: 'Receive FIFO half full: there are at least 8 words in the FIFO' - name: RXFIFOHF - - bit_offset: 16 - bit_size: 1 - description: Transmit FIFO full - name: TXFIFOF - - bit_offset: 17 - bit_size: 1 - description: Receive FIFO full - name: RXFIFOF - - bit_offset: 18 - bit_size: 1 - description: Transmit FIFO empty - name: TXFIFOE - - bit_offset: 19 - bit_size: 1 - description: Receive FIFO empty - name: RXFIFOE - - bit_offset: 20 - bit_size: 1 - description: Data available in transmit FIFO - name: TXDAVL - - bit_offset: 21 - bit_size: 1 - description: Data available in receive FIFO - name: RXDAVL - - bit_offset: 22 - bit_size: 1 - description: SDIO interrupt received - name: SDIOIT + - name: CCRCFAIL + description: Command response received (CRC check failed) + bit_offset: 0 + bit_size: 1 + - name: DCRCFAIL + description: Data block sent/received (CRC check failed) + bit_offset: 1 + bit_size: 1 + - name: CTIMEOUT + description: Command response timeout + bit_offset: 2 + bit_size: 1 + - name: DTIMEOUT + description: Data timeout + bit_offset: 3 + bit_size: 1 + - name: TXUNDERR + description: Transmit FIFO underrun error + bit_offset: 4 + bit_size: 1 + - name: RXOVERR + description: Received FIFO overrun error + bit_offset: 5 + bit_size: 1 + - name: CMDREND + description: Command response received (CRC check passed) + bit_offset: 6 + bit_size: 1 + - name: CMDSENT + description: Command sent (no response required) + bit_offset: 7 + bit_size: 1 + - name: DATAEND + description: "Data end (data counter, SDIDCOUNT, is zero)" + bit_offset: 8 + bit_size: 1 + - name: DBCKEND + description: Data block sent/received (CRC check passed) + bit_offset: 10 + bit_size: 1 + - name: CMDACT + description: Command transfer in progress + bit_offset: 11 + bit_size: 1 + - name: TXACT + description: Data transmit in progress + bit_offset: 12 + bit_size: 1 + - name: RXACT + description: Data receive in progress + bit_offset: 13 + bit_size: 1 + - name: TXFIFOHE + description: "Transmit FIFO half empty: at least 8 words can be written into the FIFO" + bit_offset: 14 + bit_size: 1 + - name: RXFIFOHF + description: "Receive FIFO half full: there are at least 8 words in the FIFO" + bit_offset: 15 + bit_size: 1 + - name: TXFIFOF + description: Transmit FIFO full + bit_offset: 16 + bit_size: 1 + - name: RXFIFOF + description: Receive FIFO full + bit_offset: 17 + bit_size: 1 + - name: TXFIFOE + description: Transmit FIFO empty + bit_offset: 18 + bit_size: 1 + - name: RXFIFOE + description: Receive FIFO empty + bit_offset: 19 + bit_size: 1 + - name: TXDAVL + description: Data available in transmit FIFO + bit_offset: 20 + bit_size: 1 + - name: RXDAVL + description: Data available in receive FIFO + bit_offset: 21 + bit_size: 1 + - name: SDIOIT + description: SDIO interrupt received + bit_offset: 22 + bit_size: 1 diff --git a/data/registers/spdifrx_v1.yaml b/data/registers/spdifrx_v1.yaml index 5e9c30d..c1f7f6a 100644 --- a/data/registers/spdifrx_v1.yaml +++ b/data/registers/spdifrx_v1.yaml @@ -2,240 +2,240 @@ block/SPDIFRX: description: Receiver Interface items: - - byte_offset: 0 - description: Control register - fieldset: CR - name: CR - - byte_offset: 4 - description: Interrupt mask register - fieldset: IMR - name: IMR - - access: Read - byte_offset: 8 - description: Status register - fieldset: SR - name: SR - - access: Write - byte_offset: 12 - description: Interrupt Flag Clear register - fieldset: IFCR - name: IFCR - - access: Read - byte_offset: 16 - description: Data input register - fieldset: DR - name: DR - - access: Read - byte_offset: 20 - description: Channel Status register - fieldset: CSR - name: CSR - - access: Read - byte_offset: 24 - description: Debug Information register - fieldset: DIR - name: DIR + - name: CR + description: Control register + byte_offset: 0 + fieldset: CR + - name: IMR + description: Interrupt mask register + byte_offset: 4 + fieldset: IMR + - name: SR + description: Status register + byte_offset: 8 + access: Read + fieldset: SR + - name: IFCR + description: Interrupt Flag Clear register + byte_offset: 12 + access: Write + fieldset: IFCR + - name: DR + description: Data input register + byte_offset: 16 + access: Read + fieldset: DR + - name: CSR + description: Channel Status register + byte_offset: 20 + access: Read + fieldset: CSR + - name: DIR + description: Debug Information register + byte_offset: 24 + access: Read + fieldset: DIR fieldset/CR: description: Control register fields: - - bit_offset: 0 - bit_size: 2 - description: Peripheral Block Enable - name: SPDIFEN - - bit_offset: 2 - bit_size: 1 - description: Receiver DMA ENable for data flow - name: RXDMAEN - - bit_offset: 3 - bit_size: 1 - description: STerEO Mode - name: RXSTEO - - bit_offset: 4 - bit_size: 2 - description: RX Data format - name: DRFMT - - bit_offset: 6 - bit_size: 1 - description: Mask Parity error bit - name: PMSK - - bit_offset: 7 - bit_size: 1 - description: Mask of Validity bit - name: VMSK - - bit_offset: 8 - bit_size: 1 - description: Mask of channel status and user bits - name: CUMSK - - bit_offset: 9 - bit_size: 1 - description: Mask of Preamble Type bits - name: PTMSK - - bit_offset: 10 - bit_size: 1 - description: Control Buffer DMA ENable for control flow - name: CBDMAEN - - bit_offset: 11 - bit_size: 1 - description: Channel Selection - name: CHSEL - - bit_offset: 12 - bit_size: 2 - description: Maximum allowed re-tries during synchronization phase - name: NBTR - - bit_offset: 14 - bit_size: 1 - description: Wait For Activity - name: WFA - - bit_offset: 16 - bit_size: 3 - description: input selection - name: INSEL + - name: SPDIFEN + description: Peripheral Block Enable + bit_offset: 0 + bit_size: 2 + - name: RXDMAEN + description: Receiver DMA ENable for data flow + bit_offset: 2 + bit_size: 1 + - name: RXSTEO + description: STerEO Mode + bit_offset: 3 + bit_size: 1 + - name: DRFMT + description: RX Data format + bit_offset: 4 + bit_size: 2 + - name: PMSK + description: Mask Parity error bit + bit_offset: 6 + bit_size: 1 + - name: VMSK + description: Mask of Validity bit + bit_offset: 7 + bit_size: 1 + - name: CUMSK + description: Mask of channel status and user bits + bit_offset: 8 + bit_size: 1 + - name: PTMSK + description: Mask of Preamble Type bits + bit_offset: 9 + bit_size: 1 + - name: CBDMAEN + description: Control Buffer DMA ENable for control flow + bit_offset: 10 + bit_size: 1 + - name: CHSEL + description: Channel Selection + bit_offset: 11 + bit_size: 1 + - name: NBTR + description: Maximum allowed re-tries during synchronization phase + bit_offset: 12 + bit_size: 2 + - name: WFA + description: Wait For Activity + bit_offset: 14 + bit_size: 1 + - name: INSEL + description: input selection + bit_offset: 16 + bit_size: 3 fieldset/CSR: description: Channel Status register fields: - - bit_offset: 0 - bit_size: 16 - description: User data information - name: USR - - bit_offset: 16 - bit_size: 8 - description: Channel A status information - name: CS - - bit_offset: 24 - bit_size: 1 - description: Start Of Block - name: SOB + - name: USR + description: User data information + bit_offset: 0 + bit_size: 16 + - name: CS + description: Channel A status information + bit_offset: 16 + bit_size: 8 + - name: SOB + description: Start Of Block + bit_offset: 24 + bit_size: 1 fieldset/DIR: description: Debug Information register fields: - - bit_offset: 0 - bit_size: 13 - description: Threshold HIGH - name: THI - - bit_offset: 16 - bit_size: 13 - description: Threshold LOW - name: TLO + - name: THI + description: Threshold HIGH + bit_offset: 0 + bit_size: 13 + - name: TLO + description: Threshold LOW + bit_offset: 16 + bit_size: 13 fieldset/DR: description: Data input register fields: - - bit_offset: 0 - bit_size: 24 - description: Parity Error bit - name: DR - - bit_offset: 24 - bit_size: 1 - description: Parity Error bit - name: PE - - bit_offset: 25 - bit_size: 1 - description: Validity bit - name: V - - bit_offset: 26 - bit_size: 1 - description: User bit - name: U - - bit_offset: 27 - bit_size: 1 - description: Channel Status bit - name: C - - bit_offset: 28 - bit_size: 2 - description: Preamble Type - name: PT + - name: DR + description: Parity Error bit + bit_offset: 0 + bit_size: 24 + - name: PE + description: Parity Error bit + bit_offset: 24 + bit_size: 1 + - name: V + description: Validity bit + bit_offset: 25 + bit_size: 1 + - name: U + description: User bit + bit_offset: 26 + bit_size: 1 + - name: C + description: Channel Status bit + bit_offset: 27 + bit_size: 1 + - name: PT + description: Preamble Type + bit_offset: 28 + bit_size: 2 fieldset/IFCR: description: Interrupt Flag Clear register fields: - - bit_offset: 2 - bit_size: 1 - description: Clears the Parity error flag - name: PERRCF - - bit_offset: 3 - bit_size: 1 - description: Clears the Overrun error flag - name: OVRCF - - bit_offset: 4 - bit_size: 1 - description: Clears the Synchronization Block Detected flag - name: SBDCF - - bit_offset: 5 - bit_size: 1 - description: Clears the Synchronization Done flag - name: SYNCDCF + - name: PERRCF + description: Clears the Parity error flag + bit_offset: 2 + bit_size: 1 + - name: OVRCF + description: Clears the Overrun error flag + bit_offset: 3 + bit_size: 1 + - name: SBDCF + description: Clears the Synchronization Block Detected flag + bit_offset: 4 + bit_size: 1 + - name: SYNCDCF + description: Clears the Synchronization Done flag + bit_offset: 5 + bit_size: 1 fieldset/IMR: description: Interrupt mask register fields: - - bit_offset: 0 - bit_size: 1 - description: RXNE interrupt enable - name: RXNEIE - - bit_offset: 1 - bit_size: 1 - description: Control Buffer Ready Interrupt Enable - name: CSRNEIE - - bit_offset: 2 - bit_size: 1 - description: Parity error interrupt enable - name: PERRIE - - bit_offset: 3 - bit_size: 1 - description: Overrun error Interrupt Enable - name: OVRIE - - bit_offset: 4 - bit_size: 1 - description: Synchronization Block Detected Interrupt Enable - name: SBLKIE - - bit_offset: 5 - bit_size: 1 - description: Synchronization Done - name: SYNCDIE - - bit_offset: 6 - bit_size: 1 - description: Serial Interface Error Interrupt Enable - name: IFEIE + - name: RXNEIE + description: RXNE interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CSRNEIE + description: Control Buffer Ready Interrupt Enable + bit_offset: 1 + bit_size: 1 + - name: PERRIE + description: Parity error interrupt enable + bit_offset: 2 + bit_size: 1 + - name: OVRIE + description: Overrun error Interrupt Enable + bit_offset: 3 + bit_size: 1 + - name: SBLKIE + description: Synchronization Block Detected Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: SYNCDIE + description: Synchronization Done + bit_offset: 5 + bit_size: 1 + - name: IFEIE + description: Serial Interface Error Interrupt Enable + bit_offset: 6 + bit_size: 1 fieldset/SR: description: Status register fields: - - bit_offset: 0 - bit_size: 1 - description: Read data register not empty - name: RXNE - - bit_offset: 1 - bit_size: 1 - description: Control Buffer register is not empty - name: CSRNE - - bit_offset: 2 - bit_size: 1 - description: Parity error - name: PERR - - bit_offset: 3 - bit_size: 1 - description: Overrun error - name: OVR - - bit_offset: 4 - bit_size: 1 - description: Synchronization Block Detected - name: SBD - - bit_offset: 5 - bit_size: 1 - description: Synchronization Done - name: SYNCD - - bit_offset: 6 - bit_size: 1 - description: Framing error - name: FERR - - bit_offset: 7 - bit_size: 1 - description: Synchronization error - name: SERR - - bit_offset: 8 - bit_size: 1 - description: Time-out error - name: TERR - - array: - len: 1 - stride: 0 - bit_offset: 16 - bit_size: 15 - description: Duration of 5 symbols counted with SPDIF_CLK - name: WIDTH + - name: RXNE + description: Read data register not empty + bit_offset: 0 + bit_size: 1 + - name: CSRNE + description: Control Buffer register is not empty + bit_offset: 1 + bit_size: 1 + - name: PERR + description: Parity error + bit_offset: 2 + bit_size: 1 + - name: OVR + description: Overrun error + bit_offset: 3 + bit_size: 1 + - name: SBD + description: Synchronization Block Detected + bit_offset: 4 + bit_size: 1 + - name: SYNCD + description: Synchronization Done + bit_offset: 5 + bit_size: 1 + - name: FERR + description: Framing error + bit_offset: 6 + bit_size: 1 + - name: SERR + description: Synchronization error + bit_offset: 7 + bit_size: 1 + - name: TERR + description: Time-out error + bit_offset: 8 + bit_size: 1 + - name: WIDTH + description: Duration of 5 symbols counted with SPDIF_CLK + bit_offset: 16 + bit_size: 15 + array: + len: 1 + stride: 0 diff --git a/data/registers/spi_f1.yaml b/data/registers/spi_f1.yaml index 9cb6ee5..a6425d6 100644 --- a/data/registers/spi_f1.yaml +++ b/data/registers/spi_f1.yaml @@ -2,483 +2,483 @@ block/SPI: description: Serial peripheral interface items: - - byte_offset: 0 - description: control register 1 - fieldset: CR1 - name: CR1 - - byte_offset: 4 - description: control register 2 - fieldset: CR2 - name: CR2 - - byte_offset: 8 - description: status register - fieldset: SR - name: SR - - byte_offset: 12 - description: data register - fieldset: DR - name: DR - - byte_offset: 16 - description: CRC polynomial register - fieldset: CRCPR - name: CRCPR - - access: Read - byte_offset: 20 - description: RX CRC register - fieldset: RXCRCR - name: RXCRCR - - access: Read - byte_offset: 24 - description: TX CRC register - fieldset: TXCRCR - name: TXCRCR - - byte_offset: 28 - description: I2S configuration register - fieldset: I2SCFGR - name: I2SCFGR - - byte_offset: 32 - description: I2S prescaler register - fieldset: I2SPR - name: I2SPR -enum/BIDIMODE: - bit_size: 1 - variants: - - description: 2-line unidirectional data mode selected - name: Unidirectional - value: 0 - - description: 1-line bidirectional data mode selected - name: Bidirectional - value: 1 -enum/BIDIOE: - bit_size: 1 - variants: - - description: Output disabled (receive-only mode) - name: OutputDisabled - value: 0 - - description: Output enabled (transmit-only mode) - name: OutputEnabled - value: 1 -enum/BR: - bit_size: 3 - variants: - - description: f_PCLK / 2 - name: Div2 - value: 0 - - description: f_PCLK / 4 - name: Div4 - value: 1 - - description: f_PCLK / 8 - name: Div8 - value: 2 - - description: f_PCLK / 16 - name: Div16 - value: 3 - - description: f_PCLK / 32 - name: Div32 - value: 4 - - description: f_PCLK / 64 - name: Div64 - value: 5 - - description: f_PCLK / 128 - name: Div128 - value: 6 - - description: f_PCLK / 256 - name: Div256 - value: 7 -enum/CHLEN: - bit_size: 1 - variants: - - description: 16-bit wide - name: SixteenBit - value: 0 - - description: 32-bit wide - name: ThirtyTwoBit - value: 1 -enum/CHSIDE: - bit_size: 1 - variants: - - description: Channel left has to be transmitted or has been received - name: Left - value: 0 - - description: Channel right has to be transmitted or has been received - name: Right - value: 1 -enum/CKPOL: - bit_size: 1 - variants: - - description: I2S clock inactive state is low level - name: IdleLow - value: 0 - - description: I2S clock inactive state is high level - name: IdleHigh - value: 1 -enum/CPHA: - bit_size: 1 - variants: - - description: The first clock transition is the first data capture edge - name: FirstEdge - value: 0 - - description: The second clock transition is the first data capture edge - name: SecondEdge - value: 1 -enum/CPOL: - bit_size: 1 - variants: - - description: CK to 0 when idle - name: IdleLow - value: 0 - - description: CK to 1 when idle - name: IdleHigh - value: 1 -enum/CRCNEXT: - bit_size: 1 - variants: - - description: Next transmit value is from Tx buffer - name: TxBuffer - value: 0 - - description: Next transmit value is from Tx CRC register - name: CRC - value: 1 -enum/DATLEN: - bit_size: 2 - variants: - - description: 16-bit data length - name: SixteenBit - value: 0 - - description: 24-bit data length - name: TwentyFourBit - value: 1 - - description: 32-bit data length - name: ThirtyTwoBit - value: 2 -enum/DFF: - bit_size: 1 - variants: - - description: 8-bit data frame format is selected for transmission/reception - name: EightBit - value: 0 - - description: 16-bit data frame format is selected for transmission/reception - name: SixteenBit - value: 1 -enum/ERRIE: - bit_size: 1 - variants: - - description: Error interrupt masked - name: Masked - value: 0 - - description: Error interrupt not masked - name: NotMasked - value: 1 -enum/ISCFG: - bit_size: 2 - variants: - - description: Slave - transmit - name: SlaveTx - value: 0 - - description: Slave - receive - name: SlaveRx - value: 1 - - description: Master - transmit - name: MasterTx - value: 2 - - description: Master - receive - name: MasterRx - value: 3 -enum/ISMOD: - bit_size: 1 - variants: - - description: SPI mode is selected - name: SPIMode - value: 0 - - description: I2S mode is selected - name: I2SMode - value: 1 -enum/ISSTD: - bit_size: 2 - variants: - - description: I2S Philips standard - name: Philips - value: 0 - - description: MSB justified standard - name: MSB - value: 1 - - description: LSB justified standard - name: LSB - value: 2 - - description: PCM standard - name: PCM - value: 3 -enum/LSBFIRST: - bit_size: 1 - variants: - - description: Data is transmitted/received with the MSB first - name: MSBFirst - value: 0 - - description: Data is transmitted/received with the LSB first - name: LSBFirst - value: 1 -enum/MSTR: - bit_size: 1 - variants: - - description: Slave configuration - name: Slave - value: 0 - - description: Master configuration - name: Master - value: 1 -enum/ODD: - bit_size: 1 - variants: - - description: Real divider value is I2SDIV * 2 - name: Even - value: 0 - - description: Real divider value is (I2SDIV * 2) + 1 - name: Odd - value: 1 -enum/OVRR: - bit_size: 1 - variants: - - description: No overrun occurred - name: NoOverrun - value: 0 - - description: Overrun occurred - name: Overrun - value: 1 -enum/PCMSYNC: - bit_size: 1 - variants: - - description: Short frame synchronisation - name: Short - value: 0 - - description: Long frame synchronisation - name: Long - value: 1 -enum/RXONLY: - bit_size: 1 - variants: - - description: Full duplex (Transmit and receive) - name: FullDuplex - value: 0 - - description: Output disabled (Receive-only mode) - name: OutputDisabled - value: 1 + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: SR + description: status register + byte_offset: 8 + fieldset: SR + - name: DR + description: data register + byte_offset: 12 + fieldset: DR + - name: CRCPR + description: CRC polynomial register + byte_offset: 16 + fieldset: CRCPR + - name: RXCRCR + description: RX CRC register + byte_offset: 20 + access: Read + fieldset: RXCRCR + - name: TXCRCR + description: TX CRC register + byte_offset: 24 + access: Read + fieldset: TXCRCR + - name: I2SCFGR + description: I2S configuration register + byte_offset: 28 + fieldset: I2SCFGR + - name: I2SPR + description: I2S prescaler register + byte_offset: 32 + fieldset: I2SPR fieldset/CR1: description: control register 1 fields: - - bit_offset: 0 - bit_size: 1 - description: Clock phase - enum: CPHA - name: CPHA - - bit_offset: 1 - bit_size: 1 - description: Clock polarity - enum: CPOL - name: CPOL - - bit_offset: 2 - bit_size: 1 - description: Master selection - enum: MSTR - name: MSTR - - bit_offset: 3 - bit_size: 3 - description: Baud rate control - enum: BR - name: BR - - bit_offset: 6 - bit_size: 1 - description: SPI enable - name: SPE - - bit_offset: 7 - bit_size: 1 - description: Frame format - enum: LSBFIRST - name: LSBFIRST - - bit_offset: 8 - bit_size: 1 - description: Internal slave select - name: SSI - - bit_offset: 9 - bit_size: 1 - description: Software slave management - name: SSM - - bit_offset: 10 - bit_size: 1 - description: Receive only - enum: RXONLY - name: RXONLY - - bit_offset: 11 - bit_size: 1 - description: Data frame format - enum: DFF - name: DFF - - bit_offset: 12 - bit_size: 1 - description: CRC transfer next - enum: CRCNEXT - name: CRCNEXT - - bit_offset: 13 - bit_size: 1 - description: Hardware CRC calculation enable - name: CRCEN - - bit_offset: 14 - bit_size: 1 - description: Output enable in bidirectional mode - enum: BIDIOE - name: BIDIOE - - bit_offset: 15 - bit_size: 1 - description: Bidirectional data mode enable - enum: BIDIMODE - name: BIDIMODE + - name: CPHA + description: Clock phase + bit_offset: 0 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 1 + bit_size: 1 + enum: CPOL + - name: MSTR + description: Master selection + bit_offset: 2 + bit_size: 1 + enum: MSTR + - name: BR + description: Baud rate control + bit_offset: 3 + bit_size: 3 + enum: BR + - name: SPE + description: SPI enable + bit_offset: 6 + bit_size: 1 + - name: LSBFIRST + description: Frame format + bit_offset: 7 + bit_size: 1 + enum: LSBFIRST + - name: SSI + description: Internal slave select + bit_offset: 8 + bit_size: 1 + - name: SSM + description: Software slave management + bit_offset: 9 + bit_size: 1 + - name: RXONLY + description: Receive only + bit_offset: 10 + bit_size: 1 + enum: RXONLY + - name: DFF + description: Data frame format + bit_offset: 11 + bit_size: 1 + enum: DFF + - name: CRCNEXT + description: CRC transfer next + bit_offset: 12 + bit_size: 1 + enum: CRCNEXT + - name: CRCEN + description: Hardware CRC calculation enable + bit_offset: 13 + bit_size: 1 + - name: BIDIOE + description: Output enable in bidirectional mode + bit_offset: 14 + bit_size: 1 + enum: BIDIOE + - name: BIDIMODE + description: Bidirectional data mode enable + bit_offset: 15 + bit_size: 1 + enum: BIDIMODE fieldset/CR2: description: control register 2 fields: - - bit_offset: 0 - bit_size: 1 - description: Rx buffer DMA enable - name: RXDMAEN - - bit_offset: 1 - bit_size: 1 - description: Tx buffer DMA enable - name: TXDMAEN - - bit_offset: 2 - bit_size: 1 - description: SS output enable - name: SSOE - - bit_offset: 5 - bit_size: 1 - description: Error interrupt enable - enum: ERRIE - name: ERRIE - - bit_offset: 6 - bit_size: 1 - description: RX buffer not empty interrupt enable - name: RXNEIE - - bit_offset: 7 - bit_size: 1 - description: Tx buffer empty interrupt enable - name: TXEIE + - name: RXDMAEN + description: Rx buffer DMA enable + bit_offset: 0 + bit_size: 1 + - name: TXDMAEN + description: Tx buffer DMA enable + bit_offset: 1 + bit_size: 1 + - name: SSOE + description: SS output enable + bit_offset: 2 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 5 + bit_size: 1 + enum: ERRIE + - name: RXNEIE + description: RX buffer not empty interrupt enable + bit_offset: 6 + bit_size: 1 + - name: TXEIE + description: Tx buffer empty interrupt enable + bit_offset: 7 + bit_size: 1 fieldset/CRCPR: description: CRC polynomial register fields: - - bit_offset: 0 - bit_size: 16 - description: CRC polynomial register - name: CRCPOLY + - name: CRCPOLY + description: CRC polynomial register + bit_offset: 0 + bit_size: 16 fieldset/DR: description: data register fields: - - bit_offset: 0 - bit_size: 16 - description: Data register - name: DR + - name: DR + description: Data register + bit_offset: 0 + bit_size: 16 fieldset/I2SCFGR: description: I2S configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: Channel length (number of bits per audio channel) - enum: CHLEN - name: CHLEN - - bit_offset: 1 - bit_size: 2 - description: Data length to be transferred - enum: DATLEN - name: DATLEN - - bit_offset: 3 - bit_size: 1 - description: Steady state clock polarity - enum: CKPOL - name: CKPOL - - bit_offset: 4 - bit_size: 2 - description: I2S standard selection - enum: ISSTD - name: I2SSTD - - bit_offset: 7 - bit_size: 1 - description: PCM frame synchronization - enum: PCMSYNC - name: PCMSYNC - - bit_offset: 8 - bit_size: 2 - description: I2S configuration mode - enum: ISCFG - name: I2SCFG - - bit_offset: 10 - bit_size: 1 - description: I2S Enable - name: I2SE - - bit_offset: 11 - bit_size: 1 - description: I2S mode selection - enum: ISMOD - name: I2SMOD + - name: CHLEN + description: Channel length (number of bits per audio channel) + bit_offset: 0 + bit_size: 1 + enum: CHLEN + - name: DATLEN + description: Data length to be transferred + bit_offset: 1 + bit_size: 2 + enum: DATLEN + - name: CKPOL + description: Steady state clock polarity + bit_offset: 3 + bit_size: 1 + enum: CKPOL + - name: I2SSTD + description: I2S standard selection + bit_offset: 4 + bit_size: 2 + enum: ISSTD + - name: PCMSYNC + description: PCM frame synchronization + bit_offset: 7 + bit_size: 1 + enum: PCMSYNC + - name: I2SCFG + description: I2S configuration mode + bit_offset: 8 + bit_size: 2 + enum: ISCFG + - name: I2SE + description: I2S Enable + bit_offset: 10 + bit_size: 1 + - name: I2SMOD + description: I2S mode selection + bit_offset: 11 + bit_size: 1 + enum: ISMOD fieldset/I2SPR: description: I2S prescaler register fields: - - bit_offset: 0 - bit_size: 8 - description: I2S Linear prescaler - name: I2SDIV - - bit_offset: 8 - bit_size: 1 - description: Odd factor for the prescaler - enum: ODD - name: ODD - - bit_offset: 9 - bit_size: 1 - description: Master clock output enable - name: MCKOE + - name: I2SDIV + description: I2S Linear prescaler + bit_offset: 0 + bit_size: 8 + - name: ODD + description: Odd factor for the prescaler + bit_offset: 8 + bit_size: 1 + enum: ODD + - name: MCKOE + description: Master clock output enable + bit_offset: 9 + bit_size: 1 fieldset/RXCRCR: description: RX CRC register fields: - - bit_offset: 0 - bit_size: 16 - description: Rx CRC register - name: RxCRC + - name: RxCRC + description: Rx CRC register + bit_offset: 0 + bit_size: 16 fieldset/SR: description: status register fields: - - bit_offset: 0 - bit_size: 1 - description: Receive buffer not empty - name: RXNE - - bit_offset: 1 - bit_size: 1 - description: Transmit buffer empty - name: TXE - - bit_offset: 2 - bit_size: 1 - description: Channel side - enum: CHSIDE - name: CHSIDE - - bit_offset: 3 - bit_size: 1 - description: Underrun flag - name: UDR - - bit_offset: 4 - bit_size: 1 - description: CRC error flag - name: CRCERR - - bit_offset: 5 - bit_size: 1 - description: Mode fault - name: MODF - - bit_offset: 6 - bit_size: 1 - description: Overrun flag - enum_read: OVRR - name: OVR - - bit_offset: 7 - bit_size: 1 - description: Busy flag - name: BSY + - name: RXNE + description: Receive buffer not empty + bit_offset: 0 + bit_size: 1 + - name: TXE + description: Transmit buffer empty + bit_offset: 1 + bit_size: 1 + - name: CHSIDE + description: Channel side + bit_offset: 2 + bit_size: 1 + enum: CHSIDE + - name: UDR + description: Underrun flag + bit_offset: 3 + bit_size: 1 + - name: CRCERR + description: CRC error flag + bit_offset: 4 + bit_size: 1 + - name: MODF + description: Mode fault + bit_offset: 5 + bit_size: 1 + - name: OVR + description: Overrun flag + bit_offset: 6 + bit_size: 1 + enum_read: OVRR + - name: BSY + description: Busy flag + bit_offset: 7 + bit_size: 1 fieldset/TXCRCR: description: TX CRC register fields: - - bit_offset: 0 - bit_size: 16 - description: Tx CRC register - name: TxCRC + - name: TxCRC + description: Tx CRC register + bit_offset: 0 + bit_size: 16 +enum/BIDIMODE: + bit_size: 1 + variants: + - name: Unidirectional + description: 2-line unidirectional data mode selected + value: 0 + - name: Bidirectional + description: 1-line bidirectional data mode selected + value: 1 +enum/BIDIOE: + bit_size: 1 + variants: + - name: OutputDisabled + description: Output disabled (receive-only mode) + value: 0 + - name: OutputEnabled + description: Output enabled (transmit-only mode) + value: 1 +enum/BR: + bit_size: 3 + variants: + - name: Div2 + description: f_PCLK / 2 + value: 0 + - name: Div4 + description: f_PCLK / 4 + value: 1 + - name: Div8 + description: f_PCLK / 8 + value: 2 + - name: Div16 + description: f_PCLK / 16 + value: 3 + - name: Div32 + description: f_PCLK / 32 + value: 4 + - name: Div64 + description: f_PCLK / 64 + value: 5 + - name: Div128 + description: f_PCLK / 128 + value: 6 + - name: Div256 + description: f_PCLK / 256 + value: 7 +enum/CHLEN: + bit_size: 1 + variants: + - name: SixteenBit + description: 16-bit wide + value: 0 + - name: ThirtyTwoBit + description: 32-bit wide + value: 1 +enum/CHSIDE: + bit_size: 1 + variants: + - name: Left + description: Channel left has to be transmitted or has been received + value: 0 + - name: Right + description: Channel right has to be transmitted or has been received + value: 1 +enum/CKPOL: + bit_size: 1 + variants: + - name: IdleLow + description: I2S clock inactive state is low level + value: 0 + - name: IdleHigh + description: I2S clock inactive state is high level + value: 1 +enum/CPHA: + bit_size: 1 + variants: + - name: FirstEdge + description: The first clock transition is the first data capture edge + value: 0 + - name: SecondEdge + description: The second clock transition is the first data capture edge + value: 1 +enum/CPOL: + bit_size: 1 + variants: + - name: IdleLow + description: CK to 0 when idle + value: 0 + - name: IdleHigh + description: CK to 1 when idle + value: 1 +enum/CRCNEXT: + bit_size: 1 + variants: + - name: TxBuffer + description: Next transmit value is from Tx buffer + value: 0 + - name: CRC + description: Next transmit value is from Tx CRC register + value: 1 +enum/DATLEN: + bit_size: 2 + variants: + - name: SixteenBit + description: 16-bit data length + value: 0 + - name: TwentyFourBit + description: 24-bit data length + value: 1 + - name: ThirtyTwoBit + description: 32-bit data length + value: 2 +enum/DFF: + bit_size: 1 + variants: + - name: EightBit + description: 8-bit data frame format is selected for transmission/reception + value: 0 + - name: SixteenBit + description: 16-bit data frame format is selected for transmission/reception + value: 1 +enum/ERRIE: + bit_size: 1 + variants: + - name: Masked + description: Error interrupt masked + value: 0 + - name: NotMasked + description: Error interrupt not masked + value: 1 +enum/ISCFG: + bit_size: 2 + variants: + - name: SlaveTx + description: Slave - transmit + value: 0 + - name: SlaveRx + description: Slave - receive + value: 1 + - name: MasterTx + description: Master - transmit + value: 2 + - name: MasterRx + description: Master - receive + value: 3 +enum/ISMOD: + bit_size: 1 + variants: + - name: SPIMode + description: SPI mode is selected + value: 0 + - name: I2SMode + description: I2S mode is selected + value: 1 +enum/ISSTD: + bit_size: 2 + variants: + - name: Philips + description: I2S Philips standard + value: 0 + - name: MSB + description: MSB justified standard + value: 1 + - name: LSB + description: LSB justified standard + value: 2 + - name: PCM + description: PCM standard + value: 3 +enum/LSBFIRST: + bit_size: 1 + variants: + - name: MSBFirst + description: Data is transmitted/received with the MSB first + value: 0 + - name: LSBFirst + description: Data is transmitted/received with the LSB first + value: 1 +enum/MSTR: + bit_size: 1 + variants: + - name: Slave + description: Slave configuration + value: 0 + - name: Master + description: Master configuration + value: 1 +enum/ODD: + bit_size: 1 + variants: + - name: Even + description: Real divider value is I2SDIV * 2 + value: 0 + - name: Odd + description: Real divider value is (I2SDIV * 2) + 1 + value: 1 +enum/OVRR: + bit_size: 1 + variants: + - name: NoOverrun + description: No overrun occurred + value: 0 + - name: Overrun + description: Overrun occurred + value: 1 +enum/PCMSYNC: + bit_size: 1 + variants: + - name: Short + description: Short frame synchronisation + value: 0 + - name: Long + description: Long frame synchronisation + value: 1 +enum/RXONLY: + bit_size: 1 + variants: + - name: FullDuplex + description: Full duplex (Transmit and receive) + value: 0 + - name: OutputDisabled + description: Output disabled (Receive-only mode) + value: 1 diff --git a/data/registers/spi_v2.yaml b/data/registers/spi_v2.yaml index 29beb35..55cb420 100644 --- a/data/registers/spi_v2.yaml +++ b/data/registers/spi_v2.yaml @@ -2,669 +2,667 @@ block/SPI: description: Serial peripheral interface items: - - byte_offset: 0 - description: control register 1 - fieldset: CR1 - name: CR1 - - byte_offset: 4 - description: control register 2 - fieldset: CR2 - name: CR2 - - byte_offset: 8 - description: status register - fieldset: SR - name: SR - - byte_offset: 12 - description: data register - fieldset: DR - name: DR - - byte_offset: 16 - description: CRC polynomial register - fieldset: CRCPR - name: CRCPR - - access: Read - byte_offset: 20 - description: RX CRC register - fieldset: RXCRCR - name: RXCRCR - - access: Read - byte_offset: 24 - description: TX CRC register - fieldset: TXCRCR - name: TXCRCR - - byte_offset: 28 - description: I2S configuration register - fieldset: I2SCFGR - name: I2SCFGR - - byte_offset: 32 - description: I2S prescaler register - fieldset: I2SPR - name: I2SPR + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: SR + description: status register + byte_offset: 8 + fieldset: SR + - name: DR + description: data register + byte_offset: 12 + fieldset: DR + - name: CRCPR + description: CRC polynomial register + byte_offset: 16 + fieldset: CRCPR + - name: RXCRCR + description: RX CRC register + byte_offset: 20 + access: Read + fieldset: RXCRCR + - name: TXCRCR + description: TX CRC register + byte_offset: 24 + access: Read + fieldset: TXCRCR + - name: I2SCFGR + description: I2S configuration register + byte_offset: 28 + fieldset: I2SCFGR + - name: I2SPR + description: I2S prescaler register + byte_offset: 32 + fieldset: I2SPR fieldset/CR1: description: control register 1 fields: - - bit_offset: 0 - bit_size: 1 - description: Clock phase - enum: CPHA - name: CPHA - - bit_offset: 1 - bit_size: 1 - description: Clock polarity - enum: CPOL - name: CPOL - - bit_offset: 2 - bit_size: 1 - description: Master selection - enum: MSTR - name: MSTR - - bit_offset: 3 - bit_size: 3 - description: Baud rate control - enum: BR - name: BR - - bit_offset: 6 - bit_size: 1 - description: SPI enable - name: SPE - - bit_offset: 7 - bit_size: 1 - description: Frame format - enum: LSBFIRST - name: LSBFIRST - - bit_offset: 8 - bit_size: 1 - description: Internal slave select - name: SSI - - bit_offset: 9 - bit_size: 1 - description: Software slave management - name: SSM - - bit_offset: 10 - bit_size: 1 - description: Receive only - enum: RXONLY - name: RXONLY - - bit_offset: 11 - bit_size: 1 - description: CRC length - enum: CRCL - name: CRCL - - bit_offset: 12 - bit_size: 1 - description: CRC transfer next - enum: CRCNEXT - name: CRCNEXT - - bit_offset: 13 - bit_size: 1 - description: Hardware CRC calculation enable - name: CRCEN - - bit_offset: 14 - bit_size: 1 - description: Output enable in bidirectional mode - enum: BIDIOE - name: BIDIOE - - bit_offset: 15 - bit_size: 1 - description: Bidirectional data mode enable - enum: BIDIMODE - name: BIDIMODE + - name: CPHA + description: Clock phase + bit_offset: 0 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 1 + bit_size: 1 + enum: CPOL + - name: MSTR + description: Master selection + bit_offset: 2 + bit_size: 1 + enum: MSTR + - name: BR + description: Baud rate control + bit_offset: 3 + bit_size: 3 + enum: BR + - name: SPE + description: SPI enable + bit_offset: 6 + bit_size: 1 + - name: LSBFIRST + description: Frame format + bit_offset: 7 + bit_size: 1 + enum: LSBFIRST + - name: SSI + description: Internal slave select + bit_offset: 8 + bit_size: 1 + - name: SSM + description: Software slave management + bit_offset: 9 + bit_size: 1 + - name: RXONLY + description: Receive only + bit_offset: 10 + bit_size: 1 + enum: RXONLY + - name: CRCL + description: CRC length + bit_offset: 11 + bit_size: 1 + enum: CRCL + - name: CRCNEXT + description: CRC transfer next + bit_offset: 12 + bit_size: 1 + enum: CRCNEXT + - name: CRCEN + description: Hardware CRC calculation enable + bit_offset: 13 + bit_size: 1 + - name: BIDIOE + description: Output enable in bidirectional mode + bit_offset: 14 + bit_size: 1 + enum: BIDIOE + - name: BIDIMODE + description: Bidirectional data mode enable + bit_offset: 15 + bit_size: 1 + enum: BIDIMODE fieldset/CR2: description: control register 2 fields: - - bit_offset: 0 - bit_size: 1 - description: Rx buffer DMA enable - name: RXDMAEN - - bit_offset: 1 - bit_size: 1 - description: Tx buffer DMA enable - name: TXDMAEN - - bit_offset: 2 - bit_size: 1 - description: SS output enable - name: SSOE - - bit_offset: 3 - bit_size: 1 - description: NSS pulse management - name: NSSP - - bit_offset: 4 - bit_size: 1 - description: Frame format - enum: FRF - name: FRF - - bit_offset: 5 - bit_size: 1 - description: Error interrupt enable - name: ERRIE - - bit_offset: 6 - bit_size: 1 - description: RX buffer not empty interrupt enable - name: RXNEIE - - bit_offset: 7 - bit_size: 1 - description: Tx buffer empty interrupt enable - name: TXEIE - - bit_offset: 8 - bit_size: 4 - description: Data size - enum: DS - name: DS - - bit_offset: 12 - bit_size: 1 - description: FIFO reception threshold - enum: FRXTH - name: FRXTH - - bit_offset: 13 - bit_size: 1 - description: Last DMA transfer for reception - enum: LDMA_RX - name: LDMA_RX - - bit_offset: 14 - bit_size: 1 - description: Last DMA transfer for transmission - enum: LDMA_TX - name: LDMA_TX + - name: RXDMAEN + description: Rx buffer DMA enable + bit_offset: 0 + bit_size: 1 + - name: TXDMAEN + description: Tx buffer DMA enable + bit_offset: 1 + bit_size: 1 + - name: SSOE + description: SS output enable + bit_offset: 2 + bit_size: 1 + - name: NSSP + description: NSS pulse management + bit_offset: 3 + bit_size: 1 + - name: FRF + description: Frame format + bit_offset: 4 + bit_size: 1 + enum: FRF + - name: ERRIE + description: Error interrupt enable + bit_offset: 5 + bit_size: 1 + - name: RXNEIE + description: RX buffer not empty interrupt enable + bit_offset: 6 + bit_size: 1 + - name: TXEIE + description: Tx buffer empty interrupt enable + bit_offset: 7 + bit_size: 1 + - name: DS + description: Data size + bit_offset: 8 + bit_size: 4 + enum: DS + - name: FRXTH + description: FIFO reception threshold + bit_offset: 12 + bit_size: 1 + enum: FRXTH + - name: LDMA_RX + description: Last DMA transfer for reception + bit_offset: 13 + bit_size: 1 + enum: LDMA_RX + - name: LDMA_TX + description: Last DMA transfer for transmission + bit_offset: 14 + bit_size: 1 + enum: LDMA_TX fieldset/CRCPR: description: CRC polynomial register fields: - - bit_offset: 0 - bit_size: 16 - description: CRC polynomial register - name: CRCPOLY + - name: CRCPOLY + description: CRC polynomial register + bit_offset: 0 + bit_size: 16 fieldset/DR: description: data register fields: - - bit_offset: 0 - bit_size: 16 - description: Data register - name: DR -fieldset/RXCRCR: - description: RX CRC register - fields: - - bit_offset: 0 + - name: DR + description: Data register + bit_offset: 0 bit_size: 16 - description: Rx CRC register - name: RxCRC -fieldset/SR: - description: status register - fields: - - bit_offset: 0 - bit_size: 1 - description: Receive buffer not empty - name: RXNE - - bit_offset: 1 - bit_size: 1 - description: Transmit buffer empty - name: TXE - - bit_offset: 2 - bit_size: 1 - description: Channel side - enum: CHSIDE - name: CHSIDE - - bit_offset: 3 - bit_size: 1 - description: Underrun flag - enum_read: UDRR - name: UDR - - bit_offset: 4 - bit_size: 1 - description: CRC error flag - name: CRCERR - - bit_offset: 5 - bit_size: 1 - description: Mode fault - name: MODF - - bit_offset: 6 - bit_size: 1 - description: Overrun flag - name: OVR - - bit_offset: 7 - bit_size: 1 - description: Busy flag - name: BSY - - bit_offset: 8 - bit_size: 1 - description: frame format error - enum_read: FRER - name: FRE - - bit_offset: 9 - bit_size: 2 - description: FIFO reception level - enum_read: FRLVLR - name: FRLVL - - bit_offset: 11 - bit_size: 2 - description: FIFO Transmission Level - enum_read: FTLVLR - name: FTLVL -fieldset/TXCRCR: - description: TX CRC register - fields: - - bit_offset: 0 - bit_size: 16 - description: Tx CRC register - name: TxCRC fieldset/I2SCFGR: description: I2S configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: Channel length (number of bits per audio channel) - enum: CHLEN - name: CHLEN - - bit_offset: 1 - bit_size: 2 - description: Data length to be transferred - enum: DATLEN - name: DATLEN - - bit_offset: 3 - bit_size: 1 - description: Steady state clock polarity - enum: CKPOL - name: CKPOL - - bit_offset: 4 - bit_size: 2 - description: I2S standard selection - enum: ISSTD - name: I2SSTD - - bit_offset: 7 - bit_size: 1 - description: PCM frame synchronization - enum: PCMSYNC - name: PCMSYNC - - bit_offset: 8 - bit_size: 2 - description: I2S configuration mode - enum: ISCFG - name: I2SCFG - - bit_offset: 10 - bit_size: 1 - description: I2S Enable - enum: ISE - name: I2SE - - bit_offset: 11 - bit_size: 1 - description: I2S mode selection - enum: ISMOD - name: I2SMOD - - bit_offset: 12 - bit_size: 1 - description: Asynchronous start enable - name: ASTRTEN + - name: CHLEN + description: Channel length (number of bits per audio channel) + bit_offset: 0 + bit_size: 1 + enum: CHLEN + - name: DATLEN + description: Data length to be transferred + bit_offset: 1 + bit_size: 2 + enum: DATLEN + - name: CKPOL + description: Steady state clock polarity + bit_offset: 3 + bit_size: 1 + enum: CKPOL + - name: I2SSTD + description: I2S standard selection + bit_offset: 4 + bit_size: 2 + enum: ISSTD + - name: PCMSYNC + description: PCM frame synchronization + bit_offset: 7 + bit_size: 1 + enum: PCMSYNC + - name: I2SCFG + description: I2S configuration mode + bit_offset: 8 + bit_size: 2 + enum: ISCFG + - name: I2SE + description: I2S Enable + bit_offset: 10 + bit_size: 1 + enum: ISE + - name: I2SMOD + description: I2S mode selection + bit_offset: 11 + bit_size: 1 + enum: ISMOD + - name: ASTRTEN + description: Asynchronous start enable + bit_offset: 12 + bit_size: 1 fieldset/I2SPR: description: I2S prescaler register fields: - - bit_offset: 0 - bit_size: 8 - description: I2S Linear prescaler - name: I2SDIV - - bit_offset: 8 - bit_size: 1 - description: Odd factor for the prescaler - enum: ODD - name: ODD - - bit_offset: 9 - bit_size: 1 - description: Master clock output enable - enum: MCKOE - name: MCKOE + - name: I2SDIV + description: I2S Linear prescaler + bit_offset: 0 + bit_size: 8 + - name: ODD + description: Odd factor for the prescaler + bit_offset: 8 + bit_size: 1 + enum: ODD + - name: MCKOE + description: Master clock output enable + bit_offset: 9 + bit_size: 1 + enum: MCKOE +fieldset/RXCRCR: + description: RX CRC register + fields: + - name: RxCRC + description: Rx CRC register + bit_offset: 0 + bit_size: 16 +fieldset/SR: + description: status register + fields: + - name: RXNE + description: Receive buffer not empty + bit_offset: 0 + bit_size: 1 + - name: TXE + description: Transmit buffer empty + bit_offset: 1 + bit_size: 1 + - name: CHSIDE + description: Channel side + bit_offset: 2 + bit_size: 1 + enum: CHSIDE + - name: UDR + description: Underrun flag + bit_offset: 3 + bit_size: 1 + enum_read: UDRR + - name: CRCERR + description: CRC error flag + bit_offset: 4 + bit_size: 1 + - name: MODF + description: Mode fault + bit_offset: 5 + bit_size: 1 + - name: OVR + description: Overrun flag + bit_offset: 6 + bit_size: 1 + - name: BSY + description: Busy flag + bit_offset: 7 + bit_size: 1 + - name: FRE + description: frame format error + bit_offset: 8 + bit_size: 1 + enum_read: FRER + - name: FRLVL + description: FIFO reception level + bit_offset: 9 + bit_size: 2 + enum_read: FRLVLR + - name: FTLVL + description: FIFO Transmission Level + bit_offset: 11 + bit_size: 2 + enum_read: FTLVLR +fieldset/TXCRCR: + description: TX CRC register + fields: + - name: TxCRC + description: Tx CRC register + bit_offset: 0 + bit_size: 16 enum/BIDIMODE: bit_size: 1 variants: - - description: 2-line unidirectional data mode selected - name: Unidirectional + - name: Unidirectional + description: 2-line unidirectional data mode selected value: 0 - - description: 1-line bidirectional data mode selected - name: Bidirectional + - name: Bidirectional + description: 1-line bidirectional data mode selected value: 1 enum/BIDIOE: bit_size: 1 variants: - - description: Output disabled (receive-only mode) - name: OutputDisabled + - name: OutputDisabled + description: Output disabled (receive-only mode) value: 0 - - description: Output enabled (transmit-only mode) - name: OutputEnabled + - name: OutputEnabled + description: Output enabled (transmit-only mode) value: 1 enum/BR: bit_size: 3 variants: - - description: f_PCLK / 2 - name: Div2 + - name: Div2 + description: f_PCLK / 2 value: 0 - - description: f_PCLK / 4 - name: Div4 + - name: Div4 + description: f_PCLK / 4 value: 1 - - description: f_PCLK / 8 - name: Div8 + - name: Div8 + description: f_PCLK / 8 value: 2 - - description: f_PCLK / 16 - name: Div16 + - name: Div16 + description: f_PCLK / 16 value: 3 - - description: f_PCLK / 32 - name: Div32 + - name: Div32 + description: f_PCLK / 32 value: 4 - - description: f_PCLK / 64 - name: Div64 + - name: Div64 + description: f_PCLK / 64 value: 5 - - description: f_PCLK / 128 - name: Div128 + - name: Div128 + description: f_PCLK / 128 value: 6 - - description: f_PCLK / 256 - name: Div256 + - name: Div256 + description: f_PCLK / 256 value: 7 enum/CHLEN: bit_size: 1 variants: - - description: 16-bit wide - name: SixteenBit + - name: SixteenBit + description: 16-bit wide value: 0 - - description: 32-bit wide - name: ThirtyTwoBit + - name: ThirtyTwoBit + description: 32-bit wide value: 1 enum/CHSIDE: bit_size: 1 variants: - - description: Channel left has to be transmitted or has been received - name: Left + - name: Left + description: Channel left has to be transmitted or has been received value: 0 - - description: Channel right has to be transmitted or has been received - name: Right + - name: Right + description: Channel right has to be transmitted or has been received value: 1 enum/CKPOL: bit_size: 1 variants: - - description: I2S clock inactive state is low level - name: IdleLow + - name: IdleLow + description: I2S clock inactive state is low level value: 0 - - description: I2S clock inactive state is high level - name: IdleHigh + - name: IdleHigh + description: I2S clock inactive state is high level value: 1 enum/CPHA: bit_size: 1 variants: - - description: The first clock transition is the first data capture edge - name: FirstEdge + - name: FirstEdge + description: The first clock transition is the first data capture edge value: 0 - - description: The second clock transition is the first data capture edge - name: SecondEdge + - name: SecondEdge + description: The second clock transition is the first data capture edge value: 1 enum/CPOL: bit_size: 1 variants: - - description: CK to 0 when idle - name: IdleLow + - name: IdleLow + description: CK to 0 when idle value: 0 - - description: CK to 1 when idle - name: IdleHigh + - name: IdleHigh + description: CK to 1 when idle value: 1 enum/CRCL: bit_size: 1 variants: - - description: 8-bit CRC length - name: EightBit + - name: EightBit + description: 8-bit CRC length value: 0 - - description: 16-bit CRC length - name: SixteenBit + - name: SixteenBit + description: 16-bit CRC length value: 1 enum/CRCNEXT: bit_size: 1 variants: - - description: Next transmit value is from Tx buffer - name: TxBuffer + - name: TxBuffer + description: Next transmit value is from Tx buffer value: 0 - - description: Next transmit value is from Tx CRC register - name: CRC + - name: CRC + description: Next transmit value is from Tx CRC register value: 1 enum/DATLEN: bit_size: 2 variants: - - description: 16-bit data length - name: SixteenBit + - name: SixteenBit + description: 16-bit data length value: 0 - - description: 24-bit data length - name: TwentyFourBit + - name: TwentyFourBit + description: 24-bit data length value: 1 - - description: 32-bit data length - name: ThirtyTwoBit + - name: ThirtyTwoBit + description: 32-bit data length value: 2 enum/DS: bit_size: 4 variants: - - description: 4-bit - name: FourBit + - name: FourBit + description: 4-bit value: 3 - - description: 5-bit - name: FiveBit + - name: FiveBit + description: 5-bit value: 4 - - description: 6-bit - name: SixBit + - name: SixBit + description: 6-bit value: 5 - - description: 7-bit - name: SevenBit + - name: SevenBit + description: 7-bit value: 6 - - description: 8-bit - name: EightBit + - name: EightBit + description: 8-bit value: 7 - - description: 9-bit - name: NineBit + - name: NineBit + description: 9-bit value: 8 - - description: 10-bit - name: TenBit + - name: TenBit + description: 10-bit value: 9 - - description: 11-bit - name: ElevenBit + - name: ElevenBit + description: 11-bit value: 10 - - description: 12-bit - name: TwelveBit + - name: TwelveBit + description: 12-bit value: 11 - - description: 13-bit - name: ThirteenBit + - name: ThirteenBit + description: 13-bit value: 12 - - description: 14-bit - name: FourteenBit + - name: FourteenBit + description: 14-bit value: 13 - - description: 15-bit - name: FifteenBit + - name: FifteenBit + description: 15-bit value: 14 - - description: 16-bit - name: SixteenBit + - name: SixteenBit + description: 16-bit value: 15 enum/FRER: bit_size: 1 variants: - - description: No frame format error - name: NoError + - name: NoError + description: No frame format error value: 0 - - description: A frame format error occurred - name: Error + - name: Error + description: A frame format error occurred value: 1 enum/FRF: bit_size: 1 variants: - - description: SPI Motorola mode - name: Motorola + - name: Motorola + description: SPI Motorola mode value: 0 - - description: SPI TI mode - name: TI + - name: TI + description: SPI TI mode value: 1 enum/FRLVLR: bit_size: 2 variants: - - description: Rx FIFO Empty - name: Empty + - name: Empty + description: Rx FIFO Empty value: 0 - - description: Rx 1/4 FIFO - name: Quarter + - name: Quarter + description: Rx 1/4 FIFO value: 1 - - description: Rx 1/2 FIFO - name: Half + - name: Half + description: Rx 1/2 FIFO value: 2 - - description: Rx FIFO full - name: Full + - name: Full + description: Rx FIFO full value: 3 enum/FRXTH: bit_size: 1 variants: - - description: RXNE event is generated if the FIFO level is greater than or equal - to 1/2 (16-bit) - name: Half + - name: Half + description: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) value: 0 - - description: RXNE event is generated if the FIFO level is greater than or equal - to 1/4 (8-bit) - name: Quarter + - name: Quarter + description: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) value: 1 enum/FTLVLR: bit_size: 2 variants: - - description: Tx FIFO Empty - name: Empty + - name: Empty + description: Tx FIFO Empty value: 0 - - description: Tx 1/4 FIFO - name: Quarter + - name: Quarter + description: Tx 1/4 FIFO value: 1 - - description: Tx 1/2 FIFO - name: Half + - name: Half + description: Tx 1/2 FIFO value: 2 - - description: Tx FIFO full - name: Full + - name: Full + description: Tx FIFO full value: 3 enum/ISCFG: bit_size: 2 variants: - - description: Slave - transmit - name: SlaveTx + - name: SlaveTx + description: Slave - transmit value: 0 - - description: Slave - receive - name: SlaveRx + - name: SlaveRx + description: Slave - receive value: 1 - - description: Master - transmit - name: MasterTx + - name: MasterTx + description: Master - transmit value: 2 - - description: Master - receive - name: MasterRx + - name: MasterRx + description: Master - receive value: 3 enum/ISE: bit_size: 1 variants: - - description: I2S peripheral is disabled - name: Disabled + - name: Disabled + description: I2S peripheral is disabled value: 0 - - description: I2S peripheral is enabled - name: Enabled + - name: Enabled + description: I2S peripheral is enabled value: 1 enum/ISMOD: bit_size: 1 variants: - - description: SPI mode is selected - name: SPIMode + - name: SPIMode + description: SPI mode is selected value: 0 - - description: I2S mode is selected - name: I2SMode + - name: I2SMode + description: I2S mode is selected value: 1 enum/ISSTD: bit_size: 2 variants: - - description: I2S Philips standard - name: Philips + - name: Philips + description: I2S Philips standard value: 0 - - description: MSB justified standard - name: MSB + - name: MSB + description: MSB justified standard value: 1 - - description: LSB justified standard - name: LSB + - name: LSB + description: LSB justified standard value: 2 - - description: PCM standard - name: PCM + - name: PCM + description: PCM standard value: 3 enum/LDMA_RX: bit_size: 1 variants: - - description: Number of data to transfer for receive is even - name: Even + - name: Even + description: Number of data to transfer for receive is even value: 0 - - description: Number of data to transfer for receive is odd - name: Odd + - name: Odd + description: Number of data to transfer for receive is odd value: 1 enum/LDMA_TX: bit_size: 1 variants: - - description: Number of data to transfer for transmit is even - name: Even + - name: Even + description: Number of data to transfer for transmit is even value: 0 - - description: Number of data to transfer for transmit is odd - name: Odd + - name: Odd + description: Number of data to transfer for transmit is odd value: 1 enum/LSBFIRST: bit_size: 1 variants: - - description: Data is transmitted/received with the MSB first - name: MSBFirst + - name: MSBFirst + description: Data is transmitted/received with the MSB first value: 0 - - description: Data is transmitted/received with the LSB first - name: LSBFirst + - name: LSBFirst + description: Data is transmitted/received with the LSB first value: 1 enum/MCKOE: bit_size: 1 variants: - - description: Master clock output is disabled - name: Disabled + - name: Disabled + description: Master clock output is disabled value: 0 - - description: Master clock output is enabled - name: Enabled + - name: Enabled + description: Master clock output is enabled value: 1 enum/MSTR: bit_size: 1 variants: - - description: Slave configuration - name: Slave + - name: Slave + description: Slave configuration value: 0 - - description: Master configuration - name: Master + - name: Master + description: Master configuration value: 1 enum/ODD: bit_size: 1 variants: - - description: Real divider value is I2SDIV * 2 - name: Even + - name: Even + description: Real divider value is I2SDIV * 2 value: 0 - - description: Real divider value is (I2SDIV * 2) + 1 - name: Odd + - name: Odd + description: Real divider value is (I2SDIV * 2) + 1 value: 1 enum/OVRR: bit_size: 1 variants: - - description: No overrun occurred - name: NoOverrun + - name: NoOverrun + description: No overrun occurred value: 0 - - description: Overrun occurred - name: Overrun + - name: Overrun + description: Overrun occurred value: 1 enum/PCMSYNC: bit_size: 1 variants: - - description: Short frame synchronisation - name: Short + - name: Short + description: Short frame synchronisation value: 0 - - description: Long frame synchronisation - name: Long + - name: Long + description: Long frame synchronisation value: 1 enum/RXONLY: bit_size: 1 variants: - - description: Full duplex (Transmit and receive) - name: FullDuplex + - name: FullDuplex + description: Full duplex (Transmit and receive) value: 0 - - description: Output disabled (Receive-only mode) - name: OutputDisabled + - name: OutputDisabled + description: Output disabled (Receive-only mode) value: 1 enum/UDRR: bit_size: 1 variants: - - description: No underrun occurred - name: NoUnderrun + - name: NoUnderrun + description: No underrun occurred value: 0 - - description: Underrun occurred - name: Underrun + - name: Underrun + description: Underrun occurred value: 1 diff --git a/data/registers/syscfg_f4.yaml b/data/registers/syscfg_f4.yaml index c5b0640..41f1661 100644 --- a/data/registers/syscfg_f4.yaml +++ b/data/registers/syscfg_f4.yaml @@ -5,12 +5,10 @@ block/SYSCFG: - name: MEMRM description: memory remap register byte_offset: 0 - reset_value: 0 fieldset: MEMRM - name: PMC description: peripheral mode configuration register byte_offset: 4 - reset_value: 0 fieldset: PMC - name: EXTICR description: external interrupt configuration register @@ -18,12 +16,10 @@ block/SYSCFG: len: 4 stride: 4 byte_offset: 8 - reset_value: 0 fieldset: EXTICR - name: CMPCR description: Compensation cell control register byte_offset: 32 - reset_value: 0 access: Read fieldset: CMPCR fieldset/CMPCR: @@ -80,4 +76,4 @@ fieldset/PMC: - name: MII_RMII_SEL description: Ethernet PHY interface selection bit_offset: 23 - bit_size: 1 \ No newline at end of file + bit_size: 1 diff --git a/data/registers/syscfg_f7.yaml b/data/registers/syscfg_f7.yaml index 50d0f6f..f5a2242 100644 --- a/data/registers/syscfg_f7.yaml +++ b/data/registers/syscfg_f7.yaml @@ -2,110 +2,110 @@ block/SYSCFG: description: System configuration controller items: - - byte_offset: 0 - description: memory remap register - fieldset: MEMRMP - name: MEMRMP - - byte_offset: 4 - description: peripheral mode configuration register - fieldset: PMC - name: PMC - - array: - len: 4 - stride: 4 - byte_offset: 8 - description: external interrupt configuration register 1 - fieldset: EXTICR - name: EXTICR - - access: Read - byte_offset: 32 - description: Compensation cell control register - fieldset: CMPCR - name: CMPCR + - name: MEMRMP + description: memory remap register + byte_offset: 0 + fieldset: MEMRMP + - name: PMC + description: peripheral mode configuration register + byte_offset: 4 + fieldset: PMC + - name: EXTICR + description: external interrupt configuration register 1 + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CMPCR + description: Compensation cell control register + byte_offset: 32 + access: Read + fieldset: CMPCR fieldset/CMPCR: description: Compensation cell control register fields: - - bit_offset: 0 - bit_size: 1 - description: Compensation cell power-down - name: CMP_PD - - bit_offset: 8 - bit_size: 1 - description: READY - name: READY + - name: CMP_PD + description: Compensation cell power-down + bit_offset: 0 + bit_size: 1 + - name: READY + description: READY + bit_offset: 8 + bit_size: 1 fieldset/EXTICR: description: external interrupt configuration register 1 fields: - - array: - len: 4 - stride: 4 - bit_offset: 0 - bit_size: 4 - description: EXTI x configuration (x = 0 to 3) - name: EXTI + - name: EXTI + description: EXTI x configuration (x = 0 to 3) + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 fieldset/MEMRMP: description: memory remap register fields: - - bit_offset: 0 - bit_size: 1 - description: Memory boot mapping - name: MEM_BOOT - - bit_offset: 8 - bit_size: 1 - description: Flash bank mode selection - name: FB_MODE - - bit_offset: 10 - bit_size: 2 - description: FMC memory mapping swap - name: SWP_FMC + - name: MEM_BOOT + description: Memory boot mapping + bit_offset: 0 + bit_size: 1 + - name: FB_MODE + description: Flash bank mode selection + bit_offset: 8 + bit_size: 1 + - name: SWP_FMC + description: FMC memory mapping swap + bit_offset: 10 + bit_size: 2 fieldset/PMC: description: peripheral mode configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: I2C1_FMP I2C1 Fast Mode + Enable - name: I2C1_FMP - - bit_offset: 1 - bit_size: 1 - description: I2C2_FMP I2C2 Fast Mode + Enable - name: I2C2_FMP - - bit_offset: 2 - bit_size: 1 - description: I2C3_FMP I2C3 Fast Mode + Enable - name: I2C3_FMP - - bit_offset: 3 - bit_size: 1 - description: I2C4 Fast Mode + Enable - name: I2C4_FMP - - bit_offset: 4 - bit_size: 1 - description: PB6_FMP Fast Mode - name: PB6_FMP - - bit_offset: 5 - bit_size: 1 - description: PB7_FMP Fast Mode + Enable - name: PB7_FMP - - bit_offset: 6 - bit_size: 1 - description: PB8_FMP Fast Mode + Enable - name: PB8_FMP - - bit_offset: 7 - bit_size: 1 - description: Fast Mode + Enable - name: PB9_FMP - - bit_offset: 16 - bit_size: 1 - description: ADC3DC2 - name: ADC1DC2 - - bit_offset: 17 - bit_size: 1 - description: ADC2DC2 - name: ADC2DC2 - - bit_offset: 18 - bit_size: 1 - description: ADC3DC2 - name: ADC3DC2 - - bit_offset: 23 - bit_size: 1 - description: Ethernet PHY interface selection - name: MII_RMII_SEL + - name: I2C1_FMP + description: I2C1_FMP I2C1 Fast Mode + Enable + bit_offset: 0 + bit_size: 1 + - name: I2C2_FMP + description: I2C2_FMP I2C2 Fast Mode + Enable + bit_offset: 1 + bit_size: 1 + - name: I2C3_FMP + description: I2C3_FMP I2C3 Fast Mode + Enable + bit_offset: 2 + bit_size: 1 + - name: I2C4_FMP + description: I2C4 Fast Mode + Enable + bit_offset: 3 + bit_size: 1 + - name: PB6_FMP + description: PB6_FMP Fast Mode + bit_offset: 4 + bit_size: 1 + - name: PB7_FMP + description: PB7_FMP Fast Mode + Enable + bit_offset: 5 + bit_size: 1 + - name: PB8_FMP + description: PB8_FMP Fast Mode + Enable + bit_offset: 6 + bit_size: 1 + - name: PB9_FMP + description: Fast Mode + Enable + bit_offset: 7 + bit_size: 1 + - name: ADC1DC2 + description: ADC3DC2 + bit_offset: 16 + bit_size: 1 + - name: ADC2DC2 + description: ADC2DC2 + bit_offset: 17 + bit_size: 1 + - name: ADC3DC2 + description: ADC3DC2 + bit_offset: 18 + bit_size: 1 + - name: MII_RMII_SEL + description: Ethernet PHY interface selection + bit_offset: 23 + bit_size: 1 diff --git a/data/registers/syscfg_g0.yaml b/data/registers/syscfg_g0.yaml index e933ef6..f67ddea 100644 --- a/data/registers/syscfg_g0.yaml +++ b/data/registers/syscfg_g0.yaml @@ -1,660 +1,655 @@ +--- block/SYSCFG: description: System configuration controller items: - - byte_offset: 0 - description: SYSCFG configuration register 1 - fieldset: CFGR1 - name: CFGR1 - - byte_offset: 24 - description: SYSCFG configuration register 1 - fieldset: CFGR2 - name: CFGR2 - - byte_offset: 48 - description: VREFBUF control and status register - fieldset: VREFBUF_CSR - name: VREFBUF_CSR - - byte_offset: 52 - description: VREFBUF calibration control register - fieldset: VREFBUF_CCR - name: VREFBUF_CCR - - access: Read - byte_offset: 128 - description: interrupt line 0 status register - fieldset: ITLINE0 - name: ITLINE0 - - access: Read - byte_offset: 132 - description: interrupt line 1 status register - fieldset: ITLINE1 - name: ITLINE1 - - access: Read - byte_offset: 136 - description: interrupt line 2 status register - fieldset: ITLINE2 - name: ITLINE2 - - access: Read - byte_offset: 140 - description: interrupt line 3 status register - fieldset: ITLINE3 - name: ITLINE3 - - access: Read - byte_offset: 144 - description: interrupt line 4 status register - fieldset: ITLINE4 - name: ITLINE4 - - access: Read - byte_offset: 148 - description: interrupt line 5 status register - fieldset: ITLINE5 - name: ITLINE5 - - access: Read - byte_offset: 152 - description: interrupt line 6 status register - fieldset: ITLINE6 - name: ITLINE6 - - access: Read - byte_offset: 156 - description: interrupt line 7 status register - fieldset: ITLINE7 - name: ITLINE7 - - access: Read - byte_offset: 160 - description: interrupt line 8 status register - fieldset: ITLINE8 - name: ITLINE8 - - access: Read - byte_offset: 164 - description: interrupt line 9 status register - fieldset: ITLINE9 - name: ITLINE9 - - access: Read - byte_offset: 168 - description: interrupt line 10 status register - fieldset: ITLINE10 - name: ITLINE10 - - access: Read - byte_offset: 172 - description: interrupt line 11 status register - fieldset: ITLINE11 - name: ITLINE11 - - access: Read - byte_offset: 176 - description: interrupt line 12 status register - fieldset: ITLINE12 - name: ITLINE12 - - access: Read - byte_offset: 180 - description: interrupt line 13 status register - fieldset: ITLINE13 - name: ITLINE13 - - access: Read - byte_offset: 184 - description: interrupt line 14 status register - fieldset: ITLINE14 - name: ITLINE14 - - access: Read - byte_offset: 188 - description: interrupt line 15 status register - fieldset: ITLINE15 - name: ITLINE15 - - access: Read - byte_offset: 192 - description: interrupt line 16 status register - fieldset: ITLINE16 - name: ITLINE16 - - access: Read - byte_offset: 196 - description: interrupt line 17 status register - fieldset: ITLINE17 - name: ITLINE17 - - access: Read - byte_offset: 200 - description: interrupt line 18 status register - fieldset: ITLINE18 - name: ITLINE18 - - access: Read - byte_offset: 204 - description: interrupt line 19 status register - fieldset: ITLINE19 - name: ITLINE19 - - access: Read - byte_offset: 208 - description: interrupt line 20 status register - fieldset: ITLINE20 - name: ITLINE20 - - access: Read - byte_offset: 212 - description: interrupt line 21 status register - fieldset: ITLINE21 - name: ITLINE21 - - access: Read - byte_offset: 216 - description: interrupt line 22 status register - fieldset: ITLINE22 - name: ITLINE22 - - access: Read - byte_offset: 220 - description: interrupt line 23 status register - fieldset: ITLINE23 - name: ITLINE23 - - access: Read - byte_offset: 224 - description: interrupt line 24 status register - fieldset: ITLINE24 - name: ITLINE24 - - access: Read - byte_offset: 228 - description: interrupt line 25 status register - fieldset: ITLINE25 - name: ITLINE25 - - access: Read - byte_offset: 232 - description: interrupt line 26 status register - fieldset: ITLINE26 - name: ITLINE26 - - access: Read - byte_offset: 236 - description: interrupt line 27 status register - fieldset: ITLINE27 - name: ITLINE27 - - access: Read - byte_offset: 240 - description: interrupt line 28 status register - fieldset: ITLINE28 - name: ITLINE28 - - access: Read - byte_offset: 244 - description: interrupt line 29 status register - fieldset: ITLINE29 - name: ITLINE29 - - access: Read - byte_offset: 248 - description: interrupt line 30 status register - fieldset: ITLINE30 - name: ITLINE30 - - access: Read - byte_offset: 252 - description: interrupt line 31 status register - fieldset: ITLINE31 - name: ITLINE31 + - name: CFGR1 + description: SYSCFG configuration register 1 + byte_offset: 0 + fieldset: CFGR1 + - name: CFGR2 + description: SYSCFG configuration register 1 + byte_offset: 24 + fieldset: CFGR2 + - name: VREFBUF_CSR + description: VREFBUF control and status register + byte_offset: 48 + fieldset: VREFBUF_CSR + - name: VREFBUF_CCR + description: VREFBUF calibration control register + byte_offset: 52 + fieldset: VREFBUF_CCR + - name: ITLINE0 + description: interrupt line 0 status register + byte_offset: 128 + access: Read + fieldset: ITLINE0 + - name: ITLINE1 + description: interrupt line 1 status register + byte_offset: 132 + access: Read + fieldset: ITLINE1 + - name: ITLINE2 + description: interrupt line 2 status register + byte_offset: 136 + access: Read + fieldset: ITLINE2 + - name: ITLINE3 + description: interrupt line 3 status register + byte_offset: 140 + access: Read + fieldset: ITLINE3 + - name: ITLINE4 + description: interrupt line 4 status register + byte_offset: 144 + access: Read + fieldset: ITLINE4 + - name: ITLINE5 + description: interrupt line 5 status register + byte_offset: 148 + access: Read + fieldset: ITLINE5 + - name: ITLINE6 + description: interrupt line 6 status register + byte_offset: 152 + access: Read + fieldset: ITLINE6 + - name: ITLINE7 + description: interrupt line 7 status register + byte_offset: 156 + access: Read + fieldset: ITLINE7 + - name: ITLINE8 + description: interrupt line 8 status register + byte_offset: 160 + access: Read + fieldset: ITLINE8 + - name: ITLINE9 + description: interrupt line 9 status register + byte_offset: 164 + access: Read + fieldset: ITLINE9 + - name: ITLINE10 + description: interrupt line 10 status register + byte_offset: 168 + access: Read + fieldset: ITLINE10 + - name: ITLINE11 + description: interrupt line 11 status register + byte_offset: 172 + access: Read + fieldset: ITLINE11 + - name: ITLINE12 + description: interrupt line 12 status register + byte_offset: 176 + access: Read + fieldset: ITLINE12 + - name: ITLINE13 + description: interrupt line 13 status register + byte_offset: 180 + access: Read + fieldset: ITLINE13 + - name: ITLINE14 + description: interrupt line 14 status register + byte_offset: 184 + access: Read + fieldset: ITLINE14 + - name: ITLINE15 + description: interrupt line 15 status register + byte_offset: 188 + access: Read + fieldset: ITLINE15 + - name: ITLINE16 + description: interrupt line 16 status register + byte_offset: 192 + access: Read + fieldset: ITLINE16 + - name: ITLINE17 + description: interrupt line 17 status register + byte_offset: 196 + access: Read + fieldset: ITLINE17 + - name: ITLINE18 + description: interrupt line 18 status register + byte_offset: 200 + access: Read + fieldset: ITLINE18 + - name: ITLINE19 + description: interrupt line 19 status register + byte_offset: 204 + access: Read + fieldset: ITLINE19 + - name: ITLINE20 + description: interrupt line 20 status register + byte_offset: 208 + access: Read + fieldset: ITLINE20 + - name: ITLINE21 + description: interrupt line 21 status register + byte_offset: 212 + access: Read + fieldset: ITLINE21 + - name: ITLINE22 + description: interrupt line 22 status register + byte_offset: 216 + access: Read + fieldset: ITLINE22 + - name: ITLINE23 + description: interrupt line 23 status register + byte_offset: 220 + access: Read + fieldset: ITLINE23 + - name: ITLINE24 + description: interrupt line 24 status register + byte_offset: 224 + access: Read + fieldset: ITLINE24 + - name: ITLINE25 + description: interrupt line 25 status register + byte_offset: 228 + access: Read + fieldset: ITLINE25 + - name: ITLINE26 + description: interrupt line 26 status register + byte_offset: 232 + access: Read + fieldset: ITLINE26 + - name: ITLINE27 + description: interrupt line 27 status register + byte_offset: 236 + access: Read + fieldset: ITLINE27 + - name: ITLINE28 + description: interrupt line 28 status register + byte_offset: 240 + access: Read + fieldset: ITLINE28 + - name: ITLINE29 + description: interrupt line 29 status register + byte_offset: 244 + access: Read + fieldset: ITLINE29 + - name: ITLINE30 + description: interrupt line 30 status register + byte_offset: 248 + access: Read + fieldset: ITLINE30 + - name: ITLINE31 + description: interrupt line 31 status register + byte_offset: 252 + access: Read + fieldset: ITLINE31 fieldset/CFGR1: description: SYSCFG configuration register 1 fields: - - bit_offset: 0 - bit_size: 2 - description: Memory mapping selection bits - name: MEM_MODE - - bit_offset: 4 - bit_size: 1 - description: PA11 and PA12 remapping bit. - name: PA11_PA12_RMP - - bit_offset: 5 - bit_size: 1 - description: IR output polarity selection - name: IR_POL - - bit_offset: 6 - bit_size: 2 - description: IR Modulation Envelope signal selection. - name: IR_MOD - - bit_offset: 8 - bit_size: 1 - description: I/O analog switch voltage booster enable - name: BOOSTEN - - bit_offset: 9 - bit_size: 1 - description: Strobe signal bit for UCPD1 - name: UCPD1_STROBE - - bit_offset: 10 - bit_size: 1 - description: Strobe signal bit for UCPD2 - name: UCPD2_STROBE - - bit_offset: 16 - bit_size: 4 - description: Fast Mode Plus (FM+) driving capability activation bits - name: I2C_PBx_FMP - - bit_offset: 20 - bit_size: 1 - description: FM+ driving capability activation for I2C1 - name: I2C1_FMP - - bit_offset: 21 - bit_size: 1 - description: FM+ driving capability activation for I2C2 - name: I2C2_FMP - - bit_offset: 22 - bit_size: 2 - description: Fast Mode Plus (FM+) driving capability activation bits - name: I2C_PAx_FMP + - name: MEM_MODE + description: Memory mapping selection bits + bit_offset: 0 + bit_size: 2 + - name: PA11_PA12_RMP + description: PA11 and PA12 remapping bit. + bit_offset: 4 + bit_size: 1 + - name: IR_POL + description: IR output polarity selection + bit_offset: 5 + bit_size: 1 + - name: IR_MOD + description: IR Modulation Envelope signal selection. + bit_offset: 6 + bit_size: 2 + - name: BOOSTEN + description: I/O analog switch voltage booster enable + bit_offset: 8 + bit_size: 1 + - name: UCPD1_STROBE + description: Strobe signal bit for UCPD1 + bit_offset: 9 + bit_size: 1 + - name: UCPD2_STROBE + description: Strobe signal bit for UCPD2 + bit_offset: 10 + bit_size: 1 + - name: I2C_PBx_FMP + description: Fast Mode Plus (FM+) driving capability activation bits + bit_offset: 16 + bit_size: 4 + - name: I2C1_FMP + description: FM+ driving capability activation for I2C1 + bit_offset: 20 + bit_size: 1 + - name: I2C2_FMP + description: FM+ driving capability activation for I2C2 + bit_offset: 21 + bit_size: 1 + - name: I2C_PAx_FMP + description: Fast Mode Plus (FM+) driving capability activation bits + bit_offset: 22 + bit_size: 2 fieldset/CFGR2: description: SYSCFG configuration register 1 fields: - - bit_offset: 0 - bit_size: 1 - description: Cortex-M0+ LOCKUP bit enable bit - name: LOCKUP_LOCK - - bit_offset: 1 - bit_size: 1 - description: SRAM parity lock bit - name: SRAM_PARITY_LOCK - - bit_offset: 2 - bit_size: 1 - description: PVD lock enable bit - name: PVD_LOCK - - bit_offset: 3 - bit_size: 1 - description: ECC error lock bit - name: ECC_LOCK - - bit_offset: 8 - bit_size: 1 - description: SRAM parity error flag - name: SRAM_PEF - - bit_offset: 16 - bit_size: 1 - description: PA1_CDEN - name: PA1_CDEN - - bit_offset: 17 - bit_size: 1 - description: PA3_CDEN - name: PA3_CDEN - - bit_offset: 18 - bit_size: 1 - description: PA5_CDEN - name: PA5_CDEN - - bit_offset: 19 - bit_size: 1 - description: PA6_CDEN - name: PA6_CDEN - - bit_offset: 20 - bit_size: 1 - description: PA13_CDEN - name: PA13_CDEN - - bit_offset: 21 - bit_size: 1 - description: PB0_CDEN - name: PB0_CDEN - - bit_offset: 22 - bit_size: 1 - description: PB1_CDEN - name: PB1_CDEN - - bit_offset: 23 - bit_size: 1 - description: PB2_CDEN - name: PB2_CDEN + - name: LOCKUP_LOCK + description: Cortex-M0+ LOCKUP bit enable bit + bit_offset: 0 + bit_size: 1 + - name: SRAM_PARITY_LOCK + description: SRAM parity lock bit + bit_offset: 1 + bit_size: 1 + - name: PVD_LOCK + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + - name: ECC_LOCK + description: ECC error lock bit + bit_offset: 3 + bit_size: 1 + - name: SRAM_PEF + description: SRAM parity error flag + bit_offset: 8 + bit_size: 1 + - name: PA1_CDEN + description: PA1_CDEN + bit_offset: 16 + bit_size: 1 + - name: PA3_CDEN + description: PA3_CDEN + bit_offset: 17 + bit_size: 1 + - name: PA5_CDEN + description: PA5_CDEN + bit_offset: 18 + bit_size: 1 + - name: PA6_CDEN + description: PA6_CDEN + bit_offset: 19 + bit_size: 1 + - name: PA13_CDEN + description: PA13_CDEN + bit_offset: 20 + bit_size: 1 + - name: PB0_CDEN + description: PB0_CDEN + bit_offset: 21 + bit_size: 1 + - name: PB1_CDEN + description: PB1_CDEN + bit_offset: 22 + bit_size: 1 + - name: PB2_CDEN + description: PB2_CDEN + bit_offset: 23 + bit_size: 1 fieldset/ITLINE0: description: interrupt line 0 status register fields: - - bit_offset: 0 - bit_size: 1 - description: Window watchdog interrupt pending flag - name: WWDG + - name: WWDG + description: Window watchdog interrupt pending flag + bit_offset: 0 + bit_size: 1 fieldset/ITLINE1: description: interrupt line 1 status register fields: - - bit_offset: 0 - bit_size: 1 - description: PVD supply monitoring interrupt request pending (EXTI line 16). - name: PVDOUT + - name: PVDOUT + description: PVD supply monitoring interrupt request pending (EXTI line 16). + bit_offset: 0 + bit_size: 1 fieldset/ITLINE10: description: interrupt line 10 status register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA1_CH1 - name: DMA1_CH2 - - bit_offset: 1 - bit_size: 1 - description: DMA1_CH3 - name: DMA1_CH3 + - name: DMA1_CH2 + description: DMA1_CH1 + bit_offset: 0 + bit_size: 1 + - name: DMA1_CH3 + description: DMA1_CH3 + bit_offset: 1 + bit_size: 1 fieldset/ITLINE11: description: interrupt line 11 status register fields: - - bit_offset: 0 - bit_size: 1 - description: DMAMUX - name: DMAMUX - - bit_offset: 1 - bit_size: 1 - description: DMA1_CH4 - name: DMA1_CH4 - - bit_offset: 2 - bit_size: 1 - description: DMA1_CH5 - name: DMA1_CH5 - - bit_offset: 3 - bit_size: 1 - description: DMA1_CH6 - name: DMA1_CH6 - - bit_offset: 4 - bit_size: 1 - description: DMA1_CH7 - name: DMA1_CH7 + - name: DMAMUX + description: DMAMUX + bit_offset: 0 + bit_size: 1 + - name: DMA1_CH4 + description: DMA1_CH4 + bit_offset: 1 + bit_size: 1 + - name: DMA1_CH5 + description: DMA1_CH5 + bit_offset: 2 + bit_size: 1 + - name: DMA1_CH6 + description: DMA1_CH6 + bit_offset: 3 + bit_size: 1 + - name: DMA1_CH7 + description: DMA1_CH7 + bit_offset: 4 + bit_size: 1 fieldset/ITLINE12: description: interrupt line 12 status register fields: - - bit_offset: 0 - bit_size: 1 - description: ADC - name: ADC - - array: - len: 2 - stride: 1 - bit_offset: 1 - bit_size: 1 - description: COMP1 - name: COMP + - name: ADC + description: ADC + bit_offset: 0 + bit_size: 1 + - name: COMP + description: COMP1 + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/ITLINE13: description: interrupt line 13 status register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM1_CCU - name: TIM1_CCU - - bit_offset: 1 - bit_size: 1 - description: TIM1_TRG - name: TIM1_TRG - - bit_offset: 2 - bit_size: 1 - description: TIM1_UPD - name: TIM1_UPD - - bit_offset: 3 - bit_size: 1 - description: TIM1_BRK - name: TIM1_BRK + - name: TIM1_CCU + description: TIM1_CCU + bit_offset: 0 + bit_size: 1 + - name: TIM1_TRG + description: TIM1_TRG + bit_offset: 1 + bit_size: 1 + - name: TIM1_UPD + description: TIM1_UPD + bit_offset: 2 + bit_size: 1 + - name: TIM1_BRK + description: TIM1_BRK + bit_offset: 3 + bit_size: 1 fieldset/ITLINE14: description: interrupt line 14 status register fields: - - bit_offset: 0 - bit_size: 1 - description: TIM1_CC - name: TIM1_CC + - name: TIM1_CC + description: TIM1_CC + bit_offset: 0 + bit_size: 1 fieldset/ITLINE15: description: interrupt line 15 status register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 1 - description: TIM2 - name: TIM + - name: TIM + description: TIM2 + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 0 fieldset/ITLINE16: description: interrupt line 16 status register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 1 - description: TIM3 - name: TIM + - name: TIM + description: TIM3 + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 0 fieldset/ITLINE17: description: interrupt line 17 status register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 1 - description: TIM6 - name: TIM - - bit_offset: 1 - bit_size: 1 - description: DAC - name: DAC - - array: - len: 1 - stride: 0 - bit_offset: 2 - bit_size: 1 - description: LPTIM1 - name: LPTIM + - name: TIM + description: TIM6 + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 0 + - name: DAC + description: DAC + bit_offset: 1 + bit_size: 1 + - name: LPTIM + description: LPTIM1 + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 0 fieldset/ITLINE18: description: interrupt line 18 status register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 1 - description: TIM7 - name: TIM - - array: - len: 1 - stride: 0 - bit_offset: 1 - bit_size: 1 - description: LPTIM2 - name: LPTIM + - name: TIM + description: TIM7 + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 0 + - name: LPTIM + description: LPTIM2 + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 0 fieldset/ITLINE19: description: interrupt line 19 status register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 1 - description: TIM14 - name: TIM + - name: TIM + description: TIM14 + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 0 fieldset/ITLINE2: description: interrupt line 2 status register fields: - - bit_offset: 0 - bit_size: 1 - description: TAMP - name: TAMP - - bit_offset: 1 - bit_size: 1 - description: RTC - name: RTC + - name: TAMP + description: TAMP + bit_offset: 0 + bit_size: 1 + - name: RTC + description: RTC + bit_offset: 1 + bit_size: 1 fieldset/ITLINE20: description: interrupt line 20 status register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 1 - description: TIM15 - name: TIM + - name: TIM + description: TIM15 + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 0 fieldset/ITLINE21: description: interrupt line 21 status register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 1 - description: TIM16 - name: TIM + - name: TIM + description: TIM16 + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 0 fieldset/ITLINE22: description: interrupt line 22 status register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 1 - description: TIM17 - name: TIM + - name: TIM + description: TIM17 + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 0 fieldset/ITLINE23: description: interrupt line 23 status register fields: - - bit_offset: 0 - bit_size: 1 - description: I2C1 - name: I2C1 + - name: I2C1 + description: I2C1 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE24: description: interrupt line 24 status register fields: - - bit_offset: 0 - bit_size: 1 - description: I2C2 - name: I2C2 + - name: I2C2 + description: I2C2 + bit_offset: 0 + bit_size: 1 fieldset/ITLINE25: description: interrupt line 25 status register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 1 - description: SPI1 - name: SPI + - name: SPI + description: SPI1 + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 0 fieldset/ITLINE26: description: interrupt line 26 status register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 1 - description: SPI2 - name: SPI + - name: SPI + description: SPI2 + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 0 fieldset/ITLINE27: description: interrupt line 27 status register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 1 - description: USART1 - name: USART + - name: USART + description: USART1 + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 0 fieldset/ITLINE28: description: interrupt line 28 status register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 1 - description: USART2 - name: USART + - name: USART + description: USART2 + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 0 fieldset/ITLINE29: description: interrupt line 29 status register fields: - - array: - len: 3 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: USART3 - name: USART + - name: USART + description: USART3 + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 1 fieldset/ITLINE3: description: interrupt line 3 status register fields: - - bit_offset: 0 - bit_size: 1 - description: FLASH_ITF - name: FLASH_ITF - - bit_offset: 1 - bit_size: 1 - description: FLASH_ECC - name: FLASH_ECC + - name: FLASH_ITF + description: FLASH_ITF + bit_offset: 0 + bit_size: 1 + - name: FLASH_ECC + description: FLASH_ECC + bit_offset: 1 + bit_size: 1 fieldset/ITLINE30: description: interrupt line 30 status register fields: - - array: - len: 1 - stride: 0 - bit_offset: 0 - bit_size: 1 - description: CEC - name: USART + - name: USART + description: CEC + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 0 fieldset/ITLINE31: description: interrupt line 31 status register fields: - - bit_offset: 0 - bit_size: 1 - description: RNG - name: RNG - - bit_offset: 1 - bit_size: 1 - description: AES - name: AES + - name: RNG + description: RNG + bit_offset: 0 + bit_size: 1 + - name: AES + description: AES + bit_offset: 1 + bit_size: 1 fieldset/ITLINE4: description: interrupt line 4 status register fields: - - bit_offset: 0 - bit_size: 1 - description: RCC - name: RCC + - name: RCC + description: RCC + bit_offset: 0 + bit_size: 1 fieldset/ITLINE5: description: interrupt line 5 status register fields: - - array: - len: 2 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: EXTI0 - name: EXTI + - name: EXTI + description: EXTI0 + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/ITLINE6: description: interrupt line 6 status register fields: - - array: - len: 2 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: EXTI2 - name: EXTI + - name: EXTI + description: EXTI2 + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/ITLINE7: description: interrupt line 7 status register fields: - - array: - len: 12 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: EXTI4 - name: EXTI + - name: EXTI + description: EXTI4 + bit_offset: 0 + bit_size: 1 + array: + len: 12 + stride: 1 fieldset/ITLINE8: description: interrupt line 8 status register fields: - - array: - len: 2 - stride: 1 - bit_offset: 0 - bit_size: 1 - description: UCPD1 - name: UCPD + - name: UCPD + description: UCPD1 + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/ITLINE9: description: interrupt line 9 status register fields: - - bit_offset: 0 - bit_size: 1 - description: DMA1_CH1 - name: DMA1_CH1 + - name: DMA1_CH1 + description: DMA1_CH1 + bit_offset: 0 + bit_size: 1 fieldset/VREFBUF_CCR: description: VREFBUF calibration control register fields: - - bit_offset: 0 - bit_size: 6 - description: Trimming code These bits are automatically initialized after reset - with the trimming value stored in the Flash memory during the production test. - Writing into these bits allows to tune the internal reference buffer voltage. - name: TRIM + - name: TRIM + description: Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage. + bit_offset: 0 + bit_size: 6 fieldset/VREFBUF_CSR: description: VREFBUF control and status register fields: - - bit_offset: 0 - bit_size: 1 - description: Voltage reference buffer mode enable This bit is used to enable the - voltage reference buffer mode. - name: ENVR - - bit_offset: 1 - bit_size: 1 - description: 'High impedance mode This bit controls the analog switch to connect - or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions - depending on ENVR bit configuration.' - name: HIZ - - bit_offset: 3 - bit_size: 1 - description: Voltage reference buffer ready - name: VRR - - bit_offset: 4 - bit_size: 3 - description: 'Voltage reference scale These bits select the value generated by - the voltage reference buffer. Other: Reserved' - name: VRS + - name: ENVR + description: Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. + bit_offset: 0 + bit_size: 1 + - name: HIZ + description: "High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration." + bit_offset: 1 + bit_size: 1 + - name: VRR + description: Voltage reference buffer ready + bit_offset: 3 + bit_size: 1 + - name: VRS + description: "Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved" + bit_offset: 4 + bit_size: 3 diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index aae5046..851964a 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -1,47 +1,72 @@ --- +block/TIM_ADV: + extends: TIM_GP16 + description: Advanced-timers + items: + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_ADV + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_ADV + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_ADV + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_ADV + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_ADV block/TIM_BASIC: description: Basic timer items: - name: CR1 description: control register 1 byte_offset: 0 - reset_value: 0 fieldset: CR1_BASIC - name: CR2 description: control register 2 byte_offset: 4 - reset_value: 0 fieldset: CR2_BASIC - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - reset_value: 0 fieldset: DIER_BASIC - name: SR description: status register byte_offset: 16 - reset_value: 0 fieldset: SR_BASIC - name: EGR description: event generation register byte_offset: 20 - reset_value: 0 access: Write fieldset: EGR_BASIC - name: CNT description: counter byte_offset: 36 - reset_value: 0 fieldset: CNT_16 - name: PSC description: prescaler byte_offset: 40 - reset_value: 0 fieldset: PSC - name: ARR description: auto-reload register byte_offset: 44 - reset_value: 0 fieldset: ARR_16 block/TIM_GP16: extends: TIM_BASIC @@ -50,32 +75,26 @@ block/TIM_GP16: - name: CR1 description: control register 1 byte_offset: 0 - reset_value: 0 fieldset: CR1_GP - name: CR2 description: control register 2 byte_offset: 4 - reset_value: 0 fieldset: CR2_GP - name: SMCR description: slave mode control register byte_offset: 8 - reset_value: 0 fieldset: SMCR - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - reset_value: 0 fieldset: DIER_GP - name: SR description: status register byte_offset: 16 - reset_value: 0 fieldset: SR_GP - name: EGR description: event generation register byte_offset: 20 - reset_value: 0 access: Write fieldset: EGR_GP - name: CCMR_Input @@ -84,7 +103,6 @@ block/TIM_GP16: len: 2 stride: 4 byte_offset: 24 - reset_value: 0 fieldset: CCMR_Input - name: CCMR_Output description: capture/compare mode register 1 (output mode) @@ -92,27 +110,22 @@ block/TIM_GP16: len: 2 stride: 4 byte_offset: 24 - reset_value: 0 fieldset: CCMR_Output - name: CCER description: capture/compare enable register byte_offset: 32 - reset_value: 0 fieldset: CCER_GP - name: PSC description: prescaler byte_offset: 40 - reset_value: 0 fieldset: PSC - name: DCR description: DMA control register byte_offset: 72 - reset_value: 0 fieldset: DCR - name: DMAR description: DMA address for full transfer byte_offset: 76 - reset_value: 0 fieldset: DMAR - name: CCR description: capture/compare register @@ -120,7 +133,6 @@ block/TIM_GP16: len: 4 stride: 4 byte_offset: 52 - reset_value: 0 fieldset: CCR_16 block/TIM_GP32: extends: TIM_GP16 @@ -129,12 +141,10 @@ block/TIM_GP32: - name: CNT description: counter byte_offset: 36 - reset_value: 0 fieldset: CNT_32 - name: ARR description: auto-reload register byte_offset: 44 - reset_value: 0 fieldset: ARR_32 - name: CCR description: capture/compare register @@ -142,55 +152,7 @@ block/TIM_GP32: len: 4 stride: 4 byte_offset: 52 - reset_value: 0 fieldset: CCR_32 -block/TIM_ADV: - extends: TIM_GP16 - description: Advanced-timers - items: - - name: RCR - description: repetition counter register - byte_offset: 48 - reset_value: 0 - fieldset: RCR - - name: BDTR - description: break and dead-time register - byte_offset: 68 - reset_value: 0 - fieldset: BDTR - - name: CCER - description: capture/compare enable register - byte_offset: 32 - reset_value: 0 - fieldset: CCER_ADV - - name: CR2 - description: control register 2 - byte_offset: 4 - reset_value: 0 - fieldset: CR2_ADV - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - reset_value: 0 - fieldset: DIER_ADV - - name: SR - description: status register - byte_offset: 16 - reset_value: 0 - fieldset: SR_ADV - - name: EGR - description: event generation register - byte_offset: 20 - reset_value: 0 - access: Write - fieldset: EGR_ADV -fieldset/ARR_32: - description: auto-reload register - fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 32 fieldset/ARR_16: description: auto-reload register fields: @@ -198,34 +160,13 @@ fieldset/ARR_16: description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/CCR_32: - description: capture/compare register 1 +fieldset/ARR_32: + description: auto-reload register fields: - - name: CCR - description: Capture/Compare 1 value + - name: ARR + description: Auto-reload value bit_offset: 0 bit_size: 32 -fieldset/CCR_16: - description: capture/compare register 1 - fields: - - name: CCR - description: Capture/Compare 1 value - bit_offset: 0 - bit_size: 16 -fieldset/CNT_32: - description: counter - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 32 -fieldset/CNT_16: - description: counter - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 16 fieldset/BDTR: description: break and dead-time register fields: @@ -263,6 +204,17 @@ fieldset/BDTR: description: Main output enable bit_offset: 15 bit_size: 1 +fieldset/CCER_ADV: + extends: CCER_GP + description: capture/compare enable register + fields: + - name: CCNE + description: Capture/Compare 1 complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 4 + stride: 4 fieldset/CCER_GP: description: capture/compare enable register fields: @@ -287,17 +239,6 @@ fieldset/CCER_GP: array: len: 4 stride: 4 -fieldset/CCER_ADV: - extends: CCER_GP - description: capture/compare enable register - fields: - - name: CCNE - description: Capture/Compare 1 complementary output enable - bit_offset: 2 - bit_size: 1 - array: - len: 4 - stride: 4 fieldset/CCMR_Input: description: capture/compare mode register 1 (input mode) fields: @@ -365,6 +306,34 @@ fieldset/CCMR_Output: array: len: 2 stride: 8 +fieldset/CCR_16: + description: capture/compare register 1 + fields: + - name: CCR + description: Capture/Compare 1 value + bit_offset: 0 + bit_size: 16 +fieldset/CCR_32: + description: capture/compare register 1 + fields: + - name: CCR + description: Capture/Compare 1 value + bit_offset: 0 + bit_size: 32 +fieldset/CNT_16: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 16 +fieldset/CNT_32: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 32 fieldset/CR1_BASIC: description: control register 1 fields: @@ -410,28 +379,6 @@ fieldset/CR1_GP: bit_offset: 8 bit_size: 2 enum: CKD -fieldset/CR2_BASIC: - description: control register 2 - fields: - - name: MMS - description: Master mode selection - bit_offset: 4 - bit_size: 3 - enum: MMS -fieldset/CR2_GP: - extends: CR2_BASIC - description: control register 2 - fields: - - name: CCDS - description: Capture/compare DMA selection - bit_offset: 3 - bit_size: 1 - enum: CCDS - - name: TI1S - description: TI1 selection - bit_offset: 7 - bit_size: 1 - enum: TIS fieldset/CR2_ADV: extends: CR2_GP description: control register 2 @@ -463,6 +410,28 @@ fieldset/CR2_ADV: description: Output Idle state 3 bit_offset: 13 bit_size: 1 +fieldset/CR2_BASIC: + description: control register 2 + fields: + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS +fieldset/CR2_GP: + extends: CR2_BASIC + description: control register 2 + fields: + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TIS fieldset/DCR: description: DMA control register fields: @@ -474,6 +443,22 @@ fieldset/DCR: description: DMA burst length bit_offset: 8 bit_size: 5 +fieldset/DIER_ADV: + extends: DIER_GP + description: DMA/Interrupt enable register + fields: + - name: COMIE + description: COM interrupt enable + bit_offset: 5 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: COMDE + description: COM DMA request enable + bit_offset: 13 + bit_size: 1 fieldset/DIER_BASIC: description: DMA/Interrupt enable register fields: @@ -511,22 +496,6 @@ fieldset/DIER_GP: description: Trigger DMA request enable bit_offset: 14 bit_size: 1 -fieldset/DIER_ADV: - extends: DIER_GP - description: DMA/Interrupt enable register - fields: - - name: COMIE - description: COM interrupt enable - bit_offset: 5 - bit_size: 1 - - name: BIE - description: Break interrupt enable - bit_offset: 7 - bit_size: 1 - - name: COMDE - description: COM DMA request enable - bit_offset: 13 - bit_size: 1 fieldset/DMAR: description: DMA address for full transfer fields: @@ -534,6 +503,18 @@ fieldset/DMAR: description: DMA register for burst accesses bit_offset: 0 bit_size: 16 +fieldset/EGR_ADV: + extends: EGR_GP + description: event generation register + fields: + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: BG + description: Break generation + bit_offset: 7 + bit_size: 1 fieldset/EGR_BASIC: description: event generation register fields: @@ -564,18 +545,6 @@ fieldset/EGR_GP: description: Break generation bit_offset: 7 bit_size: 1 -fieldset/EGR_ADV: - extends: EGR_GP - description: event generation register - fields: - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 - bit_size: 1 - - name: BG - description: Break generation - bit_offset: 7 - bit_size: 1 fieldset/PSC: description: prescaler fields: @@ -628,6 +597,18 @@ fieldset/SMCR: bit_offset: 15 bit_size: 1 enum: ETP +fieldset/SR_ADV: + extends: SR_GP + description: status register + fields: + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: BIF + description: Break interrupt flag + bit_offset: 7 + bit_size: 1 fieldset/SR_BASIC: description: status register fields: @@ -665,18 +646,6 @@ fieldset/SR_GP: array: len: 4 stride: 1 -fieldset/SR_ADV: - extends: SR_GP - description: status register - fields: - - name: COMIF - description: COM interrupt flag - bit_offset: 5 - bit_size: 1 - - name: BIF - description: Break interrupt flag - bit_offset: 7 - bit_size: 1 enum/ARPE: bit_size: 1 variants: @@ -1051,4 +1020,4 @@ enum/URS: value: 0 - name: CounterOnly description: Only counter overflow/underflow generates an update interrupt or DMA request - value: 1 \ No newline at end of file + value: 1 diff --git a/data/registers/usart_v1.yaml b/data/registers/usart_v1.yaml index 8224520..767f23a 100644 --- a/data/registers/usart_v1.yaml +++ b/data/registers/usart_v1.yaml @@ -5,32 +5,26 @@ block/UART: - name: SR description: Status register byte_offset: 0 - reset_value: 192 fieldset: SR - name: DR description: Data register byte_offset: 4 - reset_value: 0 fieldset: DR - name: BRR description: Baud rate register byte_offset: 8 - reset_value: 0 fieldset: BRR - name: CR1 description: Control register 1 byte_offset: 12 - reset_value: 0 fieldset: CR1 - name: CR2 description: Control register 2 byte_offset: 16 - reset_value: 0 fieldset: CR2 - name: CR3 description: Control register 3 byte_offset: 20 - reset_value: 0 fieldset: CR3 block/USART: extends: UART @@ -39,17 +33,14 @@ block/USART: - name: CR2 description: Control register 2 byte_offset: 16 - reset_value: 0 fieldset: CR2_USART - name: CR3 description: Control register 3 byte_offset: 20 - reset_value: 0 fieldset: CR3_USART - name: GTPR description: Guard time and prescaler register byte_offset: 24 - reset_value: 0 fieldset: GTPR fieldset/BRR: description: Baud rate register @@ -395,4 +386,4 @@ enum/WAKE: value: 0 - name: AddressMark description: USART wakeup on address mark - value: 1 \ No newline at end of file + value: 1 diff --git a/data/registers/usart_v2.yaml b/data/registers/usart_v2.yaml index 0ff3a66..f3def30 100644 --- a/data/registers/usart_v2.yaml +++ b/data/registers/usart_v2.yaml @@ -327,6 +327,13 @@ fieldset/CR3: description: Wakeup from Stop mode interrupt enable bit_offset: 22 bit_size: 1 +fieldset/DR: + description: Data register + fields: + - name: DR + description: Data value + bit_offset: 0 + bit_size: 9 fieldset/GTPR: description: Guard time and prescaler register fields: @@ -429,13 +436,6 @@ fieldset/IXR: description: Receive enable acknowledge flag bit_offset: 22 bit_size: 1 -fieldset/DR: - description: Data register - fields: - - name: DR - description: Data value - bit_offset: 0 - bit_size: 9 fieldset/RQR: description: Request register fields: @@ -444,7 +444,7 @@ fieldset/RQR: bit_offset: 0 bit_size: 1 - name: SBKRQ - description: Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available + description: "Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available" bit_offset: 1 bit_size: 1 - name: MMRQ @@ -452,7 +452,7 @@ fieldset/RQR: bit_offset: 2 bit_size: 1 - name: RXFRQ - description: Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition + description: "Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition" bit_offset: 3 bit_size: 1 - name: TXFRQ diff --git a/data/registers/wwdg_v1.yaml b/data/registers/wwdg_v1.yaml index 65a11e7..9b55c3b 100644 --- a/data/registers/wwdg_v1.yaml +++ b/data/registers/wwdg_v1.yaml @@ -2,98 +2,98 @@ block/WWDG: description: Window watchdog items: - - byte_offset: 0 - description: Control register - fieldset: CR - name: CR - - byte_offset: 4 - description: Configuration register - fieldset: CFR - name: CFR - - byte_offset: 8 - description: Status register - fieldset: SR - name: SR -enum/EWIFR: - bit_size: 1 - variants: - - description: The EWI Interrupt Service Routine has been serviced - name: Finished - value: 0 - - description: The EWI Interrupt Service Routine has been triggered - name: Pending - value: 1 -enum/EWIFW: - bit_size: 1 - variants: - - description: The EWI Interrupt Service Routine has been serviced - name: Finished - value: 0 -enum/EWIW: - bit_size: 1 - variants: - - description: interrupt occurs whenever the counter reaches the value 0x40 - name: Enable - value: 1 -enum/WDGA: - bit_size: 1 - variants: - - description: Watchdog disabled - name: Disabled - value: 0 - - description: Watchdog enabled - name: Enabled - value: 1 -enum/WDGTB: - bit_size: 2 - variants: - - description: Counter clock (PCLK1 div 4096) div 1 - name: Div1 - value: 0 - - description: Counter clock (PCLK1 div 4096) div 2 - name: Div2 - value: 1 - - description: Counter clock (PCLK1 div 4096) div 4 - name: Div4 - value: 2 - - description: Counter clock (PCLK1 div 4096) div 8 - name: Div8 - value: 3 + - name: CR + description: Control register + byte_offset: 0 + fieldset: CR + - name: CFR + description: Configuration register + byte_offset: 4 + fieldset: CFR + - name: SR + description: Status register + byte_offset: 8 + fieldset: SR fieldset/CFR: description: Configuration register fields: - - bit_offset: 0 - bit_size: 7 - description: 7-bit window value - name: W - - bit_offset: 7 - bit_size: 2 - description: Timer base - enum: WDGTB - name: WDGTB - - bit_offset: 9 - bit_size: 1 - description: Early wakeup interrupt - enum_write: EWIW - name: EWI + - name: W + description: 7-bit window value + bit_offset: 0 + bit_size: 7 + - name: WDGTB + description: Timer base + bit_offset: 7 + bit_size: 2 + enum: WDGTB + - name: EWI + description: Early wakeup interrupt + bit_offset: 9 + bit_size: 1 + enum_write: EWIW fieldset/CR: description: Control register fields: - - bit_offset: 0 - bit_size: 7 - description: 7-bit counter (MSB to LSB) - name: T - - bit_offset: 7 - bit_size: 1 - description: Activation bit - enum: WDGA - name: WDGA + - name: T + description: 7-bit counter (MSB to LSB) + bit_offset: 0 + bit_size: 7 + - name: WDGA + description: Activation bit + bit_offset: 7 + bit_size: 1 + enum: WDGA fieldset/SR: description: Status register fields: - - bit_offset: 0 - bit_size: 1 - description: Early wakeup interrupt flag - enum_read: EWIFR - enum_write: EWIFW - name: EWIF + - name: EWIF + description: Early wakeup interrupt flag + bit_offset: 0 + bit_size: 1 + enum_read: EWIFR + enum_write: EWIFW +enum/EWIFR: + bit_size: 1 + variants: + - name: Finished + description: The EWI Interrupt Service Routine has been serviced + value: 0 + - name: Pending + description: The EWI Interrupt Service Routine has been triggered + value: 1 +enum/EWIFW: + bit_size: 1 + variants: + - name: Finished + description: The EWI Interrupt Service Routine has been serviced + value: 0 +enum/EWIW: + bit_size: 1 + variants: + - name: Enable + description: interrupt occurs whenever the counter reaches the value 0x40 + value: 1 +enum/WDGA: + bit_size: 1 + variants: + - name: Disabled + description: Watchdog disabled + value: 0 + - name: Enabled + description: Watchdog enabled + value: 1 +enum/WDGTB: + bit_size: 2 + variants: + - name: Div1 + description: Counter clock (PCLK1 div 4096) div 1 + value: 0 + - name: Div2 + description: Counter clock (PCLK1 div 4096) div 2 + value: 1 + - name: Div4 + description: Counter clock (PCLK1 div 4096) div 4 + value: 2 + - name: Div8 + description: Counter clock (PCLK1 div 4096) div 8 + value: 3