0fd7b9582f
Merge branch 'embassy-rs:main' into main
2024-05-28 13:41:16 -04:00
Dario Nieuwenhuis
ad633a3e26
Merge pull request #482 from liarokapisv/spi_v3-I2SCFGR
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added I2SCFGR register to spi_v3.yaml
2024-05-22 10:05:51 +00:00
Dario Nieuwenhuis
34c0188a68
hsem: remove incorrect readonly mark.
2024-05-21 23:13:02 +02:00
Alexandros Liarokapis
1f3fd240c5
added I2SCFGR register to spi_v3.yaml
2024-05-21 02:44:43 +03:00
Alexandros Liarokapis
ac1adf946e
Added SPI45SEL to RCC for STM32H7 devices.
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RCC mux was missing the SPI45SEL selector. I had to add an extra rule to
the rcc.rs and fix the wrong SPI45SEL entries in rcc_h7ab.yaml and rcc_h7rs.yaml.
I confirmed that both default entries point to the PCLK2 instead of HCLK2.
2024-05-21 02:44:43 +03:00
Alexandros Liarokapis
8059f940cf
Added SPI45SEL to RCC for STM32H7 devices.
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RCC mux was missing the SPI45SEL selector. I had to add an extra rule to
the rcc.rs and fix the wrong SPI45SEL entries in rcc_h7ab.yaml and rcc_h7rs.yaml.
I confirmed that both default entries point to the PCLK2 instead of HCLK2.
2024-05-15 22:20:10 +03:00
8ba0a0a524
Merge branch 'embassy-rs:main' into main
2024-05-01 16:08:28 -04:00
Dario Nieuwenhuis
06e84ca199
add i2cv3 for h7rs.
2024-05-01 16:11:17 +02:00
Dario Nieuwenhuis
5d58d7ddda
chiptool fmt.
2024-05-01 16:11:06 +02:00
Dario Nieuwenhuis
afee4331ad
Add stm32h7rs family.
2024-05-01 02:16:15 +02:00
Dario Nieuwenhuis
a9e67aee12
chiptool fmt.
2024-04-30 02:25:46 +02:00
Dario Nieuwenhuis
37a0941112
Add LPDMA regs, cleanup GPDMA.
2024-04-29 20:47:57 +02:00
Dario Nieuwenhuis
e001b7dfcd
Add U5 LPDMA.
2024-04-29 18:33:48 +02:00
Dario Nieuwenhuis
37ec0ab67d
Use normalize for SBS->SYSCFG rename.
2024-04-28 23:44:57 +02:00
eZio Pan
e7ed894763
align PWR H50x to H5
2024-04-24 20:39:00 +08:00
Karun Koppula
1ab47a96b4
Update rcc config for l0 family tsc
2024-04-22 12:53:23 -04:00
Dario Nieuwenhuis
9db1729024
Merge pull request #468 from Systemscape/main
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Add DSIHOST support
2024-04-17 10:08:21 +00:00
Dario Nieuwenhuis
0e2a82de8d
Merge pull request #456 from eZioPan/lptim
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rework on LPTIM
2024-04-17 10:03:22 +00:00
bd6bc952a2
update otg high speed - ahbcfg dma en
2024-04-16 12:22:17 -04:00
Dion Dokter
50f329f131
Add opamp and rtc
2024-04-16 14:44:38 +02:00
68b0e791cf
update otg high speed - mpsiz 0 access mode
2024-04-15 11:39:58 -04:00
JuliDi
f1e684e345
fix ltdc_v1.yaml bfcr wrong definition
2024-04-15 09:20:50 +02:00
JuliDi
804326f93f
add dsihost for u5 chip family
2024-04-15 09:20:50 +02:00
JuliDi
95ff92f362
remove DSISEL from other register ymls where it is not present
2024-04-15 09:20:50 +02:00
JuliDi
dd12c3787a
change DSIPHY to DSI_PHY for rcc_l4plus.yaml to match other families
2024-04-15 09:20:50 +02:00
Joël Schulz-Ansres
8ec40e422c
Add DSIHOST support
2024-04-15 09:19:55 +02:00
d6d2f3e1ac
update otg high speed
2024-04-14 22:24:28 -04:00
160921a008
update otg high speed
2024-04-14 18:35:33 -04:00
a98c13faf5
Merge branch 'embassy-rs:main' into main
2024-04-14 12:39:59 -04:00
94439f8c67
init otg highspeed
2024-04-14 12:37:15 -04:00
Dion Dokter
a4d4695635
Add aes, crc, tsc and comp
2024-04-14 02:01:06 +02:00
Dion Dokter
7b08f67dfb
Add ADC which is basically the G0 adc but not really
2024-04-14 00:04:06 +02:00
Dion Dokter
a6ff95d7b6
Add the usbram yaml
2024-04-13 23:21:40 +02:00
eZio Pan
510f269a69
add lptim_v2b for u0
2024-04-13 23:36:32 +08:00
eZio Pan
0d43029663
lptim_v1 for l0
2024-04-13 23:27:11 +08:00
eZio Pan
d2fcff2e5e
lptim_v1a for l4(no plus), f4, f7
2024-04-13 23:27:11 +08:00
eZio Pan
096616ceda
lptim_v1b for l4+, g0, wb
2024-04-13 23:27:11 +08:00
eZio Pan
e90a3f9246
lptim_v1b_g4 for g4
2024-04-13 23:27:11 +08:00
eZio Pan
14301aa848
lptim_v1b_h7 for h7
2024-04-13 23:27:11 +08:00
eZio Pan
c3fb098274
lptim_v1c for l5 wl
2024-04-13 23:27:11 +08:00
eZio Pan
af7aefa4fe
keep lptim_v2 and remove others
2024-04-13 23:26:04 +08:00
Dario Nieuwenhuis
d4a97f60b1
Add stm32u0.
2024-04-13 03:16:25 +02:00
Dario Nieuwenhuis
b1034db59a
Merge pull request #463 from MaxiluxSystems/feature/product-states
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flash_h50: add PRODUCT_STATE enum; improve a couple other fields
2024-04-12 19:38:24 +00:00
Torin Cooper-Bennun
62b1ab50db
flash_h50: rename BKSEL variants
2024-04-12 17:04:33 +01:00
Torin Cooper-Bennun
4df4f6840c
flash_h50: plain bool for SWAP_BANK fields
2024-04-12 17:03:44 +01:00
Torin Cooper-Bennun
a0c7c136fa
flash_h50: add PRODUCT_STATE enum
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the values are taken from the official HAL headers; I have only included
enum variants which are definitively mentioned in RM0492, excluding
other variants mentioned in the HAL headers
2024-04-11 10:25:07 +01:00
Torin Cooper-Bennun
f60ad0d665
flash_h50: make _CUR registers read-only
2024-04-11 10:24:55 +01:00
Dario Nieuwenhuis
604890b9ba
hsem: rename more MASTERID->COREID
2024-04-08 14:07:46 +02:00
Michael Zill
b782384611
Arrayfied IER, ICR, ISR and MISR
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IRQ registers have for all 4 variants the same name.
V1 - array size = 2 (2 cores)
V2 - array size = 1 (1 core)
V3 - array size = 2 (2 cores)
V4 - array size = 1 (1 core)
HSEM added to GHOST_PERIS
2024-04-08 13:38:36 +02:00
Michael Zill
840e5ec5db
Fixed length COREID in v1, v2 renamed MASTERID to COREID
2024-04-08 13:36:40 +02:00
