Merge branch 'embassy-rs:main' into main

README.md

@@ -12,7 +12,7 @@ families, including:
 - :x: GPIO mappings for F1
 - :construction: Register blocks for all peripherals
 - :heavy_check_mark: DMA stream mappings
-- :x: Per-package pinouts
+- :heavy_check_mark: Per-package pinouts
 - :heavy_check_mark: Links to applicable reference manuals, datasheets, appnotes PDFs.
 
 :heavy_check_mark: = done, :construction: = work in progress, :x: = to do

data/registers/hsem_v2.yaml

@@ -29,7 +29,6 @@ block/HSEM:
       len: 1
       stride: 16
     byte_offset: 260
-    access: Read
     fieldset: ICR
   - name: ISR
     description: HSEM Interrupt status register.

data/registers/rcc_h7ab.yaml

@@ -4305,7 +4305,7 @@ enum/SPDIFRXSEL:
 enum/SPI45SEL:
   bit_size: 3
   variants:
-  - name: HCLK2
+  - name: PCLK2
     description: APB2 clock selected as peripheral clock
     value: 0
   - name: PLL2_Q

data/registers/rcc_h7rs.yaml

@@ -4095,7 +4095,7 @@ enum/SPI123SEL:
 enum/SPI45SEL:
   bit_size: 3
   variants:
-  - name: HCLK2
+  - name: PCLK2
     description: APB2 clock selected as peripheral clock
     value: 0
   - name: PLL2_Q

data/registers/spi_v3.yaml

@@ -75,6 +75,10 @@ block/SPI:
     description: Underrun Data Register
     byte_offset: 76
     fieldset: UDRDR
+  - name: I2SCFGR
+    description: I2S Configuration Register
+    byte_offset: 80
+    fieldset: I2SCFGR
 fieldset/CFG1:
   description: configuration register 1
   fields:
@@ -425,6 +429,70 @@ fieldset/UDRDR:
     description: Data at slave underrun condition
     bit_offset: 0
     bit_size: 32
+fieldset/I2SCFGR:
+  description: I2S Configuration Register
+  fields:
+  - name: MCKOE
+    description: Master clock output enable
+    bit_offset: 25
+    bit_size: 1
+  - name: ODD
+    description: Odd factor for the prescaler
+    bit_offset: 24
+    bit_size: 1
+    enum: ODD
+  - name: I2SDIV
+    description: I2S linear prescaler
+    bit_offset: 16
+    bit_size: 8
+  - name: DATFMT
+    description: Data format
+    bit_offset: 14
+    bit_size: 1
+    enum: DATFMT
+  - name: WSINV
+    description: Word select inversion
+    bit_offset: 13
+    bit_size: 1
+  - name: FIXCH
+    description: Fixed channel length in slave
+    bit_offset: 12
+    bit_size: 1
+    enum: FIXCH
+  - name: CKPOL
+    description: Serial audio clock polarity
+    bit_offset: 11
+    bit_size: 1
+    enum: CKPOL
+  - name: CHLEN
+    description: Channel length (number of bits per audio channel)
+    bit_offset: 10
+    bit_size: 1
+    enum: CHLEN
+  - name: DATLEN
+    description: Data length to be transferred
+    bit_offset: 8
+    bit_size: 2
+    enum: DATLEN
+  - name: PCMSYNC
+    description: PCM frame synchronization
+    bit_offset: 7
+    bit_size: 1
+    enum: PCMSYNC
+  - name: I2SSTD
+    description: I2S standard selection
+    bit_offset: 4
+    bit_size: 2
+    enum: I2SSTD
+  - name: I2SCFG
+    description: I2S configuration mode
+    bit_offset: 1
+    bit_size: 3
+    enum: I2SCFG
+  - name: I2SMOD
+    description: I2S mode selection
+    bit_offset: 0
+    bit_size: 1
 enum/COMM:
   bit_size: 2
   variants:
@@ -453,10 +521,10 @@ enum/CPOL:
   bit_size: 1
   variants:
   - name: IdleLow
-    description: CK to 0 when idle
+    description: SCK to 0 when idle
     value: 0
   - name: IdleHigh
-    description: CK to 1 when idle
+    description: SCK to 1 when idle
     value: 1
 enum/FTHLV:
   bit_size: 4
@@ -656,3 +724,105 @@ enum/UDRDET:
   - name: StartOfSlaveSelect
     description: Underrun is detected at begin of active SS signal
     value: 2
+enum/ODD:
+  bit_size: 1
+  variants:
+  - name: Even
+    description: Real divider value is I2SDIV*2
+    value: 0
+  - name: Odd
+    description: Real divider value is I2SDIV*2 + 1
+    value: 1
+enum/DATFMT:
+  bit_size: 1
+  variants:
+  - name: RightAligned
+    description: The data inside RXDR and TXDR are right aligned
+    value: 0
+  - name: LeftAligned
+    description: The data inside RXDR and TXDR are left aligned
+    value: 1
+enum/FIXCH:
+  bit_size: 1
+  variants:
+  - name: NotFixed
+    description: The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account)
+    value: 0
+  - name: Fixed
+    description: The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN)
+    value: 1
+enum/CKPOL:
+  bit_size: 1
+  variants:
+  - name: IdleLow
+    description: CK idle Level is Low. Signals are sampled on rising and changed on falling clock edges
+    value: 0
+  - name: IdleHigh
+    description: CK idle level is High. Signals are sampled on falling and changed on rising clock edges
+    value: 1
+enum/CHLEN:
+  bit_size: 1
+  variants:
+  - name: Bits16
+    description: 16 bits per channel
+    value: 0
+  - name: Bits32
+    description: 32 bits per channel
+    value: 1
+enum/DATLEN:
+  bit_size: 2
+  variants:
+  - name: Bits16
+    description: 16-bit data length
+    value: 0
+  - name: Bits24
+    description: 24-bit data length
+    value: 1
+  - name: Bits32
+    description: 32-bit data length
+    value: 2
+enum/PCMSYNC:
+  bit_size: 1
+  variants:
+  - name: Short
+    description: Short PCM frame synchronization
+    value: 0
+  - name: Long
+    description: Long PCM frame synchronization
+    value: 1
+enum/I2SSTD:
+  bit_size: 2
+  variants:
+  - name: Philips
+    description: I2S Philips standard
+    value: 0
+  - name: MSB
+    description: MSB/left justified standard
+    value: 1
+  - name: LSB
+    description: LSB/right justified standard
+    value: 2
+  - name: PCM
+    description: PCM standard
+    value: 3
+enum/I2SCFG:
+  bit_size: 3
+  variants:
+  - name: SlaveTx
+    description: Slave, transmit
+    value: 0
+  - name: SlaveRx
+    description: Slave, receive
+    value: 1
+  - name: MasterTx
+    description: Master, transmit
+    value: 2
+  - name: MasterRx
+    description: Master, receive
+    value: 3
+  - name: SlaveFullDuplex
+    description: Slave, full duplex
+    value: 4
+  - name: MasterFullDuplex
+    description: Master, full duplex
+    value: 5

stm32-data-gen/src/chips.rs

@@ -38,6 +38,8 @@ mod xml {
     pub struct Pin {
         #[serde(rename = "Name")]
         pub name: String,
+        #[serde(rename = "Position")]
+        pub position: String,
         #[serde(rename = "Signal", default)]
         pub signals: Vec<PinSignal>,
     }
@@ -886,6 +888,25 @@ fn parse_group(
         group_idx
     });
 
+    let mut package_pins: HashMap<String, Vec<String>> = HashMap::new();
+    for pin in &parsed.pins {
+        package_pins
+            .entry(pin.position.clone())
+            .or_default()
+            .push(gpio_af::clean_pin(&pin.name).unwrap_or_else(|| pin.name.clone()));
+    }
+    let mut package_pins: Vec<stm32_data_serde::chip::PackagePin> = package_pins
+        .into_iter()
+        .map(|(position, mut signals)| {
+            signals.sort();
+            stm32_data_serde::chip::PackagePin { position, signals }
+        })
+        .collect();
+    package_pins.sort_by_key(|p| match p.position.parse::<u32>() {
+        Ok(n) => (Some(n), None),
+        Err(_) => (None, Some(p.position.clone())),
+    });
+
     for (package_i, package_name) in package_names.iter().enumerate() {
         let chip_name = chip_name_from_package_name(package_name);
         if !chips.contains_key(&chip_name) {
@@ -906,6 +927,7 @@ fn parse_group(
             .push(stm32_data_serde::chip::Package {
                 name: package_name.clone(),
                 package: parsed.package.clone(),
+                pins: package_pins.clone(),
             });
     }
 

stm32-data-gen/src/memory.rs

@@ -132,9 +132,9 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
     ("STM32G07..8",                  mem!(BANK_1 0x08000000 64, SRAM 0x20000000 32)),
     ("STM32G0B..B",                  mem!(BANK_1 0x08000000 128, SRAM 0x20000000 128)),
     // G4. TODO: check
-    ("STM32G4...6",                  mem!(BANK_1 0x08000000 32, SRAM 0x20000000 20, SRAM2 0x20004000 0)),
-    ("STM32G4...8",                  mem!(BANK_1 0x08000000 64, SRAM 0x20000000 20, SRAM2 0x20004000 0)),
-    ("STM32G4[34]..B",               mem!(BANK_1 0x08000000 128, SRAM 0x20000000 20, SRAM2 0x20004000 0)),
+    ("STM32G4...6",                  mem!(BANK_1 0x08000000 32, CCM_SRAM_ICODE 0x10000000 10, SRAM1 0x20000000 16, SRAM2 0x20004000 6, CCM_SRAM_DCODE 0x20005800 10)),
+    ("STM32G4...8",                  mem!(BANK_1 0x08000000 64, CCM_SRAM_ICODE 0x10000000 10, SRAM1 0x20000000 16, SRAM2 0x20004000 6, CCM_SRAM_DCODE 0x20005800 10)),
+    ("STM32G4[34]..B",               mem!(BANK_1 0x08000000 128, CCM_SRAM_ICODE 0x10000000 10, SRAM1 0x20000000 16, SRAM2 0x20004000 6, CCM_SRAM_DCODE 0x20005800 10)),
     ("STM32G4[78]..E",               mem!(BANK_1 0x08000000 512, SRAM 0x20000000 96, SRAM2 0x20014000 0)),
     ("STM32G4[9A]..E",               mem!(BANK_1 0x08000000 512, SRAM 0x20000000 32, SRAM2 0x20014000 0)),
     ("STM32G47..B",                  mem!(BANK_1 0x08000000 128, SRAM 0x20000000 96, SRAM2 0x20014000 0)),

stm32-data-gen/src/rcc.rs

@@ -284,8 +284,8 @@ impl ParsedRccs {
             ("SPI1", &["SPI12", "SPI123"]),
             ("SPI2", &["SPI12", "SPI123"]),
             ("SPI3", &["SPI123"]),
-            ("SPI4", &["SPI145"]),
-            ("SPI5", &["SPI145"]),
+            ("SPI4", &["SPI145", "SPI45"]),
+            ("SPI5", &["SPI145", "SPI45"]),
             ("SAI1", &["SAI12"]),
             ("SAI2", &["SAI12", "SAI23"]),
             ("SAI3", &["SAI23"]),

stm32-data-serde/src/lib.rs

@@ -34,6 +34,13 @@ pub mod chip {
     pub struct Package {
         pub name: String,
         pub package: String,
+        pub pins: Vec<PackagePin>,
+    }
+
+    #[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)]
+    pub struct PackagePin {
+        pub position: String,
+        pub signals: Vec<String>,
     }
 
     #[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)]