Add stm32h7rs family.

2024-05-01 02:16:15 +02:00 · 2024-05-01 02:16:15 +02:00 · afee4331ad
commit afee4331ad
parent a9e67aee12
23 changed files with 6687 additions and 54 deletions
--- a/data/dmamux/H7RS_GPDMA.yaml
+++ b/data/dmamux/H7RS_GPDMA.yaml
@ -0,0 +1,110 @@
+ADC1: 0
+ADC2: 1
+CRYP_IN: 2
+CRYP_OUT: 3
+SAES_OUT: 4
+SAES_IN: 5
+HASH: 6
+TIM1_CC: 7
+TIM1_CC: 8
+TIM1_CC: 9
+TIM1_CC: 10
+TIM1_UP: 11
+TIM1_TRG: 12
+TIM1_COM: 13
+TIM2_CC: 14
+TIM2_CC: 15
+TIM2_CC: 16
+TIM2_CC: 17
+TIM2_UP: 18
+TIM2_TRG: 19
+TIM3_CC: 20
+TIM3_CC: 21
+TIM3_CC: 22
+TIM3_CC: 23
+TIM3_UP: 24
+TIM3_TRG: 25
+TIM4_CC: 26
+TIM4_CC: 27
+TIM4_CC: 28
+TIM4_CC: 29
+TIM4_UP: 30
+TIM4_TRG: 31
+TIM5_CC: 32
+TIM5_CC: 33
+TIM5_CC: 34
+TIM5_CC: 35
+TIM5_UP: 36
+TIM5_TRG: 37
+TIM6_UP: 38
+TIM7_UP: 39
+TIM15_CC: 40
+TIM15_CC: 41
+TIM15_UP: 42
+TIM15_TRG: 43
+TIM15_COM: 44
+TIM16_CC: 45
+TIM16_UP: 46
+TIM16_COM: 47
+TIM17_CC: 48
+TIM17_UP: 49
+TIM17_COM: 50
+SPI1_RX: 51
+SPI1_TX: 52
+SPI2_RX: 53
+SPI2_TX: 54
+SPI3_RX: 55
+SPI3_TX: 56
+SPI4_RX: 57
+SPI4_TX: 58
+SPI5_RX: 59
+SPI5_TX: 60
+SPI6_RX: 61
+SPI6_TX: 62
+SAI1_A: 63
+SAI1_B: 64
+SAI2_A: 65
+SAI2_B: 66
+I2C1_RX: 67
+I2C1_TX: 68
+I2C2_RX: 69
+I2C2_TX: 70
+I2C3_RX: 71
+I2C3_TX: 72
+USART1_RX: 73
+USART1_TX: 74
+USART2_RX: 75
+USART2_TX: 76
+USART3_RX: 77
+USART3_TX: 78
+UART4_RX: 79
+UART4_TX: 80
+UART5_RX: 81
+UART5_TX: 82
+UART7_RX: 83
+UART7_TX: 84
+UART8_RX: 85
+UART8_TX: 86
+CORDIC_READ: 87
+CORDIC_WRITE: 88
+LPTIM1_IC1: 89
+LPTIM1_IC2: 90
+LPTIM1_UE: 91
+LPTIM2_IC1: 92
+LPTIM2_IC2: 93
+LPTIM2_UE: 94
+SPDIFRX_DAT: 95
+SPDIFRX_CTRL: 96
+ADF1_FLT0: 97
+UCPD_TX: 98
+UCPD_RX: 99
+PSSI: 100
+LPUART1_RX: 101
+LPUART1_TX: 102
+LPTIM3_IC1: 103
+LPTIM3_IC2: 104
+LPTIM3_UE: 105
+I3C1_RX: 106
+I3C1_TX: 107
+I3C1_TC: 108
+I3C1_RS: 109
--- a/data/dmamux/H7RS_HPDMA.yaml
+++ b/data/dmamux/H7RS_HPDMA.yaml
@ -0,0 +1,20 @@
+JPEG_RX: 0
+JPEG_TX: 1
+XSPI1_RX: 2
+XSPI2_RX: 3
+SPI3_RX: 4
+SPI3_TX: 5
+SPI4_RX: 6
+SPI4_TX: 7
+ADC1: 8
+ADC2: 9
+ADF1_FLT0: 10
+UART4_RX: 11
+UART4_TX: 12
+UART5_RX: 13
+UART5_TX: 14
+UART7_RX: 15
+UART7_TX: 16
+LPTIM2_IC1: 17
+LPTIM2_IC2: 18
+LPTIM2_UE: 19
--- a/data/registers/cryp_v4.yaml
+++ b/data/registers/cryp_v4.yaml
@ -0,0 +1,215 @@
+block/CRYP:
+  description: Cryptographic processor.
+  items:
+  - name: CR
+    description: control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: status register.
+    byte_offset: 4
+    access: Read
+    fieldset: SR
+  - name: DIN
+    description: data input register.
+    byte_offset: 8
+  - name: DOUT
+    description: data output register.
+    byte_offset: 12
+    access: Read
+  - name: DMACR
+    description: DMA control register.
+    byte_offset: 16
+    fieldset: DMACR
+  - name: IMSCR
+    description: interrupt mask set/clear register.
+    byte_offset: 20
+    fieldset: IMSCR
+  - name: RISR
+    description: raw interrupt status register.
+    byte_offset: 24
+    access: Read
+    fieldset: RISR
+  - name: MISR
+    description: masked interrupt status register.
+    byte_offset: 28
+    access: Read
+    fieldset: MISR
+  - name: KEY
+    description: Cluster KEY%s, containing K?LR, K?RR.
+    array:
+      len: 4
+      stride: 8
+    byte_offset: 32
+    block: KEY
+  - name: INIT
+    description: Cluster INIT%s, containing IV?LR, IV?RR.
+    array:
+      len: 2
+      stride: 8
+    byte_offset: 64
+    block: INIT
+  - name: CSGCMCCMR
+    description: context swap register.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 80
+  - name: CSGCMR
+    description: context swap register.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 112
+block/INIT:
+  description: Cluster INIT%s, containing IV?LR, IV?RR.
+  items:
+  - name: IVLR
+    description: initialization vector registers.
+    byte_offset: 0
+  - name: IVRR
+    description: initialization vector registers.
+    byte_offset: 4
+block/KEY:
+  description: Cluster KEY%s, containing K?LR, K?RR.
+  items:
+  - name: KLR
+    description: key registers.
+    byte_offset: 0
+    access: Write
+  - name: KRR
+    description: key registers.
+    byte_offset: 4
+    access: Write
+fieldset/CR:
+  description: control register.
+  fields:
+  - name: ALGODIR
+    description: Algorithm direction.
+    bit_offset: 2
+    bit_size: 1
+  - name: ALGOMODE0
+    description: Algorithm mode.
+    bit_offset: 3
+    bit_size: 3
+  - name: DATATYPE
+    description: Data type selection.
+    bit_offset: 6
+    bit_size: 2
+  - name: KEYSIZE
+    description: Key size selection (AES mode only).
+    bit_offset: 8
+    bit_size: 2
+  - name: FFLUSH
+    description: FIFO flush.
+    bit_offset: 14
+    bit_size: 1
+  - name: CRYPEN
+    description: Cryptographic processor enable.
+    bit_offset: 15
+    bit_size: 1
+  - name: GCM_CCMPH
+    description: GCM_CCMPH.
+    bit_offset: 16
+    bit_size: 2
+  - name: ALGOMODE3
+    description: ALGOMODE.
+    bit_offset: 19
+    bit_size: 1
+  - name: NPBLB
+    description: Number of Padding Bytes in Last Block of payload.
+    bit_offset: 20
+    bit_size: 4
+  - name: KMOD
+    description: 'Key mode selection This bitfield defines how the CRYP key can be used by the application. KEYSIZE must be correctly initialized when setting KMOD[1:0] different from zero. Others: Reserved Attempts to write the bitfield are ignored when BUSY is set.'
+    bit_offset: 24
+    bit_size: 2
+    enum: KMOD
+  - name: IPRST
+    description: CRYP peripheral software reset Setting the bit resets the CRYP peripheral, putting all registers to their default values, except the IPRST bit itself. This bit must be kept cleared while writing any configuration registers.
+    bit_offset: 31
+    bit_size: 1
+fieldset/DMACR:
+  description: DMA control register.
+  fields:
+  - name: DIEN
+    description: DMA input enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: DOEN
+    description: DMA output enable.
+    bit_offset: 1
+    bit_size: 1
+fieldset/IMSCR:
+  description: interrupt mask set/clear register.
+  fields:
+  - name: INIM
+    description: Input FIFO service interrupt mask.
+    bit_offset: 0
+    bit_size: 1
+  - name: OUTIM
+    description: Output FIFO service interrupt mask.
+    bit_offset: 1
+    bit_size: 1
+fieldset/MISR:
+  description: masked interrupt status register.
+  fields:
+  - name: INMIS
+    description: Input FIFO service masked interrupt status.
+    bit_offset: 0
+    bit_size: 1
+  - name: OUTMIS
+    description: Output FIFO service masked interrupt status.
+    bit_offset: 1
+    bit_size: 1
+fieldset/RISR:
+  description: raw interrupt status register.
+  fields:
+  - name: INRIS
+    description: Input FIFO service raw interrupt status.
+    bit_offset: 0
+    bit_size: 1
+  - name: OUTRIS
+    description: Output FIFO service raw interrupt status.
+    bit_offset: 1
+    bit_size: 1
+fieldset/SR:
+  description: status register.
+  fields:
+  - name: IFEM
+    description: Input FIFO empty.
+    bit_offset: 0
+    bit_size: 1
+  - name: IFNF
+    description: Input FIFO not full.
+    bit_offset: 1
+    bit_size: 1
+  - name: OFNE
+    description: Output FIFO not empty.
+    bit_offset: 2
+    bit_size: 1
+  - name: OFFU
+    description: Output FIFO full.
+    bit_offset: 3
+    bit_size: 1
+  - name: BUSY
+    description: Busy bit.
+    bit_offset: 4
+    bit_size: 1
+  - name: KERF
+    description: 'Key error flag This read-only bit is set by hardware when key information failed to load into key registers. KERF is triggered upon any of the following errors: CRYP_KxR/LR register write does not respect the correct order (refer to Section 60.4.16: CRYP key registers for details). CRYP fails to load the key shared by SAES peripheral (KMOD = 0x2). KERF must be cleared by the application software, otherwise KEYVALID cannot be set. It can be done through IPRST bit of CRYP_CR, or when a correct key writing sequence starts.'
+    bit_offset: 6
+    bit_size: 1
+  - name: KEYVALID
+    description: 'Key valid flag This read-only bit is set by hardware when the key of size defined by KEYSIZE is loaded in CRYP_KxR/LR key registers. The CRYPEN bit can only be set when KEYVALID is set. In normal mode when KMOD[1:0] is at zero, the key must be written in the key registers in the correct sequence, otherwise the KERF flag is set and KEYVALID remains cleared. When KMOD[1:0] is different from zero, the BUSY flag is automatically set by CRYP. When the key is loaded successfully, BUSY is cleared and KEYVALID set. Upon an error, KERF is set, BUSY cleared and KEYVALID remains cleared. If set, KERF must be cleared, otherwise KEYVALID cannot be set. For further information on key loading, refer to Section 60.4.16: CRYP key registers.'
+    bit_offset: 7
+    bit_size: 1
+enum/KMOD:
+  bit_size: 2
+  variants:
+  - name: Normal
+    description: Normal-key mode. Key registers are freely usable.
+    value: 0
+  - name: Shared
+    description: Shared-key mode. If shared-key mode is properly initialized in SAES peripheral, the CRYP peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in CRYP key registers when BUSY bit is cleared and KEYVALID is set in the CRYP_SR register. Key error flag KERF is set otherwise in the CRYP_SR register.
+    value: 2
--- a/data/registers/flash_h7rs.yaml
+++ b/data/registers/flash_h7rs.yaml
@ -0,0 +1,882 @@
+block/FLASH:
+  description: Embedded Flash memory.
+  items:
+  - name: ACR
+    description: Access control register.
+    byte_offset: 0
+    fieldset: ACR
+  - name: KEYR
+    description: FLASH control key register.
+    byte_offset: 4
+    fieldset: KEYR
+  - name: CR
+    description: FLASH control register.
+    byte_offset: 16
+    fieldset: CR
+  - name: SR
+    description: FLASH status register.
+    byte_offset: 20
+    fieldset: SR
+  - name: FCR
+    description: FLASH status register.
+    byte_offset: 24
+    fieldset: FCR
+  - name: IER
+    description: FLASH interrupt enable register.
+    byte_offset: 32
+    fieldset: IER
+  - name: ISR
+    description: FLASH interrupt status register.
+    byte_offset: 36
+    fieldset: ISR
+  - name: ICR
+    description: FLASH interrupt clear register.
+    byte_offset: 40
+    fieldset: ICR
+  - name: CRCCR
+    description: FLASH CRC control register.
+    byte_offset: 48
+    fieldset: CRCCR
+  - name: CRCSADDR
+    description: FLASH CRC start address register.
+    byte_offset: 52
+    fieldset: CRCSADDR
+  - name: CRCEADDR
+    description: FLASH CRC end address register.
+    byte_offset: 56
+    fieldset: CRCEADDR
+  - name: CRCDATAR
+    description: FLASH CRC data register.
+    byte_offset: 60
+    fieldset: CRCDATAR
+  - name: ECCSFADDR
+    description: FLASH ECC single error fail address.
+    byte_offset: 64
+    fieldset: ECCSFADDR
+  - name: ECCDFADDR
+    description: FLASH ECC double error fail address.
+    byte_offset: 68
+    fieldset: ECCDFADDR
+  - name: OPTKEYR
+    description: FLASH options key register.
+    byte_offset: 256
+    fieldset: OPTKEYR
+  - name: OPTCR
+    description: FLASH options control register.
+    byte_offset: 260
+    fieldset: OPTCR
+  - name: OPTISR
+    description: FLASH options interrupt status register.
+    byte_offset: 264
+    fieldset: OPTISR
+  - name: OPTICR
+    description: FLASH options interrupt clear register.
+    byte_offset: 268
+    fieldset: OPTICR
+  - name: OBKCR
+    description: FLASH option byte key control register.
+    byte_offset: 272
+    fieldset: OBKCR
+  - name: OBKDR
+    description: FLASH option bytes key data register 0.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 280
+  - name: NVSR
+    description: FLASH non-volatile status register.
+    byte_offset: 512
+    fieldset: NVSR
+  - name: NVSRP
+    description: FLASH security status register programming.
+    byte_offset: 516
+    fieldset: NVSRP
+  - name: ROTSR
+    description: FLASH RoT status register.
+    byte_offset: 520
+    fieldset: ROTSR
+  - name: ROTSRP
+    description: FLASH RoT status register programming.
+    byte_offset: 524
+    fieldset: ROTSRP
+  - name: OTPLSR
+    description: FLASH OTP lock status register.
+    byte_offset: 528
+    fieldset: OTPLSR
+  - name: OTPLSRP
+    description: FLASH OTP lock status register programming.
+    byte_offset: 532
+    fieldset: OTPLSRP
+  - name: WRPSR
+    description: FLASH write protection status register.
+    byte_offset: 536
+    fieldset: WRPSR
+  - name: WRPSRP
+    description: FLASH write protection status register programming.
+    byte_offset: 540
+    fieldset: WRPSRP
+  - name: HDPSR
+    description: FLASH hide protection status register.
+    byte_offset: 560
+    fieldset: HDPSR
+  - name: HDPSRP
+    description: FLASH hide protection status register programming.
+    byte_offset: 564
+    fieldset: HDPSRP
+  - name: EPOCHSR
+    description: FLASH epoch status register.
+    byte_offset: 592
+    fieldset: EPOCHSR
+  - name: EPOCHSRP
+    description: FLASH RoT status register programming.
+    byte_offset: 596
+    fieldset: EPOCHSRP
+  - name: OBW1SR
+    description: FLASH option byte word 1 status register.
+    byte_offset: 608
+    fieldset: OBW1SR
+  - name: OBW1SRP
+    description: FLASH option byte word 1 status register programming.
+    byte_offset: 612
+    fieldset: OBW1SRP
+  - name: OBW2SR
+    description: FLASH option byte word 2 status register.
+    byte_offset: 616
+    fieldset: OBW2SR
+  - name: OBW2SRP
+    description: FLASH option byte word 2 status register programming.
+    byte_offset: 620
+    fieldset: OBW2SRP
+fieldset/ACR:
+  description: Access control register.
+  fields:
+  - name: LATENCY
+    description: 'Read latency These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions. Please refer to Table 27 for details. ... Note: Embedded Flash does not verify that the configuration is correct.'
+    bit_offset: 0
+    bit_size: 4
+  - name: WRHIGHFREQ
+    description: 'Flash signal delay These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to Table 27 for details. Note: Embedded Flash does not verify that the configuration is correct.'
+    bit_offset: 4
+    bit_size: 2
+fieldset/CR:
+  description: FLASH control register.
+  fields:
+  - name: LOCK
+    description: Configuration lock bit When this bit is set write to all other bits in this register, and to FLASH_IER register, are ignored. Clearing this bit requires the correct write sequence to FLASH_KEYR register (see this register for details). If a wrong sequence is executed, or if the unlock sequence is performed twice, this bit remains locked until the next system reset. During the write access to set LOCK bit from 0 to 1, it is possible to change the other bits of this register.
+    bit_offset: 0
+    bit_size: 1
+  - name: PG
+    description: Internal buffer control bit Setting this bit enables internal buffer for write operations. This allows preparing program operations even if a sector or bank erase is ongoing. When PG is cleared, the internal buffer is disabled for write operations, and all the data stored in the buffer but not sent to the operation queue are lost.
+    bit_offset: 1
+    bit_size: 1
+  - name: SER
+    description: 'Sector erase request Setting this bit requests a sector erase. Write protection error is triggered when a sector erase is required on at least one protected sector. BER has a higher priority than SER: if both bits are set, the embedded Flash memory executes a bank erase.'
+    bit_offset: 2
+    bit_size: 1
+  - name: BER
+    description: 'Bank erase request Setting this bit requests a bank erase operation (user Flash memory only). Write protection error is triggered when a bank erase is required and some sectors are protected. BER has a higher priority than SER: if both are set, the embedded Flash memory executes a bank erase.'
+    bit_offset: 3
+    bit_size: 1
+  - name: FW
+    description: 'Force write This bit forces a write operation even if the write buffer is not full. In this case all bits not written are set by hardware. The embedded Flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it will lead to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively).'
+    bit_offset: 4
+    bit_size: 1
+  - name: START
+    description: Erase start control bit This bit is used to start a sector erase or a bank erase operation. The embedded Flash memory resets START when the corresponding operation has been acknowledged. The user application cannot access any embedded Flash memory register until the operation is acknowledged.
+    bit_offset: 5
+    bit_size: 1
+  - name: SSN
+    description: Sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). ...
+    bit_offset: 6
+    bit_size: 2
+  - name: PG_OTP
+    description: Program Enable for OTP Area Set this bit to enable write operations to OTP area.
+    bit_offset: 16
+    bit_size: 1
+  - name: CRC_EN
+    description: CRC enable Setting this bit enables the CRC calculation. CRC_EN does not start CRC calculation but enables CRC configuration through FLASH_CRCCR register. When CRC calculation is performed it can be disabled by clearing CRC_EN bit. Doing so sets CRCDATA to 0x0, clears CRC configuration and resets the content of FLASH_CRCDATAR register.
+    bit_offset: 17
+    bit_size: 1
+  - name: ALL_BANKS
+    description: All banks select bit When this bit is set the erase is done on all Flash Memory sectors. ALL_BANKS is used only if a bank erase is required (BER=1). In all others operations, this control bit is ignored.
+    bit_offset: 24
+    bit_size: 1
+fieldset/CRCCR:
+  description: FLASH CRC control register.
+  fields:
+  - name: CRC_SECT
+    description: CRC sector number CRC_SECT is used to select one user Flash sectors to be added to the list of sectors on which the CRC is calculated. The CRC can be computed either between two addresses (using registers FLASH_CRCSADDR and FLASH_CRCEADDR) or on a list of sectors using this register. If this latter option is selected, it is possible to add a sector to the list of sectors by programming the sector number in CRC_SECT and then setting ADD_SECT bit. The list of sectors can be erased either by setting CLEAN_SECT bit or by disabling the CRC computation. ...
+    bit_offset: 0
+    bit_size: 2
+  - name: CRC_BY_SECT
+    description: CRC sector mode select bit When this bit is set the CRC calculation is performed at sector level, on the sectors present in the list of sectors. To add a sector to this list, use ADD_SECT and CRC_SECT bits. To clean the list, use CLEAN_SECT bit. When CRC_BY_SECT is cleared the CRC calculation is performed on all addresses defined between start and end addresses defined in FLASH_CRCSADDR and FLASH_CRCEADDR registers.
+    bit_offset: 9
+    bit_size: 1
+  - name: ADD_SECT
+    description: CRC sector select bit When this bit is set the sector whose number is written in CRC_SECT is added to the list of sectors on which the CRC is calculated.
+    bit_offset: 10
+    bit_size: 1
+  - name: CLEAN_SECT
+    description: CRC sector list clear bit When this bit is set the list of sectors on which the CRC is calculated is cleared.
+    bit_offset: 11
+    bit_size: 1
+  - name: START_CRC
+    description: CRC start bit START_CRC bit triggers a CRC calculation using the current configuration. No CRC calculation can launched when an option byte change operation is ongoing because all read accesses to embedded Flash memory registers are put on hold until the option byte change operation has completed. This bit is cleared when CRC computation starts.
+    bit_offset: 16
+    bit_size: 1
+  - name: CLEAN_CRC
+    description: CRC clear bit Setting CLEAN_CRC to 1 clears the current CRC result stored in the FLASH_CRCDATAR register.
+    bit_offset: 17
+    bit_size: 1
+  - name: CRC_BURST
+    description: CRC burst size CRC_BURST bits set the size of the bursts that are generated by the CRC calculation unit. A Flash word is 128-bit.
+    bit_offset: 20
+    bit_size: 2
+    enum: CRC_BURST
+  - name: ALL_SECT
+    description: All sectors selection When this bit is set all the sectors in user Flash are added to list of sectors on which the CRC shall be calculated. This bit is cleared when CRC computation starts.
+    bit_offset: 24
+    bit_size: 1
+fieldset/CRCDATAR:
+  description: FLASH CRC data register.
+  fields:
+  - name: CRC_DATA
+    description: CRC result This bitfield contains the result of the last CRC calculation. The value is valid only when CRC calculation completed (CRCENDF is set in FLASH_ISR register). CRC_DATA is cleared when CRC_EN is cleared in FLASH_CR register (CRC disabled), or when CLEAN_CRC bit is set in FLASH_CRCCR register.
+    bit_offset: 0
+    bit_size: 32
+fieldset/CRCEADDR:
+  description: FLASH CRC end address register.
+  fields:
+  - name: CRC_END_ADDR
+    description: CRC end address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the Flash word starting the last burst of the CRC calculation. The burst size is defined in CRC_BURST of FLASH_CRCCR register. The least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank.
+    bit_offset: 6
+    bit_size: 11
+fieldset/CRCSADDR:
+  description: FLASH CRC start address register.
+  fields:
+  - name: CRC_START_ADDR
+    description: CRC start address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the first Flash word to use for the CRC calculation, done burst by burst. CRC computation starts at an address aligned to the burst size defined in CRC_BURST of FLASH_CRCCR register. Hence least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank.
+    bit_offset: 6
+    bit_size: 11
+fieldset/ECCDFADDR:
+  description: FLASH ECC double error fail address.
+  fields:
+  - name: DED_FADD
+    description: ECC double error detection fail address When a double ECC detection occurs during a read operation, the DED_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when the DBECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC double error detection error is saved in this register.
+    bit_offset: 0
+    bit_size: 32
+fieldset/ECCSFADDR:
+  description: FLASH ECC single error fail address.
+  fields:
+  - name: SEC_FADD
+    description: ECC single error correction fail address When a single ECC error correction occurs during a read operation, the SEC_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when SNECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC single error correction error is saved in this register.
+    bit_offset: 0
+    bit_size: 32
+fieldset/EPOCHSR:
+  description: FLASH epoch status register.
+  fields:
+  - name: EPOCH
+    description: Epoch This value is distributed by hardware to the SAES peripheral.
+    bit_offset: 0
+    bit_size: 24
+fieldset/EPOCHSRP:
+  description: FLASH RoT status register programming.
+  fields:
+  - name: EPOCH
+    description: Epoch programming Write to change corresponding bits in FLASH_EPOCHSR register.
+    bit_offset: 0
+    bit_size: 24
+fieldset/FCR:
+  description: FLASH status register.
+  fields:
+  - name: RCHECKF
+    description: Root code check flag clear Set this bit to clear RCHECKF bit in FLASH_SR.
+    bit_offset: 25
+    bit_size: 1
+fieldset/HDPSR:
+  description: FLASH hide protection status register.
+  fields:
+  - name: HDP_AREA_START
+    description: Hide protection user Flash area start This option sets the start address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END<HDP_AREA_START no sectors are protected.
+    bit_offset: 0
+    bit_size: 9
+  - name: HDP_AREA_END
+    description: Hide protection user Flash area end This option sets the end address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END<HDP_AREA_START no sectors are protected.
+    bit_offset: 16
+    bit_size: 9
+fieldset/HDPSRP:
+  description: FLASH hide protection status register programming.
+  fields:
+  - name: HDP_AREA_START
+    description: Hide protection user Flash area start programming Write to change corresponding option byte bits in FLASH_HDPSR. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END<HDP_AREA_START no sectors are protected.
+    bit_offset: 0
+    bit_size: 9
+  - name: HDP_AREA_END
+    description: Hide protection user Flash area end programming Write to change corresponding option byte bits in FLASH_HDPSR. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END<HDP_AREA_START no sectors are protected.
+    bit_offset: 16
+    bit_size: 9
+fieldset/ICR:
+  description: FLASH interrupt clear register.
+  fields:
+  - name: EOPF
+    description: End-of-program flag clear Setting this bit clears EOPF flag in FLASH_ISR register.
+    bit_offset: 16
+    bit_size: 1
+  - name: WRPERRF
+    description: Write protection error flag clear Setting this bit clears WRPERRF flag in FLASH_ISR register.
+    bit_offset: 17
+    bit_size: 1
+  - name: PGSERRF
+    description: Programming sequence error flag clear Setting this bit clears PGSERRF flag in FLASH_ISR register.
+    bit_offset: 18
+    bit_size: 1
+  - name: STRBERRF
+    description: Strobe error flag clear Setting this bit clears STRBERRF flag in FLASH_ISR register.
+    bit_offset: 19
+    bit_size: 1
+  - name: OBLERRF
+    description: Option byte loading error flag clear Setting this bit clears OBLERRF flag in FLASH_ISR register.
+    bit_offset: 20
+    bit_size: 1
+  - name: INCERRF
+    description: Inconsistency error flag clear Setting this bit clears INCERRF flag in FLASH_ISR register.
+    bit_offset: 21
+    bit_size: 1
+  - name: RDSERRF
+    description: Read security error flag clear Setting this bit clears RDSERRF flag in FLASH_ISR register.
+    bit_offset: 24
+    bit_size: 1
+  - name: SNECCERRF
+    description: ECC single error flag clear Setting this bit clears SNECCERRF flag in FLASH_ISR register. If the DBECCERRF flag of FLASH_ISR register is also cleared, FLASH_ECCFAR register is reset to zero as well.
+    bit_offset: 25
+    bit_size: 1
+  - name: DBECCERRF
+    description: ECC double error flag clear Setting this bit clears DBECCERRF flag in FLASH_ISR register. If the SNECCERRF flag of FLASH_ISR register is also cleared, FLASH_ECCFAR register is reset to zero as well.
+    bit_offset: 26
+    bit_size: 1
+  - name: CRCENDF
+    description: CRC end flag clear Setting this bit clears CRCENDF flag in FLASH_ISR register.
+    bit_offset: 27
+    bit_size: 1
+  - name: CRCRDERRF
+    description: CRC error flag clear Setting this bit clears CRCRDERRF flag in FLASH_ISR register.
+    bit_offset: 28
+    bit_size: 1
+fieldset/IER:
+  description: FLASH interrupt enable register.
+  fields:
+  - name: EOPIE
+    description: End-of-program interrupt control bit.
+    bit_offset: 16
+    bit_size: 1
+  - name: WRPERRIE
+    description: Write protection error interrupt enable bit.
+    bit_offset: 17
+    bit_size: 1
+  - name: PGSERRIE
+    description: Programming sequence error interrupt enable bit.
+    bit_offset: 18
+    bit_size: 1
+  - name: STRBERRIE
+    description: Strobe error interrupt enable bit.
+    bit_offset: 19
+    bit_size: 1
+  - name: OBLERRIE
+    description: Option byte loading error interrupt enable bit.
+    bit_offset: 20
+    bit_size: 1
+  - name: INCERRIE
+    description: Inconsistency error interrupt enable bit.
+    bit_offset: 21
+    bit_size: 1
+  - name: RDSERRIE
+    description: Read security error interrupt enable bit.
+    bit_offset: 24
+    bit_size: 1
+  - name: SNECCERRIE
+    description: ECC single correction error interrupt enable bit.
+    bit_offset: 25
+    bit_size: 1
+  - name: DBECCERRIE
+    description: ECC double detection error interrupt enable bit.
+    bit_offset: 26
+    bit_size: 1
+  - name: CRCENDIE
+    description: CRC end of calculation interrupt enable bit.
+    bit_offset: 27
+    bit_size: 1
+  - name: CRCRDERRIE
+    description: CRC read error interrupt enable bit.
+    bit_offset: 28
+    bit_size: 1
+fieldset/ISR:
+  description: FLASH interrupt status register.
+  fields:
+  - name: EOPF
+    description: End-of-program flag This bit is set when a programming operation completes. An interrupt is generated if the EOPIE is set. It is not necessary to reset EOPF before starting a new operation. Setting EOPF bit in FLASH_ICR register clears this bit.
+    bit_offset: 16
+    bit_size: 1
+  - name: WRPERRF
+    description: Write protection error flag This bit is set when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set. Setting WRPERRF bit in FLASH_ICR register clears this bit.
+    bit_offset: 17
+    bit_size: 1
+  - name: PGSERRF
+    description: Programming sequence error flag This bit is set when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set. Setting PGSERRF bit in FLASH_ICR register clears this bit.
+    bit_offset: 18
+    bit_size: 1
+  - name: STRBERRF
+    description: Strobe error flag This bit is set when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set. Setting STRBERRF bit in FLASH_ICR register clears this bit.
+    bit_offset: 19
+    bit_size: 1
+  - name: OBLERRF
+    description: Option byte loading error flag This bit is set when an error is found during the option byte loading sequence. An interrupt is generated if OBLERRIE is set. Setting OBLERRF bit in the FLASH_ICR register clears this bit.
+    bit_offset: 20
+    bit_size: 1
+  - name: INCERRF
+    description: Inconsistency error flag This bit is set when a inconsistency error occurs. An interrupt is generated if INCERRIE is set. Setting INCERRF bit in the FLASH_ICR register clears this bit.
+    bit_offset: 21
+    bit_size: 1
+  - name: RDSERRF
+    description: Read security error flag This bit is set when a read security error occurs (read access to hide protected area with incorrect hide protection level). An interrupt is generated if RDSERRIE is set. Setting RDSERRF bit in FLASH_ICR register clears this bit.
+    bit_offset: 24
+    bit_size: 1
+  - name: SNECCERRF
+    description: ECC single error flag This bit is set when an ECC single correction error occurs during a read operation. An interrupt is generated if SNECCERRIE is set. Setting SNECCERRF bit in FLASH_ICR register clears this bit.
+    bit_offset: 25
+    bit_size: 1
+  - name: DBECCERRF
+    description: ECC double error flag This bit is set when an ECC double detection error occurs during a read operation. An interrupt is generated if DBECCERRIE is set. Setting DBECCERRF bit in FLASH_ICR register clears this bit.
+    bit_offset: 26
+    bit_size: 1
+  - name: CRCENDF
+    description: CRC end flag This bit is set when the CRC computation has completed. An interrupt is generated if CRCENDIE is set. It is not necessary to reset CRCEND before restarting CRC computation. Setting CRCENDF bit in FLASH_ICR register clears this bit.
+    bit_offset: 27
+    bit_size: 1
+  - name: CRCRDERRF
+    description: CRC read error flag This bit is set when a word is found read protected during a CRC operation. An interrupt is generated if CRCRDIE is set. Setting CRCRDERRF bit in FLASH_ICR register clears this bit. This flag is valid only when CRCEND bit is set.
+    bit_offset: 28
+    bit_size: 1
+fieldset/KEYR:
+  description: FLASH control key register.
+  fields:
+  - name: CUKEY
+    description: 'Control unlock key Following values must be written to FLASH_KEYR consecutively to unlock FLASH_CR register: 1st key = 0x4567 0123 2nd key = 0xCDEF 89AB Reads to this register returns zero. If above sequence is wrong or performed twice, the FLASH_CR register is locked until the next system reset, and access to it generates a bus error.'
+    bit_offset: 0
+    bit_size: 32
+fieldset/NVSR:
+  description: FLASH non-volatile status register.
+  fields:
+  - name: NVSTATE
+    description: 'Non-volatile state others: invalid configuration.'
+    bit_offset: 0
+    bit_size: 8
+    enum: NVSR_NVSTATE
+fieldset/NVSRP:
+  description: FLASH security status register programming.
+  fields:
+  - name: NVSTATE
+    description: 'Non-volatile state programming Write to change corresponding bits in FLASH_NVSR register: Actual option byte change from close to open is triggered only after memory clear hardware process is confirmed. When NVSTATE=0xB4 (resp. 0x51) writing any other value than 0x51 (resp. 0xB4) triggers an option byte change error (OPTERRF).'
+    bit_offset: 0
+    bit_size: 8
+    enum: NVSRP_NVSTATE
+fieldset/OBKCR:
+  description: FLASH option byte key control register.
+  fields:
+  - name: OBKINDEX
+    description: Option byte key index This bitfield represents the index of the option byte key in a given hide protection level. Reading keys with index lower that 8, the value is not be available in OBKDRx registers. It is instead sent directly to SAES peripheral. All others keys can be read using OBKDRx registers. Up to 32 keys can be provisioned per hide protection level (0, 1 or 2), provided there is enough space left in the Flash to store them.
+    bit_offset: 0
+    bit_size: 5
+  - name: NEXTKL
+    description: 'Next key level 10 or 11: reserved.'
+    bit_offset: 8
+    bit_size: 2
+    enum: NEXTKL
+  - name: OBKSIZE
+    description: Option byte key size Application must use this bitfield to specify how many bits must be used for the new key. Embedded Flash ignores OBKSIZE during read of option keys because size is stored with the key.
+    bit_offset: 10
+    bit_size: 2
+    enum: OBKSIZE
+  - name: KEYPROG
+    description: Key program This bit must be set to write option byte keys (keys are read otherwise).
+    bit_offset: 14
+    bit_size: 1
+  - name: KEYSTART
+    description: Key option start This bit is used to start the option byte key operation defined by the PROG bit. The embedded Flash memory resets START when the corresponding operation has been acknowledged.
+    bit_offset: 15
+    bit_size: 1
+fieldset/OBW1SR:
+  description: FLASH option byte word 1 status register.
+  fields:
+  - name: BOR_LEV
+    description: Brownout level These bits reflects the power level that generates a system reset.
+    bit_offset: 2
+    bit_size: 2
+    enum: BOR_LEV
+  - name: IWDG_HW
+    description: Independent watchdog HW Control.
+    bit_offset: 4
+    bit_size: 1
+  - name: NRST_STOP
+    description: Reset on stop mode.
+    bit_offset: 6
+    bit_size: 1
+  - name: NRST_STBY
+    description: Reset on standby mode.
+    bit_offset: 7
+    bit_size: 1
+  - name: OCTO1_HSLV
+    description: XSPIM_P1 High-Speed at Low-Voltage.
+    bit_offset: 8
+    bit_size: 1
+  - name: OCTO2_HSLV
+    description: XSPIM_P2 High-Speed at Low-Voltage.
+    bit_offset: 9
+    bit_size: 1
+  - name: IWDG_FZ_STOP
+    description: IWDG stop mode freeze When set the independent watchdog IWDG is frozen in system Stop mode.
+    bit_offset: 17
+    bit_size: 1
+  - name: IWDG_FZ_SDBY
+    description: IWDG standby mode freeze When set the independent watchdog IWDG is frozen in system Standby mode.
+    bit_offset: 18
+    bit_size: 1
+  - name: PERSO_OK
+    description: Personalization OK This bit is set on STMicroelectronics production line.
+    bit_offset: 28
+    bit_size: 1
+  - name: VDDIO_HSLV
+    description: I/O High-Speed at Low-Voltage This bit indicates that the product operates below 2.5 V.
+    bit_offset: 29
+    bit_size: 1
+fieldset/OBW1SRP:
+  description: FLASH option byte word 1 status register programming.
+  fields:
+  - name: BOR_LEV
+    description: Brownout level Write to change corresponding bits in FLASH_OBW1SR register.
+    bit_offset: 2
+    bit_size: 2
+  - name: IWDG_HW
+    description: Independent watchdog HW Control Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 4
+    bit_size: 1
+  - name: NRST_STOP
+    description: Reset on stop mode programming Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 6
+    bit_size: 1
+  - name: NRST_STBY
+    description: Reset on standby mode programming Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 7
+    bit_size: 1
+  - name: OCTO1_HSLV
+    description: XSPIM_P1 High-Speed at Low-Voltage Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 8
+    bit_size: 1
+  - name: OCTO2_HSLV
+    description: XSPIM_P2 High-Speed at Low-Voltage programming Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 9
+    bit_size: 1
+  - name: IWDG_FZ_STOP
+    description: IWDG stop mode freeze Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 17
+    bit_size: 1
+  - name: IWDG_FZ_SDBY
+    description: IWDG standby mode freeze programming Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 18
+    bit_size: 1
+  - name: VDDIO_HSLV
+    description: I/O High-Speed at Low-Voltage programming Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 29
+    bit_size: 1
+fieldset/OBW2SR:
+  description: FLASH option byte word 2 status register.
+  fields:
+  - name: ITCM_AXI_SHARE
+    description: ITCM SRAM configuration.
+    bit_offset: 0
+    bit_size: 3
+  - name: DTCM_AXI_SHARE
+    description: DTCM SRAM configuration.
+    bit_offset: 4
+    bit_size: 3
+  - name: ECC_ON_SRAM
+    description: ECC on SRAM.
+    bit_offset: 8
+    bit_size: 1
+  - name: I2C_NI3C
+    description: I2C Not I3C.
+    bit_offset: 9
+    bit_size: 1
+fieldset/OBW2SRP:
+  description: FLASH option byte word 2 status register programming.
+  fields:
+  - name: ITCM_AXI_SHARE
+    description: 'ITCM AXI share programming Write to change corresponding bits in FLASH_OBW2SR register. Bit 2 should be kept to 0: ITCM_AXI_SHARE: = 000 or 011: ITCM 64 Kbytes ITCM_AXI_SHARE = 001: ITCM 128 Kbytes ITCM_AXI_SHARE = 010: ITCM 192 Kbytes.'
+    bit_offset: 0
+    bit_size: 3
+  - name: DTCM_AXI_SHARE
+    description: 'DTCM AXI share programming Write to change corresponding bits in the FLASH_OBW2SR register. Bit 2 should be kept to 0: DTCM_AXI_SHARE = 000 or 011: DTCM 64 Kbytes DTCM_AXI_SHARE = 001: DTCM 128 Kbytes DTCM_AXI_SHARE = 010: DTCM 192 Kbytes.'
+    bit_offset: 4
+    bit_size: 3
+  - name: ECC_ON_SRAM
+    description: ECC on SRAM programming Write to change corresponding bit in FLASH_OBW2SR register.
+    bit_offset: 8
+    bit_size: 1
+  - name: I2C_NI3C
+    description: I2C Not I3C Write to change corresponding bit in FLASH_OBW2SR register.
+    bit_offset: 9
+    bit_size: 1
+fieldset/OPTCR:
+  description: FLASH options control register.
+  fields:
+  - name: OPTLOCK
+    description: Options lock When this bit is set write to all other bits in this register, and write to OTP words, option bytes and option bytes keys control registers, are ignored. Clearing this bit requires the correct write sequence to FLASH_OPTKEYR register (see this register for details). If a wrong sequence is executed, or the unlock sequence is performed twice, this bit remains locked until next system reset. During the write access to set LOCK bit from 0 to 1, it is possible to change the other bits of this register.
+    bit_offset: 0
+    bit_size: 1
+  - name: PG_OPT
+    description: Program options.
+    bit_offset: 1
+    bit_size: 1
+  - name: KVEIE
+    description: Key valid error interrupt enable bit This bit controls if an interrupt has to be generated when KVEF is set in FLASH_OPTISR.
+    bit_offset: 27
+    bit_size: 1
+  - name: KTEIE
+    description: Key transfer error interrupt enable bit This bit controls if an interrupt has to be generated when KTEF is set in FLASH_OPTISR.
+    bit_offset: 28
+    bit_size: 1
+  - name: OPTERRIE
+    description: Option byte change error interrupt enable bit This bit controls if an interrupt has to be generated when an error occurs during an option byte change.
+    bit_offset: 30
+    bit_size: 1
+fieldset/OPTICR:
+  description: FLASH options interrupt clear register.
+  fields:
+  - name: KVEF
+    description: key valid error flag Set this bit to clear KVEF flag in FLASH_OPTISR register.
+    bit_offset: 27
+    bit_size: 1
+  - name: KTEF
+    description: key transfer error flag Set this bit to clear KTEF flag in FLASH_OPTISR register.
+    bit_offset: 28
+    bit_size: 1
+  - name: OPTERRF
+    description: Option byte change error flag Set this bit to clear OPTERRF flag in FLASH_OPTISR register.
+    bit_offset: 30
+    bit_size: 1
+fieldset/OPTISR:
+  description: FLASH options interrupt status register.
+  fields:
+  - name: KVEF
+    description: 'Key valid error flag This bit is set when loading an unknown or corrupted option byte key. More specifically: Embedded Flash did not find an option byte key that corresponds to the given OBKINDEX[4:0] and the requested HDPL (optionally modified by NEXTKL[1:0]). It can happen for example when requested key has not being provisioned. A double error detection was found when loading the requested option byte key. In this case, if this key is provisioned again the error should disappear. When KVEF is set write to START bit in FLASH_OBKCR is ignored. An interrupt is generated when this flag is raised if the KVEIE bit of FLASH_OPTCR register is set. Setting KVEF bit of register FLASH_OPTICR clears this bit.'
+    bit_offset: 27
+    bit_size: 1
+  - name: KTEF
+    description: Key transfer error flag This bit is set when embedded Flash signals an error to the SAES peripheral. It happens when the key size (128-bit or 256-bit) is not matching between embedded Flash OBKSIZE[1:0] and KEYSIZE bit in SAES_CR register. It also happen when an ECC dual error detection occurred while embedded Flash loaded an option byte key for the SAES peripheral. When KTEF is set write to START bit in FLASH_OBKCR is ignored. An interrupt is generated when this flag is raised if the KTEIE bit of FLASH_OPTCR register is set. Setting KTEF bit of register FLASH_OPTICR clears this bit.
+    bit_offset: 28
+    bit_size: 1
+  - name: OPTERRF
+    description: Option byte change error flag When OPTERRF is set, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTERRIE bit of FLASH_OPTCR register is set. Setting OPTERRF of register FLASH_OPTICR clears this bit.
+    bit_offset: 30
+    bit_size: 1
+fieldset/OPTKEYR:
+  description: FLASH options key register.
+  fields:
+  - name: OCUKEY
+    description: 'Options configuration unlock key Following values must be written to FLASH_OPTKEYR consecutively to unlock FLASH_OPTCR register: 1st key = 0x0819 2A3B 2nd key = 0x4C5D 6E7F Reads to this register returns zero. If above sequence is performed twice locks up the corresponding register/bit until the next system reset, and generates a bus error.'
+    bit_offset: 0
+    bit_size: 32
+fieldset/OTPLSR:
+  description: FLASH OTP lock status register.
+  fields:
+  - name: OTPL
+    description: OTP lock n Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. OTPL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and can no longer be programmed. OTPL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked and can still be modified.
+    bit_offset: 0
+    bit_size: 16
+fieldset/OTPLSRP:
+  description: FLASH OTP lock status register programming.
+  fields:
+  - name: OTPL
+    description: OTP lock n programming Write to change corresponding option byte bit in FLASH_OTPLSR. OTPL bits can be only be set, not cleared.
+    bit_offset: 0
+    bit_size: 16
+fieldset/ROTSR:
+  description: FLASH RoT status register.
+  fields:
+  - name: OEM_PROVD
+    description: 'OEM provisioned device Any other value: device is not provisioned by the OEM.'
+    bit_offset: 0
+    bit_size: 8
+    enum: OEM_PROVD
+  - name: DBG_AUTH
+    description: 'Debug authentication method Any other value: no authentication method selected (NotSet).'
+    bit_offset: 8
+    bit_size: 8
+    enum: DBG_AUTH
+  - name: IROT_SELECT
+    description: 'iRoT selection This option is ignored for STM32H7R devices (OEM iRoT is always selected). Any other value: OEM iRoT is selected at boot.'
+    bit_offset: 24
+    bit_size: 8
+    enum: IROT_SELECT
+fieldset/ROTSRP:
+  description: FLASH RoT status register programming.
+  fields:
+  - name: OEM_PROVD
+    description: OEM provisioned device Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 1.
+    bit_offset: 0
+    bit_size: 8
+  - name: DBG_AUTH
+    description: Debug authentication method programming Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 0.
+    bit_offset: 8
+    bit_size: 8
+  - name: IROT_SELECT
+    description: iRoT selection This option is ignored for STM32H7R devices. Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 1 and if NVSTATE is not 0xB4 (OPEN).
+    bit_offset: 24
+    bit_size: 8
+fieldset/SR:
+  description: FLASH status register.
+  fields:
+  - name: BUSY
+    description: Busy flag This bit is set when an effective write, erase or option byte change operation is ongoing. It is possible to know what type of operation is being executed reading the flags IS_PROGRAM, IS_ERASE and IS_OPTCHANGE. BUSY cannot be cleared by application. It is automatically reset by hardware every time a step in a write, erase or option byte change operation completes. It is not recommended to do software polling on BUSY to know when one operation completed because, depending of operation, more pulses are possible for one only operation. For software polling it is therefore better to use QW flag or to check the EOPF flag.
+    bit_offset: 0
+    bit_size: 1
+  - name: WBNE
+    description: 'Write buffer not empty flag This bit is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_CR the embedded Flash memory detects an error that involves data loss the application software has disabled write operations This bit cannot be forced to 0. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data.'
+    bit_offset: 1
+    bit_size: 1
+  - name: QW
+    description: Wait queue flag This bit is set when a write, erase or option byte change operation is pending in the command queue buffer. It is not possible to know what type of programming operation is present in the queue. This flag is reset by hardware when all write, erase or option byte change operations have been executed and thus removed from the waiting queue(s). This bit cannot be forced to 0. It is reset after a deterministic time if no other operations are requested.
+    bit_offset: 2
+    bit_size: 1
+  - name: CRC_BUSY
+    description: CRC busy flag This bit is set when a CRC calculation is ongoing. This bit cannot be forced to 0. The user must wait until the CRC calculation has completed or disable CRC computation using CRC_EN bit in FLASH_CR register.
+    bit_offset: 3
+    bit_size: 1
+  - name: IS_PROGRAM
+    description: Is a program This bit is set together with BUSY when a program operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_OPTCHANGE, because an program operation can happen during an option change.
+    bit_offset: 4
+    bit_size: 1
+  - name: IS_ERASE
+    description: Is an erase This bit is set together with BUSY when an erase operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_OPTCHANGE, because an erase operation can happen during an option change.
+    bit_offset: 5
+    bit_size: 1
+  - name: IS_OPTCHANGE
+    description: Is an option change This bit is set together with BUSY when an option change operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_PROGRAM or IS_ERASE, because a program or erase step is ongoing during option change.
+    bit_offset: 6
+    bit_size: 1
+  - name: RCHECKF
+    description: Root code check flag This bit returns the status of the root code check performed following the first access to the Flash. This bit is cleared with RCHECKF bit in FLASH_FCR (optional).
+    bit_offset: 25
+    bit_size: 1
+fieldset/WRPSR:
+  description: FLASH write protection status register.
+  fields:
+  - name: WRPS
+    description: Write protection for sector n This bit reflects the write protection status of user Flash sector n.
+    bit_offset: 0
+    bit_size: 8
+fieldset/WRPSRP:
+  description: FLASH write protection status register programming.
+  fields:
+  - name: WRPS
+    description: Write protection for sector n programming Write to change corresponding bit in FLASH_WRPSR.
+    bit_offset: 0
+    bit_size: 8
+enum/BOR_LEV:
+  bit_size: 2
+  variants:
+  - name: Disabled
+    description: BOR OFF, POR/PDR reset threshold level is applied.
+    value: 0
+  - name: Level1
+    description: BOR Level 1, the threshold level is low (around 2.1 V).
+    value: 1
+  - name: Level2
+    description: BOR Level 2, the threshold level is medium (around 2.4 V).
+    value: 2
+  - name: Level3
+    description: BOR Level 3, the threshold level is high (around 2.7 V).
+    value: 3
+enum/CRC_BURST:
+  bit_size: 2
+  variants:
+  - name: Word4
+    description: every burst has a size of 4 Flash words (64 Bytes).
+    value: 0
+  - name: Word16
+    description: every burst has a size of 16 Flash words (256 Bytes).
+    value: 1
+  - name: Word64
+    description: every burst has a size of 64 Flash words (1 Kbytes).
+    value: 2
+  - name: Word256
+    description: every burst has a size of 256 Flash words (4 Kbytes).
+    value: 3
+enum/DBG_AUTH:
+  bit_size: 8
+  variants:
+  - name: ECDSA
+    description: Authentication method using ECDSA signature (NIST P256).
+    value: 81
+  - name: Delegated
+    description: Delegated debug (to OEM iRoT code in user Flash).
+    value: 111
+  - name: Password
+    description: Authentication method using password.
+    value: 138
+  - name: Locked
+    description: Locked device (no debug allowed).
+    value: 180
+enum/IROT_SELECT:
+  bit_size: 8
+  variants:
+  - name: Selected
+    description: ST iRoT is selected at boot.
+    value: 180
+enum/NEXTKL:
+  bit_size: 2
+  variants:
+  - name: Plus0
+    description: OBKINDEX represents the index of the option byte key stored for the hide protection level indicated in SBS_HDPLSR.
+    value: 0
+  - name: Plus1
+    description: OBKINDEX represents the index of the option byte key stored for the hide protection level indicated in SBS_HDPLSR plus one (e.g. if HDPL=1 in SBS_HDPLR the key of level 2 is selected).
+    value: 1
+enum/NVSRP_NVSTATE:
+  bit_size: 8
+  variants:
+  - name: Close
+    description: CLOSE.
+    value: 81
+  - name: Open
+    description: OPEN.
+    value: 180
+enum/NVSR_NVSTATE:
+  bit_size: 8
+  variants:
+  - name: Closed
+    description: CLOSED device.
+    value: 81
+  - name: Open
+    description: OPEN device.
+    value: 180
+enum/OBKSIZE:
+  bit_size: 2
+  variants:
+  - name: Bits32
+    description: Key size is 32 bits.
+    value: 0
+  - name: Bits64
+    description: Key size is 64 bits.
+    value: 1
+  - name: Bits128
+    description: Key size is 128 bits.
+    value: 2
+  - name: Bits256
+    description: Key size is 256 bits.
+    value: 3
+enum/OEM_PROVD:
+  bit_size: 8
+  variants:
+  - name: Provisioned
+    description: Device has been provisioned by the OEM.
+    value: 180
--- a/data/registers/pwr_h7rm0399.yaml
+++ b/data/registers/pwr_h7rm0399.yaml
@ -253,6 +253,7 @@ fieldset/WKUPEPR:
    array:
      len: 6
      stride: 2
+    enum: WKUPPUPD
 fieldset/WKUPFR:
  description: reset only by system reset, not reset by wakeup from Standby mode
  fields:
@ -283,3 +284,15 @@ enum/VOS:
    value: 2
  - name: Scale1
    value: 3
+enum/WKUPPUPD:
+  bit_size: 2
+  variants:
+  - name: NoPull
+    description: No pull-up.
+    value: 0
+  - name: PullUp
+    description: Pull-up.
+    value: 1
+  - name: PullDown
+    description: Pull-down.
+    value: 2
--- a/data/registers/pwr_h7rm0433.yaml
+++ b/data/registers/pwr_h7rm0433.yaml
@ -240,6 +240,7 @@ fieldset/WKUPEPR:
    array:
      len: 6
      stride: 2
+    enum: WKUPPUPD
 fieldset/WKUPFR:
  description: reset only by system reset, not reset by wakeup from Standby mode
  fields:
@ -259,3 +260,15 @@ enum/VOS:
    value: 2
  - name: Scale1
    value: 3
+enum/WKUPPUPD:
+  bit_size: 2
+  variants:
+  - name: NoPull
+    description: No pull-up.
+    value: 0
+  - name: PullUp
+    description: Pull-up.
+    value: 1
+  - name: PullDown
+    description: Pull-down.
+    value: 2
--- a/data/registers/pwr_h7rm0455.yaml
+++ b/data/registers/pwr_h7rm0455.yaml
@ -253,6 +253,7 @@ fieldset/WKUPEPR:
    array:
      len: 6
      stride: 2
+    enum: WKUPPUPD
 fieldset/WKUPFR:
  description: reset only by system reset, not reset by wakeup from Standby mode
  fields:
@ -285,3 +286,15 @@ enum/VOS:
    value: 2
  - name: Scale0
    value: 3
+enum/WKUPPUPD:
+  bit_size: 2
+  variants:
+  - name: NoPull
+    description: No pull-up.
+    value: 0
+  - name: PullUp
+    description: Pull-up.
+    value: 1
+  - name: PullDown
+    description: Pull-down.
+    value: 2
--- a/data/registers/pwr_h7rm0468.yaml
+++ b/data/registers/pwr_h7rm0468.yaml
@ -253,6 +253,7 @@ fieldset/WKUPEPR:
    array:
      len: 6
      stride: 2
+    enum: WKUPPUPD
 fieldset/WKUPFR:
  description: reset only by system reset, not reset by wakeup from Standby mode
  fields:
@ -285,3 +286,15 @@ enum/VOS:
    value: 2
  - name: Scale1
    value: 3
+enum/WKUPPUPD:
+  bit_size: 2
+  variants:
+  - name: NoPull
+    description: No pull-up.
+    value: 0
+  - name: PullUp
+    description: Pull-up.
+    value: 1
+  - name: PullDown
+    description: Pull-down.
+    value: 2
--- a/data/registers/pwr_h7rs.yaml
+++ b/data/registers/pwr_h7rs.yaml
@ -0,0 +1,643 @@
+block/PWR:
+  description: Power control.
+  items:
+  - name: CR1
+    description: PWR control register 1.
+    byte_offset: 0
+    fieldset: CR1
+  - name: SR1
+    description: PWR control status register 1.
+    byte_offset: 4
+    fieldset: SR1
+  - name: CSR1
+    description: PWR control status register 1.
+    byte_offset: 8
+    fieldset: CSR1
+  - name: CSR2
+    description: PWR control register 2.
+    byte_offset: 12
+    fieldset: CSR2
+  - name: CSR3
+    description: PWR CPU control register 3.
+    byte_offset: 16
+    fieldset: CSR3
+  - name: CSR4
+    description: PWR control status register 4.
+    byte_offset: 20
+    fieldset: CSR4
+  - name: WKUPCR
+    description: PWR wakeup clear register.
+    byte_offset: 32
+    fieldset: WKUPCR
+  - name: WKUPFR
+    description: PWR wakeup flag register.
+    byte_offset: 36
+    fieldset: WKUPFR
+  - name: WKUPEPR
+    description: PWR wakeup enable and polarity register.
+    byte_offset: 40
+    fieldset: WKUPEPR
+  - name: UCPDR
+    description: PWR USB Type-C and Power Delivery register.
+    byte_offset: 44
+    fieldset: UCPDR
+  - name: APCR
+    description: PWR apply pull configuration register.
+    byte_offset: 48
+    fieldset: APCR
+  - name: PUCRN
+    description: PWR port N pull-up control register.
+    byte_offset: 52
+    fieldset: PUCRN
+  - name: PDCRN
+    description: PWR port N pull-down control register.
+    byte_offset: 56
+    fieldset: PDCRN
+  - name: PUCRO
+    description: PWR port O pull-up control register.
+    byte_offset: 60
+    fieldset: PUCRO
+  - name: PDCRO
+    description: PWR port O pull-down control register.
+    byte_offset: 64
+    fieldset: PDCRO
+  - name: PDCRP
+    description: PWR port P pull-down control register.
+    byte_offset: 68
+    fieldset: PDCRP
+  - name: PDR1
+    description: PWR debug register 1.
+    byte_offset: 80
+    fieldset: PDR1
+fieldset/APCR:
+  description: PWR apply pull configuration register.
+  fields:
+  - name: APC
+    description: Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx, PDCRx registers are applied in Standby mode even after wakeup until APC bit is reset to 0. When this bit is cleared, the I/O pull-up or pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx and PDCRx registers are not applied in Standby mode and IO becomes Hi-Z.
+    bit_offset: 0
+    bit_size: 1
+  - name: PN7_PUPD
+    description: Port N bit 7 pull-up/down configuration When this bit is set, a weak pull-up or pull-down resistor is applied on PN7 following inverse logic applied on PN6. If the PUN6 bit in PWR_PUCRN register is set and APC bit is set the week pull-down is applied on PN7. If the PDN6 bit in PWR_PDCRN register is set and APC bit is set the week pull-up is applied on PN7.
+    bit_offset: 16
+    bit_size: 1
+  - name: PO5_PUPD
+    description: Port O bit 5 pull-up/down configuration When this bit is set, a weak pull-up or pull down resistor is applied on PO5 following inverse logic applied on PO4. If the PUO4 bit in PWR_PUCRO register is set and APC bit is set the week pull-down is applied on PO5. If the PDO4 bit in PWR_PDCRO register is set and APC bit is set the week pull-up is applied on PO5..
+    bit_offset: 17
+    bit_size: 1
+  - name: I3CPB6_PU
+    description: Port PB6 I3C pull-up bit When I3C is used on PB6, when set, this bit activates the pull-up on I3C1_SCL (PB6) in standby mode.
+    bit_offset: 28
+    bit_size: 1
+  - name: I3CPB7_PU
+    description: Port PB7 I3C pull-up bit When I3C is used on PB7, when set, this bit activates the pull-up on I3C1_SDA (PB7) in standby mode.
+    bit_offset: 29
+    bit_size: 1
+  - name: I3CPB8_PU
+    description: Port PB8 I3C pull-up bit When I3C is used on PB8, when set, this bit activates the pull-up on I3C1_SCL (PB8) in standby mode.
+    bit_offset: 30
+    bit_size: 1
+  - name: I3CPB9_PU
+    description: Port PB9 I3C pull-up bit When I3C is used on PB9, when set, this bit activates the pull-up on I3C1_SDA (PB9) in standby mode.
+    bit_offset: 31
+    bit_size: 1
+fieldset/CR1:
+  description: PWR control register 1.
+  fields:
+  - name: SVOS
+    description: System Stop mode voltage scaling selection.
+    bit_offset: 0
+    bit_size: 1
+    enum: SVOS
+  - name: PVDE
+    description: Programmable voltage detector enable.
+    bit_offset: 4
+    bit_size: 1
+  - name: PLS
+    description: 'Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details.'
+    bit_offset: 5
+    bit_size: 3
+    enum: PLS
+  - name: DBP
+    description: Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in the PWR_CSR1 register, are protected against parasitic write access. This bit must be set to enable write access to these registers.
+    bit_offset: 8
+    bit_size: 1
+  - name: FLPS
+    description: Flash low-power mode in Stop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when device is in Stop mode. consumption).
+    bit_offset: 9
+    bit_size: 1
+  - name: RLPSN
+    description: RAM low power mode disable in STOP. When set the RAMs will not enter to low power mode when the system enters to STOP.
+    bit_offset: 10
+    bit_size: 1
+    enum: RLPSN
+  - name: BOOSTE
+    description: analog switch VBoost control This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits.
+    bit_offset: 11
+    bit_size: 1
+  - name: AVDREADY
+    description: analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected VDDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_CSR1 register) after setting the AVDEN bit and selecting the supply level to be monitored (ALS bits).
+    bit_offset: 12
+    bit_size: 1
+  - name: AVDEN
+    description: Peripheral voltage monitor on VDDA enable.
+    bit_offset: 13
+    bit_size: 1
+  - name: ALS
+    description: 'Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details.'
+    bit_offset: 14
+    bit_size: 2
+    enum: ALS
+fieldset/CSR1:
+  description: PWR control status register 1.
+  fields:
+  - name: BREN
+    description: Backup regulator enable When set, the backup regulator (used to maintain the backup RAM content in Standby and V<sub>BAT</sub> modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and V<sub>BAT</sub> modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and V<sub>BAT</sub> modes.
+    bit_offset: 0
+    bit_size: 1
+  - name: MONEN
+    description: 'V<sub>BAT</sub> and temperature monitoring enable When set, the V<sub>BAT</sub> supply and temperature monitoring is enabled. Note: V<sub>BAT</sub> and temperature monitoring are only available when the backup regulator is enabled (BREN bit set to 1).'
+    bit_offset: 4
+    bit_size: 1
+  - name: BRRDY
+    description: Backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready.
+    bit_offset: 16
+    bit_size: 1
+  - name: VBATL
+    description: V<sub>BAT</sub> level monitoring versus low threshold.
+    bit_offset: 20
+    bit_size: 1
+  - name: VBATH
+    description: V<sub>BAT</sub> level monitoring versus high threshold.
+    bit_offset: 21
+    bit_size: 1
+  - name: TEMPL
+    description: Temperature level monitoring versus low threshold.
+    bit_offset: 22
+    bit_size: 1
+  - name: TEMPH
+    description: Temperature level monitoring versus high threshold.
+    bit_offset: 23
+    bit_size: 1
+fieldset/CSR2:
+  description: PWR control register 2.
+  fields:
+  - name: BYPASS
+    description: 'Power management unit bypass Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41.'
+    bit_offset: 0
+    bit_size: 1
+  - name: LDOEN
+    description: 'Low drop-out regulator enable Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41.'
+    bit_offset: 1
+    bit_size: 1
+  - name: SDEN
+    description: 'SMPS step-down converter enable Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41.'
+    bit_offset: 2
+    bit_size: 1
+  - name: SDEXTHP
+    description: 'SMPS external power delivery selection Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41.'
+    bit_offset: 3
+    bit_size: 1
+  - name: SDLEVEL
+    description: SMPS step-down converter voltage output for LDO or external supply This bit is used when both the LDO and SMPS step-down converter are enabled with SDEN and LDOEN enabled or when SMPSEXTHP is enabled. In this case SDHILEVEL has to be set to 1 to confirm the regulator settings.
+    bit_offset: 4
+    bit_size: 1
+    enum: SDLEVEL
+  - name: VBE
+    description: VBAT charging enable.
+    bit_offset: 8
+    bit_size: 1
+  - name: VBRS
+    description: VBAT charging resistor selection.
+    bit_offset: 9
+    bit_size: 1
+    enum: VBRS
+  - name: XSPICAP1
+    description: XSPI port 1 capacitor control bits see the product datasheet for more details.
+    bit_offset: 10
+    bit_size: 2
+    enum: XSPICAP
+  - name: XSPICAP2
+    description: XSPI port 2 capacitor control bits see the product datasheet for more details.
+    bit_offset: 12
+    bit_size: 2
+    enum: XSPICAP
+  - name: EN_XSPIM1
+    description: 'EN_XSPIM1: this bit allow the SW to enable the XSPI interface. The XSPIM_P1 supply must be stable prior to setting this bit.'
+    bit_offset: 14
+    bit_size: 1
+  - name: EN_XSPIM2
+    description: 'EN_XSPIM2: this bit allows the SW to enable the XSPI interface, when available. The XSPIM_P2 supply must be stable prior to setting this bit. It should also be set when FMC is used.'
+    bit_offset: 15
+    bit_size: 1
+  - name: SDEXTRDY
+    description: SMPS step-down converter external supply ready This bit is set by hardware to indicate that the external supply from the SMPS step-down converter is ready.
+    bit_offset: 16
+    bit_size: 1
+  - name: USB33DEN
+    description: VDD33_USB voltage level detector enable.
+    bit_offset: 24
+    bit_size: 1
+  - name: USBREGEN
+    description: USB regulator enable.
+    bit_offset: 25
+    bit_size: 1
+  - name: USB33RDY
+    description: USB supply ready.
+    bit_offset: 26
+    bit_size: 1
+  - name: USBHSREGEN
+    description: USB HS regulator enable.
+    bit_offset: 27
+    bit_size: 1
+enum/SDLEVEL:
+  bit_size: 1
+  variants:
+  - name: Reset
+    value: 0
+  - name: V1_8
+    value: 1
+fieldset/CSR3:
+  description: PWR CPU control register 3.
+  fields:
+  - name: PDDS
+    description: Power Down Deepsleep. This bit allows CPU to define the Deepsleep mode.
+    bit_offset: 0
+    bit_size: 1
+    enum: PDDS
+  - name: CSSF
+    description: Clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware.
+    bit_offset: 1
+    bit_size: 1
+  - name: STOPF
+    description: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU CSSF bit.
+    bit_offset: 8
+    bit_size: 1
+  - name: SBF
+    description: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU CSSF bit.
+    bit_offset: 9
+    bit_size: 1
+fieldset/CSR4:
+  description: PWR control status register 4.
+  fields:
+  - name: VOS
+    description: 'Voltage scaling selection according to performance These bits control the V<sub>CORE</sub> voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling must be changed before increasing the system frequency. When decreasing performance, the system frequency must first be decreased before changing the voltage scaling. Note: Refer to Section Electrical characteristics of the product datasheet for more details.'
+    bit_offset: 0
+    bit_size: 1
+    enum: VOS
+  - name: VOSRDY
+    description: VOS Ready bit.
+    bit_offset: 1
+    bit_size: 1
+fieldset/PDCRN:
+  description: PWR port N pull-down control register.
+  fields:
+  - name: PDN0
+    description: Port N pull-down bit 0 When set activates the pull-down on PN0 when the APC bit is set in PWR_APCR.
+    bit_offset: 0
+    bit_size: 1
+  - name: PDN1
+    description: Port N pull-down bit 1 When set activates the pull-down on PN1 when the APC bit is set in PWR_APCR.
+    bit_offset: 1
+    bit_size: 1
+  - name: PDN2N5
+    description: Port N PN2 to PN5 pull-down activation When set, four pull-down resistors are activated on PN2 to PN5 when the APC bit is set in PWR_APCR.
+    bit_offset: 2
+    bit_size: 1
+  - name: PDN6
+    description: Port N pull-down bit 6 When set activates the pull-down on PN6 when the APC bit is set in PWR_APCR.
+    bit_offset: 6
+    bit_size: 1
+  - name: PDN8N11
+    description: Port N - PN8 to PN11 pull-down activation When set, four pull-down resistors are activated on PN8 to PN11 when the APC bit is set in PWR_APCR.
+    bit_offset: 8
+    bit_size: 1
+  - name: PDN12
+    description: Port N pull-down bit 12 When set activates the pull-down on PN12 when the APC bit is set in PWR_APCR.
+    bit_offset: 12
+    bit_size: 1
+fieldset/PDCRO:
+  description: PWR port O pull-down control register.
+  fields:
+  - name: PDO0
+    description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR.
+    bit_offset: 0
+    bit_size: 1
+  - name: PDO1
+    description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR.
+    bit_offset: 1
+    bit_size: 1
+  - name: PDO2
+    description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR.
+    bit_offset: 2
+    bit_size: 1
+  - name: PDO3
+    description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR.
+    bit_offset: 3
+    bit_size: 1
+  - name: PDO4
+    description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR.
+    bit_offset: 4
+    bit_size: 1
+fieldset/PDCRP:
+  description: PWR port P pull-down control register.
+  fields:
+  - name: PDP0P3
+    description: Port P0-P3 pull-down activation When set, four pull-down resistors are activated on P0 to P3 when the APC bit is set in PWR_APCR.
+    bit_offset: 0
+    bit_size: 1
+  - name: PDP4P7
+    description: Port P4-P7 pull-down activation When set, four pull-down resitors are activated on P4 to P7 when the APC bit is set in PWR_APCR.
+    bit_offset: 4
+    bit_size: 1
+  - name: PDP8P11
+    description: Port P8-P11 pull-down activation When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR.
+    bit_offset: 8
+    bit_size: 1
+  - name: PDP12P15
+    description: Port P12-P15 pull-down activation When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR.
+    bit_offset: 12
+    bit_size: 1
+fieldset/PDR1:
+  description: PWR debug register 1.
+  fields:
+  - name: UNLOCKED
+    description: Debug Register Unlocked.
+    bit_offset: 0
+    bit_size: 1
+    enum: UNLOCKED
+  - name: SDFPWMEN
+    description: Step down converter force PWM mode.
+    bit_offset: 3
+    bit_size: 1
+  - name: SYNC_ADC
+    description: (Non-User bit).
+    bit_offset: 16
+    bit_size: 1
+    enum: SYNC_ADC
+fieldset/PUCRN:
+  description: PWR port N pull-up control register.
+  fields:
+  - name: PUN1
+    description: Port N pull-up bit 1 When set, each bit activates the pull-up on PN1 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD1 bit is also set.
+    bit_offset: 1
+    bit_size: 1
+  - name: PUN6
+    description: Port N pull-up bit 6 When set activates the pull-up on PN6 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PDN6 bit is also set.
+    bit_offset: 6
+    bit_size: 1
+  - name: PUN12
+    description: Port N pull-up bit 12 When set, each bit activates the pull-up on PN12 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD12 bit is also set.
+    bit_offset: 12
+    bit_size: 1
+fieldset/PUCRO:
+  description: PWR port O pull-up control register.
+  fields:
+  - name: PUO0
+    description: (n = 1 to 0) Port O pull-up bits When set, each bit activates the pull-up on POy when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits in PWR_PDCRO is also set.
+    bit_offset: 0
+    bit_size: 1
+  - name: PUO1
+    description: (n = 1 to 0) Port O pull-up bits When set, each bit activates the pull-up on POy when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits in PWR_PDCRO is also set.
+    bit_offset: 1
+    bit_size: 1
+  - name: PUO4
+    description: Port O pull-up bit 4 When set activates the pull-up on PO4 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits PDO4 in PWR_PDCRO is also set.
+    bit_offset: 4
+    bit_size: 1
+fieldset/SR1:
+  description: PWR control status register 1.
+  fields:
+  - name: ACTVOS
+    description: VOS currently applied for V<sub>CORE</sub> voltage scaling selection. These bit reflect the last VOS value applied to the PMU.
+    bit_offset: 0
+    bit_size: 1
+  - name: ACTVOSRDY
+    description: Voltage levels ready bit for currently used ACTVOS and SDHILEVEL This bit is set to 1 by hardware when the voltage regulator and the SMPS step-down converter are both disabled and Bypass mode is selected in PWR control register 2 (PWR_CSR2).
+    bit_offset: 1
+    bit_size: 1
+  - name: PVDO
+    description: 'Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. PLS[2:0] bits. bits. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.'
+    bit_offset: 4
+    bit_size: 1
+    enum: PVDO
+  - name: AVDO
+    description: 'Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.'
+    bit_offset: 13
+    bit_size: 1
+    enum: AVDO
+fieldset/UCPDR:
+  description: PWR USB Type-C and Power Delivery register.
+  fields:
+  - name: UCPD_DBDIS
+    description: UCPD dead battery disable.
+    bit_offset: 0
+    bit_size: 1
+  - name: UCPD_STBY
+    description: UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers.
+    bit_offset: 1
+    bit_size: 1
+fieldset/WKUPCR:
+  description: PWR wakeup clear register.
+  fields:
+  - name: WKUPC
+    description: Clear Wakeup pin flag for WKUP1 These bits are always read as 0.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+fieldset/WKUPEPR:
+  description: PWR wakeup enable and polarity register.
+  fields:
+  - name: WKUPEN
+    description: 'Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge.'
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+  - name: WKUPP
+    description: Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin.
+    bit_offset: 8
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+    enum: WKUPP
+  - name: WKUPPUPD
+    description: Wakeup pin pull configuration
+    bit_offset: 16
+    bit_size: 2
+    array:
+      len: 4
+      stride: 2
+    enum: WKUPPUPD
+fieldset/WKUPFR:
+  description: PWR wakeup flag register.
+  fields:
+  - name: WKUPF
+    description: Wakeup pin WKUP flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC1 bit in the PWR wakeup clear register (PWR_WKUPCR).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+enum/ALS:
+  bit_size: 2
+  variants:
+  - name: Level1
+    description: AVD level 1.
+    value: 0
+  - name: Level2
+    description: AVD level 2.
+    value: 1
+  - name: Level3
+    description: AVD level 3.
+    value: 2
+  - name: Level4
+    description: AVD level 4.
+    value: 3
+enum/AVDO:
+  bit_size: 1
+  variants:
+  - name: AboveOrEqual
+    description: VDDA is equal or higher than the AVD threshold selected with the ALS[1:0] bits.
+    value: 0
+  - name: Below
+    description: VDDA is lower than the AVD threshold selected with the ALS[1:0] bits.
+    value: 1
+enum/PDDS:
+  bit_size: 1
+  variants:
+  - name: Stop
+    description: Stop mode when device enters Deepsleep.
+    value: 0
+  - name: Standby
+    description: Standby mode when device enters Deepsleep.
+    value: 1
+enum/PLS:
+  bit_size: 3
+  variants:
+  - name: Level1
+    description: PVD level 1.
+    value: 0
+  - name: Level2
+    description: PVD level 2.
+    value: 1
+  - name: Level3
+    description: PVD level 3.
+    value: 2
+  - name: Level4
+    description: PVD level 4.
+    value: 3
+  - name: Level5
+    description: PVD level 5.
+    value: 4
+  - name: Level6
+    description: PVD level 6.
+    value: 5
+  - name: Level7
+    description: PVD level 7.
+    value: 6
+  - name: External
+    description: External voltage level on PVD_IN pin, compared to internal VREFINT level.
+    value: 7
+enum/PVDO:
+  bit_size: 1
+  variants:
+  - name: AboveOrEqual
+    description: VDD or PVD_IN voltage is equal or higher than the PVD threshold selected through the.
+    value: 0
+  - name: Below
+    description: VDD or PVD_IN voltage is lower than the PVD threshold selected through the PLS[2:0].
+    value: 1
+enum/RLPSN:
+  bit_size: 1
+  variants:
+  - name: LowPower
+    description: RAM enters to low power mode when system enters to STOP.
+    value: 0
+  - name: Normal
+    description: RAM remains in normal mode when system enters to STOP.
+    value: 1
+enum/SVOS:
+  bit_size: 1
+  variants:
+  - name: Low
+    description: SVOS Low.
+    value: 0
+  - name: High
+    description: SVOS High (default).
+    value: 1
+enum/SYNC_ADC:
+  bit_size: 1
+  variants:
+  - name: FreeRunning
+    description: SD_Converter clock free running.
+    value: 0
+  - name: Synchronized
+    description: SD_Converter clock synchronised to ADC.
+    value: 1
+enum/UNLOCKED:
+  bit_size: 1
+  variants:
+  - name: Locked
+    description: 'accessed locked: key was not written and after each register write access.'
+    value: 0
+  - name: Unlocked
+    description: after key 0xCAFECAFE was written in this register.
+    value: 1
+enum/VBRS:
+  bit_size: 1
+  variants:
+  - name: Ohm5k
+    description: Charge VBAT through a 5 k resistor.
+    value: 0
+  - name: Ohm1_5k
+    description: Charge VBAT through a 1.5 k resistor.
+    value: 1
+enum/VOS:
+  bit_size: 1
+  variants:
+  - name: Low
+    description: VOS Low level (default).
+    value: 0
+  - name: High
+    description: VOS High level.
+    value: 1
+enum/WKUPP:
+  bit_size: 1
+  variants:
+  - name: High
+    description: Detection on high level (rising edge).
+    value: 0
+  - name: Low
+    description: Detection on low level (falling edge).
+    value: 1
+enum/WKUPPUPD:
+  bit_size: 2
+  variants:
+  - name: NoPull
+    description: No pull-up.
+    value: 0
+  - name: PullUp
+    description: Pull-up.
+    value: 1
+  - name: PullDown
+    description: Pull-down.
+    value: 2
+enum/XSPICAP:
+  bit_size: 2
+  variants:
+  - name: Disabled
+    description: 'XSPI Capacitor OFF (default) note: to confirm with analog design.'
+    value: 0
+  - name: OneThird
+    description: XSPI Capacitor set to 1/3.
+    value: 1
+  - name: TwoThirds
+    description: XSPI Capacitor set to 2/3.
+    value: 2
+  - name: Full
+    description: XSPI Capacitor set to full capacitance.
+    value: 3
--- a/data/registers/rcc_h5.yaml
+++ b/data/registers/rcc_h5.yaml
@ -328,7 +328,7 @@ fieldset/AHB1RSTR:
    bit_offset: 17
    bit_size: 1
  - name: ETHRST
-    description: "ETHRST block reset\r Set and reset by software"
+    description: "ETH1 block reset\r Set and reset by software"
    bit_offset: 19
    bit_size: 1
  - name: TZSC1RST
--- a/data/registers/rcc_h7.yaml
+++ b/data/registers/rcc_h7.yaml
@ -312,15 +312,15 @@ fieldset/AHB1ENR:
    description: ART Clock Enable
    bit_offset: 14
    bit_size: 1
-  - name: ETH1MACEN
+  - name: ETHEN
    description: Ethernet MAC bus interface Clock Enable
    bit_offset: 15
    bit_size: 1
-  - name: ETH1TXEN
+  - name: ETHTXEN
    description: Ethernet Transmission Clock Enable
    bit_offset: 16
    bit_size: 1
-  - name: ETH1RXEN
+  - name: ETHRXEN
    description: Ethernet Reception Clock Enable
    bit_offset: 17
    bit_size: 1
@ -359,15 +359,15 @@ fieldset/AHB1LPENR:
    description: ART Clock Enable During CSleep Mode
    bit_offset: 14
    bit_size: 1
-  - name: ETH1MACLPEN
+  - name: ETHLPEN
    description: Ethernet MAC bus interface Clock Enable During CSleep Mode
    bit_offset: 15
    bit_size: 1
-  - name: ETH1TXLPEN
+  - name: ETHTXLPEN
    description: Ethernet Transmission Clock Enable During CSleep Mode
    bit_offset: 16
    bit_size: 1
-  - name: ETH1RXLPEN
+  - name: ETHRXLPEN
    description: Ethernet Reception Clock Enable During CSleep Mode
    bit_offset: 17
    bit_size: 1
@ -406,8 +406,8 @@ fieldset/AHB1RSTR:
    description: ART block reset
    bit_offset: 14
    bit_size: 1
-  - name: ETH1MACRST
-    description: ETH1MAC block reset
+  - name: ETHRST
+    description: ETH block reset
    bit_offset: 15
    bit_size: 1
  - name: USB_OTG_HSRST
@ -1802,15 +1802,15 @@ fieldset/C1_AHB1ENR:
    description: ART Clock Enable
    bit_offset: 14
    bit_size: 1
-  - name: ETH1MACEN
+  - name: ETHEN
    description: Ethernet MAC bus interface Clock Enable
    bit_offset: 15
    bit_size: 1
-  - name: ETH1TXEN
+  - name: ETHTXEN
    description: Ethernet Transmission Clock Enable
    bit_offset: 16
    bit_size: 1
-  - name: ETH1RXEN
+  - name: ETHRXEN
    description: Ethernet Reception Clock Enable
    bit_offset: 17
    bit_size: 1
@ -1849,15 +1849,15 @@ fieldset/C1_AHB1LPENR:
    description: ART Clock Enable During CSleep Mode
    bit_offset: 14
    bit_size: 1
-  - name: ETH1MACLPEN
+  - name: ETHLPEN
    description: Ethernet MAC bus interface Clock Enable During CSleep Mode
    bit_offset: 15
    bit_size: 1
-  - name: ETH1TXLPEN
+  - name: ETHTXLPEN
    description: Ethernet Transmission Clock Enable During CSleep Mode
    bit_offset: 16
    bit_size: 1
-  - name: ETH1RXLPEN
+  - name: ETHRXLPEN
    description: Ethernet Reception Clock Enable During CSleep Mode
    bit_offset: 17
    bit_size: 1
--- a/data/registers/rcc_h7ab.yaml
+++ b/data/registers/rcc_h7ab.yaml
@ -232,15 +232,15 @@ fieldset/AHB1ENR:
    description: ART Clock Enable
    bit_offset: 14
    bit_size: 1
-  - name: ETH1MACEN
+  - name: ETHEN
    description: Ethernet MAC bus interface Clock Enable
    bit_offset: 15
    bit_size: 1
-  - name: ETH1TXEN
+  - name: ETHTXEN
    description: Ethernet Transmission Clock Enable
    bit_offset: 16
    bit_size: 1
-  - name: ETH1RXEN
+  - name: ETHRXEN
    description: Ethernet Reception Clock Enable
    bit_offset: 17
    bit_size: 1
@ -279,15 +279,15 @@ fieldset/AHB1LPENR:
    description: ART Clock Enable During CSleep Mode
    bit_offset: 14
    bit_size: 1
-  - name: ETH1MACLPEN
+  - name: ETHLPEN
    description: Ethernet MAC bus interface Clock Enable During CSleep Mode
    bit_offset: 15
    bit_size: 1
-  - name: ETH1TXLPEN
+  - name: ETHTXLPEN
    description: Ethernet Transmission Clock Enable During CSleep Mode
    bit_offset: 16
    bit_size: 1
-  - name: ETH1RXLPEN
+  - name: ETHRXLPEN
    description: Ethernet Reception Clock Enable During CSleep Mode
    bit_offset: 17
    bit_size: 1
@ -326,8 +326,8 @@ fieldset/AHB1RSTR:
    description: ART block reset
    bit_offset: 14
    bit_size: 1
-  - name: ETH1MACRST
-    description: ETH1MAC block reset
+  - name: ETHRST
+    description: ETH block reset
    bit_offset: 15
    bit_size: 1
  - name: USB_OTG_HSRST
--- a/data/registers/rcc_h7rm0433.yaml
+++ b/data/registers/rcc_h7rm0433.yaml
@ -312,15 +312,15 @@ fieldset/AHB1ENR:
    description: ART Clock Enable
    bit_offset: 14
    bit_size: 1
-  - name: ETH1MACEN
+  - name: ETHEN
    description: Ethernet MAC bus interface Clock Enable
    bit_offset: 15
    bit_size: 1
-  - name: ETH1TXEN
+  - name: ETHTXEN
    description: Ethernet Transmission Clock Enable
    bit_offset: 16
    bit_size: 1
-  - name: ETH1RXEN
+  - name: ETHRXEN
    description: Ethernet Reception Clock Enable
    bit_offset: 17
    bit_size: 1
@ -359,15 +359,15 @@ fieldset/AHB1LPENR:
    description: ART Clock Enable During CSleep Mode
    bit_offset: 14
    bit_size: 1
-  - name: ETH1MACLPEN
+  - name: ETHLPEN
    description: Ethernet MAC bus interface Clock Enable During CSleep Mode
    bit_offset: 15
    bit_size: 1
-  - name: ETH1TXLPEN
+  - name: ETHTXLPEN
    description: Ethernet Transmission Clock Enable During CSleep Mode
    bit_offset: 16
    bit_size: 1
-  - name: ETH1RXLPEN
+  - name: ETHRXLPEN
    description: Ethernet Reception Clock Enable During CSleep Mode
    bit_offset: 17
    bit_size: 1
@ -406,8 +406,8 @@ fieldset/AHB1RSTR:
    description: ART block reset
    bit_offset: 14
    bit_size: 1
-  - name: ETH1MACRST
-    description: ETH1MAC block reset
+  - name: ETHRST
+    description: ETH block reset
    bit_offset: 15
    bit_size: 1
  - name: USB_OTG_HSRST
@ -1790,15 +1790,15 @@ fieldset/C1_AHB1ENR:
    description: ART Clock Enable
    bit_offset: 14
    bit_size: 1
-  - name: ETH1MACEN
+  - name: ETHEN
    description: Ethernet MAC bus interface Clock Enable
    bit_offset: 15
    bit_size: 1
-  - name: ETH1TXEN
+  - name: ETHTXEN
    description: Ethernet Transmission Clock Enable
    bit_offset: 16
    bit_size: 1
-  - name: ETH1RXEN
+  - name: ETHRXEN
    description: Ethernet Reception Clock Enable
    bit_offset: 17
    bit_size: 1
@ -1837,15 +1837,15 @@ fieldset/C1_AHB1LPENR:
    description: ART Clock Enable During CSleep Mode
    bit_offset: 14
    bit_size: 1
-  - name: ETH1MACLPEN
+  - name: ETHLPEN
    description: Ethernet MAC bus interface Clock Enable During CSleep Mode
    bit_offset: 15
    bit_size: 1
-  - name: ETH1TXLPEN
+  - name: ETHTXLPEN
    description: Ethernet Transmission Clock Enable During CSleep Mode
    bit_offset: 16
    bit_size: 1
-  - name: ETH1RXLPEN
+  - name: ETHRXLPEN
    description: Ethernet Reception Clock Enable During CSleep Mode
    bit_offset: 17
    bit_size: 1
--- a/data/registers/rcc_h7rs.yaml
+++ b/data/registers/rcc_h7rs.yaml
--- a/data/registers/syscfg_h5.yaml
+++ b/data/registers/syscfg_h5.yaml
@ -365,13 +365,13 @@ enum/EPOCH_SEL:
 enum/ETH_SEL_PHY:
  bit_size: 3
  variants:
-  - name: B_0x0
+  - name: MII_GMII
    description: GMII or MII
    value: 0
-  - name: B_0x1
+  - name: ReservedRGMII
    description: reserved (RGMII)
    value: 1
-  - name: B_0x4
+  - name: RMII
    description: RMII
    value: 4
 enum/HDPL:
--- a/data/registers/syscfg_h7.yaml
+++ b/data/registers/syscfg_h7.yaml
@ -139,7 +139,7 @@ fieldset/CCCSR:
    description: Code selection
    bit_offset: 1
    bit_size: 1
-  - name: READY
+  - name: RDY
    description: Compensation cell ready flag
    bit_offset: 8
    bit_size: 1
@ -218,10 +218,11 @@ fieldset/PMCR:
    description: Analog switch supply voltage selection
    bit_offset: 9
    bit_size: 1
-  - name: EPIS
-    description: Ethernet PHY Interface Selection
+  - name: ETH_SEL_PHY
+    description: Ethernet PHY interface selection.
    bit_offset: 21
    bit_size: 3
+    enum: ETH_SEL_PHY
  - name: PA0SO
    description: PA0 Switch Open
    bit_offset: 24
@ -413,6 +414,15 @@ fieldset/UR9:
    description: Protected area start address for bank 2
    bit_offset: 16
    bit_size: 12
+enum/ETH_SEL_PHY:
+  bit_size: 3
+  variants:
+  - name: MII_GMII
+    description: GMII or MII
+    value: 0
+  - name: RMII
+    description: RMII
+    value: 4
 enum/ITCM_AXI_RAM_SIZE:
  bit_size: 2
  variants:
--- a/data/registers/syscfg_h7od.yaml
+++ b/data/registers/syscfg_h7od.yaml
@ -138,7 +138,7 @@ fieldset/CCCSR:
    description: Code selection
    bit_offset: 1
    bit_size: 1
-  - name: READY
+  - name: RDY
    description: Compensation cell ready flag
    bit_offset: 8
    bit_size: 1
@ -217,10 +217,11 @@ fieldset/PMCR:
    description: Analog switch supply voltage selection
    bit_offset: 9
    bit_size: 1
-  - name: EPIS
-    description: Ethernet PHY Interface Selection
+  - name: ETH_SEL_PHY
+    description: Ethernet PHY interface selection.
    bit_offset: 21
    bit_size: 3
+    enum: ETH_SEL_PHY
  - name: PA0SO
    description: PA0 Switch Open
    bit_offset: 24
@ -407,3 +408,12 @@ fieldset/UR9:
    description: Protected area start address for bank 2
    bit_offset: 16
    bit_size: 12
+enum/ETH_SEL_PHY:
+  bit_size: 3
+  variants:
+  - name: MII_GMII
+    description: GMII or MII
+    value: 0
+  - name: RMII
+    description: RMII
+    value: 4
--- a/data/registers/syscfg_h7rs.yaml
+++ b/data/registers/syscfg_h7rs.yaml
@ -0,0 +1,364 @@
+block/SYSCFG:
+  description: System configuration, boot and security.
+  items:
+  - name: BOOTSR
+    description: SBS boot status register.
+    byte_offset: 0
+    fieldset: BOOTSR
+  - name: HDPLCR
+    description: SBS hide protection control register.
+    byte_offset: 16
+    fieldset: HDPLCR
+  - name: HDPLSR
+    description: SBS hide protection status register.
+    byte_offset: 20
+    fieldset: HDPLSR
+  - name: DBGCR
+    description: SBS debug control register.
+    byte_offset: 32
+    fieldset: DBGCR
+  - name: DBGLOCKR
+    description: SBS debug lock register.
+    byte_offset: 36
+    fieldset: DBGLOCKR
+  - name: RSSCMDR
+    description: SBS RSS command register.
+    byte_offset: 52
+    fieldset: RSSCMDR
+  - name: PMCR
+    description: SBS product mode and configuration register.
+    byte_offset: 256
+    fieldset: PMCR
+  - name: FPUIMR
+    description: SBS FPU interrupt mask register.
+    byte_offset: 260
+    fieldset: FPUIMR
+  - name: MESR
+    description: SBS memory erase status register.
+    byte_offset: 264
+    fieldset: MESR
+  - name: CCCSR
+    description: SBS I/O compensation cell control and status register.
+    byte_offset: 272
+    fieldset: CCCSR
+  - name: CCVALR
+    description: SBS compensation cell for I/Os value register.
+    byte_offset: 276
+    fieldset: CCVALR
+  - name: CCSWVALR
+    description: SBS compensation cell for I/Os software value register.
+    byte_offset: 280
+    fieldset: CCSWVALR
+  - name: BKLOCKR
+    description: SBS break lockup register.
+    byte_offset: 288
+    fieldset: BKLOCKR
+  - name: EXTICR
+    description: external interrupt configuration register
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 304
+    fieldset: EXTICR
+fieldset/BKLOCKR:
+  description: SBS break lockup register.
+  fields:
+  - name: PVD_BL
+    description: PVD break lock This bit is set by SW and cleared only by a system reset. it can be used to enable and lock the connection to TIM1/8/15/16/17Break input as well as the PVDE and PLS[2:0] bitfields in the PWR_CR1 register. Once set, this bit is cleared only by a system reset.
+    bit_offset: 2
+    bit_size: 1
+  - name: FLASHECC_BL
+    description: Flash ECC error break lock Set this bit to enable and lock the connection between embedded flash memory ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
+    bit_offset: 3
+    bit_size: 1
+  - name: CM7LCKUP_BL
+    description: Cortex-M7 lockup break lock Set this bit to enable and lock the connection between the Cortex-M7 lockup (HardFault) output and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
+    bit_offset: 6
+    bit_size: 1
+  - name: BKRAMECC_BL
+    description: Backup RAM ECC error break lock Set this bit to enable and lock the connection between backup RAM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
+    bit_offset: 7
+    bit_size: 1
+  - name: DTCMECC_BL
+    description: 'DTCM ECC error break lock Set this bit to enable and lock the connection between DTCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. Note: The DTCM0 and DTCM1 are Ored to give DTCMECC.'
+    bit_offset: 13
+    bit_size: 1
+  - name: ITCMECC_BL
+    description: ITCM ECC error break lock Set this bit to enable and lock the connection between ITCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
+    bit_offset: 14
+    bit_size: 1
+  - name: ARAM3ECC_BL
+    description: AXIRAM3 ECC error break lock Set this bit to enable and lock the connection between AXIRAM3 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set this bit is cleared only by a system reset.
+    bit_offset: 21
+    bit_size: 1
+  - name: ARAM1ECC_BL
+    description: AXIRAM1 ECC error break lock Set this bit to enable and lock the connection between AXIRAM1 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
+    bit_offset: 23
+    bit_size: 1
+fieldset/BOOTSR:
+  description: SBS boot status register.
+  fields:
+  - name: INITVTOR
+    description: initial vector for Cortex-M7 This register includes the physical boot address used by the Cortex-M7 after reset.
+    bit_offset: 0
+    bit_size: 32
+fieldset/CCCSR:
+  description: SBS I/O compensation cell control and status register.
+  fields:
+  - name: COMP_EN
+    description: Compensation cell enable Set this bit to enable the compensation cell.
+    bit_offset: 0
+    bit_size: 1
+  - name: COMP_CODESEL
+    description: Compensation cell code selection This bit selects the code to be applied for the I/O compensation cell.
+    bit_offset: 1
+    bit_size: 1
+  - name: OCTO1_COMP_EN
+    description: XSPIM_P1 compensation cell enable Set this bit to enable the XSPIM_P1 compensation cell.
+    bit_offset: 2
+    bit_size: 1
+  - name: OCTO1_COMP_CODESEL
+    description: XSPIM_P1 compensation cell code selection This bit selects the code to be applied for the XSPIM_P1 I/O compensation cell.
+    bit_offset: 3
+    bit_size: 1
+  - name: OCTO2_COMP_EN
+    description: XSPIM_P2 compensation cell enable Set this bit to enable the XSPIM_P2 compensation cell.
+    bit_offset: 4
+    bit_size: 1
+  - name: OCTO2_COMP_CODESEL
+    description: XSPIM_P2 compensation cell code selection This bit selects the code to be applied for the XSPIM_P2 I/O compensation cell.
+    bit_offset: 5
+    bit_size: 1
+  - name: COMP_RDY
+    description: Compensation cell ready This bit provides the status of the compensation cell.
+    bit_offset: 8
+    bit_size: 1
+  - name: OCTO1_COMP_RDY
+    description: XSPIM_P1 compensation cell ready This bit provides the status of the XSPIM_P1 compensation cell.
+    bit_offset: 9
+    bit_size: 1
+  - name: OCTO2_COMP_RDY
+    description: XSPIM_P2 compensation cell ready This bit provides the status of the XSPIM_P2 compensation cell.
+    bit_offset: 10
+    bit_size: 1
+  - name: IOHSLV
+    description: I/O high speed at low voltage When this bit is set, the speed of the I/Os is optimized when the device voltage is low. This bit is active only if VDDIO_HSLV user option bit is set in FLASH. It must be used only if the device supply voltage is below 2.7 V. Setting this bit when V<sub>DD</sub> is higher than 2.7 V may be destructive.
+    bit_offset: 16
+    bit_size: 1
+  - name: OCTO1_IOHSLV
+    description: XSPIM_P1 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P1 I/Os is optimized when the device voltage is low. This bit is active only if OCTO1_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when V<sub>DD</sub> is higher than 2.7 V may be destructive.
+    bit_offset: 17
+    bit_size: 1
+  - name: OCTO2_IOHSLV
+    description: XSPIM_P2 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P2 I/Os is optimized when the device voltage is low. This bit is active only if OCTO2_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when V<sub>DD</sub> is higher than 2.7 V may be destructive.
+    bit_offset: 18
+    bit_size: 1
+fieldset/CCSWVALR:
+  description: SBS compensation cell for I/Os software value register.
+  fields:
+  - name: SW_NSRC
+    description: Software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register.
+    bit_offset: 0
+    bit_size: 4
+  - name: SW_PSRC
+    description: Software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register.
+    bit_offset: 4
+    bit_size: 4
+  - name: OCTO1_SW_NSRC
+    description: XSPIM_P1 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew -ate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register.
+    bit_offset: 8
+    bit_size: 4
+  - name: OCTO1_SW_PSRC
+    description: XSPIM_P1 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register.
+    bit_offset: 12
+    bit_size: 4
+  - name: OCTO2_SW_NSRC
+    description: XSPIM_P2 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register.
+    bit_offset: 16
+    bit_size: 4
+  - name: OCTO2_SW_PSRC
+    description: XSPIM_P2 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register.
+    bit_offset: 20
+    bit_size: 4
+fieldset/CCVALR:
+  description: SBS compensation cell for I/Os value register.
+  fields:
+  - name: NSRC
+    description: NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register.
+    bit_offset: 0
+    bit_size: 4
+  - name: PSRC
+    description: PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register.
+    bit_offset: 4
+    bit_size: 4
+  - name: OCTO1_NSRC
+    description: XSPIM_P1 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register.
+    bit_offset: 8
+    bit_size: 4
+  - name: OCTO1_PSRC
+    description: XSPIM_P1 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register.
+    bit_offset: 12
+    bit_size: 4
+  - name: OCTO2_NSRC
+    description: XSPIM_P2 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register.
+    bit_offset: 16
+    bit_size: 4
+  - name: OCTO2_PSRC
+    description: XSPIM_P2 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register.
+    bit_offset: 20
+    bit_size: 4
+fieldset/DBGCR:
+  description: SBS debug control register.
+  fields:
+  - name: AP_UNLOCK
+    description: access port unlock Write 0xB4 to this bitfield to open the device access port.
+    bit_offset: 0
+    bit_size: 8
+  - name: DBG_UNLOCK
+    description: debug unlock Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register.
+    bit_offset: 8
+    bit_size: 8
+  - name: DBG_AUTH_HDPL
+    description: 'authenticated debug hide protection level Writing to this bitfield defines at which HDPL the authenticated debug opens. Note: Writing any other values is ignored. Reading any other value means the authenticated debug always fails.'
+    bit_offset: 16
+    bit_size: 8
+    enum: DBG_AUTH_HDPL
+fieldset/DBGLOCKR:
+  description: SBS debug lock register.
+  fields:
+  - name: DBGCFG_LOCK
+    description: 'debug configuration lock Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4. Other: Writes to SBS_DBGCR ignored Note: 0xC3 is the recommended value to lock the debug configuration using this bitfield.'
+    bit_offset: 0
+    bit_size: 8
+    enum: DBGCFG_LOCK
+fieldset/EXTICR:
+  description: external interrupt configuration register 2
+  fields:
+  - name: EXTI
+    description: EXTI x configuration (x = 4 to 7)
+    bit_offset: 0
+    bit_size: 4
+    array:
+      len: 4
+      stride: 4
+fieldset/FPUIMR:
+  description: SBS FPU interrupt mask register.
+  fields:
+  - name: FPU_IE
+    description: 'FPU interrupt enable Set and cleared by software to enable the Cortex-M7 FPU interrupts xxxxx1: Invalid operation interrupt enabled (xxxxx0 to disable) xxxx1x: Divide-by-zero interrupt enabled (xxxx0x to disable) xxx1xx: Underflow interrupt enabled (xxx0xx to disable) xx1xxx: Overflow interrupt enabled (xx0xxx to disable) x1xxxx: Input denormal interrupt enabled (x0xxxx to disable) 1xxxxx: Inexact interrupt enabled (0xxxxx to disable), disabled by default.'
+    bit_offset: 0
+    bit_size: 6
+fieldset/HDPLCR:
+  description: SBS hide protection control register.
+  fields:
+  - name: INCR_HDPL
+    description: increment HDPL Write 0x6A to increment device HDPL by one. After a write, the register value reverts to its default value (0xB4).
+    bit_offset: 0
+    bit_size: 8
+fieldset/HDPLSR:
+  description: SBS hide protection status register.
+  fields:
+  - name: HDPL
+    description: 'hide protection level This bitfield returns the current HDPL of the device. 0x6F and other codes: HDPL3, corresponding to non-boot application. Note: The device state (open/close) is defined in FLASH_NVSTATER register of the embedded Flash memory.'
+    bit_offset: 0
+    bit_size: 8
+    enum: HDPL
+fieldset/MESR:
+  description: SBS memory erase status register.
+  fields:
+  - name: MEF
+    description: 'memory erase flag This bit is set by hardware when BKPRAM and PKA SRAM erase is ongoing after a POWER ON reset or one tamper event (see Section 50: Tamper and backup registers (TAMP) for details). This bit is cleared when the erase is done.'
+    bit_offset: 0
+    bit_size: 1
+fieldset/PMCR:
+  description: SBS product mode and configuration register.
+  fields:
+  - name: FMPLUS_PB6
+    description: Fast-mode Plus on PB(6).
+    bit_offset: 4
+    bit_size: 1
+  - name: FMPLUS_PB7
+    description: Fast-mode Plus on PB(7).
+    bit_offset: 5
+    bit_size: 1
+  - name: FMPLUS_PB8
+    description: Fast-mode Plus on PB(8).
+    bit_offset: 6
+    bit_size: 1
+  - name: FMPLUS_PB9
+    description: Fast-mode Plus on PB(9).
+    bit_offset: 7
+    bit_size: 1
+  - name: BOOSTEN
+    description: booster enable Set this bit to reduce the THD of the analog switches when the supply voltage is below 2.7 V. guaranteeing the same performance as with the full voltage range. To avoid current consumption due to booster activation when V<sub>DDA</sub> < 2.7 V and V<sub>DD</sub> > 2.7 V, V<sub>DD</sub> can be selected as supply voltage for analog switches by setting BOOSTVDDSEL bit in SBS_PMCR. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption.
+    bit_offset: 8
+    bit_size: 1
+  - name: BOOSTVDDSEL
+    description: booster V<sub>DD</sub> selection This bit selects the analog switch supply voltage, between V<sub>DD</sub>, V<sub>DDA</sub> and booster. To avoid current consumption due to booster activation when V<sub>DDA</sub> < 2.7 V and V<sub>DD</sub> > 2.7 V, V<sub>DD</sub> can be selected as supply voltage for analog switches. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption. When both V<sub>DD and </sub>V<sub>DDA</sub> are below 2.7 V, the booster is still needed to obtain full AC performances from the I/O analog switches.
+    bit_offset: 9
+    bit_size: 1
+  - name: ETH_SEL_PHY
+    description: Ethernet PHY interface selection.
+    bit_offset: 21
+    bit_size: 3
+    enum: ETH_SEL_PHY
+  - name: AXIRAM_WS
+    description: AXIRAM wait state Set this bit to add one wait state to all AXIRAMs when ECC = 0. When ECC = 1 there is one wait state by default.
+    bit_offset: 28
+    bit_size: 1
+    enum: AXIRAM_WS
+fieldset/RSSCMDR:
+  description: SBS RSS command register.
+  fields:
+  - name: RSSCMD
+    description: RSS command The application can use this bitfield to pass on a command to the RSS, executed at the next reset.
+    bit_offset: 0
+    bit_size: 16
+enum/AXIRAM_WS:
+  bit_size: 1
+  variants:
+  - name: Ws0
+    description: No wait state added when accessing any AXIRAM with ECC = 0.
+    value: 0
+  - name: Ws1
+    description: One wait state added when accessing any AXIRAM with ECC = 0. In this case, Fmax = 500 MHz is not guaranteed. (TBC).
+    value: 1
+enum/DBGCFG_LOCK:
+  bit_size: 8
+  variants:
+  - name: Unlock
+    description: Writes to SBS_DBGCR allowed (default).
+    value: 180
+enum/DBG_AUTH_HDPL:
+  bit_size: 8
+  variants:
+  - name: HDPL1
+    description: HDPL1.
+    value: 81
+  - name: HDPL3
+    description: HDPL3.
+    value: 111
+  - name: HDPL2
+    description: HDPL2.
+    value: 138
+enum/ETH_SEL_PHY:
+  bit_size: 3
+  variants:
+  - name: MII_GMII
+    description: GMII or MII
+    value: 0
+  - name: RMII
+    description: RMII
+    value: 4
+enum/HDPL:
+  bit_size: 8
+  variants:
+  - name: HDPL1
+    description: HDPL1.
+    value: 81
+  - name: HDPL2
+    description: HDPL2.
+    value: 138
+  - name: HDPL0
+    description: HDPL0, corresponding to ST-RSS (default when device is close).
+    value: 180
--- a/stm32-data-gen/src/chips.rs
+++ b/stm32-data-gen/src/chips.rs
@ -88,7 +88,7 @@ fn chip_name_from_package_name(x: &str) -> String {
        (regex!("^(STM32G0....).xN$"), "$1"),
        (regex!("^(STM32L5....).x[PQ]$"), "$1"),
        (regex!("^(STM32L0....).xS$"), "$1"),
-        (regex!("^(STM32H7....).xQ$"), "$1"),
+        (regex!("^(STM32H7....).x[QH]$"), "$1"),
        (regex!("^(STM32U5....).xQ$"), "$1"),
        (regex!("^(STM32H5....).xQ$"), "$1"),
        (regex!("^(STM32WBA....).x$"), "$1"),
@ -247,6 +247,7 @@ impl PeriMatcher {
            ("STM32L5.*:SYSCFG:.*", ("syscfg", "l5", "SYSCFG")),
            ("STM32G0.*:SYSCFG:.*", ("syscfg", "g0", "SYSCFG")),
            ("STM32G4.*:SYSCFG:.*", ("syscfg", "g4", "SYSCFG")),
+            ("STM32H7[RS].*:SYSCFG:.*", ("syscfg", "h7rs", "SYSCFG")),
            (
                "STM32H7(45|47|55|57|42|43|53|50).*:SYSCFG:.*",
                ("syscfg", "h7od", "SYSCFG"),
@ -345,6 +346,7 @@ impl PeriMatcher {
            ("STM32F7.*:RCC:.*", ("rcc", "f7", "RCC")),
            ("STM32G0.*:RCC:.*", ("rcc", "g0", "RCC")),
            ("STM32G4.*:RCC:.*", ("rcc", "g4", "RCC")),
+            ("STM32H7[RS].*:RCC:.*", ("rcc", "h7rs", "RCC")),
            ("STM32H7[AB].*:RCC:.*", ("rcc", "h7ab", "RCC")),
            ("STM32H7(42|43|53|50).*:RCC:.*", ("rcc", "h7rm0433", "RCC")),
            ("STM32H7.*:RCC:.*", ("rcc", "h7", "RCC")),
@ -394,6 +396,7 @@ impl PeriMatcher {
            ("STM32C0.*:PWR:.*", ("pwr", "c0", "PWR")),
            ("STM32G0.*:PWR:.*", ("pwr", "g0", "PWR")),
            ("STM32G4.*:PWR:.*", ("pwr", "g4", "PWR")),
+            ("STM32H7[RS].*:PWR:.*", ("pwr", "h7rs", "PWR")),
            ("STM32H7(45|47|55|57).*:PWR:.*", ("pwr", "h7rm0399", "PWR")),
            ("STM32H7(42|43|53|50).*:PWR:.*", ("pwr", "h7rm0433", "PWR")),
            ("STM32H7(23|25|33|35|30).*:PWR:.*", ("pwr", "h7rm0468", "PWR")),
@ -417,6 +420,7 @@ impl PeriMatcher {
            ("STM32WB.*:PWR:.*", ("pwr", "wb", "PWR")),
            ("STM32H50.*:PWR:.*", ("pwr", "h50", "PWR")),
            ("STM32H5.*:PWR:.*", ("pwr", "h5", "PWR")),
+            ("STM32H7[RS].*:FLASH:.*", ("flash", "h7rs", "FLASH")),
            ("STM32H7(A3|B3|B0).*:FLASH:.*", ("flash", "h7ab", "FLASH")),
            ("STM32H7.*:FLASH:.*", ("flash", "h7", "FLASH")),
            ("STM32F0.*:FLASH:.*", ("flash", "f0", "FLASH")),
@ -573,7 +577,8 @@ impl PeriMatcher {
            ("STM32WL5.*:HSEM:.*", ("hsem", "v3", "HSEM")),
            ("STM32WLE.*:HSEM:.*", ("hsem", "v4", "HSEM")),
            (".*:DMAMUX.*", ("dmamux", "v1", "DMAMUX")),
-            (r".*:GPDMA\d?:.*", ("gpdma", "v1", "GPDMA")),
+            (r".*:GPDMA\d?:.*", ("gpdma", "v1", "GPDMA")), // TODO there's multiple versions for with+without trustzone.
+            (r".*:HPDMA\d?:.*", ("gpdma", "v1", "GPDMA")), // TODO it has a few more bits like DWX
            (r".*:LPDMA\d?:.*", ("lpdma", "v1", "LPDMA")),
            (r".*:BDMA\d?:.*", ("bdma", "v1", "DMA")),
            ("STM32H7.*:DMA2D:DMA2D:dma2d1_v1_0", ("dma2d", "v2", "DMA2D")),
@ -661,6 +666,7 @@ impl PeriMatcher {
            (".*:HASH:hash1_v4_0", ("hash", "v3", "HASH")),
            (".*:CRYP:cryp1_v1_0.*", ("cryp", "v1", "CRYP")),
            (".*:CRYP:cryp1_v2_0_H7.*", ("cryp", "v3", "CRYP")),
+            (".*:CRYP:cryp1-v2_5", ("cryp", "v4", "CRYP")),
            (".*:CRYP:cryp1_v2_0.*", ("cryp", "v2", "CRYP")),
            ("STM32F41.*:CRYP:cryp1_v2_2.*", ("cryp", "v1", "CRYP")),
            (".*:CRYP:cryp1_v2_2.*", ("cryp", "v2", "CRYP")),
@ -807,9 +813,6 @@ pub fn parse_groups() -> Result<(HashMap<String, Chip>, Vec<ChipGroup>), anyhow:
 static NOPELIST: &[&str] = &[
    // Not supported, not planned unless someone wants to do it.
    "STM32MP",
-    // not supported yet, planned. Pull requests welcome!
-    "STM32H7R",
-    "STM32H7S",
    // Does not exist in ST website. No datasheet, no RM.
    "STM32GBK",
    "STM32L485",
@ -1325,8 +1328,8 @@ fn process_core(
                );
            }
        }
-            chs.sort_by_key(|ch| (ch.channel.clone(), ch.dmamux.clone(), ch.request));
-            p.dma_channels = chs;
+        chs.sort_by_key(|ch| (ch.channel.clone(), ch.dmamux.clone(), ch.request));
+        p.dma_channels = chs;
    }

    let mut core = stm32_data_serde::chip::Core {
--- a/stm32-data-gen/src/dma.rs
+++ b/stm32-data-gen/src/dma.rs
@ -302,6 +302,8 @@ impl DmaChannels {
            ("U5_GPDMA1.yaml", "GPDMA1", "STM32U5_dma3_Cube", 16, 4),
            ("U5_LPDMA.yaml", "LPDMA1", "STM32U5_dma3_Cube", 4, 0),
            ("WBA_GPDMA1.yaml", "GPDMA1", "STM32WBA_dma3_Cube", 8, 0),
+            ("H7RS_GPDMA.yaml", "GPDMA1", "STM32H7RS_dma3_Cube", 16, 4),
+            ("H7RS_HPDMA.yaml", "HPDMA1", "STM32H7RS_dma3_Cube", 16, 4),
        ] {
            let mut chip_dma = ChipDma {
                peripherals: HashMap::new(),
--- a/stm32-data-gen/src/interrupts.rs
+++ b/stm32-data-gen/src/interrupts.rs
@ -269,6 +269,8 @@ impl ChipInterrupts {
                let peri_names: Vec<_> = parts[2]
                    .split(',')
                    .map(|x| if x == "USB_DRD_FS" { "USB" } else { x })
+                    .map(|x| if x == "XPI1" { "XSPI1" } else { x })
+                    .map(|x| if x == "XPI2" { "XSPI2" } else { x })
                    .map(ToString::to_string)
                    .collect();

@ -471,7 +473,7 @@ fn valid_signals(peri: &str) -> Vec<String> {
        ("CAN", &["TX", "RX0", "RX1", "SCE"]),
        ("FDCAN", &["IT0", "IT1", "CAL"]),
        ("I2C", &["ER", "EV"]),
-        ("I3C", &["ER", "EV"]),
+        ("I3C", &["ER", "EV", "WKUP"]),
        ("FMPI2C", &["ER", "EV"]),
        ("TIM", &["BRK", "UP", "TRG", "COM", "CC"]),
        // ("HRTIM", &["Master", "TIMA", "TIMB", "TIMC", "TIMD", "TIME", "TIMF"]),
@ -499,6 +501,8 @@ fn valid_signals(peri: &str) -> Vec<String> {
        ("USB_OTG_HS", &["GLOBAL", "EP1_OUT", "EP1_IN", "WKUP"]),
        ("USB", &["LP", "HP", "WKUP"]),
        ("GPU2D", &["ER"]),
+        ("SAI", &["A", "B"]),
+        ("ADF", &["FLT0"]),
    ];

    for (prefix, signals) in IRQ_SIGNALS_MAP {
@ -517,6 +521,8 @@ static PICK_NVIC: RegexMap<&str> = RegexMap::new(&[
    ("STM32WL5.*:cm0p", "NVIC2"),
    // Exception 2: TrustZone: NVIC1 is Secure mode, NVIC2 is NonSecure mode. For now, we pick the NonSecure one.
    ("STM32(L5|U5|H5[2367]|WBA5[245]).*", "NVIC2"),
+    // Exception 3: NVICs are split for "bootloader" and "application", not sure what that means?
+    ("STM32H7[RS].*", "NVIC2"),
    // catch-all: Most chips have a single NVIC, named "NVIC"
    (".*", "NVIC"),
 ]);
--- a/stm32-data-gen/src/memory.rs
+++ b/stm32-data-gen/src/memory.rs
@ -146,6 +146,8 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
    ("STM32H5...E",                  mem!(BANK_1 0x08000000 256, BANK_2 0x08040000 256, SRAM1 0x20000000 128, SRAM2 0x20020000 80, SRAM3 0x20034000 64)),
    ("STM32H5...G",                  mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM1 0x20000000 256, SRAM2 0x20040000 64, SRAM3 0x20050000 320)),
    ("STM32H5...I",                  mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM1 0x20000000 256, SRAM2 0x20040000 64, SRAM3 0x20050000 320)),
+    // H7RS
+    ("STM32H7[RS].*",                mem!(BANK_1 0x08000000 64, ITCM 0x00000000 192, DTCM 0x20000000 192, SRAM1 0x24000000 128, SRAM2 0x24020000 128, SRAM3 0x24040000 128, SRAM4 0x24060000 72, AHB_SRAM1 0x30000000 16, AHB_SRAM2 0x30004000 16)),
    // H7. TODO: check
    ("STM32H7...E",                  mem!(BANK_1 0x08000000 512, SRAM 0x24000000 128)),
    ("STM32H7[23]..G",               mem!(BANK_1 0x08000000 1024, SRAM 0x24000000 128)),
@ -264,6 +266,7 @@ static FLASH_INFO: RegexMap<FlashInfo> = RegexMap::new(&[
    ("STM32G4[78].*",           FlashInfo{ erase_value: 0xFF, write_size:  8, erase_size: &[(  4*1024, 0)] }),
    ("STM32G4.*",               FlashInfo{ erase_value: 0xFF, write_size:  8, erase_size: &[(  2*1024, 0)] }),
    ("STM32H5.*",               FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[(  8*1024, 0)] }),
+    ("STM32H7[RS].*",           FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[(  8*1024, 0)] }),
    ("STM32H7[AB].*",           FlashInfo{ erase_value: 0xFF, write_size: 32, erase_size: &[(  8*1024, 0)] }),
    ("STM32H7.*",               FlashInfo{ erase_value: 0xFF, write_size: 32, erase_size: &[(128*1024, 0)] }),
    ("STM32L4[PQRS].*",         FlashInfo{ erase_value: 0xFF, write_size:  8, erase_size: &[(  8*1024, 0)] }),
--- a/stm32-data-gen/src/rcc.rs
+++ b/stm32-data-gen/src/rcc.rs
@ -85,13 +85,19 @@ impl ParsedRccs {
            "PLL1_P_MUL_2",
            "PLL1_Q",
            "PLL1_R",
+            "PLL1_S",
+            "PLL1_T",
            "PLL1_VCO", // used for L0 USB
            "PLL2_P",
            "PLL2_Q",
            "PLL2_R",
+            "PLL2_S",
+            "PLL2_T",
            "PLL3_P",
            "PLL3_Q",
            "PLL3_R",
+            "PLL3_S",
+            "PLL3_T",
            "HSI",
            "SHSI",
            "HSI48",
@ -130,6 +136,10 @@ impl ParsedRccs {
            "HSI256_MSIS1024_MSIK4",
            "HSI256_MSIK1024_MSIS4",
            "HSI256_MSIK1024_MSIK4",
+            "SPDIFRX_SYMB",
+            "ETH_RMII_REF",
+            "ETH",
+            "CLK48MOHCI",
        ]);

        let mux_regexes = &[
@ -137,13 +147,19 @@ impl ParsedRccs {
            regex!(r"^CCIPR\d?/(.+)SEL$"),
            regex!(r"^D\dCCIP\d?R/(.+)SEL$"),
            regex!(r"^CFGR\d/(.+)SW$"),
+            regex!(r"^.+PERCKSELR/(.+)SEL$"),
        ];
+        let mux_nopelist = &[regex!(r"^.+PERCKSELR/USBREFCKSEL$")];

        let mut mux = HashMap::new();
        for (reg, body) in &ir.fieldsets {
            for field in &body.fields {
                let key = format!("{}/{}", reg, field.name);
                if let Some(capture) = mux_regexes.iter().find_map(|r| r.captures(&key)) {
+                    if mux_nopelist.iter().any(|r| r.is_match(&key)) {
+                        continue;
+                    }
+
                    let peri = capture.get(1).unwrap().as_str();

                    // TODO: these bits are duplicated on F4, we need to split the F4 RCCs more.
@ -331,6 +347,8 @@ impl ParsedRccs {
                        maybe_kernel_clock = "PLL1_Q".to_string();
                    } else if rcc_version.starts_with("l1") {
                        maybe_kernel_clock = "PLL1_VCO_DIV_2".to_string();
+                    } else if rcc_version.starts_with("h7rs") {
+                        maybe_kernel_clock = "USB".to_string();
                    } else {
                        panic!("rcc_{}: peripheral {} missing mux", rcc_version, peri_name)
                    }