365 lines
18 KiB
YAML
365 lines
18 KiB
YAML
block/SYSCFG:
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description: System configuration, boot and security.
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items:
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- name: BOOTSR
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description: SBS boot status register.
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byte_offset: 0
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fieldset: BOOTSR
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- name: HDPLCR
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description: SBS hide protection control register.
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byte_offset: 16
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fieldset: HDPLCR
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- name: HDPLSR
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description: SBS hide protection status register.
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byte_offset: 20
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fieldset: HDPLSR
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- name: DBGCR
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description: SBS debug control register.
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byte_offset: 32
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fieldset: DBGCR
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- name: DBGLOCKR
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description: SBS debug lock register.
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byte_offset: 36
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fieldset: DBGLOCKR
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- name: RSSCMDR
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description: SBS RSS command register.
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byte_offset: 52
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fieldset: RSSCMDR
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- name: PMCR
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description: SBS product mode and configuration register.
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byte_offset: 256
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fieldset: PMCR
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- name: FPUIMR
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description: SBS FPU interrupt mask register.
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byte_offset: 260
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fieldset: FPUIMR
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- name: MESR
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description: SBS memory erase status register.
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byte_offset: 264
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fieldset: MESR
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- name: CCCSR
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description: SBS I/O compensation cell control and status register.
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byte_offset: 272
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fieldset: CCCSR
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- name: CCVALR
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description: SBS compensation cell for I/Os value register.
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byte_offset: 276
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fieldset: CCVALR
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- name: CCSWVALR
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description: SBS compensation cell for I/Os software value register.
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byte_offset: 280
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fieldset: CCSWVALR
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- name: BKLOCKR
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description: SBS break lockup register.
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byte_offset: 288
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fieldset: BKLOCKR
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- name: EXTICR
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description: external interrupt configuration register
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array:
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len: 4
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stride: 4
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byte_offset: 304
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fieldset: EXTICR
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fieldset/BKLOCKR:
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description: SBS break lockup register.
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fields:
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- name: PVD_BL
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description: PVD break lock This bit is set by SW and cleared only by a system reset. it can be used to enable and lock the connection to TIM1/8/15/16/17Break input as well as the PVDE and PLS[2:0] bitfields in the PWR_CR1 register. Once set, this bit is cleared only by a system reset.
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bit_offset: 2
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bit_size: 1
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- name: FLASHECC_BL
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description: Flash ECC error break lock Set this bit to enable and lock the connection between embedded flash memory ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
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bit_offset: 3
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bit_size: 1
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- name: CM7LCKUP_BL
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description: Cortex-M7 lockup break lock Set this bit to enable and lock the connection between the Cortex-M7 lockup (HardFault) output and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
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bit_offset: 6
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bit_size: 1
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- name: BKRAMECC_BL
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description: Backup RAM ECC error break lock Set this bit to enable and lock the connection between backup RAM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
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bit_offset: 7
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bit_size: 1
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- name: DTCMECC_BL
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description: 'DTCM ECC error break lock Set this bit to enable and lock the connection between DTCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. Note: The DTCM0 and DTCM1 are Ored to give DTCMECC.'
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bit_offset: 13
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bit_size: 1
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- name: ITCMECC_BL
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description: ITCM ECC error break lock Set this bit to enable and lock the connection between ITCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
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bit_offset: 14
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bit_size: 1
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- name: ARAM3ECC_BL
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description: AXIRAM3 ECC error break lock Set this bit to enable and lock the connection between AXIRAM3 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set this bit is cleared only by a system reset.
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bit_offset: 21
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bit_size: 1
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- name: ARAM1ECC_BL
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description: AXIRAM1 ECC error break lock Set this bit to enable and lock the connection between AXIRAM1 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
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bit_offset: 23
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bit_size: 1
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fieldset/BOOTSR:
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description: SBS boot status register.
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fields:
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- name: INITVTOR
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description: initial vector for Cortex-M7 This register includes the physical boot address used by the Cortex-M7 after reset.
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bit_offset: 0
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bit_size: 32
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fieldset/CCCSR:
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description: SBS I/O compensation cell control and status register.
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fields:
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- name: COMP_EN
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description: Compensation cell enable Set this bit to enable the compensation cell.
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bit_offset: 0
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bit_size: 1
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- name: COMP_CODESEL
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description: Compensation cell code selection This bit selects the code to be applied for the I/O compensation cell.
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bit_offset: 1
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bit_size: 1
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- name: OCTO1_COMP_EN
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description: XSPIM_P1 compensation cell enable Set this bit to enable the XSPIM_P1 compensation cell.
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bit_offset: 2
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bit_size: 1
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- name: OCTO1_COMP_CODESEL
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description: XSPIM_P1 compensation cell code selection This bit selects the code to be applied for the XSPIM_P1 I/O compensation cell.
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bit_offset: 3
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bit_size: 1
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- name: OCTO2_COMP_EN
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description: XSPIM_P2 compensation cell enable Set this bit to enable the XSPIM_P2 compensation cell.
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bit_offset: 4
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bit_size: 1
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- name: OCTO2_COMP_CODESEL
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description: XSPIM_P2 compensation cell code selection This bit selects the code to be applied for the XSPIM_P2 I/O compensation cell.
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bit_offset: 5
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bit_size: 1
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- name: COMP_RDY
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description: Compensation cell ready This bit provides the status of the compensation cell.
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bit_offset: 8
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bit_size: 1
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- name: OCTO1_COMP_RDY
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description: XSPIM_P1 compensation cell ready This bit provides the status of the XSPIM_P1 compensation cell.
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bit_offset: 9
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bit_size: 1
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- name: OCTO2_COMP_RDY
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description: XSPIM_P2 compensation cell ready This bit provides the status of the XSPIM_P2 compensation cell.
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bit_offset: 10
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bit_size: 1
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- name: IOHSLV
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description: I/O high speed at low voltage When this bit is set, the speed of the I/Os is optimized when the device voltage is low. This bit is active only if VDDIO_HSLV user option bit is set in FLASH. It must be used only if the device supply voltage is below 2.7 V. Setting this bit when V<sub>DD</sub> is higher than 2.7 V may be destructive.
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bit_offset: 16
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bit_size: 1
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- name: OCTO1_IOHSLV
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description: XSPIM_P1 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P1 I/Os is optimized when the device voltage is low. This bit is active only if OCTO1_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when V<sub>DD</sub> is higher than 2.7 V may be destructive.
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bit_offset: 17
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bit_size: 1
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- name: OCTO2_IOHSLV
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description: XSPIM_P2 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P2 I/Os is optimized when the device voltage is low. This bit is active only if OCTO2_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when V<sub>DD</sub> is higher than 2.7 V may be destructive.
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bit_offset: 18
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bit_size: 1
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fieldset/CCSWVALR:
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description: SBS compensation cell for I/Os software value register.
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fields:
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- name: SW_NSRC
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description: Software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register.
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bit_offset: 0
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bit_size: 4
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- name: SW_PSRC
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description: Software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register.
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bit_offset: 4
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bit_size: 4
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- name: OCTO1_SW_NSRC
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description: XSPIM_P1 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew -ate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register.
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bit_offset: 8
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bit_size: 4
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- name: OCTO1_SW_PSRC
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description: XSPIM_P1 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register.
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bit_offset: 12
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bit_size: 4
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- name: OCTO2_SW_NSRC
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description: XSPIM_P2 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register.
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bit_offset: 16
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bit_size: 4
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- name: OCTO2_SW_PSRC
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description: XSPIM_P2 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register.
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bit_offset: 20
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bit_size: 4
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fieldset/CCVALR:
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description: SBS compensation cell for I/Os value register.
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fields:
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- name: NSRC
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description: NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register.
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bit_offset: 0
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bit_size: 4
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- name: PSRC
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description: PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register.
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bit_offset: 4
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bit_size: 4
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- name: OCTO1_NSRC
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description: XSPIM_P1 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register.
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bit_offset: 8
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bit_size: 4
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- name: OCTO1_PSRC
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description: XSPIM_P1 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register.
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bit_offset: 12
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bit_size: 4
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- name: OCTO2_NSRC
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description: XSPIM_P2 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register.
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bit_offset: 16
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bit_size: 4
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- name: OCTO2_PSRC
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description: XSPIM_P2 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register.
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bit_offset: 20
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bit_size: 4
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fieldset/DBGCR:
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description: SBS debug control register.
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fields:
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- name: AP_UNLOCK
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description: access port unlock Write 0xB4 to this bitfield to open the device access port.
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bit_offset: 0
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bit_size: 8
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- name: DBG_UNLOCK
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description: debug unlock Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register.
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bit_offset: 8
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bit_size: 8
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- name: DBG_AUTH_HDPL
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description: 'authenticated debug hide protection level Writing to this bitfield defines at which HDPL the authenticated debug opens. Note: Writing any other values is ignored. Reading any other value means the authenticated debug always fails.'
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bit_offset: 16
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bit_size: 8
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enum: DBG_AUTH_HDPL
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fieldset/DBGLOCKR:
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description: SBS debug lock register.
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fields:
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- name: DBGCFG_LOCK
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description: 'debug configuration lock Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4. Other: Writes to SBS_DBGCR ignored Note: 0xC3 is the recommended value to lock the debug configuration using this bitfield.'
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bit_offset: 0
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bit_size: 8
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enum: DBGCFG_LOCK
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fieldset/EXTICR:
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description: external interrupt configuration register 2
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fields:
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- name: EXTI
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description: EXTI x configuration (x = 4 to 7)
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bit_offset: 0
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bit_size: 4
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array:
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len: 4
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stride: 4
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fieldset/FPUIMR:
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description: SBS FPU interrupt mask register.
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fields:
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- name: FPU_IE
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description: 'FPU interrupt enable Set and cleared by software to enable the Cortex-M7 FPU interrupts xxxxx1: Invalid operation interrupt enabled (xxxxx0 to disable) xxxx1x: Divide-by-zero interrupt enabled (xxxx0x to disable) xxx1xx: Underflow interrupt enabled (xxx0xx to disable) xx1xxx: Overflow interrupt enabled (xx0xxx to disable) x1xxxx: Input denormal interrupt enabled (x0xxxx to disable) 1xxxxx: Inexact interrupt enabled (0xxxxx to disable), disabled by default.'
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bit_offset: 0
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bit_size: 6
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fieldset/HDPLCR:
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description: SBS hide protection control register.
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fields:
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- name: INCR_HDPL
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description: increment HDPL Write 0x6A to increment device HDPL by one. After a write, the register value reverts to its default value (0xB4).
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bit_offset: 0
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bit_size: 8
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fieldset/HDPLSR:
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description: SBS hide protection status register.
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fields:
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- name: HDPL
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description: 'hide protection level This bitfield returns the current HDPL of the device. 0x6F and other codes: HDPL3, corresponding to non-boot application. Note: The device state (open/close) is defined in FLASH_NVSTATER register of the embedded Flash memory.'
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bit_offset: 0
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bit_size: 8
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enum: HDPL
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fieldset/MESR:
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description: SBS memory erase status register.
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fields:
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- name: MEF
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description: 'memory erase flag This bit is set by hardware when BKPRAM and PKA SRAM erase is ongoing after a POWER ON reset or one tamper event (see Section 50: Tamper and backup registers (TAMP) for details). This bit is cleared when the erase is done.'
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bit_offset: 0
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bit_size: 1
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fieldset/PMCR:
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description: SBS product mode and configuration register.
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fields:
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- name: FMPLUS_PB6
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description: Fast-mode Plus on PB(6).
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bit_offset: 4
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bit_size: 1
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- name: FMPLUS_PB7
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description: Fast-mode Plus on PB(7).
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bit_offset: 5
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bit_size: 1
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- name: FMPLUS_PB8
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description: Fast-mode Plus on PB(8).
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bit_offset: 6
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bit_size: 1
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- name: FMPLUS_PB9
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description: Fast-mode Plus on PB(9).
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bit_offset: 7
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bit_size: 1
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- name: BOOSTEN
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description: booster enable Set this bit to reduce the THD of the analog switches when the supply voltage is below 2.7 V. guaranteeing the same performance as with the full voltage range. To avoid current consumption due to booster activation when V<sub>DDA</sub> < 2.7 V and V<sub>DD</sub> > 2.7 V, V<sub>DD</sub> can be selected as supply voltage for analog switches by setting BOOSTVDDSEL bit in SBS_PMCR. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption.
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bit_offset: 8
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bit_size: 1
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- name: BOOSTVDDSEL
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description: booster V<sub>DD</sub> selection This bit selects the analog switch supply voltage, between V<sub>DD</sub>, V<sub>DDA</sub> and booster. To avoid current consumption due to booster activation when V<sub>DDA</sub> < 2.7 V and V<sub>DD</sub> > 2.7 V, V<sub>DD</sub> can be selected as supply voltage for analog switches. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption. When both V<sub>DD and </sub>V<sub>DDA</sub> are below 2.7 V, the booster is still needed to obtain full AC performances from the I/O analog switches.
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bit_offset: 9
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bit_size: 1
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- name: ETH_SEL_PHY
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description: Ethernet PHY interface selection.
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bit_offset: 21
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bit_size: 3
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enum: ETH_SEL_PHY
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- name: AXIRAM_WS
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description: AXIRAM wait state Set this bit to add one wait state to all AXIRAMs when ECC = 0. When ECC = 1 there is one wait state by default.
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bit_offset: 28
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bit_size: 1
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enum: AXIRAM_WS
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fieldset/RSSCMDR:
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description: SBS RSS command register.
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fields:
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- name: RSSCMD
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description: RSS command The application can use this bitfield to pass on a command to the RSS, executed at the next reset.
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bit_offset: 0
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bit_size: 16
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enum/AXIRAM_WS:
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bit_size: 1
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variants:
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- name: Ws0
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description: No wait state added when accessing any AXIRAM with ECC = 0.
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value: 0
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- name: Ws1
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description: One wait state added when accessing any AXIRAM with ECC = 0. In this case, Fmax = 500 MHz is not guaranteed. (TBC).
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value: 1
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enum/DBGCFG_LOCK:
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bit_size: 8
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variants:
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- name: Unlock
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description: Writes to SBS_DBGCR allowed (default).
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value: 180
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enum/DBG_AUTH_HDPL:
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bit_size: 8
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variants:
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- name: HDPL1
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description: HDPL1.
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value: 81
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- name: HDPL3
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description: HDPL3.
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value: 111
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- name: HDPL2
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description: HDPL2.
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value: 138
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enum/ETH_SEL_PHY:
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bit_size: 3
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variants:
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- name: MII_GMII
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description: GMII or MII
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value: 0
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- name: RMII
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description: RMII
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value: 4
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enum/HDPL:
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bit_size: 8
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variants:
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- name: HDPL1
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description: HDPL1.
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value: 81
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- name: HDPL2
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description: HDPL2.
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value: 138
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- name: HDPL0
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description: HDPL0, corresponding to ST-RSS (default when device is close).
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value: 180
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