stm32-data/data/registers/cryp_v4.yaml

block/CRYP:
  description: Cryptographic processor.
  items:
  - name: CR
    description: control register.
    byte_offset: 0
    fieldset: CR
  - name: SR
    description: status register.
    byte_offset: 4
    access: Read
    fieldset: SR
  - name: DIN
    description: data input register.
    byte_offset: 8
  - name: DOUT
    description: data output register.
    byte_offset: 12
    access: Read
  - name: DMACR
    description: DMA control register.
    byte_offset: 16
    fieldset: DMACR
  - name: IMSCR
    description: interrupt mask set/clear register.
    byte_offset: 20
    fieldset: IMSCR
  - name: RISR
    description: raw interrupt status register.
    byte_offset: 24
    access: Read
    fieldset: RISR
  - name: MISR
    description: masked interrupt status register.
    byte_offset: 28
    access: Read
    fieldset: MISR
  - name: KEY
    description: Cluster KEY%s, containing K?LR, K?RR.
    array:
      len: 4
      stride: 8
    byte_offset: 32
    block: KEY
  - name: INIT
    description: Cluster INIT%s, containing IV?LR, IV?RR.
    array:
      len: 2
      stride: 8
    byte_offset: 64
    block: INIT
  - name: CSGCMCCMR
    description: context swap register.
    array:
      len: 8
      stride: 4
    byte_offset: 80
  - name: CSGCMR
    description: context swap register.
    array:
      len: 8
      stride: 4
    byte_offset: 112
block/INIT:
  description: Cluster INIT%s, containing IV?LR, IV?RR.
  items:
  - name: IVLR
    description: initialization vector registers.
    byte_offset: 0
  - name: IVRR
    description: initialization vector registers.
    byte_offset: 4
block/KEY:
  description: Cluster KEY%s, containing K?LR, K?RR.
  items:
  - name: KLR
    description: key registers.
    byte_offset: 0
    access: Write
  - name: KRR
    description: key registers.
    byte_offset: 4
    access: Write
fieldset/CR:
  description: control register.
  fields:
  - name: ALGODIR
    description: Algorithm direction.
    bit_offset: 2
    bit_size: 1
  - name: ALGOMODE0
    description: Algorithm mode.
    bit_offset: 3
    bit_size: 3
  - name: DATATYPE
    description: Data type selection.
    bit_offset: 6
    bit_size: 2
  - name: KEYSIZE
    description: Key size selection (AES mode only).
    bit_offset: 8
    bit_size: 2
  - name: FFLUSH
    description: FIFO flush.
    bit_offset: 14
    bit_size: 1
  - name: CRYPEN
    description: Cryptographic processor enable.
    bit_offset: 15
    bit_size: 1
  - name: GCM_CCMPH
    description: GCM_CCMPH.
    bit_offset: 16
    bit_size: 2
  - name: ALGOMODE3
    description: ALGOMODE.
    bit_offset: 19
    bit_size: 1
  - name: NPBLB
    description: Number of Padding Bytes in Last Block of payload.
    bit_offset: 20
    bit_size: 4
  - name: KMOD
    description: 'Key mode selection This bitfield defines how the CRYP key can be used by the application. KEYSIZE must be correctly initialized when setting KMOD[1:0] different from zero. Others: Reserved Attempts to write the bitfield are ignored when BUSY is set.'
    bit_offset: 24
    bit_size: 2
    enum: KMOD
  - name: IPRST
    description: CRYP peripheral software reset Setting the bit resets the CRYP peripheral, putting all registers to their default values, except the IPRST bit itself. This bit must be kept cleared while writing any configuration registers.
    bit_offset: 31
    bit_size: 1
fieldset/DMACR:
  description: DMA control register.
  fields:
  - name: DIEN
    description: DMA input enable.
    bit_offset: 0
    bit_size: 1
  - name: DOEN
    description: DMA output enable.
    bit_offset: 1
    bit_size: 1
fieldset/IMSCR:
  description: interrupt mask set/clear register.
  fields:
  - name: INIM
    description: Input FIFO service interrupt mask.
    bit_offset: 0
    bit_size: 1
  - name: OUTIM
    description: Output FIFO service interrupt mask.
    bit_offset: 1
    bit_size: 1
fieldset/MISR:
  description: masked interrupt status register.
  fields:
  - name: INMIS
    description: Input FIFO service masked interrupt status.
    bit_offset: 0
    bit_size: 1
  - name: OUTMIS
    description: Output FIFO service masked interrupt status.
    bit_offset: 1
    bit_size: 1
fieldset/RISR:
  description: raw interrupt status register.
  fields:
  - name: INRIS
    description: Input FIFO service raw interrupt status.
    bit_offset: 0
    bit_size: 1
  - name: OUTRIS
    description: Output FIFO service raw interrupt status.
    bit_offset: 1
    bit_size: 1
fieldset/SR:
  description: status register.
  fields:
  - name: IFEM
    description: Input FIFO empty.
    bit_offset: 0
    bit_size: 1
  - name: IFNF
    description: Input FIFO not full.
    bit_offset: 1
    bit_size: 1
  - name: OFNE
    description: Output FIFO not empty.
    bit_offset: 2
    bit_size: 1
  - name: OFFU
    description: Output FIFO full.
    bit_offset: 3
    bit_size: 1
  - name: BUSY
    description: Busy bit.
    bit_offset: 4
    bit_size: 1
  - name: KERF
    description: 'Key error flag This read-only bit is set by hardware when key information failed to load into key registers. KERF is triggered upon any of the following errors: CRYP_KxR/LR register write does not respect the correct order (refer to Section 60.4.16: CRYP key registers for details). CRYP fails to load the key shared by SAES peripheral (KMOD = 0x2). KERF must be cleared by the application software, otherwise KEYVALID cannot be set. It can be done through IPRST bit of CRYP_CR, or when a correct key writing sequence starts.'
    bit_offset: 6
    bit_size: 1
  - name: KEYVALID
    description: 'Key valid flag This read-only bit is set by hardware when the key of size defined by KEYSIZE is loaded in CRYP_KxR/LR key registers. The CRYPEN bit can only be set when KEYVALID is set. In normal mode when KMOD[1:0] is at zero, the key must be written in the key registers in the correct sequence, otherwise the KERF flag is set and KEYVALID remains cleared. When KMOD[1:0] is different from zero, the BUSY flag is automatically set by CRYP. When the key is loaded successfully, BUSY is cleared and KEYVALID set. Upon an error, KERF is set, BUSY cleared and KEYVALID remains cleared. If set, KERF must be cleared, otherwise KEYVALID cannot be set. For further information on key loading, refer to Section 60.4.16: CRYP key registers.'
    bit_offset: 7
    bit_size: 1
enum/KMOD:
  bit_size: 2
  variants:
  - name: Normal
    description: Normal-key mode. Key registers are freely usable.
    value: 0
  - name: Shared
    description: Shared-key mode. If shared-key mode is properly initialized in SAES peripheral, the CRYP peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in CRYP key registers when BUSY bit is cleared and KEYVALID is set in the CRYP_SR register. Key error flag KERF is set otherwise in the CRYP_SR register.
    value: 2