diff --git a/data/dmamux/H7RS_GPDMA.yaml b/data/dmamux/H7RS_GPDMA.yaml
new file mode 100644
index 0000000..28e9183
--- /dev/null
+++ b/data/dmamux/H7RS_GPDMA.yaml
@@ -0,0 +1,110 @@
+ADC1: 0
+ADC2: 1
+CRYP_IN: 2
+CRYP_OUT: 3
+SAES_OUT: 4
+SAES_IN: 5
+HASH: 6
+TIM1_CC: 7
+TIM1_CC: 8
+TIM1_CC: 9
+TIM1_CC: 10
+TIM1_UP: 11
+TIM1_TRG: 12
+TIM1_COM: 13
+TIM2_CC: 14
+TIM2_CC: 15
+TIM2_CC: 16
+TIM2_CC: 17
+TIM2_UP: 18
+TIM2_TRG: 19
+TIM3_CC: 20
+TIM3_CC: 21
+TIM3_CC: 22
+TIM3_CC: 23
+TIM3_UP: 24
+TIM3_TRG: 25
+TIM4_CC: 26
+TIM4_CC: 27
+TIM4_CC: 28
+TIM4_CC: 29
+TIM4_UP: 30
+TIM4_TRG: 31
+TIM5_CC: 32
+TIM5_CC: 33
+TIM5_CC: 34
+TIM5_CC: 35
+TIM5_UP: 36
+TIM5_TRG: 37
+TIM6_UP: 38
+TIM7_UP: 39
+TIM15_CC: 40
+TIM15_CC: 41
+TIM15_UP: 42
+TIM15_TRG: 43
+TIM15_COM: 44
+TIM16_CC: 45
+TIM16_UP: 46
+TIM16_COM: 47
+TIM17_CC: 48
+TIM17_UP: 49
+TIM17_COM: 50
+SPI1_RX: 51
+SPI1_TX: 52
+SPI2_RX: 53
+SPI2_TX: 54
+SPI3_RX: 55
+SPI3_TX: 56
+SPI4_RX: 57
+SPI4_TX: 58
+SPI5_RX: 59
+SPI5_TX: 60
+SPI6_RX: 61
+SPI6_TX: 62
+SAI1_A: 63
+SAI1_B: 64
+SAI2_A: 65
+SAI2_B: 66
+I2C1_RX: 67
+I2C1_TX: 68
+I2C2_RX: 69
+I2C2_TX: 70
+I2C3_RX: 71
+I2C3_TX: 72
+USART1_RX: 73
+USART1_TX: 74
+USART2_RX: 75
+USART2_TX: 76
+USART3_RX: 77
+USART3_TX: 78
+UART4_RX: 79
+UART4_TX: 80
+UART5_RX: 81
+UART5_TX: 82
+UART7_RX: 83
+UART7_TX: 84
+UART8_RX: 85
+UART8_TX: 86
+CORDIC_READ: 87
+CORDIC_WRITE: 88
+LPTIM1_IC1: 89
+LPTIM1_IC2: 90
+LPTIM1_UE: 91
+LPTIM2_IC1: 92
+LPTIM2_IC2: 93
+LPTIM2_UE: 94
+SPDIFRX_DAT: 95
+SPDIFRX_CTRL: 96
+ADF1_FLT0: 97
+UCPD_TX: 98
+UCPD_RX: 99
+PSSI: 100
+LPUART1_RX: 101
+LPUART1_TX: 102
+LPTIM3_IC1: 103
+LPTIM3_IC2: 104
+LPTIM3_UE: 105
+I3C1_RX: 106
+I3C1_TX: 107
+I3C1_TC: 108
+I3C1_RS: 109
diff --git a/data/dmamux/H7RS_HPDMA.yaml b/data/dmamux/H7RS_HPDMA.yaml
new file mode 100644
index 0000000..ca5c3f3
--- /dev/null
+++ b/data/dmamux/H7RS_HPDMA.yaml
@@ -0,0 +1,20 @@
+JPEG_RX: 0
+JPEG_TX: 1
+XSPI1_RX: 2
+XSPI2_RX: 3
+SPI3_RX: 4
+SPI3_TX: 5
+SPI4_RX: 6
+SPI4_TX: 7
+ADC1: 8
+ADC2: 9
+ADF1_FLT0: 10
+UART4_RX: 11
+UART4_TX: 12
+UART5_RX: 13
+UART5_TX: 14
+UART7_RX: 15
+UART7_TX: 16
+LPTIM2_IC1: 17
+LPTIM2_IC2: 18
+LPTIM2_UE: 19
diff --git a/data/registers/cryp_v4.yaml b/data/registers/cryp_v4.yaml
new file mode 100644
index 0000000..08c5850
--- /dev/null
+++ b/data/registers/cryp_v4.yaml
@@ -0,0 +1,215 @@
+block/CRYP:
+  description: Cryptographic processor.
+  items:
+  - name: CR
+    description: control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: status register.
+    byte_offset: 4
+    access: Read
+    fieldset: SR
+  - name: DIN
+    description: data input register.
+    byte_offset: 8
+  - name: DOUT
+    description: data output register.
+    byte_offset: 12
+    access: Read
+  - name: DMACR
+    description: DMA control register.
+    byte_offset: 16
+    fieldset: DMACR
+  - name: IMSCR
+    description: interrupt mask set/clear register.
+    byte_offset: 20
+    fieldset: IMSCR
+  - name: RISR
+    description: raw interrupt status register.
+    byte_offset: 24
+    access: Read
+    fieldset: RISR
+  - name: MISR
+    description: masked interrupt status register.
+    byte_offset: 28
+    access: Read
+    fieldset: MISR
+  - name: KEY
+    description: Cluster KEY%s, containing K?LR, K?RR.
+    array:
+      len: 4
+      stride: 8
+    byte_offset: 32
+    block: KEY
+  - name: INIT
+    description: Cluster INIT%s, containing IV?LR, IV?RR.
+    array:
+      len: 2
+      stride: 8
+    byte_offset: 64
+    block: INIT
+  - name: CSGCMCCMR
+    description: context swap register.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 80
+  - name: CSGCMR
+    description: context swap register.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 112
+block/INIT:
+  description: Cluster INIT%s, containing IV?LR, IV?RR.
+  items:
+  - name: IVLR
+    description: initialization vector registers.
+    byte_offset: 0
+  - name: IVRR
+    description: initialization vector registers.
+    byte_offset: 4
+block/KEY:
+  description: Cluster KEY%s, containing K?LR, K?RR.
+  items:
+  - name: KLR
+    description: key registers.
+    byte_offset: 0
+    access: Write
+  - name: KRR
+    description: key registers.
+    byte_offset: 4
+    access: Write
+fieldset/CR:
+  description: control register.
+  fields:
+  - name: ALGODIR
+    description: Algorithm direction.
+    bit_offset: 2
+    bit_size: 1
+  - name: ALGOMODE0
+    description: Algorithm mode.
+    bit_offset: 3
+    bit_size: 3
+  - name: DATATYPE
+    description: Data type selection.
+    bit_offset: 6
+    bit_size: 2
+  - name: KEYSIZE
+    description: Key size selection (AES mode only).
+    bit_offset: 8
+    bit_size: 2
+  - name: FFLUSH
+    description: FIFO flush.
+    bit_offset: 14
+    bit_size: 1
+  - name: CRYPEN
+    description: Cryptographic processor enable.
+    bit_offset: 15
+    bit_size: 1
+  - name: GCM_CCMPH
+    description: GCM_CCMPH.
+    bit_offset: 16
+    bit_size: 2
+  - name: ALGOMODE3
+    description: ALGOMODE.
+    bit_offset: 19
+    bit_size: 1
+  - name: NPBLB
+    description: Number of Padding Bytes in Last Block of payload.
+    bit_offset: 20
+    bit_size: 4
+  - name: KMOD
+    description: 'Key mode selection This bitfield defines how the CRYP key can be used by the application. KEYSIZE must be correctly initialized when setting KMOD[1:0] different from zero. Others: Reserved Attempts to write the bitfield are ignored when BUSY is set.'
+    bit_offset: 24
+    bit_size: 2
+    enum: KMOD
+  - name: IPRST
+    description: CRYP peripheral software reset Setting the bit resets the CRYP peripheral, putting all registers to their default values, except the IPRST bit itself. This bit must be kept cleared while writing any configuration registers.
+    bit_offset: 31
+    bit_size: 1
+fieldset/DMACR:
+  description: DMA control register.
+  fields:
+  - name: DIEN
+    description: DMA input enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: DOEN
+    description: DMA output enable.
+    bit_offset: 1
+    bit_size: 1
+fieldset/IMSCR:
+  description: interrupt mask set/clear register.
+  fields:
+  - name: INIM
+    description: Input FIFO service interrupt mask.
+    bit_offset: 0
+    bit_size: 1
+  - name: OUTIM
+    description: Output FIFO service interrupt mask.
+    bit_offset: 1
+    bit_size: 1
+fieldset/MISR:
+  description: masked interrupt status register.
+  fields:
+  - name: INMIS
+    description: Input FIFO service masked interrupt status.
+    bit_offset: 0
+    bit_size: 1
+  - name: OUTMIS
+    description: Output FIFO service masked interrupt status.
+    bit_offset: 1
+    bit_size: 1
+fieldset/RISR:
+  description: raw interrupt status register.
+  fields:
+  - name: INRIS
+    description: Input FIFO service raw interrupt status.
+    bit_offset: 0
+    bit_size: 1
+  - name: OUTRIS
+    description: Output FIFO service raw interrupt status.
+    bit_offset: 1
+    bit_size: 1
+fieldset/SR:
+  description: status register.
+  fields:
+  - name: IFEM
+    description: Input FIFO empty.
+    bit_offset: 0
+    bit_size: 1
+  - name: IFNF
+    description: Input FIFO not full.
+    bit_offset: 1
+    bit_size: 1
+  - name: OFNE
+    description: Output FIFO not empty.
+    bit_offset: 2
+    bit_size: 1
+  - name: OFFU
+    description: Output FIFO full.
+    bit_offset: 3
+    bit_size: 1
+  - name: BUSY
+    description: Busy bit.
+    bit_offset: 4
+    bit_size: 1
+  - name: KERF
+    description: 'Key error flag This read-only bit is set by hardware when key information failed to load into key registers. KERF is triggered upon any of the following errors: CRYP_KxR/LR register write does not respect the correct order (refer to Section 60.4.16: CRYP key registers for details). CRYP fails to load the key shared by SAES peripheral (KMOD = 0x2). KERF must be cleared by the application software, otherwise KEYVALID cannot be set. It can be done through IPRST bit of CRYP_CR, or when a correct key writing sequence starts.'
+    bit_offset: 6
+    bit_size: 1
+  - name: KEYVALID
+    description: 'Key valid flag This read-only bit is set by hardware when the key of size defined by KEYSIZE is loaded in CRYP_KxR/LR key registers. The CRYPEN bit can only be set when KEYVALID is set. In normal mode when KMOD[1:0] is at zero, the key must be written in the key registers in the correct sequence, otherwise the KERF flag is set and KEYVALID remains cleared. When KMOD[1:0] is different from zero, the BUSY flag is automatically set by CRYP. When the key is loaded successfully, BUSY is cleared and KEYVALID set. Upon an error, KERF is set, BUSY cleared and KEYVALID remains cleared. If set, KERF must be cleared, otherwise KEYVALID cannot be set. For further information on key loading, refer to Section 60.4.16: CRYP key registers.'
+    bit_offset: 7
+    bit_size: 1
+enum/KMOD:
+  bit_size: 2
+  variants:
+  - name: Normal
+    description: Normal-key mode. Key registers are freely usable.
+    value: 0
+  - name: Shared
+    description: Shared-key mode. If shared-key mode is properly initialized in SAES peripheral, the CRYP peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in CRYP key registers when BUSY bit is cleared and KEYVALID is set in the CRYP_SR register. Key error flag KERF is set otherwise in the CRYP_SR register.
+    value: 2
\ No newline at end of file
diff --git a/data/registers/flash_h7rs.yaml b/data/registers/flash_h7rs.yaml
new file mode 100644
index 0000000..ffa2410
--- /dev/null
+++ b/data/registers/flash_h7rs.yaml
@@ -0,0 +1,882 @@
+block/FLASH:
+  description: Embedded Flash memory.
+  items:
+  - name: ACR
+    description: Access control register.
+    byte_offset: 0
+    fieldset: ACR
+  - name: KEYR
+    description: FLASH control key register.
+    byte_offset: 4
+    fieldset: KEYR
+  - name: CR
+    description: FLASH control register.
+    byte_offset: 16
+    fieldset: CR
+  - name: SR
+    description: FLASH status register.
+    byte_offset: 20
+    fieldset: SR
+  - name: FCR
+    description: FLASH status register.
+    byte_offset: 24
+    fieldset: FCR
+  - name: IER
+    description: FLASH interrupt enable register.
+    byte_offset: 32
+    fieldset: IER
+  - name: ISR
+    description: FLASH interrupt status register.
+    byte_offset: 36
+    fieldset: ISR
+  - name: ICR
+    description: FLASH interrupt clear register.
+    byte_offset: 40
+    fieldset: ICR
+  - name: CRCCR
+    description: FLASH CRC control register.
+    byte_offset: 48
+    fieldset: CRCCR
+  - name: CRCSADDR
+    description: FLASH CRC start address register.
+    byte_offset: 52
+    fieldset: CRCSADDR
+  - name: CRCEADDR
+    description: FLASH CRC end address register.
+    byte_offset: 56
+    fieldset: CRCEADDR
+  - name: CRCDATAR
+    description: FLASH CRC data register.
+    byte_offset: 60
+    fieldset: CRCDATAR
+  - name: ECCSFADDR
+    description: FLASH ECC single error fail address.
+    byte_offset: 64
+    fieldset: ECCSFADDR
+  - name: ECCDFADDR
+    description: FLASH ECC double error fail address.
+    byte_offset: 68
+    fieldset: ECCDFADDR
+  - name: OPTKEYR
+    description: FLASH options key register.
+    byte_offset: 256
+    fieldset: OPTKEYR
+  - name: OPTCR
+    description: FLASH options control register.
+    byte_offset: 260
+    fieldset: OPTCR
+  - name: OPTISR
+    description: FLASH options interrupt status register.
+    byte_offset: 264
+    fieldset: OPTISR
+  - name: OPTICR
+    description: FLASH options interrupt clear register.
+    byte_offset: 268
+    fieldset: OPTICR
+  - name: OBKCR
+    description: FLASH option byte key control register.
+    byte_offset: 272
+    fieldset: OBKCR
+  - name: OBKDR
+    description: FLASH option bytes key data register 0.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 280
+  - name: NVSR
+    description: FLASH non-volatile status register.
+    byte_offset: 512
+    fieldset: NVSR
+  - name: NVSRP
+    description: FLASH security status register programming.
+    byte_offset: 516
+    fieldset: NVSRP
+  - name: ROTSR
+    description: FLASH RoT status register.
+    byte_offset: 520
+    fieldset: ROTSR
+  - name: ROTSRP
+    description: FLASH RoT status register programming.
+    byte_offset: 524
+    fieldset: ROTSRP
+  - name: OTPLSR
+    description: FLASH OTP lock status register.
+    byte_offset: 528
+    fieldset: OTPLSR
+  - name: OTPLSRP
+    description: FLASH OTP lock status register programming.
+    byte_offset: 532
+    fieldset: OTPLSRP
+  - name: WRPSR
+    description: FLASH write protection status register.
+    byte_offset: 536
+    fieldset: WRPSR
+  - name: WRPSRP
+    description: FLASH write protection status register programming.
+    byte_offset: 540
+    fieldset: WRPSRP
+  - name: HDPSR
+    description: FLASH hide protection status register.
+    byte_offset: 560
+    fieldset: HDPSR
+  - name: HDPSRP
+    description: FLASH hide protection status register programming.
+    byte_offset: 564
+    fieldset: HDPSRP
+  - name: EPOCHSR
+    description: FLASH epoch status register.
+    byte_offset: 592
+    fieldset: EPOCHSR
+  - name: EPOCHSRP
+    description: FLASH RoT status register programming.
+    byte_offset: 596
+    fieldset: EPOCHSRP
+  - name: OBW1SR
+    description: FLASH option byte word 1 status register.
+    byte_offset: 608
+    fieldset: OBW1SR
+  - name: OBW1SRP
+    description: FLASH option byte word 1 status register programming.
+    byte_offset: 612
+    fieldset: OBW1SRP
+  - name: OBW2SR
+    description: FLASH option byte word 2 status register.
+    byte_offset: 616
+    fieldset: OBW2SR
+  - name: OBW2SRP
+    description: FLASH option byte word 2 status register programming.
+    byte_offset: 620
+    fieldset: OBW2SRP
+fieldset/ACR:
+  description: Access control register.
+  fields:
+  - name: LATENCY
+    description: 'Read latency These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions. Please refer to Table 27 for details. ... Note: Embedded Flash does not verify that the configuration is correct.'
+    bit_offset: 0
+    bit_size: 4
+  - name: WRHIGHFREQ
+    description: 'Flash signal delay These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to Table 27 for details. Note: Embedded Flash does not verify that the configuration is correct.'
+    bit_offset: 4
+    bit_size: 2
+fieldset/CR:
+  description: FLASH control register.
+  fields:
+  - name: LOCK
+    description: Configuration lock bit When this bit is set write to all other bits in this register, and to FLASH_IER register, are ignored. Clearing this bit requires the correct write sequence to FLASH_KEYR register (see this register for details). If a wrong sequence is executed, or if the unlock sequence is performed twice, this bit remains locked until the next system reset. During the write access to set LOCK bit from 0 to 1, it is possible to change the other bits of this register.
+    bit_offset: 0
+    bit_size: 1
+  - name: PG
+    description: Internal buffer control bit Setting this bit enables internal buffer for write operations. This allows preparing program operations even if a sector or bank erase is ongoing. When PG is cleared, the internal buffer is disabled for write operations, and all the data stored in the buffer but not sent to the operation queue are lost.
+    bit_offset: 1
+    bit_size: 1
+  - name: SER
+    description: 'Sector erase request Setting this bit requests a sector erase. Write protection error is triggered when a sector erase is required on at least one protected sector. BER has a higher priority than SER: if both bits are set, the embedded Flash memory executes a bank erase.'
+    bit_offset: 2
+    bit_size: 1
+  - name: BER
+    description: 'Bank erase request Setting this bit requests a bank erase operation (user Flash memory only). Write protection error is triggered when a bank erase is required and some sectors are protected. BER has a higher priority than SER: if both are set, the embedded Flash memory executes a bank erase.'
+    bit_offset: 3
+    bit_size: 1
+  - name: FW
+    description: 'Force write This bit forces a write operation even if the write buffer is not full. In this case all bits not written are set by hardware. The embedded Flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it will lead to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively).'
+    bit_offset: 4
+    bit_size: 1
+  - name: START
+    description: Erase start control bit This bit is used to start a sector erase or a bank erase operation. The embedded Flash memory resets START when the corresponding operation has been acknowledged. The user application cannot access any embedded Flash memory register until the operation is acknowledged.
+    bit_offset: 5
+    bit_size: 1
+  - name: SSN
+    description: Sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). ...
+    bit_offset: 6
+    bit_size: 2
+  - name: PG_OTP
+    description: Program Enable for OTP Area Set this bit to enable write operations to OTP area.
+    bit_offset: 16
+    bit_size: 1
+  - name: CRC_EN
+    description: CRC enable Setting this bit enables the CRC calculation. CRC_EN does not start CRC calculation but enables CRC configuration through FLASH_CRCCR register. When CRC calculation is performed it can be disabled by clearing CRC_EN bit. Doing so sets CRCDATA to 0x0, clears CRC configuration and resets the content of FLASH_CRCDATAR register.
+    bit_offset: 17
+    bit_size: 1
+  - name: ALL_BANKS
+    description: All banks select bit When this bit is set the erase is done on all Flash Memory sectors. ALL_BANKS is used only if a bank erase is required (BER=1). In all others operations, this control bit is ignored.
+    bit_offset: 24
+    bit_size: 1
+fieldset/CRCCR:
+  description: FLASH CRC control register.
+  fields:
+  - name: CRC_SECT
+    description: CRC sector number CRC_SECT is used to select one user Flash sectors to be added to the list of sectors on which the CRC is calculated. The CRC can be computed either between two addresses (using registers FLASH_CRCSADDR and FLASH_CRCEADDR) or on a list of sectors using this register. If this latter option is selected, it is possible to add a sector to the list of sectors by programming the sector number in CRC_SECT and then setting ADD_SECT bit. The list of sectors can be erased either by setting CLEAN_SECT bit or by disabling the CRC computation. ...
+    bit_offset: 0
+    bit_size: 2
+  - name: CRC_BY_SECT
+    description: CRC sector mode select bit When this bit is set the CRC calculation is performed at sector level, on the sectors present in the list of sectors. To add a sector to this list, use ADD_SECT and CRC_SECT bits. To clean the list, use CLEAN_SECT bit. When CRC_BY_SECT is cleared the CRC calculation is performed on all addresses defined between start and end addresses defined in FLASH_CRCSADDR and FLASH_CRCEADDR registers.
+    bit_offset: 9
+    bit_size: 1
+  - name: ADD_SECT
+    description: CRC sector select bit When this bit is set the sector whose number is written in CRC_SECT is added to the list of sectors on which the CRC is calculated.
+    bit_offset: 10
+    bit_size: 1
+  - name: CLEAN_SECT
+    description: CRC sector list clear bit When this bit is set the list of sectors on which the CRC is calculated is cleared.
+    bit_offset: 11
+    bit_size: 1
+  - name: START_CRC
+    description: CRC start bit START_CRC bit triggers a CRC calculation using the current configuration. No CRC calculation can launched when an option byte change operation is ongoing because all read accesses to embedded Flash memory registers are put on hold until the option byte change operation has completed. This bit is cleared when CRC computation starts.
+    bit_offset: 16
+    bit_size: 1
+  - name: CLEAN_CRC
+    description: CRC clear bit Setting CLEAN_CRC to 1 clears the current CRC result stored in the FLASH_CRCDATAR register.
+    bit_offset: 17
+    bit_size: 1
+  - name: CRC_BURST
+    description: CRC burst size CRC_BURST bits set the size of the bursts that are generated by the CRC calculation unit. A Flash word is 128-bit.
+    bit_offset: 20
+    bit_size: 2
+    enum: CRC_BURST
+  - name: ALL_SECT
+    description: All sectors selection When this bit is set all the sectors in user Flash are added to list of sectors on which the CRC shall be calculated. This bit is cleared when CRC computation starts.
+    bit_offset: 24
+    bit_size: 1
+fieldset/CRCDATAR:
+  description: FLASH CRC data register.
+  fields:
+  - name: CRC_DATA
+    description: CRC result This bitfield contains the result of the last CRC calculation. The value is valid only when CRC calculation completed (CRCENDF is set in FLASH_ISR register). CRC_DATA is cleared when CRC_EN is cleared in FLASH_CR register (CRC disabled), or when CLEAN_CRC bit is set in FLASH_CRCCR register.
+    bit_offset: 0
+    bit_size: 32
+fieldset/CRCEADDR:
+  description: FLASH CRC end address register.
+  fields:
+  - name: CRC_END_ADDR
+    description: CRC end address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the Flash word starting the last burst of the CRC calculation. The burst size is defined in CRC_BURST of FLASH_CRCCR register. The least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank.
+    bit_offset: 6
+    bit_size: 11
+fieldset/CRCSADDR:
+  description: FLASH CRC start address register.
+  fields:
+  - name: CRC_START_ADDR
+    description: CRC start address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the first Flash word to use for the CRC calculation, done burst by burst. CRC computation starts at an address aligned to the burst size defined in CRC_BURST of FLASH_CRCCR register. Hence least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank.
+    bit_offset: 6
+    bit_size: 11
+fieldset/ECCDFADDR:
+  description: FLASH ECC double error fail address.
+  fields:
+  - name: DED_FADD
+    description: ECC double error detection fail address When a double ECC detection occurs during a read operation, the DED_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when the DBECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC double error detection error is saved in this register.
+    bit_offset: 0
+    bit_size: 32
+fieldset/ECCSFADDR:
+  description: FLASH ECC single error fail address.
+  fields:
+  - name: SEC_FADD
+    description: ECC single error correction fail address When a single ECC error correction occurs during a read operation, the SEC_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when SNECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC single error correction error is saved in this register.
+    bit_offset: 0
+    bit_size: 32
+fieldset/EPOCHSR:
+  description: FLASH epoch status register.
+  fields:
+  - name: EPOCH
+    description: Epoch This value is distributed by hardware to the SAES peripheral.
+    bit_offset: 0
+    bit_size: 24
+fieldset/EPOCHSRP:
+  description: FLASH RoT status register programming.
+  fields:
+  - name: EPOCH
+    description: Epoch programming Write to change corresponding bits in FLASH_EPOCHSR register.
+    bit_offset: 0
+    bit_size: 24
+fieldset/FCR:
+  description: FLASH status register.
+  fields:
+  - name: RCHECKF
+    description: Root code check flag clear Set this bit to clear RCHECKF bit in FLASH_SR.
+    bit_offset: 25
+    bit_size: 1
+fieldset/HDPSR:
+  description: FLASH hide protection status register.
+  fields:
+  - name: HDP_AREA_START
+    description: Hide protection user Flash area start This option sets the start address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END<HDP_AREA_START no sectors are protected.
+    bit_offset: 0
+    bit_size: 9
+  - name: HDP_AREA_END
+    description: Hide protection user Flash area end This option sets the end address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END<HDP_AREA_START no sectors are protected.
+    bit_offset: 16
+    bit_size: 9
+fieldset/HDPSRP:
+  description: FLASH hide protection status register programming.
+  fields:
+  - name: HDP_AREA_START
+    description: Hide protection user Flash area start programming Write to change corresponding option byte bits in FLASH_HDPSR. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END<HDP_AREA_START no sectors are protected.
+    bit_offset: 0
+    bit_size: 9
+  - name: HDP_AREA_END
+    description: Hide protection user Flash area end programming Write to change corresponding option byte bits in FLASH_HDPSR. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END<HDP_AREA_START no sectors are protected.
+    bit_offset: 16
+    bit_size: 9
+fieldset/ICR:
+  description: FLASH interrupt clear register.
+  fields:
+  - name: EOPF
+    description: End-of-program flag clear Setting this bit clears EOPF flag in FLASH_ISR register.
+    bit_offset: 16
+    bit_size: 1
+  - name: WRPERRF
+    description: Write protection error flag clear Setting this bit clears WRPERRF flag in FLASH_ISR register.
+    bit_offset: 17
+    bit_size: 1
+  - name: PGSERRF
+    description: Programming sequence error flag clear Setting this bit clears PGSERRF flag in FLASH_ISR register.
+    bit_offset: 18
+    bit_size: 1
+  - name: STRBERRF
+    description: Strobe error flag clear Setting this bit clears STRBERRF flag in FLASH_ISR register.
+    bit_offset: 19
+    bit_size: 1
+  - name: OBLERRF
+    description: Option byte loading error flag clear Setting this bit clears OBLERRF flag in FLASH_ISR register.
+    bit_offset: 20
+    bit_size: 1
+  - name: INCERRF
+    description: Inconsistency error flag clear Setting this bit clears INCERRF flag in FLASH_ISR register.
+    bit_offset: 21
+    bit_size: 1
+  - name: RDSERRF
+    description: Read security error flag clear Setting this bit clears RDSERRF flag in FLASH_ISR register.
+    bit_offset: 24
+    bit_size: 1
+  - name: SNECCERRF
+    description: ECC single error flag clear Setting this bit clears SNECCERRF flag in FLASH_ISR register. If the DBECCERRF flag of FLASH_ISR register is also cleared, FLASH_ECCFAR register is reset to zero as well.
+    bit_offset: 25
+    bit_size: 1
+  - name: DBECCERRF
+    description: ECC double error flag clear Setting this bit clears DBECCERRF flag in FLASH_ISR register. If the SNECCERRF flag of FLASH_ISR register is also cleared, FLASH_ECCFAR register is reset to zero as well.
+    bit_offset: 26
+    bit_size: 1
+  - name: CRCENDF
+    description: CRC end flag clear Setting this bit clears CRCENDF flag in FLASH_ISR register.
+    bit_offset: 27
+    bit_size: 1
+  - name: CRCRDERRF
+    description: CRC error flag clear Setting this bit clears CRCRDERRF flag in FLASH_ISR register.
+    bit_offset: 28
+    bit_size: 1
+fieldset/IER:
+  description: FLASH interrupt enable register.
+  fields:
+  - name: EOPIE
+    description: End-of-program interrupt control bit.
+    bit_offset: 16
+    bit_size: 1
+  - name: WRPERRIE
+    description: Write protection error interrupt enable bit.
+    bit_offset: 17
+    bit_size: 1
+  - name: PGSERRIE
+    description: Programming sequence error interrupt enable bit.
+    bit_offset: 18
+    bit_size: 1
+  - name: STRBERRIE
+    description: Strobe error interrupt enable bit.
+    bit_offset: 19
+    bit_size: 1
+  - name: OBLERRIE
+    description: Option byte loading error interrupt enable bit.
+    bit_offset: 20
+    bit_size: 1
+  - name: INCERRIE
+    description: Inconsistency error interrupt enable bit.
+    bit_offset: 21
+    bit_size: 1
+  - name: RDSERRIE
+    description: Read security error interrupt enable bit.
+    bit_offset: 24
+    bit_size: 1
+  - name: SNECCERRIE
+    description: ECC single correction error interrupt enable bit.
+    bit_offset: 25
+    bit_size: 1
+  - name: DBECCERRIE
+    description: ECC double detection error interrupt enable bit.
+    bit_offset: 26
+    bit_size: 1
+  - name: CRCENDIE
+    description: CRC end of calculation interrupt enable bit.
+    bit_offset: 27
+    bit_size: 1
+  - name: CRCRDERRIE
+    description: CRC read error interrupt enable bit.
+    bit_offset: 28
+    bit_size: 1
+fieldset/ISR:
+  description: FLASH interrupt status register.
+  fields:
+  - name: EOPF
+    description: End-of-program flag This bit is set when a programming operation completes. An interrupt is generated if the EOPIE is set. It is not necessary to reset EOPF before starting a new operation. Setting EOPF bit in FLASH_ICR register clears this bit.
+    bit_offset: 16
+    bit_size: 1
+  - name: WRPERRF
+    description: Write protection error flag This bit is set when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set. Setting WRPERRF bit in FLASH_ICR register clears this bit.
+    bit_offset: 17
+    bit_size: 1
+  - name: PGSERRF
+    description: Programming sequence error flag This bit is set when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set. Setting PGSERRF bit in FLASH_ICR register clears this bit.
+    bit_offset: 18
+    bit_size: 1
+  - name: STRBERRF
+    description: Strobe error flag This bit is set when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set. Setting STRBERRF bit in FLASH_ICR register clears this bit.
+    bit_offset: 19
+    bit_size: 1
+  - name: OBLERRF
+    description: Option byte loading error flag This bit is set when an error is found during the option byte loading sequence. An interrupt is generated if OBLERRIE is set. Setting OBLERRF bit in the FLASH_ICR register clears this bit.
+    bit_offset: 20
+    bit_size: 1
+  - name: INCERRF
+    description: Inconsistency error flag This bit is set when a inconsistency error occurs. An interrupt is generated if INCERRIE is set. Setting INCERRF bit in the FLASH_ICR register clears this bit.
+    bit_offset: 21
+    bit_size: 1
+  - name: RDSERRF
+    description: Read security error flag This bit is set when a read security error occurs (read access to hide protected area with incorrect hide protection level). An interrupt is generated if RDSERRIE is set. Setting RDSERRF bit in FLASH_ICR register clears this bit.
+    bit_offset: 24
+    bit_size: 1
+  - name: SNECCERRF
+    description: ECC single error flag This bit is set when an ECC single correction error occurs during a read operation. An interrupt is generated if SNECCERRIE is set. Setting SNECCERRF bit in FLASH_ICR register clears this bit.
+    bit_offset: 25
+    bit_size: 1
+  - name: DBECCERRF
+    description: ECC double error flag This bit is set when an ECC double detection error occurs during a read operation. An interrupt is generated if DBECCERRIE is set. Setting DBECCERRF bit in FLASH_ICR register clears this bit.
+    bit_offset: 26
+    bit_size: 1
+  - name: CRCENDF
+    description: CRC end flag This bit is set when the CRC computation has completed. An interrupt is generated if CRCENDIE is set. It is not necessary to reset CRCEND before restarting CRC computation. Setting CRCENDF bit in FLASH_ICR register clears this bit.
+    bit_offset: 27
+    bit_size: 1
+  - name: CRCRDERRF
+    description: CRC read error flag This bit is set when a word is found read protected during a CRC operation. An interrupt is generated if CRCRDIE is set. Setting CRCRDERRF bit in FLASH_ICR register clears this bit. This flag is valid only when CRCEND bit is set.
+    bit_offset: 28
+    bit_size: 1
+fieldset/KEYR:
+  description: FLASH control key register.
+  fields:
+  - name: CUKEY
+    description: 'Control unlock key Following values must be written to FLASH_KEYR consecutively to unlock FLASH_CR register: 1st key = 0x4567 0123 2nd key = 0xCDEF 89AB Reads to this register returns zero. If above sequence is wrong or performed twice, the FLASH_CR register is locked until the next system reset, and access to it generates a bus error.'
+    bit_offset: 0
+    bit_size: 32
+fieldset/NVSR:
+  description: FLASH non-volatile status register.
+  fields:
+  - name: NVSTATE
+    description: 'Non-volatile state others: invalid configuration.'
+    bit_offset: 0
+    bit_size: 8
+    enum: NVSR_NVSTATE
+fieldset/NVSRP:
+  description: FLASH security status register programming.
+  fields:
+  - name: NVSTATE
+    description: 'Non-volatile state programming Write to change corresponding bits in FLASH_NVSR register: Actual option byte change from close to open is triggered only after memory clear hardware process is confirmed. When NVSTATE=0xB4 (resp. 0x51) writing any other value than 0x51 (resp. 0xB4) triggers an option byte change error (OPTERRF).'
+    bit_offset: 0
+    bit_size: 8
+    enum: NVSRP_NVSTATE
+fieldset/OBKCR:
+  description: FLASH option byte key control register.
+  fields:
+  - name: OBKINDEX
+    description: Option byte key index This bitfield represents the index of the option byte key in a given hide protection level. Reading keys with index lower that 8, the value is not be available in OBKDRx registers. It is instead sent directly to SAES peripheral. All others keys can be read using OBKDRx registers. Up to 32 keys can be provisioned per hide protection level (0, 1 or 2), provided there is enough space left in the Flash to store them.
+    bit_offset: 0
+    bit_size: 5
+  - name: NEXTKL
+    description: 'Next key level 10 or 11: reserved.'
+    bit_offset: 8
+    bit_size: 2
+    enum: NEXTKL
+  - name: OBKSIZE
+    description: Option byte key size Application must use this bitfield to specify how many bits must be used for the new key. Embedded Flash ignores OBKSIZE during read of option keys because size is stored with the key.
+    bit_offset: 10
+    bit_size: 2
+    enum: OBKSIZE
+  - name: KEYPROG
+    description: Key program This bit must be set to write option byte keys (keys are read otherwise).
+    bit_offset: 14
+    bit_size: 1
+  - name: KEYSTART
+    description: Key option start This bit is used to start the option byte key operation defined by the PROG bit. The embedded Flash memory resets START when the corresponding operation has been acknowledged.
+    bit_offset: 15
+    bit_size: 1
+fieldset/OBW1SR:
+  description: FLASH option byte word 1 status register.
+  fields:
+  - name: BOR_LEV
+    description: Brownout level These bits reflects the power level that generates a system reset.
+    bit_offset: 2
+    bit_size: 2
+    enum: BOR_LEV
+  - name: IWDG_HW
+    description: Independent watchdog HW Control.
+    bit_offset: 4
+    bit_size: 1
+  - name: NRST_STOP
+    description: Reset on stop mode.
+    bit_offset: 6
+    bit_size: 1
+  - name: NRST_STBY
+    description: Reset on standby mode.
+    bit_offset: 7
+    bit_size: 1
+  - name: OCTO1_HSLV
+    description: XSPIM_P1 High-Speed at Low-Voltage.
+    bit_offset: 8
+    bit_size: 1
+  - name: OCTO2_HSLV
+    description: XSPIM_P2 High-Speed at Low-Voltage.
+    bit_offset: 9
+    bit_size: 1
+  - name: IWDG_FZ_STOP
+    description: IWDG stop mode freeze When set the independent watchdog IWDG is frozen in system Stop mode.
+    bit_offset: 17
+    bit_size: 1
+  - name: IWDG_FZ_SDBY
+    description: IWDG standby mode freeze When set the independent watchdog IWDG is frozen in system Standby mode.
+    bit_offset: 18
+    bit_size: 1
+  - name: PERSO_OK
+    description: Personalization OK This bit is set on STMicroelectronics production line.
+    bit_offset: 28
+    bit_size: 1
+  - name: VDDIO_HSLV
+    description: I/O High-Speed at Low-Voltage This bit indicates that the product operates below 2.5 V.
+    bit_offset: 29
+    bit_size: 1
+fieldset/OBW1SRP:
+  description: FLASH option byte word 1 status register programming.
+  fields:
+  - name: BOR_LEV
+    description: Brownout level Write to change corresponding bits in FLASH_OBW1SR register.
+    bit_offset: 2
+    bit_size: 2
+  - name: IWDG_HW
+    description: Independent watchdog HW Control Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 4
+    bit_size: 1
+  - name: NRST_STOP
+    description: Reset on stop mode programming Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 6
+    bit_size: 1
+  - name: NRST_STBY
+    description: Reset on standby mode programming Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 7
+    bit_size: 1
+  - name: OCTO1_HSLV
+    description: XSPIM_P1 High-Speed at Low-Voltage Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 8
+    bit_size: 1
+  - name: OCTO2_HSLV
+    description: XSPIM_P2 High-Speed at Low-Voltage programming Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 9
+    bit_size: 1
+  - name: IWDG_FZ_STOP
+    description: IWDG stop mode freeze Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 17
+    bit_size: 1
+  - name: IWDG_FZ_SDBY
+    description: IWDG standby mode freeze programming Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 18
+    bit_size: 1
+  - name: VDDIO_HSLV
+    description: I/O High-Speed at Low-Voltage programming Write to change corresponding bit in FLASH_OBW1SR register.
+    bit_offset: 29
+    bit_size: 1
+fieldset/OBW2SR:
+  description: FLASH option byte word 2 status register.
+  fields:
+  - name: ITCM_AXI_SHARE
+    description: ITCM SRAM configuration.
+    bit_offset: 0
+    bit_size: 3
+  - name: DTCM_AXI_SHARE
+    description: DTCM SRAM configuration.
+    bit_offset: 4
+    bit_size: 3
+  - name: ECC_ON_SRAM
+    description: ECC on SRAM.
+    bit_offset: 8
+    bit_size: 1
+  - name: I2C_NI3C
+    description: I2C Not I3C.
+    bit_offset: 9
+    bit_size: 1
+fieldset/OBW2SRP:
+  description: FLASH option byte word 2 status register programming.
+  fields:
+  - name: ITCM_AXI_SHARE
+    description: 'ITCM AXI share programming Write to change corresponding bits in FLASH_OBW2SR register. Bit 2 should be kept to 0: ITCM_AXI_SHARE: = 000 or 011: ITCM 64 Kbytes ITCM_AXI_SHARE = 001: ITCM 128 Kbytes ITCM_AXI_SHARE = 010: ITCM 192 Kbytes.'
+    bit_offset: 0
+    bit_size: 3
+  - name: DTCM_AXI_SHARE
+    description: 'DTCM AXI share programming Write to change corresponding bits in the FLASH_OBW2SR register. Bit 2 should be kept to 0: DTCM_AXI_SHARE = 000 or 011: DTCM 64 Kbytes DTCM_AXI_SHARE = 001: DTCM 128 Kbytes DTCM_AXI_SHARE = 010: DTCM 192 Kbytes.'
+    bit_offset: 4
+    bit_size: 3
+  - name: ECC_ON_SRAM
+    description: ECC on SRAM programming Write to change corresponding bit in FLASH_OBW2SR register.
+    bit_offset: 8
+    bit_size: 1
+  - name: I2C_NI3C
+    description: I2C Not I3C Write to change corresponding bit in FLASH_OBW2SR register.
+    bit_offset: 9
+    bit_size: 1
+fieldset/OPTCR:
+  description: FLASH options control register.
+  fields:
+  - name: OPTLOCK
+    description: Options lock When this bit is set write to all other bits in this register, and write to OTP words, option bytes and option bytes keys control registers, are ignored. Clearing this bit requires the correct write sequence to FLASH_OPTKEYR register (see this register for details). If a wrong sequence is executed, or the unlock sequence is performed twice, this bit remains locked until next system reset. During the write access to set LOCK bit from 0 to 1, it is possible to change the other bits of this register.
+    bit_offset: 0
+    bit_size: 1
+  - name: PG_OPT
+    description: Program options.
+    bit_offset: 1
+    bit_size: 1
+  - name: KVEIE
+    description: Key valid error interrupt enable bit This bit controls if an interrupt has to be generated when KVEF is set in FLASH_OPTISR.
+    bit_offset: 27
+    bit_size: 1
+  - name: KTEIE
+    description: Key transfer error interrupt enable bit This bit controls if an interrupt has to be generated when KTEF is set in FLASH_OPTISR.
+    bit_offset: 28
+    bit_size: 1
+  - name: OPTERRIE
+    description: Option byte change error interrupt enable bit This bit controls if an interrupt has to be generated when an error occurs during an option byte change.
+    bit_offset: 30
+    bit_size: 1
+fieldset/OPTICR:
+  description: FLASH options interrupt clear register.
+  fields:
+  - name: KVEF
+    description: key valid error flag Set this bit to clear KVEF flag in FLASH_OPTISR register.
+    bit_offset: 27
+    bit_size: 1
+  - name: KTEF
+    description: key transfer error flag Set this bit to clear KTEF flag in FLASH_OPTISR register.
+    bit_offset: 28
+    bit_size: 1
+  - name: OPTERRF
+    description: Option byte change error flag Set this bit to clear OPTERRF flag in FLASH_OPTISR register.
+    bit_offset: 30
+    bit_size: 1
+fieldset/OPTISR:
+  description: FLASH options interrupt status register.
+  fields:
+  - name: KVEF
+    description: 'Key valid error flag This bit is set when loading an unknown or corrupted option byte key. More specifically: Embedded Flash did not find an option byte key that corresponds to the given OBKINDEX[4:0] and the requested HDPL (optionally modified by NEXTKL[1:0]). It can happen for example when requested key has not being provisioned. A double error detection was found when loading the requested option byte key. In this case, if this key is provisioned again the error should disappear. When KVEF is set write to START bit in FLASH_OBKCR is ignored. An interrupt is generated when this flag is raised if the KVEIE bit of FLASH_OPTCR register is set. Setting KVEF bit of register FLASH_OPTICR clears this bit.'
+    bit_offset: 27
+    bit_size: 1
+  - name: KTEF
+    description: Key transfer error flag This bit is set when embedded Flash signals an error to the SAES peripheral. It happens when the key size (128-bit or 256-bit) is not matching between embedded Flash OBKSIZE[1:0] and KEYSIZE bit in SAES_CR register. It also happen when an ECC dual error detection occurred while embedded Flash loaded an option byte key for the SAES peripheral. When KTEF is set write to START bit in FLASH_OBKCR is ignored. An interrupt is generated when this flag is raised if the KTEIE bit of FLASH_OPTCR register is set. Setting KTEF bit of register FLASH_OPTICR clears this bit.
+    bit_offset: 28
+    bit_size: 1
+  - name: OPTERRF
+    description: Option byte change error flag When OPTERRF is set, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTERRIE bit of FLASH_OPTCR register is set. Setting OPTERRF of register FLASH_OPTICR clears this bit.
+    bit_offset: 30
+    bit_size: 1
+fieldset/OPTKEYR:
+  description: FLASH options key register.
+  fields:
+  - name: OCUKEY
+    description: 'Options configuration unlock key Following values must be written to FLASH_OPTKEYR consecutively to unlock FLASH_OPTCR register: 1st key = 0x0819 2A3B 2nd key = 0x4C5D 6E7F Reads to this register returns zero. If above sequence is performed twice locks up the corresponding register/bit until the next system reset, and generates a bus error.'
+    bit_offset: 0
+    bit_size: 32
+fieldset/OTPLSR:
+  description: FLASH OTP lock status register.
+  fields:
+  - name: OTPL
+    description: OTP lock n Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. OTPL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and can no longer be programmed. OTPL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked and can still be modified.
+    bit_offset: 0
+    bit_size: 16
+fieldset/OTPLSRP:
+  description: FLASH OTP lock status register programming.
+  fields:
+  - name: OTPL
+    description: OTP lock n programming Write to change corresponding option byte bit in FLASH_OTPLSR. OTPL bits can be only be set, not cleared.
+    bit_offset: 0
+    bit_size: 16
+fieldset/ROTSR:
+  description: FLASH RoT status register.
+  fields:
+  - name: OEM_PROVD
+    description: 'OEM provisioned device Any other value: device is not provisioned by the OEM.'
+    bit_offset: 0
+    bit_size: 8
+    enum: OEM_PROVD
+  - name: DBG_AUTH
+    description: 'Debug authentication method Any other value: no authentication method selected (NotSet).'
+    bit_offset: 8
+    bit_size: 8
+    enum: DBG_AUTH
+  - name: IROT_SELECT
+    description: 'iRoT selection This option is ignored for STM32H7R devices (OEM iRoT is always selected). Any other value: OEM iRoT is selected at boot.'
+    bit_offset: 24
+    bit_size: 8
+    enum: IROT_SELECT
+fieldset/ROTSRP:
+  description: FLASH RoT status register programming.
+  fields:
+  - name: OEM_PROVD
+    description: OEM provisioned device Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 1.
+    bit_offset: 0
+    bit_size: 8
+  - name: DBG_AUTH
+    description: Debug authentication method programming Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 0.
+    bit_offset: 8
+    bit_size: 8
+  - name: IROT_SELECT
+    description: iRoT selection This option is ignored for STM32H7R devices. Write to change corresponding bits in FLASH_ROTSR register. Write are ignored if HDPL is greater than 1 and if NVSTATE is not 0xB4 (OPEN).
+    bit_offset: 24
+    bit_size: 8
+fieldset/SR:
+  description: FLASH status register.
+  fields:
+  - name: BUSY
+    description: Busy flag This bit is set when an effective write, erase or option byte change operation is ongoing. It is possible to know what type of operation is being executed reading the flags IS_PROGRAM, IS_ERASE and IS_OPTCHANGE. BUSY cannot be cleared by application. It is automatically reset by hardware every time a step in a write, erase or option byte change operation completes. It is not recommended to do software polling on BUSY to know when one operation completed because, depending of operation, more pulses are possible for one only operation. For software polling it is therefore better to use QW flag or to check the EOPF flag.
+    bit_offset: 0
+    bit_size: 1
+  - name: WBNE
+    description: 'Write buffer not empty flag This bit is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_CR the embedded Flash memory detects an error that involves data loss the application software has disabled write operations This bit cannot be forced to 0. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data.'
+    bit_offset: 1
+    bit_size: 1
+  - name: QW
+    description: Wait queue flag This bit is set when a write, erase or option byte change operation is pending in the command queue buffer. It is not possible to know what type of programming operation is present in the queue. This flag is reset by hardware when all write, erase or option byte change operations have been executed and thus removed from the waiting queue(s). This bit cannot be forced to 0. It is reset after a deterministic time if no other operations are requested.
+    bit_offset: 2
+    bit_size: 1
+  - name: CRC_BUSY
+    description: CRC busy flag This bit is set when a CRC calculation is ongoing. This bit cannot be forced to 0. The user must wait until the CRC calculation has completed or disable CRC computation using CRC_EN bit in FLASH_CR register.
+    bit_offset: 3
+    bit_size: 1
+  - name: IS_PROGRAM
+    description: Is a program This bit is set together with BUSY when a program operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_OPTCHANGE, because an program operation can happen during an option change.
+    bit_offset: 4
+    bit_size: 1
+  - name: IS_ERASE
+    description: Is an erase This bit is set together with BUSY when an erase operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_OPTCHANGE, because an erase operation can happen during an option change.
+    bit_offset: 5
+    bit_size: 1
+  - name: IS_OPTCHANGE
+    description: Is an option change This bit is set together with BUSY when an option change operation is ongoing. It is cleared when BUSY is cleared. This flag can also raise with IS_PROGRAM or IS_ERASE, because a program or erase step is ongoing during option change.
+    bit_offset: 6
+    bit_size: 1
+  - name: RCHECKF
+    description: Root code check flag This bit returns the status of the root code check performed following the first access to the Flash. This bit is cleared with RCHECKF bit in FLASH_FCR (optional).
+    bit_offset: 25
+    bit_size: 1
+fieldset/WRPSR:
+  description: FLASH write protection status register.
+  fields:
+  - name: WRPS
+    description: Write protection for sector n This bit reflects the write protection status of user Flash sector n.
+    bit_offset: 0
+    bit_size: 8
+fieldset/WRPSRP:
+  description: FLASH write protection status register programming.
+  fields:
+  - name: WRPS
+    description: Write protection for sector n programming Write to change corresponding bit in FLASH_WRPSR.
+    bit_offset: 0
+    bit_size: 8
+enum/BOR_LEV:
+  bit_size: 2
+  variants:
+  - name: Disabled
+    description: BOR OFF, POR/PDR reset threshold level is applied.
+    value: 0
+  - name: Level1
+    description: BOR Level 1, the threshold level is low (around 2.1 V).
+    value: 1
+  - name: Level2
+    description: BOR Level 2, the threshold level is medium (around 2.4 V).
+    value: 2
+  - name: Level3
+    description: BOR Level 3, the threshold level is high (around 2.7 V).
+    value: 3
+enum/CRC_BURST:
+  bit_size: 2
+  variants:
+  - name: Word4
+    description: every burst has a size of 4 Flash words (64 Bytes).
+    value: 0
+  - name: Word16
+    description: every burst has a size of 16 Flash words (256 Bytes).
+    value: 1
+  - name: Word64
+    description: every burst has a size of 64 Flash words (1 Kbytes).
+    value: 2
+  - name: Word256
+    description: every burst has a size of 256 Flash words (4 Kbytes).
+    value: 3
+enum/DBG_AUTH:
+  bit_size: 8
+  variants:
+  - name: ECDSA
+    description: Authentication method using ECDSA signature (NIST P256).
+    value: 81
+  - name: Delegated
+    description: Delegated debug (to OEM iRoT code in user Flash).
+    value: 111
+  - name: Password
+    description: Authentication method using password.
+    value: 138
+  - name: Locked
+    description: Locked device (no debug allowed).
+    value: 180
+enum/IROT_SELECT:
+  bit_size: 8
+  variants:
+  - name: Selected
+    description: ST iRoT is selected at boot.
+    value: 180
+enum/NEXTKL:
+  bit_size: 2
+  variants:
+  - name: Plus0
+    description: OBKINDEX represents the index of the option byte key stored for the hide protection level indicated in SBS_HDPLSR.
+    value: 0
+  - name: Plus1
+    description: OBKINDEX represents the index of the option byte key stored for the hide protection level indicated in SBS_HDPLSR plus one (e.g. if HDPL=1 in SBS_HDPLR the key of level 2 is selected).
+    value: 1
+enum/NVSRP_NVSTATE:
+  bit_size: 8
+  variants:
+  - name: Close
+    description: CLOSE.
+    value: 81
+  - name: Open
+    description: OPEN.
+    value: 180
+enum/NVSR_NVSTATE:
+  bit_size: 8
+  variants:
+  - name: Closed
+    description: CLOSED device.
+    value: 81
+  - name: Open
+    description: OPEN device.
+    value: 180
+enum/OBKSIZE:
+  bit_size: 2
+  variants:
+  - name: Bits32
+    description: Key size is 32 bits.
+    value: 0
+  - name: Bits64
+    description: Key size is 64 bits.
+    value: 1
+  - name: Bits128
+    description: Key size is 128 bits.
+    value: 2
+  - name: Bits256
+    description: Key size is 256 bits.
+    value: 3
+enum/OEM_PROVD:
+  bit_size: 8
+  variants:
+  - name: Provisioned
+    description: Device has been provisioned by the OEM.
+    value: 180
diff --git a/data/registers/pwr_h7rm0399.yaml b/data/registers/pwr_h7rm0399.yaml
index 9e7c628..3b044f7 100644
--- a/data/registers/pwr_h7rm0399.yaml
+++ b/data/registers/pwr_h7rm0399.yaml
@@ -253,6 +253,7 @@ fieldset/WKUPEPR:
     array:
       len: 6
       stride: 2
+    enum: WKUPPUPD
 fieldset/WKUPFR:
   description: reset only by system reset, not reset by wakeup from Standby mode
   fields:
@@ -283,3 +284,15 @@ enum/VOS:
     value: 2
   - name: Scale1
     value: 3
+enum/WKUPPUPD:
+  bit_size: 2
+  variants:
+  - name: NoPull
+    description: No pull-up.
+    value: 0
+  - name: PullUp
+    description: Pull-up.
+    value: 1
+  - name: PullDown
+    description: Pull-down.
+    value: 2
diff --git a/data/registers/pwr_h7rm0433.yaml b/data/registers/pwr_h7rm0433.yaml
index e7eb3e0..f89e6fc 100644
--- a/data/registers/pwr_h7rm0433.yaml
+++ b/data/registers/pwr_h7rm0433.yaml
@@ -240,6 +240,7 @@ fieldset/WKUPEPR:
     array:
       len: 6
       stride: 2
+    enum: WKUPPUPD
 fieldset/WKUPFR:
   description: reset only by system reset, not reset by wakeup from Standby mode
   fields:
@@ -259,3 +260,15 @@ enum/VOS:
     value: 2
   - name: Scale1
     value: 3
+enum/WKUPPUPD:
+  bit_size: 2
+  variants:
+  - name: NoPull
+    description: No pull-up.
+    value: 0
+  - name: PullUp
+    description: Pull-up.
+    value: 1
+  - name: PullDown
+    description: Pull-down.
+    value: 2
diff --git a/data/registers/pwr_h7rm0455.yaml b/data/registers/pwr_h7rm0455.yaml
index 54a0f77..7c9916a 100644
--- a/data/registers/pwr_h7rm0455.yaml
+++ b/data/registers/pwr_h7rm0455.yaml
@@ -253,6 +253,7 @@ fieldset/WKUPEPR:
     array:
       len: 6
       stride: 2
+    enum: WKUPPUPD
 fieldset/WKUPFR:
   description: reset only by system reset, not reset by wakeup from Standby mode
   fields:
@@ -285,3 +286,15 @@ enum/VOS:
     value: 2
   - name: Scale0
     value: 3
+enum/WKUPPUPD:
+  bit_size: 2
+  variants:
+  - name: NoPull
+    description: No pull-up.
+    value: 0
+  - name: PullUp
+    description: Pull-up.
+    value: 1
+  - name: PullDown
+    description: Pull-down.
+    value: 2
diff --git a/data/registers/pwr_h7rm0468.yaml b/data/registers/pwr_h7rm0468.yaml
index d48059d..fdc0fcb 100644
--- a/data/registers/pwr_h7rm0468.yaml
+++ b/data/registers/pwr_h7rm0468.yaml
@@ -253,6 +253,7 @@ fieldset/WKUPEPR:
     array:
       len: 6
       stride: 2
+    enum: WKUPPUPD
 fieldset/WKUPFR:
   description: reset only by system reset, not reset by wakeup from Standby mode
   fields:
@@ -285,3 +286,15 @@ enum/VOS:
     value: 2
   - name: Scale1
     value: 3
+enum/WKUPPUPD:
+  bit_size: 2
+  variants:
+  - name: NoPull
+    description: No pull-up.
+    value: 0
+  - name: PullUp
+    description: Pull-up.
+    value: 1
+  - name: PullDown
+    description: Pull-down.
+    value: 2
diff --git a/data/registers/pwr_h7rs.yaml b/data/registers/pwr_h7rs.yaml
new file mode 100644
index 0000000..a711a61
--- /dev/null
+++ b/data/registers/pwr_h7rs.yaml
@@ -0,0 +1,643 @@
+block/PWR:
+  description: Power control.
+  items:
+  - name: CR1
+    description: PWR control register 1.
+    byte_offset: 0
+    fieldset: CR1
+  - name: SR1
+    description: PWR control status register 1.
+    byte_offset: 4
+    fieldset: SR1
+  - name: CSR1
+    description: PWR control status register 1.
+    byte_offset: 8
+    fieldset: CSR1
+  - name: CSR2
+    description: PWR control register 2.
+    byte_offset: 12
+    fieldset: CSR2
+  - name: CSR3
+    description: PWR CPU control register 3.
+    byte_offset: 16
+    fieldset: CSR3
+  - name: CSR4
+    description: PWR control status register 4.
+    byte_offset: 20
+    fieldset: CSR4
+  - name: WKUPCR
+    description: PWR wakeup clear register.
+    byte_offset: 32
+    fieldset: WKUPCR
+  - name: WKUPFR
+    description: PWR wakeup flag register.
+    byte_offset: 36
+    fieldset: WKUPFR
+  - name: WKUPEPR
+    description: PWR wakeup enable and polarity register.
+    byte_offset: 40
+    fieldset: WKUPEPR
+  - name: UCPDR
+    description: PWR USB Type-C and Power Delivery register.
+    byte_offset: 44
+    fieldset: UCPDR
+  - name: APCR
+    description: PWR apply pull configuration register.
+    byte_offset: 48
+    fieldset: APCR
+  - name: PUCRN
+    description: PWR port N pull-up control register.
+    byte_offset: 52
+    fieldset: PUCRN
+  - name: PDCRN
+    description: PWR port N pull-down control register.
+    byte_offset: 56
+    fieldset: PDCRN
+  - name: PUCRO
+    description: PWR port O pull-up control register.
+    byte_offset: 60
+    fieldset: PUCRO
+  - name: PDCRO
+    description: PWR port O pull-down control register.
+    byte_offset: 64
+    fieldset: PDCRO
+  - name: PDCRP
+    description: PWR port P pull-down control register.
+    byte_offset: 68
+    fieldset: PDCRP
+  - name: PDR1
+    description: PWR debug register 1.
+    byte_offset: 80
+    fieldset: PDR1
+fieldset/APCR:
+  description: PWR apply pull configuration register.
+  fields:
+  - name: APC
+    description: Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx, PDCRx registers are applied in Standby mode even after wakeup until APC bit is reset to 0. When this bit is cleared, the I/O pull-up or pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx and PDCRx registers are not applied in Standby mode and IO becomes Hi-Z.
+    bit_offset: 0
+    bit_size: 1
+  - name: PN7_PUPD
+    description: Port N bit 7 pull-up/down configuration When this bit is set, a weak pull-up or pull-down resistor is applied on PN7 following inverse logic applied on PN6. If the PUN6 bit in PWR_PUCRN register is set and APC bit is set the week pull-down is applied on PN7. If the PDN6 bit in PWR_PDCRN register is set and APC bit is set the week pull-up is applied on PN7.
+    bit_offset: 16
+    bit_size: 1
+  - name: PO5_PUPD
+    description: Port O bit 5 pull-up/down configuration When this bit is set, a weak pull-up or pull down resistor is applied on PO5 following inverse logic applied on PO4. If the PUO4 bit in PWR_PUCRO register is set and APC bit is set the week pull-down is applied on PO5. If the PDO4 bit in PWR_PDCRO register is set and APC bit is set the week pull-up is applied on PO5..
+    bit_offset: 17
+    bit_size: 1
+  - name: I3CPB6_PU
+    description: Port PB6 I3C pull-up bit When I3C is used on PB6, when set, this bit activates the pull-up on I3C1_SCL (PB6) in standby mode.
+    bit_offset: 28
+    bit_size: 1
+  - name: I3CPB7_PU
+    description: Port PB7 I3C pull-up bit When I3C is used on PB7, when set, this bit activates the pull-up on I3C1_SDA (PB7) in standby mode.
+    bit_offset: 29
+    bit_size: 1
+  - name: I3CPB8_PU
+    description: Port PB8 I3C pull-up bit When I3C is used on PB8, when set, this bit activates the pull-up on I3C1_SCL (PB8) in standby mode.
+    bit_offset: 30
+    bit_size: 1
+  - name: I3CPB9_PU
+    description: Port PB9 I3C pull-up bit When I3C is used on PB9, when set, this bit activates the pull-up on I3C1_SDA (PB9) in standby mode.
+    bit_offset: 31
+    bit_size: 1
+fieldset/CR1:
+  description: PWR control register 1.
+  fields:
+  - name: SVOS
+    description: System Stop mode voltage scaling selection.
+    bit_offset: 0
+    bit_size: 1
+    enum: SVOS
+  - name: PVDE
+    description: Programmable voltage detector enable.
+    bit_offset: 4
+    bit_size: 1
+  - name: PLS
+    description: 'Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details.'
+    bit_offset: 5
+    bit_size: 3
+    enum: PLS
+  - name: DBP
+    description: Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in the PWR_CSR1 register, are protected against parasitic write access. This bit must be set to enable write access to these registers.
+    bit_offset: 8
+    bit_size: 1
+  - name: FLPS
+    description: Flash low-power mode in Stop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when device is in Stop mode. consumption).
+    bit_offset: 9
+    bit_size: 1
+  - name: RLPSN
+    description: RAM low power mode disable in STOP. When set the RAMs will not enter to low power mode when the system enters to STOP.
+    bit_offset: 10
+    bit_size: 1
+    enum: RLPSN
+  - name: BOOSTE
+    description: analog switch VBoost control This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits.
+    bit_offset: 11
+    bit_size: 1
+  - name: AVDREADY
+    description: analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected VDDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_CSR1 register) after setting the AVDEN bit and selecting the supply level to be monitored (ALS bits).
+    bit_offset: 12
+    bit_size: 1
+  - name: AVDEN
+    description: Peripheral voltage monitor on VDDA enable.
+    bit_offset: 13
+    bit_size: 1
+  - name: ALS
+    description: 'Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details.'
+    bit_offset: 14
+    bit_size: 2
+    enum: ALS
+fieldset/CSR1:
+  description: PWR control status register 1.
+  fields:
+  - name: BREN
+    description: Backup regulator enable When set, the backup regulator (used to maintain the backup RAM content in Standby and V<sub>BAT</sub> modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and V<sub>BAT</sub> modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and V<sub>BAT</sub> modes.
+    bit_offset: 0
+    bit_size: 1
+  - name: MONEN
+    description: 'V<sub>BAT</sub> and temperature monitoring enable When set, the V<sub>BAT</sub> supply and temperature monitoring is enabled. Note: V<sub>BAT</sub> and temperature monitoring are only available when the backup regulator is enabled (BREN bit set to 1).'
+    bit_offset: 4
+    bit_size: 1
+  - name: BRRDY
+    description: Backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready.
+    bit_offset: 16
+    bit_size: 1
+  - name: VBATL
+    description: V<sub>BAT</sub> level monitoring versus low threshold.
+    bit_offset: 20
+    bit_size: 1
+  - name: VBATH
+    description: V<sub>BAT</sub> level monitoring versus high threshold.
+    bit_offset: 21
+    bit_size: 1
+  - name: TEMPL
+    description: Temperature level monitoring versus low threshold.
+    bit_offset: 22
+    bit_size: 1
+  - name: TEMPH
+    description: Temperature level monitoring versus high threshold.
+    bit_offset: 23
+    bit_size: 1
+fieldset/CSR2:
+  description: PWR control register 2.
+  fields:
+  - name: BYPASS
+    description: 'Power management unit bypass Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41.'
+    bit_offset: 0
+    bit_size: 1
+  - name: LDOEN
+    description: 'Low drop-out regulator enable Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41.'
+    bit_offset: 1
+    bit_size: 1
+  - name: SDEN
+    description: 'SMPS step-down converter enable Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41.'
+    bit_offset: 2
+    bit_size: 1
+  - name: SDEXTHP
+    description: 'SMPS external power delivery selection Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41.'
+    bit_offset: 3
+    bit_size: 1
+  - name: SDLEVEL
+    description: SMPS step-down converter voltage output for LDO or external supply This bit is used when both the LDO and SMPS step-down converter are enabled with SDEN and LDOEN enabled or when SMPSEXTHP is enabled. In this case SDHILEVEL has to be set to 1 to confirm the regulator settings.
+    bit_offset: 4
+    bit_size: 1
+    enum: SDLEVEL
+  - name: VBE
+    description: VBAT charging enable.
+    bit_offset: 8
+    bit_size: 1
+  - name: VBRS
+    description: VBAT charging resistor selection.
+    bit_offset: 9
+    bit_size: 1
+    enum: VBRS
+  - name: XSPICAP1
+    description: XSPI port 1 capacitor control bits see the product datasheet for more details.
+    bit_offset: 10
+    bit_size: 2
+    enum: XSPICAP
+  - name: XSPICAP2
+    description: XSPI port 2 capacitor control bits see the product datasheet for more details.
+    bit_offset: 12
+    bit_size: 2
+    enum: XSPICAP
+  - name: EN_XSPIM1
+    description: 'EN_XSPIM1: this bit allow the SW to enable the XSPI interface. The XSPIM_P1 supply must be stable prior to setting this bit.'
+    bit_offset: 14
+    bit_size: 1
+  - name: EN_XSPIM2
+    description: 'EN_XSPIM2: this bit allows the SW to enable the XSPI interface, when available. The XSPIM_P2 supply must be stable prior to setting this bit. It should also be set when FMC is used.'
+    bit_offset: 15
+    bit_size: 1
+  - name: SDEXTRDY
+    description: SMPS step-down converter external supply ready This bit is set by hardware to indicate that the external supply from the SMPS step-down converter is ready.
+    bit_offset: 16
+    bit_size: 1
+  - name: USB33DEN
+    description: VDD33_USB voltage level detector enable.
+    bit_offset: 24
+    bit_size: 1
+  - name: USBREGEN
+    description: USB regulator enable.
+    bit_offset: 25
+    bit_size: 1
+  - name: USB33RDY
+    description: USB supply ready.
+    bit_offset: 26
+    bit_size: 1
+  - name: USBHSREGEN
+    description: USB HS regulator enable.
+    bit_offset: 27
+    bit_size: 1
+enum/SDLEVEL:
+  bit_size: 1
+  variants:
+  - name: Reset
+    value: 0
+  - name: V1_8
+    value: 1
+fieldset/CSR3:
+  description: PWR CPU control register 3.
+  fields:
+  - name: PDDS
+    description: Power Down Deepsleep. This bit allows CPU to define the Deepsleep mode.
+    bit_offset: 0
+    bit_size: 1
+    enum: PDDS
+  - name: CSSF
+    description: Clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware.
+    bit_offset: 1
+    bit_size: 1
+  - name: STOPF
+    description: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU CSSF bit.
+    bit_offset: 8
+    bit_size: 1
+  - name: SBF
+    description: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU CSSF bit.
+    bit_offset: 9
+    bit_size: 1
+fieldset/CSR4:
+  description: PWR control status register 4.
+  fields:
+  - name: VOS
+    description: 'Voltage scaling selection according to performance These bits control the V<sub>CORE</sub> voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling must be changed before increasing the system frequency. When decreasing performance, the system frequency must first be decreased before changing the voltage scaling. Note: Refer to Section Electrical characteristics of the product datasheet for more details.'
+    bit_offset: 0
+    bit_size: 1
+    enum: VOS
+  - name: VOSRDY
+    description: VOS Ready bit.
+    bit_offset: 1
+    bit_size: 1
+fieldset/PDCRN:
+  description: PWR port N pull-down control register.
+  fields:
+  - name: PDN0
+    description: Port N pull-down bit 0 When set activates the pull-down on PN0 when the APC bit is set in PWR_APCR.
+    bit_offset: 0
+    bit_size: 1
+  - name: PDN1
+    description: Port N pull-down bit 1 When set activates the pull-down on PN1 when the APC bit is set in PWR_APCR.
+    bit_offset: 1
+    bit_size: 1
+  - name: PDN2N5
+    description: Port N PN2 to PN5 pull-down activation When set, four pull-down resistors are activated on PN2 to PN5 when the APC bit is set in PWR_APCR.
+    bit_offset: 2
+    bit_size: 1
+  - name: PDN6
+    description: Port N pull-down bit 6 When set activates the pull-down on PN6 when the APC bit is set in PWR_APCR.
+    bit_offset: 6
+    bit_size: 1
+  - name: PDN8N11
+    description: Port N - PN8 to PN11 pull-down activation When set, four pull-down resistors are activated on PN8 to PN11 when the APC bit is set in PWR_APCR.
+    bit_offset: 8
+    bit_size: 1
+  - name: PDN12
+    description: Port N pull-down bit 12 When set activates the pull-down on PN12 when the APC bit is set in PWR_APCR.
+    bit_offset: 12
+    bit_size: 1
+fieldset/PDCRO:
+  description: PWR port O pull-down control register.
+  fields:
+  - name: PDO0
+    description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR.
+    bit_offset: 0
+    bit_size: 1
+  - name: PDO1
+    description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR.
+    bit_offset: 1
+    bit_size: 1
+  - name: PDO2
+    description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR.
+    bit_offset: 2
+    bit_size: 1
+  - name: PDO3
+    description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR.
+    bit_offset: 3
+    bit_size: 1
+  - name: PDO4
+    description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR.
+    bit_offset: 4
+    bit_size: 1
+fieldset/PDCRP:
+  description: PWR port P pull-down control register.
+  fields:
+  - name: PDP0P3
+    description: Port P0-P3 pull-down activation When set, four pull-down resistors are activated on P0 to P3 when the APC bit is set in PWR_APCR.
+    bit_offset: 0
+    bit_size: 1
+  - name: PDP4P7
+    description: Port P4-P7 pull-down activation When set, four pull-down resitors are activated on P4 to P7 when the APC bit is set in PWR_APCR.
+    bit_offset: 4
+    bit_size: 1
+  - name: PDP8P11
+    description: Port P8-P11 pull-down activation When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR.
+    bit_offset: 8
+    bit_size: 1
+  - name: PDP12P15
+    description: Port P12-P15 pull-down activation When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR.
+    bit_offset: 12
+    bit_size: 1
+fieldset/PDR1:
+  description: PWR debug register 1.
+  fields:
+  - name: UNLOCKED
+    description: Debug Register Unlocked.
+    bit_offset: 0
+    bit_size: 1
+    enum: UNLOCKED
+  - name: SDFPWMEN
+    description: Step down converter force PWM mode.
+    bit_offset: 3
+    bit_size: 1
+  - name: SYNC_ADC
+    description: (Non-User bit).
+    bit_offset: 16
+    bit_size: 1
+    enum: SYNC_ADC
+fieldset/PUCRN:
+  description: PWR port N pull-up control register.
+  fields:
+  - name: PUN1
+    description: Port N pull-up bit 1 When set, each bit activates the pull-up on PN1 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD1 bit is also set.
+    bit_offset: 1
+    bit_size: 1
+  - name: PUN6
+    description: Port N pull-up bit 6 When set activates the pull-up on PN6 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PDN6 bit is also set.
+    bit_offset: 6
+    bit_size: 1
+  - name: PUN12
+    description: Port N pull-up bit 12 When set, each bit activates the pull-up on PN12 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD12 bit is also set.
+    bit_offset: 12
+    bit_size: 1
+fieldset/PUCRO:
+  description: PWR port O pull-up control register.
+  fields:
+  - name: PUO0
+    description: (n = 1 to 0) Port O pull-up bits When set, each bit activates the pull-up on POy when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits in PWR_PDCRO is also set.
+    bit_offset: 0
+    bit_size: 1
+  - name: PUO1
+    description: (n = 1 to 0) Port O pull-up bits When set, each bit activates the pull-up on POy when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits in PWR_PDCRO is also set.
+    bit_offset: 1
+    bit_size: 1
+  - name: PUO4
+    description: Port O pull-up bit 4 When set activates the pull-up on PO4 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits PDO4 in PWR_PDCRO is also set.
+    bit_offset: 4
+    bit_size: 1
+fieldset/SR1:
+  description: PWR control status register 1.
+  fields:
+  - name: ACTVOS
+    description: VOS currently applied for V<sub>CORE</sub> voltage scaling selection. These bit reflect the last VOS value applied to the PMU.
+    bit_offset: 0
+    bit_size: 1
+  - name: ACTVOSRDY
+    description: Voltage levels ready bit for currently used ACTVOS and SDHILEVEL This bit is set to 1 by hardware when the voltage regulator and the SMPS step-down converter are both disabled and Bypass mode is selected in PWR control register 2 (PWR_CSR2).
+    bit_offset: 1
+    bit_size: 1
+  - name: PVDO
+    description: 'Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. PLS[2:0] bits. bits. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.'
+    bit_offset: 4
+    bit_size: 1
+    enum: PVDO
+  - name: AVDO
+    description: 'Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.'
+    bit_offset: 13
+    bit_size: 1
+    enum: AVDO
+fieldset/UCPDR:
+  description: PWR USB Type-C and Power Delivery register.
+  fields:
+  - name: UCPD_DBDIS
+    description: UCPD dead battery disable.
+    bit_offset: 0
+    bit_size: 1
+  - name: UCPD_STBY
+    description: UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers.
+    bit_offset: 1
+    bit_size: 1
+fieldset/WKUPCR:
+  description: PWR wakeup clear register.
+  fields:
+  - name: WKUPC
+    description: Clear Wakeup pin flag for WKUP1 These bits are always read as 0.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+fieldset/WKUPEPR:
+  description: PWR wakeup enable and polarity register.
+  fields:
+  - name: WKUPEN
+    description: 'Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge.'
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+  - name: WKUPP
+    description: Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin.
+    bit_offset: 8
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+    enum: WKUPP
+  - name: WKUPPUPD
+    description: Wakeup pin pull configuration
+    bit_offset: 16
+    bit_size: 2
+    array:
+      len: 4
+      stride: 2
+    enum: WKUPPUPD
+fieldset/WKUPFR:
+  description: PWR wakeup flag register.
+  fields:
+  - name: WKUPF
+    description: Wakeup pin WKUP flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC1 bit in the PWR wakeup clear register (PWR_WKUPCR).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+enum/ALS:
+  bit_size: 2
+  variants:
+  - name: Level1
+    description: AVD level 1.
+    value: 0
+  - name: Level2
+    description: AVD level 2.
+    value: 1
+  - name: Level3
+    description: AVD level 3.
+    value: 2
+  - name: Level4
+    description: AVD level 4.
+    value: 3
+enum/AVDO:
+  bit_size: 1
+  variants:
+  - name: AboveOrEqual
+    description: VDDA is equal or higher than the AVD threshold selected with the ALS[1:0] bits.
+    value: 0
+  - name: Below
+    description: VDDA is lower than the AVD threshold selected with the ALS[1:0] bits.
+    value: 1
+enum/PDDS:
+  bit_size: 1
+  variants:
+  - name: Stop
+    description: Stop mode when device enters Deepsleep.
+    value: 0
+  - name: Standby
+    description: Standby mode when device enters Deepsleep.
+    value: 1
+enum/PLS:
+  bit_size: 3
+  variants:
+  - name: Level1
+    description: PVD level 1.
+    value: 0
+  - name: Level2
+    description: PVD level 2.
+    value: 1
+  - name: Level3
+    description: PVD level 3.
+    value: 2
+  - name: Level4
+    description: PVD level 4.
+    value: 3
+  - name: Level5
+    description: PVD level 5.
+    value: 4
+  - name: Level6
+    description: PVD level 6.
+    value: 5
+  - name: Level7
+    description: PVD level 7.
+    value: 6
+  - name: External
+    description: External voltage level on PVD_IN pin, compared to internal VREFINT level.
+    value: 7
+enum/PVDO:
+  bit_size: 1
+  variants:
+  - name: AboveOrEqual
+    description: VDD or PVD_IN voltage is equal or higher than the PVD threshold selected through the.
+    value: 0
+  - name: Below
+    description: VDD or PVD_IN voltage is lower than the PVD threshold selected through the PLS[2:0].
+    value: 1
+enum/RLPSN:
+  bit_size: 1
+  variants:
+  - name: LowPower
+    description: RAM enters to low power mode when system enters to STOP.
+    value: 0
+  - name: Normal
+    description: RAM remains in normal mode when system enters to STOP.
+    value: 1
+enum/SVOS:
+  bit_size: 1
+  variants:
+  - name: Low
+    description: SVOS Low.
+    value: 0
+  - name: High
+    description: SVOS High (default).
+    value: 1
+enum/SYNC_ADC:
+  bit_size: 1
+  variants:
+  - name: FreeRunning
+    description: SD_Converter clock free running.
+    value: 0
+  - name: Synchronized
+    description: SD_Converter clock synchronised to ADC.
+    value: 1
+enum/UNLOCKED:
+  bit_size: 1
+  variants:
+  - name: Locked
+    description: 'accessed locked: key was not written and after each register write access.'
+    value: 0
+  - name: Unlocked
+    description: after key 0xCAFECAFE was written in this register.
+    value: 1
+enum/VBRS:
+  bit_size: 1
+  variants:
+  - name: Ohm5k
+    description: Charge VBAT through a 5 k resistor.
+    value: 0
+  - name: Ohm1_5k
+    description: Charge VBAT through a 1.5 k resistor.
+    value: 1
+enum/VOS:
+  bit_size: 1
+  variants:
+  - name: Low
+    description: VOS Low level (default).
+    value: 0
+  - name: High
+    description: VOS High level.
+    value: 1
+enum/WKUPP:
+  bit_size: 1
+  variants:
+  - name: High
+    description: Detection on high level (rising edge).
+    value: 0
+  - name: Low
+    description: Detection on low level (falling edge).
+    value: 1
+enum/WKUPPUPD:
+  bit_size: 2
+  variants:
+  - name: NoPull
+    description: No pull-up.
+    value: 0
+  - name: PullUp
+    description: Pull-up.
+    value: 1
+  - name: PullDown
+    description: Pull-down.
+    value: 2
+enum/XSPICAP:
+  bit_size: 2
+  variants:
+  - name: Disabled
+    description: 'XSPI Capacitor OFF (default) note: to confirm with analog design.'
+    value: 0
+  - name: OneThird
+    description: XSPI Capacitor set to 1/3.
+    value: 1
+  - name: TwoThirds
+    description: XSPI Capacitor set to 2/3.
+    value: 2
+  - name: Full
+    description: XSPI Capacitor set to full capacitance.
+    value: 3
diff --git a/data/registers/rcc_h5.yaml b/data/registers/rcc_h5.yaml
index b397466..b9333bc 100644
--- a/data/registers/rcc_h5.yaml
+++ b/data/registers/rcc_h5.yaml
@@ -328,7 +328,7 @@ fieldset/AHB1RSTR:
     bit_offset: 17
     bit_size: 1
   - name: ETHRST
-    description: "ETHRST block reset\r Set and reset by software"
+    description: "ETH1 block reset\r Set and reset by software"
     bit_offset: 19
     bit_size: 1
   - name: TZSC1RST
diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml
index 69a4d94..0520366 100644
--- a/data/registers/rcc_h7.yaml
+++ b/data/registers/rcc_h7.yaml
@@ -312,15 +312,15 @@ fieldset/AHB1ENR:
     description: ART Clock Enable
     bit_offset: 14
     bit_size: 1
-  - name: ETH1MACEN
+  - name: ETHEN
     description: Ethernet MAC bus interface Clock Enable
     bit_offset: 15
     bit_size: 1
-  - name: ETH1TXEN
+  - name: ETHTXEN
     description: Ethernet Transmission Clock Enable
     bit_offset: 16
     bit_size: 1
-  - name: ETH1RXEN
+  - name: ETHRXEN
     description: Ethernet Reception Clock Enable
     bit_offset: 17
     bit_size: 1
@@ -359,15 +359,15 @@ fieldset/AHB1LPENR:
     description: ART Clock Enable During CSleep Mode
     bit_offset: 14
     bit_size: 1
-  - name: ETH1MACLPEN
+  - name: ETHLPEN
     description: Ethernet MAC bus interface Clock Enable During CSleep Mode
     bit_offset: 15
     bit_size: 1
-  - name: ETH1TXLPEN
+  - name: ETHTXLPEN
     description: Ethernet Transmission Clock Enable During CSleep Mode
     bit_offset: 16
     bit_size: 1
-  - name: ETH1RXLPEN
+  - name: ETHRXLPEN
     description: Ethernet Reception Clock Enable During CSleep Mode
     bit_offset: 17
     bit_size: 1
@@ -406,8 +406,8 @@ fieldset/AHB1RSTR:
     description: ART block reset
     bit_offset: 14
     bit_size: 1
-  - name: ETH1MACRST
-    description: ETH1MAC block reset
+  - name: ETHRST
+    description: ETH block reset
     bit_offset: 15
     bit_size: 1
   - name: USB_OTG_HSRST
@@ -1802,15 +1802,15 @@ fieldset/C1_AHB1ENR:
     description: ART Clock Enable
     bit_offset: 14
     bit_size: 1
-  - name: ETH1MACEN
+  - name: ETHEN
     description: Ethernet MAC bus interface Clock Enable
     bit_offset: 15
     bit_size: 1
-  - name: ETH1TXEN
+  - name: ETHTXEN
     description: Ethernet Transmission Clock Enable
     bit_offset: 16
     bit_size: 1
-  - name: ETH1RXEN
+  - name: ETHRXEN
     description: Ethernet Reception Clock Enable
     bit_offset: 17
     bit_size: 1
@@ -1849,15 +1849,15 @@ fieldset/C1_AHB1LPENR:
     description: ART Clock Enable During CSleep Mode
     bit_offset: 14
     bit_size: 1
-  - name: ETH1MACLPEN
+  - name: ETHLPEN
     description: Ethernet MAC bus interface Clock Enable During CSleep Mode
     bit_offset: 15
     bit_size: 1
-  - name: ETH1TXLPEN
+  - name: ETHTXLPEN
     description: Ethernet Transmission Clock Enable During CSleep Mode
     bit_offset: 16
     bit_size: 1
-  - name: ETH1RXLPEN
+  - name: ETHRXLPEN
     description: Ethernet Reception Clock Enable During CSleep Mode
     bit_offset: 17
     bit_size: 1
diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml
index a316387..fbd1732 100644
--- a/data/registers/rcc_h7ab.yaml
+++ b/data/registers/rcc_h7ab.yaml
@@ -232,15 +232,15 @@ fieldset/AHB1ENR:
     description: ART Clock Enable
     bit_offset: 14
     bit_size: 1
-  - name: ETH1MACEN
+  - name: ETHEN
     description: Ethernet MAC bus interface Clock Enable
     bit_offset: 15
     bit_size: 1
-  - name: ETH1TXEN
+  - name: ETHTXEN
     description: Ethernet Transmission Clock Enable
     bit_offset: 16
     bit_size: 1
-  - name: ETH1RXEN
+  - name: ETHRXEN
     description: Ethernet Reception Clock Enable
     bit_offset: 17
     bit_size: 1
@@ -279,15 +279,15 @@ fieldset/AHB1LPENR:
     description: ART Clock Enable During CSleep Mode
     bit_offset: 14
     bit_size: 1
-  - name: ETH1MACLPEN
+  - name: ETHLPEN
     description: Ethernet MAC bus interface Clock Enable During CSleep Mode
     bit_offset: 15
     bit_size: 1
-  - name: ETH1TXLPEN
+  - name: ETHTXLPEN
     description: Ethernet Transmission Clock Enable During CSleep Mode
     bit_offset: 16
     bit_size: 1
-  - name: ETH1RXLPEN
+  - name: ETHRXLPEN
     description: Ethernet Reception Clock Enable During CSleep Mode
     bit_offset: 17
     bit_size: 1
@@ -326,8 +326,8 @@ fieldset/AHB1RSTR:
     description: ART block reset
     bit_offset: 14
     bit_size: 1
-  - name: ETH1MACRST
-    description: ETH1MAC block reset
+  - name: ETHRST
+    description: ETH block reset
     bit_offset: 15
     bit_size: 1
   - name: USB_OTG_HSRST
diff --git a/data/registers/rcc_h7rm0433.yaml b/data/registers/rcc_h7rm0433.yaml
index 22da980..aa0103b 100644
--- a/data/registers/rcc_h7rm0433.yaml
+++ b/data/registers/rcc_h7rm0433.yaml
@@ -312,15 +312,15 @@ fieldset/AHB1ENR:
     description: ART Clock Enable
     bit_offset: 14
     bit_size: 1
-  - name: ETH1MACEN
+  - name: ETHEN
     description: Ethernet MAC bus interface Clock Enable
     bit_offset: 15
     bit_size: 1
-  - name: ETH1TXEN
+  - name: ETHTXEN
     description: Ethernet Transmission Clock Enable
     bit_offset: 16
     bit_size: 1
-  - name: ETH1RXEN
+  - name: ETHRXEN
     description: Ethernet Reception Clock Enable
     bit_offset: 17
     bit_size: 1
@@ -359,15 +359,15 @@ fieldset/AHB1LPENR:
     description: ART Clock Enable During CSleep Mode
     bit_offset: 14
     bit_size: 1
-  - name: ETH1MACLPEN
+  - name: ETHLPEN
     description: Ethernet MAC bus interface Clock Enable During CSleep Mode
     bit_offset: 15
     bit_size: 1
-  - name: ETH1TXLPEN
+  - name: ETHTXLPEN
     description: Ethernet Transmission Clock Enable During CSleep Mode
     bit_offset: 16
     bit_size: 1
-  - name: ETH1RXLPEN
+  - name: ETHRXLPEN
     description: Ethernet Reception Clock Enable During CSleep Mode
     bit_offset: 17
     bit_size: 1
@@ -406,8 +406,8 @@ fieldset/AHB1RSTR:
     description: ART block reset
     bit_offset: 14
     bit_size: 1
-  - name: ETH1MACRST
-    description: ETH1MAC block reset
+  - name: ETHRST
+    description: ETH block reset
     bit_offset: 15
     bit_size: 1
   - name: USB_OTG_HSRST
@@ -1790,15 +1790,15 @@ fieldset/C1_AHB1ENR:
     description: ART Clock Enable
     bit_offset: 14
     bit_size: 1
-  - name: ETH1MACEN
+  - name: ETHEN
     description: Ethernet MAC bus interface Clock Enable
     bit_offset: 15
     bit_size: 1
-  - name: ETH1TXEN
+  - name: ETHTXEN
     description: Ethernet Transmission Clock Enable
     bit_offset: 16
     bit_size: 1
-  - name: ETH1RXEN
+  - name: ETHRXEN
     description: Ethernet Reception Clock Enable
     bit_offset: 17
     bit_size: 1
@@ -1837,15 +1837,15 @@ fieldset/C1_AHB1LPENR:
     description: ART Clock Enable During CSleep Mode
     bit_offset: 14
     bit_size: 1
-  - name: ETH1MACLPEN
+  - name: ETHLPEN
     description: Ethernet MAC bus interface Clock Enable During CSleep Mode
     bit_offset: 15
     bit_size: 1
-  - name: ETH1TXLPEN
+  - name: ETHTXLPEN
     description: Ethernet Transmission Clock Enable During CSleep Mode
     bit_offset: 16
     bit_size: 1
-  - name: ETH1RXLPEN
+  - name: ETHRXLPEN
     description: Ethernet Reception Clock Enable During CSleep Mode
     bit_offset: 17
     bit_size: 1
diff --git a/data/registers/rcc_h7rs.yaml b/data/registers/rcc_h7rs.yaml
new file mode 100644
index 0000000..5b8c94a
--- /dev/null
+++ b/data/registers/rcc_h7rs.yaml
@@ -0,0 +1,4295 @@
+block/RCC:
+  description: Reset and clock control.
+  items:
+  - name: CR
+    description: RCC source control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: HSICFGR
+    description: RCC HSI calibration register.
+    byte_offset: 4
+    fieldset: HSICFGR
+  - name: CRRCR
+    description: RCC clock recovery RC register.
+    byte_offset: 8
+    fieldset: CRRCR
+  - name: CSICFGR
+    description: RCC CSI calibration register.
+    byte_offset: 12
+    fieldset: CSICFGR
+  - name: CFGR
+    description: RCC clock configuration register.
+    byte_offset: 16
+    fieldset: CFGR
+  - name: CDCFGR
+    description: RCC CPU domain clock configuration register.
+    byte_offset: 24
+    fieldset: CDCFGR
+  - name: BMCFGR
+    description: RCC AHB clock configuration register.
+    byte_offset: 28
+    fieldset: BMCFGR
+  - name: APBCFGR
+    description: RCC APB clocks configuration register.
+    byte_offset: 32
+    fieldset: APBCFGR
+  - name: PLLCKSELR
+    description: RCC PLLs clock source selection register.
+    byte_offset: 40
+    fieldset: PLLCKSELR
+  - name: PLLCFGR
+    description: RCC PLLs configuration register.
+    byte_offset: 44
+    fieldset: PLLCFGR
+  - name: PLLDIVR
+    description: RCC PLL dividers configuration register 1.
+    array:
+      len: 3
+      stride: 8
+    byte_offset: 48
+    fieldset: PLLDIVR
+  - name: PLLFRACR
+    description: RCC PLL fractional divider register.
+    array:
+      len: 3
+      stride: 8
+    byte_offset: 52
+    fieldset: PLLFRACR
+  - name: AHBPERCKSELR
+    description: RCC AHB peripheral kernel clock selection register.
+    byte_offset: 76
+    fieldset: AHBPERCKSELR
+  - name: APB1PERCKSELR
+    description: RCC APB1 peripherals kernel clock selection register.
+    byte_offset: 80
+    fieldset: APB1PERCKSELR
+  - name: APB2PERCKSELR
+    description: RCC APB2 peripherals kernel clock selection register.
+    byte_offset: 84
+    fieldset: APB2PERCKSELR
+  - name: APB45PERCKSELR
+    description: RCC APB4,5 peripherals kernel clock selection register.
+    byte_offset: 88
+    fieldset: APB45PERCKSELR
+  - name: CIER
+    description: RCC clock source interrupt enable register.
+    byte_offset: 96
+    fieldset: CIER
+  - name: CIFR
+    description: RCC clock source interrupt flag register.
+    byte_offset: 100
+    fieldset: CIFR
+  - name: CICR
+    description: RCC clock source interrupt clear register.
+    byte_offset: 104
+    fieldset: CICR
+  - name: BDCR
+    description: RCC Backup domain control register.
+    byte_offset: 112
+    fieldset: BDCR
+  - name: CSR
+    description: RCC clock control and status register.
+    byte_offset: 116
+    fieldset: CSR
+  - name: AHB5RSTR
+    description: RCC AHB5 peripheral reset register.
+    byte_offset: 124
+    fieldset: AHB5RSTR
+  - name: AHB1RSTR
+    description: RCC AHB1 peripheral reset register.
+    byte_offset: 128
+    fieldset: AHB1RSTR
+  - name: AHB2RSTR
+    description: RCC AHB2 peripheral reset register.
+    byte_offset: 132
+    fieldset: AHB2RSTR
+  - name: AHB4RSTR
+    description: RCC AHB4 peripheral reset register.
+    byte_offset: 136
+    fieldset: AHB4RSTR
+  - name: APB5RSTR
+    description: RCC APB5 peripheral reset register.
+    byte_offset: 140
+    fieldset: APB5RSTR
+  - name: APB1RSTR1
+    description: RCC APB1 peripheral reset register 1.
+    byte_offset: 144
+    fieldset: APB1RSTR1
+  - name: APB1RSTR2
+    description: RCC APB1 peripheral reset register 2.
+    byte_offset: 148
+    fieldset: APB1RSTR2
+  - name: APB2RSTR
+    description: RCC APB2 peripheral reset register.
+    byte_offset: 152
+    fieldset: APB2RSTR
+  - name: APB4RSTR
+    description: RCC APB4 peripheral reset register.
+    byte_offset: 156
+    fieldset: APB4RSTR
+  - name: AHB3RSTR
+    description: RCC AHB3 peripheral reset register.
+    byte_offset: 164
+    fieldset: AHB3RSTR
+  - name: CKGDISR
+    description: RCC AXI clocks gating disable register.
+    byte_offset: 176
+    fieldset: CKGDISR
+  - name: PLLDIVR2
+    description: RCC PLL dividers configuration register 2.
+    array:
+      len: 3
+      stride: 4
+    byte_offset: 192
+    fieldset: PLLDIVR2
+  - name: PLLSSCGR
+    description: RCC PLL Spread Spectrum Clock Generator register.
+    array:
+      len: 3
+      stride: 4
+    byte_offset: 204
+    fieldset: PLLSSCGR
+  - name: CKPROTR
+    description: RCC clock protection register.
+    byte_offset: 256
+    fieldset: CKPROTR
+  - name: RSR
+    description: RCC Reset status register.
+    byte_offset: 304
+    fieldset: RSR
+  - name: AHB5ENR
+    description: RCC AHB5 clock enable register.
+    byte_offset: 308
+    fieldset: AHB5ENR
+  - name: AHB1ENR
+    description: RCC AHB1 clock enable register.
+    byte_offset: 312
+    fieldset: AHB1ENR
+  - name: AHB2ENR
+    description: RCC AHB2 clock enable register.
+    byte_offset: 316
+    fieldset: AHB2ENR
+  - name: AHB4ENR
+    description: RCC AHB4 clock enable register.
+    byte_offset: 320
+    fieldset: AHB4ENR
+  - name: APB5ENR
+    description: RCC APB5 clock enable register.
+    byte_offset: 324
+    fieldset: APB5ENR
+  - name: APB1ENR1
+    description: RCC APB1 clock enable register 1.
+    byte_offset: 328
+    fieldset: APB1ENR1
+  - name: APB1ENR2
+    description: RCC APB1 clock enable register 2.
+    byte_offset: 332
+    fieldset: APB1ENR2
+  - name: APB2ENR
+    description: RCC APB2 clock enable register.
+    byte_offset: 336
+    fieldset: APB2ENR
+  - name: APB4ENR
+    description: RCC APB4 clock enable register.
+    byte_offset: 340
+    fieldset: APB4ENR
+  - name: AHB3ENR
+    description: RCC AHB3 clock enable register.
+    byte_offset: 344
+    fieldset: AHB3ENR
+  - name: AHB5LPENR
+    description: RCC AHB5 low-power clock enable register.
+    byte_offset: 348
+    fieldset: AHB5LPENR
+  - name: AHB1LPENR
+    description: RCC AHB1 low-power clock enable register.
+    byte_offset: 352
+    fieldset: AHB1LPENR
+  - name: AHB2LPENR
+    description: RCC AHB2 low-power clock enable register.
+    byte_offset: 356
+    fieldset: AHB2LPENR
+  - name: AHB4LPENR
+    description: RCC AHB4 low-power clock enable register.
+    byte_offset: 360
+    fieldset: AHB4LPENR
+  - name: AHB3LPENR
+    description: RCC AHB3 low-power clock enable register.
+    byte_offset: 364
+    fieldset: AHB3LPENR
+  - name: APB1LPENR1
+    description: RCC APB1 low-power clock enable register 1.
+    byte_offset: 368
+    fieldset: APB1LPENR1
+  - name: APB1LPENR2
+    description: RCC APB1 low-power clock enable register 2.
+    byte_offset: 372
+    fieldset: APB1LPENR2
+  - name: APB2LPENR
+    description: RCC APB2 low-power clock enable register.
+    byte_offset: 376
+    fieldset: APB2LPENR
+  - name: APB4LPENR
+    description: RCC APB4 low-power clock enable register.
+    byte_offset: 380
+    fieldset: APB4LPENR
+  - name: APB5LPENR
+    description: RCC APB5 sleep clock register.
+    byte_offset: 384
+    fieldset: APB5LPENR
+fieldset/AHB1ENR:
+  description: RCC AHB1 clock enable register.
+  fields:
+  - name: GPDMA1EN
+    description: GPDMA1 clock enable Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+  - name: ADC12EN
+    description: ADC1 and 2 peripheral clocks enable Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to ADCx_CK input, and the hclk1 bus interface clock.
+    bit_offset: 5
+    bit_size: 1
+  - name: ETHEN
+    description: ETH1 MAC peripheral clock enable Set and reset by software.
+    bit_offset: 15
+    bit_size: 1
+  - name: ETHTXEN
+    description: ETH1 transmission clock enable Set and reset by software.
+    bit_offset: 16
+    bit_size: 1
+  - name: ETHRXEN
+    description: ETH1 reception clock enable Set and reset by software.
+    bit_offset: 17
+    bit_size: 1
+  - name: USB_OTG_HSEN
+    description: OTGHS clocks enable Set and reset by software.
+    bit_offset: 25
+    bit_size: 1
+  - name: USBPHYCEN
+    description: USBPHYC clocks enable Set and reset by software.
+    bit_offset: 26
+    bit_size: 1
+  - name: USB_OTG_FSEN
+    description: OTGFS peripheral clocks enable Set and reset by software.
+    bit_offset: 27
+    bit_size: 1
+  - name: ADFEN
+    description: ADF clocks enable Set and reset by software.
+    bit_offset: 31
+    bit_size: 1
+fieldset/AHB1LPENR:
+  description: RCC AHB1 low-power clock enable register.
+  fields:
+  - name: GPDMA1LPEN
+    description: GPDMA1 clock enable in low-power mode Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+  - name: ADC12LPEN
+    description: ADC1 and 2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to ADCx_CK input, and the rcc_hclk1 bus interface clock.
+    bit_offset: 5
+    bit_size: 1
+  - name: ETHLPEN
+    description: ETH1 MAC peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 15
+    bit_size: 1
+  - name: ETHTXLPEN
+    description: ETH1 transmission peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 16
+    bit_size: 1
+  - name: ETHRXLPEN
+    description: ETH1 reception peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 17
+    bit_size: 1
+  - name: USBPDCTRL
+    description: USBPHYC common block power-down control Set and reset by software.
+    bit_offset: 24
+    bit_size: 1
+    enum: USBPDCTRL
+  - name: USB_OTG_HSLPEN
+    description: OTGHS peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 25
+    bit_size: 1
+  - name: USBPHYCLPEN
+    description: USBPHYC peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 26
+    bit_size: 1
+  - name: USB_OTG_FSLPEN
+    description: OTGFS clock enable in low-power mode Set and reset by software.
+    bit_offset: 27
+    bit_size: 1
+  - name: ADFLPEN
+    description: ADF clock enable in low-power mode Set and reset by software.
+    bit_offset: 31
+    bit_size: 1
+fieldset/AHB1RSTR:
+  description: RCC AHB1 peripheral reset register.
+  fields:
+  - name: GPDMA1RST
+    description: GPDMA1 blocks reset Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+  - name: ADC12RST
+    description: ADC1 and 2 blocks reset Set and reset by software.
+    bit_offset: 5
+    bit_size: 1
+  - name: ETHRST
+    description: ETH1 block reset Set and reset by software.
+    bit_offset: 15
+    bit_size: 1
+  - name: USB_OTG_HSRST
+    description: OTGHS block reset Set and reset by software.
+    bit_offset: 25
+    bit_size: 1
+  - name: USBPHYCRST
+    description: USBPHYC block reset Set and reset by software.
+    bit_offset: 26
+    bit_size: 1
+  - name: USB_OTG_FSRST
+    description: OTGFS block reset Set and reset by software.
+    bit_offset: 27
+    bit_size: 1
+  - name: ADFRST
+    description: ADF block reset Set and reset by software.
+    bit_offset: 31
+    bit_size: 1
+fieldset/AHB2ENR:
+  description: RCC AHB2 clock enable register.
+  fields:
+  - name: PSSIEN
+    description: PSSI peripheral clocks enable Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: SDMMC2EN
+    description: SDMMC2 and SDMMC2 delay clock enable Set and reset by software.
+    bit_offset: 9
+    bit_size: 1
+  - name: CORDICEN
+    description: CORDIC clock enable Set and reset by software.
+    bit_offset: 14
+    bit_size: 1
+  - name: SRAM1EN
+    description: SRAM1 clock enable Set and reset by software.
+    bit_offset: 29
+    bit_size: 1
+  - name: SRAM2EN
+    description: SRAM2 clock enable Set and reset by software.
+    bit_offset: 30
+    bit_size: 1
+fieldset/AHB2LPENR:
+  description: RCC AHB2 low-power clock enable register.
+  fields:
+  - name: PSSILPEN
+    description: PSSI peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: SDMMC2LPEN
+    description: SDMMC2 and SDMMC2 delay clock enable in low-power mode Set and reset by software.
+    bit_offset: 9
+    bit_size: 1
+  - name: CORDICLPEN
+    description: CORDIC clock enable in low-power mode Set and reset by software.
+    bit_offset: 14
+    bit_size: 1
+  - name: SRAM1LPEN
+    description: SRAM1 clock enable in low-power mode Set and reset by software.
+    bit_offset: 29
+    bit_size: 1
+  - name: SRAM2LPEN
+    description: SRAM2 clock enable in low-power mode Set and reset by software.
+    bit_offset: 30
+    bit_size: 1
+fieldset/AHB2RSTR:
+  description: RCC AHB2 peripheral reset register.
+  fields:
+  - name: PSSIRST
+    description: PSSI block reset Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: SDMMC2RST
+    description: SDMMC2 and SDMMC2 delay blocks reset Set and reset by software.
+    bit_offset: 9
+    bit_size: 1
+  - name: CORDICRST
+    description: CORDIC reset Set and reset by software.
+    bit_offset: 14
+    bit_size: 1
+fieldset/AHB3ENR:
+  description: RCC AHB3 clock enable register.
+  fields:
+  - name: RNGEN
+    description: RNG peripheral clocks enable Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: HASHEN
+    description: HASH peripheral clock enable Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: CRYPEN
+    description: CRYP peripheral clock enable Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: SAESEN
+    description: SAES peripheral clock enable Set and reset by software. This bit controls the enable of the clock delivered to the SAES.
+    bit_offset: 4
+    bit_size: 1
+  - name: PKAEN
+    description: PKA peripheral clock enable Set and reset by software.
+    bit_offset: 6
+    bit_size: 1
+fieldset/AHB3LPENR:
+  description: RCC AHB3 low-power clock enable register.
+  fields:
+  - name: RNGLPEN
+    description: RNG peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: HASHLPEN
+    description: HASH peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: CRYPLPEN
+    description: CRYP peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: SAESLPEN
+    description: SAES peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+  - name: PKALPEN
+    description: PKA peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 6
+    bit_size: 1
+fieldset/AHB3RSTR:
+  description: RCC AHB3 peripheral reset register.
+  fields:
+  - name: RNGRST
+    description: random number generator block reset Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: HASHRST
+    description: HASH block reset Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: CRYPRST
+    description: CRYP block reset Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: SAESRST
+    description: SAES block reset Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+  - name: PKARST
+    description: PKA block reset Set and reset by software.
+    bit_offset: 6
+    bit_size: 1
+fieldset/AHB4ENR:
+  description: RCC AHB4 clock enable register.
+  fields:
+  - name: GPIOAEN
+    description: GPIOA peripheral clock enable Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: GPIOBEN
+    description: GPIOB peripheral clock enable Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: GPIOCEN
+    description: GPIOC peripheral clock enable Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: GPIODEN
+    description: GPIOD peripheral clock enable Set and reset by software.
+    bit_offset: 3
+    bit_size: 1
+  - name: GPIOEEN
+    description: GPIOE peripheral clock enable Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+  - name: GPIOFEN
+    description: GPIOF peripheral clock enable Set and reset by software.
+    bit_offset: 5
+    bit_size: 1
+  - name: GPIOGEN
+    description: GPIOG peripheral clock enable Set and reset by software.
+    bit_offset: 6
+    bit_size: 1
+  - name: GPIOHEN
+    description: GPIOH peripheral clock enable Set and reset by software.
+    bit_offset: 7
+    bit_size: 1
+  - name: GPIOMEN
+    description: GPIOM peripheral clock enable Set and reset by software.
+    bit_offset: 12
+    bit_size: 1
+  - name: GPIONEN
+    description: GPION peripheral clock enable Set and reset by software.
+    bit_offset: 13
+    bit_size: 1
+  - name: GPIOOEN
+    description: GPIOO peripheral clock enable Set and reset by software.
+    bit_offset: 14
+    bit_size: 1
+  - name: GPIOPEN
+    description: GPIOP peripheral clock enable Set and reset by software.
+    bit_offset: 15
+    bit_size: 1
+  - name: CRCEN
+    description: CRC clock enable Set and reset by software.
+    bit_offset: 19
+    bit_size: 1
+  - name: BKPRAMEN
+    description: Backup RAM clock enable Set and reset by software.
+    bit_offset: 28
+    bit_size: 1
+fieldset/AHB4LPENR:
+  description: RCC AHB4 low-power clock enable register.
+  fields:
+  - name: GPIOALPEN
+    description: GPIOA peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: GPIOBLPEN
+    description: GPIOB peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: GPIOCLPEN
+    description: GPIOC peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: GPIODLPEN
+    description: GPIOD peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 3
+    bit_size: 1
+  - name: GPIOELPEN
+    description: GPIOE peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+  - name: GPIOFLPEN
+    description: GPIOF peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 5
+    bit_size: 1
+  - name: GPIOGLPEN
+    description: GPIOG peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 6
+    bit_size: 1
+  - name: GPIOHLPEN
+    description: GPIOH peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 7
+    bit_size: 1
+  - name: GPIOMLPEN
+    description: GPIOM peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 12
+    bit_size: 1
+  - name: GPIONLPEN
+    description: GPION peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 13
+    bit_size: 1
+  - name: GPIOOLPEN
+    description: GPIOO peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 14
+    bit_size: 1
+  - name: GPIOPLPEN
+    description: GPIOP peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 15
+    bit_size: 1
+  - name: CRCLPEN
+    description: CRC clock enable in low-power mode Set and reset by software.
+    bit_offset: 19
+    bit_size: 1
+  - name: BKPRAMLPEN
+    description: Backup RAM clock enable in low-power mode Set and reset by software.
+    bit_offset: 28
+    bit_size: 1
+fieldset/AHB4RSTR:
+  description: RCC AHB4 peripheral reset register.
+  fields:
+  - name: GPIOARST
+    description: GPIOA block reset Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: GPIOBRST
+    description: GPIOB block reset Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: GPIOCRST
+    description: GPIOC block reset Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: GPIODRST
+    description: GPIOD block reset Set and reset by software.
+    bit_offset: 3
+    bit_size: 1
+  - name: GPIOERST
+    description: GPIOE block reset Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+  - name: GPIOFRST
+    description: GPIOF block reset Set and reset by software.
+    bit_offset: 5
+    bit_size: 1
+  - name: GPIOGRST
+    description: GPIOG block reset Set and reset by software.
+    bit_offset: 6
+    bit_size: 1
+  - name: GPIOHRST
+    description: GPIOH block reset Set and reset by software.
+    bit_offset: 7
+    bit_size: 1
+  - name: GPIOMRST
+    description: GPIOM block reset Set and reset by software.
+    bit_offset: 12
+    bit_size: 1
+  - name: GPIONRST
+    description: GPION block reset Set and reset by software.
+    bit_offset: 13
+    bit_size: 1
+  - name: GPIOORST
+    description: GPIOO block reset Set and reset by software.
+    bit_offset: 14
+    bit_size: 1
+  - name: GPIOPRST
+    description: GPIOP block reset Set and reset by software.
+    bit_offset: 15
+    bit_size: 1
+  - name: CRCRST
+    description: CRC block reset Set and reset by software.
+    bit_offset: 19
+    bit_size: 1
+fieldset/AHB5ENR:
+  description: RCC AHB5 clock enable register.
+  fields:
+  - name: HPDMA1EN
+    description: HPDMA1 peripheral clock enable Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: DMA2DEN
+    description: DMA2D peripheral clock enable Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: JPEGEN
+    description: JPEG peripheral clock enable Set and reset by software.
+    bit_offset: 3
+    bit_size: 1
+  - name: FMCEN
+    description: FMC and MCE3 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock.
+    bit_offset: 4
+    bit_size: 1
+  - name: XSPI1EN
+    description: XSPI1 and MCE1 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1.
+    bit_offset: 5
+    bit_size: 1
+  - name: SDMMC1EN
+    description: SDMMC1 and DB_SDMMC1 peripheral clocks enable Set and reset by software.
+    bit_offset: 8
+    bit_size: 1
+  - name: XSPI2EN
+    description: XSPI2 and MCE2 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1.
+    bit_offset: 12
+    bit_size: 1
+  - name: IOMNGREN
+    description: XSPIM peripheral clock enable Set and reset by software.
+    bit_offset: 14
+    bit_size: 1
+  - name: GFXMMUEN
+    description: GFXMMU peripheral clock enable Set and reset by software.
+    bit_offset: 19
+    bit_size: 1
+  - name: GPUEN
+    description: GPU peripheral clock enable Set and reset by software.
+    bit_offset: 20
+    bit_size: 1
+fieldset/AHB5LPENR:
+  description: RCC AHB5 low-power clock enable register.
+  fields:
+  - name: HPDMA1LPEN
+    description: HPDMA1 low-power peripheral clock enable Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: DMA2DLPEN
+    description: DMA2D low-power peripheral clock enable Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: FLITFLPEN
+    description: FLITF low-power peripheral clock enable Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: JPEGLPEN
+    description: JPEG clock enable during Sleep mode Set and reset by software.
+    bit_offset: 3
+    bit_size: 1
+  - name: FMCLPEN
+    description: FMC and MCE3 peripheral clocks enable during Sleep mode Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock.
+    bit_offset: 4
+    bit_size: 1
+  - name: XSPI1LPEN
+    description: XSPI1 and MCE1 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1.
+    bit_offset: 5
+    bit_size: 1
+  - name: SDMMC1LPEN
+    description: SDMMC1 and SDMMC1 delay low-power peripheral clock enable Set and reset by software.
+    bit_offset: 8
+    bit_size: 1
+  - name: XSPI2LPEN
+    description: XSPI2 and MCE2 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1.
+    bit_offset: 12
+    bit_size: 1
+  - name: XSPIMLPEN
+    description: XSPIM low-power peripheral clock enable Set and reset by software.
+    bit_offset: 14
+    bit_size: 1
+  - name: GFXMMULPEN
+    description: GFXMMU low-power peripheral clock enable Set and reset by software.
+    bit_offset: 19
+    bit_size: 1
+  - name: GPULPEN
+    description: GPU low-power peripheral clock enable Set and reset by software.
+    bit_offset: 20
+    bit_size: 1
+  - name: DTCM1LPEN
+    description: DTCM1 low-power peripheral clock enable Set and reset by software.
+    bit_offset: 28
+    bit_size: 1
+  - name: DTCM2LPEN
+    description: DTCM2 low-power peripheral clock enable Set and reset by software.
+    bit_offset: 29
+    bit_size: 1
+  - name: ITCMLPEN
+    description: ITCM low-power peripheral clock enable Set and reset by software.
+    bit_offset: 30
+    bit_size: 1
+  - name: AXISRAMLPEN
+    description: AXISRAM[4:1] low-power peripheral clock enable Set and reset by software.
+    bit_offset: 31
+    bit_size: 1
+fieldset/AHB5RSTR:
+  description: RCC AHB5 peripheral reset register.
+  fields:
+  - name: HPDMA1RST
+    description: HPDMA1 block reset Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: DMA2DRST
+    description: DMA2D block reset Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: JPEGRST
+    description: JPEG block reset Set and reset by software.
+    bit_offset: 3
+    bit_size: 1
+  - name: FMCRST
+    description: FMC and MCE3 blocks reset Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1.
+    bit_offset: 4
+    bit_size: 1
+  - name: XSPI1RST
+    description: XSPI1 and MCE1 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1.
+    bit_offset: 5
+    bit_size: 1
+  - name: SDMMC1RST
+    description: SDMMC1 and DB_SDMMC1 blocks reset Set and reset by software.
+    bit_offset: 8
+    bit_size: 1
+  - name: XSPI2RST
+    description: XSPI2 and MCE2 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1.
+    bit_offset: 12
+    bit_size: 1
+  - name: IOMNGRRST
+    description: XSPIM reset Set and reset by software.
+    bit_offset: 14
+    bit_size: 1
+  - name: GFXMMURST
+    description: GFXMMU block reset Set and reset by software.
+    bit_offset: 19
+    bit_size: 1
+  - name: GPURST
+    description: GPU block reset Set and reset by software.
+    bit_offset: 20
+    bit_size: 1
+fieldset/AHBPERCKSELR:
+  description: RCC AHB peripheral kernel clock selection register.
+  fields:
+  - name: FMCSEL
+    description: FMC kernel clock source selection Set and reset by software.
+    bit_offset: 0
+    bit_size: 2
+    enum: FMCSEL
+  - name: SDMMCSEL
+    description: SDMMC1 and SDMMC2 kernel clock source selection Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+    enum: SDMMCSEL
+  - name: OCTOSPI1SEL
+    description: 'XSPI1 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock.'
+    bit_offset: 4
+    bit_size: 2
+    enum: OCTOSPISEL
+  - name: OCTOSPI2SEL
+    description: 'XSPI2 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock.'
+    bit_offset: 6
+    bit_size: 2
+    enum: OCTOSPISEL
+  - name: USBREFCKSEL
+    description: 'USBPHYC kernel clock frequency selection Set and reset by software. This field is used to indicate to the USBPHYC, the frequency of the reference kernel clock provided to the USBPHYC. others: reserved.'
+    bit_offset: 8
+    bit_size: 4
+    enum: USBREFCKSEL
+  - name: USBPHYCSEL
+    description: USBPHYC kernel clock source selection Set and reset by software.
+    bit_offset: 12
+    bit_size: 2
+    enum: USBPHYCSEL
+  - name: USB_OTG_FSSEL
+    description: OTGFS kernel clock source selection Set and reset by software.
+    bit_offset: 14
+    bit_size: 2
+    enum: USB_OTG_FSSEL
+  - name: ETH_REF_CLK_SEL
+    description: 'Ethernet reference clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
+    bit_offset: 16
+    bit_size: 2
+    enum: ETH_REF_CLK_SEL
+  - name: ETHPHY_CLK_SEL
+    description: Clock source selection for external Ethernet PHY Set and reset by software.
+    bit_offset: 18
+    bit_size: 1
+    enum: ETHPHY_CLK_SEL
+  - name: ADFSEL
+    description: 'ADF kernel clock source selection Set and reset by software. Note: I2S_CKIN is an external clock taken from a pin.'
+    bit_offset: 20
+    bit_size: 3
+    enum: ADFSEL
+  - name: ADCSEL
+    description: 'SAR ADC kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
+    bit_offset: 24
+    bit_size: 2
+    enum: ADCSEL
+  - name: PSSISEL
+    description: PSSI kernel clock source selection Set and reset by software.
+    bit_offset: 27
+    bit_size: 1
+    enum: PSSISEL
+  - name: PERSEL
+    description: per_ck clock source selection.
+    bit_offset: 28
+    bit_size: 2
+    enum: PERSEL
+fieldset/APB1ENR1:
+  description: RCC APB1 clock enable register 1.
+  fields:
+  - name: TIM2EN
+    description: TIM2 peripheral clock enable Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: TIM3EN
+    description: TIM3 peripheral clock enable Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: TIM4EN
+    description: TIM4 peripheral clock enable Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: TIM5EN
+    description: TIM5 peripheral clock enable Set and reset by software.
+    bit_offset: 3
+    bit_size: 1
+  - name: TIM6EN
+    description: TIM6 peripheral clock enable Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+  - name: TIM7EN
+    description: TIM7 peripheral clock enable Set and reset by software.
+    bit_offset: 5
+    bit_size: 1
+  - name: TIM12EN
+    description: TIM12 peripheral clock enable Set and reset by software.
+    bit_offset: 6
+    bit_size: 1
+  - name: TIM13EN
+    description: TIM13 peripheral clock enable Set and reset by software.
+    bit_offset: 7
+    bit_size: 1
+  - name: TIM14EN
+    description: TIM14 peripheral clock enable Set and reset by software.
+    bit_offset: 8
+    bit_size: 1
+  - name: LPTIM1EN
+    description: LPTIM1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to clk_lpt input, and the rcc_pclk1 bus interface clock.
+    bit_offset: 9
+    bit_size: 1
+  - name: WWDGEN
+    description: WWDG clock enable Set by software, and reset by hardware when a system reset occurs.
+    bit_offset: 11
+    bit_size: 1
+  - name: SPI2EN
+    description: SPI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock.
+    bit_offset: 14
+    bit_size: 1
+  - name: SPI3EN
+    description: SPI3 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock.
+    bit_offset: 15
+    bit_size: 1
+  - name: SPDIFRXEN
+    description: SPDIFRX peripheral clocks enable Set and reset by software. The peripheral clocks of the SPDIFRX are the kernel clock selected by SPDIFRXSEL and provided to SPDIFRX_CLK input, and the rcc_pclk1 bus interface clock.
+    bit_offset: 16
+    bit_size: 1
+  - name: USART2EN
+    description: USART2peripheral clocks enable Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock.
+    bit_offset: 17
+    bit_size: 1
+  - name: USART3EN
+    description: USART3 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock.
+    bit_offset: 18
+    bit_size: 1
+  - name: UART4EN
+    description: UART4 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock.
+    bit_offset: 19
+    bit_size: 1
+  - name: UART5EN
+    description: UART5 peripheral clocks enable Set and reset by software.
+    bit_offset: 20
+    bit_size: 1
+  - name: I2C1_I3C1EN
+    description: I2C1/I3C1 peripheral clocks enable Set and reset by software.
+    bit_offset: 21
+    bit_size: 1
+  - name: I2C2EN
+    description: I2C2 peripheral clocks enable Set and reset by software.
+    bit_offset: 22
+    bit_size: 1
+  - name: I2C3EN
+    description: I2C3 peripheral clocks enable Set and reset by software.
+    bit_offset: 23
+    bit_size: 1
+  - name: CECEN
+    description: HDMI-CEC peripheral clock enable Set and reset by software.
+    bit_offset: 27
+    bit_size: 1
+  - name: UART7EN
+    description: UART7 peripheral clocks enable Set and reset by software.
+    bit_offset: 30
+    bit_size: 1
+  - name: UART8EN
+    description: UART8 peripheral clocks enable Set and reset by software.
+    bit_offset: 31
+    bit_size: 1
+fieldset/APB1ENR2:
+  description: RCC APB1 clock enable register 2.
+  fields:
+  - name: CRSEN
+    description: clock recovery system peripheral clock enable Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: MDIOSEN
+    description: MDIOS peripheral clock enable Set and reset by software.
+    bit_offset: 5
+    bit_size: 1
+  - name: FDCANEN
+    description: FDCAN peripheral clock enable Set and reset by software.
+    bit_offset: 8
+    bit_size: 1
+  - name: UCPDEN
+    description: UCPD peripheral clock enable Set and reset by software.
+    bit_offset: 27
+    bit_size: 1
+fieldset/APB1LPENR1:
+  description: RCC APB1 low-power clock enable register 1.
+  fields:
+  - name: TIM2LPEN
+    description: TIM2 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: TIM3LPEN
+    description: TIM3 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: TIM4LPEN
+    description: TIM4 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: TIM5LPEN
+    description: TIM5 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 3
+    bit_size: 1
+  - name: TIM6LPEN
+    description: TIM6 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+  - name: TIM7LPEN
+    description: TIM7 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 5
+    bit_size: 1
+  - name: TIM12LPEN
+    description: TIM12 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 6
+    bit_size: 1
+  - name: TIM13LPEN
+    description: TIM13 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 7
+    bit_size: 1
+  - name: TIM14LPEN
+    description: TIM14 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 8
+    bit_size: 1
+  - name: LPTIM1LPEN
+    description: LPTIM1 peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 9
+    bit_size: 1
+  - name: WWDGLPEN
+    description: WWDG clock enable in low-power mode Set and reset by software.
+    bit_offset: 11
+    bit_size: 1
+  - name: SPI2LPEN
+    description: SPI2 peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 14
+    bit_size: 1
+  - name: SPI3LPEN
+    description: SPI3 peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 15
+    bit_size: 1
+  - name: SPDIFRXLPEN
+    description: SPDIFRX peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 16
+    bit_size: 1
+  - name: USART2LPEN
+    description: USART2 peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 17
+    bit_size: 1
+  - name: USART3LPEN
+    description: USART3 peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 18
+    bit_size: 1
+  - name: UART4LPEN
+    description: UART4 peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 19
+    bit_size: 1
+  - name: UART5LPEN
+    description: UART5 peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 20
+    bit_size: 1
+  - name: I2C1_I3C1LPEN
+    description: I2C1/I3C1 peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 21
+    bit_size: 1
+  - name: I2C2LPEN
+    description: I2C2 peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 22
+    bit_size: 1
+  - name: I2C3LPEN
+    description: I2C3 peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 23
+    bit_size: 1
+  - name: CECLPEN
+    description: HDMI-CEC peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 27
+    bit_size: 1
+  - name: UART7LPEN
+    description: UART7 peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 30
+    bit_size: 1
+  - name: UART8LPEN
+    description: UART8 peripheral clocks enable in low-power mode Set and reset by software.
+    bit_offset: 31
+    bit_size: 1
+fieldset/APB1LPENR2:
+  description: RCC APB1 low-power clock enable register 2.
+  fields:
+  - name: CRSLPEN
+    description: clock recovery system peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: MDIOSLPEN
+    description: MDIOS peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 5
+    bit_size: 1
+  - name: FDCANLPEN
+    description: FDCAN peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 8
+    bit_size: 1
+  - name: UCPDLPEN
+    description: UCPD peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 27
+    bit_size: 1
+fieldset/APB1PERCKSELR:
+  description: RCC APB1 peripherals kernel clock selection register.
+  fields:
+  - name: USART234578SEL
+    description: 'USART2,3, UART4,5,7,8 (APB1) kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
+    bit_offset: 0
+    bit_size: 3
+    enum: USART234578SEL
+  - name: SPI23SEL
+    description: 'SPI/I2S2 and SPI/I2S3 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.'
+    bit_offset: 4
+    bit_size: 3
+    enum: SPI123SEL
+  - name: I2C23SEL
+    description: I2C2, I2C3 kernel clock source selection Set and reset by software.
+    bit_offset: 8
+    bit_size: 2
+    enum: I2CSEL
+  - name: I2C1_I3C1SEL
+    description: I2C1 or I3C1 kernel clock source selection Set and reset by software.
+    bit_offset: 12
+    bit_size: 2
+    enum: I2C1_I3C1SEL
+  - name: LPTIM1SEL
+    description: 'LPTIM1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
+    bit_offset: 16
+    bit_size: 3
+    enum: LPTIM1SEL
+  - name: FDCANSEL
+    description: FDCAN kernel clock source selection.
+    bit_offset: 22
+    bit_size: 2
+    enum: FDCANSEL
+  - name: SPDIFRXSEL
+    description: SPDIFRX kernel clock source selection.
+    bit_offset: 24
+    bit_size: 2
+    enum: SPDIFRXSEL
+  - name: CECSEL
+    description: HDMI-CEC kernel clock source selection Set and reset by software.
+    bit_offset: 28
+    bit_size: 2
+    enum: CECSEL
+fieldset/APB1RSTR1:
+  description: RCC APB1 peripheral reset register 1.
+  fields:
+  - name: TIM2RST
+    description: TIM2 block reset Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: TIM3RST
+    description: TIM3 block reset Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: TIM4RST
+    description: TIM4 block reset Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: TIM5RST
+    description: TIM5 block reset Set and reset by software.
+    bit_offset: 3
+    bit_size: 1
+  - name: TIM6RST
+    description: TIM6 block reset Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+  - name: TIM7RST
+    description: TIM7 block reset Set and reset by software.
+    bit_offset: 5
+    bit_size: 1
+  - name: TIM12RST
+    description: TIM12 block reset Set and reset by software.
+    bit_offset: 6
+    bit_size: 1
+  - name: TIM13RST
+    description: TIM13 block reset Set and reset by software.
+    bit_offset: 7
+    bit_size: 1
+  - name: TIM14RST
+    description: TIM14 block reset Set and reset by software.
+    bit_offset: 8
+    bit_size: 1
+  - name: LPTIM1RST
+    description: LPTIM1 block reset Set and reset by software.
+    bit_offset: 9
+    bit_size: 1
+  - name: SPI2RST
+    description: SPI2S2 block reset Set and reset by software.
+    bit_offset: 14
+    bit_size: 1
+  - name: SPI3RST
+    description: SPI2S3 block reset Set and reset by software.
+    bit_offset: 15
+    bit_size: 1
+  - name: SPDIFRXRST
+    description: SPDIFRX block reset Set and reset by software.
+    bit_offset: 16
+    bit_size: 1
+  - name: USART2RST
+    description: USART2 block reset Set and reset by software.
+    bit_offset: 17
+    bit_size: 1
+  - name: USART3RST
+    description: USART3 block reset Set and reset by software.
+    bit_offset: 18
+    bit_size: 1
+  - name: UART4RST
+    description: UART4 block reset Set and reset by software.
+    bit_offset: 19
+    bit_size: 1
+  - name: UART5RST
+    description: UART5 block reset Set and reset by software.
+    bit_offset: 20
+    bit_size: 1
+  - name: I2C1_I3C1RST
+    description: I2C1/I3C1 block reset Set and reset by software.
+    bit_offset: 21
+    bit_size: 1
+  - name: I2C2RST
+    description: I2C2 block reset Set and reset by software.
+    bit_offset: 22
+    bit_size: 1
+  - name: I2C3RST
+    description: I2C3 block reset Set and reset by software.
+    bit_offset: 23
+    bit_size: 1
+  - name: CECRST
+    description: HDMI-CEC block reset Set and reset by software.
+    bit_offset: 27
+    bit_size: 1
+  - name: UART7RST
+    description: UART7 block reset Set and reset by software.
+    bit_offset: 30
+    bit_size: 1
+  - name: UART8RST
+    description: UART8 block reset Set and reset by software.
+    bit_offset: 31
+    bit_size: 1
+fieldset/APB1RSTR2:
+  description: RCC APB1 peripheral reset register 2.
+  fields:
+  - name: CRSRST
+    description: clock recovery system reset Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: MDIOSRST
+    description: MDIOS block reset Set and reset by software.
+    bit_offset: 5
+    bit_size: 1
+  - name: FDCANRST
+    description: FDCAN block reset Set and reset by software.
+    bit_offset: 8
+    bit_size: 1
+  - name: UCPDRST
+    description: UCPD block reset Set and reset by software.
+    bit_offset: 27
+    bit_size: 1
+fieldset/APB2ENR:
+  description: RCC APB2 clock enable register.
+  fields:
+  - name: TIM1EN
+    description: TIM1 peripheral clock enable Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: USART1EN
+    description: USART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART1SEL, and the pclk2 bus interface clock.
+    bit_offset: 4
+    bit_size: 1
+  - name: SPI1EN
+    description: 'SPI2S1 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI2S1 are: the kernel clock selected by SPI1SEL, and the pclk2 bus interface clock.'
+    bit_offset: 12
+    bit_size: 1
+  - name: SPI4EN
+    description: 'SPI4 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL, and the pclk2 bus interface clock.'
+    bit_offset: 13
+    bit_size: 1
+  - name: TIM15EN
+    description: TIM15 peripheral clock enable Set and reset by software.
+    bit_offset: 16
+    bit_size: 1
+  - name: TIM16EN
+    description: TIM16 peripheral clock enable Set and reset by software.
+    bit_offset: 17
+    bit_size: 1
+  - name: TIM17EN
+    description: TIM17 peripheral clock enable Set and reset by software.
+    bit_offset: 18
+    bit_size: 1
+  - name: TIM9EN
+    description: TIM9 peripheral clock enable Set and reset by software.
+    bit_offset: 19
+    bit_size: 1
+  - name: SPI5EN
+    description: SPI5 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL, and the pclk2 bus interface clock.
+    bit_offset: 20
+    bit_size: 1
+  - name: SAI1EN
+    description: SAI1 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI1 are the kernel clock selected by SAI1SEL, and the pclk2 bus interface clock.
+    bit_offset: 22
+    bit_size: 1
+  - name: SAI2EN
+    description: SAI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI2 are the kernel clock selected by SAI2SEL, and the pclk2 bus interface clock.
+    bit_offset: 23
+    bit_size: 1
+fieldset/APB2LPENR:
+  description: RCC APB2 low-power clock enable register.
+  fields:
+  - name: TIM1LPEN
+    description: TIM1 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: USART1LPEN
+    description: USART1 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART169SEL and provided to UCLK inputs, and the pclk2 bus interface clock.
+    bit_offset: 4
+    bit_size: 1
+  - name: SPI1LPEN
+    description: 'SPI2S1 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the SPI2S1 are: the kernel clock selected by I2S1SEL and provided to spi_ker_ck input, and the pclk2 bus interface clock.'
+    bit_offset: 12
+    bit_size: 1
+  - name: SPI4LPEN
+    description: 'SPI4 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to com_clk input, and the pclk2 bus interface clock.'
+    bit_offset: 13
+    bit_size: 1
+  - name: TIM15LPEN
+    description: TIM15 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 16
+    bit_size: 1
+  - name: TIM16LPEN
+    description: TIM16 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 17
+    bit_size: 1
+  - name: TIM17LPEN
+    description: TIM17 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 18
+    bit_size: 1
+  - name: TIM9LPEN
+    description: TIM9 peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 19
+    bit_size: 1
+  - name: SPI5LPEN
+    description: SPI5 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to com_clk input, and the pclk2 bus interface clock.
+    bit_offset: 20
+    bit_size: 1
+  - name: SAI1LPEN
+    description: 'SAI1 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to SAI_CK_A and SAI_CK_B inputs, and the pclk2 bus interface clock.'
+    bit_offset: 22
+    bit_size: 1
+  - name: SAI2LPEN
+    description: 'SAI2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SAI2 are: the kernel clock selected by SAI2SEL and provided to SAI_CK_A and SAI_CK_B inputs, and the pclk2 bus interface clock.'
+    bit_offset: 23
+    bit_size: 1
+fieldset/APB2PERCKSELR:
+  description: RCC APB2 peripherals kernel clock selection register.
+  fields:
+  - name: USART1SEL
+    description: 'USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
+    bit_offset: 0
+    bit_size: 3
+    enum: USART1SEL
+  - name: SPI45SEL
+    description: 'SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
+    bit_offset: 4
+    bit_size: 3
+    enum: SPI45SEL
+  - name: SPI1SEL
+    description: 'SPI/I2S1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.'
+    bit_offset: 8
+    bit_size: 3
+    enum: SPI123SEL
+  - name: SAI1SEL
+    description: 'SAI1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.'
+    bit_offset: 16
+    bit_size: 3
+    enum: SAI1SEL
+  - name: SAI2SEL
+    description: 'SAI2 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see Figure 51).'
+    bit_offset: 20
+    bit_size: 3
+    enum: SAI2SEL
+fieldset/APB2RSTR:
+  description: RCC APB2 peripheral reset register.
+  fields:
+  - name: TIM1RST
+    description: TIM1 block reset Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: USART1RST
+    description: USART1 block reset Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+  - name: SPI1RST
+    description: SPI2S1 block reset Set and reset by software.
+    bit_offset: 12
+    bit_size: 1
+  - name: SPI4RST
+    description: SPI4 block reset Set and reset by software.
+    bit_offset: 13
+    bit_size: 1
+  - name: TIM15RST
+    description: TIM15 block reset Set and reset by software.
+    bit_offset: 16
+    bit_size: 1
+  - name: TIM16RST
+    description: TIM16 block reset Set and reset by software.
+    bit_offset: 17
+    bit_size: 1
+  - name: TIM17RST
+    description: TIM17 block reset Set and reset by software.
+    bit_offset: 18
+    bit_size: 1
+  - name: TIM9RST
+    description: TIM9 block reset Set and reset by software.
+    bit_offset: 19
+    bit_size: 1
+  - name: SPI5RST
+    description: SPI5 block reset Set and reset by software.
+    bit_offset: 20
+    bit_size: 1
+  - name: SAI1RST
+    description: SAI1 block reset Set and reset by software.
+    bit_offset: 22
+    bit_size: 1
+  - name: SAI2RST
+    description: SAI2 block reset Set and reset by software.
+    bit_offset: 23
+    bit_size: 1
+fieldset/APB45PERCKSELR:
+  description: RCC APB4,5 peripherals kernel clock selection register.
+  fields:
+  - name: LPUART1SEL
+    description: 'LPUART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
+    bit_offset: 0
+    bit_size: 3
+    enum: LPUARTSEL
+  - name: SPI6SEL
+    description: 'SPI/I2S6 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
+    bit_offset: 4
+    bit_size: 3
+    enum: SPI6SEL
+  - name: LPTIM23SEL
+    description: 'LPTIM2 and LPTIM3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
+    bit_offset: 8
+    bit_size: 3
+    enum: LPTIMSEL
+  - name: LPTIM45SEL
+    description: 'LPTIM4, and LPTIM5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
+    bit_offset: 12
+    bit_size: 3
+    enum: LPTIMSEL
+fieldset/APB4ENR:
+  description: RCC APB4 clock enable register.
+  fields:
+  - name: SYSCFGEN
+    description: SBS peripheral clock enable Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: LPUART1EN
+    description: LPUART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to UCLK input, and the pclk4 bus interface clock.
+    bit_offset: 3
+    bit_size: 1
+  - name: SPI6EN
+    description: SPI/I2S6 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI/I2S6 are the kernel clock selected by SPI6SEL and provided to com_clk input, and the pclk4 bus interface clock.
+    bit_offset: 5
+    bit_size: 1
+  - name: LPTIM2EN
+    description: LPTIM2 peripheral clocks enable Set and reset by software. The LPTIM2 kernel clock can be selected by LPTIM23SEL.
+    bit_offset: 9
+    bit_size: 1
+  - name: LPTIM3EN
+    description: LPTIM3 peripheral clocks enable Set and reset by software. The LPTIM3 kernel clock can be selected by LPTIM23SEL.
+    bit_offset: 10
+    bit_size: 1
+  - name: LPTIM4EN
+    description: LPTIM4 peripheral clocks enable Set and reset by software. The LPTIM4 kernel clock can be selected by LPTIM45SEL.
+    bit_offset: 11
+    bit_size: 1
+  - name: LPTIM5EN
+    description: LPTIM5 peripheral clocks enable Set and reset by software. The LPTIM5 kernel clock can be selected by LPTIM45SEL.
+    bit_offset: 12
+    bit_size: 1
+  - name: VREFEN
+    description: VREF peripheral clock enable Set and reset by software.
+    bit_offset: 15
+    bit_size: 1
+  - name: RTCAPBEN
+    description: RTC APB clock enable Set and reset by software.
+    bit_offset: 16
+    bit_size: 1
+  - name: TMPSENSEN
+    description: Temperature Sensor peripheral clock enable Set and reset by software.
+    bit_offset: 26
+    bit_size: 1
+fieldset/APB4LPENR:
+  description: RCC APB4 low-power clock enable register.
+  fields:
+  - name: SYSCFGLPEN
+    description: SBS peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: LPUART1LPEN
+    description: LPUART1 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to UCLK input, and the rcc_pclk4 bus interface clock.
+    bit_offset: 3
+    bit_size: 1
+  - name: SPI6LPEN
+    description: SPI/I2S6 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SPI/I2S6 are the kernel clock selected by SPI6SEL and provided to com_ck input, and the rcc_pclk4 bus interface clock.
+    bit_offset: 5
+    bit_size: 1
+  - name: LPTIM2LPEN
+    description: LPTIM2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM23SEL and provided to clk_lpt input, and the pclk4 bus interface clock.
+    bit_offset: 9
+    bit_size: 1
+  - name: LPTIM3LPEN
+    description: LPTIM3 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM23SEL and provided to clk_lpt input, and the pclk4 bus interface clock.
+    bit_offset: 10
+    bit_size: 1
+  - name: LPTIM4LPEN
+    description: LPTIM4 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM4 are the kernel clock selected by LPTIM45SEL and provided to clk_lpt input, and the pclk4 bus interface clock.
+    bit_offset: 11
+    bit_size: 1
+  - name: LPTIM5LPEN
+    description: LPTIM5 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM5 are the kernel clock selected by LPTIM45SEL and provided to clk_lpt input, and the pclk4 bus interface clock.
+    bit_offset: 12
+    bit_size: 1
+  - name: VREFLPEN
+    description: VREF peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 15
+    bit_size: 1
+  - name: RTCAPBLPEN
+    description: RTC APB clock enable in low-power mode Set and reset by software.
+    bit_offset: 16
+    bit_size: 1
+  - name: TMPSENSLPEN
+    description: temperature sensor peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 26
+    bit_size: 1
+fieldset/APB4RSTR:
+  description: RCC APB4 peripheral reset register.
+  fields:
+  - name: SYSCFGRST
+    description: SBS block reset Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: LPUART1RST
+    description: LPUART1 block reset Set and reset by software.
+    bit_offset: 3
+    bit_size: 1
+  - name: SPI6RST
+    description: SPI/I2S6 block reset Set and reset by software.
+    bit_offset: 5
+    bit_size: 1
+  - name: LPTIM2RST
+    description: LPTIM2 block reset Set and reset by software.
+    bit_offset: 9
+    bit_size: 1
+  - name: LPTIM3RST
+    description: LPTIM3 block reset Set and reset by software.
+    bit_offset: 10
+    bit_size: 1
+  - name: LPTIM4RST
+    description: LPTIM4 block reset Set and reset by software.
+    bit_offset: 11
+    bit_size: 1
+  - name: LPTIM5RST
+    description: LPTIM5 block reset Set and reset by software.
+    bit_offset: 12
+    bit_size: 1
+  - name: VREFRST
+    description: VREF block reset Set and reset by software.
+    bit_offset: 15
+    bit_size: 1
+  - name: TMPSENSRST
+    description: TMPSENS block reset Set and reset by software.
+    bit_offset: 26
+    bit_size: 1
+fieldset/APB5ENR:
+  description: RCC APB5 clock enable register.
+  fields:
+  - name: LTDCEN
+    description: LTDC peripheral clock enable Provides the pixel clock (ltdc_clk) to the LTDC block. Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: DCMIPPEN
+    description: DCMIPP peripheral clock enable Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: GFXTIMEN
+    description: GFXTIM peripheral clock enable Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+fieldset/APB5LPENR:
+  description: RCC APB5 sleep clock register.
+  fields:
+  - name: LTDCLPEN
+    description: LTDC peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: DCMIPPLPEN
+    description: DCMIPP peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: GFXTIMLPEN
+    description: GFXTIM peripheral clock enable in low-power mode Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+fieldset/APB5RSTR:
+  description: RCC APB5 peripheral reset register.
+  fields:
+  - name: LTDCRST
+    description: LTDC block reset Set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: DCMIPPRST
+    description: DCMIPP block reset Set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: GFXTIMRST
+    description: GFXTIM block reset Set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+fieldset/APBCFGR:
+  description: RCC APB clocks configuration register.
+  fields:
+  - name: PPRE1
+    description: 'CPU domain APB1 prescaler Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE1 write. 0xx: rcc_pclk1 = sys_bus_ck (default after reset).'
+    bit_offset: 0
+    bit_size: 3
+    enum: PPRE
+  - name: PPRE2
+    description: 'CPU domain APB2 prescaler Set and reset by software to control the division factor of rcc_pclk2. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE2 write. 0xx: rcc_pclk2 = sys_bus_ck (default after reset).'
+    bit_offset: 4
+    bit_size: 3
+    enum: PPRE
+  - name: PPRE4
+    description: 'CPU domain APB4 prescaler Set and reset by software to control the division factor of rcc_pclk4. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE4 write. 0xx: rcc_pclk4 = sys_bus_ck (default after reset).'
+    bit_offset: 8
+    bit_size: 3
+    enum: PPRE
+  - name: PPRE5
+    description: 'CPU domain APB5 prescaler Set and reset by software to control the division factor of rcc_pclk5. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE5 write. 0xx: rcc_pclk5 = sys_bus_ck (default after reset).'
+    bit_offset: 12
+    bit_size: 3
+    enum: PPRE
+fieldset/BDCR:
+  description: RCC Backup domain control register.
+  fields:
+  - name: LSEON
+    description: LSE oscillator enabled Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: LSERDY
+    description: LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0.
+    bit_offset: 1
+    bit_size: 1
+  - name: LSEBYP
+    description: LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1).
+    bit_offset: 2
+    bit_size: 1
+  - name: LSEDRV
+    description: LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator.
+    bit_offset: 3
+    bit_size: 2
+    enum: LSEDRV
+  - name: LSECSSON
+    description: LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit can only be disabled, After a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON. After a back-up domain reset.
+    bit_offset: 5
+    bit_size: 1
+  - name: LSECSSD
+    description: LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator.
+    bit_offset: 6
+    bit_size: 1
+  - name: LSEEXT
+    description: low-speed external clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled.
+    bit_offset: 7
+    bit_size: 1
+  - name: RTCSEL
+    description: RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST).
+    bit_offset: 8
+    bit_size: 2
+    enum: RTCSEL
+  - name: LSECSSRA
+    description: 'Re-Arm the LSECSS function Set by software. After a LSE failure detection, the software application can re-enable the LSECSS by writing this bit to 1. Reading this bit returns the written value. Prior to set this bit to 1, LSECSSON must be set to 0. Please refer to Section : CSS on LSE for details.'
+    bit_offset: 12
+    bit_size: 1
+  - name: RTCEN
+    description: RTC clock enable Set and reset by software.
+    bit_offset: 15
+    bit_size: 1
+  - name: VSWRST
+    description: VSwitch domain software reset Set and reset by software. To generate a VSW reset, it is recommended to write this bit to 1, then back to 0.
+    bit_offset: 16
+    bit_size: 1
+fieldset/BMCFGR:
+  description: RCC AHB clock configuration register.
+  fields:
+  - name: BMPRE
+    description: 'Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk[5:1] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk[5:1] = rcc_aclk = sys_bus_ck.'
+    bit_offset: 0
+    bit_size: 4
+    enum: HPRE
+fieldset/CDCFGR:
+  description: RCC CPU domain clock configuration register.
+  fields:
+  - name: CPRE
+    description: 'CPU domain core prescaler Set and reset by software to control the CPU clock division factor. Changing this division ratio has an impact on the frequency of the CPU clock and all bus matrix clocks. After changing this prescaler value, it takes up to 16 periods of the slowest APB clock before the new division ratio is taken into account. The application can check if the new division factor is taken into account by reading back this register. 0xxx: sys_ck not divided (default after reset).'
+    bit_offset: 0
+    bit_size: 4
+    enum: HPRE
+fieldset/CFGR:
+  description: RCC clock configuration register.
+  fields:
+  - name: SW
+    description: 'system clock switch Set and reset by software to select system clock source (sys_ck). Set by hardware in order to force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode or in case of failure of the HSE when used directly or indirectly as system clock. others: reserved.'
+    bit_offset: 0
+    bit_size: 3
+    enum: SW
+  - name: SWS
+    description: 'system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. others: reserved.'
+    bit_offset: 3
+    bit_size: 3
+    enum: SW
+  - name: STOPWUCK
+    description: 'system clock selection after a wake up from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details. STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10).'
+    bit_offset: 6
+    bit_size: 1
+    enum: STOPWUCK
+  - name: STOPKERWUCK
+    description: 'kernel clock selection after a wake up from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details.'
+    bit_offset: 7
+    bit_size: 1
+    enum: STOPKERWUCK
+  - name: RTCPRE
+    description: 'HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ...'
+    bit_offset: 8
+    bit_size: 6
+  - name: TIMPRE
+    description: 'timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. or 4, else it is equal to 4 x F<sub>rcc_pclkx_d2</sub> Refer to Table 64: Ratio between clock timer and pclk for more details.'
+    bit_offset: 15
+    bit_size: 1
+    enum: TIMPRE
+  - name: MCO1PRE
+    description: MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ...
+    bit_offset: 18
+    bit_size: 4
+    enum: MCOPRE
+  - name: MCO1SEL
+    description: 'Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved.'
+    bit_offset: 22
+    bit_size: 3
+    enum: MCO1SEL
+  - name: MCO2PRE
+    description: MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ...
+    bit_offset: 25
+    bit_size: 4
+    enum: MCOPRE
+  - name: MCO2SEL
+    description: 'microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved.'
+    bit_offset: 29
+    bit_size: 3
+    enum: MCO2SEL
+fieldset/CICR:
+  description: RCC clock source interrupt clear register.
+  fields:
+  - name: LSIRDYC
+    description: LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done.
+    bit_offset: 0
+    bit_size: 1
+  - name: LSERDYC
+    description: LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done.
+    bit_offset: 1
+    bit_size: 1
+  - name: HSIRDYC
+    description: HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done.
+    bit_offset: 2
+    bit_size: 1
+  - name: HSERDYC
+    description: HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done.
+    bit_offset: 3
+    bit_size: 1
+  - name: CSIRDYC
+    description: CSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done.
+    bit_offset: 4
+    bit_size: 1
+  - name: HSI48RDYC
+    description: HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done.
+    bit_offset: 5
+    bit_size: 1
+  - name: PLLRDYC
+    description: PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done.
+    bit_offset: 6
+    bit_size: 1
+    array:
+      len: 3
+      stride: 1
+  - name: LSECSSC
+    description: LSE clock security system interrupt clear Set by software to clear LSECSSF. Reset by hardware when clear done.
+    bit_offset: 9
+    bit_size: 1
+  - name: HSECSSC
+    description: HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done.
+    bit_offset: 10
+    bit_size: 1
+fieldset/CIER:
+  description: RCC clock source interrupt enable register.
+  fields:
+  - name: LSIRDYIE
+    description: LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization.
+    bit_offset: 0
+    bit_size: 1
+  - name: LSERDYIE
+    description: LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization.
+    bit_offset: 1
+    bit_size: 1
+  - name: HSIRDYIE
+    description: HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization.
+    bit_offset: 2
+    bit_size: 1
+  - name: HSERDYIE
+    description: HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization.
+    bit_offset: 3
+    bit_size: 1
+  - name: CSIRDYIE
+    description: CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization.
+    bit_offset: 4
+    bit_size: 1
+  - name: HSI48RDYIE
+    description: HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization.
+    bit_offset: 5
+    bit_size: 1
+  - name: PLLRDYIE
+    description: PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock.
+    bit_offset: 6
+    bit_size: 1
+    array:
+      len: 3
+      stride: 1
+  - name: LSECSSIE
+    description: LSE clock security system interrupt enable Set and reset by software to enable/disable interrupt caused by the clock security system (CSS) on external 32 kHz oscillator.
+    bit_offset: 9
+    bit_size: 1
+fieldset/CIFR:
+  description: RCC clock source interrupt flag register.
+  fields:
+  - name: LSIRDYF
+    description: LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.
+    bit_offset: 0
+    bit_size: 1
+  - name: LSERDYF
+    description: LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set.
+    bit_offset: 1
+    bit_size: 1
+  - name: HSIRDYF
+    description: HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set.
+    bit_offset: 2
+    bit_size: 1
+  - name: HSERDYF
+    description: HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set.
+    bit_offset: 3
+    bit_size: 1
+  - name: CSIRDYF
+    description: CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set.
+    bit_offset: 4
+    bit_size: 1
+  - name: HSI48RDYF
+    description: HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.
+    bit_offset: 5
+    bit_size: 1
+  - name: PLLRDYF
+    description: PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set.
+    bit_offset: 6
+    bit_size: 1
+    array:
+      len: 3
+      stride: 1
+  - name: LSECSSF
+    description: LSE clock security system interrupt flag Reset by software by writing LSECSSC bit. Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set.
+    bit_offset: 9
+    bit_size: 1
+  - name: HSECSSF
+    description: HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure.
+    bit_offset: 10
+    bit_size: 1
+fieldset/CKGDISR:
+  description: RCC AXI clocks gating disable register.
+  fields:
+  - name: AXICKG
+    description: AXI interconnect matrix clock gating disable This bit is set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: AHBMCKG
+    description: AXI master AHB clock gating disable This bit is set and reset by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: SDMMC1CKG
+    description: AXI master SDMMC1 clock gating disable This bit is set and reset by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: HPDMA1CKG
+    description: AXI master HPDMA1 clock gating disable This bit is set and reset by software.
+    bit_offset: 3
+    bit_size: 1
+  - name: CPUCKG
+    description: AXI master CPU clock gating disable This bit is set and reset by software.
+    bit_offset: 4
+    bit_size: 1
+  - name: GPUS0CKG
+    description: AXI master 0 GPU clock gating disable This bit is set and reset by software.
+    bit_offset: 5
+    bit_size: 1
+  - name: GPUS1CKG
+    description: AXI master 1 GPU clock gating disable This bit is set and reset by software.
+    bit_offset: 6
+    bit_size: 1
+  - name: GPUCLCKG
+    description: AXI master cache GPU clock gating disable This bit is set and reset by software.
+    bit_offset: 7
+    bit_size: 1
+  - name: DCMIPPCKG
+    description: AXI master DCMIPP clock gating disable This bit is set and reset by software.
+    bit_offset: 8
+    bit_size: 1
+  - name: DMA2DCKG
+    description: AXI master DMA2D clock gating disable This bit is set and reset by software.
+    bit_offset: 9
+    bit_size: 1
+  - name: GFXMMUSCKG
+    description: AXI matrix slave GFXMMU clock gating disable This bit is set and reset by software.
+    bit_offset: 10
+    bit_size: 1
+  - name: LTDCCKG
+    description: AXI master LTDC clock gating disable This bit is set and reset by software.
+    bit_offset: 11
+    bit_size: 1
+  - name: GFXMMUMCKG
+    description: AXI master GFXMMU clock gating disable This bit is set and reset by software.
+    bit_offset: 12
+    bit_size: 1
+  - name: AHBSCKG
+    description: AXI slave AHB clock gating disable This bit is set and reset by software.
+    bit_offset: 13
+    bit_size: 1
+  - name: FMCCKG
+    description: AXI slave FMC and MCE3 clock gating disable This bit is set and reset by software.
+    bit_offset: 14
+    bit_size: 1
+  - name: XSPI1CKG
+    description: AXI slave XSPI1 and MCE1 clock gating disable This bit is set and reset by software.
+    bit_offset: 15
+    bit_size: 1
+  - name: XSPI2CKG
+    description: AXI slave XSPI2 and MCE2 clock gating disable This bit is set and reset by software.
+    bit_offset: 16
+    bit_size: 1
+  - name: AXIRAM4CKG
+    description: AXI matrix slave SRAM4 clock gating disable This bit is set and reset by software.
+    bit_offset: 17
+    bit_size: 1
+  - name: AXIRAM3CKG
+    description: AXI matrix slave SRAM3 clock gating disable This bit is set and reset by software.
+    bit_offset: 18
+    bit_size: 1
+  - name: AXIRAM2CKG
+    description: AXI slave SRAM2 clock gating disable This bit is set and reset by software.
+    bit_offset: 19
+    bit_size: 1
+  - name: AXIRAM1CKG
+    description: AXI slave SRAM1 / error code correction (ECC) clock gating disable This bit is set and reset by software.
+    bit_offset: 20
+    bit_size: 1
+  - name: FLITFCKG
+    description: AXI slave Flash interface (FLIFT) clock gating disable This bit is set and reset by software.
+    bit_offset: 21
+    bit_size: 1
+  - name: EXTICKG
+    description: EXTI clock gating disable This bit is set and reset by software.
+    bit_offset: 30
+    bit_size: 1
+  - name: JTAGCKG
+    description: JTAG automatic clock gating disabling This bit is set and reset by software.
+    bit_offset: 31
+    bit_size: 1
+fieldset/CKPROTR:
+  description: RCC clock protection register.
+  fields:
+  - name: XSPICKP
+    description: 'XSPI clock protection Set and cleared by software. When set to 1, this bit prevents disabling accidentally the XSPIs. The following fields cannot be modified when this bit is set to 1: PLL2ON, PLL2DIVSEN, PLL2DIVTEN, HSEON, HSION, CSION, XSPIxEN, OCTOSPIxLPEN, OCTOSPIxRST.'
+    bit_offset: 0
+    bit_size: 1
+  - name: FMCCKP
+    description: 'FMC clock protection Set and cleared by software. When set to 1, this bit prevents disabling accidentally the FMC. The following fields cannot be modified when this bit is set to 1: PLL1ON, PLL2ON, PLL1DIVQEN, PLL2DIVREN, HSEON, HSION, CSION, FMCEN, FMCLPEN, FMCRST.'
+    bit_offset: 1
+    bit_size: 1
+  - name: XSPI1SWP
+    description: XSPI1 kernel clock switch position Set by hardware. This field can be used to verify the real position of XSPI2 kernel switch selector.
+    bit_offset: 4
+    bit_size: 3
+    enum: XSPISWP
+  - name: XSPI2SWP
+    description: XSPI2 kernel clock switch position Set by hardware. This field can be used to verify the real position of XSPI2 kernel switch selector.
+    bit_offset: 8
+    bit_size: 3
+    enum: XSPISWP
+  - name: FMCSWP
+    description: FMC kernel clock switch position Set by hardware. This field can be used to verify the real position of FMC kernel switch selector.
+    bit_offset: 12
+    bit_size: 3
+    enum: FMCSWP
+fieldset/CR:
+  description: RCC source control register.
+  fields:
+  - name: HSION
+    description: HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 0 or STOPKERWUCK = 0. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW switch) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1.
+    bit_offset: 0
+    bit_size: 1
+  - name: HSIKERON
+    description: HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION.
+    bit_offset: 1
+    bit_size: 1
+  - name: HSIRDY
+    description: HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable.
+    bit_offset: 2
+    bit_size: 1
+  - name: HSIDIV
+    description: HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored.
+    bit_offset: 3
+    bit_size: 2
+    enum: HSIDIV
+  - name: HSIDIVF
+    description: HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. clock setting is completed).
+    bit_offset: 5
+    bit_size: 1
+  - name: CSION
+    description: CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1.
+    bit_offset: 7
+    bit_size: 1
+  - name: CSIRDY
+    description: CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request).
+    bit_offset: 8
+    bit_size: 1
+  - name: CSIKERON
+    description: CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION.
+    bit_offset: 9
+    bit_size: 1
+  - name: HSI48ON
+    description: HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode.
+    bit_offset: 12
+    bit_size: 1
+  - name: HSI48RDY
+    description: HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable.
+    bit_offset: 13
+    bit_size: 1
+  - name: HSEON
+    description: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1.
+    bit_offset: 16
+    bit_size: 1
+  - name: HSERDY
+    description: HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable.
+    bit_offset: 17
+    bit_size: 1
+  - name: HSEBYP
+    description: HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
+    bit_offset: 18
+    bit_size: 1
+  - name: HSEEXT
+    description: external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled.
+    bit_offset: 19
+    bit_size: 1
+    enum: HSEEXT
+  - name: HSECSSON
+    description: HSE clock security system enable Set by software to enable clock security system on HSE. This bit is set only (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected.
+    bit_offset: 20
+    bit_size: 1
+  - name: PLLON
+    description: PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3) or if FMCCKP = 1, or if XSPICKP = 1.
+    bit_offset: 24
+    bit_size: 1
+    array:
+      len: 3
+      stride: 2
+  - name: PLLRDY
+    description: PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked.
+    bit_offset: 25
+    bit_size: 1
+    array:
+      len: 3
+      stride: 2
+enum/HSEEXT:
+  bit_size: 1
+  variants:
+  - name: Analog
+    description: HSE in analog mode (default after reset)
+    value: 0
+  - name: Digital
+    description: HSE in digital mode
+    value: 1
+fieldset/CRRCR:
+  description: RCC clock recovery RC register.
+  fields:
+  - name: HSI48CAL
+    description: Internal RC 48 MHz clock calibration Set by hardware by option byte loading. Read-only.
+    bit_offset: 0
+    bit_size: 10
+fieldset/CSICFGR:
+  description: RCC CSI calibration register.
+  fields:
+  - name: CSICAL
+    description: CSI clock calibration Set by hardware by option byte loading. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value.
+    bit_offset: 0
+    bit_size: 8
+  - name: CSITRIM
+    description: 'CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_opt) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_opt. Note: The reset value of the field is 0x20.'
+    bit_offset: 24
+    bit_size: 6
+fieldset/CSR:
+  description: RCC clock control and status register.
+  fields:
+  - name: LSION
+    description: LSI oscillator enable Set and reset by software.
+    bit_offset: 0
+    bit_size: 1
+  - name: LSIRDY
+    description: LSI oscillator ready Set and reset by hardware to indicate when the low-speed internal RC oscillator is stable. This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to 0. This bit can be set even when LSION is not enabled if there is a request for LSI clock by the clock security system on LSE or by the low-speed watchdog or by the RTC.
+    bit_offset: 1
+    bit_size: 1
+fieldset/HSICFGR:
+  description: RCC HSI calibration register.
+  fields:
+  - name: HSICAL
+    description: HSI clock calibration Set by hardware by option byte loading. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value.
+    bit_offset: 0
+    bit_size: 12
+  - name: HSITRIM
+    description: 'HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_opt) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_opt. Note: The reset value of the field is 0x40.'
+    bit_offset: 24
+    bit_size: 7
+fieldset/PLLCFGR:
+  description: RCC PLLs configuration register.
+  fields:
+  - name: PLLFRACEN
+    description: PLL1 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 3
+      stride: 11
+  - name: PLLVCOSEL
+    description: 'PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (F<sub>ref1_ck</sub> must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (F<sub>ref1_ck</sub> must be between 1 and 2 MHz).'
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 3
+      stride: 11
+    enum: PLLVCOSEL
+  - name: PLLSSCGEN
+    description: PLL1 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks.
+    bit_offset: 2
+    bit_size: 1
+    array:
+      len: 3
+      stride: 11
+  - name: PLLRGE
+    description: PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1.
+    bit_offset: 3
+    bit_size: 2
+    array:
+      len: 3
+      stride: 11
+    enum: PLLRGE
+  - name: DIVPEN
+    description: PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled.
+    bit_offset: 5
+    bit_size: 1
+    array:
+      len: 3
+      stride: 11
+  - name: DIVQEN
+    description: PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. The hardware prevents writing this bit if FMCCKP = 1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.
+    bit_offset: 6
+    bit_size: 1
+    array:
+      len: 3
+      stride: 11
+  - name: DIVREN
+    description: PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1DIVREN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used.
+    bit_offset: 7
+    bit_size: 1
+    array:
+      len: 3
+      stride: 11
+  - name: DIVSEN
+    description: PLL1 DIVS divider output enable Set and reset by software to enable the pll1_s_ck output of the PLL1. To save power, PLL1DIVSEN must be set to 0 when the pll1_s_ck is not used.
+    bit_offset: 8
+    bit_size: 1
+    array:
+      len: 3
+      stride: 11
+  - name: DIVTEN
+    description: PLL1 DIVT divider output enable Set and reset by software to enable the pll1_t_ck output of the PLL1. To save power, PLL1DIVTEN must be set to 0 when the pll1_t_ck is not used.
+    bit_offset: 9
+    bit_size: 1
+    array:
+      len: 3
+      stride: 11
+fieldset/PLLCKSELR:
+  description: RCC PLLs clock source selection register.
+  fields:
+  - name: PLLSRC
+    description: DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, PLLSRC must be set to 11.
+    bit_offset: 0
+    bit_size: 2
+    enum: PLLSRC
+  - name: DIVM
+    description: prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ...
+    bit_offset: 4
+    bit_size: 6
+    array:
+      len: 3
+      stride: 8
+    enum: PLLM
+fieldset/PLLDIVR:
+  description: RCC PLL1 dividers configuration register 1.
+  fields:
+  - name: PLLN
+    description: 'multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = PLL1RDY = 0). ..........: not used ... ... Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = F<sub>ref1_ck</sub> x DIVN1, when fractional value 0 has been loaded into FRACN, with: DIVN1 between 8 and 420 The input frequency F<sub>ref1_ck</sub> must be between 1 and 16 MHz.'
+    bit_offset: 0
+    bit_size: 9
+    enum: PLLN
+  - name: PLLP
+    description: PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1DIVPEN = 0. ...
+    bit_offset: 9
+    bit_size: 7
+    enum: PLLDIV
+  - name: PLLQ
+    description: PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1DIVQEN = 0. ...
+    bit_offset: 16
+    bit_size: 7
+    enum: PLLDIV
+  - name: PLLR
+    description: PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1DIVREN = 0. ...
+    bit_offset: 24
+    bit_size: 7
+    enum: PLLDIV
+fieldset/PLLDIVR2:
+  description: RCC PLL1 dividers configuration register 2.
+  fields:
+  - name: PLLS
+    description: 'PLL1 DIVS division factor Set and reset by software to control the frequency of the pll1_s_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVS+1) is even, With VCOH, for all DIVS values These bits can be written only when the PLL1DIVSEN = 0.'
+    bit_offset: 0
+    bit_size: 3
+    enum: PLLDIVST
+  - name: PLLT
+    description: 'PLL1 DIVT division factor Set and reset by software to control the frequency of the pll1_t_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVT+1) is even, With VCOH, for all DIVT values These bits can be written only when the PLL1DIVTEN = 0.'
+    bit_offset: 8
+    bit_size: 3
+    enum: PLLDIVST
+fieldset/PLLFRACR:
+  description: RCC PLL1 fractional divider register.
+  fields:
+  - name: FRACN
+    description: 'fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544 MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = F<sub>ref1_ck</sub> x (DIVN1 + (FRACN / 2<sup>13</sup>)), with DIVN1 between 8 and 420 FRACN can be between 0 and 2<sup>13</sup>- 1 The input frequency F<sub>ref1_ck</sub> must be between 1 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACLE to 0. Write the new fractional value into FRACN. Set the bit PLL1FRACLE to 1.'
+    bit_offset: 3
+    bit_size: 13
+fieldset/PLLSSCGR:
+  description: RCC PLL1 Spread Spectrum Clock Generator register.
+  fields:
+  - name: MOD_PER
+    description: Modulation Period Adjustment for PLL1 Set and reset by software to adjust the modulation period of the clock spreading generator.
+    bit_offset: 0
+    bit_size: 13
+  - name: TPDFN_DIS1
+    description: Dithering TPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function.
+    bit_offset: 13
+    bit_size: 1
+  - name: RPDFN_DIS1
+    description: Dithering RPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function.
+    bit_offset: 14
+    bit_size: 1
+  - name: DWNSPREAD1
+    description: Spread spectrum clock generator mode for PLL1 Set and reset by software to select the clock spreading mode.
+    bit_offset: 15
+    bit_size: 1
+    enum: DWNSPREAD
+  - name: INC_STEP
+    description: Modulation Depth Adjustment for PLL1 Set and reset by software to adjust the modulation depth of the clock spreading generator.
+    bit_offset: 16
+    bit_size: 15
+fieldset/RSR:
+  description: RCC Reset status register.
+  fields:
+  - name: RMVF
+    description: remove reset flag Set and reset by software to reset the value of the reset flags.
+    bit_offset: 16
+    bit_size: 1
+  - name: OBLRSTF
+    description: Option byte loading reset flag <sup>(1)</sup> Reset by software by the RMVF bit. Set by hardware when a reset from the option byte loading occurs.
+    bit_offset: 17
+    bit_size: 1
+  - name: BORRSTF
+    description: BOR reset flag <sup>(1)</sup> Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst).
+    bit_offset: 21
+    bit_size: 1
+  - name: PINRSTF
+    description: pin reset flag (NRST) <sup>(1)</sup> Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs.
+    bit_offset: 22
+    bit_size: 1
+  - name: PORRSTF
+    description: POR/PDR reset flag <sup>(1)</sup> Reset by software by writing the RMVF bit. Set by hardware when a POR/PDR reset occurs.
+    bit_offset: 23
+    bit_size: 1
+  - name: SFTRSTF
+    description: system reset from CPU reset flag <sup>(1)</sup> Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M7.
+    bit_offset: 24
+    bit_size: 1
+  - name: IWDGRSTF
+    description: independent watchdog reset flag <sup>(1)</sup> Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs.
+    bit_offset: 26
+    bit_size: 1
+  - name: WWDGRSTF
+    description: window watchdog reset flag <sup>(1)</sup> Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs.
+    bit_offset: 28
+    bit_size: 1
+  - name: LPWRRSTF
+    description: reset due to illegal Stop or Standby flag Reset by software by writing the RMVF bit. Set by hardware when the CPU goes erroneously in Stop or Standby mode,.
+    bit_offset: 30
+    bit_size: 1
+enum/ADCSEL:
+  bit_size: 2
+  variants:
+  - name: PLL2_P
+    description: pll2_p selected as peripheral clock
+    value: 0
+  - name: PLL3_R
+    description: pll3_r selected as peripheral clock
+    value: 1
+  - name: PER
+    description: PER selected as peripheral clock
+    value: 2
+enum/ADFSEL:
+  bit_size: 3
+  variants:
+  - name: HCLK1
+    description: hclk1 selected as ADF kernel clock (default after reset).
+    value: 0
+  - name: PLL2_P
+    description: pll2_p_ck selected as ADF kernel clock.
+    value: 1
+enum/HPRE:
+  bit_size: 4
+  variants:
+  - name: Div1
+    value: 0
+  - name: Div2
+    value: 8
+  - name: Div4
+    value: 9
+  - name: Div8
+    value: 10
+  - name: Div16
+    value: 11
+  - name: Div64
+    value: 12
+  - name: Div128
+    value: 13
+  - name: Div256
+    value: 14
+  - name: Div512
+    value: 15
+enum/CECSEL:
+  bit_size: 2
+  variants:
+  - name: LSE
+    description: LSE selected as peripheral clock
+    value: 0
+  - name: LSI
+    description: LSI selected as peripheral clock
+    value: 1
+  - name: CSI
+    description: csi_ker selected as peripheral clock
+    value: 2
+enum/DWNSPREAD:
+  bit_size: 1
+  variants:
+  - name: CenterSpread
+    description: Center-spread modulation selected (default after reset).
+    value: 0
+  - name: DownSpread
+    description: Down-spread modulation selected.
+    value: 1
+enum/ETHPHY_CLK_SEL:
+  bit_size: 1
+  variants:
+  - name: HSE
+    description: hse_ker_ck selected as clock source (default after reset).
+    value: 0
+  - name: PLL3_S
+    description: pll3_s_ck selected clock source.
+    value: 1
+enum/ETH_REF_CLK_SEL:
+  bit_size: 2
+  variants:
+  - name: ETH_RMII_REF
+    description: PAD ETH_RMII_REF_CLK selected as kernel peripheral clock (default after reset).
+    value: 0
+  - name: HSE
+    description: hse_ker_ck selected as kernel peripheral clock.
+    value: 1
+  - name: ETH
+    description: eth_clk_fb selected as kernel peripheral clock.
+    value: 2
+enum/FDCANSEL:
+  bit_size: 2
+  variants:
+  - name: HSE
+    description: HSE selected as peripheral clock
+    value: 0
+  - name: PLL1_Q
+    description: pll1_q selected as peripheral clock
+    value: 1
+  - name: PLL2_P
+    description: pll2_p selected as peripheral clock
+    value: 2
+enum/FMCSEL:
+  bit_size: 2
+  variants:
+  - name: HCLK5
+    description: hclk5 selected as kernel peripheral clock (default after reset).
+    value: 0
+  - name: PLL1_Q
+    description: pll1_q_ck selected as kernel peripheral clock.
+    value: 1
+  - name: PLL2_R
+    description: pll2_r_ck selected as kernel peripheral clock.
+    value: 2
+  - name: HSI
+    description: hsi_ker_ck selected as kernel peripheral clock.
+    value: 3
+enum/FMCSWP:
+  bit_size: 3
+  variants:
+  - name: B_0x0
+    description: The switch is in neutral mode and output clock is gated (default after reset).
+    value: 0
+  - name: B_0x1
+    description: The switch is selecting hclk5.
+    value: 1
+  - name: B_0x2
+    description: The switch is selecting pll1_q_ck.
+    value: 2
+  - name: B_0x3
+    description: The switch is selecting pll2_r_ck.
+    value: 3
+  - name: B_0x4
+    description: The switch is selecting hsi_ker_ck.
+    value: 4
+  - name: B_0x5
+    description: The switch is in recovery position (hclk5/4).
+    value: 5
+enum/HSIDIV:
+  bit_size: 2
+  variants:
+  - name: Div1
+    description: division by 1, hsi(_ker)_ck = 64 MHz (default after reset).
+    value: 0
+  - name: Div2
+    description: division by 2, hsi(_ker)_ck = 32 MHz.
+    value: 1
+  - name: Div4
+    description: division by 4, hsi(_ker)_ck = 16 MHz.
+    value: 2
+  - name: Div8
+    description: division by 8, hsi(_ker)_ck = 8 MHz.
+    value: 3
+enum/I2C1_I3C1SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: rcc_pclk1 selected as peripheral clock
+    value: 0
+  - name: PLL3_R
+    description: pll3_r selected as peripheral clock
+    value: 1
+  - name: HSI
+    description: hsi_ker selected as peripheral clock
+    value: 2
+  - name: CSI
+    description: csi_ker selected as peripheral clock
+    value: 3
+enum/I2CSEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: pclk1 selected as kernel clock (default after reset).
+    value: 0
+  - name: PLL3_R
+    description: pll3_r selected as peripheral clock
+    value: 1
+  - name: HSI
+    description: hsi_ker selected as peripheral clock
+    value: 2
+  - name: CSI
+    description: csi_ker selected as peripheral clock
+    value: 3
+enum/LPTIM1SEL:
+  bit_size: 3
+  variants:
+  - name: PCLK1
+    description: rcc_pclk1 selected as peripheral clock
+    value: 0
+  - name: PLL2_P
+    description: pll2_p selected as peripheral clock
+    value: 1
+  - name: PLL3_R
+    description: pll3_r selected as peripheral clock
+    value: 2
+  - name: LSE
+    description: LSE selected as peripheral clock
+    value: 3
+  - name: LSI
+    description: LSI selected as peripheral clock
+    value: 4
+  - name: PER
+    description: PER selected as peripheral clock
+    value: 5
+enum/LPTIMSEL:
+  bit_size: 3
+  variants:
+  - name: PCLK4
+    description: rcc_pclk4 selected as peripheral clock
+    value: 0
+  - name: PLL2_P
+    description: pll2_p selected as peripheral clock
+    value: 1
+  - name: PLL3_R
+    description: pll3_r selected as peripheral clock
+    value: 2
+  - name: LSE
+    description: LSE selected as peripheral clock
+    value: 3
+  - name: LSI
+    description: LSI selected as peripheral clock
+    value: 4
+  - name: PER
+    description: PER selected as peripheral clock
+    value: 5
+enum/LPUARTSEL:
+  bit_size: 3
+  variants:
+  - name: PCLK4
+    description: rcc_pclk_d4 selected as peripheral clock
+    value: 0
+  - name: PLL2_Q
+    description: pll2_q selected as peripheral clock
+    value: 1
+  - name: PLL3_Q
+    description: pll3_q selected as peripheral clock
+    value: 2
+  - name: HSI
+    description: hsi_ker selected as peripheral clock
+    value: 3
+  - name: CSI
+    description: csi_ker selected as peripheral clock
+    value: 4
+  - name: LSE
+    description: LSE selected as peripheral clock
+    value: 5
+enum/LSEDRV:
+  bit_size: 2
+  variants:
+  - name: Low
+    description: Low driving capability
+    value: 0
+  - name: MediumLow
+    description: Medium low driving capability
+    value: 1
+  - name: MediumHigh
+    description: Medium high driving capability
+    value: 2
+  - name: High
+    description: High driving capability
+    value: 3
+enum/MCO1SEL:
+  bit_size: 3
+  variants:
+  - name: HSI
+    description: HSI selected for micro-controller clock output
+    value: 0
+  - name: LSE
+    description: LSE selected for micro-controller clock output
+    value: 1
+  - name: HSE
+    description: HSE selected for micro-controller clock output
+    value: 2
+  - name: PLL1_Q
+    description: pll1_q selected for micro-controller clock output
+    value: 3
+  - name: HSI48
+    description: HSI48 selected for micro-controller clock output
+    value: 4
+enum/MCO2SEL:
+  bit_size: 3
+  variants:
+  - name: SYS
+    description: System clock selected for micro-controller clock output
+    value: 0
+  - name: PLL2_P
+    description: pll2_p selected for micro-controller clock output
+    value: 1
+  - name: HSE
+    description: HSE selected for micro-controller clock output
+    value: 2
+  - name: PLL1_P
+    description: pll1_p selected for micro-controller clock output
+    value: 3
+  - name: CSI
+    description: CSI selected for micro-controller clock output
+    value: 4
+  - name: LSI
+    description: LSI selected for micro-controller clock output
+    value: 5
+enum/MCOPRE:
+  bit_size: 4
+  variants:
+  - name: Div1
+    description: Divide by 1
+    value: 1
+  - name: Div2
+    description: Divide by 2
+    value: 2
+  - name: Div3
+    description: Divide by 3
+    value: 3
+  - name: Div4
+    description: Divide by 4
+    value: 4
+  - name: Div5
+    description: Divide by 5
+    value: 5
+  - name: Div6
+    description: Divide by 6
+    value: 6
+  - name: Div7
+    description: Divide by 7
+    value: 7
+  - name: Div8
+    description: Divide by 8
+    value: 8
+  - name: Div9
+    description: Divide by 9
+    value: 9
+  - name: Div10
+    description: Divide by 10
+    value: 10
+  - name: Div11
+    description: Divide by 11
+    value: 11
+  - name: Div12
+    description: Divide by 12
+    value: 12
+  - name: Div13
+    description: Divide by 13
+    value: 13
+  - name: Div14
+    description: Divide by 14
+    value: 14
+  - name: Div15
+    description: Divide by 15
+    value: 15
+enum/OCTOSPISEL:
+  bit_size: 2
+  variants:
+  - name: HCLK5
+    description: hclk5 selected as kernel peripheral clock (default after reset).
+    value: 0
+  - name: PLL2_S
+    description: pll2_s_ck selected as kernel peripheral clock.
+    value: 1
+enum/PERSEL:
+  bit_size: 2
+  variants:
+  - name: HSI
+    description: HSI selected as peripheral clock
+    value: 0
+  - name: CSI
+    description: CSI selected as peripheral clock
+    value: 1
+  - name: HSE
+    description: HSE selected as peripheral clock
+    value: 2
+enum/PLLDIV:
+  bit_size: 7
+  variants:
+  - name: Div1
+    value: 0
+  - name: Div2
+    value: 1
+  - name: Div3
+    value: 2
+  - name: Div4
+    value: 3
+  - name: Div5
+    value: 4
+  - name: Div6
+    value: 5
+  - name: Div7
+    value: 6
+  - name: Div8
+    value: 7
+  - name: Div9
+    value: 8
+  - name: Div10
+    value: 9
+  - name: Div11
+    value: 10
+  - name: Div12
+    value: 11
+  - name: Div13
+    value: 12
+  - name: Div14
+    value: 13
+  - name: Div15
+    value: 14
+  - name: Div16
+    value: 15
+  - name: Div17
+    value: 16
+  - name: Div18
+    value: 17
+  - name: Div19
+    value: 18
+  - name: Div20
+    value: 19
+  - name: Div21
+    value: 20
+  - name: Div22
+    value: 21
+  - name: Div23
+    value: 22
+  - name: Div24
+    value: 23
+  - name: Div25
+    value: 24
+  - name: Div26
+    value: 25
+  - name: Div27
+    value: 26
+  - name: Div28
+    value: 27
+  - name: Div29
+    value: 28
+  - name: Div30
+    value: 29
+  - name: Div31
+    value: 30
+  - name: Div32
+    value: 31
+  - name: Div33
+    value: 32
+  - name: Div34
+    value: 33
+  - name: Div35
+    value: 34
+  - name: Div36
+    value: 35
+  - name: Div37
+    value: 36
+  - name: Div38
+    value: 37
+  - name: Div39
+    value: 38
+  - name: Div40
+    value: 39
+  - name: Div41
+    value: 40
+  - name: Div42
+    value: 41
+  - name: Div43
+    value: 42
+  - name: Div44
+    value: 43
+  - name: Div45
+    value: 44
+  - name: Div46
+    value: 45
+  - name: Div47
+    value: 46
+  - name: Div48
+    value: 47
+  - name: Div49
+    value: 48
+  - name: Div50
+    value: 49
+  - name: Div51
+    value: 50
+  - name: Div52
+    value: 51
+  - name: Div53
+    value: 52
+  - name: Div54
+    value: 53
+  - name: Div55
+    value: 54
+  - name: Div56
+    value: 55
+  - name: Div57
+    value: 56
+  - name: Div58
+    value: 57
+  - name: Div59
+    value: 58
+  - name: Div60
+    value: 59
+  - name: Div61
+    value: 60
+  - name: Div62
+    value: 61
+  - name: Div63
+    value: 62
+  - name: Div64
+    value: 63
+  - name: Div65
+    value: 64
+  - name: Div66
+    value: 65
+  - name: Div67
+    value: 66
+  - name: Div68
+    value: 67
+  - name: Div69
+    value: 68
+  - name: Div70
+    value: 69
+  - name: Div71
+    value: 70
+  - name: Div72
+    value: 71
+  - name: Div73
+    value: 72
+  - name: Div74
+    value: 73
+  - name: Div75
+    value: 74
+  - name: Div76
+    value: 75
+  - name: Div77
+    value: 76
+  - name: Div78
+    value: 77
+  - name: Div79
+    value: 78
+  - name: Div80
+    value: 79
+  - name: Div81
+    value: 80
+  - name: Div82
+    value: 81
+  - name: Div83
+    value: 82
+  - name: Div84
+    value: 83
+  - name: Div85
+    value: 84
+  - name: Div86
+    value: 85
+  - name: Div87
+    value: 86
+  - name: Div88
+    value: 87
+  - name: Div89
+    value: 88
+  - name: Div90
+    value: 89
+  - name: Div91
+    value: 90
+  - name: Div92
+    value: 91
+  - name: Div93
+    value: 92
+  - name: Div94
+    value: 93
+  - name: Div95
+    value: 94
+  - name: Div96
+    value: 95
+  - name: Div97
+    value: 96
+  - name: Div98
+    value: 97
+  - name: Div99
+    value: 98
+  - name: Div100
+    value: 99
+  - name: Div101
+    value: 100
+  - name: Div102
+    value: 101
+  - name: Div103
+    value: 102
+  - name: Div104
+    value: 103
+  - name: Div105
+    value: 104
+  - name: Div106
+    value: 105
+  - name: Div107
+    value: 106
+  - name: Div108
+    value: 107
+  - name: Div109
+    value: 108
+  - name: Div110
+    value: 109
+  - name: Div111
+    value: 110
+  - name: Div112
+    value: 111
+  - name: Div113
+    value: 112
+  - name: Div114
+    value: 113
+  - name: Div115
+    value: 114
+  - name: Div116
+    value: 115
+  - name: Div117
+    value: 116
+  - name: Div118
+    value: 117
+  - name: Div119
+    value: 118
+  - name: Div120
+    value: 119
+  - name: Div121
+    value: 120
+  - name: Div122
+    value: 121
+  - name: Div123
+    value: 122
+  - name: Div124
+    value: 123
+  - name: Div125
+    value: 124
+  - name: Div126
+    value: 125
+  - name: Div127
+    value: 126
+  - name: Div128
+    value: 127
+enum/PLLDIVST:
+  bit_size: 3
+  variants:
+  - name: Div1
+    value: 0
+  - name: Div2
+    value: 1
+  - name: Div3
+    value: 2
+  - name: Div4
+    value: 3
+  - name: Div5
+    value: 4
+  - name: Div6
+    value: 5
+  - name: Div7
+    value: 6
+  - name: Div8
+    value: 7
+enum/PLLM:
+  bit_size: 6
+  variants:
+  - name: Div1
+    value: 1
+  - name: Div2
+    value: 2
+  - name: Div3
+    value: 3
+  - name: Div4
+    value: 4
+  - name: Div5
+    value: 5
+  - name: Div6
+    value: 6
+  - name: Div7
+    value: 7
+  - name: Div8
+    value: 8
+  - name: Div9
+    value: 9
+  - name: Div10
+    value: 10
+  - name: Div11
+    value: 11
+  - name: Div12
+    value: 12
+  - name: Div13
+    value: 13
+  - name: Div14
+    value: 14
+  - name: Div15
+    value: 15
+  - name: Div16
+    value: 16
+  - name: Div17
+    value: 17
+  - name: Div18
+    value: 18
+  - name: Div19
+    value: 19
+  - name: Div20
+    value: 20
+  - name: Div21
+    value: 21
+  - name: Div22
+    value: 22
+  - name: Div23
+    value: 23
+  - name: Div24
+    value: 24
+  - name: Div25
+    value: 25
+  - name: Div26
+    value: 26
+  - name: Div27
+    value: 27
+  - name: Div28
+    value: 28
+  - name: Div29
+    value: 29
+  - name: Div30
+    value: 30
+  - name: Div31
+    value: 31
+  - name: Div32
+    value: 32
+  - name: Div33
+    value: 33
+  - name: Div34
+    value: 34
+  - name: Div35
+    value: 35
+  - name: Div36
+    value: 36
+  - name: Div37
+    value: 37
+  - name: Div38
+    value: 38
+  - name: Div39
+    value: 39
+  - name: Div40
+    value: 40
+  - name: Div41
+    value: 41
+  - name: Div42
+    value: 42
+  - name: Div43
+    value: 43
+  - name: Div44
+    value: 44
+  - name: Div45
+    value: 45
+  - name: Div46
+    value: 46
+  - name: Div47
+    value: 47
+  - name: Div48
+    value: 48
+  - name: Div49
+    value: 49
+  - name: Div50
+    value: 50
+  - name: Div51
+    value: 51
+  - name: Div52
+    value: 52
+  - name: Div53
+    value: 53
+  - name: Div54
+    value: 54
+  - name: Div55
+    value: 55
+  - name: Div56
+    value: 56
+  - name: Div57
+    value: 57
+  - name: Div58
+    value: 58
+  - name: Div59
+    value: 59
+  - name: Div60
+    value: 60
+  - name: Div61
+    value: 61
+  - name: Div62
+    value: 62
+  - name: Div63
+    value: 63
+enum/PLLN:
+  bit_size: 9
+  variants:
+  - name: Mul8
+    value: 7
+  - name: Mul9
+    value: 8
+  - name: Mul10
+    value: 9
+  - name: Mul11
+    value: 10
+  - name: Mul12
+    value: 11
+  - name: Mul13
+    value: 12
+  - name: Mul14
+    value: 13
+  - name: Mul15
+    value: 14
+  - name: Mul16
+    value: 15
+  - name: Mul17
+    value: 16
+  - name: Mul18
+    value: 17
+  - name: Mul19
+    value: 18
+  - name: Mul20
+    value: 19
+  - name: Mul21
+    value: 20
+  - name: Mul22
+    value: 21
+  - name: Mul23
+    value: 22
+  - name: Mul24
+    value: 23
+  - name: Mul25
+    value: 24
+  - name: Mul26
+    value: 25
+  - name: Mul27
+    value: 26
+  - name: Mul28
+    value: 27
+  - name: Mul29
+    value: 28
+  - name: Mul30
+    value: 29
+  - name: Mul31
+    value: 30
+  - name: Mul32
+    value: 31
+  - name: Mul33
+    value: 32
+  - name: Mul34
+    value: 33
+  - name: Mul35
+    value: 34
+  - name: Mul36
+    value: 35
+  - name: Mul37
+    value: 36
+  - name: Mul38
+    value: 37
+  - name: Mul39
+    value: 38
+  - name: Mul40
+    value: 39
+  - name: Mul41
+    value: 40
+  - name: Mul42
+    value: 41
+  - name: Mul43
+    value: 42
+  - name: Mul44
+    value: 43
+  - name: Mul45
+    value: 44
+  - name: Mul46
+    value: 45
+  - name: Mul47
+    value: 46
+  - name: Mul48
+    value: 47
+  - name: Mul49
+    value: 48
+  - name: Mul50
+    value: 49
+  - name: Mul51
+    value: 50
+  - name: Mul52
+    value: 51
+  - name: Mul53
+    value: 52
+  - name: Mul54
+    value: 53
+  - name: Mul55
+    value: 54
+  - name: Mul56
+    value: 55
+  - name: Mul57
+    value: 56
+  - name: Mul58
+    value: 57
+  - name: Mul59
+    value: 58
+  - name: Mul60
+    value: 59
+  - name: Mul61
+    value: 60
+  - name: Mul62
+    value: 61
+  - name: Mul63
+    value: 62
+  - name: Mul64
+    value: 63
+  - name: Mul65
+    value: 64
+  - name: Mul66
+    value: 65
+  - name: Mul67
+    value: 66
+  - name: Mul68
+    value: 67
+  - name: Mul69
+    value: 68
+  - name: Mul70
+    value: 69
+  - name: Mul71
+    value: 70
+  - name: Mul72
+    value: 71
+  - name: Mul73
+    value: 72
+  - name: Mul74
+    value: 73
+  - name: Mul75
+    value: 74
+  - name: Mul76
+    value: 75
+  - name: Mul77
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+    value: 391
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+  - name: Mul396
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+  - name: Mul402
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+  - name: Mul417
+    value: 416
+  - name: Mul418
+    value: 417
+  - name: Mul419
+    value: 418
+  - name: Mul420
+    value: 419
+enum/PLLRGE:
+  bit_size: 2
+  variants:
+  - name: Range1
+    description: Frequency is between 1 and 2 MHz
+    value: 0
+  - name: Range2
+    description: Frequency is between 2 and 4 MHz
+    value: 1
+  - name: Range4
+    description: Frequency is between 4 and 8 MHz
+    value: 2
+  - name: Range8
+    description: Frequency is between 8 and 16 MHz
+    value: 3
+enum/PLLSRC:
+  bit_size: 2
+  variants:
+  - name: HSI
+    description: HSI selected as PLL clock
+    value: 0
+  - name: CSI
+    description: CSI selected as PLL clock
+    value: 1
+  - name: HSE
+    description: HSE selected as PLL clock
+    value: 2
+  - name: DISABLE
+    description: No clock sent to DIVMx dividers and PLLs
+    value: 3
+enum/PLLVCOSEL:
+  bit_size: 1
+  variants:
+  - name: WideVCO
+    description: VCOH selected (default after reset).
+    value: 0
+  - name: MediumVCO
+    description: VCOL selected.
+    value: 1
+enum/PPRE:
+  bit_size: 3
+  variants:
+  - name: Div1
+    description: rcc_hclk not divided
+    value: 0
+  - name: Div2
+    description: rcc_hclk divided by 2
+    value: 4
+  - name: Div4
+    description: rcc_hclk divided by 4
+    value: 5
+  - name: Div8
+    description: rcc_hclk divided by 8
+    value: 6
+  - name: Div16
+    description: rcc_hclk divided by 16
+    value: 7
+enum/PSSISEL:
+  bit_size: 1
+  variants:
+  - name: PLL3_R
+    description: pll3_r_ck selected as kernel peripheral clock (default after reset).
+    value: 0
+  - name: PER
+    description: per_ck selected as kernel peripheral clock.
+    value: 1
+enum/RTCSEL:
+  bit_size: 2
+  variants:
+  - name: DISABLE
+    description: No clock
+    value: 0
+  - name: LSE
+    description: LSE oscillator clock used as RTC clock
+    value: 1
+  - name: LSI
+    description: LSI oscillator clock used as RTC clock
+    value: 2
+  - name: HSE
+    description: HSE oscillator clock divided by a prescaler used as RTC clock
+    value: 3
+enum/SAI1SEL:
+  bit_size: 3
+  variants:
+  - name: PLL1_Q
+    description: pll1_q selected as peripheral clock
+    value: 0
+  - name: PLL2_P
+    description: pll2_p selected as peripheral clock
+    value: 1
+  - name: PLL3_P
+    description: pll3_p selected as peripheral clock
+    value: 2
+  - name: I2S_CKIN
+    description: I2S_CKIN selected as peripheral clock
+    value: 3
+  - name: PER
+    description: PER selected as peripheral clock
+    value: 4
+enum/SAI2SEL:
+  bit_size: 3
+  variants:
+  - name: PLL1_Q
+    description: pll1_q selected as peripheral clock
+    value: 0
+  - name: PLL2_P
+    description: pll2_p selected as peripheral clock
+    value: 1
+  - name: PLL3_P
+    description: pll3_p selected as peripheral clock
+    value: 2
+  - name: I2S_CKIN
+    description: I2S_CKIN selected as peripheral clock
+    value: 3
+  - name: PER
+    description: PER selected as peripheral clock
+    value: 4
+  - name: SPDIFRX_SYMB
+    description: spdifrx_symb_ck selected as SAI2 kernel clock.
+    value: 5
+enum/SDMMCSEL:
+  bit_size: 1
+  variants:
+  - name: PLL2_S
+    description: pll2_s_ck selected as kernel peripheral clock (default after reset).
+    value: 0
+  - name: PLL2_T
+    description: pll2_t_ck selected as kernel peripheral clock.
+    value: 1
+enum/SPDIFRXSEL:
+  bit_size: 2
+  variants:
+  - name: PLL1_Q
+    description: pll1_q selected as peripheral clock
+    value: 0
+  - name: PLL2_R
+    description: pll2_r selected as peripheral clock
+    value: 1
+  - name: PLL3_R
+    description: pll3_r selected as peripheral clock
+    value: 2
+  - name: HSI
+    description: hsi_ker selected as peripheral clock
+    value: 3
+enum/SPI123SEL:
+  bit_size: 3
+  variants:
+  - name: PLL1_Q
+    description: pll1_q_ck selected as SPI/I2S1 and 7 kernel clock (default after reset).
+    value: 0
+  - name: PLL2_P
+    description: pll2_p_ck selected as SPI/I2S1 and 7 kernel clock.
+    value: 1
+  - name: PLL3_P
+    description: pll3_p_ck selected as SPI/I2S1 and 7 kernel clock.
+    value: 2
+  - name: I2S_CKIN
+    description: I2S_CKIN selected as SPI/I2S1 and 7 kernel clock.
+    value: 3
+  - name: PER
+    description: per_ck selected as SPI/I2S1,and 7 kernel clock.
+    value: 4
+enum/SPI45SEL:
+  bit_size: 3
+  variants:
+  - name: HCLK2
+    description: APB2 clock selected as peripheral clock
+    value: 0
+  - name: PLL2_Q
+    description: pll2_q selected as peripheral clock
+    value: 1
+  - name: PLL3_Q
+    description: pll3_q selected as peripheral clock
+    value: 2
+  - name: HSI
+    description: hsi_ker selected as peripheral clock
+    value: 3
+  - name: CSI
+    description: csi_ker selected as peripheral clock
+    value: 4
+  - name: HSE
+    description: HSE selected as peripheral clock
+    value: 5
+enum/SPI6SEL:
+  bit_size: 3
+  variants:
+  - name: PCLK4
+    description: rcc_pclk4 selected as peripheral clock
+    value: 0
+  - name: PLL2_Q
+    description: pll2_q selected as peripheral clock
+    value: 1
+  - name: PLL3_Q
+    description: pll3_q selected as peripheral clock
+    value: 2
+  - name: HSI
+    description: hsi_ker selected as peripheral clock
+    value: 3
+  - name: CSI
+    description: csi_ker selected as peripheral clock
+    value: 4
+  - name: HSE
+    description: HSE selected as peripheral clock
+    value: 5
+enum/STOPKERWUCK:
+  bit_size: 1
+  variants:
+  - name: HSI
+    description: HSI selected as wake up clock from system Stop (default after reset).
+    value: 0
+  - name: CSI
+    description: CSI selected as wake up clock from system Stop.
+    value: 1
+enum/STOPWUCK:
+  bit_size: 1
+  variants:
+  - name: HSI
+    description: HSI selected as wake up clock from system Stop
+    value: 0
+  - name: CSI
+    description: CSI selected as wake up clock from system Stop
+    value: 1
+enum/SW:
+  bit_size: 3
+  variants:
+  - name: HSI
+    description: HSI selected as system clock
+    value: 0
+  - name: CSI
+    description: CSI selected as system clock
+    value: 1
+  - name: HSE
+    description: HSE selected as system clock
+    value: 2
+  - name: PLL1_P
+    description: PLL1 selected as system clock
+    value: 3
+enum/TIMPRE:
+  bit_size: 1
+  variants:
+  - name: DefaultX2
+    description: Timer kernel clock equal to 2x pclk by default
+    value: 0
+  - name: DefaultX4
+    description: Timer kernel clock equal to 4x pclk by default
+    value: 1
+enum/USART1SEL:
+  bit_size: 3
+  variants:
+  - name: PCLK2
+    description: rcc_pclk2 selected as peripheral clock
+    value: 0
+  - name: PLL2_Q
+    description: pll2_q selected as peripheral clock
+    value: 1
+  - name: PLL3_Q
+    description: pll3_q selected as peripheral clock
+    value: 2
+  - name: HSI
+    description: hsi_ker selected as peripheral clock
+    value: 3
+  - name: CSI
+    description: csi_ker selected as peripheral clock
+    value: 4
+  - name: LSE
+    description: LSE selected as peripheral clock
+    value: 5
+enum/USART234578SEL:
+  bit_size: 3
+  variants:
+  - name: PCLK1
+    description: rcc_pclk1 selected as peripheral clock
+    value: 0
+  - name: PLL2_Q
+    description: pll2_q selected as peripheral clock
+    value: 1
+  - name: PLL3_Q
+    description: pll3_q selected as peripheral clock
+    value: 2
+  - name: HSI
+    description: hsi_ker selected as peripheral clock
+    value: 3
+  - name: CSI
+    description: csi_ker selected as peripheral clock
+    value: 4
+  - name: LSE
+    description: LSE selected as peripheral clock
+    value: 5
+enum/USBPDCTRL:
+  bit_size: 1
+  variants:
+  - name: RemainPowered
+    description: In SUSPEND, PHY state machine, bias and USBPHYC PLL remain powered (default after reset).
+    value: 0
+  - name: PowerDown
+    description: In SUSPEND, PHY state machine, bias and USBPHYC PLL are powered down.
+    value: 1
+enum/USBPHYCSEL:
+  bit_size: 2
+  variants:
+  - name: HSE
+    description: hse_ker_ck (default after reset).
+    value: 0
+  - name: HSE_DIV_2
+    description: hse_ker_ck / 2.
+    value: 1
+  - name: PLL3_Q
+    description: pll3_q_ck.
+    value: 2
+enum/USBREFCKSEL:
+  bit_size: 4
+  variants:
+  - name: Mhz16
+    description: The kernel clock frequency provided to the USBPHYC is 16 MHz.
+    value: 3
+  - name: Mhz19_2
+    description: The kernel clock frequency provided to the USBPHYC is 19.2 MHz.
+    value: 8
+  - name: Mhz20
+    description: The kernel clock frequency provided to the USBPHYC is 20MHz.
+    value: 9
+  - name: Mhz24
+    description: The kernel clock frequency provided to the USBPHYC is 24 MHz (default after reset).
+    value: 10
+  - name: Mhz32
+    description: The kernel clock frequency provided to the USBPHYC is 32 MHz.
+    value: 11
+  - name: Mhz26
+    description: The kernel clock frequency provided to the USBPHYC is 26 MHz.
+    value: 14
+enum/USB_OTG_FSSEL:
+  bit_size: 2
+  variants:
+  - name: HSI48
+    description: hsi48_ker_ck (default after reset).
+    value: 0
+  - name: PLL3_Q
+    description: pll3_q_ck.
+    value: 1
+  - name: HSE
+    description: hse_ker_ck.
+    value: 2
+  - name: CLK48MOHCI
+    description: clk48mohci.
+    value: 3
+enum/XSPISWP:
+  bit_size: 3
+  variants:
+  - name: B_0x0
+    description: The switch is in neutral mode and output clock is gated (default after reset).
+    value: 0
+  - name: B_0x1
+    description: The switch is selecting hclk5.
+    value: 1
+  - name: B_0x2
+    description: The switch is selecting pll2_s_ck.
+    value: 2
+  - name: B_0x3
+    description: The switch is selecting pll2_t_ck.
+    value: 3
+  - name: B_0x4
+    description: The switch is in recovery position (hclk5/4).
+    value: 4
diff --git a/data/registers/syscfg_h5.yaml b/data/registers/syscfg_h5.yaml
index 3094aeb..6e354dc 100644
--- a/data/registers/syscfg_h5.yaml
+++ b/data/registers/syscfg_h5.yaml
@@ -365,13 +365,13 @@ enum/EPOCH_SEL:
 enum/ETH_SEL_PHY:
   bit_size: 3
   variants:
-  - name: B_0x0
+  - name: MII_GMII
     description: GMII or MII
     value: 0
-  - name: B_0x1
+  - name: ReservedRGMII
     description: reserved (RGMII)
     value: 1
-  - name: B_0x4
+  - name: RMII
     description: RMII
     value: 4
 enum/HDPL:
diff --git a/data/registers/syscfg_h7.yaml b/data/registers/syscfg_h7.yaml
index b1d79f6..721d2bc 100644
--- a/data/registers/syscfg_h7.yaml
+++ b/data/registers/syscfg_h7.yaml
@@ -139,7 +139,7 @@ fieldset/CCCSR:
     description: Code selection
     bit_offset: 1
     bit_size: 1
-  - name: READY
+  - name: RDY
     description: Compensation cell ready flag
     bit_offset: 8
     bit_size: 1
@@ -218,10 +218,11 @@ fieldset/PMCR:
     description: Analog switch supply voltage selection
     bit_offset: 9
     bit_size: 1
-  - name: EPIS
-    description: Ethernet PHY Interface Selection
+  - name: ETH_SEL_PHY
+    description: Ethernet PHY interface selection.
     bit_offset: 21
     bit_size: 3
+    enum: ETH_SEL_PHY
   - name: PA0SO
     description: PA0 Switch Open
     bit_offset: 24
@@ -413,6 +414,15 @@ fieldset/UR9:
     description: Protected area start address for bank 2
     bit_offset: 16
     bit_size: 12
+enum/ETH_SEL_PHY:
+  bit_size: 3
+  variants:
+  - name: MII_GMII
+    description: GMII or MII
+    value: 0
+  - name: RMII
+    description: RMII
+    value: 4
 enum/ITCM_AXI_RAM_SIZE:
   bit_size: 2
   variants:
diff --git a/data/registers/syscfg_h7od.yaml b/data/registers/syscfg_h7od.yaml
index 24f8b08..b90e2e1 100644
--- a/data/registers/syscfg_h7od.yaml
+++ b/data/registers/syscfg_h7od.yaml
@@ -138,7 +138,7 @@ fieldset/CCCSR:
     description: Code selection
     bit_offset: 1
     bit_size: 1
-  - name: READY
+  - name: RDY
     description: Compensation cell ready flag
     bit_offset: 8
     bit_size: 1
@@ -217,10 +217,11 @@ fieldset/PMCR:
     description: Analog switch supply voltage selection
     bit_offset: 9
     bit_size: 1
-  - name: EPIS
-    description: Ethernet PHY Interface Selection
+  - name: ETH_SEL_PHY
+    description: Ethernet PHY interface selection.
     bit_offset: 21
     bit_size: 3
+    enum: ETH_SEL_PHY
   - name: PA0SO
     description: PA0 Switch Open
     bit_offset: 24
@@ -407,3 +408,12 @@ fieldset/UR9:
     description: Protected area start address for bank 2
     bit_offset: 16
     bit_size: 12
+enum/ETH_SEL_PHY:
+  bit_size: 3
+  variants:
+  - name: MII_GMII
+    description: GMII or MII
+    value: 0
+  - name: RMII
+    description: RMII
+    value: 4
diff --git a/data/registers/syscfg_h7rs.yaml b/data/registers/syscfg_h7rs.yaml
new file mode 100644
index 0000000..6642ab2
--- /dev/null
+++ b/data/registers/syscfg_h7rs.yaml
@@ -0,0 +1,364 @@
+block/SYSCFG:
+  description: System configuration, boot and security.
+  items:
+  - name: BOOTSR
+    description: SBS boot status register.
+    byte_offset: 0
+    fieldset: BOOTSR
+  - name: HDPLCR
+    description: SBS hide protection control register.
+    byte_offset: 16
+    fieldset: HDPLCR
+  - name: HDPLSR
+    description: SBS hide protection status register.
+    byte_offset: 20
+    fieldset: HDPLSR
+  - name: DBGCR
+    description: SBS debug control register.
+    byte_offset: 32
+    fieldset: DBGCR
+  - name: DBGLOCKR
+    description: SBS debug lock register.
+    byte_offset: 36
+    fieldset: DBGLOCKR
+  - name: RSSCMDR
+    description: SBS RSS command register.
+    byte_offset: 52
+    fieldset: RSSCMDR
+  - name: PMCR
+    description: SBS product mode and configuration register.
+    byte_offset: 256
+    fieldset: PMCR
+  - name: FPUIMR
+    description: SBS FPU interrupt mask register.
+    byte_offset: 260
+    fieldset: FPUIMR
+  - name: MESR
+    description: SBS memory erase status register.
+    byte_offset: 264
+    fieldset: MESR
+  - name: CCCSR
+    description: SBS I/O compensation cell control and status register.
+    byte_offset: 272
+    fieldset: CCCSR
+  - name: CCVALR
+    description: SBS compensation cell for I/Os value register.
+    byte_offset: 276
+    fieldset: CCVALR
+  - name: CCSWVALR
+    description: SBS compensation cell for I/Os software value register.
+    byte_offset: 280
+    fieldset: CCSWVALR
+  - name: BKLOCKR
+    description: SBS break lockup register.
+    byte_offset: 288
+    fieldset: BKLOCKR
+  - name: EXTICR
+    description: external interrupt configuration register
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 304
+    fieldset: EXTICR
+fieldset/BKLOCKR:
+  description: SBS break lockup register.
+  fields:
+  - name: PVD_BL
+    description: PVD break lock This bit is set by SW and cleared only by a system reset. it can be used to enable and lock the connection to TIM1/8/15/16/17Break input as well as the PVDE and PLS[2:0] bitfields in the PWR_CR1 register. Once set, this bit is cleared only by a system reset.
+    bit_offset: 2
+    bit_size: 1
+  - name: FLASHECC_BL
+    description: Flash ECC error break lock Set this bit to enable and lock the connection between embedded flash memory ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
+    bit_offset: 3
+    bit_size: 1
+  - name: CM7LCKUP_BL
+    description: Cortex-M7 lockup break lock Set this bit to enable and lock the connection between the Cortex-M7 lockup (HardFault) output and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
+    bit_offset: 6
+    bit_size: 1
+  - name: BKRAMECC_BL
+    description: Backup RAM ECC error break lock Set this bit to enable and lock the connection between backup RAM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
+    bit_offset: 7
+    bit_size: 1
+  - name: DTCMECC_BL
+    description: 'DTCM ECC error break lock Set this bit to enable and lock the connection between DTCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. Note: The DTCM0 and DTCM1 are Ored to give DTCMECC.'
+    bit_offset: 13
+    bit_size: 1
+  - name: ITCMECC_BL
+    description: ITCM ECC error break lock Set this bit to enable and lock the connection between ITCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
+    bit_offset: 14
+    bit_size: 1
+  - name: ARAM3ECC_BL
+    description: AXIRAM3 ECC error break lock Set this bit to enable and lock the connection between AXIRAM3 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set this bit is cleared only by a system reset.
+    bit_offset: 21
+    bit_size: 1
+  - name: ARAM1ECC_BL
+    description: AXIRAM1 ECC error break lock Set this bit to enable and lock the connection between AXIRAM1 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
+    bit_offset: 23
+    bit_size: 1
+fieldset/BOOTSR:
+  description: SBS boot status register.
+  fields:
+  - name: INITVTOR
+    description: initial vector for Cortex-M7 This register includes the physical boot address used by the Cortex-M7 after reset.
+    bit_offset: 0
+    bit_size: 32
+fieldset/CCCSR:
+  description: SBS I/O compensation cell control and status register.
+  fields:
+  - name: COMP_EN
+    description: Compensation cell enable Set this bit to enable the compensation cell.
+    bit_offset: 0
+    bit_size: 1
+  - name: COMP_CODESEL
+    description: Compensation cell code selection This bit selects the code to be applied for the I/O compensation cell.
+    bit_offset: 1
+    bit_size: 1
+  - name: OCTO1_COMP_EN
+    description: XSPIM_P1 compensation cell enable Set this bit to enable the XSPIM_P1 compensation cell.
+    bit_offset: 2
+    bit_size: 1
+  - name: OCTO1_COMP_CODESEL
+    description: XSPIM_P1 compensation cell code selection This bit selects the code to be applied for the XSPIM_P1 I/O compensation cell.
+    bit_offset: 3
+    bit_size: 1
+  - name: OCTO2_COMP_EN
+    description: XSPIM_P2 compensation cell enable Set this bit to enable the XSPIM_P2 compensation cell.
+    bit_offset: 4
+    bit_size: 1
+  - name: OCTO2_COMP_CODESEL
+    description: XSPIM_P2 compensation cell code selection This bit selects the code to be applied for the XSPIM_P2 I/O compensation cell.
+    bit_offset: 5
+    bit_size: 1
+  - name: COMP_RDY
+    description: Compensation cell ready This bit provides the status of the compensation cell.
+    bit_offset: 8
+    bit_size: 1
+  - name: OCTO1_COMP_RDY
+    description: XSPIM_P1 compensation cell ready This bit provides the status of the XSPIM_P1 compensation cell.
+    bit_offset: 9
+    bit_size: 1
+  - name: OCTO2_COMP_RDY
+    description: XSPIM_P2 compensation cell ready This bit provides the status of the XSPIM_P2 compensation cell.
+    bit_offset: 10
+    bit_size: 1
+  - name: IOHSLV
+    description: I/O high speed at low voltage When this bit is set, the speed of the I/Os is optimized when the device voltage is low. This bit is active only if VDDIO_HSLV user option bit is set in FLASH. It must be used only if the device supply voltage is below 2.7 V. Setting this bit when V<sub>DD</sub> is higher than 2.7 V may be destructive.
+    bit_offset: 16
+    bit_size: 1
+  - name: OCTO1_IOHSLV
+    description: XSPIM_P1 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P1 I/Os is optimized when the device voltage is low. This bit is active only if OCTO1_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when V<sub>DD</sub> is higher than 2.7 V may be destructive.
+    bit_offset: 17
+    bit_size: 1
+  - name: OCTO2_IOHSLV
+    description: XSPIM_P2 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P2 I/Os is optimized when the device voltage is low. This bit is active only if OCTO2_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when V<sub>DD</sub> is higher than 2.7 V may be destructive.
+    bit_offset: 18
+    bit_size: 1
+fieldset/CCSWVALR:
+  description: SBS compensation cell for I/Os software value register.
+  fields:
+  - name: SW_NSRC
+    description: Software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register.
+    bit_offset: 0
+    bit_size: 4
+  - name: SW_PSRC
+    description: Software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register.
+    bit_offset: 4
+    bit_size: 4
+  - name: OCTO1_SW_NSRC
+    description: XSPIM_P1 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew -ate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register.
+    bit_offset: 8
+    bit_size: 4
+  - name: OCTO1_SW_PSRC
+    description: XSPIM_P1 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register.
+    bit_offset: 12
+    bit_size: 4
+  - name: OCTO2_SW_NSRC
+    description: XSPIM_P2 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register.
+    bit_offset: 16
+    bit_size: 4
+  - name: OCTO2_SW_PSRC
+    description: XSPIM_P2 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register.
+    bit_offset: 20
+    bit_size: 4
+fieldset/CCVALR:
+  description: SBS compensation cell for I/Os value register.
+  fields:
+  - name: NSRC
+    description: NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register.
+    bit_offset: 0
+    bit_size: 4
+  - name: PSRC
+    description: PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register.
+    bit_offset: 4
+    bit_size: 4
+  - name: OCTO1_NSRC
+    description: XSPIM_P1 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register.
+    bit_offset: 8
+    bit_size: 4
+  - name: OCTO1_PSRC
+    description: XSPIM_P1 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register.
+    bit_offset: 12
+    bit_size: 4
+  - name: OCTO2_NSRC
+    description: XSPIM_P2 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register.
+    bit_offset: 16
+    bit_size: 4
+  - name: OCTO2_PSRC
+    description: XSPIM_P2 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register.
+    bit_offset: 20
+    bit_size: 4
+fieldset/DBGCR:
+  description: SBS debug control register.
+  fields:
+  - name: AP_UNLOCK
+    description: access port unlock Write 0xB4 to this bitfield to open the device access port.
+    bit_offset: 0
+    bit_size: 8
+  - name: DBG_UNLOCK
+    description: debug unlock Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register.
+    bit_offset: 8
+    bit_size: 8
+  - name: DBG_AUTH_HDPL
+    description: 'authenticated debug hide protection level Writing to this bitfield defines at which HDPL the authenticated debug opens. Note: Writing any other values is ignored. Reading any other value means the authenticated debug always fails.'
+    bit_offset: 16
+    bit_size: 8
+    enum: DBG_AUTH_HDPL
+fieldset/DBGLOCKR:
+  description: SBS debug lock register.
+  fields:
+  - name: DBGCFG_LOCK
+    description: 'debug configuration lock Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4. Other: Writes to SBS_DBGCR ignored Note: 0xC3 is the recommended value to lock the debug configuration using this bitfield.'
+    bit_offset: 0
+    bit_size: 8
+    enum: DBGCFG_LOCK
+fieldset/EXTICR:
+  description: external interrupt configuration register 2
+  fields:
+  - name: EXTI
+    description: EXTI x configuration (x = 4 to 7)
+    bit_offset: 0
+    bit_size: 4
+    array:
+      len: 4
+      stride: 4
+fieldset/FPUIMR:
+  description: SBS FPU interrupt mask register.
+  fields:
+  - name: FPU_IE
+    description: 'FPU interrupt enable Set and cleared by software to enable the Cortex-M7 FPU interrupts xxxxx1: Invalid operation interrupt enabled (xxxxx0 to disable) xxxx1x: Divide-by-zero interrupt enabled (xxxx0x to disable) xxx1xx: Underflow interrupt enabled (xxx0xx to disable) xx1xxx: Overflow interrupt enabled (xx0xxx to disable) x1xxxx: Input denormal interrupt enabled (x0xxxx to disable) 1xxxxx: Inexact interrupt enabled (0xxxxx to disable), disabled by default.'
+    bit_offset: 0
+    bit_size: 6
+fieldset/HDPLCR:
+  description: SBS hide protection control register.
+  fields:
+  - name: INCR_HDPL
+    description: increment HDPL Write 0x6A to increment device HDPL by one. After a write, the register value reverts to its default value (0xB4).
+    bit_offset: 0
+    bit_size: 8
+fieldset/HDPLSR:
+  description: SBS hide protection status register.
+  fields:
+  - name: HDPL
+    description: 'hide protection level This bitfield returns the current HDPL of the device. 0x6F and other codes: HDPL3, corresponding to non-boot application. Note: The device state (open/close) is defined in FLASH_NVSTATER register of the embedded Flash memory.'
+    bit_offset: 0
+    bit_size: 8
+    enum: HDPL
+fieldset/MESR:
+  description: SBS memory erase status register.
+  fields:
+  - name: MEF
+    description: 'memory erase flag This bit is set by hardware when BKPRAM and PKA SRAM erase is ongoing after a POWER ON reset or one tamper event (see Section 50: Tamper and backup registers (TAMP) for details). This bit is cleared when the erase is done.'
+    bit_offset: 0
+    bit_size: 1
+fieldset/PMCR:
+  description: SBS product mode and configuration register.
+  fields:
+  - name: FMPLUS_PB6
+    description: Fast-mode Plus on PB(6).
+    bit_offset: 4
+    bit_size: 1
+  - name: FMPLUS_PB7
+    description: Fast-mode Plus on PB(7).
+    bit_offset: 5
+    bit_size: 1
+  - name: FMPLUS_PB8
+    description: Fast-mode Plus on PB(8).
+    bit_offset: 6
+    bit_size: 1
+  - name: FMPLUS_PB9
+    description: Fast-mode Plus on PB(9).
+    bit_offset: 7
+    bit_size: 1
+  - name: BOOSTEN
+    description: booster enable Set this bit to reduce the THD of the analog switches when the supply voltage is below 2.7 V. guaranteeing the same performance as with the full voltage range. To avoid current consumption due to booster activation when V<sub>DDA</sub> < 2.7 V and V<sub>DD</sub> > 2.7 V, V<sub>DD</sub> can be selected as supply voltage for analog switches by setting BOOSTVDDSEL bit in SBS_PMCR. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption.
+    bit_offset: 8
+    bit_size: 1
+  - name: BOOSTVDDSEL
+    description: booster V<sub>DD</sub> selection This bit selects the analog switch supply voltage, between V<sub>DD</sub>, V<sub>DDA</sub> and booster. To avoid current consumption due to booster activation when V<sub>DDA</sub> < 2.7 V and V<sub>DD</sub> > 2.7 V, V<sub>DD</sub> can be selected as supply voltage for analog switches. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption. When both V<sub>DD and </sub>V<sub>DDA</sub> are below 2.7 V, the booster is still needed to obtain full AC performances from the I/O analog switches.
+    bit_offset: 9
+    bit_size: 1
+  - name: ETH_SEL_PHY
+    description: Ethernet PHY interface selection.
+    bit_offset: 21
+    bit_size: 3
+    enum: ETH_SEL_PHY
+  - name: AXIRAM_WS
+    description: AXIRAM wait state Set this bit to add one wait state to all AXIRAMs when ECC = 0. When ECC = 1 there is one wait state by default.
+    bit_offset: 28
+    bit_size: 1
+    enum: AXIRAM_WS
+fieldset/RSSCMDR:
+  description: SBS RSS command register.
+  fields:
+  - name: RSSCMD
+    description: RSS command The application can use this bitfield to pass on a command to the RSS, executed at the next reset.
+    bit_offset: 0
+    bit_size: 16
+enum/AXIRAM_WS:
+  bit_size: 1
+  variants:
+  - name: Ws0
+    description: No wait state added when accessing any AXIRAM with ECC = 0.
+    value: 0
+  - name: Ws1
+    description: One wait state added when accessing any AXIRAM with ECC = 0. In this case, Fmax = 500 MHz is not guaranteed. (TBC).
+    value: 1
+enum/DBGCFG_LOCK:
+  bit_size: 8
+  variants:
+  - name: Unlock
+    description: Writes to SBS_DBGCR allowed (default).
+    value: 180
+enum/DBG_AUTH_HDPL:
+  bit_size: 8
+  variants:
+  - name: HDPL1
+    description: HDPL1.
+    value: 81
+  - name: HDPL3
+    description: HDPL3.
+    value: 111
+  - name: HDPL2
+    description: HDPL2.
+    value: 138
+enum/ETH_SEL_PHY:
+  bit_size: 3
+  variants:
+  - name: MII_GMII
+    description: GMII or MII
+    value: 0
+  - name: RMII
+    description: RMII
+    value: 4
+enum/HDPL:
+  bit_size: 8
+  variants:
+  - name: HDPL1
+    description: HDPL1.
+    value: 81
+  - name: HDPL2
+    description: HDPL2.
+    value: 138
+  - name: HDPL0
+    description: HDPL0, corresponding to ST-RSS (default when device is close).
+    value: 180
diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs
index 2f5729c..42ea0ea 100644
--- a/stm32-data-gen/src/chips.rs
+++ b/stm32-data-gen/src/chips.rs
@@ -88,7 +88,7 @@ fn chip_name_from_package_name(x: &str) -> String {
         (regex!("^(STM32G0....).xN$"), "$1"),
         (regex!("^(STM32L5....).x[PQ]$"), "$1"),
         (regex!("^(STM32L0....).xS$"), "$1"),
-        (regex!("^(STM32H7....).xQ$"), "$1"),
+        (regex!("^(STM32H7....).x[QH]$"), "$1"),
         (regex!("^(STM32U5....).xQ$"), "$1"),
         (regex!("^(STM32H5....).xQ$"), "$1"),
         (regex!("^(STM32WBA....).x$"), "$1"),
@@ -247,6 +247,7 @@ impl PeriMatcher {
             ("STM32L5.*:SYSCFG:.*", ("syscfg", "l5", "SYSCFG")),
             ("STM32G0.*:SYSCFG:.*", ("syscfg", "g0", "SYSCFG")),
             ("STM32G4.*:SYSCFG:.*", ("syscfg", "g4", "SYSCFG")),
+            ("STM32H7[RS].*:SYSCFG:.*", ("syscfg", "h7rs", "SYSCFG")),
             (
                 "STM32H7(45|47|55|57|42|43|53|50).*:SYSCFG:.*",
                 ("syscfg", "h7od", "SYSCFG"),
@@ -345,6 +346,7 @@ impl PeriMatcher {
             ("STM32F7.*:RCC:.*", ("rcc", "f7", "RCC")),
             ("STM32G0.*:RCC:.*", ("rcc", "g0", "RCC")),
             ("STM32G4.*:RCC:.*", ("rcc", "g4", "RCC")),
+            ("STM32H7[RS].*:RCC:.*", ("rcc", "h7rs", "RCC")),
             ("STM32H7[AB].*:RCC:.*", ("rcc", "h7ab", "RCC")),
             ("STM32H7(42|43|53|50).*:RCC:.*", ("rcc", "h7rm0433", "RCC")),
             ("STM32H7.*:RCC:.*", ("rcc", "h7", "RCC")),
@@ -394,6 +396,7 @@ impl PeriMatcher {
             ("STM32C0.*:PWR:.*", ("pwr", "c0", "PWR")),
             ("STM32G0.*:PWR:.*", ("pwr", "g0", "PWR")),
             ("STM32G4.*:PWR:.*", ("pwr", "g4", "PWR")),
+            ("STM32H7[RS].*:PWR:.*", ("pwr", "h7rs", "PWR")),
             ("STM32H7(45|47|55|57).*:PWR:.*", ("pwr", "h7rm0399", "PWR")),
             ("STM32H7(42|43|53|50).*:PWR:.*", ("pwr", "h7rm0433", "PWR")),
             ("STM32H7(23|25|33|35|30).*:PWR:.*", ("pwr", "h7rm0468", "PWR")),
@@ -417,6 +420,7 @@ impl PeriMatcher {
             ("STM32WB.*:PWR:.*", ("pwr", "wb", "PWR")),
             ("STM32H50.*:PWR:.*", ("pwr", "h50", "PWR")),
             ("STM32H5.*:PWR:.*", ("pwr", "h5", "PWR")),
+            ("STM32H7[RS].*:FLASH:.*", ("flash", "h7rs", "FLASH")),
             ("STM32H7(A3|B3|B0).*:FLASH:.*", ("flash", "h7ab", "FLASH")),
             ("STM32H7.*:FLASH:.*", ("flash", "h7", "FLASH")),
             ("STM32F0.*:FLASH:.*", ("flash", "f0", "FLASH")),
@@ -573,7 +577,8 @@ impl PeriMatcher {
             ("STM32WL5.*:HSEM:.*", ("hsem", "v3", "HSEM")),
             ("STM32WLE.*:HSEM:.*", ("hsem", "v4", "HSEM")),
             (".*:DMAMUX.*", ("dmamux", "v1", "DMAMUX")),
-            (r".*:GPDMA\d?:.*", ("gpdma", "v1", "GPDMA")),
+            (r".*:GPDMA\d?:.*", ("gpdma", "v1", "GPDMA")), // TODO there's multiple versions for with+without trustzone.
+            (r".*:HPDMA\d?:.*", ("gpdma", "v1", "GPDMA")), // TODO it has a few more bits like DWX
             (r".*:LPDMA\d?:.*", ("lpdma", "v1", "LPDMA")),
             (r".*:BDMA\d?:.*", ("bdma", "v1", "DMA")),
             ("STM32H7.*:DMA2D:DMA2D:dma2d1_v1_0", ("dma2d", "v2", "DMA2D")),
@@ -661,6 +666,7 @@ impl PeriMatcher {
             (".*:HASH:hash1_v4_0", ("hash", "v3", "HASH")),
             (".*:CRYP:cryp1_v1_0.*", ("cryp", "v1", "CRYP")),
             (".*:CRYP:cryp1_v2_0_H7.*", ("cryp", "v3", "CRYP")),
+            (".*:CRYP:cryp1-v2_5", ("cryp", "v4", "CRYP")),
             (".*:CRYP:cryp1_v2_0.*", ("cryp", "v2", "CRYP")),
             ("STM32F41.*:CRYP:cryp1_v2_2.*", ("cryp", "v1", "CRYP")),
             (".*:CRYP:cryp1_v2_2.*", ("cryp", "v2", "CRYP")),
@@ -807,9 +813,6 @@ pub fn parse_groups() -> Result<(HashMap<String, Chip>, Vec<ChipGroup>), anyhow:
 static NOPELIST: &[&str] = &[
     // Not supported, not planned unless someone wants to do it.
     "STM32MP",
-    // not supported yet, planned. Pull requests welcome!
-    "STM32H7R",
-    "STM32H7S",
     // Does not exist in ST website. No datasheet, no RM.
     "STM32GBK",
     "STM32L485",
@@ -1325,8 +1328,8 @@ fn process_core(
                 );
             }
         }
-            chs.sort_by_key(|ch| (ch.channel.clone(), ch.dmamux.clone(), ch.request));
-            p.dma_channels = chs;
+        chs.sort_by_key(|ch| (ch.channel.clone(), ch.dmamux.clone(), ch.request));
+        p.dma_channels = chs;
     }
 
     let mut core = stm32_data_serde::chip::Core {
diff --git a/stm32-data-gen/src/dma.rs b/stm32-data-gen/src/dma.rs
index 8d9c711..2758ede 100644
--- a/stm32-data-gen/src/dma.rs
+++ b/stm32-data-gen/src/dma.rs
@@ -302,6 +302,8 @@ impl DmaChannels {
             ("U5_GPDMA1.yaml", "GPDMA1", "STM32U5_dma3_Cube", 16, 4),
             ("U5_LPDMA.yaml", "LPDMA1", "STM32U5_dma3_Cube", 4, 0),
             ("WBA_GPDMA1.yaml", "GPDMA1", "STM32WBA_dma3_Cube", 8, 0),
+            ("H7RS_GPDMA.yaml", "GPDMA1", "STM32H7RS_dma3_Cube", 16, 4),
+            ("H7RS_HPDMA.yaml", "HPDMA1", "STM32H7RS_dma3_Cube", 16, 4),
         ] {
             let mut chip_dma = ChipDma {
                 peripherals: HashMap::new(),
diff --git a/stm32-data-gen/src/interrupts.rs b/stm32-data-gen/src/interrupts.rs
index 400fe0c..909c7a2 100644
--- a/stm32-data-gen/src/interrupts.rs
+++ b/stm32-data-gen/src/interrupts.rs
@@ -269,6 +269,8 @@ impl ChipInterrupts {
                 let peri_names: Vec<_> = parts[2]
                     .split(',')
                     .map(|x| if x == "USB_DRD_FS" { "USB" } else { x })
+                    .map(|x| if x == "XPI1" { "XSPI1" } else { x })
+                    .map(|x| if x == "XPI2" { "XSPI2" } else { x })
                     .map(ToString::to_string)
                     .collect();
 
@@ -471,7 +473,7 @@ fn valid_signals(peri: &str) -> Vec<String> {
         ("CAN", &["TX", "RX0", "RX1", "SCE"]),
         ("FDCAN", &["IT0", "IT1", "CAL"]),
         ("I2C", &["ER", "EV"]),
-        ("I3C", &["ER", "EV"]),
+        ("I3C", &["ER", "EV", "WKUP"]),
         ("FMPI2C", &["ER", "EV"]),
         ("TIM", &["BRK", "UP", "TRG", "COM", "CC"]),
         // ("HRTIM", &["Master", "TIMA", "TIMB", "TIMC", "TIMD", "TIME", "TIMF"]),
@@ -499,6 +501,8 @@ fn valid_signals(peri: &str) -> Vec<String> {
         ("USB_OTG_HS", &["GLOBAL", "EP1_OUT", "EP1_IN", "WKUP"]),
         ("USB", &["LP", "HP", "WKUP"]),
         ("GPU2D", &["ER"]),
+        ("SAI", &["A", "B"]),
+        ("ADF", &["FLT0"]),
     ];
 
     for (prefix, signals) in IRQ_SIGNALS_MAP {
@@ -517,6 +521,8 @@ static PICK_NVIC: RegexMap<&str> = RegexMap::new(&[
     ("STM32WL5.*:cm0p", "NVIC2"),
     // Exception 2: TrustZone: NVIC1 is Secure mode, NVIC2 is NonSecure mode. For now, we pick the NonSecure one.
     ("STM32(L5|U5|H5[2367]|WBA5[245]).*", "NVIC2"),
+    // Exception 3: NVICs are split for "bootloader" and "application", not sure what that means?
+    ("STM32H7[RS].*", "NVIC2"),
     // catch-all: Most chips have a single NVIC, named "NVIC"
     (".*", "NVIC"),
 ]);
diff --git a/stm32-data-gen/src/memory.rs b/stm32-data-gen/src/memory.rs
index 56e6149..ad7c627 100644
--- a/stm32-data-gen/src/memory.rs
+++ b/stm32-data-gen/src/memory.rs
@@ -146,6 +146,8 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
     ("STM32H5...E",                  mem!(BANK_1 0x08000000 256, BANK_2 0x08040000 256, SRAM1 0x20000000 128, SRAM2 0x20020000 80, SRAM3 0x20034000 64)),
     ("STM32H5...G",                  mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM1 0x20000000 256, SRAM2 0x20040000 64, SRAM3 0x20050000 320)),
     ("STM32H5...I",                  mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM1 0x20000000 256, SRAM2 0x20040000 64, SRAM3 0x20050000 320)),
+    // H7RS
+    ("STM32H7[RS].*",                mem!(BANK_1 0x08000000 64, ITCM 0x00000000 192, DTCM 0x20000000 192, SRAM1 0x24000000 128, SRAM2 0x24020000 128, SRAM3 0x24040000 128, SRAM4 0x24060000 72, AHB_SRAM1 0x30000000 16, AHB_SRAM2 0x30004000 16)),
     // H7. TODO: check
     ("STM32H7...E",                  mem!(BANK_1 0x08000000 512, SRAM 0x24000000 128)),
     ("STM32H7[23]..G",               mem!(BANK_1 0x08000000 1024, SRAM 0x24000000 128)),
@@ -264,6 +266,7 @@ static FLASH_INFO: RegexMap<FlashInfo> = RegexMap::new(&[
     ("STM32G4[78].*",           FlashInfo{ erase_value: 0xFF, write_size:  8, erase_size: &[(  4*1024, 0)] }),
     ("STM32G4.*",               FlashInfo{ erase_value: 0xFF, write_size:  8, erase_size: &[(  2*1024, 0)] }),
     ("STM32H5.*",               FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[(  8*1024, 0)] }),
+    ("STM32H7[RS].*",           FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[(  8*1024, 0)] }),
     ("STM32H7[AB].*",           FlashInfo{ erase_value: 0xFF, write_size: 32, erase_size: &[(  8*1024, 0)] }),
     ("STM32H7.*",               FlashInfo{ erase_value: 0xFF, write_size: 32, erase_size: &[(128*1024, 0)] }),
     ("STM32L4[PQRS].*",         FlashInfo{ erase_value: 0xFF, write_size:  8, erase_size: &[(  8*1024, 0)] }),
diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs
index 32b63a3..8d489db 100644
--- a/stm32-data-gen/src/rcc.rs
+++ b/stm32-data-gen/src/rcc.rs
@@ -85,13 +85,19 @@ impl ParsedRccs {
             "PLL1_P_MUL_2",
             "PLL1_Q",
             "PLL1_R",
+            "PLL1_S",
+            "PLL1_T",
             "PLL1_VCO", // used for L0 USB
             "PLL2_P",
             "PLL2_Q",
             "PLL2_R",
+            "PLL2_S",
+            "PLL2_T",
             "PLL3_P",
             "PLL3_Q",
             "PLL3_R",
+            "PLL3_S",
+            "PLL3_T",
             "HSI",
             "SHSI",
             "HSI48",
@@ -130,6 +136,10 @@ impl ParsedRccs {
             "HSI256_MSIS1024_MSIK4",
             "HSI256_MSIK1024_MSIS4",
             "HSI256_MSIK1024_MSIK4",
+            "SPDIFRX_SYMB",
+            "ETH_RMII_REF",
+            "ETH",
+            "CLK48MOHCI",
         ]);
 
         let mux_regexes = &[
@@ -137,13 +147,19 @@ impl ParsedRccs {
             regex!(r"^CCIPR\d?/(.+)SEL$"),
             regex!(r"^D\dCCIP\d?R/(.+)SEL$"),
             regex!(r"^CFGR\d/(.+)SW$"),
+            regex!(r"^.+PERCKSELR/(.+)SEL$"),
         ];
+        let mux_nopelist = &[regex!(r"^.+PERCKSELR/USBREFCKSEL$")];
 
         let mut mux = HashMap::new();
         for (reg, body) in &ir.fieldsets {
             for field in &body.fields {
                 let key = format!("{}/{}", reg, field.name);
                 if let Some(capture) = mux_regexes.iter().find_map(|r| r.captures(&key)) {
+                    if mux_nopelist.iter().any(|r| r.is_match(&key)) {
+                        continue;
+                    }
+
                     let peri = capture.get(1).unwrap().as_str();
 
                     // TODO: these bits are duplicated on F4, we need to split the F4 RCCs more.
@@ -331,6 +347,8 @@ impl ParsedRccs {
                         maybe_kernel_clock = "PLL1_Q".to_string();
                     } else if rcc_version.starts_with("l1") {
                         maybe_kernel_clock = "PLL1_VCO_DIV_2".to_string();
+                    } else if rcc_version.starts_with("h7rs") {
+                        maybe_kernel_clock = "USB".to_string();
                     } else {
                         panic!("rcc_{}: peripheral {} missing mux", rcc_version, peri_name)
                     }