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Add stm32u0.

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This commit is contained in:
Dario Nieuwenhuis 2024-04-13 02:52:39 +02:00
parent 7197df07de
commit d4a97f60b1
12 changed files with 4232 additions and 13 deletions
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3
.vscode/settings.json vendored
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@ -3,6 +3,9 @@
"[toml]": {
"editor.formatOnSave": false
},
"[yaml]": {
"editor.formatOnSave": false
},
"[c]": {
"editor.formatOnSave": false
},

2
d
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@ -4,7 +4,7 @@ set -e
cd $(dirname $0)
CMD=$1
REV=796a8322b8f6e4329002a1fb49438aec95dae812
REV=421b5868c2175762ee4c870bb0511ae271abefc9
shift
case "$CMD" in

76
data/dmamux/U0_DMAMUX1.yaml Normal file
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GENERATOR0: 1
GENERATOR1: 2
GENERATOR2: 3
GENERATOR3: 4
ADC1: 5
AES_IN: 6
AES_OUT: 7
DAC1_CH1: 8
I2C1_RX: 9
I2C1_TX: 10
I2C2_RX: 11
I2C2_TX: 12
I2C3_RX: 13
I2C3_TX: 14
I2C4_RX: 15
I2C4_TX: 16
LPTIM1_IC1: 17
LPTIM1_IC2: 18
LPTIM1_IC3: 19
LPTIM1_IC4: 20
LPTIM1_UE4: 21
LPTIM2_IC1: 22
LPTIM2_IC2: 23
LPTIM2_UE: 24
LPTIM3_IC1: 25
LPTIM3_IC2: 26
LPTIM3_IC3: 27
LPTIM3_IC4: 28
LPTIM3_UE: 29
LPUART1_RX: 30
LPUART1_TX: 31
LPUART2_RX: 32
LPUART2_TX: 33
LPUART3_RX: 34
LPUART3_TX: 35
SPI1_RX: 36
SPI1_TX: 37
SPI2_RX: 38
SPI2_TX: 39
SPI3_RX: 40
SPI3_TX: 41
TIM1_CH1: 42
TIM1_CH2: 43
TIM1_CH3: 44
TIM1_CH4: 45
TIM1_TRIG_COM: 46
TIM1_UP: 47
TIM2_CH1: 48
TIM2_CH2: 49
TIM2_CH3: 50
TIM2_CH4: 51
TIM2_TRIG: 52
TIM2_UP: 53
TIM3_CH1: 54
TIM3_CH2: 55
TIM3_CH3: 56
TIM3_CH4: 57
TIM3_TRIG: 58
TIM3_UP: 59
TIM6_UP: 60
TIM7_UP: 61
TIM15_CH1: 62
TIM15_CH2: 63
TIM15_TRIG_COM: 64
TIM15_UP: 65
TIM16_CH1: 66
TIM16_COM: 67
TIM16_UP: 68
USART1_RX: 69
USART1_TX: 70
USART2_RX: 71
USART2_TX: 72
USART3_RX: 73
USART3_TX: 74
USART4_RX: 75
USART4_TX: 76

79
data/registers/exti_u0.yaml Normal file
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block/EXTI:
description: External interrupt/event controller
items:
- name: RTSR
description: Rising Trigger selection register
array:
len: 1
stride: 40
byte_offset: 0
fieldset: LINES
- name: FTSR
description: Falling Trigger selection register
array:
len: 1
stride: 40
byte_offset: 4
fieldset: LINES
- name: SWIER
description: Software interrupt event register
array:
len: 1
stride: 40
byte_offset: 8
fieldset: LINES
- name: RPR
description: Rising pending register
array:
len: 1
stride: 40
byte_offset: 12
fieldset: LINES
- name: FPR
description: Falling pending register
array:
len: 1
stride: 40
byte_offset: 16
fieldset: LINES
- name: EXTICR
description: Configuration register
array:
len: 4
stride: 4
byte_offset: 96
fieldset: EXTICR
- name: IMR
description: Interrupt mask register
array:
len: 2
stride: 16
byte_offset: 128
fieldset: LINES
- name: EMR
description: Event mask register
array:
len: 2
stride: 16
byte_offset: 132
fieldset: LINES
fieldset/EXTICR:
description: external interrupt configuration register 1
fields:
- name: EXTI
description: EXTI configuration bits
bit_offset: 0
bit_size: 8
array:
len: 4
stride: 8
fieldset/LINES:
description: EXTI lines register, 1 bit per line
fields:
- name: LINE
description: EXTI line
bit_offset: 0
bit_size: 1
array:
len: 32
stride: 1

368
data/registers/flash_u0.yaml Normal file
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block/FLASH:
description: Mamba FLASH register block
items:
- name: ACR
description: FLASH access control register
byte_offset: 0
fieldset: ACR
- name: KEYR
description: FLASH key register
byte_offset: 8
fieldset: KEYR
- name: OPTKEYR
description: FLASH option key register
byte_offset: 12
fieldset: OPTKEYR
- name: SR
description: FLASH status register
byte_offset: 16
fieldset: SR
- name: CR
description: FLASH control register
byte_offset: 20
fieldset: CR
- name: ECCR
description: FLASH ECC register
byte_offset: 24
fieldset: ECCR
- name: OPTR
description: FLASH option register
byte_offset: 32
fieldset: OPTR
- name: WRP1AR
description: FLASH WRP area A address register
byte_offset: 44
fieldset: WRP1AR
- name: WRP1BR
description: FLASH WRP area B address register
byte_offset: 48
fieldset: WRP1BR
- name: SECR
description: FLASH security register
byte_offset: 128
fieldset: SECR
fieldset/ACR:
description: FLASH access control register
fields:
- name: LATENCY
description: 'Flash memory access latency The value in this bitfield represents the number of CPU wait states when accessing the flash memory. Other: Reserved A new write into the bitfield becomes effective when it returns the same value upon read.'
bit_offset: 0
bit_size: 3
- name: PRFTEN
description: CPU Prefetch enable
bit_offset: 8
bit_size: 1
- name: ICEN
description: CPU Instruction cache enable
bit_offset: 9
bit_size: 1
- name: ICRST
description: CPU Instruction cache reset This bit can be written only when the instruction cache is disabled.
bit_offset: 11
bit_size: 1
- name: EMPTY
description: Main flash memory area empty This bit indicates whether the first location of the main flash memory area is erased or has a programmed value. The bit can be set and reset by software.
bit_offset: 16
bit_size: 1
- name: DBG_SWEN
description: Debug access software enable Software may use this bit to enable/disable the debugger read access.
bit_offset: 18
bit_size: 1
fieldset/CR:
description: FLASH control register
fields:
- name: PG
description: Flash memory programming enable
bit_offset: 0
bit_size: 1
- name: PER
description: Page erase enable
bit_offset: 1
bit_size: 1
- name: MER1
description: Mass erase When set, this bit triggers the mass erase, that is, all user pages.
bit_offset: 2
bit_size: 1
- name: PNB
description: 'Page number selection These bits select the page to erase: ... Note: Values corresponding to addresses outside the main memory are not allowed.'
bit_offset: 3
bit_size: 7
- name: STRT
description: Start erase operation This bit triggers an erase operation when set. This bit is possible to set only by software and to clear only by hardware. The hardware clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero.
bit_offset: 16
bit_size: 1
- name: OPTSTRT
description: Start of modification of option bytes This bit triggers an options operation when set. This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR.
bit_offset: 17
bit_size: 1
- name: FSTPG
description: Fast programming enable
bit_offset: 18
bit_size: 1
- name: EOPIE
description: End-of-operation interrupt enable This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register.
bit_offset: 24
bit_size: 1
- name: ERRIE
description: Error interrupt enable This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR register.
bit_offset: 25
bit_size: 1
- name: RDERRIE
description: PCROP read error interrupt enable This bit enables the interrupt generation upon setting the RDERR flag in the FLASH_SR register.
bit_offset: 26
bit_size: 1
- name: OBL_LAUNCH
description: Option byte load launch When set, this bit triggers the load of option bytes into option registers. It is automatically cleared upon the completion of the load. The high state of the bit indicates pending option byte load. The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set.
bit_offset: 27
bit_size: 1
- name: SEC_PROT
description: Securable memory area protection enable This bit enables the protection on securable area, provided that a non-null securable memory area size (SEC_SIZE[4:0]) is defined in option bytes. This bit is possible to set only by software and to clear only through a system reset.
bit_offset: 28
bit_size: 1
- name: OPTLOCK
description: Options Lock This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset.
bit_offset: 30
bit_size: 1
- name: LOCK
description: FLASH_CR Lock This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
bit_offset: 31
bit_size: 1
fieldset/ECCR:
description: FLASH ECC register
fields:
- name: ADDR_ECC
description: ECC fail double-word address offset In case of ECC error or ECC correction detected, this bitfield contains double-word offset (multiple of 64 bits) to main Flash memory.
bit_offset: 0
bit_size: 14
- name: SYSF_ECC
description: System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory.
bit_offset: 20
bit_size: 1
- name: ECCCIE
description: ECC correction interrupt enable
bit_offset: 24
bit_size: 1
- name: ECCC
description: ECC correction Set by hardware when one ECC error has been detected and corrected. An interrupt is generated if ECCIE is set. Cleared by writing 1.
bit_offset: 30
bit_size: 1
- name: ECCD
description: ECC detection Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is generated. Cleared by writing 1.
bit_offset: 31
bit_size: 1
fieldset/KEYR:
description: FLASH key register
fields:
- name: KEY
description: 'FLASH key The following values must be written consecutively to unlock the FLASH control register (FLASH_CR), thus enabling programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB'
bit_offset: 0
bit_size: 32
fieldset/OPTKEYR:
description: FLASH option key register
fields:
- name: OPTKEY
description: 'Option byte key The following values must be written consecutively to unlock the flash memory option registers, enabling option byte programming/erasing operations: KEY1: 0x0819 2A3B KEY2: 0x4C5D 6E7F'
bit_offset: 0
bit_size: 32
fieldset/OPTR:
description: FLASH option register
fields:
- name: RDP
description: 'Read protection level Other: Level 1, memories read protection active'
bit_offset: 0
bit_size: 8
enum: RDP
- name: BORR_LEV
description: BOR reset level
bit_offset: 8
bit_size: 3
enum: BORR_LEV
- name: NRST_STOP
description: Reset generated when entering Stop mode
bit_offset: 13
bit_size: 1
- name: NRST_STDBY
description: Reset generated when entering Standby mode
bit_offset: 14
bit_size: 1
- name: NRST_SHDW
description: Reset generated when entering Shutdown mode
bit_offset: 15
bit_size: 1
- name: IWDG_SW
description: Independent watchdog selection
bit_offset: 16
bit_size: 1
- name: IWDG_STOP
description: Independent watchdog counter freeze in Stop mode
bit_offset: 17
bit_size: 1
- name: IWDG_STDBY
description: Independent watchdog counter freeze in Standby mode
bit_offset: 18
bit_size: 1
- name: WWDG_SW
description: Window watchdog selection
bit_offset: 19
bit_size: 1
- name: BDRST
description: Backup domain reset
bit_offset: 21
bit_size: 1
- name: RAM_PARITY_CHECK
description: SRAM parity check control enable/disable
bit_offset: 22
bit_size: 1
- name: BKPSRAM_HW_ERASE_DISABLE
description: Backup SRAM erase prevention
bit_offset: 23
bit_size: 1
- name: NBOOT_SEL
description: BOOT0 signal source selection This option bit defines the source of the BOOT0 signal.
bit_offset: 24
bit_size: 1
- name: NBOOT1
description: 'Boot configuration Together with the BOOT0 pin or option bit NBOOT0 (depending on NBOOT_SEL option bit configuration), this bit selects boot mode from the main flash memory, SRAM or the system memory. Refer to Section12.5: Boot configuration.'
bit_offset: 25
bit_size: 1
- name: NBOOT0
description: NBOOT0 option bit
bit_offset: 26
bit_size: 1
- name: NRST_MODE
description: NRST pin configuration
bit_offset: 27
bit_size: 2
enum: NRST_MODE
- name: IRHEN
description: Internal reset holder enable bit
bit_offset: 29
bit_size: 1
fieldset/SECR:
description: FLASH security register
fields:
- name: HDP1_PEND
description: Last page of the first hide protection area
bit_offset: 0
bit_size: 7
- name: BOOT_LOCK
description: used to force boot from user area If the bit is set in association with RDP level 1, the debug capabilities are disabled, except in the case of a bad OBL (mismatch).
bit_offset: 16
bit_size: 1
- name: HDP1EN
description: Hide protection area enable
bit_offset: 24
bit_size: 8
fieldset/SR:
description: FLASH status register
fields:
- name: EOP
description: End of operation Set by hardware when one or more flash memory operation (programming / erase) has been completed successfully. This bit is set only if the end of operation interrupts are enabled (EOPIE=1). Cleared by writing 1.
bit_offset: 0
bit_size: 1
- name: OPERR
description: Operation error Set by hardware when a flash memory operation (program / erase) completes unsuccessfully. This bit is set only if error interrupts are enabled (ERRIE=1). Cleared by writing 1.
bit_offset: 1
bit_size: 1
- name: PROGERR
description: Programming error Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. Cleared by writing 1.
bit_offset: 3
bit_size: 1
- name: WRPERR
description: Write protection error Set by hardware when an address to be erased/programmed belongs to a write-protected part (by WRP, PCROP or RDP Level 1) of the flash memory. Cleared by writing 1.
bit_offset: 4
bit_size: 1
- name: PGAERR
description: Programming alignment error Set by hardware when the data to program cannot be contained in the same double word (64-bit) flash memory in case of standard programming, or if there is a change of page during fast programming. Cleared by writing 1.
bit_offset: 5
bit_size: 1
- name: SIZERR
description: 'Size error Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). Cleared by writing 1.'
bit_offset: 6
bit_size: 1
- name: PGSERR
description: Programming sequence error Set by hardware when a write access to the flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. Cleared by writing 1.
bit_offset: 7
bit_size: 1
- name: MISSERR
description: Fast programming data miss error In Fast programming mode, 16 double words (128 bytes) must be sent to flash memory successively, and the new data must be sent to the logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time. Cleared by writing 1.
bit_offset: 8
bit_size: 1
- name: FASTERR
description: Fast programming error Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time. Cleared by writing 1.
bit_offset: 9
bit_size: 1
- name: RDERR
description: PCROP read error Set by hardware when an address to be read belongs to a read protected area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR. Cleared by writing 1.
bit_offset: 14
bit_size: 1
- name: OPTVERR
description: Option and Engineering bits loading validity error
bit_offset: 15
bit_size: 1
- name: BSY1
description: Busy This flag indicates that a flash memory operation requested by FLASH control register (FLASH_CR) is in progress. This bit is set at the beginning of the flash memory operation, and cleared when the operation finishes or when an error occurs.
bit_offset: 16
bit_size: 1
- name: CFGBSY
description: Programming or erase configuration busy. This flag is set and cleared by hardware. It is set when the first word is sent for program or when setting the STRT bit of FLASH control register (FLASH_CR) for erase. It is cleared when the flash memory program or erase operation completes or ends with an error. When set, launching any other operation through the FLASH control register (FLASH_CR) is impossible, and must be postponed (a programming or erase operation is ongoing). When cleared, the program and erase settings in the FLASH control register (FLASH_CR) can be modified.
bit_offset: 18
bit_size: 1
fieldset/WRP1AR:
description: FLASH WRP area A address register
fields:
- name: WRP1A_STRT
description: 'WRP area A start offset This bitfield contains the offset of the first page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device.'
bit_offset: 0
bit_size: 7
- name: WRP1A_END
description: 'WRP area A end offset This bitfield contains the offset of the last page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device.'
bit_offset: 16
bit_size: 7
fieldset/WRP1BR:
description: FLASH WRP area B address register
fields:
- name: WRP1B_STRT
description: 'WRP area B start offset This bitfield contains the offset of the first page of the WRP area B. Note: The number of effective bits depends on the size of the flash memory in the device.'
bit_offset: 0
bit_size: 7
- name: WRP1B_END
description: 'WRP area B end offset This bitfield contains the offset of the last page of the WRP area B. Note: The number of effective bits depends on the size of the flash memory in the device.'
bit_offset: 16
bit_size: 7
enum/BORR_LEV:
bit_size: 3
variants:
- name: Level1
description: BOR rising level 1 with threshold around 2.1 V
value: 0
- name: Level2
description: BOR rising level 2 with threshold around 2.3 V
value: 1
- name: Level3
description: BOR rising level 3 with threshold around 2.6 V
value: 2
- name: Level4
description: BOR rising level 4 with threshold around 2.9 V
value: 3
enum/NRST_MODE:
bit_size: 2
variants:
- name: OnlyInput
description: 'Reset input only: a low level on the NRST pin generates system reset; internal RESET is not propagated to the NRST pin.'
value: 1
- name: OnlyInternal
description: 'Standard GPIO: only internal RESET is possible'
value: 2
- name: Bidirectional
description: 'Bidirectional reset: the NRST pin is configured in reset input/output (legacy) mode'
value: 3
enum/RDP:
bit_size: 8
variants:
- name: Level0
description: Level 0, read protection not active
value: 170
- name: Level2
description: Level 2, chip read protection active
value: 204

978
data/registers/pwr_u0.yaml Normal file
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block/PWR:
description: PWR register block
items:
- name: CR1
description: Power control register 1
byte_offset: 0
fieldset: CR1
- name: CR2
description: Power control register 2
byte_offset: 4
fieldset: CR2
- name: CR3
description: Power control register 3
byte_offset: 8
fieldset: CR3
- name: CR4
description: Power control register 4
byte_offset: 12
fieldset: CR4
- name: SR1
description: Power status register 1
byte_offset: 16
fieldset: SR1
- name: SR2
description: Power status register 2
byte_offset: 20
fieldset: SR2
- name: SCR
description: Power status clear register
byte_offset: 24
fieldset: SCR
- name: PUCRA
description: Power Port A pull-up control register
byte_offset: 32
fieldset: PUCRA
- name: PDCRA
description: Power Port A pull-down control register
byte_offset: 36
fieldset: PDCRA
- name: PUCRB
description: Power Port B pull-up control register
byte_offset: 40
fieldset: PUCRB
- name: PDCRB
description: Power Port B pull-down control register
byte_offset: 44
fieldset: PDCRB
- name: PUCRC
description: Power Port C pull-up control register
byte_offset: 48
fieldset: PUCRC
- name: PDCRC
description: Power Port C pull-down control register
byte_offset: 52
fieldset: PDCRC
- name: PUCRD
description: Power Port D pull-up control register
byte_offset: 56
fieldset: PUCRD
- name: PDCRD
description: Power Port D pull-down control register
byte_offset: 60
fieldset: PDCRD
- name: PUCRE
description: Power Port E pull-up control register
byte_offset: 64
fieldset: PUCRE
- name: PDCRE
description: Power Port E pull-down control register
byte_offset: 68
fieldset: PDCRE
- name: PUCRF
description: Power Port F pull-up control register
byte_offset: 72
fieldset: PUCRF
- name: PDCRF
description: Power Port F pull-down control register
byte_offset: 76
fieldset: PDCRF
fieldset/CR1:
description: Power control register 1
fields:
- name: LPMS
description: 'Low-power mode selection These bits select the low-power mode entered when CPU enters the deepsleep mode. 1xx: Shutdown mode Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered instead of Stop 2. Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3.'
bit_offset: 0
bit_size: 3
enum: LPMS
- name: FPD_STOP
description: Flash memory powered down during Stop mode. This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode.
bit_offset: 3
bit_size: 1
- name: FPD_LPRUN
description: Flash memory powered down during Low-power run mode. This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode.
bit_offset: 4
bit_size: 1
- name: FPD_LPSLP
description: Flash memory powered down during Low-power sleep mode. This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode.
bit_offset: 5
bit_size: 1
- name: DBP
description: Disable backup domain write protection In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers.
bit_offset: 8
bit_size: 1
- name: VOS
description: Voltage scaling range selection
bit_offset: 9
bit_size: 2
enum: VOS
- name: LPR
description: 'Low-power run When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead.'
bit_offset: 14
bit_size: 1
fieldset/CR2:
description: Power control register 2
fields:
- name: PVDE
description: 'Programmable voltage detector enable Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: This bit is reset only by a system reset.'
bit_offset: 0
bit_size: 1
- name: PLS
description: 'Programmable voltage detector level selection. These bits select the voltage threshold detected by the programmable voltage detector: Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: These bits are reset only by a system reset.'
bit_offset: 1
bit_size: 3
enum: PLS
- name: PVME1
description: 'Peripheral voltage monitoring 1 enable: V<sub>DDUSB</sub> vs. 1.21V'
bit_offset: 4
bit_size: 1
- name: PVME3
description: 'Peripheral voltage monitoring 3 enable: V<sub>DDA</sub> vs. 1.621V'
bit_offset: 5
bit_size: 1
- name: PVME4
description: 'Peripheral voltage monitoring 4 enable: V<sub>DDA</sub> vs. 1.861V'
bit_offset: 6
bit_size: 1
- name: USV
description: V<sub>DDUSB</sub> USB supply valid This bit is used to validate the V<sub>DDUSB</sub> supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB FS peripheral. If V<sub>DDUSB</sub> is not always present in the application, the PVM can be used to determine whether this supply is ready or not.
bit_offset: 10
bit_size: 1
fieldset/CR3:
description: Power control register 3
fields:
- name: EWUP1
description: Enable Wake-up pin WKUP1 When this bit is set, the external wake-up pin WKUP1 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register.
bit_offset: 0
bit_size: 1
- name: EWUP2
description: Enable Wake-up pin WKUP2 When this bit is set, the external wake-up pin WKUP2 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register.
bit_offset: 1
bit_size: 1
- name: EWUP3
description: Enable Wake-up pin WKUP3 When this bit is set, the external wake-up pin WKUP3 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register.
bit_offset: 2
bit_size: 1
- name: EWUP4
description: Enable Wake-up pin WKUP4 When this bit is set, the external wake-up pin WKUP4 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register.
bit_offset: 3
bit_size: 1
- name: EWUP5
description: Enable Wake-up pin WKUP5 When this bit is set, the external wake-up pin WKUP5 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register.
bit_offset: 4
bit_size: 1
- name: EWUP7
description: Enable Wake-up pin WKUP7. When this bit is set, the external wake-up pin WKUP7 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP7 bit in the PWR_CR4 register.
bit_offset: 6
bit_size: 1
- name: RRS
description: SRAM2 retention in Standby mode
bit_offset: 8
bit_size: 1
- name: ENULP
description: Enable ULP sampling When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous monitoring to reduce power consumption. Fast supply drop between two sample/compare phases is not detected in this mode. This bit has impact only on STOP2, Standby and shutdown low power modes.
bit_offset: 9
bit_size: 1
- name: APC
description: Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os, instead the I/Os are in floating mode during Standby or configured according GPIO controller GPIOx_PUPDR register during RUN mode.
bit_offset: 10
bit_size: 1
- name: EIWUL
description: Enable internal wake-up line
bit_offset: 15
bit_size: 1
fieldset/CR4:
description: Power control register 4
fields:
- name: WP1
description: Wake-up pin WKUP1 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP1
bit_offset: 0
bit_size: 1
- name: WP2
description: Wake-up pin WKUP2 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP2
bit_offset: 1
bit_size: 1
- name: WP3
description: Wake-up pin WKUP3 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP3
bit_offset: 2
bit_size: 1
- name: WP4
description: Wake-up pin WKUP4 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP4
bit_offset: 3
bit_size: 1
- name: WP5
description: Wake-up pin WKUP5 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP5
bit_offset: 4
bit_size: 1
- name: WP7
description: Wake-up pin WKUP7 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP7
bit_offset: 6
bit_size: 1
- name: VBE
description: V<sub>BAT</sub> battery charging enable
bit_offset: 8
bit_size: 1
- name: VBRS
description: V<sub>BAT</sub> battery charging resistor selection
bit_offset: 9
bit_size: 1
fieldset/PDCRA:
description: Power Port A pull-down control register
fields:
- name: PD0
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 0
bit_size: 1
- name: PD1
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 1
bit_size: 1
- name: PD2
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 2
bit_size: 1
- name: PD3
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 3
bit_size: 1
- name: PD4
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 4
bit_size: 1
- name: PD5
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 5
bit_size: 1
- name: PD6
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 6
bit_size: 1
- name: PD7
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 7
bit_size: 1
- name: PD8
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 8
bit_size: 1
- name: PD9
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 9
bit_size: 1
- name: PD10
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 10
bit_size: 1
- name: PD11
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 11
bit_size: 1
- name: PD12
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 12
bit_size: 1
- name: PD13
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 13
bit_size: 1
- name: PD14
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 14
bit_size: 1
- name: PD15
description: Port A pull-down bit y When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.
bit_offset: 15
bit_size: 1
fieldset/PDCRB:
description: Power Port B pull-down control register
fields:
- name: PD0
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 0
bit_size: 1
- name: PD1
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 1
bit_size: 1
- name: PD2
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 2
bit_size: 1
- name: PD3
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 3
bit_size: 1
- name: PD4
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 4
bit_size: 1
- name: PD5
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 5
bit_size: 1
- name: PD6
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 6
bit_size: 1
- name: PD7
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 7
bit_size: 1
- name: PD8
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 8
bit_size: 1
- name: PD9
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 9
bit_size: 1
- name: PD10
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 10
bit_size: 1
- name: PD11
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 11
bit_size: 1
- name: PD12
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 12
bit_size: 1
- name: PD13
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 13
bit_size: 1
- name: PD14
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 14
bit_size: 1
- name: PD15
description: Port B pull-down bit y When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 15
bit_size: 1
fieldset/PDCRC:
description: Power Port C pull-down control register
fields:
- name: PD0
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 0
bit_size: 1
- name: PD1
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 1
bit_size: 1
- name: PD2
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 2
bit_size: 1
- name: PD3
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 3
bit_size: 1
- name: PD4
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 4
bit_size: 1
- name: PD5
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 5
bit_size: 1
- name: PD6
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 6
bit_size: 1
- name: PD7
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 7
bit_size: 1
- name: PD8
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 8
bit_size: 1
- name: PD9
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 9
bit_size: 1
- name: PD10
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 10
bit_size: 1
- name: PD11
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 11
bit_size: 1
- name: PD12
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 12
bit_size: 1
- name: PD13
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 13
bit_size: 1
- name: PD14
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 14
bit_size: 1
- name: PD15
description: Port C pull-down bit y When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
bit_offset: 15
bit_size: 1
fieldset/PDCRD:
description: Power Port D pull-down control register
fields:
- name: PD0
description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
bit_offset: 0
bit_size: 1
- name: PD1
description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
bit_offset: 1
bit_size: 1
- name: PD2
description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
bit_offset: 2
bit_size: 1
- name: PD3
description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
bit_offset: 3
bit_size: 1
- name: PD4
description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
bit_offset: 4
bit_size: 1
- name: PD5
description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
bit_offset: 5
bit_size: 1
- name: PD6
description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
bit_offset: 6
bit_size: 1
- name: PD8
description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
bit_offset: 8
bit_size: 1
- name: PD9
description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
bit_offset: 9
bit_size: 1
- name: PD10
description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
bit_offset: 10
bit_size: 1
- name: PD11
description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
bit_offset: 11
bit_size: 1
- name: PD12
description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
bit_offset: 12
bit_size: 1
- name: PD13
description: Port D pull-down bit y When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.
bit_offset: 13
bit_size: 1
fieldset/PDCRE:
description: Power Port E pull-down control register
fields:
- name: PD3
description: Port E pull-down bit 3 When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.
bit_offset: 3
bit_size: 1
- name: PD7
description: Port E pull-down bit y When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.
bit_offset: 7
bit_size: 1
- name: PD8
description: Port E pull-down bit y When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.
bit_offset: 8
bit_size: 1
- name: PD9
description: Port E pull-down bit y When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.
bit_offset: 9
bit_size: 1
fieldset/PDCRF:
description: Power Port F pull-down control register
fields:
- name: PD0
description: Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register.
bit_offset: 0
bit_size: 1
- name: PD1
description: Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register.
bit_offset: 1
bit_size: 1
- name: PD2
description: Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register.
bit_offset: 2
bit_size: 1
- name: PD3
description: Port F pull-down bit y When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register.
bit_offset: 3
bit_size: 1
fieldset/PUCRA:
description: Power Port A pull-up control register
fields:
- name: PU0
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 0
bit_size: 1
- name: PU1
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 1
bit_size: 1
- name: PU2
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 2
bit_size: 1
- name: PU3
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 3
bit_size: 1
- name: PU4
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 4
bit_size: 1
- name: PU5
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 5
bit_size: 1
- name: PU6
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 6
bit_size: 1
- name: PU7
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 7
bit_size: 1
- name: PU8
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 8
bit_size: 1
- name: PU9
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 9
bit_size: 1
- name: PU10
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 10
bit_size: 1
- name: PU11
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 11
bit_size: 1
- name: PU12
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 12
bit_size: 1
- name: PU13
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 13
bit_size: 1
- name: PU14
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 14
bit_size: 1
- name: PU15
description: Port A pull-up bit y (y1=115 to 0) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 15
bit_size: 1
fieldset/PUCRB:
description: Power Port B pull-up control register
fields:
- name: PU0
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 0
bit_size: 1
- name: PU1
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 1
bit_size: 1
- name: PU2
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 2
bit_size: 1
- name: PU3
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 3
bit_size: 1
- name: PU4
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 4
bit_size: 1
- name: PU5
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 5
bit_size: 1
- name: PU6
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 6
bit_size: 1
- name: PU7
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 7
bit_size: 1
- name: PU8
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 8
bit_size: 1
- name: PU9
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 9
bit_size: 1
- name: PU10
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 10
bit_size: 1
- name: PU11
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 11
bit_size: 1
- name: PU12
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 12
bit_size: 1
- name: PU13
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 13
bit_size: 1
- name: PU14
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 14
bit_size: 1
- name: PU15
description: Port B pull-up bit y When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
bit_offset: 15
bit_size: 1
fieldset/PUCRC:
description: Power Port C pull-up control register
fields:
- name: PU0
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 0
bit_size: 1
- name: PU1
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 1
bit_size: 1
- name: PU2
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 2
bit_size: 1
- name: PU3
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 3
bit_size: 1
- name: PU4
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 4
bit_size: 1
- name: PU5
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 5
bit_size: 1
- name: PU6
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 6
bit_size: 1
- name: PU7
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 7
bit_size: 1
- name: PU8
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 8
bit_size: 1
- name: PU9
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 9
bit_size: 1
- name: PU10
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 10
bit_size: 1
- name: PU11
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 11
bit_size: 1
- name: PU12
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 12
bit_size: 1
- name: PU13
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 13
bit_size: 1
- name: PU14
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 14
bit_size: 1
- name: PU15
description: Port C pull-up bit y When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 15
bit_size: 1
fieldset/PUCRD:
description: Power Port D pull-up control register
fields:
- name: PU0
description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 0
bit_size: 1
- name: PU1
description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 1
bit_size: 1
- name: PU2
description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 2
bit_size: 1
- name: PU3
description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 3
bit_size: 1
- name: PU4
description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 4
bit_size: 1
- name: PU5
description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 5
bit_size: 1
- name: PU6
description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 6
bit_size: 1
- name: PU8
description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 8
bit_size: 1
- name: PU9
description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 9
bit_size: 1
- name: PU10
description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 10
bit_size: 1
- name: PU11
description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 11
bit_size: 1
- name: PU12
description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 12
bit_size: 1
- name: PU13
description: Port D pull-up bit y When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 13
bit_size: 1
fieldset/PUCRE:
description: Power Port E pull-up control register
fields:
- name: PU3
description: Port E pull-up bit 3 When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 3
bit_size: 1
- name: PU7
description: Port E pull-up bit y When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 7
bit_size: 1
- name: PU8
description: Port E pull-up bit y When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 8
bit_size: 1
- name: PU9
description: Port E pull-up bit y When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 9
bit_size: 1
fieldset/PUCRF:
description: Power Port F pull-up control register
fields:
- name: PU0
description: Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 0
bit_size: 1
- name: PU1
description: Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 1
bit_size: 1
- name: PU2
description: Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 2
bit_size: 1
- name: PU3
description: Port F pull-up bit y When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
bit_offset: 3
bit_size: 1
fieldset/SCR:
description: Power status clear register
fields:
- name: CWUF1
description: Clear wake-up flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register.
bit_offset: 0
bit_size: 1
- name: CWUF2
description: Clear wake-up flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register.
bit_offset: 1
bit_size: 1
- name: CWUF3
description: Clear wake-up flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register.
bit_offset: 2
bit_size: 1
- name: CWUF4
description: Clear wake-up flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register.
bit_offset: 3
bit_size: 1
- name: CWUF5
description: Clear wake-up flag 5 Setting this bit clears the WUF5 flag in the PWR_SR1 register.
bit_offset: 4
bit_size: 1
- name: CWUF7
description: Clear wake-up flag 7 Setting this bit clears the WUF7 flag in the PWR_SR1 register.
bit_offset: 6
bit_size: 1
- name: CSBF
description: Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register.
bit_offset: 8
bit_size: 1
fieldset/SR1:
description: Power status register 1
fields:
- name: WUF1
description: Wake-up flag 1 This bit is set when a wake-up event is detected on wake-up pin, WKUP1. It is cleared by writing 1 in the CWUF1 bit of the PWR_SCR register.
bit_offset: 0
bit_size: 1
- name: WUF2
description: Wake-up flag 2 This bit is set when a wake-up event is detected on wake-up pin, WKUP2. It is cleared by writing 1 in the CWUF2 bit of the PWR_SCR register.
bit_offset: 1
bit_size: 1
- name: WUF3
description: Wake-up flag 3 This bit is set when a wake-up event is detected on wake-up pin, WKUP3. It is cleared by writing 1 in the CWUF3 bit of the PWR_SCR register.
bit_offset: 2
bit_size: 1
- name: WUF4
description: Wake-up flag 4 This bit is set when a wake-up event is detected on wake-up pin,WKUP4. It is cleared by writing 1 in the CWUF4 bit of the PWR_SCR register.
bit_offset: 3
bit_size: 1
- name: WUF5
description: Wake-up flag 5 This bit is set when a wake-up event is detected on wake-up pin, WKUP5. It is cleared by writing 1 in the CWUF5 bit of the PWR_SCR register.
bit_offset: 4
bit_size: 1
- name: WUF7
description: Wake-up flag 7 This bit is set when a wake-up event is detected on wake-up pin, WKUP7. It is cleared by writing 1 in the CWUF7 bit of the PWR_SCR register.
bit_offset: 6
bit_size: 1
- name: SBF
description: Standby flag This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset.
bit_offset: 8
bit_size: 1
- name: STOPF
description: Stop Flags These bits are set by hardware when the device enters any stop mode and are cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset.
bit_offset: 9
bit_size: 3
enum: STOPF
- name: WUFI
description: Wake-up flag internal This bit is set when a wake-up is detected on the internal wake-up line. It is cleared when all internal wake-up sources are cleared.
bit_offset: 15
bit_size: 1
fieldset/SR2:
description: Power status register 2
fields:
- name: FLASH_RDY
description: 'Flash ready flag This bit is set by hardware to indicate when the flash memory is readey to be accessed after wake-up from power-down. To place the flash memory in power-down, set either FPD_LPRUN, FPD_LPSLP or FPD_STP bits. Note : If the system boots from SRAM, the user application must wait until the FLASH_RDY bit is set, prior to jumping to flash memory.'
bit_offset: 7
bit_size: 1
- name: REGLPS
description: Low-power regulator started This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wake-up from Standby mode time may be increased.
bit_offset: 8
bit_size: 1
- name: REGLPF
description: Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. This bit is cleared by hardware when the regulator is ready.
bit_offset: 9
bit_size: 1
- name: VOSF
description: Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register.
bit_offset: 10
bit_size: 1
- name: PVDO
description: Programmable voltage detector output
bit_offset: 11
bit_size: 1
- name: PVMO1
description: 'Peripheral voltage monitoring output: V<sub>DDUSB</sub> vs. 1.2 V Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wake-up time.'
bit_offset: 12
bit_size: 1
- name: PVMO3
description: 'Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.621V Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wake-up time.'
bit_offset: 14
bit_size: 1
- name: PVMO4
description: 'Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 2.21V Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wake-up time.'
bit_offset: 15
bit_size: 1
enum/LPMS:
bit_size: 3
variants:
- name: Stop0
description: Stop 0 mode
value: 0
- name: Stop1
description: Stop 1 mode
value: 1
- name: Stop2
description: Stop 2 mode
value: 2
- name: Standby
description: Standby mode
value: 3
enum/PLS:
bit_size: 3
variants:
- name: B_0x0
description: V<sub>PVD0</sub> around 2.01V
value: 0
- name: B_0x1
description: V<sub>PVD1</sub> around 2.21V
value: 1
- name: B_0x2
description: V<sub>PVD2</sub> around 2.41V
value: 2
- name: B_0x3
description: V<sub>PVD3</sub> around 2.51V
value: 3
- name: B_0x4
description: V<sub>PVD4</sub> around 2.61V
value: 4
- name: B_0x5
description: V<sub>PVD5</sub> around 2.81V
value: 5
- name: B_0x6
description: V<sub>PVD6</sub> around 2.91V
value: 6
- name: B_0x7
description: External input analog voltage PVD_IN (compared internally to VREFINT)
value: 7
enum/STOPF:
bit_size: 3
variants:
- name: None
description: The device did not enter any Stop mode.
value: 0
- name: Stop0
description: The device entered in Stop 0 mode.
value: 4
- name: Stop1
description: The device entered in Stop 1 mode.
value: 5
- name: Stop2
description: The device entered in Stop 2 mode.
value: 6
enum/VOS:
bit_size: 2
variants:
- name: Range1
description: Range 1
value: 1
- name: Range2
description: Range 2
value: 2

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block/SYSCFG:
description: SYSCFG register block
items:
- name: CFGR1
description: SYSCFG configuration register 1
byte_offset: 0
fieldset: CFGR1
- name: CFGR2
description: SYSCFG configuration register 2
byte_offset: 24
fieldset: CFGR2
- name: SCSR
description: SYSCFG SRAM2 control and status register
byte_offset: 28
fieldset: SCSR
- name: SKR
description: SYSCFG SRAM2 key register
byte_offset: 32
fieldset: SKR
- name: TSCCR
description: SYSCFG TSC comparator register
byte_offset: 36
fieldset: TSCCR
- name: ITLINE0
description: SYSCFG interrupt line 0 status register
byte_offset: 128
fieldset: ITLINE0
- name: ITLINE1
description: SYSCFG interrupt line 1 status register
byte_offset: 132
fieldset: ITLINE1
- name: ITLINE2
description: SYSCFG interrupt line 2 status register
byte_offset: 136
fieldset: ITLINE2
- name: ITLINE3
description: SYSCFG interrupt line 3 status register
byte_offset: 140
fieldset: ITLINE3
- name: ITLINE4
description: SYSCFG interrupt line 4 status register
byte_offset: 144
fieldset: ITLINE4
- name: ITLINE5
description: SYSCFG interrupt line 5 status register
byte_offset: 148
fieldset: ITLINE5
- name: ITLINE6
description: SYSCFG interrupt line 6 status register
byte_offset: 152
fieldset: ITLINE6
- name: ITLINE7
description: SYSCFG interrupt line 7 status register
byte_offset: 156
fieldset: ITLINE7
- name: ITLINE8
description: SYSCFG interrupt line 8 status register
byte_offset: 160
fieldset: ITLINE8
- name: ITLINE9
description: SYSCFG interrupt line 9 status register
byte_offset: 164
fieldset: ITLINE9
- name: ITLINE10
description: SYSCFG interrupt line 10 status register
byte_offset: 168
fieldset: ITLINE10
- name: ITLINE11
description: SYSCFG interrupt line 11 status register
byte_offset: 172
fieldset: ITLINE11
- name: ITLINE12
description: SYSCFG interrupt line 12 status register
byte_offset: 176
fieldset: ITLINE12
- name: ITLINE13
description: SYSCFG interrupt line 13 status register
byte_offset: 180
fieldset: ITLINE13
- name: ITLINE14
description: SYSCFG interrupt line 14 status register
byte_offset: 184
fieldset: ITLINE14
- name: ITLINE15
description: SYSCFG interrupt line 15 status register
byte_offset: 188
fieldset: ITLINE15
- name: ITLINE16
description: SYSCFG interrupt line 16 status register
byte_offset: 192
fieldset: ITLINE16
- name: ITLINE17
description: SYSCFG interrupt line 17 status register
byte_offset: 196
fieldset: ITLINE17
- name: ITLINE18
description: SYSCFG interrupt line 18 status register
byte_offset: 200
fieldset: ITLINE18
- name: ITLINE19
description: SYSCFG interrupt line 19 status register
byte_offset: 204
fieldset: ITLINE19
- name: ITLINE20
description: SYSCFG interrupt line 20 status register
byte_offset: 208
fieldset: ITLINE20
- name: ITLINE21
description: SYSCFG interrupt line 21 status register
byte_offset: 212
fieldset: ITLINE21
- name: ITLINE22
description: SYSCFG interrupt line 22 status register
byte_offset: 216
fieldset: ITLINE22
- name: ITLINE23
description: SYSCFG interrupt line 23 status register
byte_offset: 220
fieldset: ITLINE23
- name: ITLINE24
description: SYSCFG interrupt line 24 status register
byte_offset: 224
fieldset: ITLINE24
- name: ITLINE25
description: SYSCFG interrupt line 25 status register
byte_offset: 228
fieldset: ITLINE25
- name: ITLINE26
description: SYSCFG interrupt line 26 status register
byte_offset: 232
fieldset: ITLINE26
- name: ITLINE27
description: SYSCFG interrupt line 27 status register
byte_offset: 236
fieldset: ITLINE27
- name: ITLINE28
description: SYSCFG interrupt line 28 status register
byte_offset: 240
fieldset: ITLINE28
- name: ITLINE29
description: SYSCFG interrupt line 29 status register
byte_offset: 244
fieldset: ITLINE29
- name: ITLINE30
description: SYSCFG interrupt line 30 status register
byte_offset: 248
fieldset: ITLINE30
- name: ITLINE31
description: SYSCFG interrupt line 31 status register
byte_offset: 252
fieldset: ITLINE31
fieldset/CFGR1:
description: SYSCFG configuration register 1
fields:
- name: MEM_MODE
description: 'Memory mapping selection bits These bits are set and cleared by software. They control the memory internal mapping at address 0x000010000. After reset these bits take on the value selected by the actual boot mode configuration. Refer to Section12.5: Boot configuration for more details. X0: Main flash memory mapped at 0x000010000'
bit_offset: 0
bit_size: 2
enum: MEM_MODE
- name: PA11_RMP
description: |-
PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port.
0: No remap (PA11)
1: Remap (PA9)
bit_offset: 3
bit_size: 1
- name: PA12_RMP
description: |-
PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port.
0: No remap (PA12)
1: Remap (PA10)
bit_offset: 4
bit_size: 1
- name: IR_POL
description: IR output polarity selection
bit_offset: 5
bit_size: 1
- name: IR_MOD
description: 'IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope:'
bit_offset: 6
bit_size: 2
enum: IR_MOD
- name: BOOSTEN
description: 'I/O analog switch voltage booster enable This bit selects the way of supplying I/O analog switches: When using the analog inputs , setting to 0 is recommended for high V<sub>DD</sub>, setting to 1 for low V<sub>DD</sub> (less than 2.4 V).'
bit_offset: 8
bit_size: 1
- name: I2C_PB6_FMP
description: |-
Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
0: Disable
1: Enable
bit_offset: 16
bit_size: 1
- name: I2C_PB7_FMP
description: |-
Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
0: Disable
1: Enable
bit_offset: 17
bit_size: 1
- name: I2C_PB8_FMP
description: |-
Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
0: Disable
1: Enable
bit_offset: 18
bit_size: 1
- name: I2C_PB9_FMP
description: |-
Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
0: Disable
1: Enable
bit_offset: 19
bit_size: 1
- name: I2C_PA9_FMP
description: |-
Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
0: Disable
1: Enable
bit_offset: 22
bit_size: 1
- name: I2C_PA10_FMP
description: |-
Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
0: Disable
1: Enable
bit_offset: 23
bit_size: 1
- name: I2C3_FMP
description: |-
Fast Mode Plus (FM+) enable for I2C3 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on I/O ports configured as I2C3 can be enabled through their corresponding I2Cx_FMP bit. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
0: Disable
1: Enable
bit_offset: 24
bit_size: 1
fieldset/CFGR2:
description: SYSCFG configuration register 2
fields:
- name: CCL
description: Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP bit enable bit This bit is set by software and cleared by a system reset. It can be use to enable and lock the connection of Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP (Hardfault) output to TIM1/15/16 Break input.
bit_offset: 0
bit_size: 1
- name: SPL
description: SRAM1 parity lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM1 parity error signal connection to TIM1/15/16 Break input.
bit_offset: 1
bit_size: 1
- name: PVDL
description: PVD lock enable bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register.
bit_offset: 2
bit_size: 1
- name: ECCL
description: ECC error lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the flash ECC 2-bit error detection signal connection to TIM1/15/16 Break input.
bit_offset: 3
bit_size: 1
- name: BKPL
description: Backup SRAM2 parity lock This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/15/16 Break input.
bit_offset: 4
bit_size: 1
- name: BKPF
description: Backup SRAM2 parity error flag This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing 1.
bit_offset: 7
bit_size: 1
- name: SPF
description: SRAM1 parity error flag This bit is set by hardware when an SRAM1 parity error is detected. It is cleared by software by writing 1.
bit_offset: 8
bit_size: 1
fieldset/ITLINE0:
description: SYSCFG interrupt line 0 status register
fields:
- name: WWDG
description: Window watchdog interrupt pending flag
bit_offset: 0
bit_size: 1
fieldset/ITLINE1:
description: SYSCFG interrupt line 1 status register
fields:
- name: PVDOUT
description: PVD supply monitoring interrupt request pending (EXTI line 16).
bit_offset: 0
bit_size: 1
- name: PVMOUT1
description: V<sub>DDUSB</sub> supply monitoring interrupt request pending (EXTI line 19)
bit_offset: 1
bit_size: 1
- name: PVMOUT3
description: ADC supply monitoring interrupt request pending (EXTI line 20)
bit_offset: 2
bit_size: 1
- name: PVMOUT4
description: DAC supply monitoring interrupt request pending (EXTI line 21)
bit_offset: 3
bit_size: 1
fieldset/ITLINE10:
description: SYSCFG interrupt line 10 status register
fields:
- name: DMA1_CH2
description: DMA1 channel 2 interrupt request pending
bit_offset: 0
bit_size: 1
- name: DMA1_CH3
description: DMA1 channel 3 interrupt request pending
bit_offset: 1
bit_size: 1
fieldset/ITLINE11:
description: SYSCFG interrupt line 11 status register
fields:
- name: DMAMUX
description: DMAMUX interrupt request pending
bit_offset: 0
bit_size: 1
- name: DMA1_CH4
description: DMA1 channel 4 interrupt request pending
bit_offset: 1
bit_size: 1
- name: DMA1_CH5
description: DMA1 channel 5 interrupt request pending
bit_offset: 2
bit_size: 1
- name: DMA1_CH6
description: DMA1 channel 6 interrupt request pending
bit_offset: 3
bit_size: 1
- name: DMA1_CH7
description: DMA1 channel 7 interrupt request pending
bit_offset: 4
bit_size: 1
- name: DMA2_CH1
description: DMA2 channel 1 interrupt request pending
bit_offset: 5
bit_size: 1
- name: DMA2_CH2
description: DMA2 channel 2 interrupt request pending
bit_offset: 6
bit_size: 1
- name: DMA2_CH3
description: DMA2 channel 3 interrupt request pending
bit_offset: 7
bit_size: 1
- name: DMA2_CH4
description: DMA2 channel 4 interrupt request pending
bit_offset: 8
bit_size: 1
- name: DMA2_CH5
description: DMA2 channel 5 interrupt request pending
bit_offset: 9
bit_size: 1
fieldset/ITLINE12:
description: SYSCFG interrupt line 12 status register
fields:
- name: ADC
description: ADC interrupt request pending
bit_offset: 0
bit_size: 1
- name: COMP1
description: Comparator 1 interrupt request pending (EXTI line 17)
bit_offset: 1
bit_size: 1
- name: COMP2
description: Comparator 2 interrupt request pending (EXTI line 18)
bit_offset: 2
bit_size: 1
fieldset/ITLINE13:
description: SYSCFG interrupt line 13 status register
fields:
- name: TIM1_CCU
description: Timer 1 commutation interrupt request pending
bit_offset: 0
bit_size: 1
- name: TIM1_TRG
description: Timer 1 trigger interrupt request pending
bit_offset: 1
bit_size: 1
- name: TIM1_UPD
description: Timer 1 update interrupt request pending
bit_offset: 2
bit_size: 1
- name: TIM1_BRK
description: Timer 1 break interrupt request pending
bit_offset: 3
bit_size: 1
fieldset/ITLINE14:
description: SYSCFG interrupt line 14 status register
fields:
- name: TIM1_CC1
description: Timer 1 capture compare 1 interrupt request pending
bit_offset: 0
bit_size: 1
- name: TIM1_CC2
description: Timer 1 capture compare 2 interrupt request pending
bit_offset: 1
bit_size: 1
- name: TIM1_CC3
description: Timer 1 capture compare 3 interrupt request pending
bit_offset: 2
bit_size: 1
- name: TIM1_CC4
description: Timer 1 capture compare 4 interrupt request pending
bit_offset: 3
bit_size: 1
fieldset/ITLINE15:
description: SYSCFG interrupt line 15 status register
fields:
- name: TIM2
description: Timer 2 interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE16:
description: SYSCFG interrupt line 16 status register
fields:
- name: TIM3
description: Timer 3 interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE17:
description: SYSCFG interrupt line 17 status register
fields:
- name: TIM6
description: Timer 6 interrupt request pending
bit_offset: 0
bit_size: 1
- name: DAC
description: DAC underrun interrupt request pending
bit_offset: 1
bit_size: 1
- name: LPTIM1
description: Low-power timer 1 interrupt request pending (EXTI line 29)
bit_offset: 2
bit_size: 1
fieldset/ITLINE18:
description: SYSCFG interrupt line 18 status register
fields:
- name: TIM7
description: Timer 7 interrupt request pending
bit_offset: 0
bit_size: 1
- name: LPTIM2
description: Low-power timer 2 interrupt request pending (EXTI line 30)
bit_offset: 1
bit_size: 1
fieldset/ITLINE19:
description: SYSCFG interrupt line 19 status register
fields:
- name: TIM15
description: Timer 15 interrupt request pending
bit_offset: 0
bit_size: 1
- name: LPTIM3
description: Low-power timer 3 interrupt request pending
bit_offset: 1
bit_size: 1
fieldset/ITLINE2:
description: SYSCFG interrupt line 2 status register
fields:
- name: TAMP
description: Tamper interrupt request pending (EXTI line 21)
bit_offset: 0
bit_size: 1
- name: RTC
description: RTC interrupt request pending (EXTI line 19)
bit_offset: 1
bit_size: 1
fieldset/ITLINE20:
description: SYSCFG interrupt line 20 status register
fields:
- name: TIM16
description: Timer 16 interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE21:
description: SYSCFG interrupt line 21 status register
fields:
- name: TSC_MCE
description: TSC max count error interrupt request pending
bit_offset: 0
bit_size: 1
- name: TSC_EOA
description: TSC end of acquisition interrupt request pending
bit_offset: 1
bit_size: 1
fieldset/ITLINE22:
description: SYSCFG interrupt line 22 status register
fields:
- name: LCD
description: LCD interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE23:
description: SYSCFG interrupt line 23 status register
fields:
- name: I2C1
description: I2C1 interrupt request pending (EXTI line 33)
bit_offset: 0
bit_size: 1
fieldset/ITLINE24:
description: SYSCFG interrupt line 24 status register
fields:
- name: I2C2
description: I2C2 interrupt request pending
bit_offset: 0
bit_size: 1
- name: I2C4
description: I2C4 interrupt request pending
bit_offset: 1
bit_size: 1
- name: I2C3
description: I2C3 interrupt request pending (EXTI line 23)
bit_offset: 2
bit_size: 1
fieldset/ITLINE25:
description: SYSCFG interrupt line 25 status register
fields:
- name: SPI1
description: SPI1 interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE26:
description: SYSCFG interrupt line 26 status register
fields:
- name: SPI2
description: SPI2 interrupt request pending
bit_offset: 0
bit_size: 1
- name: SPI3
description: SPI3 interrupt request pending
bit_offset: 1
bit_size: 1
fieldset/ITLINE27:
description: SYSCFG interrupt line 27 status register
fields:
- name: USART1
description: USART1 interrupt request pending, combined with EXTI line 25
bit_offset: 0
bit_size: 1
fieldset/ITLINE28:
description: SYSCFG interrupt line 28 status register
fields:
- name: USART2
description: USART2 interrupt request pending (EXTI line 35)
bit_offset: 0
bit_size: 1
- name: LPUART2
description: LPUART2 interrupt request pending (EXTI line 31)
bit_offset: 1
bit_size: 1
fieldset/ITLINE29:
description: SYSCFG interrupt line 29 status register
fields:
- name: USART3
description: USART3 interrupt request pending
bit_offset: 0
bit_size: 1
- name: LPUART1
description: LPUART1 interrupt request pending (EXTI line 30)
bit_offset: 1
bit_size: 1
fieldset/ITLINE3:
description: SYSCFG interrupt line 3 status register
fields:
- name: FLASH_ITF
description: Flash interface interrupt request pending
bit_offset: 0
bit_size: 1
- name: FLASH_ECC
description: Flash interface ECC interrupt request pending
bit_offset: 1
bit_size: 1
fieldset/ITLINE30:
description: SYSCFG interrupt line 30 status register
fields:
- name: USART4
description: USART4 interrupt request pending
bit_offset: 0
bit_size: 1
- name: LPUART3
description: LPUART3 interrupt request pending (EXTI line 32)
bit_offset: 1
bit_size: 1
fieldset/ITLINE31:
description: SYSCFG interrupt line 31 status register
fields:
- name: RNG
description: RNG interrupt request pending
bit_offset: 0
bit_size: 1
- name: AES
description: AES interrupt request pending
bit_offset: 1
bit_size: 1
fieldset/ITLINE4:
description: SYSCFG interrupt line 4 status register
fields:
- name: RCC
description: Reset and clock control interrupt request pending
bit_offset: 0
bit_size: 1
- name: CRS
description: CRS interrupt request pending
bit_offset: 1
bit_size: 1
fieldset/ITLINE5:
description: SYSCFG interrupt line 5 status register
fields:
- name: EXTI0
description: EXTI line 0 interrupt request pending
bit_offset: 0
bit_size: 1
- name: EXTI1
description: EXTI line 1 interrupt request pending
bit_offset: 1
bit_size: 1
fieldset/ITLINE6:
description: SYSCFG interrupt line 6 status register
fields:
- name: EXTI2
description: EXTI line 2 interrupt request pending
bit_offset: 0
bit_size: 1
- name: EXTI3
description: EXTI line 3 interrupt request pending
bit_offset: 1
bit_size: 1
fieldset/ITLINE7:
description: SYSCFG interrupt line 7 status register
fields:
- name: EXTI4
description: EXTI line 4 interrupt request pending
bit_offset: 0
bit_size: 1
- name: EXTI5
description: EXTI line 5 interrupt request pending
bit_offset: 1
bit_size: 1
- name: EXTI6
description: EXTI line 6 interrupt request pending
bit_offset: 2
bit_size: 1
- name: EXTI7
description: EXTI line 7 interrupt request pending
bit_offset: 3
bit_size: 1
- name: EXTI8
description: EXTI line 8 interrupt request pending
bit_offset: 4
bit_size: 1
- name: EXTI9
description: EXTI line 9 interrupt request pending
bit_offset: 5
bit_size: 1
- name: EXTI10
description: EXTI line 10 interrupt request pending
bit_offset: 6
bit_size: 1
- name: EXTI11
description: EXTI line 11 interrupt request pending
bit_offset: 7
bit_size: 1
- name: EXTI12
description: EXTI line 12 interrupt request pending
bit_offset: 8
bit_size: 1
- name: EXTI13
description: EXTI line 13 interrupt request pending
bit_offset: 9
bit_size: 1
- name: EXTI14
description: EXTI line 14 interrupt request pending
bit_offset: 10
bit_size: 1
- name: EXTI15
description: EXTI line 15 interrupt request pending
bit_offset: 11
bit_size: 1
fieldset/ITLINE8:
description: SYSCFG interrupt line 8 status register
fields:
- name: USB
description: USB interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/ITLINE9:
description: SYSCFG interrupt line 9 status register
fields:
- name: DMA1_CH1
description: DMA1 channel 1 interrupt request pending
bit_offset: 0
bit_size: 1
fieldset/SCSR:
description: SYSCFG SRAM2 control and status register
fields:
- name: SRAM2ER
description: 'SRAM2 erase Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation. Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register.'
bit_offset: 0
bit_size: 1
- name: SRAM2BSY
description: SRAM2 busy by erase operation
bit_offset: 1
bit_size: 1
fieldset/SKR:
description: SYSCFG SRAM2 key register
fields:
- name: KEY
description: 'SRAM2 write protection key for software erase The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register: Write 0xCA into KEY[7:0] Write 0x53 into KEY[7:0] Writing a wrong key reactivates the write protection.'
bit_offset: 0
bit_size: 8
fieldset/TSCCR:
description: SYSCFG TSC comparator register
fields:
- name: G2_IO1
description: Comparator mode for group 2 on I/O 1
bit_offset: 0
bit_size: 1
- name: G2_IO3
description: Comparator mode for group 2 on I/O 3
bit_offset: 1
bit_size: 1
- name: G4_IO3
description: Comparator mode for group 4 on I/O 3
bit_offset: 2
bit_size: 1
- name: G6_IO1
description: Comparator mode for group 6 on I/O 1
bit_offset: 3
bit_size: 1
- name: G7_IO1
description: Comparator mode for group 7 on I/O 1
bit_offset: 4
bit_size: 1
- name: TSC_IOCTRL
description: I/O control in comparator mode The I/O control in comparator mode can be overwritten by hardware.
bit_offset: 5
bit_size: 1
enum/IR_MOD:
bit_size: 2
variants:
- name: TIM16
description: TIM16
value: 0
- name: USART1
description: USART1
value: 1
- name: USART2
description: USART2
value: 2
enum/MEM_MODE:
bit_size: 2
variants:
- name: System_Flash
description: System flash memory mapped at 0x000010000
value: 1
- name: SRAM
description: Embedded SRAM mapped at 0x000010000
value: 3

37
stm32-data-gen/src/chips.rs
View File

@ -248,6 +248,7 @@ impl PeriMatcher {
("syscfg", "h7od", "SYSCFG"),
),
("STM32H7.*:SYSCFG:.*", ("syscfg", "h7", "SYSCFG")),
("STM32U0.*:SYSCFG:.*", ("syscfg", "u0", "SYSCFG")),
("STM32U5.*:SYSCFG:.*", ("syscfg", "u5", "SYSCFG")),
("STM32WBA.*:SYSCFG:.*", ("syscfg", "wba", "SYSCFG")),
("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")),
@ -343,6 +344,7 @@ impl PeriMatcher {
("STM32L4[PQRS].*:RCC:.*", ("rcc", "l4plus", "RCC")),
("STM32L4.*:RCC:.*", ("rcc", "l4", "RCC")),
("STM32L5.*:RCC:.*", ("rcc", "l5", "RCC")),
("STM32U0.*:RCC:.*", ("rcc", "u0", "RCC")),
("STM32U5.*:RCC:.*", ("rcc", "u5", "RCC")),
("STM32H50.*:RCC:.*", ("rcc", "h50", "RCC")),
("STM32H5.*:RCC:.*", ("rcc", "h5", "RCC")),
@ -358,6 +360,7 @@ impl PeriMatcher {
("STM32C0.*:EXTI:.*", ("exti", "c0", "EXTI")),
("STM32G0.*:EXTI:.*", ("exti", "g0", "EXTI")),
("STM32H7.*:EXTI:.*", ("exti", "h7", "EXTI")),
("STM32U0.*:EXTI:.*", ("exti", "u0", "EXTI")),
("STM32U5.*:EXTI:.*", ("exti", "u5", "EXTI")),
("STM32WB.*:EXTI:.*", ("exti", "w", "EXTI")),
("STM32WL5.*:EXTI:.*", ("exti", "w", "EXTI")),
@ -395,6 +398,7 @@ impl PeriMatcher {
("STM32L1.*:PWR:.*", ("pwr", "l1", "PWR")),
("STM32L4.*:PWR:.*", ("pwr", "l4", "PWR")),
("STM32L5.*:PWR:.*", ("pwr", "l5", "PWR")),
("STM32U0.*:PWR:.*", ("pwr", "u0", "PWR")),
("STM32U5.*:PWR:.*", ("pwr", "u5", "PWR")),
("STM32WL.*:PWR:.*", ("pwr", "wl5", "PWR")),
("STM32WBA.*:PWR:.*", ("pwr", "wba", "PWR")),
@ -414,6 +418,7 @@ impl PeriMatcher {
("STM32L1.*:FLASH:.*", ("flash", "l1", "FLASH")),
("STM32L4.*:FLASH:.*", ("flash", "l4", "FLASH")),
("STM32L5.*:FLASH:.*", ("flash", "l5", "FLASH")),
("STM32U0.*:FLASH:.*", ("flash", "u0", "FLASH")),
("STM32U5.*:FLASH:.*", ("flash", "u5", "FLASH")),
("STM32WBA.*:FLASH:.*", ("flash", "wba", "FLASH")),
("STM32WB.*:FLASH:.*", ("flash", "wb", "FLASH")),
@ -490,14 +495,17 @@ impl PeriMatcher {
// AN4013 Table 4: STM32Gx/Hx/Ux/Wx (and Cx) serials
// timer_v2 for STM32Gx/Hx/Ux/Wx (and Cx) serials
("STM32U5.*:TIM(3|4):.*", ("timer", "v2", "TIM_GP32")),
("STM32(G4|H5|U5|WBA).*:TIM(1|8|20):.*", ("timer", "v2", "TIM_ADV")),
("STM32(G4|H5|U5|WBA).*:TIM(2|5|23|24):.*", ("timer", "v2", "TIM_GP32")),
("STM32(G4|H5|U5|WBA).*:TIM(3|4):.*", ("timer", "v2", "TIM_GP16")),
("STM32(G4|H5|U5|WBA).*:TIM(6|7):.*", ("timer", "v2", "TIM_BASIC")),
("STM32(G4|H5|U5|WBA).*:TIM(13|14):.*", ("timer", "v2", "TIM_1CH")),
("STM32(G4|H5|U5|WBA).*:TIM12:.*", ("timer", "v2", "TIM_2CH")),
("STM32(G4|H5|U5|WBA).*:TIM15:.*", ("timer", "v2", "TIM_2CH_CMP")),
("STM32(G4|H5|U5|WBA).*:TIM(16|17):.*", ("timer", "v2", "TIM_1CH_CMP")),
("STM32(G4|H5|U0|U5|WBA).*:TIM(1|8|20):.*", ("timer", "v2", "TIM_ADV")),
(
"STM32(G4|H5|U0|U5|WBA).*:TIM(2|5|23|24):.*",
("timer", "v2", "TIM_GP32"),
),
("STM32(G4|H5|U0|U5|WBA).*:TIM(3|4):.*", ("timer", "v2", "TIM_GP16")),
("STM32(G4|H5|U0|U5|WBA).*:TIM(6|7):.*", ("timer", "v2", "TIM_BASIC")),
("STM32(G4|H5|U0|U5|WBA).*:TIM(13|14):.*", ("timer", "v2", "TIM_1CH")),
("STM32(G4|H5|U0|U5|WBA).*:TIM12:.*", ("timer", "v2", "TIM_2CH")),
("STM32(G4|H5|U0|U5|WBA).*:TIM15:.*", ("timer", "v2", "TIM_2CH_CMP")),
("STM32(G4|H5|U0|U5|WBA).*:TIM(16|17):.*", ("timer", "v2", "TIM_1CH_CMP")),
("STM32WL.*:LPTIM.*:.*", ("lptim", "v2a", "LPTIM")),
("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2b", "LPTIM_ADV")),
("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2b", "LPTIM_BASIC")),
@ -776,11 +784,19 @@ pub fn parse_groups() -> Result<(HashMap<String, Chip>, Vec<ChipGroup>), anyhow:
static NOPELIST: &[&str] = &[
// Not supported, not planned unless someone wants to do it.
"STM32MP",
// not supported yet, planned. Pull requests welcome!
"STM32H52",
"STM32H53",
"STM32H7R",
"STM32H7S",
"STM32U5F",
"STM32U5G",
"STM32WBA50",
"STM32WBA54",
"STM32WBA55",
// Does not exist in ST website. No datasheet, no RM.
"STM32GBK",
"STM32L485",
"STM32U5F",
"STM32U5G",
// STM32WxM modules. These are based on a chip that's supported on its own,
// not sure why we want a separate target for it.
"STM32WL5M",
@ -1432,7 +1448,6 @@ pub fn dump_all_chips(
&peripheral_to_clock,
&dma_channels,
&chips,
&memories,
&docs,
)
})

8
stm32-data-gen/src/interrupts.rs
View File

@ -245,6 +245,14 @@ impl ChipInterrupts {
interrupt_signals.insert(("RCC".to_string(), "CRS".to_string()));
} else if name == "RCC" {
interrupt_signals.insert(("RCC".to_string(), "GLOBAL".to_string()));
} else if name == "RNG_CRYP" {
interrupt_signals.insert(("RNG".to_string(), "GLOBAL".to_string()));
interrupt_signals.insert(("CRYP".to_string(), "GLOBAL".to_string()));
} else if name == "WWDG_IWDG" {
interrupt_signals.insert(("WWDG".to_string(), "GLOBAL".to_string()));
interrupt_signals.insert(("IWDG".to_string(), "GLOBAL".to_string()));
} else if name == "RCC_AUDIOSYNC" {
// ignore
} else {
if parts[2].is_empty() {
trace!(" skipping because parts[2].is_empty()");

30
stm32-data-gen/src/memory.rs
View File

@ -24,10 +24,12 @@ macro_rules! mem {
#[rustfmt::skip]
static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
// C0. TODO: check
("STM32C01..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 6)),
("STM32C01..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 6)),
("STM32C03..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 12)),
("STM32C03..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 12)),
// F0. TODO: check
("STM32F0...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32)),
("STM32F0[35]..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 8)),
("STM32F0[47]..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 6)),
@ -39,6 +41,7 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
("STM32F07..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 16)),
("STM32F07..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 16)),
("STM32F09..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 32)),
// F1. TODO: check
("STM32F1.[12].6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 6)),
("STM32F1.[12].8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 10)),
("STM32F1.[12].B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 16)),
@ -66,12 +69,14 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
("STM32F1.5.8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 64)),
("STM32F10[012].4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 4)),
("STM32F103.4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 6)),
// F2. TODO: check
("STM32F2...B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 64, SRAM2 0x2001c000 0)),
("STM32F2...E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
("STM32F2...F", mem!(BANK_1 0x08000000 768, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
("STM32F2...G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
("STM32F2.5.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 96, SRAM2 0x2001c000 0)),
("STM32F2.7.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
// F3. TODO: check
("STM32F3...4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 12)),
("STM32F3...D", mem!(BANK_1 0x08000000 384, SRAM 0x20000000 64)),
("STM32F3...E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 64)),
@ -83,6 +88,7 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
("STM32F30..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 32)),
("STM32F37..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 24)),
("STM32F37..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32)),
// F4. TODO: check
("STM32F4...8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 32)),
("STM32F4...D", mem!(BANK_1 0x08000000 384, SRAM 0x20000000 64)),
("STM32F4...H", mem!(BANK_1 0x08000000 1536, SRAM 0x20000000 320, SRAM2 0x20040000 0)),
@ -102,6 +108,7 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
("STM32F413.G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 320, SRAM2 0x20040000 0)),
("STM32F429.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 192, SRAM2 0x2001c000 0)),
("STM32F469.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 320, SRAM2 0x20028000 0)),
// F7. TODO: check
("STM32F7...C", mem!(BANK_1 0x08000000 256, SRAM 0x20010000 192, SRAM2 0x2003c000 0)),
("STM32F7...I", mem!(BANK_1 0x08000000 2048, SRAM 0x20020000 384, SRAM2 0x2007c000 0)),
("STM32F7[23]..E", mem!(BANK_1 0x08000000 512, SRAM 0x20010000 192, SRAM2 0x2003c000 0)),
@ -110,6 +117,7 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
("STM32F74..E", mem!(BANK_1 0x08000000 512, SRAM 0x20010000 320, SRAM2 0x2004c000 0)),
("STM32F75..8", mem!(BANK_1 0x08000000 64, SRAM 0x20010000 320, SRAM2 0x2004c000 0)),
("STM32F76..G", mem!(BANK_1 0x08000000 1024, SRAM 0x20020000 384, SRAM2 0x2007c000 0)),
// G0. TODO: check
("STM32G0...4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 8)),
("STM32G0...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 128)),
("STM32G0...E", mem!(BANK_1 0x08000000 256, BANK_2 0x08040000 256, SRAM 0x20000000 128)),
@ -120,6 +128,7 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
("STM32G07..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 32)),
("STM32G07..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 32)),
("STM32G0B..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 128)),
// G4. TODO: check
("STM32G4...6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 20, SRAM2 0x20004000 0)),
("STM32G4...8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 20, SRAM2 0x20004000 0)),
("STM32G4[34]..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 20, SRAM2 0x20004000 0)),
@ -128,9 +137,11 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
("STM32G47..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 96, SRAM2 0x20014000 0)),
("STM32G47..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 96, SRAM2 0x20014000 0)),
("STM32G49..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32, SRAM2 0x20014000 0)),
// H5. TODO: check
("STM32H5...B", mem!(BANK_1 0x08000000 64, BANK_2 0x08010000 64, SRAM 0x20000000 32, SRAM2 0x20004000 0)),
("STM32H5...G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 256, SRAM2 0x20040000 0)),
("STM32H5...I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x20000000 256, SRAM2 0x20040000 0)),
// H7. TODO: check
("STM32H7...E", mem!(D1_ITCMRAM 0x00000000 0, D1_AXIFLASH 0x08000000 0, BANK_1 0x08000000 512, D1_AXIICP 0x1ff00000 0, D1_DTCMRAM 0x20000000 0, SRAM 0x24000000 128, D3_SRAM 0x38000000 0, D3_BKPSRAM 0x38800000 0)),
("STM32H7[23]..G", mem!(D1_ITCMRAM 0x00000000 0, D1_AXIFLASH 0x08000000 0, BANK_1 0x08000000 1024, D1_AXIICP 0x1ff00000 0, D1_DTCMRAM 0x20000000 0, SRAM 0x24000000 128, D3_SRAM 0x38000000 0, D3_BKPSRAM 0x38800000 0)),
("STM32H7[45]..I", mem!(D1_ITCMRAM 0x00000000 0, D1_AXIFLASH 0x08000000 0, BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, D2_AXISRAM 0x10000000 0, D1_AXIICP 0x1ff00000 0, D1_DTCMRAM 0x20000000 0, SRAM 0x24000000 512, D3_SRAM 0x38000000 0, D3_BKPSRAM 0x38800000 0)),
@ -140,6 +151,7 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
("STM32H75..B", mem!(D1_ITCMRAM 0x00000000 0, D1_AXIFLASH 0x08000000 0, BANK_1 0x08000000 128, D2_AXISRAM 0x10000000 0, D1_AXIICP 0x1ff00000 0, D1_DTCMRAM 0x20000000 0, SRAM 0x24000000 512, D3_SRAM 0x38000000 0, D3_BKPSRAM 0x38800000 0)),
("STM32H7A..G", mem!(BANK_1 0x08000000 1024, SRAM 0x24000000 1024)),
("STM32H7B..B", mem!(BANK_1 0x08000000 128, SRAM 0x24000000 1024)),
// L0. TODO: check
("STM32L0...3", mem!(BANK_1 0x08000000 8, SRAM 0x20000000 2)),
("STM32L0...6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 8)),
("STM32L0...B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 20)),
@ -148,6 +160,7 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
("STM32L0[156]..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 8)),
("STM32L0[34]..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 8)),
("STM32L0[78]..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 20)),
// L1. TODO: check
("STM32L1...B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 10)),
("STM32L1...C..", mem!(BANK_1 0x08000000 192, BANK_2 0x08030000 64, SRAM 0x20000000 32)),
("STM32L1...D..", mem!(BANK_1 0x08000000 128, BANK_2 0x08040000 256, SRAM 0x20000000 80)),
@ -166,6 +179,7 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
("STM32L15..8..", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 16)),
("STM32L15..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 10)),
("STM32L15..B..", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 16)),
// L4. TODO: check
("STM32L4...8", mem!(BANK_1 0x08000000 64, SRAM2 0x10000000 0, SRAM 0x20000000 40)),
("STM32L4...I", mem!(BANK_1 0x08000000 2048, SRAM2 0x10000000 0, SRAM 0x20000000 192)),
("STM32L4[12]..B", mem!(BANK_1 0x08000000 128, SRAM2 0x10000000 0, SRAM 0x20000000 40)),
@ -173,15 +187,25 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
("STM32L4[56]..E", mem!(BANK_1 0x08000000 512, SRAM2 0x10000000 0, SRAM 0x20000000 128)),
("STM32L4[78]..G", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM2 0x10000000 0, SRAM 0x20000000 96)),
("STM32L4[9A]..G", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM2 0x10000000 0, SRAM 0x20000000 256)),
("STM32L4[PQR]..G", mem!(BANK_1 0x08000000 1024, SRAM2 0x10000000 0, SRAM 0x20000000 192)),
("STM32L43..B", mem!(BANK_1 0x08000000 128, SRAM2 0x10000000 0, SRAM 0x20000000 48)),
("STM32L45..C", mem!(BANK_1 0x08000000 256, SRAM2 0x10000000 0, SRAM 0x20000000 128)),
("STM32L47..C", mem!(BANK_1 0x08000000 256, SRAM2 0x10000000 0, SRAM 0x20000000 96)),
("STM32L47..E", mem!(BANK_1 0x08000000 512, SRAM2 0x10000000 0, SRAM 0x20000000 96)),
("STM32L49..E", mem!(BANK_1 0x08000000 512, SRAM2 0x10000000 0, SRAM 0x20000000 256)),
// L4+. TODO: check
("STM32L4[PQR]..G", mem!(BANK_1 0x08000000 1024, SRAM2 0x10000000 0, SRAM 0x20000000 192)),
("STM32L4P..E", mem!(BANK_1 0x08000000 512, SRAM2 0x10000000 0, SRAM 0x20000000 192)),
// L5. TODO: check
("STM32L5...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 256, SRAM2 0x20030000 0)),
("STM32L5...E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 256, SRAM2 0x20030000 0)),
// U0
("STM32U031.4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 12)),
("STM32U031.6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 12)),
("STM32U031.8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 12)),
("STM32U0[78]3.8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 40)),
("STM32U0[78]3.B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 40)),
("STM32U0[78]3.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 40)),
// U5
("STM32U5[34]..B", mem!(BANK_1 0x08000000 64, BANK_2 0x08010000 64, SRAM 0x20000000 192, SRAM2 0x20030000 64)),
("STM32U5[34]..C", mem!(BANK_1 0x08000000 128, BANK_2 0x08020000 128, SRAM 0x20000000 192, SRAM2 0x20030000 64)),
("STM32U5[43]..E", mem!(BANK_1 0x08000000 256, BANK_2 0x08040000 256, SRAM 0x20000000 192, SRAM2 0x20030000 64)),
@ -190,6 +214,7 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
("STM32U5[9A]..I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x20000000 768, SRAM2 0x200c0000 64, SRAM3 0x200d0000 832, SRAM5 0x201a0000 832)),
("STM32U5[9A]..J", mem!(BANK_1 0x08000000 2048, BANK_2 0x08200000 2048, SRAM 0x20000000 768, SRAM2 0x200c0000 64, SRAM3 0x200d0000 832, SRAM5 0x201a0000 832)),
("STM32U5[FG]..J", mem!(BANK_1 0x08000000 2048, BANK_2 0x08200000 2048, SRAM 0x20000000 768, SRAM2 0x200c0000 64, SRAM3 0x200d0000 832, SRAM5 0x201a0000 832, SRAM6 0x20270000 512)),
// WB. TODO: check
("STM32WB...Y", mem!(BANK_1 0x08000000 640, SRAM 0x20000000 192)),
("STM32WB.(0C|5V)G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 128)),
("STM32WB.(5C|5R)G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 192)),
@ -199,8 +224,10 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
("STM32WB5..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 128)),
("STM32WB5.[CR]E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 192)),
("STM32WB5.VE", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 128)),
// WBA. TODO: check
("STM32WBA...E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 96, SRAM2 0x20010000 0)),
("STM32WBA...G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 128, SRAM2 0x20010000 0)),
// WL. TODO: check
("STM32WL...8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 12, SRAM2 0x20008000 0)),
("STM32WL...B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 12, SRAM2 0x20008000 0)),
("STM32WL...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 12, SRAM2 0x20008000 0)),
@ -237,6 +264,7 @@ static FLASH_INFO: RegexMap<FlashInfo> = RegexMap::new(&[
("STM32L0.*", FlashInfo{ erase_value: 0x00, write_size: 4, erase_size: &[( 128, 0)] }),
("STM32L1.*", FlashInfo{ erase_value: 0x00, write_size: 4, erase_size: &[( 256, 0)] }),
("STM32L5.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 4*1024, 0)] }),
("STM32U0.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
("STM32U5[78].*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 8*1024, 0)] }),
("STM32U5.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 16*1024, 0)] }),
("STM32WBA.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 8*1024, 0)] }),

1
stm32-metapac-gen/res/Cargo.toml
View File

@ -36,6 +36,7 @@ flavors = [
{ regex_feature = "stm32l1.*", target = "thumbv7m-none-eabi" },
{ regex_feature = "stm32l4.*", target = "thumbv7em-none-eabi" },
{ regex_feature = "stm32l5.*", target = "thumbv8m.main-none-eabihf" },
{ regex_feature = "stm32u0.*", target = "thumbv6m-none-eabi" },
{ regex_feature = "stm32u5.*", target = "thumbv8m.main-none-eabihf" },
{ regex_feature = "stm32wb.*", target = "thumbv7em-none-eabi" },
{ regex_feature = "stm32wl.*", target = "thumbv7em-none-eabi" },