Merge pull request #468 from Systemscape/main

Add DSIHOST support

data/registers/ltdc_v1.yaml

@@ -145,14 +145,16 @@ fieldset/BCCR:
 fieldset/BFCR:
   description: Layerx Blending Factors Configuration Register
   fields:
-  - name: BF
+  - name: BF2
     description: Blending Factor 2
     bit_offset: 0
     bit_size: 3
-    array:
-      len: 2
-      stride: 8
     enum: BF2
+  - name: BF1
+    description: Blending Factor 1
+    bit_offset: 8
+    bit_size: 3
+    enum: BF1
 fieldset/BPCR:
   description: Back Porch Configuration Register
   fields:
@@ -470,6 +472,15 @@ fieldset/WVPCR:
     description: Window Vertical Stop Position
     bit_offset: 16
     bit_size: 11
+enum/BF1:
+  bit_size: 3
+  variants:
+  - name: Constant
+    description: BF1 = constant alpha
+    value: 4
+  - name: Pixel
+    description: BF1 = pixel alpha * constant alpha
+    value: 7
 enum/BF2:
   bit_size: 3
   variants:

data/registers/rcc_h7.yaml

@@ -3073,9 +3073,10 @@ fieldset/D1CCIPR:
     bit_size: 2
     enum: FMCSEL
   - name: DSISEL
-    description: kernel clock source selection
+    description: DSI clock source selection (not available on all chips)
     bit_offset: 8
     bit_size: 1
+    enum: DSISEL
   - name: SDMMCSEL
     description: SDMMC kernel clock source selection
     bit_offset: 16
@@ -3550,6 +3551,15 @@ enum/DFSDMSEL:
   - name: SYS
     description: System clock selected as peripheral clock
     value: 1
+enum/DSISEL:
+  bit_size: 1
+  variants:
+  - name: DSI_PHY
+    description: DSI-PHY used as DSI byte lane clock source (usual case)
+    value: 0
+  - name: PLL2_Q
+    description: PLL2_Q used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)
+    value: 1
 enum/FDCANSEL:
   bit_size: 2
   variants:

data/registers/rcc_h7ab.yaml

@@ -2018,10 +2018,6 @@ fieldset/D1CCIPR:
     bit_offset: 4
     bit_size: 2
     enum: FMCSEL
-  - name: DSISEL
-    description: kernel clock source selection
-    bit_offset: 8
-    bit_size: 1
   - name: SDMMCSEL
     description: SDMMC kernel clock source selection
     bit_offset: 16

data/registers/rcc_h7rm0433.yaml

@@ -3055,10 +3055,6 @@ fieldset/D1CCIPR:
     bit_offset: 4
     bit_size: 2
     enum: FMCSEL
-  - name: DSISEL
-    description: kernel clock source selection
-    bit_offset: 8
-    bit_size: 1
   - name: SDMMCSEL
     description: SDMMC kernel clock source selection
     bit_offset: 16

data/registers/rcc_l4plus.yaml

@@ -1713,7 +1713,7 @@ enum/DFSDMSEL:
 enum/DSISEL:
   bit_size: 1
   variants:
-  - name: DSIPHY
+  - name: DSI_PHY
     description: DSI-PHY is selected as DSI byte lane clock source (usual case)
     value: 0
   - name: PLLSAI2_Q

stm32-data-gen/src/chips.rs

@@ -269,6 +269,10 @@ impl PeriMatcher {
             (".*:WWDG:wwdg1_v2_0", ("wwdg", "v2", "WWDG")),
             (".*:JPEG:jpeg1_v1_0", ("jpeg", "v1", "JPEG")),
             (".*:LTDC:lcdtft1_v1_1", ("ltdc", "v1", "LTDC")),
+            (".*:DSIHOST:dsihost1_v1_0", ("dsihost", "v1", "DSIHOST")),
+            (".*:DSIHOST:dsihost1_v1_0_SHARK", ("dsihost", "v1", "DSIHOST")),
+            (".*:DSIHOST:dsihost1_v2_0", ("dsihost", "v2", "DSIHOST")),
+            (".*:DSIHOST:dsihost_U5", ("dsihost", "u5", "DSIHOST")),
             (".*:MDIOS:mdios1_v1_0", ("mdios", "v1", "MDIOS")),
             (".*:QUADSPI:.*", ("quadspi", "v1", "QUADSPI")),
             ("STM32F1.*:BKP.*", ("bkp", "v1", "BKP")),

stm32-data-gen/src/header.rs

@@ -190,6 +190,7 @@ impl Defines {
             ),
             ("FDCANRAM", &["SRAMCAN_BASE", "SRAMCAN_BASE_NS"]),
             ("VREFINTCAL", &["VREFINT_CAL_ADDR_CMSIS"]),
+            ("DSIHOST", &["DSI_BASE"]),
         ];
         let alt_peri_defines: HashMap<_, _> = ALT_PERI_DEFINES.iter().copied().collect();
 

stm32-data-gen/src/rcc.rs

@@ -106,10 +106,10 @@ impl ParsedRccs {
             "AUDIOCLK",
             "PER",
             "CLK48",
+            "DSI_PHY",
             // TODO: variants to cleanup
             "AFIF",
             "HSI_HSE",
-            "DSI_PHY",
             "HSI_Div488",
             "SAI1_EXTCLK",
             "SAI2_EXTCLK",
@@ -120,7 +120,6 @@ impl ParsedRccs {
             "DAC_HOLD_2",
             "RTCCLK",
             "RTC_WKUP",
-            "DSIPHY",
             "ICLK",
             "DCLK",
             "I2S1",
@@ -264,6 +263,7 @@ impl ParsedRccs {
             ("DAC", &["DAC1", "ADCDAC"]),
             ("DAC1", &["DAC12", "ADCDAC"]),
             ("DAC2", &["DAC12", "ADCDAC"]),
+            ("DSIHOST", &["DSI"]),
             ("ETH", &["ETHMAC", "ETH1MAC"]),
             ("SPI1", &["SPI12", "SPI123"]),
             ("SPI2", &["SPI12", "SPI123"]),