From 8ec40e422c9c4c952cbc9f2b52b25a67693d3fbe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=ABl=20Schulz-Ansres?= Date: Sun, 7 Apr 2024 13:01:34 +0200 Subject: [PATCH 1/6] Add DSIHOST support --- data/registers/dsihost_v1.yaml | 1741 ++++++++++++++++++++++++++++++++ data/registers/dsihost_v2.yaml | 1716 +++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 3 + stm32-data-gen/src/header.rs | 1 + 4 files changed, 3461 insertions(+) create mode 100644 data/registers/dsihost_v1.yaml create mode 100644 data/registers/dsihost_v2.yaml diff --git a/data/registers/dsihost_v1.yaml b/data/registers/dsihost_v1.yaml new file mode 100644 index 0000000..c1fc718 --- /dev/null +++ b/data/registers/dsihost_v1.yaml @@ -0,0 +1,1741 @@ +block/DSIHOST: + description: DSI Host. + items: + - name: VR + description: DSI Host Version Register. + byte_offset: 0 + access: Read + fieldset: VR + - name: CR + description: DSI Host Control Register. + byte_offset: 4 + fieldset: CR + - name: CCR + description: DSI HOST Clock Control Register. + byte_offset: 8 + fieldset: CCR + - name: LVCIDR + description: DSI Host LTDC VCID Register. + byte_offset: 12 + fieldset: LVCIDR + - name: LCOLCR + description: DSI Host LTDC Color Coding Register. + byte_offset: 16 + fieldset: LCOLCR + - name: LPCR + description: DSI Host LTDC Polarity Configuration Register. + byte_offset: 20 + fieldset: LPCR + - name: LPMCR + description: DSI Host Low-Power mode Configuration Register. + byte_offset: 24 + fieldset: LPMCR + - name: PCR + description: DSI Host Protocol Configuration Register. + byte_offset: 44 + fieldset: PCR + - name: GVCIDR + description: DSI Host Generic VCID Register. + byte_offset: 48 + fieldset: GVCIDR + - name: MCR + description: DSI Host mode Configuration Register. + byte_offset: 52 + fieldset: MCR + - name: VMCR + description: DSI Host Video mode Configuration Register. + byte_offset: 56 + fieldset: VMCR + - name: VPCR + description: DSI Host Video Packet Configuration Register. + byte_offset: 60 + fieldset: VPCR + - name: VCCR + description: DSI Host Video Chunks Configuration Register. + byte_offset: 64 + fieldset: VCCR + - name: VNPCR + description: DSI Host Video Null Packet Configuration Register. + byte_offset: 68 + fieldset: VNPCR + - name: VHSACR + description: DSI Host Video HSA Configuration Register. + byte_offset: 72 + fieldset: VHSACR + - name: VHBPCR + description: DSI Host Video HBP Configuration Register. + byte_offset: 76 + fieldset: VHBPCR + - name: VLCR + description: DSI Host Video Line Configuration Register. + byte_offset: 80 + fieldset: VLCR + - name: VVSACR + description: DSI Host Video VSA Configuration Register. + byte_offset: 84 + fieldset: VVSACR + - name: VVBPCR + description: DSI Host Video VBP Configuration Register. + byte_offset: 88 + fieldset: VVBPCR + - name: VVFPCR + description: DSI Host Video VFP Configuration Register. + byte_offset: 92 + fieldset: VVFPCR + - name: VVACR + description: DSI Host Video VA Configuration Register. + byte_offset: 96 + fieldset: VVACR + - name: LCCR + description: DSI Host LTDC Command Configuration Register. + byte_offset: 100 + fieldset: LCCR + - name: CMCR + description: DSI Host Command mode Configuration Register. + byte_offset: 104 + fieldset: CMCR + - name: GHCR + description: DSI Host Generic Header Configuration Register. + byte_offset: 108 + fieldset: GHCR + - name: GPDR + description: DSI Host Generic Payload Data Register. + byte_offset: 112 + fieldset: GPDR + - name: GPSR + description: DSI Host Generic Packet Status Register. + byte_offset: 116 + access: Read + fieldset: GPSR + - name: TCCR0 + description: DSI Host Timeout Counter Configuration Register 0. + byte_offset: 120 + fieldset: TCCR0 + - name: TCCR1 + description: DSI Host Timeout Counter Configuration Register 1. + byte_offset: 124 + fieldset: TCCR1 + - name: TCCR2 + description: DSI Host Timeout Counter Configuration Register 2. + byte_offset: 128 + fieldset: TCCR2 + - name: TCCR3 + description: DSI Host Timeout Counter Configuration Register 3. + byte_offset: 132 + fieldset: TCCR3 + - name: TCCR4 + description: DSI Host Timeout Counter Configuration Register 4. + byte_offset: 136 + fieldset: TCCR4 + - name: TCCR5 + description: DSI Host Timeout Counter Configuration Register 5. + byte_offset: 140 + fieldset: TCCR5 + - name: CLCR + description: DSI Host Clock Lane Configuration Register. + byte_offset: 148 + fieldset: CLCR + - name: CLTCR + description: DSI Host Clock Lane Timer Configuration Register. + byte_offset: 152 + fieldset: CLTCR + - name: DLTCR + description: DSI Host Data Lane Timer Configuration Register. + byte_offset: 156 + fieldset: DLTCR + - name: PCTLR + description: DSI Host PHY Control Register. + byte_offset: 160 + fieldset: PCTLR + - name: PCONFR + description: DSI Host PHY Configuration Register. + byte_offset: 164 + fieldset: PCONFR + - name: PUCR + description: DSI Host PHY ULPS Control Register. + byte_offset: 168 + fieldset: PUCR + - name: PTTCR + description: DSI Host PHY TX Triggers Configuration Register. + byte_offset: 172 + fieldset: PTTCR + - name: PSR + description: DSI Host PHY Status Register. + byte_offset: 176 + access: Read + fieldset: PSR + - name: ISR0 + description: DSI Host Interrupt & Status Register 0. + byte_offset: 188 + access: Read + fieldset: ISR0 + - name: ISR1 + description: DSI Host Interrupt & Status Register 1. + byte_offset: 192 + access: Read + fieldset: ISR1 + - name: IER0 + description: DSI Host Interrupt Enable Register 0. + byte_offset: 196 + fieldset: IER0 + - name: IER1 + description: DSI Host Interrupt Enable Register 1. + byte_offset: 200 + fieldset: IER1 + - name: FIR0 + description: DSI Host Force Interrupt Register 0. + byte_offset: 216 + access: Write + fieldset: FIR0 + - name: FIR1 + description: DSI Host Force Interrupt Register 1. + byte_offset: 220 + access: Write + fieldset: FIR1 + - name: VSCR + description: DSI Host Video Shadow Control Register. + byte_offset: 256 + fieldset: VSCR + - name: LCVCIDR + description: DSI Host LTDC Current VCID Register. + byte_offset: 268 + access: Read + fieldset: LCVCIDR + - name: LCCCR + description: DSI Host LTDC Current Color Coding Register. + byte_offset: 272 + access: Read + fieldset: LCCCR + - name: LPMCCR + description: DSI Host Low-Power mode Current Configuration Register. + byte_offset: 280 + access: Read + fieldset: LPMCCR + - name: VMCCR + description: DSI Host Video mode Current Configuration Register. + byte_offset: 312 + access: Read + fieldset: VMCCR + - name: VPCCR + description: DSI Host Video Packet Current Configuration Register. + byte_offset: 316 + access: Read + fieldset: VPCCR + - name: VCCCR + description: DSI Host Video Chunks Current Configuration Register. + byte_offset: 320 + access: Read + fieldset: VCCCR + - name: VNPCCR + description: DSI Host Video Null Packet Current Configuration Register. + byte_offset: 324 + access: Read + fieldset: VNPCCR + - name: VHSACCR + description: DSI Host Video HSA Current Configuration Register. + byte_offset: 328 + access: Read + fieldset: VHSACCR + - name: VHBPCCR + description: DSI Host Video HBP Current Configuration Register. + byte_offset: 332 + access: Read + fieldset: VHBPCCR + - name: VLCCR + description: DSI Host Video Line Current Configuration Register. + byte_offset: 336 + access: Read + fieldset: VLCCR + - name: VVSACCR + description: DSI Host Video VSA Current Configuration Register. + byte_offset: 340 + access: Read + fieldset: VVSACCR + - name: VVBPCCR + description: DSI Host Video VBP Current Configuration Register. + byte_offset: 344 + access: Read + fieldset: VVBPCCR + - name: VVFPCCR + description: DSI Host Video VFP Current Configuration Register. + byte_offset: 348 + access: Read + fieldset: VVFPCCR + - name: VVACCR + description: DSI Host Video VA Current Configuration Register. + byte_offset: 352 + access: Read + fieldset: VVACCR + - name: WCFGR + description: DSI Wrapper Configuration Register. + byte_offset: 1024 + fieldset: WCFGR + - name: WCR + description: DSI Wrapper Control Register. + byte_offset: 1028 + fieldset: WCR + - name: WIER + description: DSI Wrapper Interrupt Enable Register. + byte_offset: 1032 + fieldset: WIER + - name: WISR + description: DSI Wrapper Interrupt & Status Register. + byte_offset: 1036 + access: Read + fieldset: WISR + - name: WIFCR + description: DSI Wrapper Interrupt Flag Clear Register. + byte_offset: 1040 + fieldset: WIFCR + - name: WPCR0 + description: DSI Wrapper PHY Configuration Register 0. + byte_offset: 1048 + fieldset: WPCR0 + - name: WPCR1 + description: DSI Wrapper PHY Configuration Register 1. + byte_offset: 1052 + fieldset: WPCR1 + - name: WPCR2 + description: DSI Wrapper PHY Configuration Register 2. + byte_offset: 1056 + fieldset: WPCR2 + - name: WPCR3 + description: DSI Wrapper PHY Configuration Register 3. + byte_offset: 1060 + fieldset: WPCR3 + - name: WPCR4 + description: DSI Wrapper PHY Configuration Register 4. + byte_offset: 1064 + fieldset: WPCR4 + - name: WRPCR + description: DSI Wrapper Regulator and PLL Control Register. + byte_offset: 1072 + fieldset: WRPCR +fieldset/CCR: + description: DSI HOST Clock Control Register. + fields: + - name: TXECKDIV + description: TX Escape Clock Division. + bit_offset: 0 + bit_size: 8 + - name: TOCKDIV + description: Timeout Clock Division. + bit_offset: 8 + bit_size: 8 +fieldset/CLCR: + description: DSI Host Clock Lane Configuration Register. + fields: + - name: DPCC + description: D-PHY Clock Control. + bit_offset: 0 + bit_size: 1 + - name: ACR + description: Automatic Clock lane Control. + bit_offset: 1 + bit_size: 1 +fieldset/CLTCR: + description: DSI Host Clock Lane Timer Configuration Register. + fields: + - name: LP2HS_TIME + description: Low-Power to High-Speed Time. + bit_offset: 0 + bit_size: 10 + - name: HS2LP_TIME + description: High-Speed to Low-Power Time. + bit_offset: 16 + bit_size: 10 +fieldset/CMCR: + description: DSI Host Command mode Configuration Register. + fields: + - name: TEARE + description: Tearing Effect Acknowledge Request Enable. + bit_offset: 0 + bit_size: 1 + - name: ARE + description: Acknowledge Request Enable. + bit_offset: 1 + bit_size: 1 + - name: GSW0TX + description: Generic Short Write Zero parameters Transmission. + bit_offset: 8 + bit_size: 1 + - name: GSW1TX + description: Generic Short Write One parameters Transmission. + bit_offset: 9 + bit_size: 1 + - name: GSW2TX + description: Generic Short Write Two parameters Transmission. + bit_offset: 10 + bit_size: 1 + - name: GSR0TX + description: Generic Short Read Zero parameters Transmission. + bit_offset: 11 + bit_size: 1 + - name: GSR1TX + description: Generic Short Read One parameters Transmission. + bit_offset: 12 + bit_size: 1 + - name: GSR2TX + description: Generic Short Read Two parameters Transmission. + bit_offset: 13 + bit_size: 1 + - name: GLWTX + description: Generic Long Write Transmission. + bit_offset: 14 + bit_size: 1 + - name: DSW0TX + description: DCS Short Write Zero parameter Transmission. + bit_offset: 16 + bit_size: 1 + - name: DSW1TX + description: DCS Short Read One parameter Transmission. + bit_offset: 17 + bit_size: 1 + - name: DSR0TX + description: DCS Short Read Zero parameter Transmission. + bit_offset: 18 + bit_size: 1 + - name: DLWTX + description: DCS Long Write Transmission. + bit_offset: 19 + bit_size: 1 + - name: MRDPS + description: Maximum Read Packet Size. + bit_offset: 24 + bit_size: 1 +fieldset/CR: + description: DSI Host Control Register. + fields: + - name: EN + description: Enable. + bit_offset: 0 + bit_size: 1 +fieldset/DLTCR: + description: DSI Host Data Lane Timer Configuration Register. + fields: + - name: MRD_TIME + description: Maximum Read Time. + bit_offset: 0 + bit_size: 15 + - name: LP2HS_TIME + description: Low-Power To High-Speed Time. + bit_offset: 16 + bit_size: 8 + - name: HS2LP_TIME + description: High-Speed To Low-Power Time. + bit_offset: 24 + bit_size: 8 +fieldset/FIR0: + description: DSI Host Force Interrupt Register 0. + fields: + - name: FAE0 + description: Force Acknowledge Error 0. + bit_offset: 0 + bit_size: 1 + - name: FAE1 + description: Force Acknowledge Error 1. + bit_offset: 1 + bit_size: 1 + - name: FAE2 + description: Force Acknowledge Error 2. + bit_offset: 2 + bit_size: 1 + - name: FAE3 + description: Force Acknowledge Error 3. + bit_offset: 3 + bit_size: 1 + - name: FAE4 + description: Force Acknowledge Error 4. + bit_offset: 4 + bit_size: 1 + - name: FAE5 + description: Force Acknowledge Error 5. + bit_offset: 5 + bit_size: 1 + - name: FAE6 + description: Force Acknowledge Error 6. + bit_offset: 6 + bit_size: 1 + - name: FAE7 + description: Force Acknowledge Error 7. + bit_offset: 7 + bit_size: 1 + - name: FAE8 + description: Force Acknowledge Error 8. + bit_offset: 8 + bit_size: 1 + - name: FAE9 + description: Force Acknowledge Error 9. + bit_offset: 9 + bit_size: 1 + - name: FAE10 + description: Force Acknowledge Error 10. + bit_offset: 10 + bit_size: 1 + - name: FAE11 + description: Force Acknowledge Error 11. + bit_offset: 11 + bit_size: 1 + - name: FAE12 + description: Force Acknowledge Error 12. + bit_offset: 12 + bit_size: 1 + - name: FAE13 + description: Force Acknowledge Error 13. + bit_offset: 13 + bit_size: 1 + - name: FAE14 + description: Force Acknowledge Error 14. + bit_offset: 14 + bit_size: 1 + - name: FAE15 + description: Force Acknowledge Error 15. + bit_offset: 15 + bit_size: 1 + - name: FPE0 + description: Force PHY Error 0. + bit_offset: 16 + bit_size: 1 + - name: FPE1 + description: Force PHY Error 1. + bit_offset: 17 + bit_size: 1 + - name: FPE2 + description: Force PHY Error 2. + bit_offset: 18 + bit_size: 1 + - name: FPE3 + description: Force PHY Error 3. + bit_offset: 19 + bit_size: 1 + - name: FPE4 + description: Force PHY Error 4. + bit_offset: 20 + bit_size: 1 +fieldset/FIR1: + description: DSI Host Force Interrupt Register 1. + fields: + - name: FTOHSTX + description: Force Timeout High-Speed Transmission. + bit_offset: 0 + bit_size: 1 + - name: FTOLPRX + description: Force Timeout Low-Power Reception. + bit_offset: 1 + bit_size: 1 + - name: FECCSE + description: Force ECC Single-bit Error. + bit_offset: 2 + bit_size: 1 + - name: FECCME + description: Force ECC Multi-bit Error. + bit_offset: 3 + bit_size: 1 + - name: FCRCE + description: Force CRC Error. + bit_offset: 4 + bit_size: 1 + - name: FPSE + description: Force Packet Size Error. + bit_offset: 5 + bit_size: 1 + - name: FEOTPE + description: Force EoTp Error. + bit_offset: 6 + bit_size: 1 + - name: FLPWRE + description: Force LTDC Payload Write Error. + bit_offset: 7 + bit_size: 1 + - name: FGCWRE + description: Force Generic Command Write Error. + bit_offset: 8 + bit_size: 1 + - name: FGPWRE + description: Force Generic Payload Write Error. + bit_offset: 9 + bit_size: 1 + - name: FGPTXE + description: Force Generic Payload Transmit Error. + bit_offset: 10 + bit_size: 1 + - name: FGPRDE + description: Force Generic Payload Read Error. + bit_offset: 11 + bit_size: 1 + - name: FGPRXE + description: Force Generic Payload Receive Error. + bit_offset: 12 + bit_size: 1 +fieldset/GHCR: + description: DSI Host Generic Header Configuration Register. + fields: + - name: DT + description: Type. + bit_offset: 0 + bit_size: 6 + - name: VCID + description: Channel. + bit_offset: 6 + bit_size: 2 + - name: WCLSB + description: WordCount LSB. + bit_offset: 8 + bit_size: 8 + - name: WCMSB + description: WordCount MSB. + bit_offset: 16 + bit_size: 8 +fieldset/GPDR: + description: DSI Host Generic Payload Data Register. + fields: + - name: DATA1 + description: Payload Byte 1. + bit_offset: 0 + bit_size: 8 + - name: DATA2 + description: Payload Byte 2. + bit_offset: 8 + bit_size: 8 + - name: DATA3 + description: Payload Byte 3. + bit_offset: 16 + bit_size: 8 + - name: DATA4 + description: Payload Byte 4. + bit_offset: 24 + bit_size: 8 +fieldset/GPSR: + description: DSI Host Generic Packet Status Register. + fields: + - name: CMDFE + description: Command FIFO Empty. + bit_offset: 0 + bit_size: 1 + - name: CMDFF + description: Command FIFO Full. + bit_offset: 1 + bit_size: 1 + - name: PWRFE + description: Payload Write FIFO Empty. + bit_offset: 2 + bit_size: 1 + - name: PWRFF + description: Payload Write FIFO Full. + bit_offset: 3 + bit_size: 1 + - name: PRDFE + description: Payload Read FIFO Empty. + bit_offset: 4 + bit_size: 1 + - name: PRDFF + description: Payload Read FIFO Full. + bit_offset: 5 + bit_size: 1 + - name: RCB + description: Read Command Busy. + bit_offset: 6 + bit_size: 1 +fieldset/GVCIDR: + description: DSI Host Generic VCID Register. + fields: + - name: VCID + description: Virtual Channel ID. + bit_offset: 0 + bit_size: 2 +fieldset/IER0: + description: DSI Host Interrupt Enable Register 0. + fields: + - name: AE0IE + description: Acknowledge Error 0 Interrupt Enable. + bit_offset: 0 + bit_size: 1 + - name: AE1IE + description: Acknowledge Error 1 Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: AE2IE + description: Acknowledge Error 2 Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: AE3IE + description: Acknowledge Error 3 Interrupt Enable. + bit_offset: 3 + bit_size: 1 + - name: AE4IE + description: Acknowledge Error 4 Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: AE5IE + description: Acknowledge Error 5 Interrupt Enable. + bit_offset: 5 + bit_size: 1 + - name: AE6IE + description: Acknowledge Error 6 Interrupt Enable. + bit_offset: 6 + bit_size: 1 + - name: AE7IE + description: Acknowledge Error 7 Interrupt Enable. + bit_offset: 7 + bit_size: 1 + - name: AE8IE + description: Acknowledge Error 8 Interrupt Enable. + bit_offset: 8 + bit_size: 1 + - name: AE9IE + description: Acknowledge Error 9 Interrupt Enable. + bit_offset: 9 + bit_size: 1 + - name: AE10IE + description: Acknowledge Error 10 Interrupt Enable. + bit_offset: 10 + bit_size: 1 + - name: AE11IE + description: Acknowledge Error 11 Interrupt Enable. + bit_offset: 11 + bit_size: 1 + - name: AE12IE + description: Acknowledge Error 12 Interrupt Enable. + bit_offset: 12 + bit_size: 1 + - name: AE13IE + description: Acknowledge Error 13 Interrupt Enable. + bit_offset: 13 + bit_size: 1 + - name: AE14IE + description: Acknowledge Error 14 Interrupt Enable. + bit_offset: 14 + bit_size: 1 + - name: AE15IE + description: Acknowledge Error 15 Interrupt Enable. + bit_offset: 15 + bit_size: 1 + - name: PE0IE + description: PHY Error 0 Interrupt Enable. + bit_offset: 16 + bit_size: 1 + - name: PE1IE + description: PHY Error 1 Interrupt Enable. + bit_offset: 17 + bit_size: 1 + - name: PE2IE + description: PHY Error 2 Interrupt Enable. + bit_offset: 18 + bit_size: 1 + - name: PE3IE + description: PHY Error 3 Interrupt Enable. + bit_offset: 19 + bit_size: 1 + - name: PE4IE + description: PHY Error 4 Interrupt Enable. + bit_offset: 20 + bit_size: 1 +fieldset/IER1: + description: DSI Host Interrupt Enable Register 1. + fields: + - name: TOHSTXIE + description: Timeout High-Speed Transmission Interrupt Enable. + bit_offset: 0 + bit_size: 1 + - name: TOLPRXIE + description: Timeout Low-Power Reception Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: ECCSEIE + description: ECC Single-bit Error Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: ECCMEIE + description: ECC Multi-bit Error Interrupt Enable. + bit_offset: 3 + bit_size: 1 + - name: CRCEIE + description: CRC Error Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: PSEIE + description: Packet Size Error Interrupt Enable. + bit_offset: 5 + bit_size: 1 + - name: EOTPEIE + description: EoTp Error Interrupt Enable. + bit_offset: 6 + bit_size: 1 + - name: LPWREIE + description: LTDC Payload Write Error Interrupt Enable. + bit_offset: 7 + bit_size: 1 + - name: GCWREIE + description: Generic Command Write Error Interrupt Enable. + bit_offset: 8 + bit_size: 1 + - name: GPWREIE + description: Generic Payload Write Error Interrupt Enable. + bit_offset: 9 + bit_size: 1 + - name: GPTXEIE + description: Generic Payload Transmit Error Interrupt Enable. + bit_offset: 10 + bit_size: 1 + - name: GPRDEIE + description: Generic Payload Read Error Interrupt Enable. + bit_offset: 11 + bit_size: 1 + - name: GPRXEIE + description: Generic Payload Receive Error Interrupt Enable. + bit_offset: 12 + bit_size: 1 +fieldset/ISR0: + description: DSI Host Interrupt & Status Register 0. + fields: + - name: AE0 + description: Acknowledge Error 0. + bit_offset: 0 + bit_size: 1 + - name: AE1 + description: Acknowledge Error 1. + bit_offset: 1 + bit_size: 1 + - name: AE2 + description: Acknowledge Error 2. + bit_offset: 2 + bit_size: 1 + - name: AE3 + description: Acknowledge Error 3. + bit_offset: 3 + bit_size: 1 + - name: AE4 + description: Acknowledge Error 4. + bit_offset: 4 + bit_size: 1 + - name: AE5 + description: Acknowledge Error 5. + bit_offset: 5 + bit_size: 1 + - name: AE6 + description: Acknowledge Error 6. + bit_offset: 6 + bit_size: 1 + - name: AE7 + description: Acknowledge Error 7. + bit_offset: 7 + bit_size: 1 + - name: AE8 + description: Acknowledge Error 8. + bit_offset: 8 + bit_size: 1 + - name: AE9 + description: Acknowledge Error 9. + bit_offset: 9 + bit_size: 1 + - name: AE10 + description: Acknowledge Error 10. + bit_offset: 10 + bit_size: 1 + - name: AE11 + description: Acknowledge Error 11. + bit_offset: 11 + bit_size: 1 + - name: AE12 + description: Acknowledge Error 12. + bit_offset: 12 + bit_size: 1 + - name: AE13 + description: Acknowledge Error 13. + bit_offset: 13 + bit_size: 1 + - name: AE14 + description: Acknowledge Error 14. + bit_offset: 14 + bit_size: 1 + - name: AE15 + description: Acknowledge Error 15. + bit_offset: 15 + bit_size: 1 + - name: PE0 + description: PHY Error 0. + bit_offset: 16 + bit_size: 1 + - name: PE1 + description: PHY Error 1. + bit_offset: 17 + bit_size: 1 + - name: PE2 + description: PHY Error 2. + bit_offset: 18 + bit_size: 1 + - name: PE3 + description: PHY Error 3. + bit_offset: 19 + bit_size: 1 + - name: PE4 + description: PHY Error 4. + bit_offset: 20 + bit_size: 1 +fieldset/ISR1: + description: DSI Host Interrupt & Status Register 1. + fields: + - name: TOHSTX + description: Timeout High-Speed Transmission. + bit_offset: 0 + bit_size: 1 + - name: TOLPRX + description: Timeout Low-Power Reception. + bit_offset: 1 + bit_size: 1 + - name: ECCSE + description: ECC Single-bit Error. + bit_offset: 2 + bit_size: 1 + - name: ECCME + description: ECC Multi-bit Error. + bit_offset: 3 + bit_size: 1 + - name: CRCE + description: CRC Error. + bit_offset: 4 + bit_size: 1 + - name: PSE + description: Packet Size Error. + bit_offset: 5 + bit_size: 1 + - name: EOTPE + description: EoTp Error. + bit_offset: 6 + bit_size: 1 + - name: LPWRE + description: LTDC Payload Write Error. + bit_offset: 7 + bit_size: 1 + - name: GCWRE + description: Generic Command Write Error. + bit_offset: 8 + bit_size: 1 + - name: GPWRE + description: Generic Payload Write Error. + bit_offset: 9 + bit_size: 1 + - name: GPTXE + description: Generic Payload Transmit Error. + bit_offset: 10 + bit_size: 1 + - name: GPRDE + description: Generic Payload Read Error. + bit_offset: 11 + bit_size: 1 + - name: GPRXE + description: Generic Payload Receive Error. + bit_offset: 12 + bit_size: 1 +fieldset/LCCCR: + description: DSI Host LTDC Current Color Coding Register. + fields: + - name: COLC + description: Color Coding. + bit_offset: 0 + bit_size: 4 + - name: LPE + description: Loosely Packed Enable. + bit_offset: 8 + bit_size: 1 +fieldset/LCCR: + description: DSI Host LTDC Command Configuration Register. + fields: + - name: CMDSIZE + description: Command Size. + bit_offset: 0 + bit_size: 16 +fieldset/LCOLCR: + description: DSI Host LTDC Color Coding Register. + fields: + - name: COLC + description: Color Coding. + bit_offset: 0 + bit_size: 4 + - name: LPE + description: Loosely Packet Enable. + bit_offset: 8 + bit_size: 1 +fieldset/LCVCIDR: + description: DSI Host LTDC Current VCID Register. + fields: + - name: VCID + description: Virtual Channel ID. + bit_offset: 0 + bit_size: 2 +fieldset/LPCR: + description: DSI Host LTDC Polarity Configuration Register. + fields: + - name: DEP + description: Data Enable Polarity. + bit_offset: 0 + bit_size: 1 + - name: VSP + description: VSYNC Polarity. + bit_offset: 1 + bit_size: 1 + - name: HSP + description: HSYNC Polarity. + bit_offset: 2 + bit_size: 1 +fieldset/LPMCCR: + description: DSI Host Low-Power mode Current Configuration Register. + fields: + - name: VLPSIZE + description: VACT Largest Packet Size. + bit_offset: 0 + bit_size: 8 + - name: LPSIZE + description: Largest Packet Size. + bit_offset: 16 + bit_size: 8 +fieldset/LPMCR: + description: DSI Host Low-Power mode Configuration Register. + fields: + - name: VLPSIZE + description: VACT Largest Packet Size. + bit_offset: 0 + bit_size: 8 + - name: LPSIZE + description: Largest Packet Size. + bit_offset: 16 + bit_size: 8 +fieldset/LVCIDR: + description: DSI Host LTDC VCID Register. + fields: + - name: VCID + description: Virtual Channel ID. + bit_offset: 0 + bit_size: 2 +fieldset/MCR: + description: DSI Host mode Configuration Register. + fields: + - name: CMDM + description: Command mode. + bit_offset: 0 + bit_size: 1 +fieldset/PCONFR: + description: DSI Host PHY Configuration Register. + fields: + - name: NL + description: Number of Lanes. + bit_offset: 0 + bit_size: 2 + - name: SW_TIME + description: Stop Wait Time. + bit_offset: 8 + bit_size: 8 +fieldset/PCR: + description: DSI Host Protocol Configuration Register. + fields: + - name: ETTXE + description: EoTp Transmission Enable. + bit_offset: 0 + bit_size: 1 + - name: ETRXE + description: EoTp Reception Enable. + bit_offset: 1 + bit_size: 1 + - name: BTAE + description: Bus Turn Around Enable. + bit_offset: 2 + bit_size: 1 + - name: ECCRXE + description: ECC Reception Enable. + bit_offset: 3 + bit_size: 1 + - name: CRCRXE + description: CRC Reception Enable. + bit_offset: 4 + bit_size: 1 +fieldset/PCTLR: + description: DSI Host PHY Control Register. + fields: + - name: DEN + description: Digital Enable. + bit_offset: 1 + bit_size: 1 + - name: CKE + description: Clock Enable. + bit_offset: 2 + bit_size: 1 +fieldset/PSR: + description: DSI Host PHY Status Register. + fields: + - name: PD + description: PHY Direction. + bit_offset: 1 + bit_size: 1 + - name: PSSC + description: PHY Stop State Clock lane. + bit_offset: 2 + bit_size: 1 + - name: UANC + description: ULPS Active Not Clock lane. + bit_offset: 3 + bit_size: 1 + - name: PSS0 + description: PHY Stop State lane 0. + bit_offset: 4 + bit_size: 1 + - name: UAN0 + description: ULPS Active Not lane 1. + bit_offset: 5 + bit_size: 1 + - name: RUE0 + description: RX ULPS Escape lane 0. + bit_offset: 6 + bit_size: 1 + - name: PSS1 + description: PHY Stop State lane 1. + bit_offset: 7 + bit_size: 1 + - name: UAN1 + description: ULPS Active Not lane 1. + bit_offset: 8 + bit_size: 1 +fieldset/PTTCR: + description: DSI Host PHY TX Triggers Configuration Register. + fields: + - name: TX_TRIG + description: Transmission Trigger. + bit_offset: 0 + bit_size: 4 +fieldset/PUCR: + description: DSI Host PHY ULPS Control Register. + fields: + - name: URCL + description: ULPS Request on Clock Lane. + bit_offset: 0 + bit_size: 1 + - name: UECL + description: ULPS Exit on Clock Lane. + bit_offset: 1 + bit_size: 1 + - name: URDL + description: ULPS Request on Data Lane. + bit_offset: 2 + bit_size: 1 + - name: UEDL + description: ULPS Exit on Data Lane. + bit_offset: 3 + bit_size: 1 +fieldset/TCCR0: + description: DSI Host Timeout Counter Configuration Register 0. + fields: + - name: LPRX_TOCNT + description: Low-power Reception Timeout Counter. + bit_offset: 0 + bit_size: 16 + - name: HSTX_TOCNT + description: High-Speed Transmission Timeout Counter. + bit_offset: 16 + bit_size: 16 +fieldset/TCCR1: + description: DSI Host Timeout Counter Configuration Register 1. + fields: + - name: HSRD_TOCNT + description: High-Speed Read Timeout Counter. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR2: + description: DSI Host Timeout Counter Configuration Register 2. + fields: + - name: LPRD_TOCNT + description: Low-Power Read Timeout Counter. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR3: + description: DSI Host Timeout Counter Configuration Register 3. + fields: + - name: HSWR_TOCNT + description: High-Speed Write Timeout Counter. + bit_offset: 0 + bit_size: 16 + - name: PM + description: Presp mode. + bit_offset: 24 + bit_size: 1 +fieldset/TCCR4: + description: DSI Host Timeout Counter Configuration Register 4. + fields: + - name: LSWR_TOCNT + description: Low-Power Write Timeout Counter. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR5: + description: DSI Host Timeout Counter Configuration Register 5. + fields: + - name: BTA_TOCNT + description: Bus-Turn-Around Timeout Counter. + bit_offset: 0 + bit_size: 16 +fieldset/VCCCR: + description: DSI Host Video Chunks Current Configuration Register. + fields: + - name: NUMC + description: Number of Chunks. + bit_offset: 0 + bit_size: 13 +fieldset/VCCR: + description: DSI Host Video Chunks Configuration Register. + fields: + - name: NUMC + description: Number of Chunks. + bit_offset: 0 + bit_size: 13 +fieldset/VHBPCCR: + description: DSI Host Video HBP Current Configuration Register. + fields: + - name: HBP + description: Horizontal Back-Porch duration. + bit_offset: 0 + bit_size: 12 +fieldset/VHBPCR: + description: DSI Host Video HBP Configuration Register. + fields: + - name: HBP + description: Horizontal Back-Porch duration. + bit_offset: 0 + bit_size: 12 +fieldset/VHSACCR: + description: DSI Host Video HSA Current Configuration Register. + fields: + - name: HSA + description: Horizontal Synchronism Active duration. + bit_offset: 0 + bit_size: 12 +fieldset/VHSACR: + description: DSI Host Video HSA Configuration Register. + fields: + - name: HSA + description: Horizontal Synchronism Active duration. + bit_offset: 0 + bit_size: 12 +fieldset/VLCCR: + description: DSI Host Video Line Current Configuration Register. + fields: + - name: HLINE + description: Horizontal Line duration. + bit_offset: 0 + bit_size: 15 +fieldset/VLCR: + description: DSI Host Video Line Configuration Register. + fields: + - name: HLINE + description: Horizontal Line duration. + bit_offset: 0 + bit_size: 15 +fieldset/VMCCR: + description: DSI Host Video mode Current Configuration Register. + fields: + - name: VMT + description: Video mode Type. + bit_offset: 0 + bit_size: 2 + - name: LPVSAE + description: Low-Power Vertical Sync time Enable. + bit_offset: 2 + bit_size: 1 + - name: LPVBPE + description: Low-power Vertical Back-Porch Enable. + bit_offset: 3 + bit_size: 1 + - name: LPVFPE + description: Low-power Vertical Front-Porch Enable. + bit_offset: 4 + bit_size: 1 + - name: LPVAE + description: Low-Power Vertical Active Enable. + bit_offset: 5 + bit_size: 1 + - name: LPHBPE + description: Low-power Horizontal Back-Porch Enable. + bit_offset: 6 + bit_size: 1 + - name: LPHFE + description: Low-Power Horizontal Front-Porch Enable. + bit_offset: 7 + bit_size: 1 + - name: FBTAAE + description: Frame BTA Acknowledge Enable. + bit_offset: 8 + bit_size: 1 + - name: LPCE + description: Low-Power Command Enable. + bit_offset: 9 + bit_size: 1 +fieldset/VMCR: + description: DSI Host Video mode Configuration Register. + fields: + - name: VMT + description: Video mode Type. + bit_offset: 0 + bit_size: 2 + - name: LPVSAE + description: Low-Power Vertical Sync Active Enable. + bit_offset: 8 + bit_size: 1 + - name: LPVBPE + description: Low-power Vertical Back-Porch Enable. + bit_offset: 9 + bit_size: 1 + - name: LPVFPE + description: Low-power Vertical Front-porch Enable. + bit_offset: 10 + bit_size: 1 + - name: LPVAE + description: Low-Power Vertical Active Enable. + bit_offset: 11 + bit_size: 1 + - name: LPHBPE + description: Low-Power Horizontal Back-Porch Enable. + bit_offset: 12 + bit_size: 1 + - name: LPHFPE + description: Low-Power Horizontal Front-Porch Enable. + bit_offset: 13 + bit_size: 1 + - name: FBTAAE + description: Frame Bus-Turn-Around Acknowledge Enable. + bit_offset: 14 + bit_size: 1 + - name: LPCE + description: Low-Power Command Enable. + bit_offset: 15 + bit_size: 1 + - name: PGE + description: Pattern Generator Enable. + bit_offset: 16 + bit_size: 1 + - name: PGM + description: Pattern Generator mode. + bit_offset: 20 + bit_size: 1 + - name: PGO + description: Pattern Generator Orientation. + bit_offset: 24 + bit_size: 1 +fieldset/VNPCCR: + description: DSI Host Video Null Packet Current Configuration Register. + fields: + - name: NPSIZE + description: Null Packet Size. + bit_offset: 0 + bit_size: 13 +fieldset/VNPCR: + description: DSI Host Video Null Packet Configuration Register. + fields: + - name: NPSIZE + description: Null Packet Size. + bit_offset: 0 + bit_size: 13 +fieldset/VPCCR: + description: DSI Host Video Packet Current Configuration Register. + fields: + - name: VPSIZE + description: Video Packet Size. + bit_offset: 0 + bit_size: 14 +fieldset/VPCR: + description: DSI Host Video Packet Configuration Register. + fields: + - name: VPSIZE + description: Video Packet Size. + bit_offset: 0 + bit_size: 14 +fieldset/VR: + description: DSI Host Version Register. + fields: + - name: VERSION + description: Version of the DSI Host. + bit_offset: 0 + bit_size: 32 +fieldset/VSCR: + description: DSI Host Video Shadow Control Register. + fields: + - name: EN + description: Enable. + bit_offset: 0 + bit_size: 1 + - name: UR + description: Update Register. + bit_offset: 8 + bit_size: 1 +fieldset/VVACCR: + description: DSI Host Video VA Current Configuration Register. + fields: + - name: VA + description: Vertical Active duration. + bit_offset: 0 + bit_size: 14 +fieldset/VVACR: + description: DSI Host Video VA Configuration Register. + fields: + - name: VA + description: Vertical Active duration. + bit_offset: 0 + bit_size: 14 +fieldset/VVBPCCR: + description: DSI Host Video VBP Current Configuration Register. + fields: + - name: VBP + description: Vertical Back-Porch duration. + bit_offset: 0 + bit_size: 10 +fieldset/VVBPCR: + description: DSI Host Video VBP Configuration Register. + fields: + - name: VBP + description: Vertical Back-Porch duration. + bit_offset: 0 + bit_size: 10 +fieldset/VVFPCCR: + description: DSI Host Video VFP Current Configuration Register. + fields: + - name: VFP + description: Vertical Front-Porch duration. + bit_offset: 0 + bit_size: 10 +fieldset/VVFPCR: + description: DSI Host Video VFP Configuration Register. + fields: + - name: VFP + description: Vertical Front-Porch duration. + bit_offset: 0 + bit_size: 10 +fieldset/VVSACCR: + description: DSI Host Video VSA Current Configuration Register. + fields: + - name: VSA + description: Vertical Synchronism Active duration. + bit_offset: 0 + bit_size: 10 +fieldset/VVSACR: + description: DSI Host Video VSA Configuration Register. + fields: + - name: VSA + description: Vertical Synchronism Active duration. + bit_offset: 0 + bit_size: 10 +fieldset/WCFGR: + description: DSI Wrapper Configuration Register. + fields: + - name: DSIM + description: DSI Mode. + bit_offset: 0 + bit_size: 1 + - name: COLMUX + description: Color Multiplexing. + bit_offset: 1 + bit_size: 3 + - name: TESRC + description: TE Source. + bit_offset: 4 + bit_size: 1 + - name: TEPOL + description: TE Polarity. + bit_offset: 5 + bit_size: 1 + - name: AR + description: Automatic Refresh. + bit_offset: 6 + bit_size: 1 + - name: VSPOL + description: VSync Polarity. + bit_offset: 7 + bit_size: 1 +fieldset/WCR: + description: DSI Wrapper Control Register. + fields: + - name: COLM + description: Color Mode. + bit_offset: 0 + bit_size: 1 + - name: SHTDN + description: Shutdown. + bit_offset: 1 + bit_size: 1 + - name: LTDCEN + description: LTDC Enable. + bit_offset: 2 + bit_size: 1 + - name: DSIEN + description: DSI Enable. + bit_offset: 3 + bit_size: 1 +fieldset/WIER: + description: DSI Wrapper Interrupt Enable Register. + fields: + - name: TEIE + description: Tearing Effect Interrupt Enable. + bit_offset: 0 + bit_size: 1 + - name: ERIE + description: End of Refresh Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: PLLLIE + description: PLL Lock Interrupt Enable. + bit_offset: 9 + bit_size: 1 + - name: PLLUIE + description: PLL Unlock Interrupt Enable. + bit_offset: 10 + bit_size: 1 + - name: RRIE + description: Regulator Ready Interrupt Enable. + bit_offset: 13 + bit_size: 1 +fieldset/WIFCR: + description: DSI Wrapper Interrupt Flag Clear Register. + fields: + - name: CTEIF + description: Clear Tearing Effect Interrupt Flag. + bit_offset: 0 + bit_size: 1 + - name: CERIF + description: Clear End of Refresh Interrupt Flag. + bit_offset: 1 + bit_size: 1 + - name: CPLLLIF + description: Clear PLL Lock Interrupt Flag. + bit_offset: 9 + bit_size: 1 + - name: CPLLUIF + description: Clear PLL Unlock Interrupt Flag. + bit_offset: 10 + bit_size: 1 + - name: CRRIF + description: Clear Regulator Ready Interrupt Flag. + bit_offset: 13 + bit_size: 1 +fieldset/WISR: + description: DSI Wrapper Interrupt & Status Register. + fields: + - name: TEIF + description: Tearing Effect Interrupt Flag. + bit_offset: 0 + bit_size: 1 + - name: ERIF + description: End of Refresh Interrupt Flag. + bit_offset: 1 + bit_size: 1 + - name: BUSY + description: Busy Flag. + bit_offset: 2 + bit_size: 1 + - name: PLLLS + description: PLL Lock Status. + bit_offset: 8 + bit_size: 1 + - name: PLLLIF + description: PLL Lock Interrupt Flag. + bit_offset: 9 + bit_size: 1 + - name: PLLUIF + description: PLL Unlock Interrupt Flag. + bit_offset: 10 + bit_size: 1 + - name: RRS + description: Regulator Ready Status. + bit_offset: 12 + bit_size: 1 + - name: RRIF + description: Regulator Ready Interrupt Flag. + bit_offset: 13 + bit_size: 1 +fieldset/WPCR0: + description: DSI Wrapper PHY Configuration Register 0. + fields: + - name: UIX4 + description: Unit Interval multiplied by 4. + bit_offset: 0 + bit_size: 6 + - name: SWCL + description: Swap Clock Lane pins. + bit_offset: 6 + bit_size: 1 + - name: SWDL0 + description: Swap Data Lane 0 pins. + bit_offset: 7 + bit_size: 1 + - name: SWDL1 + description: Swap Data Lane 1 pins. + bit_offset: 8 + bit_size: 1 + - name: HSICL + description: Invert Hight-Speed data signal on Clock Lane. + bit_offset: 9 + bit_size: 1 + - name: HSIDL0 + description: Invert the Hight-Speed data signal on Data Lane 0. + bit_offset: 10 + bit_size: 1 + - name: HSIDL1 + description: Invert the High-Speed data signal on Data Lane 1. + bit_offset: 11 + bit_size: 1 + - name: FTXSMCL + description: Force in TX Stop Mode the Clock Lane. + bit_offset: 12 + bit_size: 1 + - name: FTXSMDL + description: Force in TX Stop Mode the Data Lanes. + bit_offset: 13 + bit_size: 1 + - name: CDOFFDL + description: Contention Detection OFF on Data Lanes. + bit_offset: 14 + bit_size: 1 + - name: TDDL + description: Turn Disable Data Lanes. + bit_offset: 16 + bit_size: 1 + - name: PDEN + description: Pull-Down Enable. + bit_offset: 18 + bit_size: 1 + - name: TCLKPREPEN + description: custom time for tCLK-PREPARE Enable. + bit_offset: 19 + bit_size: 1 + - name: TCLKZEROEN + description: custom time for tCLK-ZERO Enable. + bit_offset: 20 + bit_size: 1 + - name: THSPREPEN + description: custom time for tHS-PREPARE Enable. + bit_offset: 21 + bit_size: 1 + - name: THSTRAILEN + description: custom time for tHS-TRAIL Enable. + bit_offset: 22 + bit_size: 1 + - name: THSZEROEN + description: custom time for tHS-ZERO Enable. + bit_offset: 23 + bit_size: 1 + - name: TLPXDEN + description: custom time for tLPX for Data lanes Enable. + bit_offset: 24 + bit_size: 1 + - name: THSEXITEN + description: custom time for tHS-EXIT Enable. + bit_offset: 25 + bit_size: 1 + - name: TLPXCEN + description: custom time for tLPX for Clock lane Enable. + bit_offset: 26 + bit_size: 1 + - name: TCLKPOSTEN + description: custom time for tCLK-POST Enable. + bit_offset: 27 + bit_size: 1 +fieldset/WPCR1: + description: DSI Wrapper PHY Configuration Register 1. + fields: + - name: HSTXDCL + description: High-Speed Transmission Delay on Clock Lane. + bit_offset: 0 + bit_size: 2 + - name: HSTXDLL + description: High-Speed Transmission Delay on Data Lanes. + bit_offset: 2 + bit_size: 2 + - name: LPSRCL + description: Low-Power transmission Slew Rate Compensation on Clock Lane. + bit_offset: 6 + bit_size: 2 + - name: LPSRDL + description: Low-Power transmission Slew Rate Compensation on Data Lanes. + bit_offset: 8 + bit_size: 2 + - name: SDCC + description: SDD Control. + bit_offset: 12 + bit_size: 1 + - name: HSTXSRCCL + description: High-Speed Transmission Slew Rate Control on Clock Lane. + bit_offset: 16 + bit_size: 2 + - name: HSTXSRCDL + description: High-Speed Transmission Slew Rate Control on Data Lanes. + bit_offset: 18 + bit_size: 2 + - name: FLPRXLPM + description: Forces LP Receiver in Low-Power Mode. + bit_offset: 22 + bit_size: 1 + - name: LPRXFT + description: Low-Power RX low-pass Filtering Tuning. + bit_offset: 25 + bit_size: 2 +fieldset/WPCR2: + description: DSI Wrapper PHY Configuration Register 2. + fields: + - name: TCLKPREP + description: tCLK-PREPARE. + bit_offset: 0 + bit_size: 8 + - name: TCLKZEO + description: tCLK-ZERO. + bit_offset: 8 + bit_size: 8 + - name: THSPREP + description: tHS-PREPARE. + bit_offset: 16 + bit_size: 8 + - name: THSTRAIL + description: tHSTRAIL. + bit_offset: 24 + bit_size: 8 +fieldset/WPCR3: + description: DSI Wrapper PHY Configuration Register 3. + fields: + - name: THSZERO + description: tHS-ZERO. + bit_offset: 0 + bit_size: 8 + - name: TLPXD + description: tLPX for Data lanes. + bit_offset: 8 + bit_size: 8 + - name: THSEXIT + description: tHSEXIT. + bit_offset: 16 + bit_size: 8 + - name: TLPXC + description: tLPXC for Clock lane. + bit_offset: 24 + bit_size: 8 +fieldset/WPCR4: + description: DSI Wrapper PHY Configuration Register 4. + fields: + - name: TCLKPOST + description: tCLK-POST. + bit_offset: 0 + bit_size: 8 +fieldset/WRPCR: + description: DSI Wrapper Regulator and PLL Control Register. + fields: + - name: PLLEN + description: PLL Enable. + bit_offset: 0 + bit_size: 1 + - name: NDIV + description: PLL Loop Division Factor. + bit_offset: 2 + bit_size: 7 + - name: IDF + description: PLL Input Division Factor. + bit_offset: 11 + bit_size: 4 + - name: ODF + description: PLL Output Division Factor. + bit_offset: 16 + bit_size: 2 + - name: REGEN + description: Regulator Enable. + bit_offset: 24 + bit_size: 1 diff --git a/data/registers/dsihost_v2.yaml b/data/registers/dsihost_v2.yaml new file mode 100644 index 0000000..0b564ac --- /dev/null +++ b/data/registers/dsihost_v2.yaml @@ -0,0 +1,1716 @@ +block/DSIHOST: + description: DSIHOST1. + items: + - name: VR + description: DSI Host version register. + byte_offset: 0 + access: Read + fieldset: VR + - name: CR + description: DSI Host control register. + byte_offset: 4 + fieldset: CR + - name: CCR + description: DSI Host clock control register. + byte_offset: 8 + fieldset: CCR + - name: LVCIDR + description: DSI Host LTDC VCID register. + byte_offset: 12 + fieldset: LVCIDR + - name: LCOLCR + description: DSI Host LTDC color coding register. + byte_offset: 16 + fieldset: LCOLCR + - name: LPCR + description: DSI Host LTDC polarity configuration register. + byte_offset: 20 + fieldset: LPCR + - name: LPMCR + description: DSI Host low-power mode configuration register. + byte_offset: 24 + fieldset: LPMCR + - name: PCR + description: DSI Host protocol configuration register. + byte_offset: 44 + fieldset: PCR + - name: GVCIDR + description: DSI Host generic VCID register. + byte_offset: 48 + access: Read + fieldset: GVCIDR + - name: MCR + description: DSI Host mode configuration register. + byte_offset: 52 + fieldset: MCR + - name: VMCR + description: DSI Host video mode configuration register. + byte_offset: 56 + fieldset: VMCR + - name: VPCR + description: DSI Host video packet configuration register. + byte_offset: 60 + fieldset: VPCR + - name: VCCR + description: DSI Host video chunks configuration register. + byte_offset: 64 + fieldset: VCCR + - name: VNPCR + description: DSI Host video null packet configuration register. + byte_offset: 68 + fieldset: VNPCR + - name: VHSACR + description: DSI Host video HSA configuration register. + byte_offset: 72 + fieldset: VHSACR + - name: VHBPCR + description: DSI Host video HBP configuration register. + byte_offset: 76 + fieldset: VHBPCR + - name: VLCR + description: DSI Host video line configuration register. + byte_offset: 80 + fieldset: VLCR + - name: VVSACR + description: DSI Host video VSA configuration register. + byte_offset: 84 + fieldset: VVSACR + - name: VVBPCR + description: DSI Host video VBP configuration register. + byte_offset: 88 + fieldset: VVBPCR + - name: VVFPCR + description: DSI Host video VFP configuration register. + byte_offset: 92 + fieldset: VVFPCR + - name: VVACR + description: DSI Host video VA configuration register. + byte_offset: 96 + fieldset: VVACR + - name: LCCR + description: DSI Host LTDC command configuration register. + byte_offset: 100 + fieldset: LCCR + - name: CMCR + description: DSI Host command mode configuration register. + byte_offset: 104 + fieldset: CMCR + - name: GHCR + description: DSI Host generic header configuration register. + byte_offset: 108 + fieldset: GHCR + - name: GPDR + description: DSI Host generic payload data register. + byte_offset: 112 + fieldset: GPDR + - name: GPSR + description: DSI Host generic packet status register. + byte_offset: 116 + access: Read + fieldset: GPSR + - name: TCCR0 + description: DSI Host timeout counter configuration register 0. + byte_offset: 120 + fieldset: TCCR0 + - name: TCCR1 + description: DSI Host timeout counter configuration register 1. + byte_offset: 124 + fieldset: TCCR1 + - name: TCCR2 + description: DSI Host timeout counter configuration register 2. + byte_offset: 128 + fieldset: TCCR2 + - name: TCCR3 + description: DSI Host timeout counter configuration register 3. + byte_offset: 132 + fieldset: TCCR3 + - name: TCCR4 + description: DSI Host timeout counter configuration register 4. + byte_offset: 136 + fieldset: TCCR4 + - name: TCCR5 + description: DSI Host timeout counter configuration register 5. + byte_offset: 140 + fieldset: TCCR5 + - name: CLCR + description: DSI Host clock lane configuration register. + byte_offset: 148 + fieldset: CLCR + - name: CLTCR + description: DSI Host clock lane timer configuration register. + byte_offset: 152 + fieldset: CLTCR + - name: DLTCR + description: DSI Host data lane timer configuration register. + byte_offset: 156 + fieldset: DLTCR + - name: PCTLR + description: DSI Host PHY control register. + byte_offset: 160 + fieldset: PCTLR + - name: PCONFR + description: DSI Host PHY configuration register. + byte_offset: 164 + fieldset: PCONFR + - name: PUCR + description: DSI Host PHY ULPS control register. + byte_offset: 168 + fieldset: PUCR + - name: PTTCR + description: DSI Host PHY TX triggers configuration register. + byte_offset: 172 + fieldset: PTTCR + - name: PSR + description: DSI Host PHY status register. + byte_offset: 176 + access: Read + fieldset: PSR + - name: ISR0 + description: DSI Host interrupt and status register 0. + byte_offset: 188 + access: Read + fieldset: ISR0 + - name: ISR1 + description: DSI Host interrupt and status register 1. + byte_offset: 192 + access: Read + fieldset: ISR1 + - name: IER0 + description: DSI Host interrupt enable register 0. + byte_offset: 196 + fieldset: IER0 + - name: IER1 + description: DSI Host interrupt enable register 1. + byte_offset: 200 + fieldset: IER1 + - name: FIR0 + description: DSI Host force interrupt register 0. + byte_offset: 216 + access: Write + fieldset: FIR0 + - name: FIR1 + description: DSI Host force interrupt register 1. + byte_offset: 220 + access: Write + fieldset: FIR1 + - name: DLTRCR + description: DSI Host data lane timer read configuration register. + byte_offset: 244 + fieldset: DLTRCR + - name: VSCR + description: DSI Host video shadow control register. + byte_offset: 256 + fieldset: VSCR + - name: LCVCIDR + description: DSI Host LTDC current VCID register. + byte_offset: 268 + fieldset: LCVCIDR + - name: LCCCR + description: DSI Host LTDC current color coding register. + byte_offset: 272 + access: Read + fieldset: LCCCR + - name: LPMCCR + description: DSI Host low-power mode current configuration register. + byte_offset: 280 + access: Read + fieldset: LPMCCR + - name: VMCCR + description: DSI Host video mode current configuration register. + byte_offset: 312 + access: Read + fieldset: VMCCR + - name: VPCCR + description: DSI Host video packet current configuration register. + byte_offset: 316 + access: Read + fieldset: VPCCR + - name: VCCCR + description: DSI Host video chunks current configuration register. + byte_offset: 320 + access: Read + fieldset: VCCCR + - name: VNPCCR + description: DSI Host video null packet current configuration register. + byte_offset: 324 + access: Read + fieldset: VNPCCR + - name: VHSACCR + description: DSI Host video HSA current configuration register. + byte_offset: 328 + access: Read + fieldset: VHSACCR + - name: VHBPCCR + description: DSI Host video HBP current configuration register. + byte_offset: 332 + access: Read + fieldset: VHBPCCR + - name: VLCCR + description: DSI Host video line current configuration register. + byte_offset: 336 + access: Read + fieldset: VLCCR + - name: VVSACCR + description: DSI Host video VSA current configuration register. + byte_offset: 340 + access: Read + fieldset: VVSACCR + - name: VVBPCCR + description: DSI Host video VBP current configuration register. + byte_offset: 344 + access: Read + fieldset: VVBPCCR + - name: VVFPCCR + description: DSI Host video VFP current configuration register. + byte_offset: 348 + access: Read + fieldset: VVFPCCR + - name: VVACCR + description: DSI Host video VA current configuration register. + byte_offset: 352 + access: Read + fieldset: VVACCR + - name: WCFGR + description: DSI wrapper configuration register. + byte_offset: 1024 + fieldset: WCFGR + - name: WCR + description: DSI wrapper control register. + byte_offset: 1028 + fieldset: WCR + - name: WIER + description: DSI wrapper interrupt enable register. + byte_offset: 1032 + fieldset: WIER + - name: WISR + description: DSI wrapper interrupt and status register. + byte_offset: 1036 + access: Read + fieldset: WISR + - name: WIFCR + description: DSI wrapper interrupt flag clear register. + byte_offset: 1040 + access: Write + fieldset: WIFCR + - name: WPCR0 + description: DSI wrapper PHY configuration register 0. + byte_offset: 1048 + fieldset: WPCR0 + - name: WPCR1 + description: This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0). + byte_offset: 1052 + fieldset: WPCR1 + - name: WRPCR + description: DSI wrapper regulator and PLL control register. + byte_offset: 1072 + fieldset: WRPCR + - name: HWCFGR + description: DSI Host hardware configuration register. + byte_offset: 2032 + access: Read + fieldset: HWCFGR + - name: VERR + description: DSI Host version register. + byte_offset: 2036 + access: Read + fieldset: VERR + - name: IPIDR + description: DSI Host identification register. + byte_offset: 2040 + access: Read + fieldset: IPIDR + - name: SIDR + description: DSI Host size identification register. + byte_offset: 2044 + access: Read + fieldset: SIDR +fieldset/CCR: + description: DSI Host clock control register. + fields: + - name: TXECKDIV + description: TXECKDIV. + bit_offset: 0 + bit_size: 8 + - name: TOCKDIV + description: TOCKDIV. + bit_offset: 8 + bit_size: 8 +fieldset/CLCR: + description: DSI Host clock lane configuration register. + fields: + - name: DPCC + description: DPCC. + bit_offset: 0 + bit_size: 1 + - name: ACR + description: ACR. + bit_offset: 1 + bit_size: 1 +fieldset/CLTCR: + description: DSI Host clock lane timer configuration register. + fields: + - name: LP2HS_TIME + description: LP2HS_TIME. + bit_offset: 0 + bit_size: 10 + - name: HS2LP_TIME + description: HS2LP_TIME. + bit_offset: 16 + bit_size: 10 +fieldset/CMCR: + description: DSI Host command mode configuration register. + fields: + - name: TEARE + description: TEARE. + bit_offset: 0 + bit_size: 1 + - name: ARE + description: ARE. + bit_offset: 1 + bit_size: 1 + - name: GSW0TX + description: GSW0TX. + bit_offset: 8 + bit_size: 1 + - name: GSW1TX + description: GSW1TX. + bit_offset: 9 + bit_size: 1 + - name: GSW2TX + description: GSW2TX. + bit_offset: 10 + bit_size: 1 + - name: GSR0TX + description: GSR0TX. + bit_offset: 11 + bit_size: 1 + - name: GSR1TX + description: GSR1TX. + bit_offset: 12 + bit_size: 1 + - name: GSR2TX + description: GSR2TX. + bit_offset: 13 + bit_size: 1 + - name: GLWTX + description: GLWTX. + bit_offset: 14 + bit_size: 1 + - name: DSW0TX + description: DSW0TX. + bit_offset: 16 + bit_size: 1 + - name: DSW1TX + description: DSW1TX. + bit_offset: 17 + bit_size: 1 + - name: DSR0TX + description: DSR0TX. + bit_offset: 18 + bit_size: 1 + - name: DLWTX + description: DLWTX. + bit_offset: 19 + bit_size: 1 + - name: MRDPS + description: MRDPS. + bit_offset: 24 + bit_size: 1 +fieldset/CR: + description: DSI Host control register. + fields: + - name: EN + description: EN. + bit_offset: 0 + bit_size: 1 +fieldset/DLTCR: + description: DSI Host data lane timer configuration register. + fields: + - name: LP2HS_TIME + description: LP2HS_TIME. + bit_offset: 0 + bit_size: 10 + - name: HS2LP_TIME + description: HS2LP_TIME. + bit_offset: 16 + bit_size: 10 +fieldset/DLTRCR: + description: DSI Host data lane timer read configuration register. + fields: + - name: MRD_TIME + description: MRD_TIME. + bit_offset: 0 + bit_size: 15 +fieldset/FIR0: + description: DSI Host force interrupt register 0. + fields: + - name: FAE0 + description: FAE0. + bit_offset: 0 + bit_size: 1 + - name: FAE1 + description: FAE1. + bit_offset: 1 + bit_size: 1 + - name: FAE2 + description: FAE2. + bit_offset: 2 + bit_size: 1 + - name: FAE3 + description: FAE3. + bit_offset: 3 + bit_size: 1 + - name: FAE4 + description: FAE4. + bit_offset: 4 + bit_size: 1 + - name: FAE5 + description: FAE5. + bit_offset: 5 + bit_size: 1 + - name: FAE6 + description: FAE6. + bit_offset: 6 + bit_size: 1 + - name: FAE7 + description: FAE7. + bit_offset: 7 + bit_size: 1 + - name: FAE8 + description: FAE8. + bit_offset: 8 + bit_size: 1 + - name: FAE9 + description: FAE9. + bit_offset: 9 + bit_size: 1 + - name: FAE10 + description: FAE10. + bit_offset: 10 + bit_size: 1 + - name: FAE11 + description: FAE11. + bit_offset: 11 + bit_size: 1 + - name: FAE12 + description: FAE12. + bit_offset: 12 + bit_size: 1 + - name: FAE13 + description: FAE13. + bit_offset: 13 + bit_size: 1 + - name: FAE14 + description: FAE14. + bit_offset: 14 + bit_size: 1 + - name: FAE15 + description: FAE15. + bit_offset: 15 + bit_size: 1 + - name: FPE0 + description: FPE0. + bit_offset: 16 + bit_size: 1 + - name: FPE1 + description: FPE1. + bit_offset: 17 + bit_size: 1 + - name: FPE2 + description: FPE2. + bit_offset: 18 + bit_size: 1 + - name: FPE3 + description: FPE3. + bit_offset: 19 + bit_size: 1 + - name: FPE4 + description: FPE4. + bit_offset: 20 + bit_size: 1 +fieldset/FIR1: + description: DSI Host force interrupt register 1. + fields: + - name: FTOHSTX + description: FTOHSTX. + bit_offset: 0 + bit_size: 1 + - name: FTOLPRX + description: FTOLPRX. + bit_offset: 1 + bit_size: 1 + - name: FECCSE + description: FECCSE. + bit_offset: 2 + bit_size: 1 + - name: FECCME + description: FECCME. + bit_offset: 3 + bit_size: 1 + - name: FCRCE + description: FCRCE. + bit_offset: 4 + bit_size: 1 + - name: FPSE + description: FPSE. + bit_offset: 5 + bit_size: 1 + - name: FEOTPE + description: FEOTPE. + bit_offset: 6 + bit_size: 1 + - name: FLPWRE + description: FLPWRE. + bit_offset: 7 + bit_size: 1 + - name: FGCWRE + description: FGCWRE. + bit_offset: 8 + bit_size: 1 + - name: FGPWRE + description: FGPWRE. + bit_offset: 9 + bit_size: 1 + - name: FGPTXE + description: FGPTXE. + bit_offset: 10 + bit_size: 1 + - name: FGPRDE + description: FGPRDE. + bit_offset: 11 + bit_size: 1 + - name: FGPRXE + description: FGPRXE. + bit_offset: 12 + bit_size: 1 +fieldset/GHCR: + description: DSI Host generic header configuration register. + fields: + - name: DT + description: DT. + bit_offset: 0 + bit_size: 6 + - name: VCID + description: VCID. + bit_offset: 6 + bit_size: 2 + - name: WCLSB + description: WCLSB. + bit_offset: 8 + bit_size: 8 + - name: WCMSB + description: WCMSB. + bit_offset: 16 + bit_size: 8 +fieldset/GPDR: + description: DSI Host generic payload data register. + fields: + - name: DATA1 + description: DATA1. + bit_offset: 0 + bit_size: 8 + - name: DATA2 + description: DATA2. + bit_offset: 8 + bit_size: 8 + - name: DATA3 + description: DATA3. + bit_offset: 16 + bit_size: 8 + - name: DATA4 + description: DATA4. + bit_offset: 24 + bit_size: 8 +fieldset/GPSR: + description: DSI Host generic packet status register. + fields: + - name: CMDFE + description: CMDFE. + bit_offset: 0 + bit_size: 1 + - name: CMDFF + description: CMDFF. + bit_offset: 1 + bit_size: 1 + - name: PWRFE + description: PWRFE. + bit_offset: 2 + bit_size: 1 + - name: PWRFF + description: PWRFF. + bit_offset: 3 + bit_size: 1 + - name: PRDFE + description: PRDFE. + bit_offset: 4 + bit_size: 1 + - name: PRDFF + description: PRDFF. + bit_offset: 5 + bit_size: 1 + - name: RCB + description: RCB. + bit_offset: 6 + bit_size: 1 +fieldset/GVCIDR: + description: DSI Host generic VCID register. + fields: + - name: VCID + description: VCID. + bit_offset: 0 + bit_size: 2 +fieldset/HWCFGR: + description: DSI Host hardware configuration register. + fields: + - name: TECHNO + description: TECHNO. + bit_offset: 0 + bit_size: 4 + - name: FIFOSIZE + description: FIFOSIZE. + bit_offset: 4 + bit_size: 12 +fieldset/IER0: + description: DSI Host interrupt enable register 0. + fields: + - name: AE0IE + description: AE0IE. + bit_offset: 0 + bit_size: 1 + - name: AE1IE + description: AE1IE. + bit_offset: 1 + bit_size: 1 + - name: AE2IE + description: AE2IE. + bit_offset: 2 + bit_size: 1 + - name: AE3IE + description: AE3IE. + bit_offset: 3 + bit_size: 1 + - name: AE4IE + description: AE4IE. + bit_offset: 4 + bit_size: 1 + - name: AE5IE + description: AE5IE. + bit_offset: 5 + bit_size: 1 + - name: AE6IE + description: AE6IE. + bit_offset: 6 + bit_size: 1 + - name: AE7IE + description: AE7IE. + bit_offset: 7 + bit_size: 1 + - name: AE8IE + description: AE8IE. + bit_offset: 8 + bit_size: 1 + - name: AE9IE + description: AE9IE. + bit_offset: 9 + bit_size: 1 + - name: AE10IE + description: AE10IE. + bit_offset: 10 + bit_size: 1 + - name: AE11IE + description: AE11IE. + bit_offset: 11 + bit_size: 1 + - name: AE12IE + description: AE12IE. + bit_offset: 12 + bit_size: 1 + - name: AE13IE + description: AE13IE. + bit_offset: 13 + bit_size: 1 + - name: AE14IE + description: AE14IE. + bit_offset: 14 + bit_size: 1 + - name: AE15IE + description: AE15IE. + bit_offset: 15 + bit_size: 1 + - name: PE0IE + description: PE0IE. + bit_offset: 16 + bit_size: 1 + - name: PE1IE + description: PE1IE. + bit_offset: 17 + bit_size: 1 + - name: PE2IE + description: PE2IE. + bit_offset: 18 + bit_size: 1 + - name: PE3IE + description: PE3IE. + bit_offset: 19 + bit_size: 1 + - name: PE4IE + description: PE4IE. + bit_offset: 20 + bit_size: 1 +fieldset/IER1: + description: DSI Host interrupt enable register 1. + fields: + - name: TOHSTXIE + description: TOHSTXIE. + bit_offset: 0 + bit_size: 1 + - name: TOLPRXIE + description: TOLPRXIE. + bit_offset: 1 + bit_size: 1 + - name: ECCSEIE + description: ECCSEIE. + bit_offset: 2 + bit_size: 1 + - name: ECCMEIE + description: ECCMEIE. + bit_offset: 3 + bit_size: 1 + - name: CRCEIE + description: CRCEIE. + bit_offset: 4 + bit_size: 1 + - name: PSEIE + description: PSEIE. + bit_offset: 5 + bit_size: 1 + - name: EOTPEIE + description: EOTPEIE. + bit_offset: 6 + bit_size: 1 + - name: LPWREIE + description: LPWREIE. + bit_offset: 7 + bit_size: 1 + - name: GCWREIE + description: GCWREIE. + bit_offset: 8 + bit_size: 1 + - name: GPWREIE + description: GPWREIE. + bit_offset: 9 + bit_size: 1 + - name: GPTXEIE + description: GPTXEIE. + bit_offset: 10 + bit_size: 1 + - name: GPRDEIE + description: GPRDEIE. + bit_offset: 11 + bit_size: 1 + - name: GPRXEIE + description: GPRXEIE. + bit_offset: 12 + bit_size: 1 +fieldset/IPIDR: + description: DSI Host identification register. + fields: + - name: ID + description: ID. + bit_offset: 0 + bit_size: 32 +fieldset/ISR0: + description: DSI Host interrupt and status register 0. + fields: + - name: AE0 + description: AE0. + bit_offset: 0 + bit_size: 1 + - name: AE1 + description: AE1. + bit_offset: 1 + bit_size: 1 + - name: AE2 + description: AE2. + bit_offset: 2 + bit_size: 1 + - name: AE3 + description: AE3. + bit_offset: 3 + bit_size: 1 + - name: AE4 + description: AE4. + bit_offset: 4 + bit_size: 1 + - name: AE5 + description: AE5. + bit_offset: 5 + bit_size: 1 + - name: AE6 + description: AE6. + bit_offset: 6 + bit_size: 1 + - name: AE7 + description: AE7. + bit_offset: 7 + bit_size: 1 + - name: AE8 + description: AE8. + bit_offset: 8 + bit_size: 1 + - name: AE9 + description: AE9. + bit_offset: 9 + bit_size: 1 + - name: AE10 + description: AE10. + bit_offset: 10 + bit_size: 1 + - name: AE11 + description: AE11. + bit_offset: 11 + bit_size: 1 + - name: AE12 + description: AE12. + bit_offset: 12 + bit_size: 1 + - name: AE13 + description: AE13. + bit_offset: 13 + bit_size: 1 + - name: AE14 + description: AE14. + bit_offset: 14 + bit_size: 1 + - name: AE15 + description: AE15. + bit_offset: 15 + bit_size: 1 + - name: PE0 + description: PE0. + bit_offset: 16 + bit_size: 1 + - name: PE1 + description: PE1. + bit_offset: 17 + bit_size: 1 + - name: PE2 + description: PE2. + bit_offset: 18 + bit_size: 1 + - name: PE3 + description: PE3. + bit_offset: 19 + bit_size: 1 + - name: PE4 + description: PE4. + bit_offset: 20 + bit_size: 1 +fieldset/ISR1: + description: DSI Host interrupt and status register 1. + fields: + - name: TOHSTX + description: TOHSTX. + bit_offset: 0 + bit_size: 1 + - name: TOLPRX + description: TOLPRX. + bit_offset: 1 + bit_size: 1 + - name: ECCSE + description: ECCSE. + bit_offset: 2 + bit_size: 1 + - name: ECCME + description: ECCME. + bit_offset: 3 + bit_size: 1 + - name: CRCE + description: CRCE. + bit_offset: 4 + bit_size: 1 + - name: PSE + description: PSE. + bit_offset: 5 + bit_size: 1 + - name: EOTPE + description: EOTPE. + bit_offset: 6 + bit_size: 1 + - name: LPWRE + description: LPWRE. + bit_offset: 7 + bit_size: 1 + - name: GCWRE + description: GCWRE. + bit_offset: 8 + bit_size: 1 + - name: GPWRE + description: GPWRE. + bit_offset: 9 + bit_size: 1 + - name: GPTXE + description: GPTXE. + bit_offset: 10 + bit_size: 1 + - name: GPRDE + description: GPRDE. + bit_offset: 11 + bit_size: 1 + - name: GPRXE + description: GPRXE. + bit_offset: 12 + bit_size: 1 +fieldset/LCCCR: + description: DSI Host LTDC current color coding register. + fields: + - name: COLC + description: COLC. + bit_offset: 0 + bit_size: 4 + - name: LPE + description: LPE. + bit_offset: 8 + bit_size: 1 +fieldset/LCCR: + description: DSI Host LTDC command configuration register. + fields: + - name: CMDSIZE + description: CMDSIZE. + bit_offset: 0 + bit_size: 16 +fieldset/LCOLCR: + description: DSI Host LTDC color coding register. + fields: + - name: COLC + description: COLC. + bit_offset: 0 + bit_size: 4 + - name: LPE + description: LPE. + bit_offset: 8 + bit_size: 1 +fieldset/LCVCIDR: + description: DSI Host LTDC current VCID register. + fields: + - name: VCID + description: VCID. + bit_offset: 0 + bit_size: 2 +fieldset/LPCR: + description: DSI Host LTDC polarity configuration register. + fields: + - name: DEP + description: DEP. + bit_offset: 0 + bit_size: 1 + - name: VSP + description: VSP. + bit_offset: 1 + bit_size: 1 + - name: HSP + description: HSP. + bit_offset: 2 + bit_size: 1 +fieldset/LPMCCR: + description: DSI Host low-power mode current configuration register. + fields: + - name: VLPSIZE + description: VLPSIZE. + bit_offset: 0 + bit_size: 8 + - name: LPSIZE + description: LPSIZE. + bit_offset: 16 + bit_size: 8 +fieldset/LPMCR: + description: DSI Host low-power mode configuration register. + fields: + - name: VLPSIZE + description: VLPSIZE. + bit_offset: 0 + bit_size: 8 + - name: LPSIZE + description: LPSIZE. + bit_offset: 16 + bit_size: 8 +fieldset/LVCIDR: + description: DSI Host LTDC VCID register. + fields: + - name: VCID + description: VCID. + bit_offset: 0 + bit_size: 2 +fieldset/MCR: + description: DSI Host mode configuration register. + fields: + - name: CMDM + description: CMDM. + bit_offset: 0 + bit_size: 1 +fieldset/PCONFR: + description: DSI Host PHY configuration register. + fields: + - name: NL + description: NL. + bit_offset: 0 + bit_size: 2 + - name: SW_TIME + description: SW_TIME. + bit_offset: 8 + bit_size: 8 +fieldset/PCR: + description: DSI Host protocol configuration register. + fields: + - name: ETTXE + description: ETTXE. + bit_offset: 0 + bit_size: 1 + - name: ETRXE + description: ETRXE. + bit_offset: 1 + bit_size: 1 + - name: BTAE + description: BTAE. + bit_offset: 2 + bit_size: 1 + - name: ECCRXE + description: ECCRXE. + bit_offset: 3 + bit_size: 1 + - name: CRCRXE + description: CRCRXE. + bit_offset: 4 + bit_size: 1 +fieldset/PCTLR: + description: DSI Host PHY control register. + fields: + - name: DEN + description: DEN. + bit_offset: 1 + bit_size: 1 + - name: CKE + description: CKE. + bit_offset: 2 + bit_size: 1 +fieldset/PSR: + description: DSI Host PHY status register. + fields: + - name: PD + description: PD. + bit_offset: 1 + bit_size: 1 + - name: PSSC + description: PSSC. + bit_offset: 2 + bit_size: 1 + - name: UANC + description: UANC. + bit_offset: 3 + bit_size: 1 + - name: PSS0 + description: PSS0. + bit_offset: 4 + bit_size: 1 + - name: UAN0 + description: UAN0. + bit_offset: 5 + bit_size: 1 + - name: RUE0 + description: RUE0. + bit_offset: 6 + bit_size: 1 + - name: PSS1 + description: PSS1. + bit_offset: 7 + bit_size: 1 + - name: UAN1 + description: UAN1. + bit_offset: 8 + bit_size: 1 +fieldset/PTTCR: + description: DSI Host PHY TX triggers configuration register. + fields: + - name: TX_TRIG + description: TX_TRIG. + bit_offset: 0 + bit_size: 4 +fieldset/PUCR: + description: DSI Host PHY ULPS control register. + fields: + - name: URCL + description: URCL. + bit_offset: 0 + bit_size: 1 + - name: UECL + description: UECL. + bit_offset: 1 + bit_size: 1 + - name: URDL + description: URDL. + bit_offset: 2 + bit_size: 1 + - name: UEDL + description: UEDL. + bit_offset: 3 + bit_size: 1 +fieldset/SIDR: + description: DSI Host size identification register. + fields: + - name: SID + description: SID. + bit_offset: 0 + bit_size: 32 +fieldset/TCCR0: + description: DSI Host timeout counter configuration register 0. + fields: + - name: LPRX_TOCNT + description: LPRX_TOCNT. + bit_offset: 0 + bit_size: 16 + - name: HSTX_TOCNT + description: HSTX_TOCNT. + bit_offset: 16 + bit_size: 16 +fieldset/TCCR1: + description: DSI Host timeout counter configuration register 1. + fields: + - name: HSRD_TOCNT + description: HSRD_TOCNT. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR2: + description: DSI Host timeout counter configuration register 2. + fields: + - name: LPRD_TOCNT + description: LPRD_TOCNT. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR3: + description: DSI Host timeout counter configuration register 3. + fields: + - name: HSWR_TOCNT + description: HSWR_TOCNT. + bit_offset: 0 + bit_size: 16 + - name: PM + description: PM. + bit_offset: 24 + bit_size: 1 +fieldset/TCCR4: + description: DSI Host timeout counter configuration register 4. + fields: + - name: LPWR_TOCNT + description: LPWR_TOCNT. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR5: + description: DSI Host timeout counter configuration register 5. + fields: + - name: BTA_TOCNT + description: BTA_TOCNT. + bit_offset: 0 + bit_size: 16 +fieldset/VCCCR: + description: DSI Host video chunks current configuration register. + fields: + - name: NUMC + description: NUMC. + bit_offset: 0 + bit_size: 13 +fieldset/VCCR: + description: DSI Host video chunks configuration register. + fields: + - name: NUMC + description: NUMC. + bit_offset: 0 + bit_size: 13 +fieldset/VERR: + description: DSI Host version register. + fields: + - name: MINREV + description: MINREV. + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: MAJREV. + bit_offset: 4 + bit_size: 4 +fieldset/VHBPCCR: + description: DSI Host video HBP current configuration register. + fields: + - name: HBP + description: HBP. + bit_offset: 0 + bit_size: 12 +fieldset/VHBPCR: + description: DSI Host video HBP configuration register. + fields: + - name: HBP + description: HBP. + bit_offset: 0 + bit_size: 12 +fieldset/VHSACCR: + description: DSI Host video HSA current configuration register. + fields: + - name: HSA + description: HSA. + bit_offset: 0 + bit_size: 12 +fieldset/VHSACR: + description: DSI Host video HSA configuration register. + fields: + - name: HSA + description: HSA. + bit_offset: 0 + bit_size: 12 +fieldset/VLCCR: + description: DSI Host video line current configuration register. + fields: + - name: HLINE + description: HLINE. + bit_offset: 0 + bit_size: 15 +fieldset/VLCR: + description: DSI Host video line configuration register. + fields: + - name: HLINE + description: HLINE. + bit_offset: 0 + bit_size: 15 +fieldset/VMCCR: + description: DSI Host video mode current configuration register. + fields: + - name: VMT + description: VMT. + bit_offset: 0 + bit_size: 2 + - name: LPVSAE + description: LPVSAE. + bit_offset: 2 + bit_size: 1 + - name: LPVBPE + description: LPVBPE. + bit_offset: 3 + bit_size: 1 + - name: LPVFPE + description: LPVFPE. + bit_offset: 4 + bit_size: 1 + - name: LPVAE + description: LPVAE. + bit_offset: 5 + bit_size: 1 + - name: LPHBPE + description: LPHBPE. + bit_offset: 6 + bit_size: 1 + - name: LPHFE + description: LPHFE. + bit_offset: 7 + bit_size: 1 + - name: FBTAAE + description: FBTAAE. + bit_offset: 8 + bit_size: 1 + - name: LPCE + description: LPCE. + bit_offset: 9 + bit_size: 1 +fieldset/VMCR: + description: DSI Host video mode configuration register. + fields: + - name: VMT + description: VMT. + bit_offset: 0 + bit_size: 2 + - name: LPVSAE + description: LPVSAE. + bit_offset: 8 + bit_size: 1 + - name: LPVBPE + description: LPVBPE. + bit_offset: 9 + bit_size: 1 + - name: LPVFPE + description: LPVFPE. + bit_offset: 10 + bit_size: 1 + - name: LPVAE + description: LPVAE. + bit_offset: 11 + bit_size: 1 + - name: LPHBPE + description: LPHBPE. + bit_offset: 12 + bit_size: 1 + - name: LPHFPE + description: LPHFPE. + bit_offset: 13 + bit_size: 1 + - name: FBTAAE + description: FBTAAE. + bit_offset: 14 + bit_size: 1 + - name: LPCE + description: LPCE. + bit_offset: 15 + bit_size: 1 + - name: PGE + description: PGE. + bit_offset: 16 + bit_size: 1 + - name: PGM + description: PGM. + bit_offset: 20 + bit_size: 1 + - name: PGO + description: PGO. + bit_offset: 24 + bit_size: 1 +fieldset/VNPCCR: + description: DSI Host video null packet current configuration register. + fields: + - name: NPSIZE + description: NPSIZE. + bit_offset: 0 + bit_size: 13 +fieldset/VNPCR: + description: DSI Host video null packet configuration register. + fields: + - name: NPSIZE + description: NPSIZE. + bit_offset: 0 + bit_size: 13 +fieldset/VPCCR: + description: DSI Host video packet current configuration register. + fields: + - name: VPSIZE + description: VPSIZE. + bit_offset: 0 + bit_size: 14 +fieldset/VPCR: + description: DSI Host video packet configuration register. + fields: + - name: VPSIZE + description: VPSIZE. + bit_offset: 0 + bit_size: 14 +fieldset/VR: + description: DSI Host version register. + fields: + - name: VERSION + description: VERSION. + bit_offset: 0 + bit_size: 32 +fieldset/VSCR: + description: DSI Host video shadow control register. + fields: + - name: EN + description: EN. + bit_offset: 0 + bit_size: 1 + - name: UR + description: UR. + bit_offset: 8 + bit_size: 1 +fieldset/VVACCR: + description: DSI Host video VA current configuration register. + fields: + - name: VA + description: VA. + bit_offset: 0 + bit_size: 14 +fieldset/VVACR: + description: DSI Host video VA configuration register. + fields: + - name: VA + description: VA. + bit_offset: 0 + bit_size: 14 +fieldset/VVBPCCR: + description: DSI Host video VBP current configuration register. + fields: + - name: VBP + description: VBP. + bit_offset: 0 + bit_size: 10 +fieldset/VVBPCR: + description: DSI Host video VBP configuration register. + fields: + - name: VBP + description: VBP. + bit_offset: 0 + bit_size: 10 +fieldset/VVFPCCR: + description: DSI Host video VFP current configuration register. + fields: + - name: VFP + description: VFP. + bit_offset: 0 + bit_size: 10 +fieldset/VVFPCR: + description: DSI Host video VFP configuration register. + fields: + - name: VFP + description: VFP. + bit_offset: 0 + bit_size: 10 +fieldset/VVSACCR: + description: DSI Host video VSA current configuration register. + fields: + - name: VSA + description: VSA. + bit_offset: 0 + bit_size: 10 +fieldset/VVSACR: + description: DSI Host video VSA configuration register. + fields: + - name: VSA + description: VSA. + bit_offset: 0 + bit_size: 10 +fieldset/WCFGR: + description: DSI wrapper configuration register. + fields: + - name: DSIM + description: DSIM. + bit_offset: 0 + bit_size: 1 + - name: COLMUX + description: COLMUX. + bit_offset: 1 + bit_size: 3 + - name: TESRC + description: TESRC. + bit_offset: 4 + bit_size: 1 + - name: TEPOL + description: TEPOL. + bit_offset: 5 + bit_size: 1 + - name: AR + description: AR. + bit_offset: 6 + bit_size: 1 + - name: VSPOL + description: VSPOL. + bit_offset: 7 + bit_size: 1 +fieldset/WCR: + description: DSI wrapper control register. + fields: + - name: COLM + description: COLM. + bit_offset: 0 + bit_size: 1 + - name: SHTDN + description: SHTDN. + bit_offset: 1 + bit_size: 1 + - name: LTDCEN + description: LTDCEN. + bit_offset: 2 + bit_size: 1 + - name: DSIEN + description: DSIEN. + bit_offset: 3 + bit_size: 1 +fieldset/WIER: + description: DSI wrapper interrupt enable register. + fields: + - name: TEIE + description: TEIE. + bit_offset: 0 + bit_size: 1 + - name: ERIE + description: ERIE. + bit_offset: 1 + bit_size: 1 + - name: PLLLIE + description: PLLLIE. + bit_offset: 9 + bit_size: 1 + - name: PLLUIE + description: PLLUIE. + bit_offset: 10 + bit_size: 1 + - name: RRIE + description: RRIE. + bit_offset: 13 + bit_size: 1 +fieldset/WIFCR: + description: DSI wrapper interrupt flag clear register. + fields: + - name: CTEIF + description: CTEIF. + bit_offset: 0 + bit_size: 1 + - name: CERIF + description: CERIF. + bit_offset: 1 + bit_size: 1 + - name: CPLLLIF + description: CPLLLIF. + bit_offset: 9 + bit_size: 1 + - name: CPLLUIF + description: CPLLUIF. + bit_offset: 10 + bit_size: 1 + - name: CRRIF + description: CRRIF. + bit_offset: 13 + bit_size: 1 +fieldset/WISR: + description: DSI wrapper interrupt and status register. + fields: + - name: TEIF + description: TEIF. + bit_offset: 0 + bit_size: 1 + - name: ERIF + description: ERIF. + bit_offset: 1 + bit_size: 1 + - name: BUSY + description: BUSY. + bit_offset: 2 + bit_size: 1 + - name: PLLLS + description: PLLLS. + bit_offset: 8 + bit_size: 1 + - name: PLLLIF + description: PLLLIF. + bit_offset: 9 + bit_size: 1 + - name: PLLUIF + description: PLLUIF. + bit_offset: 10 + bit_size: 1 + - name: RRS + description: RRS. + bit_offset: 12 + bit_size: 1 + - name: RRIF + description: RRIF. + bit_offset: 13 + bit_size: 1 +fieldset/WPCR0: + description: DSI wrapper PHY configuration register 0. + fields: + - name: UIX4 + description: UIX4. + bit_offset: 0 + bit_size: 6 + - name: SWCL + description: SWCL. + bit_offset: 6 + bit_size: 1 + - name: SWDL0 + description: SWDL0. + bit_offset: 7 + bit_size: 1 + - name: SWDL1 + description: SWDL1. + bit_offset: 8 + bit_size: 1 + - name: HSICL + description: HSICL. + bit_offset: 9 + bit_size: 1 + - name: HSIDL0 + description: HSIDL0. + bit_offset: 10 + bit_size: 1 + - name: HSIDL1 + description: HSIDL1. + bit_offset: 11 + bit_size: 1 + - name: FTXSMCL + description: FTXSMCL. + bit_offset: 12 + bit_size: 1 + - name: FTXSMDL + description: FTXSMDL. + bit_offset: 13 + bit_size: 1 + - name: CDOFFDL + description: CDOFFDL. + bit_offset: 14 + bit_size: 1 + - name: TDDL + description: TDDL. + bit_offset: 16 + bit_size: 1 +fieldset/WPCR1: + description: This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0). + fields: + - name: SKEWCL + description: SKEWCL. + bit_offset: 0 + bit_size: 2 + - name: SKEWDL + description: SKEWDL. + bit_offset: 2 + bit_size: 2 + - name: LPTXSRCL + description: LPTXSRCL. + bit_offset: 6 + bit_size: 2 + - name: LPTXSRDL + description: LPTXSRDL. + bit_offset: 8 + bit_size: 2 + - name: SDDCCL + description: SDDCCL. + bit_offset: 12 + bit_size: 1 + - name: SDDCDL + description: SDDCDL. + bit_offset: 13 + bit_size: 1 + - name: HSTXSRUCL + description: HSTXSRUCL. + bit_offset: 16 + bit_size: 1 + - name: HSTXSRDCL + description: HSTXSRDCL. + bit_offset: 17 + bit_size: 1 + - name: HSTXSRUDL + description: HSTXSRUDL. + bit_offset: 18 + bit_size: 1 + - name: HSTXSRDDL + description: HSTXSRDDL. + bit_offset: 19 + bit_size: 1 +fieldset/WRPCR: + description: DSI wrapper regulator and PLL control register. + fields: + - name: PLLEN + description: PLLEN. + bit_offset: 0 + bit_size: 1 + - name: NDIV + description: NDIV. + bit_offset: 2 + bit_size: 7 + - name: IDF + description: IDF. + bit_offset: 11 + bit_size: 4 + - name: ODF + description: ODF. + bit_offset: 16 + bit_size: 2 + - name: REGEN + description: REGEN. + bit_offset: 24 + bit_size: 1 + - name: BGREN + description: BGREN. + bit_offset: 28 + bit_size: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index c58363c..e348e9e 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -263,6 +263,9 @@ impl PeriMatcher { (".*:WWDG:wwdg1_v2_0", ("wwdg", "v2", "WWDG")), (".*:JPEG:jpeg1_v1_0", ("jpeg", "v1", "JPEG")), (".*:LTDC:lcdtft1_v1_1", ("ltdc", "v1", "LTDC")), + (".*:DSIHOST:dsihost1_v1_0", ("dsihost", "v1", "DSIHOST")), + (".*:DSIHOST:dsihost1_v1_0_SHARK", ("dsihost", "v1", "DSIHOST")), + (".*:DSIHOST:dsihost1_v2_0", ("dsihost", "v2", "DSIHOST")), (".*:MDIOS:mdios1_v1_0", ("mdios", "v1", "MDIOS")), (".*:QUADSPI:.*", ("quadspi", "v1", "QUADSPI")), ("STM32F1.*:BKP.*", ("bkp", "v1", "BKP")), diff --git a/stm32-data-gen/src/header.rs b/stm32-data-gen/src/header.rs index b6dfb44..82fc349 100644 --- a/stm32-data-gen/src/header.rs +++ b/stm32-data-gen/src/header.rs @@ -190,6 +190,7 @@ impl Defines { ), ("FDCANRAM", &["SRAMCAN_BASE", "SRAMCAN_BASE_NS"]), ("VREFINTCAL", &["VREFINT_CAL_ADDR_CMSIS"]), + ("DSIHOST", &["DSI_BASE"]), ]; let alt_peri_defines: HashMap<_, _> = ALT_PERI_DEFINES.iter().copied().collect(); From c8a3e8875de9816a5e240466f09590fede8d037b Mon Sep 17 00:00:00 2001 From: JuliDi <20155974+JuliDi@users.noreply.github.com> Date: Sun, 7 Apr 2024 16:22:22 +0200 Subject: [PATCH 2/6] add DSI as fallback for DSIHOST in stm32-data-gen rcc.rs --- stm32-data-gen/src/rcc.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index b5846ac..740fb3d 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -264,6 +264,7 @@ impl ParsedRccs { ("DAC", &["DAC1", "ADCDAC"]), ("DAC1", &["DAC12", "ADCDAC"]), ("DAC2", &["DAC12", "ADCDAC"]), + ("DSIHOST", &["DSI"]), ("ETH", &["ETHMAC", "ETH1MAC"]), ("SPI1", &["SPI12", "SPI123"]), ("SPI2", &["SPI12", "SPI123"]), From dd12c3787ae4b1c812595a5ce9662955045c0a3d Mon Sep 17 00:00:00 2001 From: JuliDi <20155974+JuliDi@users.noreply.github.com> Date: Mon, 8 Apr 2024 13:48:25 +0200 Subject: [PATCH 3/6] change DSIPHY to DSI_PHY for rcc_l4plus.yaml to match other families --- data/registers/rcc_l4plus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/data/registers/rcc_l4plus.yaml b/data/registers/rcc_l4plus.yaml index 17e9f27..9db03de 100644 --- a/data/registers/rcc_l4plus.yaml +++ b/data/registers/rcc_l4plus.yaml @@ -1713,7 +1713,7 @@ enum/DFSDMSEL: enum/DSISEL: bit_size: 1 variants: - - name: DSIPHY + - name: DSI_PHY description: DSI-PHY is selected as DSI byte lane clock source (usual case) value: 0 - name: PLLSAI2_Q From 95ff92f362817d30e0460eebed8e3597a4c804c1 Mon Sep 17 00:00:00 2001 From: JuliDi <20155974+JuliDi@users.noreply.github.com> Date: Mon, 8 Apr 2024 14:10:32 +0200 Subject: [PATCH 4/6] remove DSISEL from other register ymls where it is not present --- data/registers/rcc_h7.yaml | 12 +++++++++++- data/registers/rcc_h7ab.yaml | 4 ---- data/registers/rcc_h7rm0433.yaml | 4 ---- stm32-data-gen/src/rcc.rs | 3 +-- 4 files changed, 12 insertions(+), 11 deletions(-) diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index d3d5b62..69a4d94 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -3073,9 +3073,10 @@ fieldset/D1CCIPR: bit_size: 2 enum: FMCSEL - name: DSISEL - description: kernel clock source selection + description: DSI clock source selection (not available on all chips) bit_offset: 8 bit_size: 1 + enum: DSISEL - name: SDMMCSEL description: SDMMC kernel clock source selection bit_offset: 16 @@ -3550,6 +3551,15 @@ enum/DFSDMSEL: - name: SYS description: System clock selected as peripheral clock value: 1 +enum/DSISEL: + bit_size: 1 + variants: + - name: DSI_PHY + description: DSI-PHY used as DSI byte lane clock source (usual case) + value: 0 + - name: PLL2_Q + description: PLL2_Q used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode) + value: 1 enum/FDCANSEL: bit_size: 2 variants: diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index 554992a..aab77da 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -2018,10 +2018,6 @@ fieldset/D1CCIPR: bit_offset: 4 bit_size: 2 enum: FMCSEL - - name: DSISEL - description: kernel clock source selection - bit_offset: 8 - bit_size: 1 - name: SDMMCSEL description: SDMMC kernel clock source selection bit_offset: 16 diff --git a/data/registers/rcc_h7rm0433.yaml b/data/registers/rcc_h7rm0433.yaml index 90549fa..22da980 100644 --- a/data/registers/rcc_h7rm0433.yaml +++ b/data/registers/rcc_h7rm0433.yaml @@ -3055,10 +3055,6 @@ fieldset/D1CCIPR: bit_offset: 4 bit_size: 2 enum: FMCSEL - - name: DSISEL - description: kernel clock source selection - bit_offset: 8 - bit_size: 1 - name: SDMMCSEL description: SDMMC kernel clock source selection bit_offset: 16 diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index 740fb3d..32b63a3 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -106,10 +106,10 @@ impl ParsedRccs { "AUDIOCLK", "PER", "CLK48", + "DSI_PHY", // TODO: variants to cleanup "AFIF", "HSI_HSE", - "DSI_PHY", "HSI_Div488", "SAI1_EXTCLK", "SAI2_EXTCLK", @@ -120,7 +120,6 @@ impl ParsedRccs { "DAC_HOLD_2", "RTCCLK", "RTC_WKUP", - "DSIPHY", "ICLK", "DCLK", "I2S1", From 804326f93f48e5ce83ae50fd75aa9987ea670ad9 Mon Sep 17 00:00:00 2001 From: JuliDi <20155974+JuliDi@users.noreply.github.com> Date: Mon, 8 Apr 2024 14:36:24 +0200 Subject: [PATCH 5/6] add dsihost for u5 chip family --- data/registers/dsihost_u5.yaml | 1718 +++++++ data/registers/rcc_u5.yaml | 8406 ++++++++++++++++---------------- stm32-data-gen/src/chips.rs | 1 + 3 files changed, 5922 insertions(+), 4203 deletions(-) create mode 100644 data/registers/dsihost_u5.yaml diff --git a/data/registers/dsihost_u5.yaml b/data/registers/dsihost_u5.yaml new file mode 100644 index 0000000..082dbbc --- /dev/null +++ b/data/registers/dsihost_u5.yaml @@ -0,0 +1,1718 @@ +block/DSIHOST: + description: DSI Host. + items: + - name: VR + description: DSI Host version register. + byte_offset: 0 + fieldset: VR + - name: CR + description: DSI Host control register. + byte_offset: 4 + fieldset: CR + - name: CCR + description: DSI Host clock control register. + byte_offset: 8 + fieldset: CCR + - name: LVCIDR + description: DSI Host LTDC VCID register. + byte_offset: 12 + fieldset: LVCIDR + - name: LCOLCR + description: DSI Host LTDC color coding register. + byte_offset: 16 + fieldset: LCOLCR + - name: LPCR + description: DSI Host LTDC polarity configuration register. + byte_offset: 20 + fieldset: LPCR + - name: LPMCR + description: DSI Host low-power mode configuration register. + byte_offset: 24 + fieldset: LPMCR + - name: PCR + description: DSI Host protocol configuration register. + byte_offset: 44 + fieldset: PCR + - name: GVCIDR + description: DSI Host generic VCID register. + byte_offset: 48 + fieldset: GVCIDR + - name: MCR + description: DSI Host mode configuration register. + byte_offset: 52 + fieldset: MCR + - name: VMCR + description: DSI Host video mode configuration register. + byte_offset: 56 + fieldset: VMCR + - name: VPCR + description: DSI Host video packet configuration register. + byte_offset: 60 + fieldset: VPCR + - name: VCCR + description: DSI Host video chunks configuration register. + byte_offset: 64 + fieldset: VCCR + - name: VNPCR + description: DSI Host video null packet configuration register. + byte_offset: 68 + fieldset: VNPCR + - name: VHSACR + description: DSI Host video HSA configuration register. + byte_offset: 72 + fieldset: VHSACR + - name: VHBPCR + description: DSI Host video HBP configuration register. + byte_offset: 76 + fieldset: VHBPCR + - name: VLCR + description: DSI Host video line configuration register. + byte_offset: 80 + fieldset: VLCR + - name: VVSACR + description: DSI Host video VSA configuration register. + byte_offset: 84 + fieldset: VVSACR + - name: VVBPCR + description: DSI Host video VBP configuration register. + byte_offset: 88 + fieldset: VVBPCR + - name: VVFPCR + description: DSI Host video VFP configuration register. + byte_offset: 92 + fieldset: VVFPCR + - name: VVACR + description: DSI Host video VA configuration register. + byte_offset: 96 + fieldset: VVACR + - name: LCCR + description: DSI Host LTDC command configuration register. + byte_offset: 100 + fieldset: LCCR + - name: CMCR + description: DSI Host command mode configuration register. + byte_offset: 104 + fieldset: CMCR + - name: GHCR + description: DSI Host generic header configuration register. + byte_offset: 108 + fieldset: GHCR + - name: GPDR + description: DSI Host generic payload data register. + byte_offset: 112 + fieldset: GPDR + - name: GPSR + description: DSI Host generic packet status register. + byte_offset: 116 + fieldset: GPSR + - name: TCCR0 + description: DSI Host timeout counter configuration register 0. + byte_offset: 120 + fieldset: TCCR0 + - name: TCCR1 + description: DSI Host timeout counter configuration register 1. + byte_offset: 124 + fieldset: TCCR1 + - name: TCCR2 + description: DSI Host timeout counter configuration register 2. + byte_offset: 128 + fieldset: TCCR2 + - name: TCCR3 + description: DSI Host timeout counter configuration register 3. + byte_offset: 132 + fieldset: TCCR3 + - name: TCCR4 + description: DSI Host timeout counter configuration register 4. + byte_offset: 136 + fieldset: TCCR4 + - name: TCCR5 + description: DSI Host timeout counter configuration register 5. + byte_offset: 140 + fieldset: TCCR5 + - name: CLCR + description: DSI Host clock lane configuration register. + byte_offset: 148 + fieldset: CLCR + - name: CLTCR + description: DSI Host clock lane timer configuration register. + byte_offset: 152 + fieldset: CLTCR + - name: DLTCR + description: DSI Host data lane timer configuration register. + byte_offset: 156 + fieldset: DLTCR + - name: PCTLR + description: DSI Host PHY control register. + byte_offset: 160 + fieldset: PCTLR + - name: PCONFR + description: DSI Host PHY configuration register. + byte_offset: 164 + fieldset: PCONFR + - name: PUCR + description: DSI Host PHY ULPS control register. + byte_offset: 168 + fieldset: PUCR + - name: PTTCR + description: DSI Host PHY TX triggers configuration register. + byte_offset: 172 + fieldset: PTTCR + - name: PSR + description: DSI Host PHY status register. + byte_offset: 176 + fieldset: PSR + - name: ISR0 + description: DSI Host interrupt and status register 0. + byte_offset: 188 + fieldset: ISR0 + - name: ISR1 + description: DSI Host interrupt and status register 1. + byte_offset: 192 + fieldset: ISR1 + - name: IER0 + description: DSI Host interrupt enable register 0. + byte_offset: 196 + fieldset: IER0 + - name: IER1 + description: DSI Host interrupt enable register 1. + byte_offset: 200 + fieldset: IER1 + - name: FIR0 + description: DSI Host force interrupt register 0. + byte_offset: 216 + fieldset: FIR0 + - name: FIR1 + description: DSI Host force interrupt register 1. + byte_offset: 220 + fieldset: FIR1 + - name: DLTRCR + description: DSI Host data lane timer read configuration register. + byte_offset: 244 + fieldset: DLTRCR + - name: VSCR + description: DSI Host video shadow control register. + byte_offset: 256 + fieldset: VSCR + - name: LCVCIDR + description: DSI Host LTDC current VCID register. + byte_offset: 268 + fieldset: LCVCIDR + - name: LCCCR + description: DSI Host LTDC current color coding register. + byte_offset: 272 + fieldset: LCCCR + - name: LPMCCR + description: DSI Host low-power mode current configuration register. + byte_offset: 280 + fieldset: LPMCCR + - name: VMCCR + description: DSI Host video mode current configuration register. + byte_offset: 312 + fieldset: VMCCR + - name: VPCCR + description: DSI Host video packet current configuration register. + byte_offset: 316 + fieldset: VPCCR + - name: VCCCR + description: DSI Host video chunks current configuration register. + byte_offset: 320 + fieldset: VCCCR + - name: VNPCCR + description: DSI Host video null packet current configuration register. + byte_offset: 324 + fieldset: VNPCCR + - name: VHSACCR + description: DSI Host video HSA current configuration register. + byte_offset: 328 + fieldset: VHSACCR + - name: VHBPCCR + description: DSI Host video HBP current configuration register. + byte_offset: 332 + fieldset: VHBPCCR + - name: VLCCR + description: DSI Host video line current configuration register. + byte_offset: 336 + fieldset: VLCCR + - name: VVSACCR + description: DSI Host video VSA current configuration register. + byte_offset: 340 + fieldset: VVSACCR + - name: VVBPCCR + description: DSI Host video VBP current configuration register. + byte_offset: 344 + fieldset: VVBPCCR + - name: VVFPCCR + description: DSI Host video VFP current configuration register. + byte_offset: 348 + fieldset: VVFPCCR + - name: VVACCR + description: DSI Host video VA current configuration register. + byte_offset: 352 + fieldset: VVACCR + - name: FBSR + description: DSI Host FIFO and buffer status register. + byte_offset: 360 + fieldset: FBSR + - name: WCFGR + description: DSI Wrapper configuration register. + byte_offset: 1024 + fieldset: WCFGR + - name: WCR + description: DSI Wrapper control register. + byte_offset: 1028 + fieldset: WCR + - name: WIER + description: DSI Wrapper interrupt enable register. + byte_offset: 1032 + fieldset: WIER + - name: WISR + description: DSI Wrapper interrupt and status register. + byte_offset: 1036 + fieldset: WISR + - name: WIFCR + description: DSI Wrapper interrupt flag clear register. + byte_offset: 1040 + fieldset: WIFCR + - name: WPCR0 + description: DSI Wrapper PHY configuration register 0. + byte_offset: 1048 + fieldset: WPCR0 + - name: WRPCR + description: DSI Wrapper regulator and PLL control register. + byte_offset: 1072 + fieldset: WRPCR + - name: BCFGR + description: DSI bias configuration register. + byte_offset: 2056 + fieldset: BCFGR + - name: DPCBCR + description: DSI D-PHY clock band control register. + byte_offset: 3076 + fieldset: DPCBCR + - name: DPCSRCR + description: DSI D-PHY clock skew rate control register. + byte_offset: 3124 + fieldset: DPCSRCR + - name: DPDL0BCR + description: DSI D-PHY data lane 0 band control register. + byte_offset: 3184 + fieldset: DPDL0BCR + - name: DPDL0SRCR + description: DSI D-PHY data lane 0 skew rate control register. + byte_offset: 3232 + fieldset: DPDL0SRCR + - name: DPDL1BCR + description: DSI D-PHY data lane 1 band control register. + byte_offset: 3336 + fieldset: DPDL1BCR + - name: DPDL1SRCR + description: DSI D-PHY data lane 1 skew rate control register. + byte_offset: 3384 + fieldset: DPDL1SRCR +fieldset/BCFGR: + description: DSI bias configuration register. + fields: + - name: PWRUP + description: Power-up This bit powers-up the reference bias for the MIPI D-PHY. + bit_offset: 6 + bit_size: 1 +fieldset/CCR: + description: DSI Host clock control register. + fields: + - name: TXECKDIV + description: TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation. + bit_offset: 0 + bit_size: 8 + - name: TOCKDIV + description: Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error. + bit_offset: 8 + bit_size: 8 +fieldset/CLCR: + description: DSI Host clock lane configuration register. + fields: + - name: DPCC + description: D-PHY clock control This bit controls the D-PHY clock state:. + bit_offset: 0 + bit_size: 1 + - name: ACR + description: Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows. + bit_offset: 1 + bit_size: 1 +fieldset/CLTCR: + description: DSI Host clock lane timer configuration register. + fields: + - name: LP2HS_TIME + description: "Low-power to high-speed time This field configures the maximum time that the D-PHY clock lane takes to go from lowâ\x80\x91power to high-speed transmission measured in lane byte clock cycles." + bit_offset: 0 + bit_size: 10 + - name: HS2LP_TIME + description: "High-speed to low-power time This field configures the maximum time that the D-PHY clock lane takes to go from highâ\x80\x91speed to low-power transmission measured in lane byte clock cycles." + bit_offset: 16 + bit_size: 10 +fieldset/CMCR: + description: DSI Host command mode configuration register. + fields: + - name: TEARE + description: Tearing effect acknowledge request enable This bit enables the tearing effect acknowledge request:. + bit_offset: 0 + bit_size: 1 + - name: ARE + description: Acknowledge request enable This bit enables the acknowledge request after each packet transmission:. + bit_offset: 1 + bit_size: 1 + - name: GSW0TX + description: Generic short write zero parameters transmission This bit configures the generic short write packet with zero parameters command transmission type:. + bit_offset: 8 + bit_size: 1 + - name: GSW1TX + description: Generic short write one parameters transmission This bit configures the generic short write packet with one parameters command transmission type:. + bit_offset: 9 + bit_size: 1 + - name: GSW2TX + description: Generic short write two parameters transmission This bit configures the generic short write packet with two parameters command transmission type:. + bit_offset: 10 + bit_size: 1 + - name: GSR0TX + description: Generic short read zero parameters transmission This bit configures the generic short read packet with zero parameters command transmission type:. + bit_offset: 11 + bit_size: 1 + - name: GSR1TX + description: Generic short read one parameters transmission This bit configures the generic short read packet with one parameters command transmission type:. + bit_offset: 12 + bit_size: 1 + - name: GSR2TX + description: Generic short read two parameters transmission This bit configures the generic short read packet with two parameters command transmission type:. + bit_offset: 13 + bit_size: 1 + - name: GLWTX + description: Generic long write transmission This bit configures the generic long write packet command transmission type :. + bit_offset: 14 + bit_size: 1 + - name: DSW0TX + description: DCS short write zero parameter transmission This bit configures the DCS short write packet with zero parameter command transmission type:. + bit_offset: 16 + bit_size: 1 + - name: DSW1TX + description: DCS short read one parameter transmission This bit configures the DCS short read packet with one parameter command transmission type:. + bit_offset: 17 + bit_size: 1 + - name: DSR0TX + description: DCS short read zero parameter transmission This bit configures the DCS short read packet with zero parameter command transmission type:. + bit_offset: 18 + bit_size: 1 + - name: DLWTX + description: DCS long write transmission This bit configures the DCS long write packet command transmission type:. + bit_offset: 19 + bit_size: 1 + - name: MRDPS + description: Maximum read packet size This bit configures the maximum read packet size command transmission type:. + bit_offset: 24 + bit_size: 1 +fieldset/CR: + description: DSI Host control register. + fields: + - name: EN + description: Enable This bit configures the DSI Host in either power-up mode or to reset. + bit_offset: 0 + bit_size: 1 +fieldset/DLTCR: + description: DSI Host data lane timer configuration register. + fields: + - name: LP2HS_TIME + description: Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles. + bit_offset: 0 + bit_size: 10 + - name: HS2LP_TIME + description: High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles. + bit_offset: 16 + bit_size: 10 +fieldset/DLTRCR: + description: DSI Host data lane timer read configuration register. + fields: + - name: MRD_TIME + description: Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress. + bit_offset: 0 + bit_size: 15 +fieldset/DPCBCR: + description: DSI D-PHY clock band control register. + fields: + - name: BC + description: "Band control This field selects the frequency band used by the D-PHY. Others: Reserved." + bit_offset: 3 + bit_size: 5 +fieldset/DPCSRCR: + description: DSI D-PHY clock skew rate control register. + fields: + - name: SRC + description: "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved." + bit_offset: 0 + bit_size: 8 +fieldset/DPDL0BCR: + description: DSI D-PHY data lane 0 band control register. + fields: + - name: BC + description: "Band control This field selects the frequency band used by the D-PHY. Others: Reserved." + bit_offset: 0 + bit_size: 5 +fieldset/DPDL0SRCR: + description: DSI D-PHY data lane 0 skew rate control register. + fields: + - name: SRC + description: "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved." + bit_offset: 0 + bit_size: 8 +fieldset/DPDL1BCR: + description: DSI D-PHY data lane 1 band control register. + fields: + - name: BC + description: "Band control This field selects the frequency band used by the D-PHY. Others: Reserved." + bit_offset: 0 + bit_size: 5 +fieldset/DPDL1SRCR: + description: DSI D-PHY data lane 1 skew rate control register. + fields: + - name: SRC + description: "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved." + bit_offset: 0 + bit_size: 8 +fieldset/FBSR: + description: DSI Host FIFO and buffer status register. + fields: + - name: VCWFE + description: Video mode command write FIFO empty This bit indicates the empty status of the video mode write command FIFO:. + bit_offset: 0 + bit_size: 1 + - name: VCWFF + description: Video mode command write FIFO full This bit indicates the full status of the video mode write command FIFO:. + bit_offset: 1 + bit_size: 1 + - name: VPWFE + description: Video mode payload write FIFO empty This bit indicates the empty status of the video mode write payload FIFO:. + bit_offset: 2 + bit_size: 1 + - name: VPWFF + description: Video mode payload write FIFO full This bit indicates the full status of the video mode write payload FIFO:. + bit_offset: 3 + bit_size: 1 + - name: ACWFE + description: Adapted command mode command write FIFO empty This bit indicates the empty status of the adapted command mode write command FIFO:. + bit_offset: 4 + bit_size: 1 + - name: ACWFF + description: Adapted command mode command write FIFO full This bit indicates the full status of the adapted command mode write command FIFO:. + bit_offset: 5 + bit_size: 1 + - name: APWFE + description: Adapted command mode payload write FIFO empty This bit indicates the empty status of the adapted command mode write payload FIFO:. + bit_offset: 6 + bit_size: 1 + - name: APWFF + description: Adapted command mode payload write FIFO full This bit indicates the full status of the adapted command mode write payload FIFO:. + bit_offset: 7 + bit_size: 1 + - name: VPBE + description: Video mode payload buffer empty This bit indicates the empty status of the video mode payload internal buffer:. + bit_offset: 16 + bit_size: 1 + - name: VPBF + description: Video mode payload buffer full This bit indicates the full status of the video mode payload internal buffer:. + bit_offset: 17 + bit_size: 1 + - name: ACBE + description: Adapted command mode command buffer empty This bit indicates the empty status of the adapted command mode command internal buffer:. + bit_offset: 20 + bit_size: 1 + - name: ACBF + description: Adapted command mode command buffer full This bit indicates the full status of the adapted command mode command internal buffer:. + bit_offset: 21 + bit_size: 1 + - name: APBE + description: Adapted command mode payload buffer empty This bit indicates the empty status of the adapted command mode payload internal buffer:. + bit_offset: 22 + bit_size: 1 + - name: APBF + description: Adapted command mode payload buffer full This bit indicates the full status of the adapted command mode payload internal buffer:. + bit_offset: 23 + bit_size: 1 +fieldset/FIR0: + description: DSI Host force interrupt register 0. + fields: + - name: FAE0 + description: Force acknowledge error 0 Writing one to this bit forces an acknowledge error 0. + bit_offset: 0 + bit_size: 1 + - name: FAE1 + description: Force acknowledge error 1 Writing one to this bit forces an acknowledge error 1. + bit_offset: 1 + bit_size: 1 + - name: FAE2 + description: Force acknowledge error 2 Writing one to this bit forces an acknowledge error 2. + bit_offset: 2 + bit_size: 1 + - name: FAE3 + description: Force acknowledge error 3 Writing one to this bit forces an acknowledge error 3. + bit_offset: 3 + bit_size: 1 + - name: FAE4 + description: Force acknowledge error 4 Writing one to this bit forces an acknowledge error 4. + bit_offset: 4 + bit_size: 1 + - name: FAE5 + description: Force acknowledge error 5 Writing one to this bit forces an acknowledge error 5. + bit_offset: 5 + bit_size: 1 + - name: FAE6 + description: Force acknowledge error 6 Writing one to this bit forces an acknowledge error 6. + bit_offset: 6 + bit_size: 1 + - name: FAE7 + description: Force acknowledge error 7 Writing one to this bit forces an acknowledge error 7. + bit_offset: 7 + bit_size: 1 + - name: FAE8 + description: Force acknowledge error 8 Writing one to this bit forces an acknowledge error 8. + bit_offset: 8 + bit_size: 1 + - name: FAE9 + description: Force acknowledge error 9 Writing one to this bit forces an acknowledge error 9. + bit_offset: 9 + bit_size: 1 + - name: FAE10 + description: Force acknowledge error 10 Writing one to this bit forces an acknowledge error 10. + bit_offset: 10 + bit_size: 1 + - name: FAE11 + description: Force acknowledge error 11 Writing one to this bit forces an acknowledge error 11. + bit_offset: 11 + bit_size: 1 + - name: FAE12 + description: Force acknowledge error 12 Writing one to this bit forces an acknowledge error 12. + bit_offset: 12 + bit_size: 1 + - name: FAE13 + description: Force acknowledge error 13 Writing one to this bit forces an acknowledge error 13. + bit_offset: 13 + bit_size: 1 + - name: FAE14 + description: Force acknowledge error 14 Writing one to this bit forces an acknowledge error 14. + bit_offset: 14 + bit_size: 1 + - name: FAE15 + description: Force acknowledge error 15 Writing one to this bit forces an acknowledge error 15. + bit_offset: 15 + bit_size: 1 + - name: FPE0 + description: Force PHY error 0 Writing one to this bit forces a PHY error 0. + bit_offset: 16 + bit_size: 1 + - name: FPE1 + description: Force PHY error 1 Writing one to this bit forces a PHY error 1. + bit_offset: 17 + bit_size: 1 + - name: FPE2 + description: Force PHY error 2 Writing one to this bit forces a PHY error 2. + bit_offset: 18 + bit_size: 1 + - name: FPE3 + description: Force PHY error 3 Writing one to this bit forces a PHY error 3. + bit_offset: 19 + bit_size: 1 + - name: FPE4 + description: Force PHY error 4 Writing one to this bit forces a PHY error 4. + bit_offset: 20 + bit_size: 1 +fieldset/FIR1: + description: DSI Host force interrupt register 1. + fields: + - name: FTOHSTX + description: Force timeout high-speed transmission Writing one to this bit forces a timeout high-speed transmission. + bit_offset: 0 + bit_size: 1 + - name: FTOLPRX + description: Force timeout low-power reception Writing one to this bit forces a timeout low-power reception. + bit_offset: 1 + bit_size: 1 + - name: FECCSE + description: Force ECC single-bit error Writing one to this bit forces a ECC single-bit error. + bit_offset: 2 + bit_size: 1 + - name: FECCME + description: Force ECC multi-bit error Writing one to this bit forces a ECC multi-bit error. + bit_offset: 3 + bit_size: 1 + - name: FCRCE + description: Force CRC error Writing one to this bit forces a CRC error. + bit_offset: 4 + bit_size: 1 + - name: FPSE + description: Force packet size error Writing one to this bit forces a packet size error. + bit_offset: 5 + bit_size: 1 + - name: FEOTPE + description: Force EoTp error Writing one to this bit forces a EoTp error. + bit_offset: 6 + bit_size: 1 + - name: FLPWRE + description: Force LTDC payload write error Writing one to this bit forces a LTDC payload write error. + bit_offset: 7 + bit_size: 1 + - name: FGCWRE + description: Force generic command write error Writing one to this bit forces a generic command write error. + bit_offset: 8 + bit_size: 1 + - name: FGPWRE + description: Force generic payload write error Writing one to this bit forces a generic payload write error. + bit_offset: 9 + bit_size: 1 + - name: FGPTXE + description: Force generic payload transmit error Writing one to this bit forces a generic payload transmit error. + bit_offset: 10 + bit_size: 1 + - name: FGPRDE + description: Force generic payload read error Writing one to this bit forces a generic payload read error. + bit_offset: 11 + bit_size: 1 + - name: FGPRXE + description: Force generic payload receive error Writing one to this bit forces a generic payload receive error. + bit_offset: 12 + bit_size: 1 + - name: FPBUE + description: Force payload buffer underflow error Writing one to this bit forces a payload undrflow error. + bit_offset: 19 + bit_size: 1 +fieldset/GHCR: + description: DSI Host generic header configuration register. + fields: + - name: DT + description: Type This field configures the packet data type of the header packet. + bit_offset: 0 + bit_size: 6 + - name: VCID + description: Channel This field configures the virtual channel ID of the header packet. + bit_offset: 6 + bit_size: 2 + - name: WCLSB + description: WordCount LSB This field configures the less significant byte of the header packet word count for long packets, or data 0 for short packets. + bit_offset: 8 + bit_size: 8 + - name: WCMSB + description: WordCount MSB This field configures the most significant byte of the header packet's word count for long packets, or data 1 for short packets. + bit_offset: 16 + bit_size: 8 +fieldset/GPDR: + description: DSI Host generic payload data register. + fields: + - name: DATA1 + description: Payload byte 1 This field indicates the byte 1 of the packet payload. + bit_offset: 0 + bit_size: 8 + - name: DATA2 + description: Payload byte 2 This field indicates the byte 2 of the packet payload. + bit_offset: 8 + bit_size: 8 + - name: DATA3 + description: Payload byte 3 This field indicates the byte 3 of the packet payload. + bit_offset: 16 + bit_size: 8 + - name: DATA4 + description: Payload byte 4 This field indicates the byte 4 of the packet payload. + bit_offset: 24 + bit_size: 8 +fieldset/GPSR: + description: DSI Host generic packet status register. + fields: + - name: CMDFE + description: Command FIFO empty This bit indicates the empty status of the generic command FIFO:. + bit_offset: 0 + bit_size: 1 + - name: CMDFF + description: Command FIFO full This bit indicates the full status of the generic command FIFO:. + bit_offset: 1 + bit_size: 1 + - name: PWRFE + description: Payload write FIFO empty This bit indicates the empty status of the generic write payload FIFO:. + bit_offset: 2 + bit_size: 1 + - name: PWRFF + description: Payload write FIFO full This bit indicates the full status of the generic write payload FIFO:. + bit_offset: 3 + bit_size: 1 + - name: PRDFE + description: Payload read FIFO empty This bit indicates the empty status of the generic read payload FIFO:. + bit_offset: 4 + bit_size: 1 + - name: PRDFF + description: Payload read FIFO full This bit indicates the full status of the generic read payload FIFO:. + bit_offset: 5 + bit_size: 1 + - name: RCB + description: Read command busy This bit is set when a read command is issued and cleared when the entire response is stored in the FIFO:. + bit_offset: 6 + bit_size: 1 + - name: CMDBE + description: Command buffer empty This bit indicates the empty status of the generic payload internal buffer:. + bit_offset: 16 + bit_size: 1 + - name: CMDBF + description: Command buffer full This bit indicates the full status of the generic command internal buffer:. + bit_offset: 17 + bit_size: 1 + - name: PBE + description: Payload buffer empty This bit indicates the empty status of the generic payload internal buffer:. + bit_offset: 18 + bit_size: 1 + - name: PBF + description: Payload buffer full This bit indicates the full status of the generic payload internal buffer:. + bit_offset: 19 + bit_size: 1 +fieldset/GVCIDR: + description: DSI Host generic VCID register. + fields: + - name: VCIDRX + description: Virtual channel ID for reception This field indicates the generic interface read-back virtual channel identification. + bit_offset: 0 + bit_size: 2 + - name: VCIDTX + description: Virtual channel ID for transmission This field indicates the generic interface virtual channel identification where the generic packet is automatically generated and transmitted. + bit_offset: 16 + bit_size: 2 +fieldset/IER0: + description: DSI Host interrupt enable register 0. + fields: + - name: AE0IE + description: Acknowledge error 0 interrupt enable This bit enables the interrupt generation on acknowledge error 0. + bit_offset: 0 + bit_size: 1 + - name: AE1IE + description: Acknowledge error 1 interrupt enable This bit enables the interrupt generation on acknowledge error 1. + bit_offset: 1 + bit_size: 1 + - name: AE2IE + description: Acknowledge error 2 interrupt enable This bit enables the interrupt generation on acknowledge error 2. + bit_offset: 2 + bit_size: 1 + - name: AE3IE + description: Acknowledge error 3 interrupt enable This bit enables the interrupt generation on acknowledge error 3. + bit_offset: 3 + bit_size: 1 + - name: AE4IE + description: Acknowledge error 4 interrupt enable This bit enables the interrupt generation on acknowledge error 4. + bit_offset: 4 + bit_size: 1 + - name: AE5IE + description: Acknowledge error 5 interrupt enable This bit enables the interrupt generation on acknowledge error 5. + bit_offset: 5 + bit_size: 1 + - name: AE6IE + description: Acknowledge error 6 interrupt enable This bit enables the interrupt generation on acknowledge error 6. + bit_offset: 6 + bit_size: 1 + - name: AE7IE + description: Acknowledge error 7 interrupt enable This bit enables the interrupt generation on acknowledge error 7. + bit_offset: 7 + bit_size: 1 + - name: AE8IE + description: Acknowledge error 8 interrupt enable This bit enables the interrupt generation on acknowledge error 8. + bit_offset: 8 + bit_size: 1 + - name: AE9IE + description: Acknowledge error 9 interrupt enable This bit enables the interrupt generation on acknowledge error 9. + bit_offset: 9 + bit_size: 1 + - name: AE10IE + description: Acknowledge error 10 interrupt enable This bit enables the interrupt generation on acknowledge error 10. + bit_offset: 10 + bit_size: 1 + - name: AE11IE + description: Acknowledge error 11 interrupt enable This bit enables the interrupt generation on acknowledge error 11. + bit_offset: 11 + bit_size: 1 + - name: AE12IE + description: Acknowledge error 12 interrupt enable This bit enables the interrupt generation on acknowledge error 12. + bit_offset: 12 + bit_size: 1 + - name: AE13IE + description: Acknowledge error 13 interrupt enable This bit enables the interrupt generation on acknowledge error 13. + bit_offset: 13 + bit_size: 1 + - name: AE14IE + description: Acknowledge error 14 interrupt enable This bit enables the interrupt generation on acknowledge error 14. + bit_offset: 14 + bit_size: 1 + - name: AE15IE + description: Acknowledge error 15 interrupt enable This bit enables the interrupt generation on acknowledge error 15. + bit_offset: 15 + bit_size: 1 + - name: PE0IE + description: PHY error 0 interrupt enable This bit enables the interrupt generation on PHY error 0. + bit_offset: 16 + bit_size: 1 + - name: PE1IE + description: PHY error 1 interrupt enable This bit enables the interrupt generation on PHY error 1. + bit_offset: 17 + bit_size: 1 + - name: PE2IE + description: PHY error 2 interrupt enable This bit enables the interrupt generation on PHY error 2. + bit_offset: 18 + bit_size: 1 + - name: PE3IE + description: PHY error 3 interrupt enable This bit enables the interrupt generation on PHY error 4. + bit_offset: 19 + bit_size: 1 + - name: PE4IE + description: PHY error 4 interrupt enable This bit enables the interrupt generation on PHY error 4. + bit_offset: 20 + bit_size: 1 +fieldset/IER1: + description: DSI Host interrupt enable register 1. + fields: + - name: TOHSTXIE + description: Timeout high-speed transmission interrupt enable This bit enables the interrupt generation on timeout high-speed transmission. + bit_offset: 0 + bit_size: 1 + - name: TOLPRXIE + description: Timeout low-power reception interrupt enable This bit enables the interrupt generation on timeout low-power reception. + bit_offset: 1 + bit_size: 1 + - name: ECCSEIE + description: ECC single-bit error interrupt enable This bit enables the interrupt generation on ECC single-bit error. + bit_offset: 2 + bit_size: 1 + - name: ECCMEIE + description: ECC multi-bit error interrupt enable This bit enables the interrupt generation on ECC multi-bit error. + bit_offset: 3 + bit_size: 1 + - name: CRCEIE + description: CRC error interrupt enable This bit enables the interrupt generation on CRC error. + bit_offset: 4 + bit_size: 1 + - name: PSEIE + description: Packet size error interrupt enable This bit enables the interrupt generation on packet size error. + bit_offset: 5 + bit_size: 1 + - name: EOTPEIE + description: EoTp error interrupt enable This bit enables the interrupt generation on EoTp error. + bit_offset: 6 + bit_size: 1 + - name: LPWREIE + description: LTDC payload write error interrupt enable This bit enables the interrupt generation on LTDC payload write error. + bit_offset: 7 + bit_size: 1 + - name: GCWREIE + description: Generic command write error interrupt enable This bit enables the interrupt generation on generic command write error. + bit_offset: 8 + bit_size: 1 + - name: GPWREIE + description: Generic payload write error interrupt enable This bit enables the interrupt generation on generic payload write error. + bit_offset: 9 + bit_size: 1 + - name: GPTXEIE + description: Generic payload transmit error interrupt enable This bit enables the interrupt generation on generic payload transmit error. + bit_offset: 10 + bit_size: 1 + - name: GPRDEIE + description: Generic payload read error interrupt enable This bit enables the interrupt generation on generic payload read error. + bit_offset: 11 + bit_size: 1 + - name: GPRXEIE + description: Generic payload receive error interrupt enable This bit enables the interrupt generation on generic payload receive error. + bit_offset: 12 + bit_size: 1 + - name: PBUEIE + description: Payload buffer underflow error interrupt enable This bit enables the interrupt generation on payload buffer underflow error. + bit_offset: 19 + bit_size: 1 +fieldset/ISR0: + description: DSI Host interrupt and status register 0. + fields: + - name: AE0 + description: Acknowledge error 0 This bit retrieves the SoT error from the acknowledge error report. + bit_offset: 0 + bit_size: 1 + - name: AE1 + description: Acknowledge error 1 This bit retrieves the SoT sync error from the acknowledge error report. + bit_offset: 1 + bit_size: 1 + - name: AE2 + description: Acknowledge error 2 This bit retrieves the EoT sync error from the acknowledge error report. + bit_offset: 2 + bit_size: 1 + - name: AE3 + description: Acknowledge error 3 This bit retrieves the escape mode entry command error from the acknowledge error report. + bit_offset: 3 + bit_size: 1 + - name: AE4 + description: Acknowledge error 4 This bit retrieves the LP transmit sync error from the acknowledge error report. + bit_offset: 4 + bit_size: 1 + - name: AE5 + description: Acknowledge error 5 This bit retrieves the peripheral timeout error from the acknowledge error report. + bit_offset: 5 + bit_size: 1 + - name: AE6 + description: Acknowledge error 6 This bit retrieves the false control error from the acknowledge error report. + bit_offset: 6 + bit_size: 1 + - name: AE7 + description: Acknowledge error 7 This bit retrieves the reserved (specific to the device) from the acknowledge error report. + bit_offset: 7 + bit_size: 1 + - name: AE8 + description: Acknowledge error 8 This bit retrieves the ECC error, single-bit (detected and corrected) from the acknowledge error report. + bit_offset: 8 + bit_size: 1 + - name: AE9 + description: Acknowledge error 9 This bit retrieves the ECC error, multi-bit (detected, not corrected) from the acknowledge error report. + bit_offset: 9 + bit_size: 1 + - name: AE10 + description: Acknowledge error 10 This bit retrieves the checksum error (long packet only) from the acknowledge error report. + bit_offset: 10 + bit_size: 1 + - name: AE11 + description: Acknowledge error 11 This bit retrieves the not recognized DSI data type from the acknowledge error report. + bit_offset: 11 + bit_size: 1 + - name: AE12 + description: Acknowledge error 12 This bit retrieves the DSI VC ID Invalid from the acknowledge error report. + bit_offset: 12 + bit_size: 1 + - name: AE13 + description: Acknowledge error 13 This bit retrieves the invalid transmission length from the acknowledge error report. + bit_offset: 13 + bit_size: 1 + - name: AE14 + description: Acknowledge error 14 This bit retrieves the reserved (specific to the device) from the acknowledge error report. + bit_offset: 14 + bit_size: 1 + - name: AE15 + description: Acknowledge error 15 This bit retrieves the DSI protocol violation from the acknowledge error report. + bit_offset: 15 + bit_size: 1 + - name: PE0 + description: PHY error 0 This bit indicates the ErrEsc escape entry error from lane 0. + bit_offset: 16 + bit_size: 1 + - name: PE1 + description: PHY error 1 This bit indicates the ErrSyncEsc low-power transmission synchronization error from lane 0. + bit_offset: 17 + bit_size: 1 + - name: PE2 + description: PHY error 2 This bit indicates the ErrControl error from lane 0. + bit_offset: 18 + bit_size: 1 + - name: PE3 + description: PHY error 3 This bit indicates the LP0 contention error ErrContentionLP0 from lane 0. + bit_offset: 19 + bit_size: 1 + - name: PE4 + description: PHY error 4 This bit indicates the LP1 contention error ErrContentionLP1 from lane 0. + bit_offset: 20 + bit_size: 1 +fieldset/ISR1: + description: DSI Host interrupt and status register 1. + fields: + - name: TOHSTX + description: Timeout high-speed transmission This bit indicates that the high-speed transmission timeout counter reached the end and contention is detected. + bit_offset: 0 + bit_size: 1 + - name: TOLPRX + description: Timeout low-power reception This bit indicates that the low-power reception timeout counter reached the end and contention is detected. + bit_offset: 1 + bit_size: 1 + - name: ECCSE + description: ECC single-bit error This bit indicates that the ECC single error is detected and corrected in a received packet. + bit_offset: 2 + bit_size: 1 + - name: ECCME + description: ECC multi-bit error This bit indicates that the ECC multiple error is detected in a received packet. + bit_offset: 3 + bit_size: 1 + - name: CRCE + description: CRC error This bit indicates that the CRC error is detected in the received packet payload. + bit_offset: 4 + bit_size: 1 + - name: PSE + description: Packet size error This bit indicates that the packet size error is detected during the packet reception. + bit_offset: 5 + bit_size: 1 + - name: EOTPE + description: EoTp error This bit indicates that the EoTp packet is not received at the end of the incoming peripheral transmission. + bit_offset: 6 + bit_size: 1 + - name: LPWRE + description: LTDC payload write error This bit indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted. + bit_offset: 7 + bit_size: 1 + - name: GCWRE + description: Generic command write error This bit indicates that the system tried to write a command through the generic interface and the FIFO is full. Therefore, the command is not written. + bit_offset: 8 + bit_size: 1 + - name: GPWRE + description: Generic payload write error This bit indicates that the system tried to write a payload data through the generic interface and the FIFO is full. Therefore, the payload is not written. + bit_offset: 9 + bit_size: 1 + - name: GPTXE + description: Generic payload transmit error This bit indicates that during a generic interface packet build, the payload FIFO becomes empty and corrupt data is sent. + bit_offset: 10 + bit_size: 1 + - name: GPRDE + description: Generic payload read error This bit indicates that during a DCS read data, the payload FIFO becomes empty and the data sent to the interface is corrupted. + bit_offset: 11 + bit_size: 1 + - name: GPRXE + description: Generic payload receive error This bit indicates that during a generic interface packet read back, the payload FIFO becomes full and the received data is corrupted. + bit_offset: 12 + bit_size: 1 + - name: PBUE + description: Payload buffer underflow error This bit indicates that underflow has occurred when reading payload to build DSI packet for video mode. + bit_offset: 19 + bit_size: 1 +fieldset/LCCCR: + description: DSI Host LTDC current color coding register. + fields: + - name: COLC + description: "Color coding This field returns the current LTDC interface color coding. 0110-1111: reserved If LTDC interface in command mode is chosen and currently works in the command mode (CMDM=1), then 0110-1111: 24-bit." + bit_offset: 0 + bit_size: 4 + - name: LPE + description: Loosely packed enable This bit returns the current state of the loosely packed variant to 18-bit configurations. + bit_offset: 8 + bit_size: 1 +fieldset/LCCR: + description: DSI Host LTDC command configuration register. + fields: + - name: CMDSIZE + description: Command size This field configures the maximum allowed size for an LTDC write memory command, measured in pixels. Automatic partitioning of data obtained from LTDC is permanently enabled. + bit_offset: 0 + bit_size: 16 +fieldset/LCOLCR: + description: DSI Host LTDC color coding register. + fields: + - name: COLC + description: "Color coding This field configures the DPI color coding. Others: Reserved." + bit_offset: 0 + bit_size: 4 + - name: LPE + description: Loosely packet enable This bit enables the loosely packed variant to 18-bit configuration. + bit_offset: 8 + bit_size: 1 +fieldset/LCVCIDR: + description: DSI Host LTDC current VCID register. + fields: + - name: VCID + description: Virtual channel ID This field returns the virtual channel ID for the LTDC interface. + bit_offset: 0 + bit_size: 2 +fieldset/LPCR: + description: DSI Host LTDC polarity configuration register. + fields: + - name: DEP + description: Data enable polarity This bit configures the polarity of data enable pin. + bit_offset: 0 + bit_size: 1 + - name: VSP + description: VSYNC polarity This bit configures the polarity of VSYNC pin. + bit_offset: 1 + bit_size: 1 + - name: HSP + description: HSYNC polarity This bit configures the polarity of HSYNC pin. + bit_offset: 2 + bit_size: 1 +fieldset/LPMCCR: + description: DSI Host low-power mode current configuration register. + fields: + - name: VLPSIZE + description: VACT largest packet size This field returns the current size, in bytes, of the largest packet that can fit in a line during VACT regions, for the transmission of commands in low-power mode. + bit_offset: 0 + bit_size: 8 + - name: LPSIZE + description: Largest packet size This field is returns the current size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions, for the transmission of commands in low-power mode. + bit_offset: 16 + bit_size: 8 +fieldset/LPMCR: + description: DSI Host low-power mode configuration register. + fields: + - name: VLPSIZE + description: VACT largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VACT regions. + bit_offset: 0 + bit_size: 8 + - name: LPSIZE + description: Largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions. + bit_offset: 16 + bit_size: 8 +fieldset/LVCIDR: + description: DSI Host LTDC VCID register. + fields: + - name: VCID + description: Virtual channel ID These bits configure the virtual channel ID for the LTDC interface traffic. + bit_offset: 0 + bit_size: 2 +fieldset/MCR: + description: DSI Host mode configuration register. + fields: + - name: CMDM + description: Command mode This bit configures the DSI Host in either video or command mode. + bit_offset: 0 + bit_size: 1 +fieldset/PCONFR: + description: DSI Host PHY configuration register. + fields: + - name: NL + description: "Number of lanes This field configures the number of active data lanes: Others: Reserved." + bit_offset: 0 + bit_size: 2 + - name: SW_TIME + description: Stop wait time This field configures the minimum wait period to request a high-speed transmission after the Stop state. + bit_offset: 8 + bit_size: 8 +fieldset/PCR: + description: DSI Host protocol configuration register. + fields: + - name: ETTXE + description: EoTp transmission enable This bit enables the EoTP transmission. + bit_offset: 0 + bit_size: 1 + - name: ETRXE + description: EoTp reception enable This bit enables the EoTp reception. + bit_offset: 1 + bit_size: 1 + - name: BTAE + description: Bus-turn-around enable This bit enables the bus-turn-around (BTA) request. + bit_offset: 2 + bit_size: 1 + - name: ECCRXE + description: ECC reception enable This bit enables the ECC reception, error correction and reporting. + bit_offset: 3 + bit_size: 1 + - name: CRCRXE + description: CRC reception enable This bit enables the CRC reception and error reporting. + bit_offset: 4 + bit_size: 1 + - name: ETTXLPE + description: EoTp transmission in low-power enable This bit enables the EoTP transmission in low-power. + bit_offset: 5 + bit_size: 1 +fieldset/PCTLR: + description: DSI Host PHY control register. + fields: + - name: DEN + description: Digital enable When set to 0, this bit places the digital section of the D-PHY in the reset state. + bit_offset: 1 + bit_size: 1 + - name: CKE + description: Clock enable This bit enables the D-PHY clock lane module:. + bit_offset: 2 + bit_size: 1 +fieldset/PSR: + description: DSI Host PHY status register. + fields: + - name: PD + description: PHY direction This bit indicates the status of phydirection D-PHY signal. + bit_offset: 1 + bit_size: 1 + - name: PSSC + description: PHY stop state clock lane This bit indicates the status of phystopstateclklane D-PHY signal. + bit_offset: 2 + bit_size: 1 + - name: UANC + description: ULPS active not clock lane This bit indicates the status of ulpsactivenotclklane D-PHY signal. + bit_offset: 3 + bit_size: 1 + - name: PSS0 + description: PHY stop state lane 0 This bit indicates the status of phystopstate0lane D-PHY signal. + bit_offset: 4 + bit_size: 1 + - name: UAN0 + description: ULPS active not lane 1 This bit indicates the status of ulpsactivenot0lane D-PHY signal. + bit_offset: 5 + bit_size: 1 + - name: RUE0 + description: RX ULPS escape lane 0 This bit indicates the status of rxulpsesc0lane D-PHY signal. + bit_offset: 6 + bit_size: 1 + - name: PSS1 + description: PHY stop state lane 1 This bit indicates the status of phystopstate1lane D-PHY signal. + bit_offset: 7 + bit_size: 1 + - name: UAN1 + description: ULPS active not lane 1 This bit indicates the status of ulpsactivenot1lane D-PHY signal. + bit_offset: 8 + bit_size: 1 +fieldset/PTTCR: + description: DSI Host PHY TX triggers configuration register. + fields: + - name: TX_TRIG + description: Transmission trigger Escape mode transmit trigger 0-3. Only one bit of TX_TRIG is asserted at any given time. + bit_offset: 0 + bit_size: 4 +fieldset/PUCR: + description: DSI Host PHY ULPS control register. + fields: + - name: URCL + description: ULPS request on clock lane ULPS mode request on clock lane. + bit_offset: 0 + bit_size: 1 + - name: UECL + description: ULPS exit on clock lane ULPS mode exit on clock lane. + bit_offset: 1 + bit_size: 1 + - name: URDL + description: ULPS request on data lane ULPS mode request on all active data lanes. + bit_offset: 2 + bit_size: 1 + - name: UEDL + description: ULPS exit on data lane ULPS mode exit on all active data lanes. + bit_offset: 3 + bit_size: 1 +fieldset/TCCR0: + description: DSI Host timeout counter configuration register 0. + fields: + - name: LPRX_TOCNT + description: Low-power reception timeout counter This field configures the timeout counter that triggers a low-power reception timeout contention detection (measured in TOCKDIV cycles). + bit_offset: 0 + bit_size: 16 + - name: HSTX_TOCNT + description: "High-speed transmission timeout counter This field configures the timeout counter that triggers a high-speed transmission timeout contention detection (measured in TOCKDIV cycles). If using the non-burst mode and there is no enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link returns the low-power state once per frame, then configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV â\x89¥ the time of one FRAME data transmission * (1 + 10%) In burst mode, RGB pixel packets are time-compressed, leaving more time during a scan line. Therefore, if in burst mode and there is enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link can return low-power mode and back in this time interval to save power. For this, configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV â\x89¥ the time of one LINE data transmission * (1 + 10%)." + bit_offset: 16 + bit_size: 16 +fieldset/TCCR1: + description: DSI Host timeout counter configuration register 1. + fields: + - name: HSRD_TOCNT + description: High-speed read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a high-speed read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR2: + description: DSI Host timeout counter configuration register 2. + fields: + - name: LPRD_TOCNT + description: Low-power read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR3: + description: DSI Host timeout counter configuration register 3. + fields: + - name: HSWR_TOCNT + description: High-speed write timeout counter This field sets a period for which the DSI Host keeps the link inactive after sending a high-speed write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + bit_offset: 0 + bit_size: 16 + - name: PM + description: "Presp mode When set to 1, this bit ensures that the peripheral response timeout caused by HSWR_TOCNT is used only once per LTDC frame in command mode, when both the following conditions are met: dpivsync_edpiwms has risen and fallen. Packets originated from LTDC in command mode have been transmitted and its FIFO is empty again. In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is traffic from generic interface ready to be sent, making it return to stop state. When it does so, PRESP_TO counter is activated and only when it finishes does the controller send any other traffic that is ready." + bit_offset: 24 + bit_size: 1 +fieldset/TCCR4: + description: DSI Host timeout counter configuration register 4. + fields: + - name: LPWR_TOCNT + description: Low-power write timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR5: + description: DSI Host timeout counter configuration register 5. + fields: + - name: BTA_TOCNT + description: "Bus-turn-around timeout counter This field sets a period for which the DSI Host keeps the link still, after completing a bus-turn-around. This period is measured in cycles of lanebyteclk. The counting starts when the Dâ\x80\x91PHY enters the Stop state and causes no interrupts." + bit_offset: 0 + bit_size: 16 +fieldset/VCCCR: + description: DSI Host video chunks current configuration register. + fields: + - name: NUMC + description: Number of chunks This field returns the number of chunks being transmitted during a line period. + bit_offset: 0 + bit_size: 13 +fieldset/VCCR: + description: DSI Host video chunks configuration register. + fields: + - name: NUMC + description: Number of chunks This register configures the number of chunks to be transmitted during a line period (a chunk consists of a video packet and a null packet). If set to 0 or 1, the video line is transmitted in a single packet. If set to 1, the packet is part of a chunk, so a null packet follows it if NPSIZE > 0. Otherwise, multiple chunks are used to transmit each video line. + bit_offset: 0 + bit_size: 13 +fieldset/VHBPCCR: + description: DSI Host video HBP current configuration register. + fields: + - name: HBP + description: Horizontal back-porch duration This field returns the horizontal back-porch period in lane byte clock cycles. + bit_offset: 0 + bit_size: 12 +fieldset/VHBPCR: + description: DSI Host video HBP configuration register. + fields: + - name: HBP + description: Horizontal back-porch duration This fields configures the horizontal back-porch period in lane byte clock cycles. + bit_offset: 0 + bit_size: 12 +fieldset/VHSACCR: + description: DSI Host video HSA current configuration register. + fields: + - name: HSA + description: Horizontal synchronism active duration This fields returns the horizontal synchronism active period in lane byte clock cycles. + bit_offset: 0 + bit_size: 12 +fieldset/VHSACR: + description: DSI Host video HSA configuration register. + fields: + - name: HSA + description: Horizontal synchronism active duration This fields configures the horizontal synchronism active period in lane byte clock cycles. + bit_offset: 0 + bit_size: 12 +fieldset/VLCCR: + description: DSI Host video line current configuration register. + fields: + - name: HLINE + description: Horizontal line duration This field returns the current total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles. + bit_offset: 0 + bit_size: 15 +fieldset/VLCR: + description: DSI Host video line configuration register. + fields: + - name: HLINE + description: Horizontal line duration This fields configures the total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles. + bit_offset: 0 + bit_size: 15 +fieldset/VMCCR: + description: DSI Host video mode current configuration register. + fields: + - name: VMT + description: "Video mode type This field returns the current video mode transmission type: 1x: Burst mode." + bit_offset: 0 + bit_size: 2 + - name: LPVSAE + description: Low-power vertical sync time enable This bit returns the current state of return to low-power inside the vertical sync time (VSA) period when timing allows. + bit_offset: 2 + bit_size: 1 + - name: LPVBPE + description: Low-power vertical back-porch enable This bit returns the current state of return to low-power inside the vertical back-porch (VBP) period when timing allows. + bit_offset: 3 + bit_size: 1 + - name: LPVFPE + description: Low-power vertical front-porch enable This bit returns the current state of return to low-power inside the vertical front-porch (VFP) period when timing allows. + bit_offset: 4 + bit_size: 1 + - name: LPVAE + description: Low-power vertical active enable This bit returns the current state of return to low-power inside the vertical active (VACT) period when timing allows. + bit_offset: 5 + bit_size: 1 + - name: LPHBPE + description: Low-power horizontal back-porch enable This bit returns the current state of return to low-power inside the horizontal back-porch (HBP) period when timing allows. + bit_offset: 6 + bit_size: 1 + - name: LPHFE + description: Low-power horizontal front-porch enable This bit returns the current state of return to low-power inside the horizontal front-porch (HFP) period when timing allows. + bit_offset: 7 + bit_size: 1 + - name: FBTAAE + description: Frame BTA acknowledge enable This bit returns the current state of request for an acknowledge response at the end of a frame. + bit_offset: 8 + bit_size: 1 + - name: LPCE + description: Low-power command enable This bit returns the current command transmission state in low-power mode. + bit_offset: 9 + bit_size: 1 +fieldset/VMCR: + description: DSI Host video mode configuration register. + fields: + - name: VMT + description: "Video mode type This field configures the video mode transmission type : 1x: Burst mode." + bit_offset: 0 + bit_size: 2 + - name: LPVSAE + description: Low-power vertical sync active enable This bit enables to return to low-power inside the vertical sync time (VSA) period when timing allows. + bit_offset: 8 + bit_size: 1 + - name: LPVBPE + description: Low-power vertical back-porch enable This bit enables to return to low-power inside the vertical back-porch (VBP) period when timing allows. + bit_offset: 9 + bit_size: 1 + - name: LPVFPE + description: Low-power vertical front-porch enable This bit enables to return to low-power inside the vertical front-porch (VFP) period when timing allows. + bit_offset: 10 + bit_size: 1 + - name: LPVAE + description: Low-power vertical active enable This bit enables to return to low-power inside the vertical active (VACT) period when timing allows. + bit_offset: 11 + bit_size: 1 + - name: LPHBPE + description: Low-power horizontal back-porch enable This bit enables the return to low-power inside the horizontal back-porch (HBP) period when timing allows. + bit_offset: 12 + bit_size: 1 + - name: LPHFPE + description: Low-power horizontal front-porch enable This bit enables the return to low-power inside the horizontal front-porch (HFP) period when timing allows. + bit_offset: 13 + bit_size: 1 + - name: FBTAAE + description: Frame bus-turn-around acknowledge enable This bit enables the request for an acknowledge response at the end of a frame. + bit_offset: 14 + bit_size: 1 + - name: LPCE + description: Low-power command enable This bit enables the command transmission only in low-power mode. + bit_offset: 15 + bit_size: 1 + - name: PGE + description: Pattern generator enable This bit enables the video mode pattern generator. + bit_offset: 16 + bit_size: 1 + - name: PGM + description: Pattern generator mode This bit configures the pattern generator mode. + bit_offset: 20 + bit_size: 1 + - name: PGO + description: Pattern generator orientation This bit configures the color bar orientation. + bit_offset: 24 + bit_size: 1 +fieldset/VNPCCR: + description: DSI Host video null packet current configuration register. + fields: + - name: NPSIZE + description: Null packet size This field returns the number of bytes inside a null packet. + bit_offset: 0 + bit_size: 13 +fieldset/VNPCR: + description: DSI Host video null packet configuration register. + fields: + - name: NPSIZE + description: Null packet size This field configures the number of bytes inside a null packet. Setting to 0 disables the null packets. + bit_offset: 0 + bit_size: 13 +fieldset/VPCCR: + description: DSI Host video packet current configuration register. + fields: + - name: VPSIZE + description: Video packet size This field returns the number of pixels in a single video packet. + bit_offset: 0 + bit_size: 14 +fieldset/VPCR: + description: DSI Host video packet configuration register. + fields: + - name: VPSIZE + description: Video packet size This field configures the number of pixels in a single video packet. For 18-bit not loosely packed data types, this number must be a multiple of 4. For YCbCr data types, it must be a multiple of 2 as described in the DSI specification. + bit_offset: 0 + bit_size: 14 +fieldset/VR: + description: DSI Host version register. + fields: + - name: VERSION + description: Version of the DSI Host This read-only register contains the version of the DSI Host. + bit_offset: 0 + bit_size: 32 +fieldset/VSCR: + description: DSI Host video shadow control register. + fields: + - name: EN + description: Enable When set to 1, DSI Host LTDC interface receives the active configuration from the auxiliary registers. When this bit is set along with the UR bit, the auxiliary registers are automatically updated. + bit_offset: 0 + bit_size: 1 + - name: UR + description: Update register When set to 1, the LTDC registers are copied to the auxiliary registers. After copying, this bit is auto cleared. + bit_offset: 8 + bit_size: 1 +fieldset/VVACCR: + description: DSI Host video VA current configuration register. + fields: + - name: VA + description: Vertical active duration This field returns the current vertical active period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 14 +fieldset/VVACR: + description: DSI Host video VA configuration register. + fields: + - name: VA + description: Vertical active duration This fields configures the vertical active period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 14 +fieldset/VVBPCCR: + description: DSI Host video VBP current configuration register. + fields: + - name: VBP + description: Vertical back-porch duration This field returns the current vertical back-porch period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 10 +fieldset/VVBPCR: + description: DSI Host video VBP configuration register. + fields: + - name: VBP + description: Vertical back-porch duration This fields configures the vertical back-porch period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 10 +fieldset/VVFPCCR: + description: DSI Host video VFP current configuration register. + fields: + - name: VFP + description: Vertical front-porch duration This field returns the current vertical front-porch period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 10 +fieldset/VVFPCR: + description: DSI Host video VFP configuration register. + fields: + - name: VFP + description: Vertical front-porch duration This fields configures the vertical front-porch period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 10 +fieldset/VVSACCR: + description: DSI Host video VSA current configuration register. + fields: + - name: VSA + description: Vertical synchronism active duration This field returns the current vertical synchronism active period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 10 +fieldset/VVSACR: + description: DSI Host video VSA configuration register. + fields: + - name: VSA + description: Vertical synchronism active duration This fields configures the vertical synchronism active period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 10 +fieldset/WCFGR: + description: DSI Wrapper configuration register. + fields: + - name: DSIM + description: DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (CR.EN = 0). + bit_offset: 0 + bit_size: 1 + - name: COLMUX + description: Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.EN = 0). + bit_offset: 1 + bit_size: 3 + - name: TESRC + description: TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0). + bit_offset: 4 + bit_size: 1 + - name: TEPOL + description: TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0). + bit_offset: 5 + bit_size: 1 + - name: AR + description: Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (CR.EN = 0). + bit_offset: 6 + bit_size: 1 + - name: VSPOL + description: VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.EN = 0). + bit_offset: 7 + bit_size: 1 +fieldset/WCR: + description: DSI Wrapper control register. + fields: + - name: COLM + description: Color mode This bit controls the display color mode in video mode. + bit_offset: 0 + bit_size: 1 + - name: SHTDN + description: Shutdown This bit controls the display shutdown in video mode. + bit_offset: 1 + bit_size: 1 + - name: LTDCEN + description: LTDC enable This bit enables the LTDC for a frame transfer in adapted command mode. + bit_offset: 2 + bit_size: 1 + - name: DSIEN + description: DSI enable This bit enables the DSI Wrapper. + bit_offset: 3 + bit_size: 1 +fieldset/WIER: + description: DSI Wrapper interrupt enable register. + fields: + - name: TEIE + description: Tearing effect interrupt enable This bit enables the tearing effect interrupt. + bit_offset: 0 + bit_size: 1 + - name: ERIE + description: End of refresh interrupt enable This bit enables the end of refresh interrupt. + bit_offset: 1 + bit_size: 1 + - name: PLLLIE + description: PLL lock interrupt enable This bit enables the PLL lock interrupt. + bit_offset: 9 + bit_size: 1 + - name: PLLUIE + description: PLL unlock interrupt enable This bit enables the PLL unlock interrupt. + bit_offset: 10 + bit_size: 1 +fieldset/WIFCR: + description: DSI Wrapper interrupt flag clear register. + fields: + - name: CTEIF + description: Clear tearing effect interrupt flag Write 1 clears the TEIF flag in the WSR register. + bit_offset: 0 + bit_size: 1 + - name: CERIF + description: Clear end of refresh interrupt flag Write 1 clears the ERIF flag in the WSR register. + bit_offset: 1 + bit_size: 1 + - name: CPLLLIF + description: Clear PLL lock interrupt flag Write 1 clears the PLLLIF flag in the WSR register. + bit_offset: 9 + bit_size: 1 + - name: CPLLUIF + description: Clear PLL unlock interrupt flag Write 1 clears the PLLUIF flag in the WSR register. + bit_offset: 10 + bit_size: 1 +fieldset/WISR: + description: DSI Wrapper interrupt and status register. + fields: + - name: TEIF + description: Tearing effect interrupt flag This bit is set when a tearing effect event occurs. + bit_offset: 0 + bit_size: 1 + - name: ERIF + description: End of refresh interrupt flag This bit is set when the transfer of a frame in adapted command mode is finished. + bit_offset: 1 + bit_size: 1 + - name: BUSY + description: Busy flag This bit is set when the transfer of a frame in adapted command mode is ongoing. + bit_offset: 2 + bit_size: 1 + - name: PLLLS + description: PLL lock status This bit is set when the PLL is locked and cleared when it is unlocked. + bit_offset: 8 + bit_size: 1 + - name: PLLLIF + description: PLL lock interrupt flag This bit is set when the PLL becomes locked. + bit_offset: 9 + bit_size: 1 + - name: PLLUIF + description: PLL unlock interrupt flag This bit is set when the PLL becomes unlocked. + bit_offset: 10 + bit_size: 1 +fieldset/WPCR0: + description: DSI Wrapper PHY configuration register 0. + fields: + - name: SWCL + description: Swap clock lane pins This bit swaps the pins on clock lane. + bit_offset: 6 + bit_size: 1 + - name: SWDL0 + description: Swap data lane 0 pins This bit swaps the pins on data lane 0. + bit_offset: 7 + bit_size: 1 + - name: SWDL1 + description: Swap data lane 1 pins This bit swaps the pins on clock lane. + bit_offset: 8 + bit_size: 1 + - name: FTXSMCL + description: Force in TX Stop mode the clock lane This bit forces the clock lane in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. + bit_offset: 12 + bit_size: 1 + - name: FTXSMDL + description: Force in TX Stop mode the data lanes This bit forces the data lanes in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. + bit_offset: 13 + bit_size: 1 +fieldset/WRPCR: + description: DSI Wrapper regulator and PLL control register. + fields: + - name: PLLEN + description: PLL enable This bit enables the D-PHY PLL. + bit_offset: 0 + bit_size: 1 + - name: NDIV + description: "PLL loop division factor This field configures the PLL loop division factor. 2: PLL loop divided by 2x2 ... 511: PLL loop divided by 511x2." + bit_offset: 2 + bit_size: 9 + - name: IDF + description: "PLL input division factor This field configures the PLL input division factor. 2: PLL input divided by 2 ... 511: PLL input divided by 511." + bit_offset: 11 + bit_size: 9 + - name: ODF + description: "PLL output division factor This field configures the PLL output division factor. 2: PLL output divided by 2 ... 511: PLL output divided by 511." + bit_offset: 20 + bit_size: 9 diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index d345691..6affaee 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -1,4506 +1,4506 @@ block/RCC: description: Reset and clock control items: - - name: CR - description: RCC clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR1 - description: RCC internal clock sources calibration register 1 - byte_offset: 8 - fieldset: ICSCR1 - - name: ICSCR2 - description: RCC internal clock sources calibration register 2 - byte_offset: 12 - fieldset: ICSCR2 - - name: ICSCR3 - description: RCC internal clock sources calibration register 3 - byte_offset: 16 - fieldset: ICSCR3 - - name: CRRCR - description: RCC clock recovery RC register - byte_offset: 20 - fieldset: CRRCR - - name: CFGR1 - description: RCC clock configuration register 1 - byte_offset: 28 - fieldset: CFGR1 - - name: CFGR2 - description: RCC clock configuration register 2 - byte_offset: 32 - fieldset: CFGR2 - - name: CFGR3 - description: RCC clock configuration register 3 - byte_offset: 36 - fieldset: CFGR3 - - name: PLL1CFGR - description: RCC PLL1 configuration register - byte_offset: 40 - fieldset: PLL1CFGR - - name: PLL2CFGR - description: RCC PLL2 configuration register - byte_offset: 44 - fieldset: PLL23CFGR - - name: PLL3CFGR - description: RCC PLL3 configuration register - byte_offset: 48 - fieldset: PLL23CFGR - - name: PLL1DIVR - description: RCC PLL1 dividers register - byte_offset: 52 - fieldset: PLLDIVR - - name: PLL1FRACR - description: RCC PLL1 fractional divider register - byte_offset: 56 - fieldset: PLLFRACR - - name: PLL2DIVR - description: RCC PLL2 dividers configuration register - byte_offset: 60 - fieldset: PLLDIVR - - name: PLL2FRACR - description: RCC PLL2 fractional divider register - byte_offset: 64 - fieldset: PLLFRACR - - name: PLL3DIVR - description: RCC PLL3 dividers configuration register - byte_offset: 68 - fieldset: PLLDIVR - - name: PLL3FRACR - description: RCC PLL3 fractional divider register - byte_offset: 72 - fieldset: PLLFRACR - - name: CIER - description: RCC clock interrupt enable register - byte_offset: 80 - fieldset: CIER - - name: CIFR - description: RCC clock interrupt flag register - byte_offset: 84 - fieldset: CIFR - - name: CICR - description: RCC clock interrupt clear register - byte_offset: 88 - fieldset: CICR - - name: AHB1RSTR - description: RCC AHB1 peripheral reset register - byte_offset: 96 - fieldset: AHB1RSTR - - name: AHB2RSTR1 - description: RCC AHB2 peripheral reset register 1 - byte_offset: 100 - fieldset: AHB2RSTR1 - - name: AHB2RSTR2 - description: RCC AHB2 peripheral reset register 2 - byte_offset: 104 - fieldset: AHB2RSTR2 - - name: AHB3RSTR - description: RCC AHB3 peripheral reset register - byte_offset: 108 - fieldset: AHB3RSTR - - name: APB1RSTR1 - description: RCC APB1 peripheral reset register 1 - byte_offset: 116 - fieldset: APB1RSTR1 - - name: APB1RSTR2 - description: RCC APB1 peripheral reset register 2 - byte_offset: 120 - fieldset: APB1RSTR2 - - name: APB2RSTR - description: RCC APB2 peripheral reset register - byte_offset: 124 - fieldset: APB2RSTR - - name: APB3RSTR - description: RCC APB3 peripheral reset register - byte_offset: 128 - fieldset: APB3RSTR - - name: AHB1ENR - description: RCC AHB1 peripheral clock enable register - byte_offset: 136 - fieldset: AHB1ENR - - name: AHB2ENR1 - description: RCC AHB2 peripheral clock enable register 1 - byte_offset: 140 - fieldset: AHB2ENR1 - - name: AHB2ENR2 - description: RCC AHB2 peripheral clock enable register 2 - byte_offset: 144 - fieldset: AHB2ENR2 - - name: AHB3ENR - description: RCC AHB3 peripheral clock enable register - byte_offset: 148 - fieldset: AHB3ENR - - name: APB1ENR1 - description: RCC APB1 peripheral clock enable register 1 - byte_offset: 156 - fieldset: APB1ENR1 - - name: APB1ENR2 - description: RCC APB1 peripheral clock enable register 2 - byte_offset: 160 - fieldset: APB1ENR2 - - name: APB2ENR - description: RCC APB2 peripheral clock enable register - byte_offset: 164 - fieldset: APB2ENR - - name: APB3ENR - description: RCC APB3 peripheral clock enable register - byte_offset: 168 - fieldset: APB3ENR - - name: AHB1SMENR - description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 176 - fieldset: AHB1SMENR - - name: AHB2SMENR1 - description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1" - byte_offset: 180 - fieldset: AHB2SMENR1 - - name: AHB2SMENR2 - description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2" - byte_offset: 184 - fieldset: AHB2SMENR2 - - name: AHB3SMENR - description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 188 - fieldset: AHB3SMENR - - name: APB1SMENR1 - description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1" - byte_offset: 196 - fieldset: APB1SMENR1 - - name: APB1SMENR2 - description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2" - byte_offset: 200 - fieldset: APB1SMENR2 - - name: APB2SMENR - description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register - byte_offset: 204 - fieldset: APB2SMENR - - name: APB3SMENR - description: RCC APB3 peripheral clock enable in Sleep and Stop modes register - byte_offset: 208 - fieldset: APB3SMENR - - name: SRDAMR - description: RCC SmartRun domain peripheral autonomous mode register - byte_offset: 216 - fieldset: SRDAMR - - name: CCIPR1 - description: RCC peripherals independent clock configuration register 1 - byte_offset: 224 - fieldset: CCIPR1 - - name: CCIPR2 - description: RCC peripherals independent clock configuration register 2 - byte_offset: 228 - fieldset: CCIPR2 - - name: CCIPR3 - description: RCC peripherals independent clock configuration register 3 - byte_offset: 232 - fieldset: CCIPR3 - - name: BDCR - description: RCC Backup domain control register - byte_offset: 240 - fieldset: BDCR - - name: CSR - description: RCC control/status register - byte_offset: 244 - fieldset: CSR - - name: SECCFGR - description: RCC secure configuration register - byte_offset: 272 - fieldset: SECCFGR - - name: PRIVCFGR - description: RCC privilege configuration register - byte_offset: 276 - fieldset: PRIVCFGR + - name: CR + description: RCC clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR1 + description: RCC internal clock sources calibration register 1 + byte_offset: 8 + fieldset: ICSCR1 + - name: ICSCR2 + description: RCC internal clock sources calibration register 2 + byte_offset: 12 + fieldset: ICSCR2 + - name: ICSCR3 + description: RCC internal clock sources calibration register 3 + byte_offset: 16 + fieldset: ICSCR3 + - name: CRRCR + description: RCC clock recovery RC register + byte_offset: 20 + fieldset: CRRCR + - name: CFGR1 + description: RCC clock configuration register 1 + byte_offset: 28 + fieldset: CFGR1 + - name: CFGR2 + description: RCC clock configuration register 2 + byte_offset: 32 + fieldset: CFGR2 + - name: CFGR3 + description: RCC clock configuration register 3 + byte_offset: 36 + fieldset: CFGR3 + - name: PLL1CFGR + description: RCC PLL1 configuration register + byte_offset: 40 + fieldset: PLL1CFGR + - name: PLL2CFGR + description: RCC PLL2 configuration register + byte_offset: 44 + fieldset: PLL23CFGR + - name: PLL3CFGR + description: RCC PLL3 configuration register + byte_offset: 48 + fieldset: PLL23CFGR + - name: PLL1DIVR + description: RCC PLL1 dividers register + byte_offset: 52 + fieldset: PLLDIVR + - name: PLL1FRACR + description: RCC PLL1 fractional divider register + byte_offset: 56 + fieldset: PLLFRACR + - name: PLL2DIVR + description: RCC PLL2 dividers configuration register + byte_offset: 60 + fieldset: PLLDIVR + - name: PLL2FRACR + description: RCC PLL2 fractional divider register + byte_offset: 64 + fieldset: PLLFRACR + - name: PLL3DIVR + description: RCC PLL3 dividers configuration register + byte_offset: 68 + fieldset: PLLDIVR + - name: PLL3FRACR + description: RCC PLL3 fractional divider register + byte_offset: 72 + fieldset: PLLFRACR + - name: CIER + description: RCC clock interrupt enable register + byte_offset: 80 + fieldset: CIER + - name: CIFR + description: RCC clock interrupt flag register + byte_offset: 84 + fieldset: CIFR + - name: CICR + description: RCC clock interrupt clear register + byte_offset: 88 + fieldset: CICR + - name: AHB1RSTR + description: RCC AHB1 peripheral reset register + byte_offset: 96 + fieldset: AHB1RSTR + - name: AHB2RSTR1 + description: RCC AHB2 peripheral reset register 1 + byte_offset: 100 + fieldset: AHB2RSTR1 + - name: AHB2RSTR2 + description: RCC AHB2 peripheral reset register 2 + byte_offset: 104 + fieldset: AHB2RSTR2 + - name: AHB3RSTR + description: RCC AHB3 peripheral reset register + byte_offset: 108 + fieldset: AHB3RSTR + - name: APB1RSTR1 + description: RCC APB1 peripheral reset register 1 + byte_offset: 116 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: RCC APB1 peripheral reset register 2 + byte_offset: 120 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: RCC APB2 peripheral reset register + byte_offset: 124 + fieldset: APB2RSTR + - name: APB3RSTR + description: RCC APB3 peripheral reset register + byte_offset: 128 + fieldset: APB3RSTR + - name: AHB1ENR + description: RCC AHB1 peripheral clock enable register + byte_offset: 136 + fieldset: AHB1ENR + - name: AHB2ENR1 + description: RCC AHB2 peripheral clock enable register 1 + byte_offset: 140 + fieldset: AHB2ENR1 + - name: AHB2ENR2 + description: RCC AHB2 peripheral clock enable register 2 + byte_offset: 144 + fieldset: AHB2ENR2 + - name: AHB3ENR + description: RCC AHB3 peripheral clock enable register + byte_offset: 148 + fieldset: AHB3ENR + - name: APB1ENR1 + description: RCC APB1 peripheral clock enable register 1 + byte_offset: 156 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: RCC APB1 peripheral clock enable register 2 + byte_offset: 160 + fieldset: APB1ENR2 + - name: APB2ENR + description: RCC APB2 peripheral clock enable register + byte_offset: 164 + fieldset: APB2ENR + - name: APB3ENR + description: RCC APB3 peripheral clock enable register + byte_offset: 168 + fieldset: APB3ENR + - name: AHB1SMENR + description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 176 + fieldset: AHB1SMENR + - name: AHB2SMENR1 + description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1" + byte_offset: 180 + fieldset: AHB2SMENR1 + - name: AHB2SMENR2 + description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2" + byte_offset: 184 + fieldset: AHB2SMENR2 + - name: AHB3SMENR + description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 188 + fieldset: AHB3SMENR + - name: APB1SMENR1 + description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1" + byte_offset: 196 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2" + byte_offset: 200 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 204 + fieldset: APB2SMENR + - name: APB3SMENR + description: RCC APB3 peripheral clock enable in Sleep and Stop modes register + byte_offset: 208 + fieldset: APB3SMENR + - name: SRDAMR + description: RCC SmartRun domain peripheral autonomous mode register + byte_offset: 216 + fieldset: SRDAMR + - name: CCIPR1 + description: RCC peripherals independent clock configuration register 1 + byte_offset: 224 + fieldset: CCIPR1 + - name: CCIPR2 + description: RCC peripherals independent clock configuration register 2 + byte_offset: 228 + fieldset: CCIPR2 + - name: CCIPR3 + description: RCC peripherals independent clock configuration register 3 + byte_offset: 232 + fieldset: CCIPR3 + - name: BDCR + description: RCC Backup domain control register + byte_offset: 240 + fieldset: BDCR + - name: CSR + description: RCC control/status register + byte_offset: 244 + fieldset: CSR + - name: SECCFGR + description: RCC secure configuration register + byte_offset: 272 + fieldset: SECCFGR + - name: PRIVCFGR + description: RCC privilege configuration register + byte_offset: 276 + fieldset: PRIVCFGR fieldset/AHB1ENR: description: RCC AHB1 peripheral clock enable register fields: - - name: GPDMA1EN - description: "GPDMA1 clock enable\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: CORDICEN - description: "CORDIC clock enable\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: FMACEN - description: "FMAC clock enable\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - - name: MDF1EN - description: "MDF1 clock enable\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - - name: FLASHEN - description: "FLASH clock enable\r Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode." - bit_offset: 8 - bit_size: 1 - - name: CRCEN - description: "CRC clock enable\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: JPEGEN - description: "JPEG clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 15 - bit_size: 1 - - name: TSCEN - description: "Touch sensing controller clock enable\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: RAMCFGEN - description: "RAMCFG clock enable\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: DMA2DEN - description: "DMA2D clock enable\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: GFXMMUEN - description: "GFXMMU clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 19 - bit_size: 1 - - name: GPU2DEN - description: "GPU2D clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 20 - bit_size: 1 - - name: DCACHE2EN - description: "DCACHE2 clock enable \r This bit is set and reset by software.\r Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 21 - bit_size: 1 - - name: GTZC1EN - description: "GTZC1 clock enable\r Set and reset by software." - bit_offset: 24 - bit_size: 1 - - name: BKPSRAMEN - description: "BKPSRAM clock enable\r Set and reset by software." - bit_offset: 28 - bit_size: 1 - - name: DCACHE1EN - description: "DCACHE1 clock enable\r Set and reset by software.\r Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed." - bit_offset: 30 - bit_size: 1 - - name: SRAM1EN - description: "SRAM1 clock enable\r Set and reset by software." - bit_offset: 31 - bit_size: 1 + - name: GPDMA1EN + description: "GPDMA1 clock enable\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: CORDICEN + description: "CORDIC clock enable\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: FMACEN + description: "FMAC clock enable\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + - name: MDF1EN + description: "MDF1 clock enable\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: FLASHEN + description: "FLASH clock enable\r Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode." + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: "CRC clock enable\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: JPEGEN + description: "JPEG clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 15 + bit_size: 1 + - name: TSCEN + description: "Touch sensing controller clock enable\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: RAMCFGEN + description: "RAMCFG clock enable\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: DMA2DEN + description: "DMA2D clock enable\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: GFXMMUEN + description: "GFXMMU clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 19 + bit_size: 1 + - name: GPU2DEN + description: "GPU2D clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 20 + bit_size: 1 + - name: DCACHE2EN + description: "DCACHE2 clock enable \r This bit is set and reset by software.\r Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 21 + bit_size: 1 + - name: GTZC1EN + description: "GTZC1 clock enable\r Set and reset by software." + bit_offset: 24 + bit_size: 1 + - name: BKPSRAMEN + description: "BKPSRAM clock enable\r Set and reset by software." + bit_offset: 28 + bit_size: 1 + - name: DCACHE1EN + description: "DCACHE1 clock enable\r Set and reset by software.\r Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed." + bit_offset: 30 + bit_size: 1 + - name: SRAM1EN + description: "SRAM1 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB1RSTR: description: RCC AHB1 peripheral reset register fields: - - name: GPDMA1RST - description: "GPDMA1 reset\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: CORDICRST - description: "CORDIC reset\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: FMACRST - description: "FMAC reset\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: MDF1RST - description: "MDF1 reset\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: CRCRST - description: "CRC reset\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: JPEGRST - description: "JPEG reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 15 - bit_size: 1 - - name: TSCRST - description: "TSC reset\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: RAMCFGRST - description: "RAMCFG reset\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: DMA2DRST - description: "DMA2D reset\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: GFXMMURST - description: "GFXMMU reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 19 - bit_size: 1 - - name: GPU2DRST - description: "GPU2D reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 20 - bit_size: 1 + - name: GPDMA1RST + description: "GPDMA1 reset\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: CORDICRST + description: "CORDIC reset\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: FMACRST + description: "FMAC reset\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: MDF1RST + description: "MDF1 reset\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: CRCRST + description: "CRC reset\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: JPEGRST + description: "JPEG reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 15 + bit_size: 1 + - name: TSCRST + description: "TSC reset\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: RAMCFGRST + description: "RAMCFG reset\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: DMA2DRST + description: "DMA2D reset\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: GFXMMURST + description: "GFXMMU reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 19 + bit_size: 1 + - name: GPU2DRST + description: "GPU2D reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 20 + bit_size: 1 fieldset/AHB1SMENR: description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register fields: - - name: GPDMA1SMEN - description: "GPDMA1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 0 - bit_size: 1 - - name: CORDICSMEN - description: "CORDIC clocks enable during Sleep and Stop modes\r Set and cleared by software during Sleep mode." - bit_offset: 1 - bit_size: 1 - - name: FMACSMEN - description: "FMAC clocks enable during Sleep and Stop modes.\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: MDF1SMEN - description: "MDF1 clocks enable during Sleep and Stop modes.\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 3 - bit_size: 1 - - name: FLASHSMEN - description: "FLASH clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: CRCSMEN - description: "CRC clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: JPEGSMEN - description: "JPEG clocks enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 15 - bit_size: 1 - - name: TSCSMEN - description: "TSC clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: RAMCFGSMEN - description: "RAMCFG clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: DMA2DSMEN - description: "DMA2D clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: GFXMMUSMEN - description: "GFXMMU clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 19 - bit_size: 1 - - name: GPU2DSMEN - description: "GPU2D clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 20 - bit_size: 1 - - name: DCACHE2SMEN - description: "DCACHE2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 21 - bit_size: 1 - - name: GTZC1SMEN - description: "GTZC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: BKPSRAMSMEN - description: "BKPSRAM clocks enable during Sleep and Stop modes\r Set and cleared by software" - bit_offset: 28 - bit_size: 1 - - name: ICACHESMEN - description: "ICACHE clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 29 - bit_size: 1 - - name: DCACHE1SMEN - description: "DCACHE1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 30 - bit_size: 1 - - name: SRAM1SMEN - description: "SRAM1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 31 - bit_size: 1 + - name: GPDMA1SMEN + description: "GPDMA1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 0 + bit_size: 1 + - name: CORDICSMEN + description: "CORDIC clocks enable during Sleep and Stop modes\r Set and cleared by software during Sleep mode." + bit_offset: 1 + bit_size: 1 + - name: FMACSMEN + description: "FMAC clocks enable during Sleep and Stop modes.\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: MDF1SMEN + description: "MDF1 clocks enable during Sleep and Stop modes.\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 3 + bit_size: 1 + - name: FLASHSMEN + description: "FLASH clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: CRCSMEN + description: "CRC clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: JPEGSMEN + description: "JPEG clocks enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 15 + bit_size: 1 + - name: TSCSMEN + description: "TSC clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: RAMCFGSMEN + description: "RAMCFG clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: DMA2DSMEN + description: "DMA2D clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: GFXMMUSMEN + description: "GFXMMU clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 19 + bit_size: 1 + - name: GPU2DSMEN + description: "GPU2D clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 20 + bit_size: 1 + - name: DCACHE2SMEN + description: "DCACHE2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 21 + bit_size: 1 + - name: GTZC1SMEN + description: "GTZC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: BKPSRAMSMEN + description: "BKPSRAM clocks enable during Sleep and Stop modes\r Set and cleared by software" + bit_offset: 28 + bit_size: 1 + - name: ICACHESMEN + description: "ICACHE clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 29 + bit_size: 1 + - name: DCACHE1SMEN + description: "DCACHE1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 30 + bit_size: 1 + - name: SRAM1SMEN + description: "SRAM1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB2ENR1: description: RCC AHB2 peripheral clock enable register 1 fields: - - name: GPIOAEN - description: "IO port A clock enable\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: "IO port B clock enable\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: "IO port C clock enable\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: "IO port D clock enable\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: "IO port E clock enable\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: "IO port F clock enable\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: "IO port G clock enable\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: "IO port H clock enable\r Set and cleared by software." - bit_offset: 7 - bit_size: 1 - - name: GPIOIEN - description: "IO port I clock enable\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: GPIOJEN - description: "I/O port J clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 9 - bit_size: 1 - - name: ADC12EN - description: "ADC1 and ADC2 clock enable\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx." - bit_offset: 10 - bit_size: 1 - - name: DCMIEN - description: "DCMI and PSSI clock enable\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: USB_OTG_FSEN - description: "OTG_FS clock enable\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USB_OTG_HSEN - description: "OTG_HS clock enable\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USB_OTG_HS_PHYEN - description: "OTG_HS PHY clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 15 - bit_size: 1 - - name: AESEN - description: "AES clock enable\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: HASHEN - description: "HASH clock enable\r Set and cleared by software" - bit_offset: 17 - bit_size: 1 - - name: RNGEN - description: "RNG clock enable\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: PKAEN - description: "PKA clock enable\r Set and cleared by software." - bit_offset: 19 - bit_size: 1 - - name: SAESEN - description: "SAES clock enable\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: OCTOSPIMEN - description: "OCTOSPIM clock enable\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: OTFDEC1EN - description: "OTFDEC1 clock enable\r Set and cleared by software." - bit_offset: 23 - bit_size: 1 - - name: OTFDEC2EN - description: "OTFDEC2 clock enable\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: SDMMC1EN - description: "SDMMC1 clock enable\r Set and cleared by software." - bit_offset: 27 - bit_size: 1 - - name: SDMMC2EN - description: "SDMMC2 clock enable\r Set and cleared by software." - bit_offset: 28 - bit_size: 1 - - name: SRAM2EN - description: "SRAM2 clock enable\r Set and reset by software." - bit_offset: 30 - bit_size: 1 - - name: SRAM3EN - description: "SRAM3 clock enable\r Set and reset by software." - bit_offset: 31 - bit_size: 1 + - name: GPIOAEN + description: "IO port A clock enable\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: "IO port B clock enable\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: "IO port C clock enable\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: "IO port D clock enable\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: "IO port E clock enable\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: "IO port F clock enable\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: "IO port G clock enable\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: "IO port H clock enable\r Set and cleared by software." + bit_offset: 7 + bit_size: 1 + - name: GPIOIEN + description: "IO port I clock enable\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: GPIOJEN + description: "I/O port J clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 9 + bit_size: 1 + - name: ADC12EN + description: "ADC1 and ADC2 clock enable\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx." + bit_offset: 10 + bit_size: 1 + - name: DCMIEN + description: "DCMI and PSSI clock enable\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: USB_OTG_FSEN + description: "OTG_FS clock enable\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USB_OTG_HSEN + description: "OTG_HS clock enable\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USB_OTG_HS_PHYEN + description: "OTG_HS PHY clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 15 + bit_size: 1 + - name: AESEN + description: "AES clock enable\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: HASHEN + description: "HASH clock enable\r Set and cleared by software" + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: "RNG clock enable\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: PKAEN + description: "PKA clock enable\r Set and cleared by software." + bit_offset: 19 + bit_size: 1 + - name: SAESEN + description: "SAES clock enable\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: OCTOSPIMEN + description: "OCTOSPIM clock enable\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: OTFDEC1EN + description: "OTFDEC1 clock enable\r Set and cleared by software." + bit_offset: 23 + bit_size: 1 + - name: OTFDEC2EN + description: "OTFDEC2 clock enable\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: SDMMC1EN + description: "SDMMC1 clock enable\r Set and cleared by software." + bit_offset: 27 + bit_size: 1 + - name: SDMMC2EN + description: "SDMMC2 clock enable\r Set and cleared by software." + bit_offset: 28 + bit_size: 1 + - name: SRAM2EN + description: "SRAM2 clock enable\r Set and reset by software." + bit_offset: 30 + bit_size: 1 + - name: SRAM3EN + description: "SRAM3 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB2ENR2: description: RCC AHB2 peripheral clock enable register 2 fields: - - name: FSMCEN - description: "FSMC clock enable\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: OCTOSPI1EN - description: "OCTOSPI1 clock enable\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: OCTOSPI2EN - description: "OCTOSPI2 clock enable\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: HSPI1EN - description: "HSPI1 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 12 - bit_size: 1 - - name: SRAM6EN - description: "SRAM6 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 30 - bit_size: 1 - - name: SRAM5EN - description: "SRAM5 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 31 - bit_size: 1 + - name: FSMCEN + description: "FSMC clock enable\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: OCTOSPI1EN + description: "OCTOSPI1 clock enable\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: OCTOSPI2EN + description: "OCTOSPI2 clock enable\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: HSPI1EN + description: "HSPI1 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 12 + bit_size: 1 + - name: SRAM6EN + description: "SRAM6 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 30 + bit_size: 1 + - name: SRAM5EN + description: "SRAM5 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 31 + bit_size: 1 fieldset/AHB2RSTR1: description: RCC AHB2 peripheral reset register 1 fields: - - name: GPIOARST - description: "IO port A reset\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: "IO port B reset\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: "IO port C reset\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: "IO port D reset\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: "IO port E reset\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: GPIOFRST - description: "IO port F reset\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: "IO port G reset\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: GPIOHRST - description: "IO port H reset\r Set and cleared by software." - bit_offset: 7 - bit_size: 1 - - name: GPIOIRST - description: "IO port I reset\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: GPIOJRST - description: "I/O port J reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 9 - bit_size: 1 - - name: ADC12RST - description: "ADC1 and ADC2 reset\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx." - bit_offset: 10 - bit_size: 1 - - name: DCMIRST - description: "DCMI and PSSI reset\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: USB_OTG_FSRST - description: "OTG_FS reset\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USB_OTG_HSRST - description: "OTG_HS reset\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: AESRST - description: "AES hardware accelerator reset\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: HASHRST - description: "Hash reset\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: RNGRST - description: "Random number generator reset\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: PKARST - description: "PKA reset\r Set and cleared by software." - bit_offset: 19 - bit_size: 1 - - name: SAESRST - description: "SAES hardware accelerator reset\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: OCTOSPIMRST - description: "OCTOSPIM reset\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: OTFDEC1RST - description: "OTFDEC1 reset\r Set and cleared by software." - bit_offset: 23 - bit_size: 1 - - name: OTFDEC2RST - description: "OTFDEC2 reset\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: SDMMC1RST - description: "SDMMC1 reset\r Set and cleared by software." - bit_offset: 27 - bit_size: 1 - - name: SDMMC2RST - description: "SDMMC2 reset\r Set and cleared by software." - bit_offset: 28 - bit_size: 1 + - name: GPIOARST + description: "IO port A reset\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: "IO port B reset\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: "IO port C reset\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: "IO port D reset\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: "IO port E reset\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: "IO port F reset\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: "IO port G reset\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: "IO port H reset\r Set and cleared by software." + bit_offset: 7 + bit_size: 1 + - name: GPIOIRST + description: "IO port I reset\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: GPIOJRST + description: "I/O port J reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 9 + bit_size: 1 + - name: ADC12RST + description: "ADC1 and ADC2 reset\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx." + bit_offset: 10 + bit_size: 1 + - name: DCMIRST + description: "DCMI and PSSI reset\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: USB_OTG_FSRST + description: "OTG_FS reset\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USB_OTG_HSRST + description: "OTG_HS reset\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: AESRST + description: "AES hardware accelerator reset\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: HASHRST + description: "Hash reset\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: "Random number generator reset\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: PKARST + description: "PKA reset\r Set and cleared by software." + bit_offset: 19 + bit_size: 1 + - name: SAESRST + description: "SAES hardware accelerator reset\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: OCTOSPIMRST + description: "OCTOSPIM reset\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: OTFDEC1RST + description: "OTFDEC1 reset\r Set and cleared by software." + bit_offset: 23 + bit_size: 1 + - name: OTFDEC2RST + description: "OTFDEC2 reset\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: SDMMC1RST + description: "SDMMC1 reset\r Set and cleared by software." + bit_offset: 27 + bit_size: 1 + - name: SDMMC2RST + description: "SDMMC2 reset\r Set and cleared by software." + bit_offset: 28 + bit_size: 1 fieldset/AHB2RSTR2: description: RCC AHB2 peripheral reset register 2 fields: - - name: FSMCRST - description: "Flexible memory controller reset\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: OCTOSPI1RST - description: "OCTOSPI1 reset\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: OCTOSPI2RST - description: "OCTOSPI2 reset\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: HSPI1RST - description: "HSPI1 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 12 - bit_size: 1 + - name: FSMCRST + description: "Flexible memory controller reset\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: OCTOSPI1RST + description: "OCTOSPI1 reset\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: OCTOSPI2RST + description: "OCTOSPI2 reset\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: HSPI1RST + description: "HSPI1 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 12 + bit_size: 1 fieldset/AHB2SMENR1: description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1" fields: - - name: GPIOASMEN - description: "IO port A clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: GPIOBSMEN - description: "IO port B clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: GPIOCSMEN - description: "IO port C clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: GPIODSMEN - description: "IO port D clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: GPIOESMEN - description: "IO port E clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: GPIOFSMEN - description: "IO port F clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: GPIOGSMEN - description: "IO port G clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: GPIOHSMEN - description: "IO port H clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 7 - bit_size: 1 - - name: GPIOISMEN - description: "IO port I clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: GPIOJSMEN - description: "I/O port J clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 9 - bit_size: 1 - - name: ADC12SMEN - description: "ADC1 and ADC2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx." - bit_offset: 10 - bit_size: 1 - - name: DCMISMEN - description: "DCMI and PSSI clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: USB_OTG_FSSMEN - description: "OTG_FS clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USB_OTG_HSSMEN - description: "OTG_HS clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USB_OTG_HS_PHYSMEN - description: "OTG_HS PHY clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 15 - bit_size: 1 - - name: AESSMEN - description: "AES clock enable during Sleep and Stop modes\r Set and cleared by software" - bit_offset: 16 - bit_size: 1 - - name: HASHSMEN - description: "HASH clock enable during Sleep and Stop modes\r Set and cleared by software" - bit_offset: 17 - bit_size: 1 - - name: RNGSMEN - description: "Random number generator (RNG) clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: PKASMEN - description: "PKA clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 19 - bit_size: 1 - - name: SAESSMEN - description: "SAES accelerator clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: OCTOSPIMSMEN - description: "OCTOSPIM clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: OTFDEC1SMEN - description: "OTFDEC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 23 - bit_size: 1 - - name: OTFDEC2SMEN - description: "OTFDEC2 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: SDMMC1SMEN - description: "SDMMC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 27 - bit_size: 1 - - name: SDMMC2SMEN - description: "SDMMC2 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 28 - bit_size: 1 - - name: SRAM2SMEN - description: "SRAM2 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 30 - bit_size: 1 - - name: SRAM3SMEN - description: "SRAM3 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 31 - bit_size: 1 + - name: GPIOASMEN + description: "IO port A clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: "IO port B clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: "IO port C clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: GPIODSMEN + description: "IO port D clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: GPIOESMEN + description: "IO port E clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: GPIOFSMEN + description: "IO port F clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: GPIOGSMEN + description: "IO port G clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: GPIOHSMEN + description: "IO port H clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 7 + bit_size: 1 + - name: GPIOISMEN + description: "IO port I clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: GPIOJSMEN + description: "I/O port J clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 9 + bit_size: 1 + - name: ADC12SMEN + description: "ADC1 and ADC2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx." + bit_offset: 10 + bit_size: 1 + - name: DCMISMEN + description: "DCMI and PSSI clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: USB_OTG_FSSMEN + description: "OTG_FS clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USB_OTG_HSSMEN + description: "OTG_HS clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USB_OTG_HS_PHYSMEN + description: "OTG_HS PHY clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 15 + bit_size: 1 + - name: AESSMEN + description: "AES clock enable during Sleep and Stop modes\r Set and cleared by software" + bit_offset: 16 + bit_size: 1 + - name: HASHSMEN + description: "HASH clock enable during Sleep and Stop modes\r Set and cleared by software" + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: "Random number generator (RNG) clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: PKASMEN + description: "PKA clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 19 + bit_size: 1 + - name: SAESSMEN + description: "SAES accelerator clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: OCTOSPIMSMEN + description: "OCTOSPIM clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: OTFDEC1SMEN + description: "OTFDEC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 23 + bit_size: 1 + - name: OTFDEC2SMEN + description: "OTFDEC2 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: SDMMC1SMEN + description: "SDMMC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 27 + bit_size: 1 + - name: SDMMC2SMEN + description: "SDMMC2 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 28 + bit_size: 1 + - name: SRAM2SMEN + description: "SRAM2 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 30 + bit_size: 1 + - name: SRAM3SMEN + description: "SRAM3 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB2SMENR2: description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2" fields: - - name: FSMCSMEN - description: "FSMC clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: OCTOSPI1SMEN - description: "OCTOSPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: OCTOSPI2SMEN - description: "OCTOSPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 8 - bit_size: 1 - - name: HSPI1SMEN - description: "HSPI1 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 12 - bit_size: 1 - - name: SRAM6SMEN - description: "SRAM6 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 30 - bit_size: 1 - - name: SRAM5SMEN - description: "SRAM5 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 31 - bit_size: 1 + - name: FSMCSMEN + description: "FSMC clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: OCTOSPI1SMEN + description: "OCTOSPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: OCTOSPI2SMEN + description: "OCTOSPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 8 + bit_size: 1 + - name: HSPI1SMEN + description: "HSPI1 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 12 + bit_size: 1 + - name: SRAM6SMEN + description: "SRAM6 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 30 + bit_size: 1 + - name: SRAM5SMEN + description: "SRAM5 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 31 + bit_size: 1 fieldset/AHB3ENR: description: RCC AHB3 peripheral clock enable register fields: - - name: LPGPIO1EN - description: "LPGPIO1 enable\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: PWREN - description: "PWR clock enable\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: ADC4EN - description: "ADC4 clock enable\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: DAC1EN - description: "DAC1 clock enable\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: LPDMA1EN - description: "LPDMA1 clock enable\r Set and cleared by software." - bit_offset: 9 - bit_size: 1 - - name: ADF1EN - description: "ADF1 clock enable\r Set and cleared by software." - bit_offset: 10 - bit_size: 1 - - name: GTZC2EN - description: "GTZC2 clock enable\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: SRAM4EN - description: "SRAM4 clock enable\r Set and reset by software." - bit_offset: 31 - bit_size: 1 + - name: LPGPIO1EN + description: "LPGPIO1 enable\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: PWREN + description: "PWR clock enable\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: ADC4EN + description: "ADC4 clock enable\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: DAC1EN + description: "DAC1 clock enable\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: LPDMA1EN + description: "LPDMA1 clock enable\r Set and cleared by software." + bit_offset: 9 + bit_size: 1 + - name: ADF1EN + description: "ADF1 clock enable\r Set and cleared by software." + bit_offset: 10 + bit_size: 1 + - name: GTZC2EN + description: "GTZC2 clock enable\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: SRAM4EN + description: "SRAM4 clock enable\r Set and reset by software." + bit_offset: 31 + bit_size: 1 fieldset/AHB3RSTR: description: RCC AHB3 peripheral reset register fields: - - name: LPGPIO1RST - description: "LPGPIO1 reset\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: ADC4RST - description: "ADC4 reset\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: DAC1RST - description: "DAC1 reset\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: LPDMA1RST - description: "LPDMA1 reset\r Set and cleared by software." - bit_offset: 9 - bit_size: 1 - - name: ADF1RST - description: "ADF1 reset\r Set and cleared by software." - bit_offset: 10 - bit_size: 1 + - name: LPGPIO1RST + description: "LPGPIO1 reset\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: ADC4RST + description: "ADC4 reset\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: DAC1RST + description: "DAC1 reset\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: LPDMA1RST + description: "LPDMA1 reset\r Set and cleared by software." + bit_offset: 9 + bit_size: 1 + - name: ADF1RST + description: "ADF1 reset\r Set and cleared by software." + bit_offset: 10 + bit_size: 1 fieldset/AHB3SMENR: description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - - name: LPGPIO1SMEN - description: "LPGPIO1 enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: PWRSMEN - description: "PWR clock enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: ADC4SMEN - description: "ADC4 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 5 - bit_size: 1 - - name: DAC1SMEN - description: "DAC1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 6 - bit_size: 1 - - name: LPDMA1SMEN - description: "LPDMA1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 9 - bit_size: 1 - - name: ADF1SMEN - description: "ADF1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 10 - bit_size: 1 - - name: GTZC2SMEN - description: "GTZC2 clock enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: SRAM4SMEN - description: "SRAM4 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 31 - bit_size: 1 + - name: LPGPIO1SMEN + description: "LPGPIO1 enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: PWRSMEN + description: "PWR clock enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: ADC4SMEN + description: "ADC4 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 + - name: DAC1SMEN + description: "DAC1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 6 + bit_size: 1 + - name: LPDMA1SMEN + description: "LPDMA1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 9 + bit_size: 1 + - name: ADF1SMEN + description: "ADF1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 10 + bit_size: 1 + - name: GTZC2SMEN + description: "GTZC2 clock enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: SRAM4SMEN + description: "SRAM4 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 31 + bit_size: 1 fieldset/APB1ENR1: description: RCC APB1 peripheral clock enable register 1 fields: - - name: TIM2EN - description: "TIM2 clock enable\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: "TIM3 clock enable\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: "TIM4 clock enable\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: "TIM5 clock enable\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: "TIM6 clock enable\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: "TIM7 clock enable\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: WWDGEN - description: "WWDG clock enable\r Set by software to enable the window watchdog clock. Reset by hardware system reset.\r This bit can also be set by hardware if the WWDG_SW option bit is reset." - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: "SPI2 clock enable\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USART2EN - description: "USART2 clock enable\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: "USART3 clock enable\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: "UART4 clock enable\r Set and cleared by software." - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: "UART5 clock enable\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: "I2C1 clock enable\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: "I2C2 clock enable\r Set and cleared by software." - bit_offset: 22 - bit_size: 1 - - name: CRSEN - description: "CRS clock enable\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: USART6EN - description: "USART6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 25 - bit_size: 1 + - name: TIM2EN + description: "TIM2 clock enable\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: "TIM3 clock enable\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: "TIM4 clock enable\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: "TIM5 clock enable\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: "TIM6 clock enable\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: "TIM7 clock enable\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: WWDGEN + description: "WWDG clock enable\r Set by software to enable the window watchdog clock. Reset by hardware system reset.\r This bit can also be set by hardware if the WWDG_SW option bit is reset." + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: "SPI2 clock enable\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: "USART2 clock enable\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: "USART3 clock enable\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: "UART4 clock enable\r Set and cleared by software." + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: "UART5 clock enable\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: "I2C1 clock enable\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: "I2C2 clock enable\r Set and cleared by software." + bit_offset: 22 + bit_size: 1 + - name: CRSEN + description: "CRS clock enable\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: USART6EN + description: "USART6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 25 + bit_size: 1 fieldset/APB1ENR2: description: RCC APB1 peripheral clock enable register 2 fields: - - name: I2C4EN - description: "I2C4 clock enable\r Set and cleared by software" - bit_offset: 1 - bit_size: 1 - - name: LPTIM2EN - description: "LPTIM2 clock enable\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: I2C5EN - description: "I2C5 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 6 - bit_size: 1 - - name: I2C6EN - description: "I2C6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 7 - bit_size: 1 - - name: FDCAN1EN - description: "FDCAN1 clock enable\r Set and cleared by software." - bit_offset: 9 - bit_size: 1 - - name: UCPD1EN - description: "UCPD1 clock enable\r Set and cleared by software." - bit_offset: 23 - bit_size: 1 + - name: I2C4EN + description: "I2C4 clock enable\r Set and cleared by software" + bit_offset: 1 + bit_size: 1 + - name: LPTIM2EN + description: "LPTIM2 clock enable\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: I2C5EN + description: "I2C5 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 6 + bit_size: 1 + - name: I2C6EN + description: "I2C6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 7 + bit_size: 1 + - name: FDCAN1EN + description: "FDCAN1 clock enable\r Set and cleared by software." + bit_offset: 9 + bit_size: 1 + - name: UCPD1EN + description: "UCPD1 clock enable\r Set and cleared by software." + bit_offset: 23 + bit_size: 1 fieldset/APB1RSTR1: description: RCC APB1 peripheral reset register 1 fields: - - name: TIM2RST - description: "TIM2 reset\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: "TIM3 reset\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: "TIM4 reset\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: "TIM5 reset\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: "TIM6 reset\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: "TIM7 reset\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: SPI2RST - description: "SPI2 reset\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: USART2RST - description: "USART2 reset\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: "USART3 reset\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: "UART4 reset\r Set and cleared by software." - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: "UART5 reset\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: "I2C1 reset\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: "I2C2 reset\r Set and cleared by software." - bit_offset: 22 - bit_size: 1 - - name: CRSRST - description: "CRS reset\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: USART6RST - description: "USART6 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 25 - bit_size: 1 + - name: TIM2RST + description: "TIM2 reset\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: "TIM3 reset\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: "TIM4 reset\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: "TIM5 reset\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: "TIM6 reset\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: "TIM7 reset\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: SPI2RST + description: "SPI2 reset\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: "USART2 reset\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: "USART3 reset\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: "UART4 reset\r Set and cleared by software." + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: "UART5 reset\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: "I2C1 reset\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: "I2C2 reset\r Set and cleared by software." + bit_offset: 22 + bit_size: 1 + - name: CRSRST + description: "CRS reset\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: USART6RST + description: "USART6 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 25 + bit_size: 1 fieldset/APB1RSTR2: description: RCC APB1 peripheral reset register 2 fields: - - name: I2C4RST - description: "I2C4 reset\r Set and cleared by software" - bit_offset: 1 - bit_size: 1 - - name: LPTIM2RST - description: "LPTIM2 reset\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: I2C5RST - description: "I2C5 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 6 - bit_size: 1 - - name: I2C6RST - description: "I2C6 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 7 - bit_size: 1 - - name: FDCAN1RST - description: "FDCAN1 reset\r Set and cleared by software." - bit_offset: 9 - bit_size: 1 - - name: UCPD1RST - description: "UCPD1 reset\r Set and cleared by software." - bit_offset: 23 - bit_size: 1 + - name: I2C4RST + description: "I2C4 reset\r Set and cleared by software" + bit_offset: 1 + bit_size: 1 + - name: LPTIM2RST + description: "LPTIM2 reset\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: I2C5RST + description: "I2C5 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 6 + bit_size: 1 + - name: I2C6RST + description: "I2C6 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 7 + bit_size: 1 + - name: FDCAN1RST + description: "FDCAN1 reset\r Set and cleared by software." + bit_offset: 9 + bit_size: 1 + - name: UCPD1RST + description: "UCPD1 reset\r Set and cleared by software." + bit_offset: 23 + bit_size: 1 fieldset/APB1SMENR1: description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1" fields: - - name: TIM2SMEN - description: "TIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: TIM3SMEN - description: "TIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: TIM4SMEN - description: "TIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 2 - bit_size: 1 - - name: TIM5SMEN - description: "TIM5 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 3 - bit_size: 1 - - name: TIM6SMEN - description: "TIM6 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 4 - bit_size: 1 - - name: TIM7SMEN - description: "TIM7 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: WWDGSMEN - description: "Window watchdog clocks enable during Sleep and Stop modes\r Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated." - bit_offset: 11 - bit_size: 1 - - name: SPI2SMEN - description: "SPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 14 - bit_size: 1 - - name: USART2SMEN - description: "USART2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 17 - bit_size: 1 - - name: USART3SMEN - description: "USART3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 18 - bit_size: 1 - - name: UART4SMEN - description: "UART4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 19 - bit_size: 1 - - name: UART5SMEN - description: "UART5 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 20 - bit_size: 1 - - name: I2C1SMEN - description: "I2C1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 21 - bit_size: 1 - - name: I2C2SMEN - description: "I2C2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 22 - bit_size: 1 - - name: CRSSMEN - description: "CRS clock enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: USART6SMEN - description: "USART6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 25 - bit_size: 1 + - name: TIM2SMEN + description: "TIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: "TIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: TIM4SMEN + description: "TIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 2 + bit_size: 1 + - name: TIM5SMEN + description: "TIM5 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 3 + bit_size: 1 + - name: TIM6SMEN + description: "TIM6 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 4 + bit_size: 1 + - name: TIM7SMEN + description: "TIM7 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: WWDGSMEN + description: "Window watchdog clocks enable during Sleep and Stop modes\r Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated." + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: "SPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 14 + bit_size: 1 + - name: USART2SMEN + description: "USART2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 17 + bit_size: 1 + - name: USART3SMEN + description: "USART3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 18 + bit_size: 1 + - name: UART4SMEN + description: "UART4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 19 + bit_size: 1 + - name: UART5SMEN + description: "UART5 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 20 + bit_size: 1 + - name: I2C1SMEN + description: "I2C1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: "I2C2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 22 + bit_size: 1 + - name: CRSSMEN + description: "CRS clock enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: USART6SMEN + description: "USART6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 25 + bit_size: 1 fieldset/APB1SMENR2: description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2" fields: - - name: I2C4SMEN - description: "I2C4 clocks enable during Sleep and Stop modes\r Set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 1 - bit_size: 1 - - name: LPTIM2SMEN - description: "LPTIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 5 - bit_size: 1 - - name: I2C5SMEN - description: "I2C5 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 6 - bit_size: 1 - - name: I2C6SMEN - description: "I2C6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 7 - bit_size: 1 - - name: FDCAN1SMEN - description: "FDCAN1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 9 - bit_size: 1 - - name: UCPD1SMEN - description: "UCPD1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 23 - bit_size: 1 + - name: I2C4SMEN + description: "I2C4 clocks enable during Sleep and Stop modes\r Set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 1 + bit_size: 1 + - name: LPTIM2SMEN + description: "LPTIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 + - name: I2C5SMEN + description: "I2C5 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 6 + bit_size: 1 + - name: I2C6SMEN + description: "I2C6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 7 + bit_size: 1 + - name: FDCAN1SMEN + description: "FDCAN1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 9 + bit_size: 1 + - name: UCPD1SMEN + description: "UCPD1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 23 + bit_size: 1 fieldset/APB2ENR: description: RCC APB2 peripheral clock enable register fields: - - name: TIM1EN - description: "TIM1 clock enable\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: "SPI1 clock enable\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: TIM8EN - description: "TIM8 clock enable\r Set and cleared by software." - bit_offset: 13 - bit_size: 1 - - name: USART1EN - description: "USART1clock enable\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: TIM15EN - description: "TIM15 clock enable\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: "TIM16 clock enable\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: "TIM17 clock enable\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: SAI1EN - description: "SAI1 clock enable\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: SAI2EN - description: "SAI2 clock enable\r Set and cleared by software." - bit_offset: 22 - bit_size: 1 - - name: USBEN - description: "USB clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 24 - bit_size: 1 - - name: GFXTIMEN - description: "GFXTIM clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 25 - bit_size: 1 - - name: LTDCEN - description: "LTDC clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 26 - bit_size: 1 - - name: DSIEN - description: "DSI clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 27 - bit_size: 1 + - name: TIM1EN + description: "TIM1 clock enable\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: "SPI1 clock enable\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: "TIM8 clock enable\r Set and cleared by software." + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: "USART1clock enable\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: "TIM15 clock enable\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: "TIM16 clock enable\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: "TIM17 clock enable\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: SAI1EN + description: "SAI1 clock enable\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: SAI2EN + description: "SAI2 clock enable\r Set and cleared by software." + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: "USB clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 24 + bit_size: 1 + - name: GFXTIMEN + description: "GFXTIM clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 25 + bit_size: 1 + - name: LTDCEN + description: "LTDC clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 26 + bit_size: 1 + - name: DSIEN + description: "DSI clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 27 + bit_size: 1 fieldset/APB2RSTR: description: RCC APB2 peripheral reset register fields: - - name: TIM1RST - description: "TIM1 reset\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: "SPI1 reset\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: TIM8RST - description: "TIM8 reset\r Set and cleared by software." - bit_offset: 13 - bit_size: 1 - - name: USART1RST - description: "USART1 reset\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: TIM15RST - description: "TIM15 reset\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: "TIM16 reset\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: "TIM17 reset\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: SAI1RST - description: "SAI1 reset\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: SAI2RST - description: "SAI2 reset\r Set and cleared by software." - bit_offset: 22 - bit_size: 1 - - name: USBRST - description: "USB reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 24 - bit_size: 1 - - name: GFXTIMRST - description: "GFXTIM reset\r This bit is set and cleared by software.\r Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 25 - bit_size: 1 - - name: LTDCRST - description: "LTDC reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 26 - bit_size: 1 - - name: DSIRST - description: "DSI reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 27 - bit_size: 1 + - name: TIM1RST + description: "TIM1 reset\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: "SPI1 reset\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: "TIM8 reset\r Set and cleared by software." + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: "USART1 reset\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: "TIM15 reset\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: "TIM16 reset\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: "TIM17 reset\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: SAI1RST + description: "SAI1 reset\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: SAI2RST + description: "SAI2 reset\r Set and cleared by software." + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: "USB reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 24 + bit_size: 1 + - name: GFXTIMRST + description: "GFXTIM reset\r This bit is set and cleared by software.\r Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 25 + bit_size: 1 + - name: LTDCRST + description: "LTDC reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 26 + bit_size: 1 + - name: DSIRST + description: "DSI reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 27 + bit_size: 1 fieldset/APB2SMENR: description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register fields: - - name: TIM1SMEN - description: "TIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: SPI1SMEN - description: "SPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 12 - bit_size: 1 - - name: TIM8SMEN - description: "TIM8 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 13 - bit_size: 1 - - name: USART1SMEN - description: "USART1clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 14 - bit_size: 1 - - name: TIM15SMEN - description: "TIM15 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: TIM16SMEN - description: "TIM16 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 17 - bit_size: 1 - - name: TIM17SMEN - description: "TIM17 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 18 - bit_size: 1 - - name: SAI1SMEN - description: "SAI1 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 - - name: SAI2SMEN - description: "SAI2 clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 22 - bit_size: 1 - - name: USBSMEN - description: "USB clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 24 - bit_size: 1 - - name: GFXTIMSMEN - description: "GFXTIM clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 25 - bit_size: 1 - - name: LTDCSMEN - description: "LTDC clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 26 - bit_size: 1 - - name: DSISMEN - description: "DSI clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 27 - bit_size: 1 + - name: TIM1SMEN + description: "TIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: "SPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 12 + bit_size: 1 + - name: TIM8SMEN + description: "TIM8 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 13 + bit_size: 1 + - name: USART1SMEN + description: "USART1clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 14 + bit_size: 1 + - name: TIM15SMEN + description: "TIM15 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: TIM16SMEN + description: "TIM16 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: "TIM17 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 18 + bit_size: 1 + - name: SAI1SMEN + description: "SAI1 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 + - name: SAI2SMEN + description: "SAI2 clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 22 + bit_size: 1 + - name: USBSMEN + description: "USB clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 24 + bit_size: 1 + - name: GFXTIMSMEN + description: "GFXTIM clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 25 + bit_size: 1 + - name: LTDCSMEN + description: "LTDC clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 26 + bit_size: 1 + - name: DSISMEN + description: "DSI clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 27 + bit_size: 1 fieldset/APB3ENR: description: RCC APB3 peripheral clock enable register fields: - - name: SYSCFGEN - description: "SYSCFG clock enable\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: SPI3EN - description: "SPI3 clock enable\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: LPUART1EN - description: "LPUART1 clock enable\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: I2C3EN - description: "I2C3 clock enable\r Set and cleared by software." - bit_offset: 7 - bit_size: 1 - - name: LPTIM1EN - description: "LPTIM1 clock enable\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: LPTIM3EN - description: "LPTIM3 clock enable\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: LPTIM4EN - description: "LPTIM4 clock enable\r Set and cleared by software." - bit_offset: 13 - bit_size: 1 - - name: OPAMPEN - description: "OPAMP clock enable\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: COMPEN - description: "COMP clock enable\r Set and cleared by software." - bit_offset: 15 - bit_size: 1 - - name: VREFEN - description: "VREFBUF clock enable\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: RTCAPBEN - description: "RTC and TAMP APB clock enable\r Set and cleared by software." - bit_offset: 21 - bit_size: 1 + - name: SYSCFGEN + description: "SYSCFG clock enable\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: SPI3EN + description: "SPI3 clock enable\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: LPUART1EN + description: "LPUART1 clock enable\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: I2C3EN + description: "I2C3 clock enable\r Set and cleared by software." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1EN + description: "LPTIM1 clock enable\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3EN + description: "LPTIM3 clock enable\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4EN + description: "LPTIM4 clock enable\r Set and cleared by software." + bit_offset: 13 + bit_size: 1 + - name: OPAMPEN + description: "OPAMP clock enable\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: COMPEN + description: "COMP clock enable\r Set and cleared by software." + bit_offset: 15 + bit_size: 1 + - name: VREFEN + description: "VREFBUF clock enable\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBEN + description: "RTC and TAMP APB clock enable\r Set and cleared by software." + bit_offset: 21 + bit_size: 1 fieldset/APB3RSTR: description: RCC APB3 peripheral reset register fields: - - name: SYSCFGRST - description: "SYSCFG reset\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: SPI3RST - description: "SPI3 reset\r Set and cleared by software." - bit_offset: 5 - bit_size: 1 - - name: LPUART1RST - description: "LPUART1 reset\r Set and cleared by software." - bit_offset: 6 - bit_size: 1 - - name: I2C3RST - description: "I2C3 reset\r Set and cleared by software." - bit_offset: 7 - bit_size: 1 - - name: LPTIM1RST - description: "LPTIM1 reset\r Set and cleared by software." - bit_offset: 11 - bit_size: 1 - - name: LPTIM3RST - description: "LPTIM3 reset\r Set and cleared by software." - bit_offset: 12 - bit_size: 1 - - name: LPTIM4RST - description: "LPTIM4 reset\r Set and cleared by software." - bit_offset: 13 - bit_size: 1 - - name: OPAMPRST - description: "OPAMP reset\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: COMPRST - description: "COMP reset\r Set and cleared by software." - bit_offset: 15 - bit_size: 1 - - name: VREFRST - description: "VREFBUF reset\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 + - name: SYSCFGRST + description: "SYSCFG reset\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: SPI3RST + description: "SPI3 reset\r Set and cleared by software." + bit_offset: 5 + bit_size: 1 + - name: LPUART1RST + description: "LPUART1 reset\r Set and cleared by software." + bit_offset: 6 + bit_size: 1 + - name: I2C3RST + description: "I2C3 reset\r Set and cleared by software." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1RST + description: "LPTIM1 reset\r Set and cleared by software." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3RST + description: "LPTIM3 reset\r Set and cleared by software." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4RST + description: "LPTIM4 reset\r Set and cleared by software." + bit_offset: 13 + bit_size: 1 + - name: OPAMPRST + description: "OPAMP reset\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: COMPRST + description: "COMP reset\r Set and cleared by software." + bit_offset: 15 + bit_size: 1 + - name: VREFRST + description: "VREFBUF reset\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 fieldset/APB3SMENR: description: RCC APB3 peripheral clock enable in Sleep and Stop modes register fields: - - name: SYSCFGSMEN - description: "SYSCFG clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 1 - bit_size: 1 - - name: SPI3SMEN - description: "SPI3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 5 - bit_size: 1 - - name: LPUART1SMEN - description: "LPUART1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 6 - bit_size: 1 - - name: I2C3SMEN - description: "I2C3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 7 - bit_size: 1 - - name: LPTIM1SMEN - description: "LPTIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 11 - bit_size: 1 - - name: LPTIM3SMEN - description: "LPTIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 12 - bit_size: 1 - - name: LPTIM4SMEN - description: "LPTIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 13 - bit_size: 1 - - name: OPAMPSMEN - description: "OPAMP clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: COMPSMEN - description: "COMP clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 15 - bit_size: 1 - - name: VREFSMEN - description: "VREFBUF clocks enable during Sleep and Stop modes\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: RTCAPBSMEN - description: "RTC and TAMP APB clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 21 - bit_size: 1 + - name: SYSCFGSMEN + description: "SYSCFG clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 1 + bit_size: 1 + - name: SPI3SMEN + description: "SPI3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 + - name: LPUART1SMEN + description: "LPUART1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 6 + bit_size: 1 + - name: I2C3SMEN + description: "I2C3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1SMEN + description: "LPTIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3SMEN + description: "LPTIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4SMEN + description: "LPTIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 13 + bit_size: 1 + - name: OPAMPSMEN + description: "OPAMP clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: COMPSMEN + description: "COMP clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 15 + bit_size: 1 + - name: VREFSMEN + description: "VREFBUF clocks enable during Sleep and Stop modes\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBSMEN + description: "RTC and TAMP APB clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 21 + bit_size: 1 fieldset/BDCR: description: RCC Backup domain control register fields: - - name: LSEON - description: "LSE oscillator enable\r Set and cleared by software." - bit_offset: 0 - bit_size: 1 - - name: LSERDY - description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles." - bit_offset: 1 - bit_size: 1 - - name: LSEBYP - description: "LSE oscillator bypass\r Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0)." - bit_offset: 2 - bit_size: 1 - - name: LSEDRV - description: "LSE oscillator drive capability\r Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).\r Note: The oscillator is in 'Xtal mode when it is not in bypass mode." - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: LSECSSON - description: "CSS on LSE enable\r Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit." - bit_offset: 5 - bit_size: 1 - - name: LSECSSD - description: "CSS on LSE failure Detection\r Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE)." - bit_offset: 6 - bit_size: 1 - - name: LSESYSEN - description: "LSE system clock (LSESYS) enable\r Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed.\r The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE." - bit_offset: 7 - bit_size: 1 - - name: RTCSEL - description: "RTC and TAMP clock source selection\r Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them." - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: LSESYSRDY - description: "LSE system clock (LSESYS) ready\r Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles.\r The LSE clock must be already enabled and stable (LSEON and LSERDY are set).\r When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles." - bit_offset: 11 - bit_size: 1 - - name: LSEGFON - description: "LSE clock glitch filter enable\r Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)" - bit_offset: 12 - bit_size: 1 - - name: RTCEN - description: "RTC and TAMP clock enable\r Set and cleared by software." - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: "Backup domain software reset\r Set and cleared by software." - bit_offset: 16 - bit_size: 1 - - name: LSCOEN - description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." - bit_offset: 24 - bit_size: 1 - - name: LSCOSEL - description: "Low-speed clock output selection\r Set and cleared by software." - bit_offset: 25 - bit_size: 1 - enum: LSCOSEL - - name: LSION - description: "LSI oscillator enable\r Set and cleared by software." - bit_offset: 26 - bit_size: 1 - - name: LSIRDY - description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0." - bit_offset: 27 - bit_size: 1 - - name: LSIPREDIV - description: "Low-speed clock divider configuration\r Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC." - bit_offset: 28 - bit_size: 1 - enum: LSIPREDIV + - name: LSEON + description: "LSE oscillator enable\r Set and cleared by software." + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles." + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: "LSE oscillator bypass\r Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0)." + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: "LSE oscillator drive capability\r Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).\r Note: The oscillator is in 'Xtal mode when it is not in bypass mode." + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: "CSS on LSE enable\r Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit." + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: "CSS on LSE failure Detection\r Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE)." + bit_offset: 6 + bit_size: 1 + - name: LSESYSEN + description: "LSE system clock (LSESYS) enable\r Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed.\r The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE." + bit_offset: 7 + bit_size: 1 + - name: RTCSEL + description: "RTC and TAMP clock source selection\r Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them." + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: LSESYSRDY + description: "LSE system clock (LSESYS) ready\r Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles.\r The LSE clock must be already enabled and stable (LSEON and LSERDY are set).\r When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles." + bit_offset: 11 + bit_size: 1 + - name: LSEGFON + description: "LSE clock glitch filter enable\r Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)" + bit_offset: 12 + bit_size: 1 + - name: RTCEN + description: "RTC and TAMP clock enable\r Set and cleared by software." + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: "Backup domain software reset\r Set and cleared by software." + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: "Low-speed clock output selection\r Set and cleared by software." + bit_offset: 25 + bit_size: 1 + enum: LSCOSEL + - name: LSION + description: "LSI oscillator enable\r Set and cleared by software." + bit_offset: 26 + bit_size: 1 + - name: LSIRDY + description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0." + bit_offset: 27 + bit_size: 1 + - name: LSIPREDIV + description: "Low-speed clock divider configuration\r Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC." + bit_offset: 28 + bit_size: 1 + enum: LSIPREDIV fieldset/CCIPR1: description: RCC peripherals independent clock configuration register 1 fields: - - name: USART1SEL - description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." - bit_offset: 0 - bit_size: 2 - enum: USART1SEL - - name: USART2SEL - description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." - bit_offset: 2 - bit_size: 2 - enum: USARTSEL - - name: USART3SEL - description: "USART3 kernel clock source selection\r This bits are used to select the USART3 kernel clock source.\r Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." - bit_offset: 4 - bit_size: 2 - enum: USARTSEL - - name: UART4SEL - description: "UART4 kernel clock source selection\r This bits are used to select the UART4 kernel clock source.\r Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." - bit_offset: 6 - bit_size: 2 - enum: USARTSEL - - name: UART5SEL - description: "UART5 kernel clock source selection\r These bits are used to select the UART5 kernel clock source.\r Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." - bit_offset: 8 - bit_size: 2 - enum: USARTSEL - - name: I2C1SEL - description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." - bit_offset: 10 - bit_size: 2 - enum: I2CSEL - - name: I2C2SEL - description: "I2C2 kernel clock source selection\r These bits are used to select the I2C2 kernel clock source.\r Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." - bit_offset: 12 - bit_size: 2 - enum: I2CSEL - - name: I2C4SEL - description: "I2C4 kernel clock source selection\r These bits are used to select the I2C4 kernel clock source.\r Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." - bit_offset: 14 - bit_size: 2 - enum: I2CSEL - - name: SPI2SEL - description: "SPI2 kernel clock source selection\r These bits are used to select the SPI2 kernel clock source.\r Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." - bit_offset: 16 - bit_size: 2 - enum: SPI2SEL - - name: LPTIM2SEL - description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1." - bit_offset: 18 - bit_size: 2 - enum: LPTIM2SEL - - name: SPI1SEL - description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." - bit_offset: 20 - bit_size: 2 - enum: SPI1SEL - - name: SYSTICKSEL - description: "SysTick clock source selection\r These bits are used to select the SysTick clock source.\r Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry." - bit_offset: 22 - bit_size: 2 - enum: SYSTICKSEL - - name: FDCAN1SEL - description: "FDCAN1 kernel clock source selection\r These bits are used to select the FDCAN1 kernel clock source." - bit_offset: 24 - bit_size: 2 - enum: FDCANSEL - - name: ICLKSEL - description: "intermediate clock source selection\r These bits are used to select the clock source used by OTG_FS and SDMMC." - bit_offset: 26 - bit_size: 2 - enum: ICLKSEL - - name: TIMICSEL - description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture\r When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS.\r When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r 0xx: HSI, MSIK and MSIS dividers disabled\r Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division." - bit_offset: 29 - bit_size: 3 - enum: TIMICSEL + - name: USART1SEL + description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." + bit_offset: 0 + bit_size: 2 + enum: USART1SEL + - name: USART2SEL + description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." + bit_offset: 2 + bit_size: 2 + enum: USARTSEL + - name: USART3SEL + description: "USART3 kernel clock source selection\r This bits are used to select the USART3 kernel clock source.\r Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." + bit_offset: 4 + bit_size: 2 + enum: USARTSEL + - name: UART4SEL + description: "UART4 kernel clock source selection\r This bits are used to select the UART4 kernel clock source.\r Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." + bit_offset: 6 + bit_size: 2 + enum: USARTSEL + - name: UART5SEL + description: "UART5 kernel clock source selection\r These bits are used to select the UART5 kernel clock source.\r Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." + bit_offset: 8 + bit_size: 2 + enum: USARTSEL + - name: I2C1SEL + description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." + bit_offset: 10 + bit_size: 2 + enum: I2CSEL + - name: I2C2SEL + description: "I2C2 kernel clock source selection\r These bits are used to select the I2C2 kernel clock source.\r Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." + bit_offset: 12 + bit_size: 2 + enum: I2CSEL + - name: I2C4SEL + description: "I2C4 kernel clock source selection\r These bits are used to select the I2C4 kernel clock source.\r Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." + bit_offset: 14 + bit_size: 2 + enum: I2CSEL + - name: SPI2SEL + description: "SPI2 kernel clock source selection\r These bits are used to select the SPI2 kernel clock source.\r Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." + bit_offset: 16 + bit_size: 2 + enum: SPI2SEL + - name: LPTIM2SEL + description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1." + bit_offset: 18 + bit_size: 2 + enum: LPTIM2SEL + - name: SPI1SEL + description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." + bit_offset: 20 + bit_size: 2 + enum: SPI1SEL + - name: SYSTICKSEL + description: "SysTick clock source selection\r These bits are used to select the SysTick clock source.\r Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry." + bit_offset: 22 + bit_size: 2 + enum: SYSTICKSEL + - name: FDCAN1SEL + description: "FDCAN1 kernel clock source selection\r These bits are used to select the FDCAN1 kernel clock source." + bit_offset: 24 + bit_size: 2 + enum: FDCANSEL + - name: ICLKSEL + description: "intermediate clock source selection\r These bits are used to select the clock source used by OTG_FS and SDMMC." + bit_offset: 26 + bit_size: 2 + enum: ICLKSEL + - name: TIMICSEL + description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture\r When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS.\r When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r 0xx: HSI, MSIK and MSIS dividers disabled\r Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division." + bit_offset: 29 + bit_size: 3 + enum: TIMICSEL fieldset/CCIPR2: description: RCC peripherals independent clock configuration register 2 fields: - - name: MDF1SEL - description: "MDF1 kernel clock source selection\r These bits are used to select the MDF1 kernel clock source.\r others: reserved" - bit_offset: 0 - bit_size: 3 - enum: MDFSEL - - name: SAI1SEL - description: "SAI1 kernel clock source selection\r These bits are used to select the SAI1 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible." - bit_offset: 5 - bit_size: 3 - enum: SAISEL - - name: SAI2SEL - description: "SAI2 kernel clock source selection\r These bits are used to select the SAI2 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible." - bit_offset: 8 - bit_size: 3 - enum: SAISEL - - name: SAESSEL - description: "SAES kernel clock source selection\r This bit is used to select the SAES kernel clock source." - bit_offset: 11 - bit_size: 1 - enum: SAESSEL - - name: RNGSEL - description: "RNGSEL kernel clock source selection\r These bits are used to select the RNG kernel clock source." - bit_offset: 12 - bit_size: 2 - enum: RNGSEL - - name: SDMMCSEL - description: "SDMMC1 and SDMMC2 kernel clock source selection\r This bit is used to select the SDMMC kernel clock source. It is recommended to change this bit only after reset and before enabling the SDMMC." - bit_offset: 14 - bit_size: 1 - enum: SDMMCSEL - - name: DSISEL - description: "DSI kernel clock source selection\r This bit is used to select the DSI kernel clock source.\r This bit is only available on some devices in the STM32U5 Series. \r Refer to the device datasheet for availability of its associated peripheral. \r Note: If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 15 - bit_size: 1 - enum: DSISEL - - name: USART6SEL - description: "USART6 kernel clock source selection\r These bits are used to select the USART6 kernel clock source.\r The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI or LSE.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." - bit_offset: 16 - bit_size: 2 - enum: USARTSEL - - name: LTDCSEL - description: "LTDC kernel clock source selection\r This bit is used to select the LTDC kernel clock source.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." - bit_offset: 18 - bit_size: 1 - enum: LTDCSEL - - name: OCTOSPISEL - description: "OCTOSPI1 and OCTOSPI2 kernel clock source selection\r These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source." - bit_offset: 20 - bit_size: 2 - enum: OCTOSPISEL - - name: HSPI1SEL - description: "HSPI1 kernel clock source selection\r These bits are used to select the HSPI1 kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." - bit_offset: 22 - bit_size: 2 - enum: HSPISEL - - name: I2C5SEL - description: "I2C5 kernel clock source selection\r These bits are used to select the I2C5 kernel clock source.\r The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." - bit_offset: 24 - bit_size: 2 - enum: I2CSEL - - name: I2C6SEL - description: "I2C6 kernel clock source selection\r These bits are used to select the I2C6 kernel clock source.\r The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." - bit_offset: 26 - bit_size: 2 - enum: I2CSEL - - name: OTGHSSEL - description: "OTG_HS PHY kernel clock source selection\r These bits are used to select the OTG_HS PHY kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." - bit_offset: 30 - bit_size: 2 - enum: OTGHSSEL + - name: MDF1SEL + description: "MDF1 kernel clock source selection\r These bits are used to select the MDF1 kernel clock source.\r others: reserved" + bit_offset: 0 + bit_size: 3 + enum: MDFSEL + - name: SAI1SEL + description: "SAI1 kernel clock source selection\r These bits are used to select the SAI1 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible." + bit_offset: 5 + bit_size: 3 + enum: SAISEL + - name: SAI2SEL + description: "SAI2 kernel clock source selection\r These bits are used to select the SAI2 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible." + bit_offset: 8 + bit_size: 3 + enum: SAISEL + - name: SAESSEL + description: "SAES kernel clock source selection\r This bit is used to select the SAES kernel clock source." + bit_offset: 11 + bit_size: 1 + enum: SAESSEL + - name: RNGSEL + description: "RNGSEL kernel clock source selection\r These bits are used to select the RNG kernel clock source." + bit_offset: 12 + bit_size: 2 + enum: RNGSEL + - name: SDMMCSEL + description: "SDMMC1 and SDMMC2 kernel clock source selection\r This bit is used to select the SDMMC kernel clock source. It is recommended to change this bit only after reset and before enabling the SDMMC." + bit_offset: 14 + bit_size: 1 + enum: SDMMCSEL + - name: DSISEL + description: "DSI kernel clock source selection\r This bit is used to select the DSI kernel clock source.\r This bit is only available on some devices in the STM32U5 Series. \r Refer to the device datasheet for availability of its associated peripheral. \r Note: If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 15 + bit_size: 1 + enum: DSISEL + - name: USART6SEL + description: "USART6 kernel clock source selection\r These bits are used to select the USART6 kernel clock source.\r The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI or LSE.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + bit_offset: 16 + bit_size: 2 + enum: USARTSEL + - name: LTDCSEL + description: "LTDC kernel clock source selection\r This bit is used to select the LTDC kernel clock source.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value." + bit_offset: 18 + bit_size: 1 + enum: LTDCSEL + - name: OCTOSPISEL + description: "OCTOSPI1 and OCTOSPI2 kernel clock source selection\r These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source." + bit_offset: 20 + bit_size: 2 + enum: OCTOSPISEL + - name: HSPI1SEL + description: "HSPI1 kernel clock source selection\r These bits are used to select the HSPI1 kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + bit_offset: 22 + bit_size: 2 + enum: HSPISEL + - name: I2C5SEL + description: "I2C5 kernel clock source selection\r These bits are used to select the I2C5 kernel clock source.\r The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + bit_offset: 24 + bit_size: 2 + enum: I2CSEL + - name: I2C6SEL + description: "I2C6 kernel clock source selection\r These bits are used to select the I2C6 kernel clock source.\r The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + bit_offset: 26 + bit_size: 2 + enum: I2CSEL + - name: OTGHSSEL + description: "OTG_HS PHY kernel clock source selection\r These bits are used to select the OTG_HS PHY kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + bit_offset: 30 + bit_size: 2 + enum: OTGHSSEL fieldset/CCIPR3: description: RCC peripherals independent clock configuration register 3 fields: - - name: LPUART1SEL - description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r others: reserved\r Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI, LSE or MSIK." - bit_offset: 0 - bit_size: 3 - enum: LPUSARTSEL - - name: SPI3SEL - description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK." - bit_offset: 3 - bit_size: 2 - enum: SPI3SEL - - name: I2C3SEL - description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK." - bit_offset: 6 - bit_size: 2 - enum: I2C3SEL - - name: LPTIM34SEL - description: "LPTIM3 and LPTIM4 kernel clock source selection\r These bits are used to select the LPTIM3 and LPTIM4 kernel clock source.\r Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1." - bit_offset: 8 - bit_size: 2 - enum: LPTIMSEL - - name: LPTIM1SEL - description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1." - bit_offset: 10 - bit_size: 2 - enum: LPTIMSEL - - name: ADCDACSEL - description: "ADC1, ADC4 and DAC1 kernel clock source selection\r These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source.\r others: reserved\r Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode)." - bit_offset: 12 - bit_size: 3 - enum: ADCDACSEL - - name: DAC1SEL - description: "DAC1 sample and hold clock source selection\r This bit is used to select the DAC1 sample and hold clock source." - bit_offset: 15 - bit_size: 1 - enum: DACSEL - - name: ADF1SEL - description: "ADF1 kernel clock source selection\r These bits are used to select the ADF1 kernel clock source.\r others: reserved\r Note: The ADF1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK." - bit_offset: 16 - bit_size: 3 - enum: ADFSEL + - name: LPUART1SEL + description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r others: reserved\r Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI, LSE or MSIK." + bit_offset: 0 + bit_size: 3 + enum: LPUSARTSEL + - name: SPI3SEL + description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK." + bit_offset: 3 + bit_size: 2 + enum: SPI3SEL + - name: I2C3SEL + description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK." + bit_offset: 6 + bit_size: 2 + enum: I2C3SEL + - name: LPTIM34SEL + description: "LPTIM3 and LPTIM4 kernel clock source selection\r These bits are used to select the LPTIM3 and LPTIM4 kernel clock source.\r Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1." + bit_offset: 8 + bit_size: 2 + enum: LPTIMSEL + - name: LPTIM1SEL + description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1." + bit_offset: 10 + bit_size: 2 + enum: LPTIMSEL + - name: ADCDACSEL + description: "ADC1, ADC4 and DAC1 kernel clock source selection\r These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source.\r others: reserved\r Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode)." + bit_offset: 12 + bit_size: 3 + enum: ADCDACSEL + - name: DAC1SEL + description: "DAC1 sample and hold clock source selection\r This bit is used to select the DAC1 sample and hold clock source." + bit_offset: 15 + bit_size: 1 + enum: DACSEL + - name: ADF1SEL + description: "ADF1 kernel clock source selection\r These bits are used to select the ADF1 kernel clock source.\r others: reserved\r Note: The ADF1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK." + bit_offset: 16 + bit_size: 3 + enum: ADFSEL fieldset/CFGR1: description: RCC clock configuration register 1 fields: - - name: SW - description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value." - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: "system clock switch status\r Set and cleared by hardware to indicate which clock source is used as system clock." - bit_offset: 2 - bit_size: 2 - enum: SW - - name: STOPWUCK - description: "wakeup from Stop and CSS backup clock selection\r Set and cleared by software to select the system clock used when exiting Stop mode.\r The selected clock is also used as emergency clock for the clock security system on HSE. Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in RCC_CR and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW = 10)." - bit_offset: 4 - bit_size: 1 - enum: STOPWUCK - - name: STOPKERWUCK - description: "wakeup from Stop kernel clock automatic enable selection\r Set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals." - bit_offset: 5 - bit_size: 1 - enum: STOPKERWUCK - - name: MCOSEL - description: "microcontroller clock output\r Set and cleared by software.\r Others: reserved\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching." - bit_offset: 24 - bit_size: 4 - enum: MCOSEL - - name: MCOPRE - description: "microcontroller clock output prescaler\r Set and cleared by software.\r It is highly recommended to change this prescaler before MCO output is enabled.\r Others: not allowed" - bit_offset: 28 - bit_size: 3 - enum: MCOPRE + - name: SW + description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value." + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: "system clock switch status\r Set and cleared by hardware to indicate which clock source is used as system clock." + bit_offset: 2 + bit_size: 2 + enum: SW + - name: STOPWUCK + description: "wakeup from Stop and CSS backup clock selection\r Set and cleared by software to select the system clock used when exiting Stop mode.\r The selected clock is also used as emergency clock for the clock security system on HSE. Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in RCC_CR and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW = 10)." + bit_offset: 4 + bit_size: 1 + enum: STOPWUCK + - name: STOPKERWUCK + description: "wakeup from Stop kernel clock automatic enable selection\r Set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals." + bit_offset: 5 + bit_size: 1 + enum: STOPKERWUCK + - name: MCOSEL + description: "microcontroller clock output\r Set and cleared by software.\r Others: reserved\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching." + bit_offset: 24 + bit_size: 4 + enum: MCOSEL + - name: MCOPRE + description: "microcontroller clock output prescaler\r Set and cleared by software.\r It is highly recommended to change this prescaler before MCO output is enabled.\r Others: not allowed" + bit_offset: 28 + bit_size: 3 + enum: MCOPRE fieldset/CFGR2: description: RCC clock configuration register 2 fields: - - name: HPRE - description: "AHB prescaler\r Set and cleared by software to control the division factor of the AHB clock (HCLK).\r Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xxx: SYSCLK not divided" - bit_offset: 0 - bit_size: 4 - enum: HPRE - - name: PPRE1 - description: "APB1 prescaler\r Set and cleared by software to control the division factor of the APB1 clock (PCLK1).\r 0xx: HCLK not divided" - bit_offset: 4 - bit_size: 3 - enum: PPRE - - name: PPRE2 - description: "APB2 prescaler\r Set and cleared by software to control the division factor of the APB2 clock (PCLK2).\r 0xx: HCLK not divided" - bit_offset: 8 - bit_size: 3 - enum: PPRE - - name: DPRE - description: "DSI PHY prescaler\r This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK).\r 0xx: DCLK not divided\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." - bit_offset: 12 - bit_size: 3 - enum: DPRE - - name: AHB1DIS - description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1." - bit_offset: 16 - bit_size: 1 - - name: AHB2DIS1 - description: "AHB2_1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3." - bit_offset: 17 - bit_size: 1 - - name: AHB2DIS2 - description: "AHB2_2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off." - bit_offset: 18 - bit_size: 1 - - name: APB1DIS - description: "APB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG." - bit_offset: 19 - bit_size: 1 - - name: APB2DIS - description: "APB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off." - bit_offset: 20 - bit_size: 1 + - name: HPRE + description: "AHB prescaler\r Set and cleared by software to control the division factor of the AHB clock (HCLK).\r Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xxx: SYSCLK not divided" + bit_offset: 0 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: "APB1 prescaler\r Set and cleared by software to control the division factor of the APB1 clock (PCLK1).\r 0xx: HCLK not divided" + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: "APB2 prescaler\r Set and cleared by software to control the division factor of the APB2 clock (PCLK2).\r 0xx: HCLK not divided" + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: DPRE + description: "DSI PHY prescaler\r This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK).\r 0xx: DCLK not divided\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + bit_offset: 12 + bit_size: 3 + enum: DPRE + - name: AHB1DIS + description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1." + bit_offset: 16 + bit_size: 1 + - name: AHB2DIS1 + description: "AHB2_1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3." + bit_offset: 17 + bit_size: 1 + - name: AHB2DIS2 + description: "AHB2_2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off." + bit_offset: 18 + bit_size: 1 + - name: APB1DIS + description: "APB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG." + bit_offset: 19 + bit_size: 1 + - name: APB2DIS + description: "APB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off." + bit_offset: 20 + bit_size: 1 fieldset/CFGR3: description: RCC clock configuration register 3 fields: - - name: PPRE3 - description: "APB3 prescaler\r Set and cleared by software to control the division factor of the APB3 clock (PCLK3).\r 0xx: HCLK not divided" - bit_offset: 4 - bit_size: 3 - enum: PPRE - - name: AHB3DIS - description: "AHB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4." - bit_offset: 16 - bit_size: 1 - - name: APB3DIS - description: "APB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off." - bit_offset: 17 - bit_size: 1 + - name: PPRE3 + description: "APB3 prescaler\r Set and cleared by software to control the division factor of the APB3 clock (PCLK3).\r 0xx: HCLK not divided" + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: AHB3DIS + description: "AHB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4." + bit_offset: 16 + bit_size: 1 + - name: APB3DIS + description: "APB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off." + bit_offset: 17 + bit_size: 1 fieldset/CICR: description: RCC clock interrupt clear register fields: - - name: LSIRDYC - description: "LSI ready interrupt clear\r Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect." - bit_offset: 0 - bit_size: 1 - - name: LSERDYC - description: "LSE ready interrupt clear\r Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect." - bit_offset: 1 - bit_size: 1 - - name: MSISRDYC - description: "MSIS ready interrupt clear\r Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect." - bit_offset: 2 - bit_size: 1 - - name: HSIRDYC - description: "HSI ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect." - bit_offset: 3 - bit_size: 1 - - name: HSERDYC - description: "HSE ready interrupt clear\r Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect." - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYC - description: "HSI48 ready interrupt clear\r Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect." - bit_offset: 5 - bit_size: 1 - - name: PLLRDYC - description: "PLL1 ready interrupt clear\r Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect." - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: CSSC - description: "Clock security system interrupt clear\r Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect." - bit_offset: 10 - bit_size: 1 - - name: MSIKRDYC - description: "MSIK oscillator ready interrupt clear\r Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect." - bit_offset: 11 - bit_size: 1 - - name: SHSIRDYC - description: "SHSI oscillator ready interrupt clear\r Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect." - bit_offset: 12 - bit_size: 1 + - name: LSIRDYC + description: "LSI ready interrupt clear\r Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect." + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: "LSE ready interrupt clear\r Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect." + bit_offset: 1 + bit_size: 1 + - name: MSISRDYC + description: "MSIS ready interrupt clear\r Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: "HSI ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect." + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: "HSE ready interrupt clear\r Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYC + description: "HSI48 ready interrupt clear\r Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYC + description: "PLL1 ready interrupt clear\r Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect." + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: CSSC + description: "Clock security system interrupt clear\r Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect." + bit_offset: 10 + bit_size: 1 + - name: MSIKRDYC + description: "MSIK oscillator ready interrupt clear\r Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect." + bit_offset: 11 + bit_size: 1 + - name: SHSIRDYC + description: "SHSI oscillator ready interrupt clear\r Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect." + bit_offset: 12 + bit_size: 1 fieldset/CIER: description: RCC clock interrupt enable register fields: - - name: LSIRDYIE - description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization." - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization." - bit_offset: 1 - bit_size: 1 - - name: MSISRDYIE - description: "MSIS ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization." - bit_offset: 2 - bit_size: 1 - - name: HSIRDYIE - description: "HSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization." - bit_offset: 3 - bit_size: 1 - - name: HSERDYIE - description: "HSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization." - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYIE - description: "HSI48 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization." - bit_offset: 5 - bit_size: 1 - - name: PLLRDYIE - description: "PLL ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by PLL1 lock." - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: MSIKRDYIE - description: "MSIK ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization." - bit_offset: 11 - bit_size: 1 - - name: SHSIRDYIE - description: "SHSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization." - bit_offset: 12 - bit_size: 1 + - name: LSIRDYIE + description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization." + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization." + bit_offset: 1 + bit_size: 1 + - name: MSISRDYIE + description: "MSIS ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: "HSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization." + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: "HSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYIE + description: "HSI48 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYIE + description: "PLL ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by PLL1 lock." + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: MSIKRDYIE + description: "MSIK ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization." + bit_offset: 11 + bit_size: 1 + - name: SHSIRDYIE + description: "SHSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization." + bit_offset: 12 + bit_size: 1 fieldset/CIFR: description: RCC clock interrupt flag register fields: - - name: LSIRDYF - description: "LSI ready interrupt flag\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.\r Cleared by software setting the LSIRDYC bit." - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: "LSE ready interrupt flag\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set.\r Cleared by software setting the LSERDYC bit." - bit_offset: 1 - bit_size: 1 - - name: MSISRDYF - description: "MSIS ready interrupt flag\r Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set.\r Cleared by software setting the MSISRDYC bit." - bit_offset: 2 - bit_size: 1 - - name: HSIRDYF - description: "HSI ready interrupt flag\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit." - bit_offset: 3 - bit_size: 1 - - name: HSERDYF - description: "HSE ready interrupt flag\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit." - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYF - description: "HSI48 ready interrupt flag\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.\r Cleared by software setting the HSI48RDYC bit." - bit_offset: 5 - bit_size: 1 - - name: PLLRDYF - description: "PLL1 ready interrupt flag\r Set by hardware when the PLL1 locks and PLL1RDYIE is set.\r Cleared by software setting the PLL1RDYC bit." - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: CSSF - description: "Clock security system interrupt flag\r Set by hardware when a failure is detected in the HSE oscillator.\r Cleared by software setting the CSSC bit." - bit_offset: 10 - bit_size: 1 - - name: MSIKRDYF - description: "MSIK ready interrupt flag\r Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set.\r Cleared by software setting the MSIKRDYC bit." - bit_offset: 11 - bit_size: 1 - - name: SHSIRDYF - description: "SHSI ready interrupt flag\r Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set.\r Cleared by software setting the SHSIRDYC bit." - bit_offset: 12 - bit_size: 1 + - name: LSIRDYF + description: "LSI ready interrupt flag\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.\r Cleared by software setting the LSIRDYC bit." + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: "LSE ready interrupt flag\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set.\r Cleared by software setting the LSERDYC bit." + bit_offset: 1 + bit_size: 1 + - name: MSISRDYF + description: "MSIS ready interrupt flag\r Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set.\r Cleared by software setting the MSISRDYC bit." + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: "HSI ready interrupt flag\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit." + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: "HSE ready interrupt flag\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit." + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYF + description: "HSI48 ready interrupt flag\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.\r Cleared by software setting the HSI48RDYC bit." + bit_offset: 5 + bit_size: 1 + - name: PLLRDYF + description: "PLL1 ready interrupt flag\r Set by hardware when the PLL1 locks and PLL1RDYIE is set.\r Cleared by software setting the PLL1RDYC bit." + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: CSSF + description: "Clock security system interrupt flag\r Set by hardware when a failure is detected in the HSE oscillator.\r Cleared by software setting the CSSC bit." + bit_offset: 10 + bit_size: 1 + - name: MSIKRDYF + description: "MSIK ready interrupt flag\r Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set.\r Cleared by software setting the MSIKRDYC bit." + bit_offset: 11 + bit_size: 1 + - name: SHSIRDYF + description: "SHSI ready interrupt flag\r Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set.\r Cleared by software setting the SHSIRDYC bit." + bit_offset: 12 + bit_size: 1 fieldset/CR: description: RCC clock control register fields: - - name: MSISON - description: "MSIS clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator.\r Set by hardware when used directly or indirectly as system clock." - bit_offset: 0 - bit_size: 1 - - name: MSIKERON - description: "MSI enable for some peripheral kernels\r Set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI ON in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see autonomous mode for more details).\r The MSIKERON must be configured at 0 before entering Stop 3 mode." - bit_offset: 1 - bit_size: 1 - - name: MSISRDY - description: "MSIS clock ready flag\r Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON.\r Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles." - bit_offset: 2 - bit_size: 1 - - name: MSIPLLEN - description: "MSI clock PLL-mode enable\r Set and cleared by software to enable/disable the PLL part of the MSI clock source.\r MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready.\r This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR)." - bit_offset: 3 - bit_size: 1 - - name: MSIKON - description: "MSIK clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIK when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when STOPWUCK = 0 or STOPKERWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator." - bit_offset: 4 - bit_size: 1 - - name: MSIKRDY - description: "MSIK clock ready flag\r Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON.\r Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles." - bit_offset: 5 - bit_size: 1 - - name: MSIPLLSEL - description: "MSI clock with PLL mode selection\r Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0).\r Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs." - bit_offset: 6 - bit_size: 1 - enum: MSIPLLSEL - - name: MSIPLLFAST - description: "MSI PLL mode fast startup\r Set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock\r source. This bit is used only if PLL mode is selected (MSIPLLEN = 1).\r The fast start-up feature is not active the first time the PLL mode is selected. The fast start-up is active when the MSI in PLL mode returns from switch off." - bit_offset: 7 - bit_size: 1 - enum: MSIPLLFAST - - name: HSION - description: "HSI clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the HSI oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.\r This bit is set by hardware if the HSI is used directly or indirectly as system clock." - bit_offset: 8 - bit_size: 1 - - name: HSIKERON - description: "HSI enable for some peripheral kernels\r Set and cleared by software to force HSI ON even in Stop modes. Keeping the HSI ON in Stop mode allows the communication speed not to be reduced by the HSI startup time. This bit has no effect on HSION value.\r Refer to for more details.\r The HSIKERON must be configured at 0 before entering Stop 3 mode." - bit_offset: 9 - bit_size: 1 - - name: HSIRDY - description: "HSI clock ready flag\r Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI clock cycles." - bit_offset: 10 - bit_size: 1 - - name: HSI48ON - description: "HSI48 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes." - bit_offset: 12 - bit_size: 1 - - name: HSI48RDY - description: "HSI48 clock ready flag\r Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON." - bit_offset: 13 - bit_size: 1 - - name: SHSION - description: "SHSI clock enable\r Set and cleared by software.\r Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes." - bit_offset: 14 - bit_size: 1 - - name: SHSIRDY - description: "SHSI clock ready flag\r Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION.\r Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles." - bit_offset: 15 - bit_size: 1 - - name: HSEON - description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock." - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable.\r Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles." - bit_offset: 17 - bit_size: 1 - - name: HSEBYP - description: "HSE crystal oscillator bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled." - bit_offset: 18 - bit_size: 1 - - name: CSSON - description: "Clock security system enable\r Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset." - bit_offset: 19 - bit_size: 1 - - name: HSEEXT - description: "HSE external clock bypass mode\r Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled." - bit_offset: 20 - bit_size: 1 - enum: HSEEXT - - name: PLLON - description: "PLL1 enable\r Set and cleared by software to enable the main PLL.\r Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock." - bit_offset: 24 - bit_size: 1 - array: - len: 3 - stride: 2 - - name: PLLRDY - description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked." - bit_offset: 25 - bit_size: 1 - array: - len: 3 - stride: 2 + - name: MSISON + description: "MSIS clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator.\r Set by hardware when used directly or indirectly as system clock." + bit_offset: 0 + bit_size: 1 + - name: MSIKERON + description: "MSI enable for some peripheral kernels\r Set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI ON in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see autonomous mode for more details).\r The MSIKERON must be configured at 0 before entering Stop 3 mode." + bit_offset: 1 + bit_size: 1 + - name: MSISRDY + description: "MSIS clock ready flag\r Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON.\r Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles." + bit_offset: 2 + bit_size: 1 + - name: MSIPLLEN + description: "MSI clock PLL-mode enable\r Set and cleared by software to enable/disable the PLL part of the MSI clock source.\r MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready.\r This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR)." + bit_offset: 3 + bit_size: 1 + - name: MSIKON + description: "MSIK clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIK when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when STOPWUCK = 0 or STOPKERWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator." + bit_offset: 4 + bit_size: 1 + - name: MSIKRDY + description: "MSIK clock ready flag\r Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON.\r Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles." + bit_offset: 5 + bit_size: 1 + - name: MSIPLLSEL + description: "MSI clock with PLL mode selection\r Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0).\r Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs." + bit_offset: 6 + bit_size: 1 + enum: MSIPLLSEL + - name: MSIPLLFAST + description: "MSI PLL mode fast startup\r Set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock\r source. This bit is used only if PLL mode is selected (MSIPLLEN = 1).\r The fast start-up feature is not active the first time the PLL mode is selected. The fast start-up is active when the MSI in PLL mode returns from switch off." + bit_offset: 7 + bit_size: 1 + enum: MSIPLLFAST + - name: HSION + description: "HSI clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the HSI oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.\r This bit is set by hardware if the HSI is used directly or indirectly as system clock." + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: "HSI enable for some peripheral kernels\r Set and cleared by software to force HSI ON even in Stop modes. Keeping the HSI ON in Stop mode allows the communication speed not to be reduced by the HSI startup time. This bit has no effect on HSION value.\r Refer to for more details.\r The HSIKERON must be configured at 0 before entering Stop 3 mode." + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: "HSI clock ready flag\r Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI clock cycles." + bit_offset: 10 + bit_size: 1 + - name: HSI48ON + description: "HSI48 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes." + bit_offset: 12 + bit_size: 1 + - name: HSI48RDY + description: "HSI48 clock ready flag\r Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON." + bit_offset: 13 + bit_size: 1 + - name: SHSION + description: "SHSI clock enable\r Set and cleared by software.\r Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes." + bit_offset: 14 + bit_size: 1 + - name: SHSIRDY + description: "SHSI clock ready flag\r Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION.\r Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles." + bit_offset: 15 + bit_size: 1 + - name: HSEON + description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock." + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable.\r Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles." + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: "HSE crystal oscillator bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled." + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: "Clock security system enable\r Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset." + bit_offset: 19 + bit_size: 1 + - name: HSEEXT + description: "HSE external clock bypass mode\r Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled." + bit_offset: 20 + bit_size: 1 + enum: HSEEXT + - name: PLLON + description: "PLL1 enable\r Set and cleared by software to enable the main PLL.\r Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock." + bit_offset: 24 + bit_size: 1 + array: + len: 3 + stride: 2 + - name: PLLRDY + description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked." + bit_offset: 25 + bit_size: 1 + array: + len: 3 + stride: 2 fieldset/CRRCR: description: RCC clock recovery RC register fields: - - name: HSI48CAL - description: "HSI48 clock calibration\r These bits are initialized at startup with the factory-programmed HSI48 calibration trim value." - bit_offset: 0 - bit_size: 9 + - name: HSI48CAL + description: "HSI48 clock calibration\r These bits are initialized at startup with the factory-programmed HSI48 calibration trim value." + bit_offset: 0 + bit_size: 9 fieldset/CSR: description: RCC control/status register fields: - - name: MSIKSRANGE - description: "MSIK range after Standby mode\r Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSIKSRANGE does not change the current MSIK frequency." - bit_offset: 8 - bit_size: 4 - enum: MSIXSRANGE - - name: MSISSRANGE - description: "MSIS range after Standby mode\r Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSISSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSISSRANGE does not change the current MSIS frequency." - bit_offset: 12 - bit_size: 4 - enum: MSIXSRANGE - - name: RMVF - description: "Remove reset flag\r Set by software to clear the reset flags." - bit_offset: 23 - bit_size: 1 - - name: OBLRSTF - description: "Option byte loader reset flag\r Set by hardware when a reset from the option byte loading occurs.\r Cleared by writing to the RMVF bit." - bit_offset: 25 - bit_size: 1 - - name: PINRSTF - description: "NRST pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by writing to the RMVF bit." - bit_offset: 26 - bit_size: 1 - - name: BORRSTF - description: "BOR flag\r Set by hardware when a BOR occurs.\r Cleared by writing to the RMVF bit." - bit_offset: 27 - bit_size: 1 - - name: SFTRSTF - description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by writing to the RMVF bit." - bit_offset: 28 - bit_size: 1 - - name: IWDGRSTF - description: "Independent watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by writing to the RMVF bit." - bit_offset: 29 - bit_size: 1 - - name: WWDGRSTF - description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by writing to the RMVF bit." - bit_offset: 30 - bit_size: 1 - - name: LPWRRSTF - description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared.\r Cleared by writing to the RMVF bit." - bit_offset: 31 - bit_size: 1 + - name: MSIKSRANGE + description: "MSIK range after Standby mode\r Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSIKSRANGE does not change the current MSIK frequency." + bit_offset: 8 + bit_size: 4 + enum: MSIXSRANGE + - name: MSISSRANGE + description: "MSIS range after Standby mode\r Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSISSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSISSRANGE does not change the current MSIS frequency." + bit_offset: 12 + bit_size: 4 + enum: MSIXSRANGE + - name: RMVF + description: "Remove reset flag\r Set by software to clear the reset flags." + bit_offset: 23 + bit_size: 1 + - name: OBLRSTF + description: "Option byte loader reset flag\r Set by hardware when a reset from the option byte loading occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: "NRST pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: "BOR flag\r Set by hardware when a BOR occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: "Independent watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared.\r Cleared by writing to the RMVF bit." + bit_offset: 31 + bit_size: 1 fieldset/ICSCR1: description: RCC internal clock sources calibration register 1 fields: - - name: MSICAL3 - description: "MSIRC3 clock calibration for MSI ranges 12 to 15\r These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." - bit_offset: 0 - bit_size: 5 - - name: MSICAL2 - description: "MSIRC2 clock calibration for MSI ranges 8 to 11\r These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." - bit_offset: 5 - bit_size: 5 - - name: MSICAL1 - description: "MSIRC1 clock calibration for MSI ranges 4 to 7\r These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." - bit_offset: 10 - bit_size: 5 - - name: MSICAL0 - description: "MSIRC0 clock calibration for MSI ranges 0 to 3\r These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0]." - bit_offset: 15 - bit_size: 5 - - name: MSIBIAS - description: "MSI bias mode selection\r Set by software to select the MSI bias mode. By default, the MSI bias is in continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy." - bit_offset: 22 - bit_size: 1 - enum: MSIBIAS - - name: MSIRGSEL - description: "MSI clock range selection\r Set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect.\r After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR." - bit_offset: 23 - bit_size: 1 - enum: MSIRGSEL - - name: MSIKRANGE - description: "MSIK clock ranges\r These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY = 1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0)\r MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz)." - bit_offset: 24 - bit_size: 4 - enum: MSIRANGE - - name: MSISRANGE - description: "MSIS clock ranges\r These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY = 1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON = 1 and MSISRDY = 0)\r MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz)." - bit_offset: 28 - bit_size: 4 - enum: MSIRANGE + - name: MSICAL3 + description: "MSIRC3 clock calibration for MSI ranges 12 to 15\r These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." + bit_offset: 0 + bit_size: 5 + - name: MSICAL2 + description: "MSIRC2 clock calibration for MSI ranges 8 to 11\r These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." + bit_offset: 5 + bit_size: 5 + - name: MSICAL1 + description: "MSIRC1 clock calibration for MSI ranges 4 to 7\r These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." + bit_offset: 10 + bit_size: 5 + - name: MSICAL0 + description: "MSIRC0 clock calibration for MSI ranges 0 to 3\r These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0]." + bit_offset: 15 + bit_size: 5 + - name: MSIBIAS + description: "MSI bias mode selection\r Set by software to select the MSI bias mode. By default, the MSI bias is in continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy." + bit_offset: 22 + bit_size: 1 + enum: MSIBIAS + - name: MSIRGSEL + description: "MSI clock range selection\r Set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect.\r After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR." + bit_offset: 23 + bit_size: 1 + enum: MSIRGSEL + - name: MSIKRANGE + description: "MSIK clock ranges\r These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY = 1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0)\r MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz)." + bit_offset: 24 + bit_size: 4 + enum: MSIRANGE + - name: MSISRANGE + description: "MSIS clock ranges\r These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY = 1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON = 1 and MSISRDY = 0)\r MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz)." + bit_offset: 28 + bit_size: 4 + enum: MSIRANGE fieldset/ICSCR2: description: RCC internal clock sources calibration register 2 fields: - - name: MSITRIM3 - description: "MSI clock trimming for ranges 12 to 15\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." - bit_offset: 0 - bit_size: 5 - - name: MSITRIM2 - description: "MSI clock trimming for ranges 8 to 11\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." - bit_offset: 5 - bit_size: 5 - - name: MSITRIM1 - description: "MSI clock trimming for ranges 4 to 7\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." - bit_offset: 10 - bit_size: 5 - - name: MSITRIM0 - description: "MSI clock trimming for ranges 0 to 3\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." - bit_offset: 15 - bit_size: 5 + - name: MSITRIM3 + description: "MSI clock trimming for ranges 12 to 15\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." + bit_offset: 0 + bit_size: 5 + - name: MSITRIM2 + description: "MSI clock trimming for ranges 8 to 11\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." + bit_offset: 5 + bit_size: 5 + - name: MSITRIM1 + description: "MSI clock trimming for ranges 4 to 7\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." + bit_offset: 10 + bit_size: 5 + - name: MSITRIM0 + description: "MSI clock trimming for ranges 0 to 3\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." + bit_offset: 15 + bit_size: 5 fieldset/ICSCR3: description: RCC internal clock sources calibration register 3 fields: - - name: HSICAL - description: "HSI clock calibration\r These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value." - bit_offset: 0 - bit_size: 12 - - name: HSITRIM - description: "HSI clock trimming\r These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI." - bit_offset: 16 - bit_size: 5 + - name: HSICAL + description: "HSI clock calibration\r These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value." + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: "HSI clock trimming\r These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI." + bit_offset: 16 + bit_size: 5 fieldset/PLL1CFGR: description: RCC PLL configuration register fields: - - name: PLLSRC - description: "PLL entry clock source\r Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled.\r In order to save power, when no PLL is used, the value of PLLSRC must be 0." - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: PLLRGE - description: "PLL input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL.\r This bit must be written before enabling the PLL.\r 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz" - bit_offset: 2 - bit_size: 2 - enum: PLLRGE - - name: PLLFRACEN - description: "PLL fractional latch enable\r Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator.\r In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details)." - bit_offset: 4 - bit_size: 1 - - name: PLLM - description: "Prescaler for PLL\r Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).\r ..." - bit_offset: 8 - bit_size: 4 - enum: PLLM - - name: PLLMBOOST - description: "Prescaler for EPOD booster input clock\r Set and cleared by software to configure the prescaler of the PLL, used for the EPOD booster. The EPOD booster input frequency is PLL input clock frequency/PLLMBOOST.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0) and EPOD Boost mode is disabled (see ).\r others: reserved" - bit_offset: 12 - bit_size: 4 - enum: PLLMBOOST - - name: PLLPEN - description: "PLL DIVP divider output enable\r Set and reset by software to enable the PLL_p_ck output of the PLL.\r To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)." - bit_offset: 16 - bit_size: 1 - - name: PLLQEN - description: "PLL DIVQ divider output enable\r Set and reset by software to enable the PLL_q_ck output of the PLL.\r To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)." - bit_offset: 17 - bit_size: 1 - - name: PLLREN - description: "PLL DIVR divider output enable\r Set and reset by software to enable the PLL_r_ck output of the PLL.\r To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)." - bit_offset: 18 - bit_size: 1 + - name: PLLSRC + description: "PLL entry clock source\r Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled.\r In order to save power, when no PLL is used, the value of PLLSRC must be 0." + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLRGE + description: "PLL input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL.\r This bit must be written before enabling the PLL.\r 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz" + bit_offset: 2 + bit_size: 2 + enum: PLLRGE + - name: PLLFRACEN + description: "PLL fractional latch enable\r Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator.\r In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details)." + bit_offset: 4 + bit_size: 1 + - name: PLLM + description: "Prescaler for PLL\r Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).\r ..." + bit_offset: 8 + bit_size: 4 + enum: PLLM + - name: PLLMBOOST + description: "Prescaler for EPOD booster input clock\r Set and cleared by software to configure the prescaler of the PLL, used for the EPOD booster. The EPOD booster input frequency is PLL input clock frequency/PLLMBOOST.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0) and EPOD Boost mode is disabled (see ).\r others: reserved" + bit_offset: 12 + bit_size: 4 + enum: PLLMBOOST + - name: PLLPEN + description: "PLL DIVP divider output enable\r Set and reset by software to enable the PLL_p_ck output of the PLL.\r To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)." + bit_offset: 16 + bit_size: 1 + - name: PLLQEN + description: "PLL DIVQ divider output enable\r Set and reset by software to enable the PLL_q_ck output of the PLL.\r To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)." + bit_offset: 17 + bit_size: 1 + - name: PLLREN + description: "PLL DIVR divider output enable\r Set and reset by software to enable the PLL_r_ck output of the PLL.\r To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)." + bit_offset: 18 + bit_size: 1 fieldset/PLL23CFGR: description: RCC PLL configuration register fields: - - name: PLLSRC - description: "PLL entry clock source\r Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled.\r In order to save power, when no PLL is used, the value of PLLSRC must be 0." - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: PLLRGE - description: "PLL input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL.\r This bit must be written before enabling the PLL.\r 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz" - bit_offset: 2 - bit_size: 2 - enum: PLLRGE - - name: PLLFRACEN - description: "PLL fractional latch enable\r Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator.\r In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details)." - bit_offset: 4 - bit_size: 1 - - name: PLLM - description: "Prescaler for PLL\r Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).\r ..." - bit_offset: 8 - bit_size: 4 - enum: PLLM - - name: PLLPEN - description: "PLL DIVP divider output enable\r Set and reset by software to enable the PLL_p_ck output of the PLL.\r To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)." - bit_offset: 16 - bit_size: 1 - - name: PLLQEN - description: "PLL DIVQ divider output enable\r Set and reset by software to enable the PLL_q_ck output of the PLL.\r To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)." - bit_offset: 17 - bit_size: 1 - - name: PLLREN - description: "PLL DIVR divider output enable\r Set and reset by software to enable the PLL_r_ck output of the PLL.\r To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)." - bit_offset: 18 - bit_size: 1 + - name: PLLSRC + description: "PLL entry clock source\r Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled.\r In order to save power, when no PLL is used, the value of PLLSRC must be 0." + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLRGE + description: "PLL input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL.\r This bit must be written before enabling the PLL.\r 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz" + bit_offset: 2 + bit_size: 2 + enum: PLLRGE + - name: PLLFRACEN + description: "PLL fractional latch enable\r Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator.\r In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details)." + bit_offset: 4 + bit_size: 1 + - name: PLLM + description: "Prescaler for PLL\r Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).\r ..." + bit_offset: 8 + bit_size: 4 + enum: PLLM + - name: PLLPEN + description: "PLL DIVP divider output enable\r Set and reset by software to enable the PLL_p_ck output of the PLL.\r To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)." + bit_offset: 16 + bit_size: 1 + - name: PLLQEN + description: "PLL DIVQ divider output enable\r Set and reset by software to enable the PLL_q_ck output of the PLL.\r To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)." + bit_offset: 17 + bit_size: 1 + - name: PLLREN + description: "PLL DIVR divider output enable\r Set and reset by software to enable the PLL_r_ck output of the PLL.\r To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)." + bit_offset: 18 + bit_size: 1 fieldset/PLLDIVR: description: RCC PLL1 dividers register fields: - - name: PLLN - description: "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with:\r PLL1N between 4 and 512\r input frequency Fref1_ck between 4 and 16 MHz" - bit_offset: 0 - bit_size: 9 - enum: PLLN - - name: PLLP - description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." - bit_offset: 9 - bit_size: 7 - enum: PLLDIV - - name: PLLQ - description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." - bit_offset: 16 - bit_size: 7 - enum: PLLDIV - - name: PLLR - description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." - bit_offset: 24 - bit_size: 7 - enum: PLLDIV + - name: PLLN + description: "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with:\r PLL1N between 4 and 512\r input frequency Fref1_ck between 4 and 16 MHz" + bit_offset: 0 + bit_size: 9 + enum: PLLN + - name: PLLP + description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." + bit_offset: 9 + bit_size: 7 + enum: PLLDIV + - name: PLLQ + description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 16 + bit_size: 7 + enum: PLLDIV + - name: PLLR + description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 24 + bit_size: 7 + enum: PLLDIV fieldset/PLLFRACR: description: RCC PLL1 fractional divider register fields: - - name: PLLFRACN - description: "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with:\r PLL1N must be between 4 and 512.\r PLL1FRACN can be between 0 and 213- 1.\r The input frequency Fref1_ck must be between 4 and 16 MHz.\r To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0.\r Write the new fractional value into PLL1FRACN.\r Set the bit PLL1FRACEN to 1." - bit_offset: 3 - bit_size: 13 + - name: PLLFRACN + description: "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with:\r PLL1N must be between 4 and 512.\r PLL1FRACN can be between 0 and 213- 1.\r The input frequency Fref1_ck must be between 4 and 16 MHz.\r To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0.\r Write the new fractional value into PLL1FRACN.\r Set the bit PLL1FRACEN to 1." + bit_offset: 3 + bit_size: 13 fieldset/PRIVCFGR: description: RCC privilege configuration register fields: - - name: SPRIV - description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." - bit_offset: 0 - bit_size: 1 - - name: NSPRIV - description: "RCC non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." - bit_offset: 1 - bit_size: 1 + - name: SPRIV + description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." + bit_offset: 0 + bit_size: 1 + - name: NSPRIV + description: "RCC non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." + bit_offset: 1 + bit_size: 1 fieldset/SECCFGR: description: RCC secure configuration register fields: - - name: HSISEC - description: "HSI clock configuration and status bits security\r Set and reset by software." - bit_offset: 0 - bit_size: 1 - enum: SECURITY - - name: HSESEC - description: "HSE clock configuration bits, status bits and HSE_CSS security\r Set and reset by software." - bit_offset: 1 - bit_size: 1 - enum: SECURITY - - name: MSISEC - description: "MSI clock configuration and status bits security\r Set and reset by software." - bit_offset: 2 - bit_size: 1 - enum: SECURITY - - name: LSISEC - description: "LSI clock configuration and status bits security\r Set and reset by software." - bit_offset: 3 - bit_size: 1 - enum: SECURITY - - name: LSESEC - description: "LSE clock configuration and status bits security\r Set and reset by software." - bit_offset: 4 - bit_size: 1 - enum: SECURITY - - name: SYSCLKSEC - description: "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security\r Set and reset by software." - bit_offset: 5 - bit_size: 1 - enum: SECURITY - - name: PRESCSEC - description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software." - bit_offset: 6 - bit_size: 1 - enum: SECURITY - - name: PLLSEC - description: "PLL1 clock configuration and status bits security\r Set and reset by software." - bit_offset: 7 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: SECURITY - - name: ICLKSEC - description: "intermediate clock source selection security\r Set and reset by software." - bit_offset: 10 - bit_size: 1 - enum: SECURITY - - name: HSI48SEC - description: "HSI48 clock configuration and status bits security\r Set and reset by software." - bit_offset: 11 - bit_size: 1 - enum: SECURITY - - name: RMVFSEC - description: "Remove reset flag security\r Set and reset by software." - bit_offset: 12 - bit_size: 1 - enum: SECURITY + - name: HSISEC + description: "HSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + enum: SECURITY + - name: HSESEC + description: "HSE clock configuration bits, status bits and HSE_CSS security\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + enum: SECURITY + - name: MSISEC + description: "MSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 2 + bit_size: 1 + enum: SECURITY + - name: LSISEC + description: "LSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + enum: SECURITY + - name: LSESEC + description: "LSE clock configuration and status bits security\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + enum: SECURITY + - name: SYSCLKSEC + description: "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + enum: SECURITY + - name: PRESCSEC + description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + enum: SECURITY + - name: PLLSEC + description: "PLL1 clock configuration and status bits security\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: SECURITY + - name: ICLKSEC + description: "intermediate clock source selection security\r Set and reset by software." + bit_offset: 10 + bit_size: 1 + enum: SECURITY + - name: HSI48SEC + description: "HSI48 clock configuration and status bits security\r Set and reset by software." + bit_offset: 11 + bit_size: 1 + enum: SECURITY + - name: RMVFSEC + description: "Remove reset flag security\r Set and reset by software." + bit_offset: 12 + bit_size: 1 + enum: SECURITY fieldset/SRDAMR: description: RCC SmartRun domain peripheral autonomous mode register fields: - - name: SPI3AMEN - description: "SPI3 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 5 - bit_size: 1 - - name: LPUART1AMEN - description: "LPUART1 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 6 - bit_size: 1 - - name: I2C3AMEN - description: "I2C3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 7 - bit_size: 1 - - name: LPTIM1AMEN - description: "LPTIM1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 11 - bit_size: 1 - - name: LPTIM3AMEN - description: "LPTIM3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 12 - bit_size: 1 - - name: LPTIM4AMEN - description: "LPTIM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 13 - bit_size: 1 - - name: OPAMPAMEN - description: "OPAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." - bit_offset: 14 - bit_size: 1 - - name: COMPAMEN - description: "COMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." - bit_offset: 15 - bit_size: 1 - - name: VREFAMEN - description: "VREFBUF autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." - bit_offset: 20 - bit_size: 1 - - name: RTCAPBAMEN - description: "RTC and TAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 21 - bit_size: 1 - - name: ADC4AMEN - description: "ADC4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 25 - bit_size: 1 - - name: LPGPIO1AMEN - description: "LPGPIO1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." - bit_offset: 26 - bit_size: 1 - - name: DAC1AMEN - description: "DAC1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 27 - bit_size: 1 - - name: LPDMA1AMEN - description: "LPDMA1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 28 - bit_size: 1 - - name: ADF1AMEN - description: "ADF1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." - bit_offset: 29 - bit_size: 1 - - name: SRAM4AMEN - description: "SRAM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." - bit_offset: 31 - bit_size: 1 + - name: SPI3AMEN + description: "SPI3 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 + - name: LPUART1AMEN + description: "LPUART1 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 6 + bit_size: 1 + - name: I2C3AMEN + description: "I2C3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1AMEN + description: "LPTIM1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 11 + bit_size: 1 + - name: LPTIM3AMEN + description: "LPTIM3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 12 + bit_size: 1 + - name: LPTIM4AMEN + description: "LPTIM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 13 + bit_size: 1 + - name: OPAMPAMEN + description: "OPAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." + bit_offset: 14 + bit_size: 1 + - name: COMPAMEN + description: "COMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." + bit_offset: 15 + bit_size: 1 + - name: VREFAMEN + description: "VREFBUF autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." + bit_offset: 20 + bit_size: 1 + - name: RTCAPBAMEN + description: "RTC and TAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 21 + bit_size: 1 + - name: ADC4AMEN + description: "ADC4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 25 + bit_size: 1 + - name: LPGPIO1AMEN + description: "LPGPIO1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." + bit_offset: 26 + bit_size: 1 + - name: DAC1AMEN + description: "DAC1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 27 + bit_size: 1 + - name: LPDMA1AMEN + description: "LPDMA1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 28 + bit_size: 1 + - name: ADF1AMEN + description: "ADF1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 29 + bit_size: 1 + - name: SRAM4AMEN + description: "SRAM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." + bit_offset: 31 + bit_size: 1 enum/ADCDACSEL: bit_size: 3 variants: - - name: HCLK1 - description: HCLK clock selected - value: 0 - - name: SYS - description: SYSCLK selected - value: 1 - - name: PLL2_R - description: PLL2 R (pll2_r_ck) selected - value: 2 - - name: HSE - description: HSE clock selected - value: 3 - - name: HSI - description: HSI clock selected - value: 4 - - name: MSIK - description: MSIK clock selected - value: 5 + - name: HCLK1 + description: HCLK clock selected + value: 0 + - name: SYS + description: SYSCLK selected + value: 1 + - name: PLL2_R + description: PLL2 R (pll2_r_ck) selected + value: 2 + - name: HSE + description: HSE clock selected + value: 3 + - name: HSI + description: HSI clock selected + value: 4 + - name: MSIK + description: MSIK clock selected + value: 5 enum/ADFSEL: bit_size: 3 variants: - - name: HCLK3 - description: HCLK selected - value: 0 - - name: PLL1_P - description: PLL1 P (pll1_p_ck) selected - value: 1 - - name: PLL3_Q - description: PLL3 Q (pll3_q_ck) selected - value: 2 - - name: AUDIOCLK - description: input pin AUDIOCLK selected - value: 3 - - name: MSIK - description: MSIK clock selected - value: 4 + - name: HCLK3 + description: HCLK selected + value: 0 + - name: PLL1_P + description: PLL1 P (pll1_p_ck) selected + value: 1 + - name: PLL3_Q + description: PLL3 Q (pll3_q_ck) selected + value: 2 + - name: AUDIOCLK + description: input pin AUDIOCLK selected + value: 3 + - name: MSIK + description: MSIK clock selected + value: 4 enum/DACSEL: bit_size: 1 variants: - - name: LSE - description: LSE selected - value: 0 - - name: LSI - description: LSI selected - value: 1 + - name: LSE + description: LSE selected + value: 0 + - name: LSI + description: LSI selected + value: 1 enum/DPRE: bit_size: 3 variants: - - name: Div1 - description: DCLK not divided - value: 0 - - name: Div2 - description: DCLK divided by 2 - value: 4 - - name: Div4 - description: DCLK divided by 4 - value: 5 - - name: Div8 - description: DCLK divided by 8 - value: 6 - - name: Div16 - description: DCLK divided by 16 - value: 7 + - name: Div1 + description: DCLK not divided + value: 0 + - name: Div2 + description: DCLK divided by 2 + value: 4 + - name: Div4 + description: DCLK divided by 4 + value: 5 + - name: Div8 + description: DCLK divided by 8 + value: 6 + - name: Div16 + description: DCLK divided by 16 + value: 7 enum/DSISEL: bit_size: 1 variants: - - name: PLL3_P - description: PLL3 “P” (pll3_p_ck) selected - value: 0 - - name: DCLK - description: DSI PHY PLL output selected - value: 1 + - name: PLL3_P + description: PLL3 “P” (pll3_p_ck) selected + value: 0 + - name: DSI_PHY + description: DSI PHY PLL output selected (formerly called DCLK, renamed to DSI_PHY to match other chip families) + value: 1 enum/FDCANSEL: bit_size: 2 variants: - - name: HSE - description: HSE clock selected - value: 0 - - name: PLL1_Q - description: PLL1 Q (pll1_q_ck) selected - value: 1 - - name: PLL2_P - description: PLL2 P (pll2_p_ck) selected - value: 2 + - name: HSE + description: HSE clock selected + value: 0 + - name: PLL1_Q + description: PLL1 Q (pll1_q_ck) selected + value: 1 + - name: PLL2_P + description: PLL2 P (pll2_p_ck) selected + value: 2 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK divided by 2 - value: 8 - - name: Div4 - description: SYSCLK divided by 4 - value: 9 - - name: Div8 - description: SYSCLK divided by 8 - value: 10 - - name: Div16 - description: SYSCLK divided by 16 - value: 11 - - name: Div64 - description: SYSCLK divided by 64 - value: 12 - - name: Div128 - description: SYSCLK divided by 128 - value: 13 - - name: Div256 - description: SYSCLK divided by 256 - value: 14 - - name: Div512 - description: SYSCLK divided by 512 - value: 15 + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 enum/HSEEXT: bit_size: 1 variants: - - name: ANALOG - description: external HSE clock analog mode - value: 0 - - name: DIGITAL - description: external HSE clock digital mode (through I/O Schmitt trigger) - value: 1 + - name: ANALOG + description: external HSE clock analog mode + value: 0 + - name: DIGITAL + description: external HSE clock digital mode (through I/O Schmitt trigger) + value: 1 enum/HSPISEL: bit_size: 2 variants: - - name: SYS - description: SYSCLK selected - value: 0 - - name: PLL1_Q - description: PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz - value: 1 - - name: PLL2_Q - description: PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz - value: 2 - - name: PLL3_R - description: PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz - value: 3 + - name: SYS + description: SYSCLK selected + value: 0 + - name: PLL1_Q + description: PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz + value: 1 + - name: PLL2_Q + description: PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz + value: 2 + - name: PLL3_R + description: PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz + value: 3 enum/I2C3SEL: bit_size: 2 variants: - - name: PCLK3 - description: PCLK3 selected - value: 0 - - name: SYS - description: SYSCLK selected - value: 1 - - name: HSI - description: HSI selected - value: 2 - - name: MSIK - description: MSIK selected - value: 3 + - name: PCLK3 + description: PCLK3 selected + value: 0 + - name: SYS + description: SYSCLK selected + value: 1 + - name: HSI + description: HSI selected + value: 2 + - name: MSIK + description: MSIK selected + value: 3 enum/I2CSEL: bit_size: 2 variants: - - name: PCLK1 - description: PCLK1 selected - value: 0 - - name: SYS - description: SYSCLK selected - value: 1 - - name: HSI - description: HSI selected - value: 2 - - name: MSIK - description: MSIK selected - value: 3 + - name: PCLK1 + description: PCLK1 selected + value: 0 + - name: SYS + description: SYSCLK selected + value: 1 + - name: HSI + description: HSI selected + value: 2 + - name: MSIK + description: MSIK selected + value: 3 enum/ICLKSEL: bit_size: 2 variants: - - name: HSI48 - description: HSI48 clock selected - value: 0 - - name: PLL2_Q - description: PLL2 Q (pll2_q_ck) selected - value: 1 - - name: PLL1_Q - description: PLL1 Q (pll1_q_ck) selected - value: 2 - - name: MSIK - description: MSIK clock selected - value: 3 + - name: HSI48 + description: HSI48 clock selected + value: 0 + - name: PLL2_Q + description: PLL2 Q (pll2_q_ck) selected + value: 1 + - name: PLL1_Q + description: PLL1 Q (pll1_q_ck) selected + value: 2 + - name: MSIK + description: MSIK clock selected + value: 3 enum/LPTIM2SEL: bit_size: 2 variants: - - name: PCLK1 - description: PCLK1 selected - value: 0 - - name: LSI - description: LSI selected - value: 1 - - name: HSI - description: HSI selected - value: 2 - - name: LSE - description: LSE selected - value: 3 + - name: PCLK1 + description: PCLK1 selected + value: 0 + - name: LSI + description: LSI selected + value: 1 + - name: HSI + description: HSI selected + value: 2 + - name: LSE + description: LSE selected + value: 3 enum/LPTIMSEL: bit_size: 2 variants: - - name: PCLK3 - description: PCLK3 selected - value: 0 - - name: LSI - description: LSI selected - value: 1 - - name: HSI - description: HSI selected - value: 2 - - name: LSE - description: LSE selected - value: 3 + - name: PCLK3 + description: PCLK3 selected + value: 0 + - name: LSI + description: LSI selected + value: 1 + - name: HSI + description: HSI selected + value: 2 + - name: LSE + description: LSE selected + value: 3 enum/LPUSARTSEL: bit_size: 3 variants: - - name: PCLK3 - description: PCLK3 selected - value: 0 - - name: SYS - description: SYSCLK selected - value: 1 - - name: HSI - description: HSI selected - value: 2 - - name: LSE - description: LSE selected - value: 3 - - name: MSIK - description: MSIK selected - value: 4 + - name: PCLK3 + description: PCLK3 selected + value: 0 + - name: SYS + description: SYSCLK selected + value: 1 + - name: HSI + description: HSI selected + value: 2 + - name: LSE + description: LSE selected + value: 3 + - name: MSIK + description: MSIK selected + value: 4 enum/LSCOSEL: bit_size: 1 variants: - - name: LSI - description: LSI clock selected - value: 0 - - name: LSE - description: LSE clock selected - value: 1 + - name: LSI + description: LSI clock selected + value: 0 + - name: LSE + description: LSE clock selected + value: 1 enum/LSEDRV: bit_size: 2 variants: - - name: Low - description: Low driving capability - value: 0 - - name: MediumLow - description: Medium low driving capability - value: 1 - - name: MediumHigh - description: Medium high driving capability - value: 2 - - name: High - description: High driving capability - value: 3 + - name: Low + description: Low driving capability + value: 0 + - name: MediumLow + description: Medium low driving capability + value: 1 + - name: MediumHigh + description: Medium high driving capability + value: 2 + - name: High + description: High driving capability + value: 3 enum/LSIPREDIV: bit_size: 1 variants: - - name: Div1 - description: LSI not divided - value: 0 - - name: Div128 - description: LSI divided by 128 - value: 1 + - name: Div1 + description: LSI not divided + value: 0 + - name: Div128 + description: LSI divided by 128 + value: 1 enum/LTDCSEL: bit_size: 1 variants: - - name: PLL3_R - description: PLL3 “R” (pll3_r_ck) selected - value: 0 - - name: PLL2_R - description: PLL2 “R” (pll2_r_ck) selected - value: 1 + - name: PLL3_R + description: PLL3 “R” (pll3_r_ck) selected + value: 0 + - name: PLL2_R + description: PLL2 “R” (pll2_r_ck) selected + value: 1 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: MCO divided by 1 - value: 0 - - name: Div2 - description: MCO divided by 2 - value: 1 - - name: Div4 - description: MCO divided by 4 - value: 2 - - name: Div8 - description: MCO divided by 8 - value: 3 - - name: Div16 - description: MCO divided by 16 - value: 4 + - name: Div1 + description: MCO divided by 1 + value: 0 + - name: Div2 + description: MCO divided by 2 + value: 1 + - name: Div4 + description: MCO divided by 4 + value: 2 + - name: Div8 + description: MCO divided by 8 + value: 3 + - name: Div16 + description: MCO divided by 16 + value: 4 enum/MCOSEL: bit_size: 4 variants: - - name: DISABLE - description: MCO output disabled, no clock on MCO - value: 0 - - name: SYS - description: SYSCLK system clock selected - value: 1 - - name: MSIS - description: MSIS clock selected - value: 2 - - name: HSI - description: HSI clock selected - value: 3 - - name: HSE - description: HSE clock selected - value: 4 - - name: PLL1_R - description: Main PLL clock pll1_r_ck selected - value: 5 - - name: LSI - description: LSI clock selected - value: 6 - - name: LSE - description: LSE clock selected - value: 7 - - name: HSI48 - description: Internal HSI48 clock selected - value: 8 - - name: MSIK - description: MSIK clock selected - value: 9 + - name: DISABLE + description: MCO output disabled, no clock on MCO + value: 0 + - name: SYS + description: SYSCLK system clock selected + value: 1 + - name: MSIS + description: MSIS clock selected + value: 2 + - name: HSI + description: HSI clock selected + value: 3 + - name: HSE + description: HSE clock selected + value: 4 + - name: PLL1_R + description: Main PLL clock pll1_r_ck selected + value: 5 + - name: LSI + description: LSI clock selected + value: 6 + - name: LSE + description: LSE clock selected + value: 7 + - name: HSI48 + description: Internal HSI48 clock selected + value: 8 + - name: MSIK + description: MSIK clock selected + value: 9 enum/MDFSEL: bit_size: 3 variants: - - name: HCLK1 - description: HCLK selected - value: 0 - - name: PLL1_P - description: PLL1 P (pll1_p_ck) selected - value: 1 - - name: PLL3_Q - description: PLL3 Q (pll3_q_ck) selected - value: 2 - - name: AUDIOCLK - description: input pin AUDIOCLK selected - value: 3 - - name: MSIK - description: MSIK clock selected - value: 4 + - name: HCLK1 + description: HCLK selected + value: 0 + - name: PLL1_P + description: PLL1 P (pll1_p_ck) selected + value: 1 + - name: PLL3_Q + description: PLL3 Q (pll3_q_ck) selected + value: 2 + - name: AUDIOCLK + description: input pin AUDIOCLK selected + value: 3 + - name: MSIK + description: MSIK clock selected + value: 4 enum/MSIBIAS: bit_size: 1 variants: - - name: CONTINUOUS - description: MSI bias continuous mode (clock accuracy fast settling time) - value: 0 - - name: SAMPLING - description: MSI bias sampling mode (ultra-low-power mode) - value: 1 + - name: CONTINUOUS + description: MSI bias continuous mode (clock accuracy fast settling time) + value: 0 + - name: SAMPLING + description: MSI bias sampling mode (ultra-low-power mode) + value: 1 enum/MSIPLLFAST: bit_size: 1 variants: - - name: NORMAL - description: MSI PLL normal start-up - value: 0 - - name: FAST - description: MSI PLL fast start-up - value: 1 + - name: NORMAL + description: MSI PLL normal start-up + value: 0 + - name: FAST + description: MSI PLL fast start-up + value: 1 enum/MSIPLLSEL: bit_size: 1 variants: - - name: MSIK - description: PLL mode applied to MSIK (MSI kernel) clock output - value: 0 - - name: MSIS - description: PLL mode applied to MSIS (MSI system) clock output - value: 1 + - name: MSIK + description: PLL mode applied to MSIK (MSI kernel) clock output + value: 0 + - name: MSIS + description: PLL mode applied to MSIS (MSI system) clock output + value: 1 enum/MSIRANGE: bit_size: 4 variants: - - name: RANGE_48MHZ - description: range 0 around 48 MHz - value: 0 - - name: RANGE_24MHZ - description: range 1 around 24 MHz - value: 1 - - name: RANGE_16MHZ - description: range 2 around 16 MHz - value: 2 - - name: RANGE_12MHZ - description: range 3 around 12 MHz - value: 3 - - name: RANGE_4MHZ - description: range 4 around 4 MHz (reset value) - value: 4 - - name: RANGE_2MHZ - description: range 5 around 2 MHz - value: 5 - - name: RANGE_1_33MHZ - description: range 6 around 1.33 MHz - value: 6 - - name: RANGE_1MHZ - description: range 7 around 1 MHz - value: 7 - - name: RANGE_3_072MHZ - description: range 8 around 3.072 MHz - value: 8 - - name: RANGE_1_536MHZ - description: range 9 around 1.536 MHz - value: 9 - - name: RANGE_1_024MHZ - description: range 10 around 1.024 MHz - value: 10 - - name: RANGE_768KHZ - description: range 11 around 768 kHz - value: 11 - - name: RANGE_400KHZ - description: range 12 around 400 kHz - value: 12 - - name: RANGE_200KHZ - description: range 13 around 200 kHz - value: 13 - - name: RANGE_133KHZ - description: range 14 around 133 kHz - value: 14 - - name: RANGE_100KHZ - description: range 15 around 100 kHz - value: 15 + - name: RANGE_48MHZ + description: range 0 around 48 MHz + value: 0 + - name: RANGE_24MHZ + description: range 1 around 24 MHz + value: 1 + - name: RANGE_16MHZ + description: range 2 around 16 MHz + value: 2 + - name: RANGE_12MHZ + description: range 3 around 12 MHz + value: 3 + - name: RANGE_4MHZ + description: range 4 around 4 MHz (reset value) + value: 4 + - name: RANGE_2MHZ + description: range 5 around 2 MHz + value: 5 + - name: RANGE_1_33MHZ + description: range 6 around 1.33 MHz + value: 6 + - name: RANGE_1MHZ + description: range 7 around 1 MHz + value: 7 + - name: RANGE_3_072MHZ + description: range 8 around 3.072 MHz + value: 8 + - name: RANGE_1_536MHZ + description: range 9 around 1.536 MHz + value: 9 + - name: RANGE_1_024MHZ + description: range 10 around 1.024 MHz + value: 10 + - name: RANGE_768KHZ + description: range 11 around 768 kHz + value: 11 + - name: RANGE_400KHZ + description: range 12 around 400 kHz + value: 12 + - name: RANGE_200KHZ + description: range 13 around 200 kHz + value: 13 + - name: RANGE_133KHZ + description: range 14 around 133 kHz + value: 14 + - name: RANGE_100KHZ + description: range 15 around 100 kHz + value: 15 enum/MSIRGSEL: bit_size: 1 variants: - - name: CSR - description: MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR - value: 0 - - name: ICSCR1 - description: MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1 - value: 1 + - name: CSR + description: MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR + value: 0 + - name: ICSCR1 + description: MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1 + value: 1 enum/MSIXSRANGE: bit_size: 4 variants: - - name: RANGE_4MHZ - description: range 4 around 4M Hz (reset value) - value: 4 - - name: RANGE_2MHZ - description: range 5 around 2 MHz - value: 5 - - name: RANGE_1_5MHZ - description: range 6 around 1.5 MHz - value: 6 - - name: RANGE_1MHZ - description: range 7 around 1 MHz - value: 7 - - name: RANGE_3_072MHZ - description: range 8 around 3.072 MHz - value: 8 + - name: RANGE_4MHZ + description: range 4 around 4M Hz (reset value) + value: 4 + - name: RANGE_2MHZ + description: range 5 around 2 MHz + value: 5 + - name: RANGE_1_5MHZ + description: range 6 around 1.5 MHz + value: 6 + - name: RANGE_1MHZ + description: range 7 around 1 MHz + value: 7 + - name: RANGE_3_072MHZ + description: range 8 around 3.072 MHz + value: 8 enum/OCTOSPISEL: bit_size: 2 variants: - - name: SYS - description: SYSCLK selected - value: 0 - - name: MSIK - description: MSIK selected - value: 1 - - name: PLL1_Q - description: PLL1 Q (pll1_q_ck) selected, can be up to 200 MHz - value: 2 - - name: PLL2_Q - description: PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz - value: 3 + - name: SYS + description: SYSCLK selected + value: 0 + - name: MSIK + description: MSIK selected + value: 1 + - name: PLL1_Q + description: PLL1 Q (pll1_q_ck) selected, can be up to 200 MHz + value: 2 + - name: PLL2_Q + description: PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz + value: 3 enum/OTGHSSEL: bit_size: 2 variants: - - name: HSE - description: HSE selected - value: 0 - - name: PLL1_P - description: PLL1 “P” (pll1_q_ck) selected, - value: 1 - - name: HSE_DIV_2 - description: HSE/2 selected - value: 2 - - name: PLL1_P_DIV_2 - description: PLL1 “P” divided by 2 (pll1_p_ck/2) selected - value: 3 + - name: HSE + description: HSE selected + value: 0 + - name: PLL1_P + description: PLL1 “P” (pll1_q_ck) selected, + value: 1 + - name: HSE_DIV_2 + description: HSE/2 selected + value: 2 + - name: PLL1_P_DIV_2 + description: PLL1 “P” divided by 2 (pll1_p_ck/2) selected + value: 3 enum/PLLDIV: bit_size: 7 variants: - - name: Div1 - value: 0 - - name: Div2 - value: 1 - - name: Div3 - value: 2 - - name: Div4 - value: 3 - - name: Div5 - value: 4 - - name: Div6 - value: 5 - - name: Div7 - value: 6 - - name: Div8 - value: 7 - - name: Div9 - value: 8 - - name: Div10 - value: 9 - - name: Div11 - value: 10 - - name: Div12 - value: 11 - - name: Div13 - value: 12 - - name: Div14 - value: 13 - - name: Div15 - value: 14 - - name: Div16 - value: 15 - - name: Div17 - value: 16 - - name: Div18 - value: 17 - - name: Div19 - value: 18 - - name: Div20 - value: 19 - - name: Div21 - value: 20 - - name: Div22 - value: 21 - - name: Div23 - value: 22 - - name: Div24 - value: 23 - - name: Div25 - value: 24 - - name: Div26 - value: 25 - - name: Div27 - value: 26 - - name: Div28 - value: 27 - - name: Div29 - value: 28 - - name: Div30 - value: 29 - - name: Div31 - value: 30 - - name: Div32 - value: 31 - - name: Div33 - value: 32 - - name: Div34 - value: 33 - - name: Div35 - value: 34 - - name: Div36 - value: 35 - - name: Div37 - value: 36 - - name: Div38 - value: 37 - - name: Div39 - value: 38 - - name: Div40 - value: 39 - - name: Div41 - value: 40 - - name: Div42 - value: 41 - - name: Div43 - value: 42 - - name: Div44 - value: 43 - - name: Div45 - value: 44 - - name: Div46 - value: 45 - - name: Div47 - value: 46 - - name: Div48 - value: 47 - - name: Div49 - value: 48 - - name: Div50 - value: 49 - - name: Div51 - value: 50 - - name: Div52 - value: 51 - - name: Div53 - value: 52 - - name: Div54 - value: 53 - - name: Div55 - value: 54 - - name: Div56 - value: 55 - - name: Div57 - value: 56 - - name: Div58 - value: 57 - - name: Div59 - value: 58 - - name: Div60 - value: 59 - - name: Div61 - value: 60 - - name: Div62 - value: 61 - - name: Div63 - value: 62 - - name: Div64 - value: 63 - - name: Div65 - value: 64 - - name: Div66 - value: 65 - - name: Div67 - value: 66 - - name: Div68 - value: 67 - - name: Div69 - value: 68 - - name: Div70 - value: 69 - - name: Div71 - value: 70 - - name: Div72 - value: 71 - - name: Div73 - value: 72 - - name: Div74 - value: 73 - - name: Div75 - value: 74 - - name: Div76 - value: 75 - - name: Div77 - value: 76 - - name: Div78 - value: 77 - - name: Div79 - value: 78 - - name: Div80 - value: 79 - - name: Div81 - value: 80 - - name: Div82 - value: 81 - - name: Div83 - value: 82 - - name: Div84 - value: 83 - - name: Div85 - value: 84 - - name: Div86 - value: 85 - - name: Div87 - value: 86 - - name: Div88 - value: 87 - - name: Div89 - value: 88 - - name: Div90 - value: 89 - - name: Div91 - value: 90 - - name: Div92 - value: 91 - - name: Div93 - value: 92 - - name: Div94 - value: 93 - - name: Div95 - value: 94 - - name: Div96 - value: 95 - - name: Div97 - value: 96 - - name: Div98 - value: 97 - - name: Div99 - value: 98 - - name: Div100 - value: 99 - - name: Div101 - value: 100 - - name: Div102 - value: 101 - - name: Div103 - value: 102 - - name: Div104 - value: 103 - - name: Div105 - value: 104 - - name: Div106 - value: 105 - - name: Div107 - value: 106 - - name: Div108 - value: 107 - - name: Div109 - value: 108 - - name: Div110 - value: 109 - - name: Div111 - value: 110 - - name: Div112 - value: 111 - - name: Div113 - value: 112 - - name: Div114 - value: 113 - - name: Div115 - value: 114 - - name: Div116 - value: 115 - - name: Div117 - value: 116 - - name: Div118 - value: 117 - - name: Div119 - value: 118 - - name: Div120 - value: 119 - - name: Div121 - value: 120 - - name: Div122 - value: 121 - - name: Div123 - value: 122 - - name: Div124 - value: 123 - - name: Div125 - value: 124 - - name: Div126 - value: 125 - - name: Div127 - value: 126 - - name: Div128 - value: 127 + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div3 + value: 2 + - name: Div4 + value: 3 + - name: Div5 + value: 4 + - name: Div6 + value: 5 + - name: Div7 + value: 6 + - name: Div8 + value: 7 + - name: Div9 + value: 8 + - name: Div10 + value: 9 + - name: Div11 + value: 10 + - name: Div12 + value: 11 + - name: Div13 + value: 12 + - name: Div14 + value: 13 + - name: Div15 + value: 14 + - name: Div16 + value: 15 + - name: Div17 + value: 16 + - name: Div18 + value: 17 + - name: Div19 + value: 18 + - name: Div20 + value: 19 + - name: Div21 + value: 20 + - name: Div22 + value: 21 + - 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name: Mul488 + value: 487 + - name: Mul489 + value: 488 + - name: Mul490 + value: 489 + - name: Mul491 + value: 490 + - name: Mul492 + value: 491 + - name: Mul493 + value: 492 + - name: Mul494 + value: 493 + - name: Mul495 + value: 494 + - name: Mul496 + value: 495 + - name: Mul497 + value: 496 + - name: Mul498 + value: 497 + - name: Mul499 + value: 498 + - name: Mul500 + value: 499 + - name: Mul501 + value: 500 + - name: Mul502 + value: 501 + - name: Mul503 + value: 502 + - name: Mul504 + value: 503 + - name: Mul505 + value: 504 + - name: Mul506 + value: 505 + - name: Mul507 + value: 506 + - name: Mul508 + value: 507 + - name: Mul509 + value: 508 + - name: Mul510 + value: 509 + - name: Mul511 + value: 510 + - name: Mul512 + value: 511 enum/PLLRGE: bit_size: 2 variants: - - name: FREQ_4TO8MHZ - description: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz - value: 0 - - name: FREQ_8TO16MHZ - description: PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz - value: 3 + - name: FREQ_4TO8MHZ + description: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz + value: 0 + - name: FREQ_8TO16MHZ + description: PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz + value: 3 enum/PLLSRC: bit_size: 2 variants: - - name: DISABLE - description: No clock sent to PLL3 - value: 0 - - name: MSIS - description: MSIS clock selected as PLL3 clock entry - value: 1 - - name: HSI - description: HSI clock selected as PLL3 clock entry - value: 2 - - name: HSE - description: HSE clock selected as PLL3 clock entry - value: 3 + - name: DISABLE + description: No clock sent to PLL3 + value: 0 + - name: MSIS + description: MSIS clock selected as PLL3 clock entry + value: 1 + - name: HSI + description: HSI clock selected as PLL3 clock entry + value: 2 + - name: HSE + description: HSE clock selected as PLL3 clock entry + value: 3 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 enum/RNGSEL: bit_size: 2 variants: - - name: HSI48 - description: HSI48 selected - value: 0 - - name: HSI48_DIV_2 - description: HSI48 / 2 selected, can be used in Range 4 - value: 1 - - name: HSI - description: HSI selected - value: 2 + - name: HSI48 + description: HSI48 selected + value: 0 + - name: HSI48_DIV_2 + description: HSI48 / 2 selected, can be used in Range 4 + value: 1 + - name: HSI + description: HSI selected + value: 2 enum/RTCSEL: bit_size: 2 variants: - - name: DISABLE - description: No clock selected - value: 0 - - name: LSE - description: LSE oscillator clock selected - value: 1 - - name: LSI - description: LSI oscillator clock selected - value: 2 - - name: HSE - description: HSE oscillator clock divided by 32 selected - value: 3 + - name: DISABLE + description: No clock selected + value: 0 + - name: LSE + description: LSE oscillator clock selected + value: 1 + - name: LSI + description: LSI oscillator clock selected + value: 2 + - name: HSE + description: HSE oscillator clock divided by 32 selected + value: 3 enum/SAESSEL: bit_size: 1 variants: - - name: SHSI - description: SHSI selected - value: 0 - - name: SHSI_DIV_2 - description: SHSI / 2 selected, can be used in Range 4 - value: 1 + - name: SHSI + description: SHSI selected + value: 0 + - name: SHSI_DIV_2 + description: SHSI / 2 selected, can be used in Range 4 + value: 1 enum/SAISEL: bit_size: 3 variants: - - name: PLL2_P - description: PLL2 P (pll2_p_ck) selected - value: 0 - - name: PLL3_P - description: PLL3 P (pll3_p_ck) selected - value: 1 - - name: PLL1_P - description: PLL1 P (pll1_p_ck) selected - value: 2 - - name: AUDIOCLK - description: input pin AUDIOCLK selected - value: 3 - - name: HSI - description: HSI clock selected - value: 4 + - name: PLL2_P + description: PLL2 P (pll2_p_ck) selected + value: 0 + - name: PLL3_P + description: PLL3 P (pll3_p_ck) selected + value: 1 + - name: PLL1_P + description: PLL1 P (pll1_p_ck) selected + value: 2 + - name: AUDIOCLK + description: input pin AUDIOCLK selected + value: 3 + - name: HSI + description: HSI clock selected + value: 4 enum/SDMMCSEL: bit_size: 1 variants: - - name: ICLK - description: ICLK clock selected - value: 0 - - name: PLL1_P - description: PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) - value: 1 + - name: ICLK + description: ICLK clock selected + value: 0 + - name: PLL1_P + description: PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) + value: 1 enum/SECURITY: bit_size: 1 variants: - - name: NON_SECURE - description: non secure - value: 0 - - name: SECURE - description: secure - value: 1 + - name: NON_SECURE + description: non secure + value: 0 + - name: SECURE + description: secure + value: 1 enum/SPI1SEL: bit_size: 2 variants: - - name: PCLK2 - description: PCLK2 selected - value: 0 - - name: SYS - description: SYSCLK selected - value: 1 - - name: HSI - description: HSI selected - value: 2 - - name: MSIK - description: MSIK selected - value: 3 + - name: PCLK2 + description: PCLK2 selected + value: 0 + - name: SYS + description: SYSCLK selected + value: 1 + - name: HSI + description: HSI selected + value: 2 + - name: MSIK + description: MSIK selected + value: 3 enum/SPI2SEL: bit_size: 2 variants: - - name: PCLK1 - description: PCLK2 selected - value: 0 - - name: SYS - description: SYSCLK selected - value: 1 - - name: HSI - description: HSI selected - value: 2 - - name: MSIK - description: MSIK selected - value: 3 + - name: PCLK1 + description: PCLK2 selected + value: 0 + - name: SYS + description: SYSCLK selected + value: 1 + - name: HSI + description: HSI selected + value: 2 + - name: MSIK + description: MSIK selected + value: 3 enum/SPI3SEL: bit_size: 2 variants: - - name: PCLK3 - description: PCLK2 selected - value: 0 - - name: SYS - description: SYSCLK selected - value: 1 - - name: HSI - description: HSI selected - value: 2 - - name: MSIK - description: MSIK selected - value: 3 + - name: PCLK3 + description: PCLK2 selected + value: 0 + - name: SYS + description: SYSCLK selected + value: 1 + - name: HSI + description: HSI selected + value: 2 + - name: MSIK + description: MSIK selected + value: 3 enum/STOPKERWUCK: bit_size: 1 variants: - - name: MSIK - description: MSIK oscillator automatically enabled when exiting Stop mode - value: 0 - - name: HSI - description: HSI oscillator automatically enabled when exiting Stop mode - value: 1 + - name: MSIK + description: MSIK oscillator automatically enabled when exiting Stop mode + value: 0 + - name: HSI + description: HSI oscillator automatically enabled when exiting Stop mode + value: 1 enum/STOPWUCK: bit_size: 1 variants: - - name: MSIS - description: MSIS oscillator selected as wakeup from stop clock and CSS backup clock - value: 0 - - name: HSI - description: HSI oscillator selected as wakeup from stop clock and CSS backup clock - value: 1 + - name: MSIS + description: MSIS oscillator selected as wakeup from stop clock and CSS backup clock + value: 0 + - name: HSI + description: HSI oscillator selected as wakeup from stop clock and CSS backup clock + value: 1 enum/SW: bit_size: 2 variants: - - name: MSIS - description: MSIS selected as system clock - value: 0 - - name: HSI - description: HSI selected as system clock - value: 1 - - name: HSE - description: HSE selected as system clock - value: 2 - - name: PLL1_R - description: PLL pll1_r_ck selected as system clock - value: 3 + - name: MSIS + description: MSIS selected as system clock + value: 0 + - name: HSI + description: HSI selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL1_R + description: PLL pll1_r_ck selected as system clock + value: 3 enum/SYSTICKSEL: bit_size: 2 variants: - - name: HCLK1_DIV_8 - description: HCLK/8 selected - value: 0 - - name: LSI - description: LSI selected - value: 1 - - name: LSE - description: LSE selected - value: 2 + - name: HCLK1_DIV_8 + description: HCLK/8 selected + value: 0 + - name: LSI + description: LSI selected + value: 1 + - name: LSE + description: LSE selected + value: 2 enum/TIMICSEL: bit_size: 3 variants: - - name: DISABLE - description: No sources can be selected by TIM16, TIM17 and LPTIM2 as internal input capture - value: 0 - - name: HSI256_MSIS1024_MSIS4 - description: HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture - value: 4 - - name: HSI256_MSIS1024_MSIK4 - description: HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture - value: 5 - - name: HSI256_MSIK1024_MSIS4 - description: HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture - value: 6 - - name: HSI256_MSIK1024_MSIK4 - description: HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture - value: 7 + - name: DISABLE + description: No sources can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + value: 0 + - name: HSI256_MSIS1024_MSIS4 + description: HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + value: 4 + - name: HSI256_MSIS1024_MSIK4 + description: HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + value: 5 + - name: HSI256_MSIK1024_MSIS4 + description: HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + value: 6 + - name: HSI256_MSIK1024_MSIK4 + description: HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + value: 7 enum/USART1SEL: bit_size: 2 variants: - - name: PCLK2 - description: PCLK2 selected - value: 0 - - name: SYS - description: SYSCLK selected - value: 1 - - name: HSI - description: HSI selected - value: 2 - - name: LSE - description: LSE selected - value: 3 + - name: PCLK2 + description: PCLK2 selected + value: 0 + - name: SYS + description: SYSCLK selected + value: 1 + - name: HSI + description: HSI selected + value: 2 + - name: LSE + description: LSE selected + value: 3 enum/USARTSEL: bit_size: 2 variants: - - name: PCLK1 - description: PCLK1 selected - value: 0 - - name: SYS - description: SYSCLK selected - value: 1 - - name: HSI - description: HSI selected - value: 2 - - name: LSE - description: LSE selected - value: 3 + - name: PCLK1 + description: PCLK1 selected + value: 0 + - name: SYS + description: SYSCLK selected + value: 1 + - name: HSI + description: HSI selected + value: 2 + - name: LSE + description: LSE selected + value: 3 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index e348e9e..8a77b5e 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -266,6 +266,7 @@ impl PeriMatcher { (".*:DSIHOST:dsihost1_v1_0", ("dsihost", "v1", "DSIHOST")), (".*:DSIHOST:dsihost1_v1_0_SHARK", ("dsihost", "v1", "DSIHOST")), (".*:DSIHOST:dsihost1_v2_0", ("dsihost", "v2", "DSIHOST")), + (".*:DSIHOST:dsihost_U5", ("dsihost", "u5", "DSIHOST")), (".*:MDIOS:mdios1_v1_0", ("mdios", "v1", "MDIOS")), (".*:QUADSPI:.*", ("quadspi", "v1", "QUADSPI")), ("STM32F1.*:BKP.*", ("bkp", "v1", "BKP")), From f1e684e345944b740ff451277c9bb1c2ceed3dd6 Mon Sep 17 00:00:00 2001 From: JuliDi <20155974+JuliDi@users.noreply.github.com> Date: Fri, 12 Apr 2024 17:05:04 +0200 Subject: [PATCH 6/6] fix ltdc_v1.yaml bfcr wrong definition --- data/registers/ltdc_v1.yaml | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/data/registers/ltdc_v1.yaml b/data/registers/ltdc_v1.yaml index 19186aa..dd40b3d 100644 --- a/data/registers/ltdc_v1.yaml +++ b/data/registers/ltdc_v1.yaml @@ -145,14 +145,16 @@ fieldset/BCCR: fieldset/BFCR: description: Layerx Blending Factors Configuration Register fields: - - name: BF + - name: BF2 description: Blending Factor 2 bit_offset: 0 bit_size: 3 - array: - len: 2 - stride: 8 enum: BF2 + - name: BF1 + description: Blending Factor 1 + bit_offset: 8 + bit_size: 3 + enum: BF1 fieldset/BPCR: description: Back Porch Configuration Register fields: @@ -470,6 +472,15 @@ fieldset/WVPCR: description: Window Vertical Stop Position bit_offset: 16 bit_size: 11 +enum/BF1: + bit_size: 3 + variants: + - name: Constant + description: BF1 = constant alpha + value: 4 + - name: Pixel + description: BF1 = pixel alpha * constant alpha + value: 7 enum/BF2: bit_size: 3 variants: