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Author SHA1 Message Date
JuliDi
804326f93f
add dsihost for u5 chip family 2024-04-15 09:20:50 +02:00
JuliDi
95ff92f362
remove DSISEL from other register ymls where it is not present 2024-04-15 09:20:50 +02:00
JuliDi
dd12c3787a
change DSIPHY to DSI_PHY for rcc_l4plus.yaml to match other families 2024-04-15 09:20:50 +02:00
JuliDi
c8a3e8875d
add DSI as fallback for DSIHOST in stm32-data-gen rcc.rs 2024-04-15 09:20:50 +02:00
Joël Schulz-Ansres
8ec40e422c
Add DSIHOST support 2024-04-15 09:19:55 +02:00
Dario Nieuwenhuis
d674277b78 update sources (adds missing irq) 2024-04-13 03:51:22 +02:00
Dario Nieuwenhuis
0c4baf4783 Remove a few zero-sized memory regions that are breaking memory.x generation. 2024-04-13 03:27:35 +02:00
Dario Nieuwenhuis
9a0154110c
Merge pull request #466 from embassy-rs/u0 
Add stm32u0.
 2024-04-13 01:18:48 +00:00
Dario Nieuwenhuis
d4a97f60b1 Add stm32u0. 2024-04-13 03:16:25 +02:00
Dario Nieuwenhuis
7197df07de
Merge pull request #464 from wagcampbell/wgc/stm32u5-memory-fix 
Corrects STM32U5 memory sizes
 2024-04-12 21:26:40 +00:00
Dario Nieuwenhuis
b1034db59a
Merge pull request #463 from MaxiluxSystems/feature/product-states 
flash_h50: add PRODUCT_STATE enum; improve a couple other fields
 2024-04-12 19:38:24 +00:00
Torin Cooper-Bennun
62b1ab50db flash_h50: rename BKSEL variants 2024-04-12 17:04:33 +01:00
Torin Cooper-Bennun
4df4f6840c flash_h50: plain bool for SWAP_BANK fields 2024-04-12 17:03:44 +01:00
Warren Campbell
af9e902172 Corrects STM32U5 memory sizes 2024-04-11 18:04:35 -04:00
Torin Cooper-Bennun
a0c7c136fa flash_h50: add PRODUCT_STATE enum 
the values are taken from the official HAL headers; I have only included
enum variants which are definitively mentioned in RM0492, excluding
other variants mentioned in the HAL headers
 2024-04-11 10:25:07 +01:00
Torin Cooper-Bennun
f60ad0d665 flash_h50: make _CUR registers read-only 2024-04-11 10:24:55 +01:00
Dario Nieuwenhuis
1f79295b80
Merge pull request #460 from embassy-rs/memfix 
Manually maintain memory maps instead of parsing them from cubeprogdb.
 2024-04-09 02:15:22 +00:00
Dario Nieuwenhuis
8e26f36a8e Manually maintain memory maps instead of parsing them from cubeprogdb. 
First step towards fixing #301

The cubeprogdb has turned out to be a quite bad data source. It's not granular
enough (it has one entry per chip die, not per chip) so the previous code joined
the data with the C headers and cubedb to fill in the gaps, essentialy "guessing"
stuff. This has been quite error prone (see #301) and hard to make fixes to.

Instead, we're going to manually maintain memory maps in a .rs file. This way, if
something is wrong we can simply go and fix it.

This commit just migrates the existing data, even if it's wrong. (it does fix
a few very minor mistakes). Next steps is actually fixing the memory maps.
 2024-04-09 03:38:33 +02:00
Dario Nieuwenhuis
9d3d5c9690 Sort memory regions by addr. 2024-04-09 02:43:44 +02:00
Dario Nieuwenhuis
4e3ed9abee Remove OTP from memory map. 2024-04-09 02:19:17 +02:00
Dario Nieuwenhuis
2480982cc5
Merge pull request #450 from taunusflieger/feature/HSEM 
Add support for HSEM
 2024-04-08 12:10:36 +00:00
Dario Nieuwenhuis
604890b9ba hsem: rename more MASTERID->COREID 2024-04-08 14:07:46 +02:00
Michael Zill
b782384611 Arrayfied IER, ICR, ISR and MISR 
IRQ registers have for all 4 variants the same name.
V1 - array size = 2 (2 cores)
V2 - array size = 1 (1 core)
V3 - array size = 2 (2 cores)
V4 - array size = 1 (1 core)

HSEM added to GHOST_PERIS
 2024-04-08 13:38:36 +02:00
Michael Zill
840e5ec5db Fixed length COREID in v1, v2 renamed MASTERID to COREID 2024-04-08 13:36:40 +02:00
Michael Zill
e029a55f7a Arrayfied v2, v3, v4 - removed enums, aligned yaml structure 
The following list shows the different hsem yaml versions and the coresponding chips.

    wba is on purpose not included at is complex and very different from the others which will
    also make the HSEM implementation in the HAL more complex. I leave this out for another PR.

    h747
    wb55

    h735
    h7b3
    h753v
    h753
    h743
    h743v

    wl5x_cm0p
    wl5x_cm4

    wle5
 2024-04-08 13:36:40 +02:00
Michael Zill
bde330f46e Fixed C1ICR, C2ICR read/write 2024-04-08 13:36:40 +02:00
Michael Zill
c0c35d80f9 Remove temp patch doc 2024-04-08 13:36:40 +02:00
Michael Zill
6ba934d366 Remote debug code 2024-04-08 13:36:40 +02:00
Michael Zill
d1f1f4bfeb Arrayfied v1 and v8 - preliminary fix for missing HSEM in Cube XML 2024-04-08 13:36:40 +02:00
Michael Zill
44967f3776 Initial add 2024-04-08 13:36:40 +02:00
Dario Nieuwenhuis
378deee68b
Merge pull request #457 from eZioPan/UID-to-GHOST_PERIS 
move "UID" to "GHOST_PERIS"
 2024-04-06 20:41:14 +00:00
eZio Pan
60398cad51 move "UID" to "GHOST_PERIS" 2024-04-06 22:07:19 +08:00
Dario Nieuwenhuis
fff3cddff0
Merge pull request #455 from dlaw/main 
Add 8 and 16 bit wide SPI data registers
 2024-04-05 18:12:54 +00:00
David Lawrence
bef34f5e8a Add 8 and 16 bit wide SPI data registers 2024-04-05 14:07:39 -04:00
Dario Nieuwenhuis
5a39cb448a
Merge pull request #454 from dlaw/main 
Split STM32G4 flash peripheral by device category
 2024-04-05 16:31:59 +00:00
David Lawrence
d258cf858d Split STM32G4 flash peripheral by device category 2024-04-05 12:10:59 -04:00
Dario Nieuwenhuis
73ab4d3f67
Merge pull request #451 from eZioPan/lptim-v2 
lptim v2
 2024-04-05 11:28:05 +00:00
Dario Nieuwenhuis
e0a0af600e
Merge pull request #452 from qff233/main 
Fix ADC resolution enum for stm32g4
 2024-04-05 11:20:07 +00:00
eZio Pan
16b4fd12c1 merge lptim CCMR output and input 
move overlap to field level
 2024-04-05 15:01:07 +08:00
qff233
a2c4423ed5 Fix DMA enum 2024-04-05 13:07:24 +08:00
qff233
408a20839a Fix serial registers for stm32g4 serial:q 2024-04-05 12:58:59 +08:00
eZio Pan
f789074a4b merge input mode and output mode 2024-04-05 12:36:35 +08:00
qff233
9dfb42cd91 Fix ADC sample_time enum for stm32g4 2024-04-05 01:39:04 +08:00
qff233
cf5ab0f41b Fix ADC resolution enum for stm32g4 2024-04-05 01:13:23 +08:00
eZio Pan
d9625637f2 add lptim_v2a to chips.rs 2024-04-05 00:06:01 +08:00
eZio Pan
8b036d7f87 add enum 2024-04-04 23:47:06 +08:00
eZio Pan
c25b401647 extract lptim_v2a from l5 2024-04-04 23:40:12 +08:00
eZio Pan
029320446b add lptim to u5 wba 2024-04-04 23:29:48 +08:00
eZio Pan
59cb83596f add to chips.rs 2024-04-04 23:04:21 +08:00
eZio Pan
8bd35deb56 add enum 2024-04-04 23:04:21 +08:00