Merge pull request #452 from qff233/main
Fix ADC resolution enum for stm32g4
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
e0a0af600e
743
data/registers/adc_g4.yaml
Normal file
743
data/registers/adc_g4.yaml
Normal file
@ -0,0 +1,743 @@
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block/ADC:
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description: Analog to Digital Converter
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items:
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- name: ISR
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description: interrupt and status register
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byte_offset: 0
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fieldset: ISR
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- name: IER
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description: interrupt enable register
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byte_offset: 4
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fieldset: IER
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- name: CR
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description: control register
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byte_offset: 8
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fieldset: CR
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- name: CFGR
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description: configuration register 1
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byte_offset: 12
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fieldset: CFGR
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- name: CFGR2
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description: configuration register 2
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byte_offset: 16
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fieldset: CFGR2
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- name: SMPR
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description: sampling time register 1
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byte_offset: 20
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fieldset: SMPR
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- name: SMPR2
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description: sampling time register 2
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byte_offset: 24
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fieldset: SMPR2
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- name: TR1
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description: analog watchdog threshold register 1
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byte_offset: 32
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fieldset: TR1
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- name: TR2
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description: analog watchdog threshold register 2
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byte_offset: 36
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fieldset: TR2
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- name: TR3
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description: analog watchdog threshold register 3
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byte_offset: 40
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fieldset: TR3
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- name: SQR1
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description: group regular sequencer ranks register 1
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byte_offset: 48
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fieldset: SQR1
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- name: SQR2
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description: group regular sequencer ranks register 2
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byte_offset: 52
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fieldset: SQR2
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- name: SQR3
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description: group regular sequencer ranks register 3
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byte_offset: 56
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fieldset: SQR3
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- name: SQR4
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description: group regular sequencer ranks register 4
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byte_offset: 60
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fieldset: SQR4
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- name: DR
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description: group regular conversion data register
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byte_offset: 64
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access: Read
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fieldset: DR
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- name: JSQR
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description: group injected sequencer register
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byte_offset: 76
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fieldset: JSQR
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- name: OFR
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description: offset number 1-4 register
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array:
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len: 4
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stride: 4
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byte_offset: 96
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fieldset: OFR
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- name: JDR
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description: group injected sequencer rank 1-4 register
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array:
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len: 4
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stride: 4
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byte_offset: 128
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access: Read
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fieldset: JDR
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- name: AWD2CR
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description: analog watchdog 2 configuration register
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byte_offset: 160
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fieldset: AWD2CR
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- name: AWD3CR
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description: analog watchdog 3 configuration register
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byte_offset: 164
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fieldset: AWD3CR
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- name: DIFSEL
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description: channel differential or single-ended mode selection register
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byte_offset: 176
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fieldset: DIFSEL
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- name: CALFACT
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description: calibration factors register
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byte_offset: 180
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fieldset: CALFACT
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- name: GCOMP
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description: Gain compensation register
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byte_offset: 192
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fieldset: GCOMP
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fieldset/AWD2CR:
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description: analog watchdog 2 configuration register
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fields:
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- name: AWD2CH
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description: analog watchdog 2 channel selection
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bit_offset: 0
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bit_size: 19
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fieldset/AWD3CR:
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description: analog watchdog 3 configuration register
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fields:
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- name: AWD3CH
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description: analog watchdog 3 channel selection
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bit_offset: 0
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bit_size: 19
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fieldset/CALFACT:
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description: calibration factors register
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fields:
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- name: CALFACT_S
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description: calibration factor in single-ended mode
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bit_offset: 0
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bit_size: 7
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- name: CALFACT_D
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description: calibration factor in differential mode
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bit_offset: 16
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bit_size: 7
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fieldset/CFGR:
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description: configuration register 1
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fields:
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- name: DMAEN
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description: Direct memory access enable
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bit_offset: 0
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bit_size: 1
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enum: DMAEN
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- name: DMACFG
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description: direct memory access configuration
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bit_offset: 0
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bit_size: 1
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enum: DMACFG
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- name: RES
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description: data resolution
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bit_offset: 3
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bit_size: 2
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enum: RES
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- name: EXTSEL
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description: external trigger selection for regular group
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bit_offset: 5
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bit_size: 5
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- name: EXTEN
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description: external trigger enable and polarity selection for regular channels
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bit_offset: 10
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bit_size: 2
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enum: EXTEN
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- name: OVRMOD
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description: overrun mode
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bit_offset: 12
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bit_size: 1
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enum: OVRMOD
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- name: CONT
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description: single / continuous conversion mode for regular conversions
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bit_offset: 13
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bit_size: 1
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- name: AUTDLY
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description: delayed conversion mode
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bit_offset: 14
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bit_size: 1
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- name: ALIGN
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description: data alignment
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bit_offset: 15
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bit_size: 1
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- name: DISCEN
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description: discontinuous mode for regular channels
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bit_offset: 16
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bit_size: 1
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- name: DISCNUM
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description: discontinuous mode channel count
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bit_offset: 17
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bit_size: 3
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- name: JDISCEN
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description: discontinuous mode on injected channels
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bit_offset: 20
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bit_size: 1
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- name: JQM
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description: JSQR queue mode
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bit_offset: 21
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bit_size: 1
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enum: JQM
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- name: AWD1SGL
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description: enable the watchdog 1 on a single channel or on all channels
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bit_offset: 22
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bit_size: 1
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enum: AWD1SGL
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- name: AWD1EN
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description: analog watchdog 1 enable on regular channels
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bit_offset: 23
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bit_size: 1
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- name: JAWD1EN
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description: analog watchdog 1 enable on injected channels
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bit_offset: 24
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bit_size: 1
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- name: JAUTO
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description: automatic injected group conversion
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bit_offset: 25
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bit_size: 1
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- name: AWD1CH
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description: analog watchdog 1 channel selection
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bit_offset: 26
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bit_size: 5
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- name: JQDIS
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description: injected queue disable
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bit_offset: 31
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bit_size: 1
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fieldset/CFGR2:
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description: configuration register 2
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fields:
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- name: ROVSE
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description: Regular Oversampling Enable
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bit_offset: 0
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bit_size: 1
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- name: JOVSE
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description: Injected Oversampling Enable
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bit_offset: 1
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bit_size: 1
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- name: OVSR
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description: Oversampling ratio
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bit_offset: 2
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bit_size: 3
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- name: OVSS
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description: Oversampling shift
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bit_offset: 5
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bit_size: 4
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- name: TROVS
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description: Triggered Regular Oversampling
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bit_offset: 9
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bit_size: 1
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enum: TROVS
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- name: ROVSM
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description: Regular Oversampling mode
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bit_offset: 10
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bit_size: 1
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enum: ROVSM
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- name: GCOMP
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description: Gain compensation mode
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bit_offset: 16
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bit_size: 1
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- name: SWTRIG
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description: Software trigger bit for sampling time control trigger mode
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bit_offset: 25
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bit_size: 1
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- name: BULB
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description: Bulb sampling mode
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bit_offset: 26
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bit_size: 1
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- name: SMPTRIG
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description: Sampling time control trigger mode
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bit_offset: 27
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bit_size: 1
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fieldset/CR:
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description: control register
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fields:
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- name: ADEN
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description: enable
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bit_offset: 0
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bit_size: 1
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- name: ADDIS
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description: disable
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bit_offset: 1
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bit_size: 1
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- name: ADSTART
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description: group regular conversion start
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bit_offset: 2
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bit_size: 1
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- name: JADSTART
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description: group injected conversion start
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bit_offset: 3
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bit_size: 1
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- name: ADSTP
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description: group regular conversion stop
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bit_offset: 4
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bit_size: 1
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enum: ADSTP
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- name: JADSTP
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description: group injected conversion stop
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bit_offset: 5
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bit_size: 1
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enum: ADSTP
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- name: ADVREGEN
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description: voltage regulator enable
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bit_offset: 28
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bit_size: 1
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- name: DEEPPWD
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description: deep power down enable
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bit_offset: 29
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bit_size: 1
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- name: ADCALDIF
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description: differential mode for calibration
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bit_offset: 30
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bit_size: 1
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enum: ADCALDIF
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- name: ADCAL
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description: calibration
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bit_offset: 31
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bit_size: 1
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fieldset/DIFSEL:
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description: channel differential or single-ended mode selection register
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fields:
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- name: DIFSEL
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description: channel differential or single-ended mode for channel
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bit_offset: 0
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bit_size: 1
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array:
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len: 18
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stride: 1
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enum: DIFSEL
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fieldset/DR:
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description: group regular conversion data register
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fields:
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- name: RDATA
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description: group regular conversion data
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bit_offset: 0
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bit_size: 16
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fieldset/IER:
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description: interrupt enable register
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fields:
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- name: ADRDYIE
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description: ready interrupt
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bit_offset: 0
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bit_size: 1
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- name: EOSMPIE
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description: group regular end of sampling interrupt
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bit_offset: 1
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bit_size: 1
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- name: EOCIE
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description: group regular end of unitary conversion interrupt
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bit_offset: 2
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bit_size: 1
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- name: EOSIE
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description: group regular end of sequence conversions interrupt
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bit_offset: 3
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bit_size: 1
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- name: OVRIE
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description: group regular overrun interrupt
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bit_offset: 4
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bit_size: 1
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- name: JEOCIE
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description: group injected end of unitary conversion interrupt
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bit_offset: 5
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bit_size: 1
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- name: JEOSIE
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description: group injected end of sequence conversions interrupt
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bit_offset: 6
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bit_size: 1
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- name: AWD1IE
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description: analog watchdog 1 interrupt
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bit_offset: 7
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bit_size: 1
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- name: AWD2IE
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description: analog watchdog 2 interrupt
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bit_offset: 8
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bit_size: 1
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- name: AWD3IE
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description: analog watchdog 3 interrupt
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bit_offset: 9
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bit_size: 1
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- name: JQOVFIE
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description: group injected contexts queue overflow interrupt
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bit_offset: 10
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bit_size: 1
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fieldset/ISR:
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description: interrupt and status register
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fields:
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- name: ADRDY
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description: ready flag
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bit_offset: 0
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bit_size: 1
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- name: EOSMP
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description: group regular end of sampling flag
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bit_offset: 1
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bit_size: 1
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- name: EOC
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description: group regular end of unitary conversion flag
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bit_offset: 2
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bit_size: 1
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- name: EOS
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description: group regular end of sequence conversions flag
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bit_offset: 3
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bit_size: 1
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- name: OVR
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description: group regular overrun flag
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bit_offset: 4
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bit_size: 1
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- name: JEOC
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description: group injected end of unitary conversion flag
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bit_offset: 5
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bit_size: 1
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- name: JEOS
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description: group injected end of sequence conversions flag
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bit_offset: 6
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bit_size: 1
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- name: AWD1
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description: analog watchdog 1 flag
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bit_offset: 7
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bit_size: 1
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- name: AWD2
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description: analog watchdog 2 flag
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bit_offset: 8
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bit_size: 1
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- name: AWD3
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description: analog watchdog 3 flag
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bit_offset: 9
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bit_size: 1
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- name: JQOVF
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description: group injected contexts queue overflow flag
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bit_offset: 10
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bit_size: 1
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fieldset/JDR:
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description: group injected sequencer rank 1-4 register
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fields:
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- name: JDATA
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description: group injected sequencer rank conversion data
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bit_offset: 0
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bit_size: 16
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fieldset/JSQR:
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description: group injected sequencer register
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fields:
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- name: JL
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description: group injected sequencer scan length
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bit_offset: 0
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bit_size: 2
|
||||
- name: JEXTSEL
|
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description: group injected external trigger source
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bit_offset: 2
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bit_size: 5
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- name: JEXTEN
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description: group injected external trigger polarity
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bit_offset: 7
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bit_size: 2
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||||
enum: JEXTEN
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- name: JSQ
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||||
description: group injected sequencer rank 1-4
|
||||
bit_offset: 9
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||||
bit_size: 5
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||||
array:
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||||
len: 4
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stride: 6
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fieldset/TR1:
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description: analog watchdog threshold register 1
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fields:
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- name: LT1
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description: analog watchdog 1 lower threshold
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bit_offset: 0
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||||
bit_size: 12
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||||
- name: AWDFILT
|
||||
description: analog watchdog filtering parameter
|
||||
bit_offset: 12
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||||
bit_size: 3
|
||||
- name: HT1
|
||||
description: analog watchdog 1 higher threshold
|
||||
bit_offset: 16
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||||
bit_size: 12
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||||
fieldset/TR2:
|
||||
description: analog watchdog threshold register 2
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||||
fields:
|
||||
- name: LT2
|
||||
description: analog watchdog 2 lower threshold
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: HT2
|
||||
description: analog watchdog 2 higher threshold
|
||||
bit_offset: 16
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||||
bit_size: 8
|
||||
fieldset/TR3:
|
||||
description: analog watchdog threshold register 3
|
||||
fields:
|
||||
- name: LT3
|
||||
description: analog watchdog 3 lower threshold
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: HT3
|
||||
description: analog watchdog 3 higher threshold
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
fieldset/OFR:
|
||||
description: offset number x register
|
||||
fields:
|
||||
- name: OFFSET
|
||||
description: data offset
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: OFFSETPOS
|
||||
description: Positive offset
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SATEN
|
||||
description: Saturation enable
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: OFFSET1_CH
|
||||
description: Channel selection for the data offset
|
||||
bit_offset: 26
|
||||
bit_size: 5
|
||||
- name: OFFSET_EN
|
||||
description: Offset enable
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SMPR:
|
||||
description: sampling time register
|
||||
fields:
|
||||
- name: SMP
|
||||
description: channel n * 10 + x sampling time
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 10
|
||||
stride: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMPPLUS
|
||||
description: Addition of one clock cycle to the sampling time
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SMPR2:
|
||||
description: sampling time register
|
||||
fields:
|
||||
- name: SMP
|
||||
description: channel n * 10 + x sampling time
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 9
|
||||
stride: 3
|
||||
enum: SAMPLE_TIME
|
||||
fieldset/SQR1:
|
||||
description: group regular sequencer ranks register 1
|
||||
fields:
|
||||
- name: L
|
||||
description: L
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: SQ
|
||||
description: group regular sequencer rank 1-4
|
||||
bit_offset: 6
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 6
|
||||
fieldset/SQR2:
|
||||
description: group regular sequencer ranks register 2
|
||||
fields:
|
||||
- name: SQ
|
||||
description: group regular sequencer rank 5-9
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 5
|
||||
stride: 6
|
||||
fieldset/SQR3:
|
||||
description: group regular sequencer ranks register 3
|
||||
fields:
|
||||
- name: SQ
|
||||
description: group regular sequencer rank 10-14
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 5
|
||||
stride: 6
|
||||
fieldset/SQR4:
|
||||
description: group regular sequencer ranks register 4
|
||||
fields:
|
||||
- name: SQ
|
||||
description: group regular sequencer rank 15-16
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 2
|
||||
stride: 6
|
||||
fieldset/GCOMP:
|
||||
description: Gain compensation coefficient
|
||||
fields:
|
||||
- name: GCOMPCOEFF
|
||||
description: Gain compensation coefficient
|
||||
bit_offset: 0
|
||||
bit_size: 14
|
||||
enum/ADCALDIF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: SingleEnded
|
||||
description: Calibration for single-ended mode
|
||||
value: 0
|
||||
- name: Differential
|
||||
description: Calibration for differential mode
|
||||
value: 1
|
||||
enum/ADSTP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Stop
|
||||
description: Stop conversion of channel
|
||||
value: 1
|
||||
enum/AWD1SGL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: All
|
||||
description: Analog watchdog 1 enabled on all channels
|
||||
value: 0
|
||||
- name: Single
|
||||
description: Analog watchdog 1 enabled on single channel selected in AWD1CH
|
||||
value: 1
|
||||
enum/DIFSEL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: SingleEnded
|
||||
description: Input channel is configured in single-ended mode
|
||||
value: 0
|
||||
- name: Differential
|
||||
description: Input channel is configured in differential mode
|
||||
value: 1
|
||||
enum/DMAEN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disable
|
||||
description: DMA disable
|
||||
value: 0
|
||||
- name: Enable
|
||||
description: DMA enable
|
||||
value: 1
|
||||
enum/DMACFG:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: OneShotMode
|
||||
description: DMA One Shot mode selected
|
||||
value: 0
|
||||
- name: CircularMode
|
||||
description: DMA Circular mode selected
|
||||
value: 1
|
||||
enum/EXTEN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Trigger detection disabled
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: Trigger detection on the rising edge
|
||||
value: 1
|
||||
- name: FallingEdge
|
||||
description: Trigger detection on the falling edge
|
||||
value: 2
|
||||
- name: BothEdges
|
||||
description: Trigger detection on both the rising and falling edges
|
||||
value: 3
|
||||
enum/JEXTEN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Trigger detection disabled
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: Trigger detection on the rising edge
|
||||
value: 1
|
||||
- name: FallingEdge
|
||||
description: Trigger detection on the falling edge
|
||||
value: 2
|
||||
- name: BothEdges
|
||||
description: Trigger detection on both the rising and falling edges
|
||||
value: 3
|
||||
enum/JQM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Mode0
|
||||
description: 'JSQR Mode 0: Queue maintains the last written configuration into JSQR'
|
||||
value: 0
|
||||
- name: Mode1
|
||||
description: 'JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence'
|
||||
value: 1
|
||||
enum/OVRMOD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Preserve
|
||||
description: Preserve DR register when an overrun is detected
|
||||
value: 0
|
||||
- name: Overwrite
|
||||
description: Overwrite DR register when an overrun is detected
|
||||
value: 1
|
||||
enum/RES:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Bits12
|
||||
description: 12-bit resolution
|
||||
value: 0
|
||||
- name: Bits10
|
||||
description: 10-bit resolution
|
||||
value: 1
|
||||
- name: Bits8
|
||||
description: 8-bit resolution
|
||||
value: 2
|
||||
- name: Bits6
|
||||
description: 6-bit resolution
|
||||
value: 3
|
||||
enum/ROVSM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Continued
|
||||
description: Oversampling is temporary stopped and continued after injection sequence
|
||||
value: 0
|
||||
- name: Resumed
|
||||
description: Oversampling is aborted and resumed from start after injection sequence
|
||||
value: 1
|
||||
enum/SAMPLE_TIME:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Cycles2_5
|
||||
description: 2.5 clock cycles
|
||||
value: 0
|
||||
- name: Cycles6_5
|
||||
description: 6.5 clock cycles
|
||||
value: 1
|
||||
- name: Cycles12_5
|
||||
description: 12.5 clock cycles
|
||||
value: 2
|
||||
- name: Cycles24_5
|
||||
description: 24.5 clock cycles
|
||||
value: 3
|
||||
- name: Cycles47_5
|
||||
description: 47.5 clock cycles
|
||||
value: 4
|
||||
- name: Cycles92_5
|
||||
description: 92.5 clock cycles
|
||||
value: 5
|
||||
- name: Cycles247_5
|
||||
description: 247.5 clock cycles
|
||||
value: 6
|
||||
- name: Cycles640_5
|
||||
description: 640.5 clock cycles
|
||||
value: 7
|
||||
enum/TROVS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Automatic
|
||||
description: All oversampled conversions for a channel are done consecutively following a trigger
|
||||
value: 0
|
||||
- name: Triggered
|
||||
description: Each oversampled conversion for a channel needs a new trigger
|
||||
value: 1
|
||||
@ -209,7 +209,7 @@ impl PeriMatcher {
|
||||
("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")),
|
||||
("STM32G0.*:ADC:.*", ("adc", "g0", "ADC")),
|
||||
("STM32G0.*:ADC_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")),
|
||||
("STM32G4.*:ADC:.*", ("adc", "v4", "ADC")),
|
||||
("STM32G4.*:ADC:.*", ("adc", "g4", "ADC")),
|
||||
("STM32G4.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")),
|
||||
(".*:ADC_COMMON:aditf2_v1_1", ("adccommon", "v2", "ADC_COMMON")),
|
||||
(".*:ADC_COMMON:aditf5_v2_0", ("adccommon", "v3", "ADC_COMMON")),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user