guangzong/stm32-data
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780 Commits

Author SHA1 Message Date
Bob McWhirter
21f31372a6 Adjust the d script. 
Extract some peripherals for U5.
Update parse.py for some U5 perculiarities.
 2021-11-02 12:02:38 -04:00
Ben Gamari
2f42ebcd2c Add support for LPTIM peripherals 2021-10-26 17:55:48 +02:00
Matous Hybl
2e1302c4e8 Support for STM32F767ZI and basic support for the rest of the family. 2021-10-25 10:38:28 +02:00
Tobias Pisani
b8de47fa04 feat: Add F1 SPI registers 2021-10-06 20:51:27 +02:00
Dario Nieuwenhuis
f6ce6dc36b CRC register cleanup 2021-09-27 00:26:24 +02:00
Joshua Salzedo
24dabf68e5 Add three distinct versions of CRC 
- remove F4 specific version
 2021-09-26 14:58:47 -07:00
Joshua Salzedo
a8a8b88661 add CRC32 peripheral for the F4 family 2021-09-24 16:59:18 -07:00
Vincent Stakenburg
97fd020941 add l4 flash register 2021-09-24 16:45:59 +02:00
Mariusz Ryndzionek
8dde100c15 Updated register mapping for STM32 F1 AFIO 2021-09-23 18:54:22 +02:00
Dario Nieuwenhuis
5dec590202 Merge pull request #85 from mryndzionek/stm32f1_support 
Add initial register mapping for STM32 F1 AFIO and FLASH
 2021-09-23 17:36:38 +02:00
Ulf Lilleengen
a302947e87 Add PWR register block and fix RCC register block 2021-09-23 14:40:59 +02:00
Mariusz Ryndzionek
fbea23bd00 Added missing FLASH registers (generated automatically) 2021-09-23 07:09:11 +02:00
Mariusz Ryndzionek
c0938c9102 Add initial register mapping for STM32 F1 AFIO and FLASH 2021-09-22 18:22:36 +02:00
Ulf Lilleengen
9f1bd7d0d0 Update chip yaml 2021-09-15 14:47:33 +02:00
Dario Nieuwenhuis
616a2779d0 Merge pull request #82 from bgamari/stm32g0 
Fix ADC register layout on STM32G0
 2021-08-31 22:21:51 +02:00
Ulf Lilleengen
902b9a6986 Add PWR peripheral for STM32WL5 2021-08-31 14:34:54 +02:00
Ben Gamari
3a88360dc6 Add PWR registers for STM32G0 2021-08-31 01:46:26 -04:00
Ben Gamari
5366833cbd Introduce ADC register set for STM32G0 2021-08-31 01:46:02 -04:00
Dario Nieuwenhuis
deb37365d7 exti: g0 and l5 are 8 bits per line... 2021-08-20 01:26:33 +02:00
Dario Nieuwenhuis
8534ae884d rcc: make GPIO EN/RST regs naming consistent. 2021-08-19 23:50:42 +02:00
Dario Nieuwenhuis
3b6363dffb wl rcc: rename SPI2S2 -> SPI2 2021-08-19 22:37:07 +02:00
Dario Nieuwenhuis
49e579e97f Add F2 RCC 2021-08-19 22:12:39 +02:00
Dario Nieuwenhuis
e289dd883f Cleanup EXTI 2021-08-19 21:54:22 +02:00
Dario Nieuwenhuis
701ab04c2a Cleanup SYSCFG naming 2021-08-19 21:28:32 +02:00
Dario Nieuwenhuis
31997049ea Fix wrong register offsets in WB SYSCFG 2021-08-19 19:20:13 +02:00
Dario Nieuwenhuis
6af9f2c0d1 Add RCC for F3, F7, G4, H7AB, L1, L5, WB*, WL5, WLE 2021-08-19 19:13:30 +02:00
Ben Gamari
f57a268b9f Add STM32G0 support 
Includes manually specified register layouts for EXTI and SYSCFG.
 2021-08-19 15:57:00 +02:00
Ben Gamari
f5808de749 Add RCC support for STM32G0 2021-08-19 15:54:36 +02:00
Ulf Lilleengen
919a61e847 Add STM32WL5x exti block 2021-08-17 13:02:49 +02:00
Bob McWhirter
541091cded Include the reg block. 2021-08-16 15:12:17 -04:00
Timo Kröger
198e4f3247 Add bxcan registers 2021-08-06 11:52:47 +02:00
Timo Kröger
7506b50031 rcc_l4: Remove duplicate bits 2021-08-03 16:33:59 +02:00
Timo Kröger
f865878b4b rcc_f4: Fix RCC bits 
## LPTIM1EN / LPTIMER1EN

Only stm32f413 has LPTIM1 peripheral, ref manual bit names:
LPTIMER1EN, LPTIMER1RST, LPTIMER1LPEN, LPTIMER1SEL

action: Rename to LPTIM1(EN|RST|...) for consistency (matches peripheral name)

## FMC / FSMC

not available as peripheral in the YAML anyway.. TODO: why?

EN and RST

FSMC: f405, f407, f412, f413
FSC: f427, f429, f446, f469

action: none

## CECEN / CAN3EN

mutually exclusive peripherals, alias ok?

CECEN: f446
CAN3EN: f413

action: split off f4x3 yaml, f423 exists, but not available as svd

## USART / UART

all over the place, register names in ref manual not always consistent
stm32 follows a simple rule for the actual peripherals:
USART 1-3, 6
UART 4, 5, 7-10

action: rename enable/rst bits to rules above
 2021-08-03 14:55:36 +02:00
Timo Kröger
babbe782f3 rcc_l0: Remove non existing RCC bits 
## firewall

l0x0, l0x1: FWEN - Firewall clock enable bit
l0x2, l0x3: MIFIEN - MiFaRe Firewall clock enable bit
action: none

## watchdog

peripheral: WWDG
WWDGRST vs WWDRST
action: remove

## CRS vs CRC

l0x2, l0x3: CRC reset is wrong
action: remove duplicate CRC bit

## LPUART12RST vs USART2RST

action: rename, it sholud be USART2
 2021-08-03 14:31:36 +02:00
Timo Kröger
d1597c646d rcc_l0: Remove duplicate I2C3 reset bit 2021-08-03 10:55:51 +02:00
Timo Kröger
ded4f52051 rcc_f4: Remove duplicate USBF bit 2021-08-03 10:55:51 +02:00
Bob McWhirter
83f5b39ecb Parse memory names slightly better from the XML. 2021-08-02 11:06:26 -04:00
Bob McWhirter
99cd26c33f Parse memory layouts for actual region sizes. 2021-08-02 11:06:25 -04:00
Timo Kröger
c02e3dc9ab Split f410 and f4 RCC yamls 
f410 has the RNGEN at a different position
 2021-07-31 17:40:30 +02:00
Timo Kröger
074aad8a66 Remove invalid bits from F4, L4 RCC 2021-07-30 17:35:52 +02:00
Thales Fragoso
02b44906c9 Add F4 PWR 2021-07-28 19:14:39 -03:00
Dario Nieuwenhuis
0bbd7c2d31 Merge pull request #67 from embassy-rs/f4-flash 
Add F4 FLASH
 2021-07-28 11:45:51 +02:00
Thales Fragoso
d53b964978 Add F4 FLASH 2021-07-27 21:53:08 -03:00
Grant Miller
d80e5e736c Remove trivial enums 2021-07-27 12:11:36 -05:00
Grant Miller
369401ca07 Add F1 RCC 2021-07-27 12:11:25 -05:00
Dario Nieuwenhuis
60b4b7d155 Add dmamux yamls, use them instead of xml/c parsing. 2021-07-17 07:23:48 +02:00
Bob McWhirter
02dd4e13f2 Parse in the dma HAL headers for the actual request numbers. 
Then apply them to fix up where possible because the XML is crap.
 2021-07-16 13:44:40 -04:00
Dario Nieuwenhuis
134d22af37 Add H7 SMPS 2021-07-16 00:38:49 +02:00
Dario Nieuwenhuis
ac29cdf3cd Add write-only access to TDR 2021-07-15 00:47:27 +02:00
Dario Nieuwenhuis
48b70bdf76 Merge USARTv2 and USARTv3, they're identical. 2021-07-15 00:20:17 +02:00