guangzong/stm32-data
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780 Commits

Author SHA1 Message Date
Matthew W. Samsonoff
57903f105d stm32g0: add enums for RCC 2022-03-02 11:27:33 -05:00
Matthew W. Samsonoff
14a26e9edd stm32g0: fix typo 2022-03-02 11:26:45 -05:00
Matthew W. Samsonoff
0f5292f20e stm32g0: CCIPR2/USBSEL is two bits wide 2022-03-02 11:26:38 -05:00
Dario Nieuwenhuis
324e5bee8d rcc/h7: add missing stuff, cleanup. 2022-02-24 05:54:43 +01:00
Dario Nieuwenhuis
b6bccb1456 cleanup gpio regs. 2022-02-24 01:59:57 +01:00
Dario Nieuwenhuis
85854d8f42 usart_v2: fix wrong M1 bit 2022-02-14 02:07:49 +01:00
Dario Nieuwenhuis
fde7738019 flash/u5: fix inconsistent BKPRAM vs BKPSRAM 2022-02-14 02:07:33 +01:00
Dario Nieuwenhuis
9b32ce66b6 mdios: fix accidentally merge-regs'd file. 2022-02-14 02:07:20 +01:00
Dario Nieuwenhuis
c2804abc9a rcc: fix inconsistent naming. 2022-02-14 02:07:08 +01:00
Dario Nieuwenhuis
2c5e858584 chiptool fmt 2022-02-14 00:45:36 +01:00
Dario Nieuwenhuis
7b2df420ac rcc: remove useless enums. 2022-02-14 00:26:46 +01:00
Dario Nieuwenhuis
66ecaf8b98 rcc: unify rcc_f0, rcc_f0x0 2022-02-14 00:25:12 +01:00
Dario Nieuwenhuis
fcd18b3e3d i2c: cleanup a bit. 2022-02-13 23:21:48 +01:00
Dario Nieuwenhuis
5365ea053a split "magic" block string into an object, so consumers don't have to do tricky parsing. 2022-02-07 23:12:40 +01:00
Dario Nieuwenhuis
7b368b0035 move memory parsing to own file 2022-02-07 02:06:23 +01:00
Dario Nieuwenhuis
48fdf50203 Change peripherals from dict to array 2022-02-07 02:05:30 +01:00
Dario Nieuwenhuis
f79e304d07 u5/rcc: fix inconsistent DCMI bit names 2022-02-05 03:02:57 +01:00
Dario Nieuwenhuis
048f6766fd lpuart: cleanup v1, v2. Merge v2 and v3 2022-02-05 00:59:20 +01:00
Maarten Oosting
6b86d9e104 LPUART: Add registers 2022-02-05 00:59:20 +01:00
chemicstry
2aaec03094 Fix USB OTG field names in RCC registers 2022-02-04 03:34:08 +02:00
Dario Nieuwenhuis
61bca5a789 rcc/g0: add lots of missing bits 2022-01-24 02:13:53 +01:00
Dario Nieuwenhuis
11290fd274 rcc: make GPIOxEN/IOPxEN consistent. 2022-01-24 02:13:24 +01:00
Greg V
76572f3d55 Add flash for STM32L1 
NOTE: named 'Flash' instead of 'FLASH' in SVD
 2022-01-14 16:50:35 +03:00
Matous Hybl
2c7984f962 Unify SPI LSBFirst enums. 2022-01-14 10:23:27 +01:00
Dario Nieuwenhuis
0f04776eaa rcc: l0, l1, l4: add missing enums. 2022-01-04 23:56:52 +01:00
Dario Nieuwenhuis
7061d52abd pwr f4, f7: cleanup a bit 2022-01-04 21:10:54 +01:00
Dominik Boehi
bb6321bc87 Extract flash information for STM32WB by looking for FLASH_REG_BASE define 2022-01-04 19:38:05 +01:00
Dominik Boehi
d8189255fa Add Flash, RTC, PWR for STM32WB55, fix IPCC CPU registers 2022-01-04 18:52:34 +01:00
Sjoerd Simons
8ed35ce95b Add registers for F1 ADC block 2021-12-29 15:51:27 +01:00
Dario Nieuwenhuis
0e9fa2f438 Merge pull request #109 from VasanthakumarV/f3-registers 
Add `SYSCFG`, `PWR`, `FLASH` and `SPI` registers for `STM32F3`
 2021-12-16 08:12:07 +01:00
VasanthakumarV
b9193128ed [manual] Make EXTICRx in SYSCFG register an array 
The four variants of EXTICRx has been manually edited into
an array of size and stride four.
The corresponding fieldset was also manually changed.
 2021-12-09 13:47:55 +05:30
VasanthakumarV
fdf0cc95b9 [manual] Deduplicate PLLSRC entry of RCC_CFGR register 
I have manually removed the single bit PLLSRC under RCC_CFGR register,
and I have manually updated the `enum/PLLSRC` to have 3 variants to match
the bit_size of PLLSRC.
 2021-12-09 13:24:25 +05:30
Matous Hybl
8402040d17 Fix generation of FMC peripheral in chip yamls. Add FMC registers. 2021-12-08 20:01:57 +01:00
VasanthakumarV
ef950a6feb [generate] Create SYSCFG, PWR, FLASH register files 2021-12-08 15:43:23 +05:30
Dario Nieuwenhuis
f6c9772cf4 usart: make v1 and v2 more consistent. 2021-12-08 04:48:21 +01:00
Dario Nieuwenhuis
df6b1a13b0 rcc_f3: add lots of missing stuff. 2021-11-28 23:25:16 +01:00
Dario Nieuwenhuis
3780dbab57 rcc_l5: fix typo 2021-11-28 22:45:06 +01:00
Dario Nieuwenhuis
2e8c0bc791 Fix stm32u5 accidentally removed fieldset/PRIVCFGR 2021-11-27 02:32:51 +01:00
Dario Nieuwenhuis
353411841c stm32g4 support. 2021-11-27 02:20:17 +01:00
Dario Nieuwenhuis
6af084d858 SYSCFG_H7: random typo fix 2021-11-27 02:19:55 +01:00
Dario Nieuwenhuis
b630a96365 PWR: arrayify PUCRx, PDCRx 2021-11-27 02:19:38 +01:00
Dario Nieuwenhuis
0dcaaa07fe cleanup spi v1/f1, add missing i2s stuff 2021-11-17 21:30:52 +01:00
Dario Nieuwenhuis
c6c5c099bb fmt all register yamls 2021-11-17 21:23:26 +01:00
Bob McWhirter
e501a9746f Complete enum cleanup. 2021-11-11 14:52:45 -05:00
Bob McWhirter
91c77958bd Remove some useless enums. 
Apply better variant names to some enums.
 2021-11-11 14:09:49 -05:00
Bob McWhirter
117e3f3f4b Clean up some enum variants, reduce some enums that duplicate. 2021-11-11 10:25:04 -05:00
Matous Hybl
bfc7856d75 Fix DCMI reset. 2021-11-10 17:31:06 +01:00
Bob McWhirter
d2e9ef3622 U5 FLASH and RCC. 2021-11-08 13:48:03 -05:00
Matous Hybl
6ef7659b9d Add support for H723 RCC differences. 2021-11-04 15:26:52 +01:00
Matous Hybl
3d7e46e6c9 Fix v1c ethernet definition. 2021-11-03 10:13:15 +01:00