Jensenn
8b59cb1d85
Fix LCD display memory array
2022-05-06 14:59:23 -06:00
Jensenn
521417bbb0
make LCD display memory an array
2022-05-06 14:26:20 -06:00
Matous Hybl
f2498652f1
Clean-up F3 and F7 flash registers
2022-05-06 21:52:51 +02:00
Grant Miller
423a80a8f8
Fix ADCPRE descriptions
2022-05-01 19:31:43 -05:00
Grant Miller
ad6f5a5434
Clean up rcc_f1cl.yaml
2022-05-01 19:29:40 -05:00
Grant Miller
e905859bdf
Clean up rcc_f1.yaml
2022-05-01 19:28:29 -05:00
Grant Miller
d7674ab524
Create rcc_f100.yaml
2022-05-01 19:27:28 -05:00
Dario Nieuwenhuis
c36a510e47
unify ETH vs ETHMAC in RCC regs.
2022-04-28 01:54:55 +02:00
Matous Hybl
a87cf34197
Add ADC registers for F1 and H7
2022-04-27 00:50:46 +02:00
Dario Nieuwenhuis
eff26e3e77
Add stm32u5 GPDMA, SPI
2022-04-26 23:53:28 +02:00
Dario Nieuwenhuis
bb6053d4ee
chiptool fmt
2022-04-26 21:16:00 +02:00
Dario Nieuwenhuis
2db5d47cc6
Merge pull request #140 from davidlenfesty/eth-v1a
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Generate support for ethernet v1a and v1b
2022-04-26 18:28:41 +02:00
Ulf Lilleengen
afcd7a7d69
Rename flash_w[bl]55 flash_w[bl]
2022-04-26 18:17:09 +02:00
David Lenfesty
121e5bc92b
Generate ethernet peripherals for f2 and f4
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These are eth v1b, according to stm32-rs it should have the same register
changes as v1c, so I just copied it over.
2022-04-26 10:09:28 -06:00
David Lenfesty
05bf8c23c1
fix RCC MCO register for f1 CL variants
2022-04-26 10:04:50 -06:00
Ulf Lilleengen
83544cfdfc
Remove enums from l0 regs
2022-04-26 14:53:40 +02:00
Ulf Lilleengen
004542bf86
Add l0 flash support
2022-04-26 14:51:37 +02:00
Ulf Lilleengen
3dd39de946
Add flash for stm32wl
2022-04-26 14:51:37 +02:00
Jensenn
9728ff7a95
Remove useless fieldsets in LCD display memory
2022-04-25 12:08:32 -06:00
Jensenn
974de5f19b
Add BUFEN field from l4xx devices
2022-04-25 12:05:36 -06:00
Jensenn
338c78b771
Add LCD register set from l100 device
2022-04-25 12:04:23 -06:00
David Lenfesty
a0368410a5
Add STM32F107 ethernet v1a peripheral
2022-04-21 17:05:23 -06:00
Dario Nieuwenhuis
c01cb449e9
Add L5 PWR
2022-04-10 01:46:46 +02:00
Philip A Reimer
13a9eebb52
add l4 pwr enums
2022-04-09 11:05:50 -06:00
Philip A Reimer
5f64d3d148
arrayify l4 power control registers
2022-04-09 11:05:50 -06:00
Philip A Reimer
e81eeb157e
add pwr_l4
2022-04-09 11:05:50 -06:00
Dario Nieuwenhuis
c90234583e
RCC: fix USBFS -> USB
2022-04-09 00:43:48 +02:00
Dario Nieuwenhuis
6107d5a72e
Add USB
2022-04-09 00:28:44 +02:00
Dario Nieuwenhuis
b5d84de6e6
L5: add FLASH, SYSCFG
2022-04-08 02:54:56 +02:00
Dario Nieuwenhuis
eb678443a3
L5: fix RCC
2022-04-08 02:54:37 +02:00
Dario Nieuwenhuis
1d5853be40
run chiptool fmt with new version that trims descriptions.
2022-04-08 01:17:53 +02:00
Dario Nieuwenhuis
b797baeb14
Merge pull request #136 from ant32/main
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Use OTG v1 for v3
2022-03-30 01:27:02 +02:00
chemicstry
1d9e453670
Add missing timer ITR3 field
2022-03-30 01:59:08 +03:00
Philip A Reimer
62ebc483f9
use otg v1 for v3
2022-03-28 22:37:11 -06:00
Philip A Reimer
55163d5857
Add OTG FS v3
2022-03-24 21:16:11 -06:00
Nicolas Viennot
4ed9a42360
Add OTG register definitions
2022-03-20 19:07:24 -04:00
Dario Nieuwenhuis
b5ffa60b5f
Merge pull request #133 from nviennot/fsmc
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FSMC register block
2022-03-20 21:01:20 +01:00
Dario Nieuwenhuis
d5b53707d0
Merge pull request #132 from Gekkio/improve-f2-support
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F2: Add SYSCFG/FLASH/PWR, fix DBGMCU SVD typos
2022-03-20 20:59:33 +01:00
Nicolas Viennot
f9301d42f0
Add the FSMC register block
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The current v1 yaml has a few extra registers defined that don't belong to
some of the chips out there (the ones at byte_offset 320 and above), but
the rest of registers are identical.
2022-03-18 23:41:56 -04:00
Joonas Javanainen
f622be8f03
Add PWR block for F2
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Verified using RM0033 (F205xx/F207xx/F215xx/F217xx) Rev 9
2022-03-17 21:44:23 +02:00
Joonas Javanainen
dfc24f37fd
Fix F2 DBGMCU typos
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The typos come from the original SVD files
2022-03-17 21:37:27 +02:00
Joonas Javanainen
e36b972e3c
Add FLASH block for F2
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Verified using PM0059 Programming manual (F205/215, F207/217) Rev 5
2022-03-17 21:32:59 +02:00
Joonas Javanainen
b47951b4a2
Add SYSCFG block for F2
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Verified using RM0033 (F205xx/F207xx/F215xx/F217xx) Rev 9
2022-03-17 21:32:37 +02:00
chemicstry
410790c595
Update fieldset
2022-03-16 19:18:12 +02:00
chemicstry
802a2b8a29
Update fieldset
2022-03-16 18:50:55 +02:00
chemicstry
d29a2a3d20
Update fieldset
2022-03-16 18:48:50 +02:00
chemicstry
118dde4d4c
Fix fieldset
2022-03-16 18:44:25 +02:00
chemicstry
caa613eab2
Unify SDMMC register names
2022-03-16 18:40:36 +02:00
Matthew W. Samsonoff
03b2707944
stm32g0: fix embarrassing typo
2022-03-02 11:45:26 -05:00
Matthew W. Samsonoff
1a4706a799
stm32g0: add registers for FLASH
2022-03-02 11:27:38 -05:00
