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fix RCC MCO register for f1 CL variants

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This commit is contained in:
David Lenfesty 2022-04-26 09:44:38 -06:00
parent a0368410a5
commit 05bf8c23c1
3 changed files with 1142 additions and 3 deletions
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4
data/registers/rcc_f1.yaml
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@ -873,7 +873,7 @@ enum/I2S2SRC:
description: PLL3 VCO clock selected as I2S clock entry
value: 1
enum/MCO:
bit_size: 4
bit_size: 3
variants:
- name: NoMCO
description: "MCO output disabled, no clock on MCO"
@ -888,7 +888,7 @@ enum/MCO:
description: HSE oscillator clock selected
value: 6
- name: PLL
description: "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)"
description: "PLL clock divided by 2 selected"
value: 7
enum/OTGFSPRE:
bit_size: 1

1138
data/registers/rcc_f1cl.yaml Normal file
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3
stm32data/__main__.py
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@ -168,7 +168,8 @@ perimap = [
('.*:USB_OTG_HS:otghs1_v1_.*', ('otghs', 'v1', 'OTG_HS')),
('STM32F0.*:RCC:.*', ('rcc', 'f0', 'RCC')),
('STM32F1.*:RCC:.*', ('rcc', 'f1', 'RCC')),
('STM32F10[0123].*:RCC:.*', ('rcc', 'f1', 'RCC')),
('STM32F10[57].*:RCC:.*', ('rcc', 'f1cl', 'RCC')),
('STM32F2.*:RCC:.*', ('rcc', 'f2', 'RCC')),
('STM32F3.*:RCC:.*', ('rcc', 'f3', 'RCC')),
('STM32F410.*:RCC:.*', ('rcc', 'f410', 'RCC')),