Add FLASH block for F2

Verified using PM0059 Programming manual (F205/215, F207/217) Rev 5

data/registers/flash_f2.yaml

@@ -0,0 +1,328 @@
+---
+block/FLASH:
+  description: FLASH
+  items:
+    - name: ACR
+      description: Flash access control register
+      byte_offset: 0
+      fieldset: ACR
+    - name: KEYR
+      description: Flash key register
+      byte_offset: 4
+      access: Write
+      fieldset: KEYR
+    - name: OPTKEYR
+      description: Flash option key register
+      byte_offset: 8
+      access: Write
+      fieldset: OPTKEYR
+    - name: SR
+      description: Status register
+      byte_offset: 12
+      fieldset: SR
+    - name: CR
+      description: Control register
+      byte_offset: 16
+      fieldset: CR
+    - name: OPTCR
+      description: Flash option control register
+      byte_offset: 20
+      fieldset: OPTCR
+fieldset/ACR:
+  description: Flash access control register
+  fields:
+    - name: LATENCY
+      description: Latency
+      bit_offset: 0
+      bit_size: 3
+      enum: LATENCY
+    - name: PRFTEN
+      description: Prefetch enable
+      bit_offset: 8
+      bit_size: 1
+      enum: PRFTEN
+    - name: ICEN
+      description: Instruction cache enable
+      bit_offset: 9
+      bit_size: 1
+      enum: ICEN
+    - name: DCEN
+      description: Data cache enable
+      bit_offset: 10
+      bit_size: 1
+      enum: DCEN
+    - name: ICRST
+      description: Instruction cache reset
+      bit_offset: 11
+      bit_size: 1
+      enum: ICRST
+    - name: DCRST
+      description: Data cache reset
+      bit_offset: 12
+      bit_size: 1
+      enum: DCRST
+fieldset/CR:
+  description: Control register
+  fields:
+    - name: PG
+      description: Programming
+      bit_offset: 0
+      bit_size: 1
+      enum: PG
+    - name: SER
+      description: Sector Erase
+      bit_offset: 1
+      bit_size: 1
+      enum: SER
+    - name: MER
+      description: Mass Erase
+      bit_offset: 2
+      bit_size: 1
+      enum: MER
+    - name: SNB
+      description: Sector number
+      bit_offset: 3
+      bit_size: 4
+    - name: PSIZE
+      description: Program size
+      bit_offset: 8
+      bit_size: 2
+      enum: PSIZE
+    - name: STRT
+      description: Start
+      bit_offset: 16
+      bit_size: 1
+      enum: STRT
+    - name: EOPIE
+      description: End of operation interrupt enable
+      bit_offset: 24
+      bit_size: 1
+      enum: EOPIE
+    - name: ERRIE
+      description: Error interrupt enable
+      bit_offset: 25
+      bit_size: 1
+      enum: ERRIE
+    - name: LOCK
+      description: Lock
+      bit_offset: 31
+      bit_size: 1
+      enum: LOCK
+fieldset/KEYR:
+  description: Flash key register
+  fields:
+    - name: KEY
+      description: FPEC key
+      bit_offset: 0
+      bit_size: 32
+fieldset/OPTCR:
+  description: Flash option control register
+  fields:
+    - name: OPTLOCK
+      description: Option lock
+      bit_offset: 0
+      bit_size: 1
+    - name: OPTSTRT
+      description: Option start
+      bit_offset: 1
+      bit_size: 1
+    - name: BOR_LEV
+      description: BOR reset Level
+      bit_offset: 2
+      bit_size: 2
+    - name: WDG_SW
+      description: WDG_SW User option bytes
+      bit_offset: 5
+      bit_size: 1
+    - name: nRST_STOP
+      description: nRST_STOP User option bytes
+      bit_offset: 6
+      bit_size: 1
+    - name: nRST_STDBY
+      description: nRST_STDBY User option bytes
+      bit_offset: 7
+      bit_size: 1
+    - name: RDP
+      description: Read protect
+      bit_offset: 8
+      bit_size: 8
+    - name: nWRP
+      description: Not write protect
+      bit_offset: 16
+      bit_size: 12
+fieldset/OPTKEYR:
+  description: Flash option key register
+  fields:
+    - name: OPTKEY
+      description: Option byte key
+      bit_offset: 0
+      bit_size: 32
+fieldset/SR:
+  description: Status register
+  fields:
+    - name: EOP
+      description: End of operation
+      bit_offset: 0
+      bit_size: 1
+    - name: OPERR
+      description: Operation error
+      bit_offset: 1
+      bit_size: 1
+    - name: WRPERR
+      description: Write protection error
+      bit_offset: 4
+      bit_size: 1
+    - name: PGAERR
+      description: Programming alignment error
+      bit_offset: 5
+      bit_size: 1
+    - name: PGPERR
+      description: Programming parallelism error
+      bit_offset: 6
+      bit_size: 1
+    - name: PGSERR
+      description: Programming sequence error
+      bit_offset: 7
+      bit_size: 1
+    - name: BSY
+      description: Busy
+      bit_offset: 16
+      bit_size: 1
+enum/DCEN:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Data cache is disabled
+      value: 0
+    - name: Enabled
+      description: Data cache is enabled
+      value: 1
+enum/DCRST:
+  bit_size: 1
+  variants:
+    - name: NotReset
+      description: Data cache is not reset
+      value: 0
+    - name: Reset
+      description: Data cache is reset
+      value: 1
+enum/EOPIE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: End of operation interrupt disabled
+      value: 0
+    - name: Enabled
+      description: End of operation interrupt enabled
+      value: 1
+enum/ERRIE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Error interrupt generation disabled
+      value: 0
+    - name: Enabled
+      description: Error interrupt generation enabled
+      value: 1
+enum/ICEN:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Instruction cache is disabled
+      value: 0
+    - name: Enabled
+      description: Instruction cache is enabled
+      value: 1
+enum/ICRST:
+  bit_size: 1
+  variants:
+    - name: NotReset
+      description: Instruction cache is not reset
+      value: 0
+    - name: Reset
+      description: Instruction cache is reset
+      value: 1
+enum/LATENCY:
+  bit_size: 3
+  variants:
+    - name: WS0
+      description: 0 wait states
+      value: 0
+    - name: WS1
+      description: 1 wait states
+      value: 1
+    - name: WS2
+      description: 2 wait states
+      value: 2
+    - name: WS3
+      description: 3 wait states
+      value: 3
+    - name: WS4
+      description: 4 wait states
+      value: 4
+    - name: WS5
+      description: 5 wait states
+      value: 5
+    - name: WS6
+      description: 6 wait states
+      value: 6
+    - name: WS7
+      description: 7 wait states
+      value: 7
+enum/LOCK:
+  bit_size: 1
+  variants:
+    - name: Unlocked
+      description: FLASH_CR register is unlocked
+      value: 0
+    - name: Locked
+      description: FLASH_CR register is locked
+      value: 1
+enum/MER:
+  bit_size: 1
+  variants:
+    - name: MassErase
+      description: Erase activated for all user sectors
+      value: 1
+enum/PG:
+  bit_size: 1
+  variants:
+    - name: Program
+      description: Flash programming activated
+      value: 1
+enum/PRFTEN:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Prefetch is disabled
+      value: 0
+    - name: Enabled
+      description: Prefetch is enabled
+      value: 1
+enum/PSIZE:
+  bit_size: 2
+  variants:
+    - name: PSIZE8
+      description: Program x8
+      value: 0
+    - name: PSIZE16
+      description: Program x16
+      value: 1
+    - name: PSIZE32
+      description: Program x32
+      value: 2
+    - name: PSIZE64
+      description: Program x64
+      value: 3
+enum/SER:
+  bit_size: 1
+  variants:
+    - name: SectorErase
+      description: Erase activated for selected sector
+      value: 1
+enum/STRT:
+  bit_size: 1
+  variants:
+    - name: Start
+      description: Trigger an erase operation
+      value: 1

stm32data/__main__.py

@@ -209,6 +209,7 @@ perimap = [
     ('STM32H7.*:FLASH:.*', ('flash', 'h7', 'FLASH')),
     ('STM32F0.*:FLASH:.*', ('flash', 'f0', 'FLASH')),
     ('STM32F1.*:FLASH:.*', ('flash', 'f1', 'FLASH')),
+    ('STM32F2.*:FLASH:.*', ('flash', 'f2', 'FLASH')),
     ('STM32F3.*:FLASH:.*', ('flash', 'f3', 'FLASH')),
     ('STM32F4.*:FLASH:.*', ('flash', 'f4', 'FLASH')),
     ('STM32F7.*:FLASH:.*', ('flash', 'f7', 'FLASH')),