L5: add FLASH, SYSCFG

data/registers/flash_l5.yaml

@@ -0,0 +1,698 @@
+---
+block/FLASH:
+  description: Flash
+  items:
+    - name: ACR
+      description: Access control register
+      byte_offset: 0
+      fieldset: ACR
+    - name: PDKEYR
+      description: Power down key register
+      byte_offset: 4
+      access: Write
+      fieldset: PDKEYR
+    - name: NSKEYR
+      description: Flash non-secure key register
+      byte_offset: 8
+      access: Write
+      fieldset: NSKEYR
+    - name: SECKEYR
+      description: Flash secure key register
+      byte_offset: 12
+      access: Write
+      fieldset: SECKEYR
+    - name: OPTKEYR
+      description: Flash option key register
+      byte_offset: 16
+      access: Write
+      fieldset: OPTKEYR
+    - name: LVEKEYR
+      description: Flash low voltage key register
+      byte_offset: 20
+      access: Write
+      fieldset: LVEKEYR
+    - name: NSSR
+      description: Flash status register
+      byte_offset: 32
+      fieldset: NSSR
+    - name: SECSR
+      description: Flash status register
+      byte_offset: 36
+      fieldset: SECSR
+    - name: NSCR
+      description: Flash non-secure control register
+      byte_offset: 40
+      fieldset: NSCR
+    - name: SECCR
+      description: Flash secure control register
+      byte_offset: 44
+      fieldset: SECCR
+    - name: ECCR
+      description: Flash ECC register
+      byte_offset: 48
+      fieldset: ECCR
+    - name: OPTR
+      description: Flash option register
+      byte_offset: 64
+      fieldset: OPTR
+    - name: NSBOOTADD0R
+      description: Flash non-secure boot address 0 register
+      byte_offset: 68
+      access: Write
+      fieldset: NSBOOTADD0R
+    - name: NSBOOTADD1R
+      description: Flash non-secure boot address 1 register
+      byte_offset: 72
+      access: Write
+      fieldset: NSBOOTADD1R
+    - name: SECBOOTADD0R
+      description: FFlash secure boot address 0 register
+      byte_offset: 76
+      fieldset: SECBOOTADD0R
+    - name: SECWM1R1
+      description: Flash bank 1 secure watermak1 register
+      byte_offset: 80
+      fieldset: SECWM1R1
+    - name: SECWM1R2
+      description: Flash secure watermak1 register 2
+      byte_offset: 84
+      fieldset: SECWM1R2
+    - name: WRP1AR
+      description: Flash Bank 1 WRP area A address register
+      byte_offset: 88
+      fieldset: WRP1AR
+    - name: WRP1BR
+      description: Flash Bank 1 WRP area B address register
+      byte_offset: 92
+      fieldset: WRP1BR
+    - name: SECWM2R1
+      description: Flash secure watermak2 register
+      byte_offset: 96
+      fieldset: SECWM2R1
+    - name: SECWM2R2
+      description: Flash secure watermak2 register2
+      byte_offset: 100
+      fieldset: SECWM2R2
+    - name: WRP2AR
+      description: Flash WPR2 area A address register
+      byte_offset: 104
+      fieldset: WRP2AR
+    - name: WRP2BR
+      description: Flash WPR2 area B address register
+      byte_offset: 108
+      fieldset: WRP2BR
+    - name: SECBB1R1
+      description: FLASH secure block based bank 1 register
+      byte_offset: 128
+      fieldset: SECBB1R1
+    - name: SECBB1R2
+      description: FLASH secure block based bank 1 register
+      byte_offset: 132
+      fieldset: SECBB1R2
+    - name: SECBB1R3
+      description: FLASH secure block based bank 1 register
+      byte_offset: 136
+      fieldset: SECBB1R3
+    - name: SECBB1R4
+      description: FLASH secure block based bank 1 register
+      byte_offset: 140
+      fieldset: SECBB1R4
+    - name: SECBB2R1
+      description: FLASH secure block based bank 2 register
+      byte_offset: 160
+      fieldset: SECBB2R1
+    - name: SECBB2R2
+      description: FLASH secure block based bank 2 register
+      byte_offset: 164
+      fieldset: SECBB2R2
+    - name: SECBB2R3
+      description: FLASH secure block based bank 2 register
+      byte_offset: 168
+      fieldset: SECBB2R3
+    - name: SECBB2R4
+      description: FLASH secure block based bank 2 register
+      byte_offset: 172
+      fieldset: SECBB2R4
+    - name: SECHDPCR
+      description: FLASH secure HDP control register
+      byte_offset: 192
+      fieldset: SECHDPCR
+    - name: PRIVCFGR
+      description: Power privilege configuration register
+      byte_offset: 196
+      fieldset: PRIVCFGR
+fieldset/ACR:
+  description: Access control register
+  fields:
+    - name: LATENCY
+      description: Latency
+      bit_offset: 0
+      bit_size: 4
+    - name: RUN_PD
+      description: Flash Power-down mode during Low-power run mode
+      bit_offset: 13
+      bit_size: 1
+    - name: SLEEP_PD
+      description: Flash Power-down mode during Low-power sleep mode
+      bit_offset: 14
+      bit_size: 1
+    - name: LVEN
+      description: LVEN
+      bit_offset: 15
+      bit_size: 1
+fieldset/ECCR:
+  description: Flash ECC register
+  fields:
+    - name: ADDR_ECC
+      description: ECC fail address
+      bit_offset: 0
+      bit_size: 19
+    - name: BK_ECC
+      description: BK_ECC
+      bit_offset: 21
+      bit_size: 1
+    - name: SYSF_ECC
+      description: SYSF_ECC
+      bit_offset: 22
+      bit_size: 1
+    - name: ECCIE
+      description: ECC correction interrupt enable
+      bit_offset: 24
+      bit_size: 1
+    - name: ECCC2
+      description: ECCC2
+      bit_offset: 28
+      bit_size: 1
+    - name: ECCD2
+      description: ECCD2
+      bit_offset: 29
+      bit_size: 1
+    - name: ECCC
+      description: ECC correction
+      bit_offset: 30
+      bit_size: 1
+    - name: ECCD
+      description: ECC detection
+      bit_offset: 31
+      bit_size: 1
+fieldset/LVEKEYR:
+  description: Flash low voltage key register
+  fields:
+    - name: LVEKEYR
+      description: LVEKEYR
+      bit_offset: 0
+      bit_size: 32
+fieldset/NSBOOTADD0R:
+  description: Flash non-secure boot address 0 register
+  fields:
+    - name: NSBOOTADD0
+      description: NSBOOTADD0
+      bit_offset: 7
+      bit_size: 25
+fieldset/NSBOOTADD1R:
+  description: Flash non-secure boot address 1 register
+  fields:
+    - name: NSBOOTADD1
+      description: NSBOOTADD1
+      bit_offset: 7
+      bit_size: 25
+fieldset/NSCR:
+  description: Flash non-secure control register
+  fields:
+    - name: NSPG
+      description: NSPG
+      bit_offset: 0
+      bit_size: 1
+    - name: NSPER
+      description: NSPER
+      bit_offset: 1
+      bit_size: 1
+    - name: NSMER1
+      description: NSMER1
+      bit_offset: 2
+      bit_size: 1
+    - name: NSPNB
+      description: NSPNB
+      bit_offset: 3
+      bit_size: 7
+    - name: NSBKER
+      description: NSBKER
+      bit_offset: 11
+      bit_size: 1
+    - name: NSMER2
+      description: NSMER2
+      bit_offset: 15
+      bit_size: 1
+    - name: NSSTRT
+      description: Options modification start
+      bit_offset: 16
+      bit_size: 1
+    - name: OPTSTRT
+      description: Options modification start
+      bit_offset: 17
+      bit_size: 1
+    - name: NSEOPIE
+      description: NSEOPIE
+      bit_offset: 24
+      bit_size: 1
+    - name: NSERRIE
+      description: NSERRIE
+      bit_offset: 25
+      bit_size: 1
+    - name: OBL_LAUNCH
+      description: Force the option byte loading
+      bit_offset: 27
+      bit_size: 1
+    - name: OPTLOCK
+      description: Options Lock
+      bit_offset: 30
+      bit_size: 1
+    - name: NSLOCK
+      description: NSLOCK
+      bit_offset: 31
+      bit_size: 1
+fieldset/NSKEYR:
+  description: Flash non-secure key register
+  fields:
+    - name: NSKEYR
+      description: NSKEYR
+      bit_offset: 0
+      bit_size: 32
+fieldset/NSSR:
+  description: Flash status register
+  fields:
+    - name: NSEOP
+      description: NSEOP
+      bit_offset: 0
+      bit_size: 1
+    - name: NSOPERR
+      description: NSOPERR
+      bit_offset: 1
+      bit_size: 1
+    - name: NSPROGERR
+      description: NSPROGERR
+      bit_offset: 3
+      bit_size: 1
+    - name: NSWRPERR
+      description: NSWRPERR
+      bit_offset: 4
+      bit_size: 1
+    - name: NSPGAERR
+      description: NSPGAERR
+      bit_offset: 5
+      bit_size: 1
+    - name: NSSIZERR
+      description: NSSIZERR
+      bit_offset: 6
+      bit_size: 1
+    - name: NSPGSERR
+      description: NSPGSERR
+      bit_offset: 7
+      bit_size: 1
+    - name: OPTWERR
+      description: OPTWERR
+      bit_offset: 13
+      bit_size: 1
+    - name: OPTVERR
+      description: OPTVERR
+      bit_offset: 15
+      bit_size: 1
+    - name: NSBSY
+      description: NSBusy
+      bit_offset: 16
+      bit_size: 1
+fieldset/OPTKEYR:
+  description: Flash option key register
+  fields:
+    - name: OPTKEYR
+      description: OPTKEYR
+      bit_offset: 0
+      bit_size: 32
+fieldset/OPTR:
+  description: Flash option register
+  fields:
+    - name: RDP
+      description: Read protection level
+      bit_offset: 0
+      bit_size: 8
+    - name: BOR_LEV
+      description: BOR reset Level
+      bit_offset: 8
+      bit_size: 3
+    - name: nRST_STOP
+      description: nRST_STOP
+      bit_offset: 12
+      bit_size: 1
+    - name: nRST_STDBY
+      description: nRST_STDBY
+      bit_offset: 13
+      bit_size: 1
+    - name: nRST_SHDW
+      description: nRST_SHDW
+      bit_offset: 14
+      bit_size: 1
+    - name: IWDG_SW
+      description: Independent watchdog selection
+      bit_offset: 16
+      bit_size: 1
+    - name: IWDG_STOP
+      description: Independent watchdog counter freeze in Stop mode
+      bit_offset: 17
+      bit_size: 1
+    - name: IWDG_STDBY
+      description: Independent watchdog counter freeze in Standby mode
+      bit_offset: 18
+      bit_size: 1
+    - name: WWDG_SW
+      description: Window watchdog selection
+      bit_offset: 19
+      bit_size: 1
+    - name: SWAP_BANK
+      description: SWAP_BANK
+      bit_offset: 20
+      bit_size: 1
+    - name: DB256K
+      description: DB256K
+      bit_offset: 21
+      bit_size: 1
+    - name: DBANK
+      description: DBANK
+      bit_offset: 22
+      bit_size: 1
+    - name: SRAM2_PE
+      description: SRAM2 parity check enable
+      bit_offset: 24
+      bit_size: 1
+    - name: SRAM2_RST
+      description: SRAM2 Erase when system reset
+      bit_offset: 25
+      bit_size: 1
+    - name: nSWBOOT0
+      description: nSWBOOT0
+      bit_offset: 26
+      bit_size: 1
+    - name: nBOOT0
+      description: nBOOT0
+      bit_offset: 27
+      bit_size: 1
+    - name: PA15_PUPEN
+      description: PA15_PUPEN
+      bit_offset: 28
+      bit_size: 1
+    - name: TZEN
+      description: TZEN
+      bit_offset: 31
+      bit_size: 1
+fieldset/PDKEYR:
+  description: Power down key register
+  fields:
+    - name: PDKEYR
+      description: RUN_PD in FLASH_ACR key
+      bit_offset: 0
+      bit_size: 32
+fieldset/PRIVCFGR:
+  description: Power privilege configuration register
+  fields:
+    - name: PRIV
+      description: PRIV
+      bit_offset: 0
+      bit_size: 1
+fieldset/SECBB1R1:
+  description: FLASH secure block based bank 1 register
+  fields:
+    - name: SECBB1
+      description: SECBB1
+      bit_offset: 0
+      bit_size: 32
+fieldset/SECBB1R2:
+  description: FLASH secure block based bank 1 register
+  fields:
+    - name: SECBB1
+      description: SECBB1
+      bit_offset: 0
+      bit_size: 32
+fieldset/SECBB1R3:
+  description: FLASH secure block based bank 1 register
+  fields:
+    - name: SECBB1
+      description: SECBB1
+      bit_offset: 0
+      bit_size: 32
+fieldset/SECBB1R4:
+  description: FLASH secure block based bank 1 register
+  fields:
+    - name: SECBB1
+      description: SECBB1
+      bit_offset: 0
+      bit_size: 32
+fieldset/SECBB2R1:
+  description: FLASH secure block based bank 2 register
+  fields:
+    - name: SECBB2
+      description: SECBB2
+      bit_offset: 0
+      bit_size: 32
+fieldset/SECBB2R2:
+  description: FLASH secure block based bank 2 register
+  fields:
+    - name: SECBB2
+      description: SECBB2
+      bit_offset: 0
+      bit_size: 32
+fieldset/SECBB2R3:
+  description: FLASH secure block based bank 2 register
+  fields:
+    - name: SECBB2
+      description: SECBB2
+      bit_offset: 0
+      bit_size: 32
+fieldset/SECBB2R4:
+  description: FLASH secure block based bank 2 register
+  fields:
+    - name: SECBB2
+      description: SECBB2
+      bit_offset: 0
+      bit_size: 32
+fieldset/SECBOOTADD0R:
+  description: FFlash secure boot address 0 register
+  fields:
+    - name: BOOT_LOCK
+      description: BOOT_LOCK
+      bit_offset: 0
+      bit_size: 1
+    - name: SECBOOTADD0
+      description: SECBOOTADD0
+      bit_offset: 7
+      bit_size: 25
+fieldset/SECCR:
+  description: Flash secure control register
+  fields:
+    - name: SECPG
+      description: SECPG
+      bit_offset: 0
+      bit_size: 1
+    - name: SECPER
+      description: SECPER
+      bit_offset: 1
+      bit_size: 1
+    - name: SECMER1
+      description: SECMER1
+      bit_offset: 2
+      bit_size: 1
+    - name: SECPNB
+      description: SECPNB
+      bit_offset: 3
+      bit_size: 7
+    - name: SECBKER
+      description: SECBKER
+      bit_offset: 11
+      bit_size: 1
+    - name: SECMER2
+      description: SECMER2
+      bit_offset: 15
+      bit_size: 1
+    - name: SECSTRT
+      description: SECSTRT
+      bit_offset: 16
+      bit_size: 1
+    - name: SECEOPIE
+      description: SECEOPIE
+      bit_offset: 24
+      bit_size: 1
+    - name: SECERRIE
+      description: SECERRIE
+      bit_offset: 25
+      bit_size: 1
+    - name: SECRDERRIE
+      description: SECRDERRIE
+      bit_offset: 26
+      bit_size: 1
+    - name: SECINV
+      description: SECINV
+      bit_offset: 29
+      bit_size: 1
+    - name: SECLOCK
+      description: SECLOCK
+      bit_offset: 31
+      bit_size: 1
+fieldset/SECHDPCR:
+  description: FLASH secure HDP control register
+  fields:
+    - name: HDP1_ACCDIS
+      description: HDP1_ACCDIS
+      bit_offset: 0
+      bit_size: 1
+    - name: HDP2_ACCDIS
+      description: HDP2_ACCDIS
+      bit_offset: 1
+      bit_size: 1
+fieldset/SECKEYR:
+  description: Flash secure key register
+  fields:
+    - name: SECKEYR
+      description: SECKEYR
+      bit_offset: 0
+      bit_size: 32
+fieldset/SECSR:
+  description: Flash status register
+  fields:
+    - name: SECEOP
+      description: SECEOP
+      bit_offset: 0
+      bit_size: 1
+    - name: SECOPERR
+      description: SECOPERR
+      bit_offset: 1
+      bit_size: 1
+    - name: SECPROGERR
+      description: SECPROGERR
+      bit_offset: 3
+      bit_size: 1
+    - name: SECWRPERR
+      description: SECWRPERR
+      bit_offset: 4
+      bit_size: 1
+    - name: SECPGAERR
+      description: SECPGAERR
+      bit_offset: 5
+      bit_size: 1
+    - name: SECSIZERR
+      description: SECSIZERR
+      bit_offset: 6
+      bit_size: 1
+    - name: SECPGSERR
+      description: SECPGSERR
+      bit_offset: 7
+      bit_size: 1
+    - name: SECRDERR
+      description: Secure read protection error
+      bit_offset: 14
+      bit_size: 1
+    - name: SECBSY
+      description: SECBusy
+      bit_offset: 16
+      bit_size: 1
+fieldset/SECWM1R1:
+  description: Flash bank 1 secure watermak1 register
+  fields:
+    - name: SECWM1_PSTRT
+      description: SECWM1_PSTRT
+      bit_offset: 0
+      bit_size: 7
+    - name: SECWM1_PEND
+      description: SECWM1_PEND
+      bit_offset: 16
+      bit_size: 7
+fieldset/SECWM1R2:
+  description: Flash secure watermak1 register 2
+  fields:
+    - name: PCROP1_PSTRT
+      description: PCROP1_PSTRT
+      bit_offset: 0
+      bit_size: 7
+    - name: PCROP1EN
+      description: PCROP1EN
+      bit_offset: 15
+      bit_size: 1
+    - name: HDP1_PEND
+      description: HDP1_PEND
+      bit_offset: 16
+      bit_size: 7
+    - name: HDP1EN
+      description: HDP1EN
+      bit_offset: 31
+      bit_size: 1
+fieldset/SECWM2R1:
+  description: Flash secure watermak2 register
+  fields:
+    - name: SECWM2_PSTRT
+      description: SECWM2_PSTRT
+      bit_offset: 0
+      bit_size: 7
+    - name: SECWM2_PEND
+      description: SECWM2_PEND
+      bit_offset: 16
+      bit_size: 7
+fieldset/SECWM2R2:
+  description: Flash secure watermak2 register2
+  fields:
+    - name: PCROP2_PSTRT
+      description: PCROP2_PSTRT
+      bit_offset: 0
+      bit_size: 7
+    - name: PCROP2EN
+      description: PCROP2EN
+      bit_offset: 15
+      bit_size: 1
+    - name: HDP2_PEND
+      description: HDP2_PEND
+      bit_offset: 16
+      bit_size: 7
+    - name: HDP2EN
+      description: HDP2EN
+      bit_offset: 31
+      bit_size: 1
+fieldset/WRP1AR:
+  description: Flash Bank 1 WRP area A address register
+  fields:
+    - name: WRP1A_PSTRT
+      description: WRP1A_PSTRT
+      bit_offset: 0
+      bit_size: 7
+    - name: WRP1A_PEND
+      description: WRP1A_PEND
+      bit_offset: 16
+      bit_size: 7
+fieldset/WRP1BR:
+  description: Flash Bank 1 WRP area B address register
+  fields:
+    - name: WRP1B_PSTRT
+      description: WRP1B_PSTRT
+      bit_offset: 0
+      bit_size: 7
+    - name: WRP1B_PEND
+      description: WRP1B_PEND
+      bit_offset: 16
+      bit_size: 7
+fieldset/WRP2AR:
+  description: Flash WPR2 area A address register
+  fields:
+    - name: WRP2A_PSTRT
+      description: WRP2A_PSTRT
+      bit_offset: 0
+      bit_size: 7
+    - name: WRP2A_PEND
+      description: WRP2A_PEND
+      bit_offset: 16
+      bit_size: 7
+fieldset/WRP2BR:
+  description: Flash WPR2 area B address register
+  fields:
+    - name: WRP2B_PSTRT
+      description: WRP2B_PSTRT
+      bit_offset: 0
+      bit_size: 7
+    - name: WRP2B_PEND
+      description: WRP2B_PEND
+      bit_offset: 16
+      bit_size: 7

data/registers/syscfg_l5.yaml

@@ -0,0 +1,456 @@
+---
+block/SYSCFG:
+  description: System configuration controller
+  items:
+    - name: SECCFGR
+      description: SYSCFG secure configuration register
+      byte_offset: 0
+      fieldset: SECCFGR
+    - name: CFGR1
+      description: configuration register 1
+      byte_offset: 4
+      fieldset: CFGR1
+    - name: FPUIMR
+      description: FPU interrupt mask register
+      byte_offset: 8
+      fieldset: FPUIMR
+    - name: CNSLCKR
+      description: SYSCFG CPU non-secure lock register
+      byte_offset: 12
+      fieldset: CNSLCKR
+    - name: CSLOCKR
+      description: SYSCFG CPU secure lock register
+      byte_offset: 16
+      fieldset: CSLOCKR
+    - name: CFGR2
+      description: CFGR2
+      byte_offset: 20
+      fieldset: CFGR2
+    - name: SCSR
+      description: SCSR
+      byte_offset: 24
+      fieldset: SCSR
+    - name: SKR
+      description: SKR
+      byte_offset: 28
+      access: Write
+      fieldset: SKR
+    - name: SWPR
+      description: SWPR
+      byte_offset: 32
+      access: Write
+      fieldset: SWPR
+    - name: SWPR2
+      description: SWPR2
+      byte_offset: 36
+      access: Write
+      fieldset: SWPR2
+    - name: RSSCMDR
+      description: RSSCMDR
+      byte_offset: 44
+      fieldset: RSSCMDR
+fieldset/CFGR1:
+  description: configuration register 1
+  fields:
+    - name: BOOSTEN
+      description: I/O analog switch voltage booster enable
+      bit_offset: 8
+      bit_size: 1
+    - name: ANASWVDD
+      description: GPIO analog switch control voltage selection
+      bit_offset: 9
+      bit_size: 1
+    - name: I2C_PB6_FMP
+      description: Fast-mode Plus (Fm+) driving capability activation on PB6
+      bit_offset: 16
+      bit_size: 1
+    - name: I2C_PB7_FMP
+      description: Fast-mode Plus (Fm+) driving capability activation on PB7
+      bit_offset: 17
+      bit_size: 1
+    - name: I2C_PB8_FMP
+      description: Fast-mode Plus (Fm+) driving capability activation on PB8
+      bit_offset: 18
+      bit_size: 1
+    - name: I2C_PB9_FMP
+      description: Fast-mode Plus (Fm+) driving capability activation on PB9
+      bit_offset: 19
+      bit_size: 1
+    - name: I2C1_FMP
+      description: I2C1 Fast-mode Plus driving capability activation
+      bit_offset: 20
+      bit_size: 1
+    - name: I2C2_FMP
+      description: I2C2 Fast-mode Plus driving capability activation
+      bit_offset: 21
+      bit_size: 1
+    - name: I2C3_FMP
+      description: I2C3 Fast-mode Plus driving capability activation
+      bit_offset: 22
+      bit_size: 1
+    - name: I2C4_FMP
+      description: I2C4_FMP
+      bit_offset: 23
+      bit_size: 1
+fieldset/CFGR2:
+  description: CFGR2
+  fields:
+    - name: CLL
+      description: LOCKUP (hardfault) output enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: SPL
+      description: SRAM2 parity lock bit
+      bit_offset: 1
+      bit_size: 1
+    - name: PVDL
+      description: PVD lock enable bit
+      bit_offset: 2
+      bit_size: 1
+    - name: ECCL
+      description: ECC Lock
+      bit_offset: 3
+      bit_size: 1
+    - name: SPF
+      description: SRAM2 parity error flag
+      bit_offset: 8
+      bit_size: 1
+fieldset/CNSLCKR:
+  description: SYSCFG CPU non-secure lock register
+  fields:
+    - name: LOCKNSVTOR
+      description: VTOR_NS register lock
+      bit_offset: 0
+      bit_size: 1
+    - name: LOCKNSMPU
+      description: Non-secure MPU registers lock
+      bit_offset: 1
+      bit_size: 1
+fieldset/CSLOCKR:
+  description: SYSCFG CPU secure lock register
+  fields:
+    - name: LOCKSVTAIRCR
+      description: LOCKSVTAIRCR
+      bit_offset: 0
+      bit_size: 1
+    - name: LOCKSMPU
+      description: LOCKSMPU
+      bit_offset: 1
+      bit_size: 1
+    - name: LOCKSAU
+      description: LOCKSAU
+      bit_offset: 2
+      bit_size: 1
+fieldset/FPUIMR:
+  description: FPU interrupt mask register
+  fields:
+    - name: FPU_IE
+      description: Floating point unit interrupts enable bits
+      bit_offset: 0
+      bit_size: 6
+fieldset/RSSCMDR:
+  description: RSSCMDR
+  fields:
+    - name: RSSCMD
+      description: RSS commands
+      bit_offset: 0
+      bit_size: 8
+fieldset/SCSR:
+  description: SCSR
+  fields:
+    - name: SRAM2ER
+      description: SRAM2 Erase
+      bit_offset: 0
+      bit_size: 1
+    - name: SRAM2BSY
+      description: SRAM2 busy by erase operation
+      bit_offset: 1
+      bit_size: 1
+fieldset/SECCFGR:
+  description: SYSCFG secure configuration register
+  fields:
+    - name: SYSCFGSEC
+      description: SYSCFG clock control security
+      bit_offset: 0
+      bit_size: 1
+    - name: CLASSBSEC
+      description: ClassB security
+      bit_offset: 1
+      bit_size: 1
+    - name: SRAM2SEC
+      description: SRAM2 security
+      bit_offset: 2
+      bit_size: 1
+    - name: FPUSEC
+      description: FPUSEC
+      bit_offset: 3
+      bit_size: 1
+fieldset/SKR:
+  description: SKR
+  fields:
+    - name: KEY
+      description: SRAM2 write protection key for software erase
+      bit_offset: 0
+      bit_size: 8
+fieldset/SWPR:
+  description: SWPR
+  fields:
+    - name: P0WP
+      description: P0WP
+      bit_offset: 0
+      bit_size: 1
+    - name: P1WP
+      description: P1WP
+      bit_offset: 1
+      bit_size: 1
+    - name: P2WP
+      description: P2WP
+      bit_offset: 2
+      bit_size: 1
+    - name: P3WP
+      description: P3WP
+      bit_offset: 3
+      bit_size: 1
+    - name: P4WP
+      description: P4WP
+      bit_offset: 4
+      bit_size: 1
+    - name: P5WP
+      description: P5WP
+      bit_offset: 5
+      bit_size: 1
+    - name: P6WP
+      description: P6WP
+      bit_offset: 6
+      bit_size: 1
+    - name: P7WP
+      description: P7WP
+      bit_offset: 7
+      bit_size: 1
+    - name: P8WP
+      description: P8WP
+      bit_offset: 8
+      bit_size: 1
+    - name: P9WP
+      description: P9WP
+      bit_offset: 9
+      bit_size: 1
+    - name: P10WP
+      description: P10WP
+      bit_offset: 10
+      bit_size: 1
+    - name: P11WP
+      description: P11WP
+      bit_offset: 11
+      bit_size: 1
+    - name: P12WP
+      description: P12WP
+      bit_offset: 12
+      bit_size: 1
+    - name: P13WP
+      description: P13WP
+      bit_offset: 13
+      bit_size: 1
+    - name: P14WP
+      description: P14WP
+      bit_offset: 14
+      bit_size: 1
+    - name: P15WP
+      description: P15WP
+      bit_offset: 15
+      bit_size: 1
+    - name: P16WP
+      description: P16WP
+      bit_offset: 16
+      bit_size: 1
+    - name: P17WP
+      description: P17WP
+      bit_offset: 17
+      bit_size: 1
+    - name: P18WP
+      description: P18WP
+      bit_offset: 18
+      bit_size: 1
+    - name: P19WP
+      description: P19WP
+      bit_offset: 19
+      bit_size: 1
+    - name: P20WP
+      description: P20WP
+      bit_offset: 20
+      bit_size: 1
+    - name: P21WP
+      description: P21WP
+      bit_offset: 21
+      bit_size: 1
+    - name: P22WP
+      description: P22WP
+      bit_offset: 22
+      bit_size: 1
+    - name: P23WP
+      description: P23WP
+      bit_offset: 23
+      bit_size: 1
+    - name: P24WP
+      description: P24WP
+      bit_offset: 24
+      bit_size: 1
+    - name: P25WP
+      description: P25WP
+      bit_offset: 25
+      bit_size: 1
+    - name: P26WP
+      description: P26WP
+      bit_offset: 26
+      bit_size: 1
+    - name: P27WP
+      description: P27WP
+      bit_offset: 27
+      bit_size: 1
+    - name: P28WP
+      description: P28WP
+      bit_offset: 28
+      bit_size: 1
+    - name: P29WP
+      description: P29WP
+      bit_offset: 29
+      bit_size: 1
+    - name: P30WP
+      description: P30WP
+      bit_offset: 30
+      bit_size: 1
+    - name: P31WP
+      description: SRAM2 page 31 write protection
+      bit_offset: 31
+      bit_size: 1
+fieldset/SWPR2:
+  description: SWPR2
+  fields:
+    - name: P32WP
+      description: P32WP
+      bit_offset: 0
+      bit_size: 1
+    - name: P33WP
+      description: P33WP
+      bit_offset: 1
+      bit_size: 1
+    - name: P34WP
+      description: P34WP
+      bit_offset: 2
+      bit_size: 1
+    - name: P35WP
+      description: P35WP
+      bit_offset: 3
+      bit_size: 1
+    - name: P36WP
+      description: P36WP
+      bit_offset: 4
+      bit_size: 1
+    - name: P37WP
+      description: P37WP
+      bit_offset: 5
+      bit_size: 1
+    - name: P38WP
+      description: P38WP
+      bit_offset: 6
+      bit_size: 1
+    - name: P39WP
+      description: P39WP
+      bit_offset: 7
+      bit_size: 1
+    - name: P40WP
+      description: P40WP
+      bit_offset: 8
+      bit_size: 1
+    - name: P41WP
+      description: P41WP
+      bit_offset: 9
+      bit_size: 1
+    - name: P42WP
+      description: P42WP
+      bit_offset: 10
+      bit_size: 1
+    - name: P43WP
+      description: P43WP
+      bit_offset: 11
+      bit_size: 1
+    - name: P44WP
+      description: P44WP
+      bit_offset: 12
+      bit_size: 1
+    - name: P45WP
+      description: P45WP
+      bit_offset: 13
+      bit_size: 1
+    - name: P46WP
+      description: P46WP
+      bit_offset: 14
+      bit_size: 1
+    - name: P47WP
+      description: P47WP
+      bit_offset: 15
+      bit_size: 1
+    - name: P48WP
+      description: P48WP
+      bit_offset: 16
+      bit_size: 1
+    - name: P49WP
+      description: P49WP
+      bit_offset: 17
+      bit_size: 1
+    - name: P50WP
+      description: P50WP
+      bit_offset: 18
+      bit_size: 1
+    - name: P51WP
+      description: P51WP
+      bit_offset: 19
+      bit_size: 1
+    - name: P52WP
+      description: P52WP
+      bit_offset: 20
+      bit_size: 1
+    - name: P53WP
+      description: P53WP
+      bit_offset: 21
+      bit_size: 1
+    - name: P54WP
+      description: P54WP
+      bit_offset: 22
+      bit_size: 1
+    - name: P55WP
+      description: P55WP
+      bit_offset: 23
+      bit_size: 1
+    - name: P56WP
+      description: P56WP
+      bit_offset: 24
+      bit_size: 1
+    - name: P57WP
+      description: P57WP
+      bit_offset: 25
+      bit_size: 1
+    - name: P58WP
+      description: P58WP
+      bit_offset: 26
+      bit_size: 1
+    - name: P59WP
+      description: P59WP
+      bit_offset: 27
+      bit_size: 1
+    - name: P60WP
+      description: P60WP
+      bit_offset: 28
+      bit_size: 1
+    - name: P61WP
+      description: P61WP
+      bit_offset: 29
+      bit_size: 1
+    - name: P62WP
+      description: P62WP
+      bit_offset: 30
+      bit_size: 1
+    - name: P63WP
+      description: P63WP
+      bit_offset: 31
+      bit_size: 1

stm32data/__main__.py

@@ -134,9 +134,10 @@ perimap = [
     ('STM32F3.*:SYSCFG:.*',  ('syscfg', 'f3', 'SYSCFG')),
     ('STM32F4.*:SYSCFG:.*',  ('syscfg', 'f4', 'SYSCFG')),
     ('STM32F7.*:SYSCFG:.*',  ('syscfg', 'f7', 'SYSCFG')),
-    ('STM32L4.*:SYSCFG:.*',  ('syscfg', 'l4', 'SYSCFG')),
     ('STM32L0.*:SYSCFG:.*',  ('syscfg', 'l0', 'SYSCFG')),
     ('STM32L1.*:SYSCFG:.*',  ('syscfg', 'l1', 'SYSCFG')),
+    ('STM32L4.*:SYSCFG:.*',  ('syscfg', 'l4', 'SYSCFG')),
+    ('STM32L5.*:SYSCFG:.*',  ('syscfg', 'l5', 'SYSCFG')),
     ('STM32G0.*:SYSCFG:.*',  ('syscfg', 'g0', 'SYSCFG')),
     ('STM32G4.*:SYSCFG:.*',  ('syscfg', 'g4', 'SYSCFG')),
     ('STM32H7.*:SYSCFG:.*',  ('syscfg', 'h7', 'SYSCFG')),
@@ -219,6 +220,7 @@ perimap = [
     ('STM32F7.*:FLASH:.*', ('flash', 'f7', 'FLASH')),
     ('STM32L1.*:FLASH:.*', ('flash', 'l1', 'FLASH')),
     ('STM32L4.*:FLASH:.*', ('flash', 'l4', 'FLASH')),
+    ('STM32L5.*:FLASH:.*', ('flash', 'l5', 'FLASH')),
     ('STM32U5.*:FLASH:.*', ('flash', 'u5', 'FLASH')),
     ('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')),
     ('STM32G0.*:FLASH:.*', ('flash', 'g0', 'FLASH')),