Matous Hybl
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8402040d17
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Fix generation of FMC peripheral in chip yamls. Add FMC registers.
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2021-12-08 20:01:57 +01:00 |
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VasanthakumarV
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ef950a6feb
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[generate] Create SYSCFG, PWR, FLASH register files
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2021-12-08 15:43:23 +05:30 |
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Dario Nieuwenhuis
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f6c9772cf4
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usart: make v1 and v2 more consistent.
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2021-12-08 04:48:21 +01:00 |
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Dario Nieuwenhuis
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df6b1a13b0
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rcc_f3: add lots of missing stuff.
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2021-11-28 23:25:16 +01:00 |
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Dario Nieuwenhuis
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3780dbab57
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rcc_l5: fix typo
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2021-11-28 22:45:06 +01:00 |
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Dario Nieuwenhuis
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2e8c0bc791
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Fix stm32u5 accidentally removed fieldset/PRIVCFGR
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2021-11-27 02:32:51 +01:00 |
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Dario Nieuwenhuis
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353411841c
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stm32g4 support.
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2021-11-27 02:20:17 +01:00 |
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Dario Nieuwenhuis
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6af084d858
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SYSCFG_H7: random typo fix
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2021-11-27 02:19:55 +01:00 |
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Dario Nieuwenhuis
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b630a96365
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PWR: arrayify PUCRx, PDCRx
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2021-11-27 02:19:38 +01:00 |
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Dario Nieuwenhuis
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0dcaaa07fe
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cleanup spi v1/f1, add missing i2s stuff
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2021-11-17 21:30:52 +01:00 |
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Dario Nieuwenhuis
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c6c5c099bb
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fmt all register yamls
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2021-11-17 21:23:26 +01:00 |
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Bob McWhirter
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e501a9746f
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Complete enum cleanup.
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2021-11-11 14:52:45 -05:00 |
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Bob McWhirter
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91c77958bd
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Remove some useless enums.
Apply better variant names to some enums.
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2021-11-11 14:09:49 -05:00 |
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Bob McWhirter
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117e3f3f4b
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Clean up some enum variants, reduce some enums that duplicate.
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2021-11-11 10:25:04 -05:00 |
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Matous Hybl
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bfc7856d75
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Fix DCMI reset.
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2021-11-10 17:31:06 +01:00 |
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Bob McWhirter
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d2e9ef3622
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U5 FLASH and RCC.
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2021-11-08 13:48:03 -05:00 |
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Matous Hybl
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6ef7659b9d
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Add support for H723 RCC differences.
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2021-11-04 15:26:52 +01:00 |
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Matous Hybl
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3d7e46e6c9
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Fix v1c ethernet definition.
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2021-11-03 10:13:15 +01:00 |
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Bob McWhirter
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21f31372a6
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Adjust the d script.
Extract some peripherals for U5.
Update parse.py for some U5 perculiarities.
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2021-11-02 12:02:38 -04:00 |
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Ben Gamari
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2f42ebcd2c
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Add support for LPTIM peripherals
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2021-10-26 17:55:48 +02:00 |
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Matous Hybl
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2e1302c4e8
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Support for STM32F767ZI and basic support for the rest of the family.
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2021-10-25 10:38:28 +02:00 |
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Tobias Pisani
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b8de47fa04
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feat: Add F1 SPI registers
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2021-10-06 20:51:27 +02:00 |
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Dario Nieuwenhuis
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f6ce6dc36b
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CRC register cleanup
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2021-09-27 00:26:24 +02:00 |
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Joshua Salzedo
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24dabf68e5
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Add three distinct versions of CRC
- remove F4 specific version
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2021-09-26 14:58:47 -07:00 |
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Joshua Salzedo
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a8a8b88661
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add CRC32 peripheral for the F4 family
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2021-09-24 16:59:18 -07:00 |
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Vincent Stakenburg
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97fd020941
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add l4 flash register
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2021-09-24 16:45:59 +02:00 |
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Mariusz Ryndzionek
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8dde100c15
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Updated register mapping for STM32 F1 AFIO
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2021-09-23 18:54:22 +02:00 |
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Dario Nieuwenhuis
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5dec590202
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Merge pull request #85 from mryndzionek/stm32f1_support
Add initial register mapping for STM32 F1 AFIO and FLASH
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2021-09-23 17:36:38 +02:00 |
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Ulf Lilleengen
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a302947e87
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Add PWR register block and fix RCC register block
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2021-09-23 14:40:59 +02:00 |
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Mariusz Ryndzionek
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fbea23bd00
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Added missing FLASH registers (generated automatically)
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2021-09-23 07:09:11 +02:00 |
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Mariusz Ryndzionek
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c0938c9102
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Add initial register mapping for STM32 F1 AFIO and FLASH
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2021-09-22 18:22:36 +02:00 |
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Ulf Lilleengen
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9f1bd7d0d0
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Update chip yaml
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2021-09-15 14:47:33 +02:00 |
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Dario Nieuwenhuis
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616a2779d0
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Merge pull request #82 from bgamari/stm32g0
Fix ADC register layout on STM32G0
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2021-08-31 22:21:51 +02:00 |
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Ulf Lilleengen
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902b9a6986
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Add PWR peripheral for STM32WL5
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2021-08-31 14:34:54 +02:00 |
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Ben Gamari
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3a88360dc6
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Add PWR registers for STM32G0
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2021-08-31 01:46:26 -04:00 |
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Ben Gamari
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5366833cbd
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Introduce ADC register set for STM32G0
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2021-08-31 01:46:02 -04:00 |
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Dario Nieuwenhuis
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deb37365d7
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exti: g0 and l5 are 8 bits per line...
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2021-08-20 01:26:33 +02:00 |
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Dario Nieuwenhuis
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8534ae884d
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rcc: make GPIO EN/RST regs naming consistent.
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2021-08-19 23:50:42 +02:00 |
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Dario Nieuwenhuis
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3b6363dffb
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wl rcc: rename SPI2S2 -> SPI2
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2021-08-19 22:37:07 +02:00 |
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Dario Nieuwenhuis
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49e579e97f
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Add F2 RCC
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2021-08-19 22:12:39 +02:00 |
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Dario Nieuwenhuis
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e289dd883f
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Cleanup EXTI
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2021-08-19 21:54:22 +02:00 |
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Dario Nieuwenhuis
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701ab04c2a
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Cleanup SYSCFG naming
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2021-08-19 21:28:32 +02:00 |
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Dario Nieuwenhuis
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31997049ea
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Fix wrong register offsets in WB SYSCFG
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2021-08-19 19:20:13 +02:00 |
|
Dario Nieuwenhuis
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6af9f2c0d1
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Add RCC for F3, F7, G4, H7AB, L1, L5, WB*, WL5, WLE
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2021-08-19 19:13:30 +02:00 |
|
Ben Gamari
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f57a268b9f
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Add STM32G0 support
Includes manually specified register layouts for EXTI and SYSCFG.
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2021-08-19 15:57:00 +02:00 |
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Ben Gamari
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f5808de749
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Add RCC support for STM32G0
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2021-08-19 15:54:36 +02:00 |
|
Ulf Lilleengen
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919a61e847
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Add STM32WL5x exti block
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2021-08-17 13:02:49 +02:00 |
|
Bob McWhirter
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541091cded
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Include the reg block.
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2021-08-16 15:12:17 -04:00 |
|
Timo Kröger
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198e4f3247
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Add bxcan registers
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2021-08-06 11:52:47 +02:00 |
|
Timo Kröger
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7506b50031
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rcc_l4: Remove duplicate bits
|
2021-08-03 16:33:59 +02:00 |
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