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93 Commits

Author SHA1 Message Date
Dario Nieuwenhuis
eff26e3e77 Add stm32u5 GPDMA, SPI 2022-04-26 23:53:28 +02:00
Joonas Javanainen
ad291b5af3 Map spi2s1_v2_1 used on F2 devices 
This seems identical to v2_2 (as used by F429) with one naming exception
in status register SR bit 8 (TI frame format error):

v2_1 data names the bit "TIFRFE" and the enum TIFRERR
v2_2 data names the bit "FRE" and the enum FRER

The register bit layout is identical.
 2022-04-26 20:24:36 +03:00
Dario Nieuwenhuis
2db5d47cc6 Merge pull request #140 from davidlenfesty/eth-v1a 
Generate support for ethernet v1a and v1b
 2022-04-26 18:28:41 +02:00
Ulf Lilleengen
afcd7a7d69 Rename flash_w[bl]55 flash_w[bl] 2022-04-26 18:17:09 +02:00
David Lenfesty
121e5bc92b Generate ethernet peripherals for f2 and f4 
These are eth v1b, according to stm32-rs it should have the same register
changes as v1c, so I just copied it over.
 2022-04-26 10:09:28 -06:00
David Lenfesty
05bf8c23c1 fix RCC MCO register for f1 CL variants 2022-04-26 10:04:50 -06:00
Ulf Lilleengen
004542bf86 Add l0 flash support 2022-04-26 14:51:37 +02:00
Ulf Lilleengen
3dd39de946 Add flash for stm32wl 2022-04-26 14:51:37 +02:00
David Lenfesty
a0368410a5 Add STM32F107 ethernet v1a peripheral 2022-04-21 17:05:23 -06:00
Dario Nieuwenhuis
c01cb449e9 Add L5 PWR 2022-04-10 01:46:46 +02:00
Philip A Reimer
e81eeb157e add pwr_l4 2022-04-09 11:05:50 -06:00
Dario Nieuwenhuis
6107d5a72e Add USB 2022-04-09 00:28:44 +02:00
Dario Nieuwenhuis
b5d84de6e6 L5: add FLASH, SYSCFG 2022-04-08 02:54:56 +02:00
Philip A Reimer
62ebc483f9 use otg v1 for v3 2022-03-28 22:37:11 -06:00
Philip A Reimer
55163d5857 Add OTG FS v3 2022-03-24 21:16:11 -06:00
Nicolas Viennot
4ed9a42360 Add OTG register definitions 2022-03-20 19:07:24 -04:00
Dario Nieuwenhuis
b5ffa60b5f Merge pull request #133 from nviennot/fsmc 
FSMC register block
 2022-03-20 21:01:20 +01:00
Dario Nieuwenhuis
6ee54e8bf1 Merge pull request #131 from chemicstry/f4_uart 
Fix F4 UART definitions
 2022-03-20 21:00:04 +01:00
Dario Nieuwenhuis
d5b53707d0 Merge pull request #132 from Gekkio/improve-f2-support 
F2: Add SYSCFG/FLASH/PWR, fix DBGMCU SVD typos
 2022-03-20 20:59:33 +01:00
Dario Nieuwenhuis
ca8f4b3e0d Merge pull request #130 from chemicstry/sdio_fix2 
Unify SDMMC v1 and v2 register names
 2022-03-20 20:52:20 +01:00
Dario Nieuwenhuis
5c2ec818f6 Merge pull request #129 from nviennot/timer_clock 
Timers use the clock speed apb1_tim and apb2_tim
 2022-03-20 20:51:45 +01:00
Nicolas Viennot
f9301d42f0 Add the FSMC register block 
The current v1 yaml has a few extra registers defined that don't belong to
some of the chips out there (the ones at byte_offset 320 and above), but
the rest of registers are identical.
 2022-03-18 23:41:56 -04:00
Joonas Javanainen
f622be8f03 Add PWR block for F2 
Verified using RM0033 (F205xx/F207xx/F215xx/F217xx) Rev 9
 2022-03-17 21:44:23 +02:00
Joonas Javanainen
e36b972e3c Add FLASH block for F2 
Verified using PM0059 Programming manual (F205/215, F207/217) Rev 5
 2022-03-17 21:32:59 +02:00
Joonas Javanainen
b47951b4a2 Add SYSCFG block for F2 
Verified using RM0033 (F205xx/F207xx/F215xx/F217xx) Rev 9
 2022-03-17 21:32:37 +02:00
chemicstry
0f80d10a1f Fix F4 UART parsing 2022-03-17 16:33:34 +02:00
chemicstry
caa613eab2 Unify SDMMC register names 2022-03-16 18:40:36 +02:00
Nicolas Viennot
b3f9f3e286 Timers use the clock speed apb1_tim and apb2_tim 2022-03-15 02:55:33 -04:00
Nicolas Viennot
2cd7632fc9 Add SPI modules for F1 family 2022-03-15 02:51:18 -04:00
Grant Miller
ea9e59931f Don't rename DMA channels if they don't start at zero 2022-03-08 16:18:24 -06:00
Grant Miller
a1972e7a22 Create tmp/dmas/ if it doesn't exist 2022-03-08 15:53:16 -06:00
Matthew W. Samsonoff
1a4706a799 stm32g0: add registers for FLASH 2022-03-02 11:27:38 -05:00
Dario Nieuwenhuis
ce7ba764c9 fix multicore nvic 2022-02-25 01:14:39 +01:00
Dario Nieuwenhuis
8a935d22e5 Fix parsing of H7ab BDMA1/BDMA2 2022-02-24 05:55:16 +01:00
Dario Nieuwenhuis
66ecaf8b98 rcc: unify rcc_f0, rcc_f0x0 2022-02-14 00:25:12 +01:00
Dario Nieuwenhuis
3d6895a77f Rename clocks AHB -> AHB1, APB -> APB1. 
This makes it more consistent across chips, no more "AHB vs AHB1" issues.
 2022-02-13 23:22:10 +01:00
Dario Nieuwenhuis
8402b43853 remove 'registers' nested struct in rcc 2022-02-07 23:12:40 +01:00
Dario Nieuwenhuis
5365ea053a split "magic" block string into an object, so consumers don't have to do tricky parsing. 2022-02-07 23:12:40 +01:00
Dario Nieuwenhuis
32b5a815c6 change memory regions from dict to array 2022-02-07 20:37:35 +01:00
Dario Nieuwenhuis
00fc25453d switch chip files from yaml to json. remove OrderedDict. 2022-02-07 02:06:23 +01:00
Dario Nieuwenhuis
7b368b0035 move memory parsing to own file 2022-02-07 02:06:23 +01:00
Dario Nieuwenhuis
48fdf50203 Change peripherals from dict to array 2022-02-07 02:05:30 +01:00
Dario Nieuwenhuis
d8b8bac3a5 change dma channels from dict to array 2022-02-07 02:05:30 +01:00
Dario Nieuwenhuis
f07c93a64a change chip interrupts from dict to array 2022-02-07 02:05:30 +01:00
Dario Nieuwenhuis
2a14936a5e Split interrupt parsing to separate module 2022-02-05 01:45:34 +01:00
Dario Nieuwenhuis
048f6766fd lpuart: cleanup v1, v2. Merge v2 and v3 2022-02-05 00:59:20 +01:00
Maarten Oosting
e5da7538e1 LPUART: append lpuart peripherals to perimap 2022-02-05 00:59:20 +01:00
chemicstry
432619467f Fix encoding on windows 2022-02-04 15:49:56 +02:00
chemicstry
f1d0a09b79 Fix USB OTG pin AF parsing 2022-02-04 02:32:39 +02:00
chemicstry
8e1a07b928 Fix peripheral names with underscores 2022-02-04 01:49:39 +02:00