Split interrupt parsing to separate module
This commit is contained in:
Dario Nieuwenhuis
parent
183c31f534
commit
2a14936a5e
@ -9,9 +9,9 @@ import os
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from collections import OrderedDict
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from glob import glob
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from stm32data import yaml, header
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from stm32data import yaml, header, interrupts
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from stm32data.yaml import DecimalInt, HexInt
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from stm32data.util import removeprefix, removesuffix
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from stm32data.util import *
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def corename(d):
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@ -580,9 +580,11 @@ def parse_chips():
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chip['die'] = chip['xml']['Die']
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chip_nvic = next(filter(lambda x: x['@Name'] == 'NVIC', chip['ips'].values()), None)
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if chip_nvic is None:
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# L5, U5 have NVIC1=S, NVIC2=NS. Use NS.
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if chip_nvic is None and not chip_name.startswith('STM32L5') and not chip_name.startswith('STM32U5'):
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chip_nvic = next(filter(lambda x: x['@Name'] == 'NVIC1', chip['ips'].values()), None)
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chip_nvic = chip_nvic['@Version']
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if chip_nvic is None:
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chip_nvic = next(filter(lambda x: x['@Name'] == 'NVIC2', chip['ips'].values()), None)
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chip_dma = next(filter(lambda x: x['@Name'] == 'DMA', chip['ips'].values()), None)
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if chip_dma is not None:
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@ -614,25 +616,23 @@ def parse_chips():
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})
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cores.append(core)
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if (chip_nvic + '-' + core_name) in chip_interrupts:
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# if there's a more specific set of irqs...
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chip_nvic = chip_nvic + '-' + core_name
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if not core_name in h['interrupts'] or not core_name in h['defines']:
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core_name = 'all'
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# print("Defining for core", core_name)
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# Gather all interrupts and defines for this core
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interrupts = h['interrupts'][core_name]
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header_irqs = h['interrupts'][core_name]
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chip_irqs = interrupts.get(chip_nvic['@Name'], chip_nvic['@Version'], core_name)
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defines = h['defines'][core_name]
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# F100xE MISC_REMAP remaps some DMA IRQs, so ST decided to give two names
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# to the same IRQ number.
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if chip_name.startswith('STM32F100') and 'DMA2_Channel4_5' in interrupts:
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del interrupts['DMA2_Channel4_5']
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if chip_name.startswith('STM32F100') and 'DMA2_Channel4_5' in header_irqs:
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del header_irqs['DMA2_Channel4_5']
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core['interrupts'] = interrupts
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core['interrupts'] = header_irqs
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peri_kinds = {}
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@ -707,10 +707,9 @@ def parse_chips():
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pins = merge_periph_pins_info('STM32F1' in chip_name, pname, pins, af_pins)
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p['pins'] = pins
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if chip_nvic in chip_interrupts:
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if pname in chip_interrupts[chip_nvic]:
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# filter by available, because some are conditioned on <Die>
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p['interrupts'] = filter_interrupts(chip_interrupts[chip_nvic][pname], interrupts)
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if pname in chip_irqs:
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# filter by available, because some are conditioned on <Die>
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p['interrupts'] = interrupts.filter_interrupts(chip_irqs[pname], header_irqs)
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peris[pname] = p
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@ -1173,127 +1172,6 @@ def match_peri_clock(rcc_block, peri_name):
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return None
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chip_interrupts = {}
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def parse_interrupts():
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print("parsing interrupts")
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for f in glob('sources/cubedb/mcu/IP/NVIC*_Modes.xml'):
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f = f.replace(os.path.sep, '/')
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ff = removeprefix(f, 'sources/cubedb/mcu/IP/NVIC')
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ff = removesuffix(ff, '_Modes.xml')
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chip_irqs = {}
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r = xmltodict.parse(open(f, 'rb'))
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if ff.startswith('1') or ff.startswith('2'):
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ff = removeprefix(ff, '1')
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ff = removeprefix(ff, '2')
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core = corename(next(filter(lambda x: x['@Name'] == 'CoreName', r['IP']['RefParameter']))['@DefaultValue'])
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ff = ff + "-" + core
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ff = removeprefix(ff, '-')
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irqs = next(filter(lambda x: x['@Name'] == 'IRQn', r['IP']['RefParameter']))
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for irq in irqs['PossibleValue']:
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value = irq['@Value']
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parts = value.split(':')
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irq_name = removesuffix(parts[0], "_IRQn")
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# F100xE MISC_REMAP remaps some DMA IRQs, so ST decided to give two names
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# to the same IRQ number.
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if ff == 'STM32F100E' and irq_name == 'DMA2_Channel4_5':
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continue
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peri_names = parts[2].split(',')
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if len(peri_names) == 1 and peri_names[0] == '':
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continue
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elif len(peri_names) == 1 and (peri_names[0] == 'DMA' or peri_names[0].startswith("DMAL")):
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peri_names = [parts[3]]
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split = split_interrupts(peri_names, irq_name)
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for p in peri_names:
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if p not in chip_irqs:
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chip_irqs[p] = {}
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merge_peri_irq_signals(chip_irqs[p], split[p])
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chip_interrupts[ff] = chip_irqs
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def merge_peri_irq_signals(peri_irqs, additional):
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for key, value in additional.items():
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if key not in peri_irqs:
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peri_irqs[key] = []
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peri_irqs[key].append(value)
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def split_interrupts(peri_names, irq_name):
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split = {}
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for p in peri_names:
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split[p] = remap_interrupt_signals(p, irq_name)
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return split
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irq_signals_map = {
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'CAN': ['TX', 'RX0', 'RX1', 'SCE'],
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'I2C': ['ER', 'EV'],
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'TIM': ['BRK', 'UP', 'TRG', 'COM'],
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'HRTIM': ['Master', 'TIMA', 'TIMB', 'TIMC', 'TIMD', 'TIME', 'TIMF']
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}
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def remap_interrupt_signals(peri_name, irq_name):
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if peri_name == irq_name:
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return expand_all_irq_signals(peri_name, irq_name)
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if (peri_name.startswith('DMA') or peri_name.startswith('BDMA')) and irq_name.startswith(peri_name):
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return {irq_name: irq_name}
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if peri_name.startswith('USART') and irq_name.startswith(peri_name):
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return {'GLOBAL': irq_name}
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if peri_name in irq_name:
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signals = {}
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start = irq_name.index(peri_name)
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regexp = re.compile('(_[^_]+)')
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if match := regexp.findall(irq_name, start):
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for m in match:
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signal = removeprefix(m, '_').strip()
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if is_valid_irq_signal(peri_name, signal):
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signals[signal] = irq_name
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else:
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signals = expand_all_irq_signals(peri_name, irq_name)
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return signals
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else:
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return {'GLOBAL': irq_name}
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def is_valid_irq_signal(peri_name, signal):
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for prefix, signals in irq_signals_map.items():
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if peri_name.startswith(prefix):
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return signal in signals
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return False
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def expand_all_irq_signals(peri_name, irq_name):
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expanded = {}
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for prefix, signals in irq_signals_map.items():
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if peri_name.startswith(prefix):
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for s in irq_signals_map[prefix]:
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expanded[s] = irq_name
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return expanded
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return {'GLOBAL': irq_name}
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def filter_interrupts(peri_irqs, all_irqs):
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filtered = {}
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for signal, irqs in peri_irqs.items():
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for irq in all_irqs:
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if irq in irqs:
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filtered[signal] = irq
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break
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return filtered
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memories = []
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@ -1336,7 +1214,7 @@ def is_chip_name_match(pattern, chip_name):
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parse_memories()
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parse_interrupts()
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interrupts.parse()
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parse_rcc_regs()
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parse_documentations()
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parse_dma()
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124
stm32data/interrupts.py
Normal file
124
stm32data/interrupts.py
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@ -0,0 +1,124 @@
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from stm32data.util import *
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from glob import glob
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import xmltodict
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import re
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import os
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chip_interrupts = {}
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def get(nvic_name, nvic_version, core):
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return chip_interrupts[(nvic_name, nvic_version)]
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def parse():
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print("parsing interrupts")
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for f in glob('sources/cubedb/mcu/IP/NVIC*_Modes.xml'):
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f = f.replace(os.path.sep, '/')
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ff = removeprefix(f, 'sources/cubedb/mcu/IP/')
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ff = removesuffix(ff, '_Modes.xml')
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[nvic_name, nvic_version] = ff.split('-')
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chip_irqs = {}
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r = xmltodict.parse(open(f, 'rb'))
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irqs = next(filter(lambda x: x['@Name'] == 'IRQn', r['IP']['RefParameter']))
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for irq in irqs['PossibleValue']:
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value = irq['@Value']
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parts = value.split(':')
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irq_name = removesuffix(parts[0], "_IRQn")
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# F100xE MISC_REMAP remaps some DMA IRQs, so ST decided to give two names
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# to the same IRQ number.
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if nvic_version == 'STM32F100E' and irq_name == 'DMA2_Channel4_5':
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continue
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peri_names = parts[2].split(',')
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if len(peri_names) == 1 and peri_names[0] == '':
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continue
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elif len(peri_names) == 1 and (peri_names[0] == 'DMA' or peri_names[0].startswith("DMAL")):
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peri_names = [parts[3]]
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split = split_interrupts(peri_names, irq_name)
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for p in peri_names:
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if p not in chip_irqs:
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chip_irqs[p] = {}
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merge_peri_irq_signals(chip_irqs[p], split[p])
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chip_interrupts[(nvic_name, nvic_version)] = chip_irqs
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def merge_peri_irq_signals(peri_irqs, additional):
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for key, value in additional.items():
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if key not in peri_irqs:
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peri_irqs[key] = []
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peri_irqs[key].append(value)
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def split_interrupts(peri_names, irq_name):
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split = {}
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for p in peri_names:
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split[p] = remap_interrupt_signals(p, irq_name)
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return split
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irq_signals_map = {
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'CAN': ['TX', 'RX0', 'RX1', 'SCE'],
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'I2C': ['ER', 'EV'],
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'TIM': ['BRK', 'UP', 'TRG', 'COM'],
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'HRTIM': ['Master', 'TIMA', 'TIMB', 'TIMC', 'TIMD', 'TIME', 'TIMF']
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}
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def remap_interrupt_signals(peri_name, irq_name):
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if peri_name == irq_name:
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return expand_all_irq_signals(peri_name, irq_name)
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if (peri_name.startswith('DMA') or peri_name.startswith('BDMA')) and irq_name.startswith(peri_name):
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return {irq_name: irq_name}
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if peri_name.startswith('USART') and irq_name.startswith(peri_name):
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return {'GLOBAL': irq_name}
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if peri_name in irq_name:
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signals = {}
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start = irq_name.index(peri_name)
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regexp = re.compile('(_[^_]+)')
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if match := regexp.findall(irq_name, start):
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for m in match:
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signal = removeprefix(m, '_').strip()
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if is_valid_irq_signal(peri_name, signal):
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signals[signal] = irq_name
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else:
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signals = expand_all_irq_signals(peri_name, irq_name)
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return signals
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else:
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return {'GLOBAL': irq_name}
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def is_valid_irq_signal(peri_name, signal):
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for prefix, signals in irq_signals_map.items():
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if peri_name.startswith(prefix):
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return signal in signals
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return False
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def expand_all_irq_signals(peri_name, irq_name):
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expanded = {}
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for prefix, signals in irq_signals_map.items():
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if peri_name.startswith(prefix):
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for s in irq_signals_map[prefix]:
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expanded[s] = irq_name
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return expanded
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return {'GLOBAL': irq_name}
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def filter_interrupts(peri_irqs, all_irqs):
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filtered = {}
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for signal, irqs in peri_irqs.items():
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for irq in all_irqs:
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if irq in irqs:
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filtered[signal] = irq
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break
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return filtered
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