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Author SHA1 Message Date
Matous Hybl
6ef7659b9d Add support for H723 RCC differences. 2021-11-04 15:26:52 +01:00
Matous Hybl
dac1140b17 Fix pin names by removing pin functions in brackets. 2021-11-04 10:35:18 +01:00
Dario Nieuwenhuis
2e06408221 Merge pull request #96 from matoushybl/f7-support 
Fix v1c ethernet definition.
 2021-11-04 00:23:50 +01:00
Matous Hybl
3d7e46e6c9 Fix v1c ethernet definition. 2021-11-03 10:13:15 +01:00
Dario Nieuwenhuis
c40960c953 Merge pull request #95 from bobmcwhirter/weird_u5_headers 
Weird u5 headers
 2021-11-02 17:35:16 +01:00
Bob McWhirter
21f31372a6 Adjust the d script. 
Extract some peripherals for U5.
Update parse.py for some U5 perculiarities.
 2021-11-02 12:02:38 -04:00
Bob McWhirter
dc4a94e868 Parse out U5xx packages. 
Avoid barfing if we're not yet parsing DMA, because we aren't for GPDMA.
 2021-10-29 13:08:21 -04:00
Bob McWhirter
dca5886b25 Parse decimal in the form of '08U'. 
Parse division such as FLASH_BANK_SIZE / FLASH_SOMETHING in defines.
 2021-10-29 11:45:27 -04:00
Bob McWhirter
0358c950da Change d to just clone the -sources repository. 2021-10-28 13:48:36 -04:00
Dario Nieuwenhuis
09c1a7102a Merge pull request #93 from bgamari/wip/lptim 
stm32g0: Add support for LPTIM peripherals
 2021-10-26 17:57:15 +02:00
Ben Gamari
2f42ebcd2c Add support for LPTIM peripherals 2021-10-26 17:55:48 +02:00
Dario Nieuwenhuis
6bedd95ce1 Merge pull request #92 from matoushybl/f7-support 
Initial support for STM32F767ZI.
 2021-10-26 17:21:47 +02:00
Matous Hybl
2e1302c4e8 Support for STM32F767ZI and basic support for the rest of the family. 2021-10-25 10:38:28 +02:00
Ulf Lilleengen
a90f756dda Merge pull request #91 from topisani/main 
feat: Add F1 SPI registers
 2021-10-07 13:54:48 +02:00
Tobias Pisani
b8de47fa04 feat: Add F1 SPI registers 2021-10-06 20:51:27 +02:00
Dario Nieuwenhuis
6caf69650a Merge pull request #90 from mryndzionek/dev 
Added AFIO block definition to STM32F103C8 chip
 2021-09-27 16:04:27 +02:00
Mariusz Ryndzionek
9e6eff587c Correct AFIO support (code review request) 2021-09-27 15:35:29 +02:00
Dario Nieuwenhuis
fccbab0aae Merge pull request #89 from theunkn0wn1/feature/crc32 
F4 CRC peripheral
 2021-09-27 00:30:21 +02:00
Dario Nieuwenhuis
f6ce6dc36b CRC register cleanup 2021-09-27 00:26:24 +02:00
Joshua Salzedo
fb4d8b7033 Add CRC rules to parse.py 2021-09-26 15:09:45 -07:00
Joshua Salzedo
24dabf68e5 Add three distinct versions of CRC 
- remove F4 specific version
 2021-09-26 14:58:47 -07:00
Joshua Salzedo
a8a8b88661 add CRC32 peripheral for the F4 family 2021-09-24 16:59:18 -07:00
Dario Nieuwenhuis
9752672268 Merge pull request #88 from FrozenDroid/add-l4-flash 
Add L4 flash register
 2021-09-24 18:30:52 +02:00
Vincent Stakenburg
97fd020941 add l4 flash register 2021-09-24 16:45:59 +02:00
Vincent Stakenburg
f699571831 add l4 flash parse line 2021-09-24 16:45:17 +02:00
Dario Nieuwenhuis
e317d781d8 Merge pull request #87 from mryndzionek/stm32f1_support 
Updated register mapping for STM32 F1 AFIO
 2021-09-23 18:57:52 +02:00
Mariusz Ryndzionek
8dde100c15 Updated register mapping for STM32 F1 AFIO 2021-09-23 18:54:22 +02:00
Dario Nieuwenhuis
5dec590202 Merge pull request #85 from mryndzionek/stm32f1_support 
Add initial register mapping for STM32 F1 AFIO and FLASH
 2021-09-23 17:36:38 +02:00
Ulf Lilleengen
f1e7e9ef84 Merge pull request #86 from lulf/stm32l1-pwr-and-fix 
Add PWR register block and fix RCC register block
 2021-09-23 14:42:49 +02:00
Ulf Lilleengen
a302947e87 Add PWR register block and fix RCC register block 2021-09-23 14:40:59 +02:00
Mariusz Ryndzionek
fbea23bd00 Added missing FLASH registers (generated automatically) 2021-09-23 07:09:11 +02:00
Mariusz Ryndzionek
c0938c9102 Add initial register mapping for STM32 F1 AFIO and FLASH 2021-09-22 18:22:36 +02:00
Dario Nieuwenhuis
1d62ba5e14 Merge pull request #84 from lulf/l1-regs 
L1 regs
 2021-09-15 14:55:09 +02:00
Ulf Lilleengen
9f1bd7d0d0 Update chip yaml 2021-09-15 14:47:33 +02:00
Ulf Lilleengen
e2bf041808 Add register mapping for STM32 L1 SYSCFG and DBGMCU 
Add missing GPIO port mapping
 2021-09-15 14:47:01 +02:00
Dario Nieuwenhuis
616a2779d0 Merge pull request #82 from bgamari/stm32g0 
Fix ADC register layout on STM32G0
 2021-08-31 22:21:51 +02:00
Dario Nieuwenhuis
96c902c66c Merge pull request #83 from lulf/stm32wl55-pwr 
Stm32wl55 pwr
 2021-08-31 22:18:57 +02:00
Ulf Lilleengen
201510407c Handle SUBGHZSPI peripheral so it is recognized as an SPI peripheral 2021-08-31 14:43:02 +02:00
Ulf Lilleengen
902b9a6986 Add PWR peripheral for STM32WL5 2021-08-31 14:34:54 +02:00
Ben Gamari
3a88360dc6 Add PWR registers for STM32G0 2021-08-31 01:46:26 -04:00
Ben Gamari
5366833cbd Introduce ADC register set for STM32G0 2021-08-31 01:46:02 -04:00
Dario Nieuwenhuis
deb37365d7 exti: g0 and l5 are 8 bits per line... 2021-08-20 01:26:33 +02:00
Dario Nieuwenhuis
8534ae884d rcc: make GPIO EN/RST regs naming consistent. 2021-08-19 23:50:42 +02:00
Dario Nieuwenhuis
3b6363dffb wl rcc: rename SPI2S2 -> SPI2 2021-08-19 22:37:07 +02:00
Dario Nieuwenhuis
49e579e97f Add F2 RCC 2021-08-19 22:12:39 +02:00
Dario Nieuwenhuis
e289dd883f Cleanup EXTI 2021-08-19 21:54:22 +02:00
Dario Nieuwenhuis
701ab04c2a Cleanup SYSCFG naming 2021-08-19 21:28:32 +02:00
Dario Nieuwenhuis
31997049ea Fix wrong register offsets in WB SYSCFG 2021-08-19 19:20:13 +02:00
Dario Nieuwenhuis
6af9f2c0d1 Add RCC for F3, F7, G4, H7AB, L1, L5, WB*, WL5, WLE 2021-08-19 19:13:30 +02:00
Dario Nieuwenhuis
bd402a58f2 Merge pull request #72 from bgamari/stm32g0 
STM32G0 support
 2021-08-19 16:05:29 +02:00