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Merge pull request #86 from lulf/stm32l1-pwr-and-fix

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Add PWR register block and fix RCC register block
This commit is contained in:
Ulf Lilleengen 2021-09-23 14:42:49 +02:00 committed by GitHub
commit f1e7e9ef84
3 changed files with 111 additions and 452 deletions
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103
data/registers/pwr_l1.yaml Normal file
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@ -0,0 +1,103 @@
---
block/PWR:
description: Power control
items:
- name: CR
description: power control register
byte_offset: 0
fieldset: CR
- name: CSR
description: power control/status register
byte_offset: 4
fieldset: CSR
fieldset/CR:
description: power control register
fields:
- name: LPSDSR
description: Low-power deep sleep
bit_offset: 0
bit_size: 1
- name: PDDS
description: Power down deepsleep
bit_offset: 1
bit_size: 1
enum: PDDS
- name: CWUF
description: Clear wakeup flag
bit_offset: 2
bit_size: 1
- name: CSBF
description: Clear standby flag
bit_offset: 3
bit_size: 1
- name: PVDE
description: Power voltage detector enable
bit_offset: 4
bit_size: 1
- name: PLS
description: PVD level selection
bit_offset: 5
bit_size: 3
- name: DBP
description: Disable backup domain write protection
bit_offset: 8
bit_size: 1
- name: ULP
description: Ultralow power mode
bit_offset: 9
bit_size: 1
- name: FWU
description: Fast wakeup
bit_offset: 10
bit_size: 1
- name: VOS
description: Voltage scaling range selection
bit_offset: 11
bit_size: 2
- name: LPRUN
description: Low power run mode
bit_offset: 14
bit_size: 1
fieldset/CSR:
description: power control/status register
fields:
- name: WUF
description: Wakeup flag
bit_offset: 0
bit_size: 1
- name: SBF
description: Standby flag
bit_offset: 1
bit_size: 1
- name: PVDO
description: PVD output
bit_offset: 2
bit_size: 1
- name: VREFINTRDYF
description: Internal voltage reference (VREFINT) ready flag
bit_offset: 3
bit_size: 1
- name: VOSF
description: Voltage Scaling select flag
bit_offset: 4
bit_size: 1
- name: REGLPF
description: Regulator LP flag
bit_offset: 5
bit_size: 1
- name: EWUP
description: Enable WKUP pin 1
bit_offset: 8
bit_size: 1
array:
len: 3
stride: 1
enum/PDDS:
bit_size: 1
variants:
- name: STOP_MODE
description: Enter Stop mode when the CPU enters deepsleep
value: 0
- name: STANDBY_MODE
description: Enter Standby mode when the CPU enters deepsleep
value: 1

459
data/registers/rcc_l1.yaml
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@ -168,14 +168,6 @@ fieldset/AHBLPENR:
description: DMA2 clock enable during Sleep mode
bit_offset: 25
bit_size: 1
- name: AESLPEN
description: AES clock enable during Sleep mode
bit_offset: 27
bit_size: 1
- name: FSMCLPEN
description: FSMC clock enable during Sleep mode
bit_offset: 30
bit_size: 1
fieldset/AHBRSTR:
description: AHB peripheral reset register
fields:
@ -183,67 +175,54 @@ fieldset/AHBRSTR:
description: IO port A reset
bit_offset: 0
bit_size: 1
enum_write: FSMCRSTW
- name: GPIOBRST
description: IO port B reset
bit_offset: 1
bit_size: 1
enum_write: FSMCRSTW
- name: GPIOCRST
description: IO port C reset
bit_offset: 2
bit_size: 1
enum_write: FSMCRSTW
- name: GPIODRST
description: IO port D reset
bit_offset: 3
bit_size: 1
enum_write: FSMCRSTW
- name: GPIOERST
description: IO port E reset
bit_offset: 4
bit_size: 1
enum_write: FSMCRSTW
- name: GPIOHRST
description: IO port H reset
bit_offset: 5
bit_size: 1
enum_write: FSMCRSTW
- name: GPIOFRST
description: IO port F reset
bit_offset: 6
bit_size: 1
enum_write: FSMCRSTW
- name: GPIOGRST
description: IO port G reset
bit_offset: 7
bit_size: 1
enum_write: FSMCRSTW
- name: CRCRST
description: CRC reset
bit_offset: 12
bit_size: 1
enum_write: FSMCRSTW
- name: FLITFRST
description: FLITF reset
bit_offset: 15
bit_size: 1
enum_write: FSMCRSTW
- name: DMA1RST
description: DMA1 reset
bit_offset: 24
bit_size: 1
enum_write: FSMCRSTW
- name: DMA2RST
description: DMA2 reset
bit_offset: 25
bit_size: 1
enum_write: FSMCRSTW
- name: FSMCRST
description: FSMC reset
bit_offset: 30
bit_size: 1
enum_write: FSMCRSTW
fieldset/APB1ENR:
description: APB1 peripheral clock enable register
fields:
@ -342,10 +321,6 @@ fieldset/APB1LPENR:
description: Timer 4 clock enable during Sleep mode
bit_offset: 2
bit_size: 1
- name: TIM5LPEN
description: Timer 5 clock enable during Sleep mode
bit_offset: 3
bit_size: 1
- name: TIM6LPEN
description: Timer 6 clock enable during Sleep mode
bit_offset: 4
@ -366,10 +341,6 @@ fieldset/APB1LPENR:
description: SPI 2 clock enable during Sleep mode
bit_offset: 14
bit_size: 1
- name: SPI3LPEN
description: SPI 3 clock enable during Sleep mode
bit_offset: 15
bit_size: 1
- name: USART2LPEN
description: USART 2 clock enable during Sleep mode
bit_offset: 17
@ -378,14 +349,6 @@ fieldset/APB1LPENR:
description: USART 3 clock enable during Sleep mode
bit_offset: 18
bit_size: 1
- name: UART4LPEN
description: USART 4 clock enable during Sleep mode
bit_offset: 19
bit_size: 1
- name: UART5LPEN
description: USART 5 clock enable during Sleep mode
bit_offset: 20
bit_size: 1
- name: I2C1LPEN
description: I2C 1 clock enable during Sleep mode
bit_offset: 21
@ -417,102 +380,82 @@ fieldset/APB1RSTR:
description: Timer 2 reset
bit_offset: 0
bit_size: 1
enum_write: COMPRSTW
- name: TIM3RST
description: Timer 3 reset
bit_offset: 1
bit_size: 1
enum_write: COMPRSTW
- name: TIM4RST
description: Timer 4 reset
bit_offset: 2
bit_size: 1
enum_write: COMPRSTW
- name: TIM5RST
description: Timer 5 reset
bit_offset: 3
bit_size: 1
enum_write: COMPRSTW
- name: TIM6RST
description: Timer 6reset
bit_offset: 4
bit_size: 1
enum_write: COMPRSTW
- name: TIM7RST
description: Timer 7 reset
bit_offset: 5
bit_size: 1
enum_write: COMPRSTW
- name: LCDRST
description: LCD reset
bit_offset: 9
bit_size: 1
enum_write: COMPRSTW
- name: WWDRST
description: Window watchdog reset
bit_offset: 11
bit_size: 1
enum_write: COMPRSTW
- name: SPI2RST
description: SPI 2 reset
bit_offset: 14
bit_size: 1
enum_write: COMPRSTW
- name: SPI3RST
description: SPI 3 reset
bit_offset: 15
bit_size: 1
enum_write: COMPRSTW
- name: USART2RST
description: USART 2 reset
bit_offset: 17
bit_size: 1
enum_write: COMPRSTW
- name: USART3RST
description: USART 3 reset
bit_offset: 18
bit_size: 1
enum_write: COMPRSTW
- name: UART4RST
description: UART 4 reset
bit_offset: 19
bit_size: 1
enum_write: COMPRSTW
- name: UART5RST
description: UART 5 reset
bit_offset: 20
bit_size: 1
enum_write: COMPRSTW
- name: I2C1RST
description: I2C 1 reset
bit_offset: 21
bit_size: 1
enum_write: COMPRSTW
- name: I2C2RST
description: I2C 2 reset
bit_offset: 22
bit_size: 1
enum_write: COMPRSTW
- name: USBRST
description: USB reset
bit_offset: 23
bit_size: 1
enum_write: COMPRSTW
- name: PWRRST
description: Power interface reset
bit_offset: 28
bit_size: 1
enum_write: COMPRSTW
- name: DACRST
description: DAC interface reset
bit_offset: 29
bit_size: 1
enum_write: COMPRSTW
- name: COMPRST
description: COMP interface reset
bit_offset: 31
bit_size: 1
enum_write: COMPRSTW
fieldset/APB2ENR:
description: APB2 peripheral clock enable register
fields:
@ -590,42 +533,34 @@ fieldset/APB2RSTR:
description: SYSCFGRST
bit_offset: 0
bit_size: 1
enum_write: USARTRSTW
- name: TIM9RST
description: TIM9RST
bit_offset: 2
bit_size: 1
enum_write: USARTRSTW
- name: TM10RST
description: TM10RST
bit_offset: 3
bit_size: 1
enum_write: USARTRSTW
- name: TM11RST
description: TM11RST
bit_offset: 4
bit_size: 1
enum_write: USARTRSTW
- name: ADC1RST
description: ADC1RST
bit_offset: 9
bit_size: 1
enum_write: USARTRSTW
- name: SDIORST
description: SDIORST
bit_offset: 11
bit_size: 1
enum_write: USARTRSTW
- name: SPI1RST
description: SPI1RST
bit_offset: 12
bit_size: 1
enum_write: USARTRSTW
- name: USART1RST
description: USART1RST
bit_offset: 14
bit_size: 1
enum_write: USARTRSTW
fieldset/CFGR:
description: Clock configuration register
fields:
@ -633,52 +568,42 @@ fieldset/CFGR:
description: System clock switch
bit_offset: 0
bit_size: 2
enum: SW
- name: SWS
description: System clock switch status
bit_offset: 2
bit_size: 2
enum_read: SWSR
- name: HPRE
description: AHB prescaler
bit_offset: 4
bit_size: 4
enum: HPRE
- name: PPRE1
description: APB low-speed prescaler (APB1)
bit_offset: 8
bit_size: 3
enum: PPRE
- name: PPRE2
description: APB high-speed prescaler (APB2)
bit_offset: 11
bit_size: 3
enum: PPRE
- name: PLLSRC
description: PLL entry clock source
bit_offset: 16
bit_size: 1
enum: PLLSRC
- name: PLLMUL
description: PLL multiplication factor
bit_offset: 18
bit_size: 4
enum: PLLMUL
- name: PLLDIV
description: PLL output division
bit_offset: 22
bit_size: 2
enum: PLLDIV
- name: MCOSEL
description: Microcontroller clock output selection
bit_offset: 24
bit_size: 3
enum: MCOSEL
- name: MCOPRE
description: Microcontroller clock output prescaler
bit_offset: 28
bit_size: 3
enum: MCOPRE
fieldset/CIR:
description: Clock interrupt register
fields:
@ -686,117 +611,82 @@ fieldset/CIR:
description: LSI ready interrupt flag
bit_offset: 0
bit_size: 1
enum_read: MSIRDYFR
- name: LSERDYF
description: LSE ready interrupt flag
bit_offset: 1
bit_size: 1
enum_read: MSIRDYFR
- name: HSIRDYF
description: HSI ready interrupt flag
bit_offset: 2
bit_size: 1
enum_read: MSIRDYFR
- name: HSERDYF
description: HSE ready interrupt flag
bit_offset: 3
bit_size: 1
enum_read: MSIRDYFR
- name: PLLRDYF
description: PLL ready interrupt flag
bit_offset: 4
bit_size: 1
enum_read: MSIRDYFR
- name: MSIRDYF
description: MSI ready interrupt flag
bit_offset: 5
bit_size: 1
enum_read: MSIRDYFR
- name: LSECSSF
description: LSE Clock security system interrupt flag
bit_offset: 6
bit_size: 1
enum_read: LSECSSFR
- name: CSSF
description: Clock security system interrupt flag
bit_offset: 7
bit_size: 1
enum_read: CSSFR
- name: LSIRDYIE
description: LSI ready interrupt enable
bit_offset: 8
bit_size: 1
enum: MSIRDYIE
- name: LSERDYIE
description: LSE ready interrupt enable
bit_offset: 9
bit_size: 1
enum: MSIRDYIE
- name: HSIRDYIE
description: HSI ready interrupt enable
bit_offset: 10
bit_size: 1
enum: MSIRDYIE
- name: HSERDYIE
description: HSE ready interrupt enable
bit_offset: 11
bit_size: 1
enum: MSIRDYIE
- name: PLLRDYIE
description: PLL ready interrupt enable
bit_offset: 12
bit_size: 1
enum: MSIRDYIE
- name: MSIRDYIE
description: MSI ready interrupt enable
bit_offset: 13
bit_size: 1
enum: MSIRDYIE
- name: LSECSSIE
description: LSE clock security system interrupt enable
bit_offset: 14
bit_size: 1
enum: LSECSSIE
- name: LSIRDYC
description: LSI ready interrupt clear
bit_offset: 16
bit_size: 1
enum_write: MSIRDYCW
- name: LSERDYC
description: LSE ready interrupt clear
bit_offset: 17
bit_size: 1
enum_write: MSIRDYCW
- name: HSIRDYC
description: HSI ready interrupt clear
bit_offset: 18
bit_size: 1
enum_write: MSIRDYCW
- name: HSERDYC
description: HSE ready interrupt clear
bit_offset: 19
bit_size: 1
enum_write: MSIRDYCW
- name: PLLRDYC
description: PLL ready interrupt clear
bit_offset: 20
bit_size: 1
enum_write: MSIRDYCW
- name: MSIRDYC
description: MSI ready interrupt clear
bit_offset: 21
bit_size: 1
enum_write: MSIRDYCW
- name: LSECSSC
description: LSE Clock security system interrupt clear
bit_offset: 22
bit_size: 1
enum_write: CSSCW
- name: CSSC
description: Clock security system interrupt clear
bit_offset: 23
bit_size: 1
enum_write: CSSCW
fieldset/CR:
description: Clock control register
fields:
@ -808,7 +698,6 @@ fieldset/CR:
description: Internal high-speed clock ready flag
bit_offset: 1
bit_size: 1
enum_read: HSERDYR
- name: MSION
description: MSI clock enable
bit_offset: 8
@ -817,7 +706,6 @@ fieldset/CR:
description: MSI clock ready flag
bit_offset: 9
bit_size: 1
enum_read: HSERDYR
- name: HSEON
description: HSE clock enable
bit_offset: 16
@ -826,12 +714,10 @@ fieldset/CR:
description: HSE clock ready flag
bit_offset: 17
bit_size: 1
enum_read: HSERDYR
- name: HSEBYP
description: HSE clock bypass
bit_offset: 18
bit_size: 1
enum: HSEBYP
- name: PLLON
description: PLL enable
bit_offset: 24
@ -840,16 +726,18 @@ fieldset/CR:
description: PLL clock ready flag
bit_offset: 25
bit_size: 1
enum_read: PLLRDYR
- name: CSSON
description: Clock security system enable
bit_offset: 28
bit_size: 1
- name: RTCPRE
description: TC/LCD prescaler
- name: RTCPRE0
description: RTCPRE0
bit_offset: 29
bit_size: 2
enum: RTCPRE
bit_size: 1
- name: RTCPRE1
description: TC/LCD prescaler
bit_offset: 30
bit_size: 1
fieldset/CSR:
description: Control/status register
fields:
@ -873,14 +761,6 @@ fieldset/CSR:
description: External low-speed oscillator bypass
bit_offset: 10
bit_size: 1
- name: LSECSSON
description: CSS on LSE enable
bit_offset: 11
bit_size: 1
- name: LSECSSD
description: CSS on LSE failure Detection
bit_offset: 12
bit_size: 1
- name: RTCSEL
description: RTC and LCD clock source selection
bit_offset: 16
@ -893,47 +773,34 @@ fieldset/CSR:
description: RTC software reset
bit_offset: 23
bit_size: 1
enum_write: RTCRSTW
- name: RMVF
description: Remove reset flag
bit_offset: 24
bit_size: 1
enum_write: RMVFW
- name: OBLRSTF
description: Options bytes loading reset flag
bit_offset: 25
bit_size: 1
enum_read: LPWRSTFR
- name: PINRSTF
description: PIN reset flag
bit_offset: 26
bit_size: 1
enum_read: LPWRSTFR
- name: PORRSTF
description: POR/PDR reset flag
bit_offset: 27
bit_size: 1
enum_read: LPWRSTFR
- name: SFTRSTF
description: Software reset flag
bit_offset: 28
bit_size: 1
enum_read: LPWRSTFR
- name: IWDGRSTF
description: Independent watchdog reset flag
bit_offset: 29
bit_size: 1
enum_read: LPWRSTFR
- name: WWDGRSTF
description: Window watchdog reset flag
bit_offset: 30
bit_size: 1
enum_read: LPWRSTFR
- name: LPWRSTF
description: Low-power reset flag
bit_offset: 31
bit_size: 1
enum_read: LPWRSTFR
fieldset/ICSCR:
description: Internal clock sources calibration register
fields:
@ -957,315 +824,3 @@ fieldset/ICSCR:
description: MSI clock trimming
bit_offset: 24
bit_size: 8
enum/COMPRSTW:
bit_size: 1
variants:
- name: Reset
description: Reset the module
value: 1
enum/CSSCW:
bit_size: 1
variants:
- name: Clear
description: Clear interrupt
value: 1
enum/CSSFR:
bit_size: 1
variants:
- name: NotInterupted
description: No clock security interrupt caused by HSE clock failure
value: 0
- name: Interupted
description: Clock security interrupt caused by HSE clock failure
value: 1
enum/FSMCRSTW:
bit_size: 1
variants:
- name: Reset
description: Reset the module
value: 1
enum/HPRE:
bit_size: 4
variants:
- name: Div1
description: system clock not divided
value: 0
- name: Div2
description: system clock divided by 2
value: 8
- name: Div4
description: system clock divided by 4
value: 9
- name: Div8
description: system clock divided by 8
value: 10
- name: Div16
description: system clock divided by 16
value: 11
- name: Div64
description: system clock divided by 64
value: 12
- name: Div128
description: system clock divided by 128
value: 13
- name: Div256
description: system clock divided by 256
value: 14
- name: Div512
description: system clock divided by 512
value: 15
enum/HSEBYP:
bit_size: 1
variants:
- name: NotBypassed
description: HSE oscillator not bypassed
value: 0
- name: Bypassed
description: HSE oscillator bypassed
value: 1
enum/HSERDYR:
bit_size: 1
variants:
- name: NotReady
description: Oscillator is not stable
value: 0
- name: Ready
description: Oscillator is stable
value: 1
enum/LPWRSTFR:
bit_size: 1
variants:
- name: NoReset
description: No reset has occured
value: 0
- name: Reset
description: A reset has occured
value: 1
enum/LSECSSFR:
bit_size: 1
variants:
- name: NoFailure
description: No failure detected on the external 32 KHz oscillator
value: 0
- name: Failure
description: A failure is detected on the external 32 kHz oscillator
value: 1
enum/LSECSSIE:
bit_size: 1
variants:
- name: Disabled
description: LSE CSS interrupt disabled
value: 0
- name: Enabled
description: LSE CSS interrupt enabled
value: 1
enum/MCOPRE:
bit_size: 3
variants:
- name: Div1
description: No division
value: 0
- name: Div2
description: Division by 2
value: 1
- name: Div4
description: Division by 4
value: 2
- name: Div8
description: Division by 8
value: 3
- name: Div16
description: Division by 16
value: 4
enum/MCOSEL:
bit_size: 3
variants:
- name: NoClock
description: No clock
value: 0
- name: SYSCLK
description: SYSCLK clock selected
value: 1
- name: HSI
description: HSI oscillator clock selected
value: 2
- name: MSI
description: MSI oscillator clock selected
value: 3
- name: HSE
description: HSE oscillator clock selected
value: 4
- name: PLL
description: PLL clock selected
value: 5
- name: LSI
description: LSI oscillator clock selected
value: 6
- name: LSE
description: LSE oscillator clock selected
value: 7
enum/MSIRDYCW:
bit_size: 1
variants:
- name: Clear
description: Clear interrupt
value: 1
enum/MSIRDYFR:
bit_size: 1
variants:
- name: NotStable
description: Clock is not stable
value: 0
- name: Stable
description: Clock is stable
value: 1
enum/MSIRDYIE:
bit_size: 1
variants:
- name: Disabled
description: Interrupt disabled
value: 0
- name: Enabled
description: Interrupt enabled
value: 1
enum/PLLDIV:
bit_size: 2
variants:
- name: Div2
description: PLLVCO / 2
value: 1
- name: Div3
description: PLLVCO / 3
value: 2
- name: Div4
description: PLLVCO / 4
value: 3
enum/PLLMUL:
bit_size: 4
variants:
- name: Mul3
description: PLL clock entry x 3
value: 0
- name: Mul4
description: PLL clock entry x 4
value: 1
- name: Mul6
description: PLL clock entry x 6
value: 2
- name: Mul8
description: PLL clock entry x 8
value: 3
- name: Mul12
description: PLL clock entry x 12
value: 4
- name: Mul16
description: PLL clock entry x 16
value: 5
- name: Mul24
description: PLL clock entry x 24
value: 6
- name: Mul32
description: PLL clock entry x 32
value: 7
- name: Mul48
description: PLL clock entry x 48
value: 8
enum/PLLRDYR:
bit_size: 1
variants:
- name: Unlocked
description: PLL unlocked
value: 0
- name: Locked
description: PLL locked
value: 1
enum/PLLSRC:
bit_size: 1
variants:
- name: HSI
description: HSI selected as PLL input clock
value: 0
- name: HSE
description: HSE selected as PLL input clock
value: 1
enum/PPRE:
bit_size: 3
variants:
- name: Div1
description: HCLK not divided
value: 0
- name: Div2
description: HCLK divided by 2
value: 4
- name: Div4
description: HCLK divided by 4
value: 5
- name: Div8
description: HCLK divided by 8
value: 6
- name: Div16
description: HCLK divided by 16
value: 7
enum/RMVFW:
bit_size: 1
variants:
- name: Clear
description: Clears the reset flag
value: 1
enum/RTCPRE:
bit_size: 2
variants:
- name: Div2
description: HSE divided by 2
value: 0
- name: Div4
description: HSE divided by 4
value: 1
- name: Div8
description: HSE divided by 8
value: 2
- name: Div16
description: HSE divided by 16
value: 3
enum/RTCRSTW:
bit_size: 1
variants:
- name: Reset
description: Resets the RTC peripheral
value: 1
enum/SW:
bit_size: 2
variants:
- name: HSI
description: MSI oscillator used as system clock
value: 0
- name: MSI
description: HSI oscillator used as system clock
value: 1
- name: HSE
description: HSE oscillator used as system clock
value: 2
- name: PLL
description: PLL used as system clock
value: 3
enum/SWSR:
bit_size: 2
variants:
- name: HSI
description: MSI oscillator used as system clock
value: 0
- name: MSI
description: HSI oscillator used as system clock
value: 1
- name: HSE
description: HSE oscillator used as system clock
value: 2
- name: PLL
description: PLL used as system clock
value: 3
enum/USARTRSTW:
bit_size: 1
variants:
- name: Reset
description: Reset the module
value: 1

1
parse.py
View File

@ -389,6 +389,7 @@ perimap = [
('STM32H7(42|43|53|50).*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'),
('.*:STM32H7_pwr_v1_0', 'pwr_h7smps/PWR'),
('.*:STM32F4_pwr_v1_0', 'pwr_f4/PWR'),
('.*:STM32L1_pwr_v1_0', 'pwr_l1/PWR'),
('.*:STM32WL_pwr_v1_0', 'pwr_wl5/PWR'),
('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'),
('.*:STM32F0_flash_v1_0', 'flash_f0/FLASH'),