Dario Nieuwenhuis
8ee7107b6d
Merge pull request #470 from phycrax/stm32-g03g04-memory-x
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Correct flash size for g03 and g04
2024-04-17 15:10:59 +00:00
Süha
6f0aff1df4
Correct flash size for g03 and g04
2024-04-17 22:18:34 +08:00
Dario Nieuwenhuis
9db1729024
Merge pull request #468 from Systemscape/main
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Add DSIHOST support
2024-04-17 10:08:21 +00:00
Dario Nieuwenhuis
0e2a82de8d
Merge pull request #456 from eZioPan/lptim
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rework on LPTIM
2024-04-17 10:03:22 +00:00
Dario Nieuwenhuis
01ac9bfd03
Merge pull request #467 from diondokter/U0
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More U0 support
2024-04-16 15:04:21 +00:00
Dion Dokter
e44b6798dc
Clean up ADC
2024-04-16 16:42:50 +02:00
Dion Dokter
50f329f131
Add opamp and rtc
2024-04-16 14:44:38 +02:00
JuliDi
f1e684e345
fix ltdc_v1.yaml bfcr wrong definition
2024-04-15 09:20:50 +02:00
JuliDi
804326f93f
add dsihost for u5 chip family
2024-04-15 09:20:50 +02:00
JuliDi
95ff92f362
remove DSISEL from other register ymls where it is not present
2024-04-15 09:20:50 +02:00
JuliDi
dd12c3787a
change DSIPHY to DSI_PHY for rcc_l4plus.yaml to match other families
2024-04-15 09:20:50 +02:00
JuliDi
c8a3e8875d
add DSI as fallback for DSIHOST in stm32-data-gen rcc.rs
2024-04-15 09:20:50 +02:00
Joël Schulz-Ansres
8ec40e422c
Add DSIHOST support
2024-04-15 09:19:55 +02:00
Dion Dokter
a4d4695635
Add aes, crc, tsc and comp
2024-04-14 02:01:06 +02:00
Dion Dokter
7b08f67dfb
Add ADC which is basically the G0 adc but not really
2024-04-14 00:04:06 +02:00
Dion Dokter
a6ff95d7b6
Add the usbram yaml
2024-04-13 23:21:40 +02:00
Dion Dokter
8490e2c8c9
Add rng, dac, crs, and usb
2024-04-13 18:39:00 +02:00
eZio Pan
471c377368
clippy fix
2024-04-13 23:36:32 +08:00
eZio Pan
510f269a69
add lptim_v2b for u0
2024-04-13 23:36:32 +08:00
eZio Pan
0d43029663
lptim_v1 for l0
2024-04-13 23:27:11 +08:00
eZio Pan
d2fcff2e5e
lptim_v1a for l4(no plus), f4, f7
2024-04-13 23:27:11 +08:00
eZio Pan
096616ceda
lptim_v1b for l4+, g0, wb
2024-04-13 23:27:11 +08:00
eZio Pan
e90a3f9246
lptim_v1b_g4 for g4
2024-04-13 23:27:11 +08:00
eZio Pan
14301aa848
lptim_v1b_h7 for h7
2024-04-13 23:27:11 +08:00
eZio Pan
c3fb098274
lptim_v1c for l5 wl
2024-04-13 23:27:11 +08:00
eZio Pan
af7aefa4fe
keep lptim_v2 and remove others
2024-04-13 23:26:04 +08:00
Dario Nieuwenhuis
d674277b78
update sources (adds missing irq)
2024-04-13 03:51:22 +02:00
Dario Nieuwenhuis
0c4baf4783
Remove a few zero-sized memory regions that are breaking memory.x generation.
2024-04-13 03:27:35 +02:00
Dario Nieuwenhuis
9a0154110c
Merge pull request #466 from embassy-rs/u0
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Add stm32u0.
2024-04-13 01:18:48 +00:00
Dario Nieuwenhuis
d4a97f60b1
Add stm32u0.
2024-04-13 03:16:25 +02:00
Dario Nieuwenhuis
7197df07de
Merge pull request #464 from wagcampbell/wgc/stm32u5-memory-fix
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Corrects STM32U5 memory sizes
2024-04-12 21:26:40 +00:00
Dario Nieuwenhuis
b1034db59a
Merge pull request #463 from MaxiluxSystems/feature/product-states
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flash_h50: add PRODUCT_STATE enum; improve a couple other fields
2024-04-12 19:38:24 +00:00
Torin Cooper-Bennun
62b1ab50db
flash_h50: rename BKSEL variants
2024-04-12 17:04:33 +01:00
Torin Cooper-Bennun
4df4f6840c
flash_h50: plain bool for SWAP_BANK fields
2024-04-12 17:03:44 +01:00
Warren Campbell
af9e902172
Corrects STM32U5 memory sizes
2024-04-11 18:04:35 -04:00
Torin Cooper-Bennun
a0c7c136fa
flash_h50: add PRODUCT_STATE enum
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the values are taken from the official HAL headers; I have only included
enum variants which are definitively mentioned in RM0492, excluding
other variants mentioned in the HAL headers
2024-04-11 10:25:07 +01:00
Torin Cooper-Bennun
f60ad0d665
flash_h50: make _CUR registers read-only
2024-04-11 10:24:55 +01:00
Dario Nieuwenhuis
1f79295b80
Merge pull request #460 from embassy-rs/memfix
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Manually maintain memory maps instead of parsing them from cubeprogdb.
2024-04-09 02:15:22 +00:00
Dario Nieuwenhuis
8e26f36a8e
Manually maintain memory maps instead of parsing them from cubeprogdb.
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First step towards fixing #301
The cubeprogdb has turned out to be a quite bad data source. It's not granular
enough (it has one entry per chip die, not per chip) so the previous code joined
the data with the C headers and cubedb to fill in the gaps, essentialy "guessing"
stuff. This has been quite error prone (see #301 ) and hard to make fixes to.
Instead, we're going to manually maintain memory maps in a .rs file. This way, if
something is wrong we can simply go and fix it.
This commit just migrates the existing data, even if it's wrong. (it does fix
a few very minor mistakes). Next steps is actually fixing the memory maps.
2024-04-09 03:38:33 +02:00
Dario Nieuwenhuis
9d3d5c9690
Sort memory regions by addr.
2024-04-09 02:43:44 +02:00
Dario Nieuwenhuis
4e3ed9abee
Remove OTP from memory map.
2024-04-09 02:19:17 +02:00
Dario Nieuwenhuis
2480982cc5
Merge pull request #450 from taunusflieger/feature/HSEM
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Add support for HSEM
2024-04-08 12:10:36 +00:00
Dario Nieuwenhuis
604890b9ba
hsem: rename more MASTERID->COREID
2024-04-08 14:07:46 +02:00
Michael Zill
b782384611
Arrayfied IER, ICR, ISR and MISR
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IRQ registers have for all 4 variants the same name.
V1 - array size = 2 (2 cores)
V2 - array size = 1 (1 core)
V3 - array size = 2 (2 cores)
V4 - array size = 1 (1 core)
HSEM added to GHOST_PERIS
2024-04-08 13:38:36 +02:00
Michael Zill
840e5ec5db
Fixed length COREID in v1, v2 renamed MASTERID to COREID
2024-04-08 13:36:40 +02:00
Michael Zill
e029a55f7a
Arrayfied v2, v3, v4 - removed enums, aligned yaml structure
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The following list shows the different hsem yaml versions and the coresponding chips.
wba is on purpose not included at is complex and very different from the others which will
also make the HSEM implementation in the HAL more complex. I leave this out for another PR.
h747
wb55
h735
h7b3
h753v
h753
h743
h743v
wl5x_cm0p
wl5x_cm4
wle5
2024-04-08 13:36:40 +02:00
Michael Zill
bde330f46e
Fixed C1ICR, C2ICR read/write
2024-04-08 13:36:40 +02:00
Michael Zill
c0c35d80f9
Remove temp patch doc
2024-04-08 13:36:40 +02:00
Michael Zill
6ba934d366
Remote debug code
2024-04-08 13:36:40 +02:00
Michael Zill
d1f1f4bfeb
Arrayfied v1 and v8 - preliminary fix for missing HSEM in Cube XML
2024-04-08 13:36:40 +02:00