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310 Commits

Author SHA1 Message Date
Dario Nieuwenhuis
afee4331ad Add stm32h7rs family. 2024-05-01 02:16:15 +02:00
Dario Nieuwenhuis
37a0941112 Add LPDMA regs, cleanup GPDMA. 2024-04-29 20:47:57 +02:00
Dario Nieuwenhuis
e001b7dfcd Add U5 LPDMA. 2024-04-29 18:33:48 +02:00
Dario Nieuwenhuis
a51bae6042 Simplify DMA matching a bit. 2024-04-29 18:30:50 +02:00
Dario Nieuwenhuis
706b07e020 Normalize DAC => DAC1 2024-04-29 17:59:16 +02:00
Dario Nieuwenhuis
d296bed417 Add WBA5[045] 2024-04-29 00:43:07 +02:00
Dario Nieuwenhuis
f2f067ce14 Add U5[FG]. 2024-04-29 00:39:45 +02:00
Dario Nieuwenhuis
722f70a701 Add H5[23]. 2024-04-29 00:36:24 +02:00
Dario Nieuwenhuis
37ec0ab67d Use normalize for SBS->SYSCFG rename. 2024-04-28 23:44:57 +02:00
Dario Nieuwenhuis
24a684e9e6 adc: fix chips with multiple ADC_COMMON, normalize ADC to ADC1. 2024-04-28 23:28:37 +02:00
Dario Nieuwenhuis
849ed606a1 Add normalize_peri_name. 2024-04-28 23:19:15 +02:00
Dario Nieuwenhuis
ce5c57db68 Remove parse_signal_name duplicate. 2024-04-28 23:01:21 +02:00
Süha
6f0aff1df4
Correct flash size for g03 and g04 2024-04-17 22:18:34 +08:00
Dario Nieuwenhuis
9db1729024
Merge pull request #468 from Systemscape/main 
Add DSIHOST support
 2024-04-17 10:08:21 +00:00
Dario Nieuwenhuis
0e2a82de8d
Merge pull request #456 from eZioPan/lptim 
rework on LPTIM
 2024-04-17 10:03:22 +00:00
Dion Dokter
e44b6798dc Clean up ADC 2024-04-16 16:42:50 +02:00
Dion Dokter
50f329f131 Add opamp and rtc 2024-04-16 14:44:38 +02:00
JuliDi
804326f93f
add dsihost for u5 chip family 2024-04-15 09:20:50 +02:00
JuliDi
95ff92f362
remove DSISEL from other register ymls where it is not present 2024-04-15 09:20:50 +02:00
JuliDi
c8a3e8875d
add DSI as fallback for DSIHOST in stm32-data-gen rcc.rs 2024-04-15 09:20:50 +02:00
Joël Schulz-Ansres
8ec40e422c
Add DSIHOST support 2024-04-15 09:19:55 +02:00
Dion Dokter
a4d4695635 Add aes, crc, tsc and comp 2024-04-14 02:01:06 +02:00
Dion Dokter
7b08f67dfb Add ADC which is basically the G0 adc but not really 2024-04-14 00:04:06 +02:00
Dion Dokter
8490e2c8c9 Add rng, dac, crs, and usb 2024-04-13 18:39:00 +02:00
eZio Pan
471c377368 clippy fix 2024-04-13 23:36:32 +08:00
eZio Pan
510f269a69 add lptim_v2b for u0 2024-04-13 23:36:32 +08:00
eZio Pan
0d43029663 lptim_v1 for l0 2024-04-13 23:27:11 +08:00
eZio Pan
d2fcff2e5e lptim_v1a for l4(no plus), f4, f7 2024-04-13 23:27:11 +08:00
eZio Pan
096616ceda lptim_v1b for l4+, g0, wb 2024-04-13 23:27:11 +08:00
eZio Pan
e90a3f9246 lptim_v1b_g4 for g4 2024-04-13 23:27:11 +08:00
eZio Pan
14301aa848 lptim_v1b_h7 for h7 2024-04-13 23:27:11 +08:00
eZio Pan
c3fb098274 lptim_v1c for l5 wl 2024-04-13 23:27:11 +08:00
eZio Pan
af7aefa4fe keep lptim_v2 and remove others 2024-04-13 23:26:04 +08:00
Dario Nieuwenhuis
0c4baf4783 Remove a few zero-sized memory regions that are breaking memory.x generation. 2024-04-13 03:27:35 +02:00
Dario Nieuwenhuis
d4a97f60b1 Add stm32u0. 2024-04-13 03:16:25 +02:00
Warren Campbell
af9e902172 Corrects STM32U5 memory sizes 2024-04-11 18:04:35 -04:00
Dario Nieuwenhuis
8e26f36a8e Manually maintain memory maps instead of parsing them from cubeprogdb. 
First step towards fixing #301

The cubeprogdb has turned out to be a quite bad data source. It's not granular
enough (it has one entry per chip die, not per chip) so the previous code joined
the data with the C headers and cubedb to fill in the gaps, essentialy "guessing"
stuff. This has been quite error prone (see #301) and hard to make fixes to.

Instead, we're going to manually maintain memory maps in a .rs file. This way, if
something is wrong we can simply go and fix it.

This commit just migrates the existing data, even if it's wrong. (it does fix
a few very minor mistakes). Next steps is actually fixing the memory maps.
 2024-04-09 03:38:33 +02:00
Dario Nieuwenhuis
9d3d5c9690 Sort memory regions by addr. 2024-04-09 02:43:44 +02:00
Dario Nieuwenhuis
4e3ed9abee Remove OTP from memory map. 2024-04-09 02:19:17 +02:00
Michael Zill
b782384611 Arrayfied IER, ICR, ISR and MISR 
IRQ registers have for all 4 variants the same name.
V1 - array size = 2 (2 cores)
V2 - array size = 1 (1 core)
V3 - array size = 2 (2 cores)
V4 - array size = 1 (1 core)

HSEM added to GHOST_PERIS
 2024-04-08 13:38:36 +02:00
Michael Zill
e029a55f7a Arrayfied v2, v3, v4 - removed enums, aligned yaml structure 
The following list shows the different hsem yaml versions and the coresponding chips.

    wba is on purpose not included at is complex and very different from the others which will
    also make the HSEM implementation in the HAL more complex. I leave this out for another PR.

    h747
    wb55

    h735
    h7b3
    h753v
    h753
    h743
    h743v

    wl5x_cm0p
    wl5x_cm4

    wle5
 2024-04-08 13:36:40 +02:00
Michael Zill
6ba934d366 Remote debug code 2024-04-08 13:36:40 +02:00
Michael Zill
d1f1f4bfeb Arrayfied v1 and v8 - preliminary fix for missing HSEM in Cube XML 2024-04-08 13:36:40 +02:00
Michael Zill
44967f3776 Initial add 2024-04-08 13:36:40 +02:00
eZio Pan
60398cad51 move "UID" to "GHOST_PERIS" 2024-04-06 22:07:19 +08:00
David Lawrence
d258cf858d Split STM32G4 flash peripheral by device category 2024-04-05 12:10:59 -04:00
Dario Nieuwenhuis
73ab4d3f67
Merge pull request #451 from eZioPan/lptim-v2 
lptim v2
 2024-04-05 11:28:05 +00:00
qff233
cf5ab0f41b Fix ADC resolution enum for stm32g4 2024-04-05 01:13:23 +08:00
eZio Pan
d9625637f2 add lptim_v2a to chips.rs 2024-04-05 00:06:01 +08:00
eZio Pan
029320446b add lptim to u5 wba 2024-04-04 23:29:48 +08:00