Michael Zill b782384611 Arrayfied IER, ICR, ISR and MISR ...

IRQ registers have for all 4 variants the same name.
V1 - array size = 2 (2 cores)
V2 - array size = 1 (1 core)
V3 - array size = 2 (2 cores)
V4 - array size = 1 (1 core)

HSEM added to GHOST_PERIS

2024-04-08 13:38:36 +02:00

..

chips.rs

Arrayfied IER, ICR, ISR and MISR

2024-04-08 13:38:36 +02:00

dma.rs

Add STM32WBA support.

2023-09-16 02:34:03 +02:00

docs.rs

New repo structure: includes stm32-metapac, doesn't commit generated files.

2023-03-20 01:56:23 +01:00

gpio_af.rs

rustfmt.

2024-01-03 02:00:48 +01:00

header.rs

Fix register address for OCTOSPI2 peripheral

2024-02-07 16:58:16 +01:00

interrupts.rs

add irq name exception for "TIM6_DAC"

2024-01-03 18:17:17 +08:00

main.rs

Refactor RCC code to find more muxes.

2024-02-10 02:40:36 +01:00

memory.rs

refactor with clippy

2023-12-24 19:07:32 +08:00

rcc.rs

rcc: add override so SAI23SEL is used

2024-03-09 18:53:48 +00:00

registers.rs

apply chiptool validate on yaml parse

2024-01-08 16:30:57 +08:00