Torin Cooper-Bennun
27c71ac451
fdcan: generate register blocks for message RAM
...
this is a special case, as most data sources don't mention this as a
separate peripheral at all, and those that do don't handle the offsets
in the case of multiple FDCANS
H7 chips have a single 10KB block shared between all FDCANs
2023-11-21 10:45:51 +00:00
Torin Cooper-Bennun
f65fd694e1
fdcan: fix register block definitions; separate version for H7
...
the Cube XMLs refer to "fdcan_v1_0" and "fdcan_v1_1" but these seem to
have no bearing on the actual registers used. Thus chips.rs should make
no distinction between v1_0 and v1_1.
the previous YAML seems to have been generated from a G4 SVD, but this
series' SVDs consistently have several errata.
I have therefore replaced can_fdcan.yaml with can_fdcan_v1.yaml, built
from an H5 SVD which appears to match the RMs of G0, G4, H5 and L5
chips.
the H7 series has a totally different FDCAN, so I've added a separate
YAML for it.
2023-11-21 10:45:51 +00:00
Dario Nieuwenhuis
fbb8f77326
rcc: consistency fixes on f2
2023-11-13 01:47:21 +01:00
Dario Nieuwenhuis
c551c07bf1
rcc: consistency fixes.
2023-11-13 01:00:53 +01:00
shakencodes
9ba39f0f2d
Corrects name of enum/ADCSEL::PLLSAI1_R on smt32l5
2023-11-01 13:04:57 -07:00
shakencodes
445f314531
Add enum/ADCSET to rcc_l5.yaml
2023-11-01 12:39:09 -07:00
Dario Nieuwenhuis
bcc9b6bf9f
rcc/wb: add misrange enum
2023-10-23 01:02:53 +02:00
Dario Nieuwenhuis
4ddcb77c9d
rcc: rename NONE -> DISABLED
2023-10-23 00:30:16 +02:00
Dario Nieuwenhuis
b59a5c1812
rcc: add missing enums to wb, wl.
2023-10-23 00:30:16 +02:00
Dario Nieuwenhuis
ee64389697
Rename HSI16 -> HSI
2023-10-22 22:32:08 +02:00
xoviat
e20aed5f9a
rcc/l4: fix dup enable
2023-10-20 18:43:56 -05:00
xoviat
e4b19a6fd9
rcc: fix l4 sw enum
2023-10-19 21:06:26 -05:00
Olle Sandberg
9f019bd9ba
wwdg: register definitions for window watchdog v2
2023-10-19 14:49:41 +02:00
xoviat
8bd7ff51b0
rcc: expand checker to all chips
2023-10-18 21:01:57 -05:00
Dario Nieuwenhuis
5b04234fbe
rcc: cleanup f4, f7 plls.
2023-10-18 05:08:14 +02:00
xoviat
3d9c8b70e3
rcc: check l4plus and l5
2023-10-17 17:21:06 -05:00
xoviat
c61495fd4e
rcc: more cleanup
2023-10-17 16:57:33 -05:00
xoviat
fb84c0ac55
rcc: fixup clock names and expand checking
2023-10-16 17:53:26 -05:00
JackN
120168456f
TSC: Add transform and new peripheral
2023-10-16 09:54:09 -04:00
Dario Nieuwenhuis
5ecc410f93
rcc/l5: cleanup
2023-10-16 03:56:19 +02:00
Dario Nieuwenhuis
73e3f8a965
rcc: separate L4 and L4+
2023-10-16 03:11:00 +02:00
Dario Nieuwenhuis
f437c33b41
rcc/l5: unify clk48sel vs clk48msel
2023-10-16 01:37:21 +02:00
xoviat
b9a89a1851
rcc: cleanup variants and rename ahb -> clk
2023-10-15 18:01:50 -05:00
xoviat
8b8686a852
rcc: more mux and enum cleanup
2023-10-15 10:37:36 -05:00
xoviat
5d51e3b706
rcc: add more mux data
2023-10-14 17:20:25 -05:00
xoviat
68d77f487b
rcc: add more mux data
2023-10-14 11:41:21 -05:00
xoviat
b14427f2d1
Merge branch 'main' of https://github.com/embassy-rs/stm32-data into rcc
2023-10-13 22:22:05 -05:00
xoviat
8a09bbb62c
rcc: more cleanup
2023-10-13 22:20:18 -05:00
xoviat
e90a83a4f0
Merge pull request #281 from noppej/gfxmmu
...
Add GFXMMU peripheral
2023-10-14 02:26:15 +00:00
xoviat
aa5e909e11
rcc: more enum cleanup
2023-10-13 20:54:24 -05:00
JackN
53c636386b
GFXMMU: New peripheral yamls
2023-10-13 17:12:57 -04:00
xoviat
c4cd46927d
rcc: rename h5 clock enum variants and add check
2023-10-12 20:48:35 -05:00
JackN
019e802e27
OCTOSPI: Fix "MAXTRAN was in wrong yaml".
2023-10-12 18:52:50 -04:00
JackN
af1a5f5877
OCTOSPI: Merge peri yamls
2023-10-12 17:44:41 -04:00
JackN
4e2bf3eb20
PR Review corrections
2023-10-12 16:45:54 -04:00
JackN
e99c97f0f6
OCTOSPI: Merge peripheral yamls and consolidate enums
2023-10-12 15:43:04 -04:00
JackN
b07f5a1ba2
Reformat yaml's with chiptool fmt
2023-10-12 10:49:41 -04:00
JackN
c34f46566e
Add STM32u5xx to header_map.yaml
2023-10-12 10:24:00 -04:00
JackN
e933ee6cc4
New peripherals: octospim_v1+v2, and octospi_v1-v4
2023-10-12 10:23:59 -04:00
Dario Nieuwenhuis
6bfa5a0dce
rtc/bd fixes.
2023-10-11 03:41:10 +02:00
Dario Nieuwenhuis
9f45b0c48c
Rename HSI to HSI16 in L1.
2023-10-11 01:21:46 +02:00
Dario Nieuwenhuis
f40f5a40c1
Not all L0s have HSI48/CRS.
2023-10-11 01:21:26 +02:00
Dario Nieuwenhuis
71f81b44e3
Rename HSE32 -> HSE.
2023-10-11 00:29:01 +02:00
Dario Nieuwenhuis
ff45aa382e
rcc: add more missing enums.
2023-10-11 00:07:28 +02:00
Dario Nieuwenhuis
e89b8cfc30
rcc: add PLL enums.
2023-10-09 02:44:42 +02:00
Dario Nieuwenhuis
6c73ffbd0b
rcc: make naming consistent between "mco" and "mcosel".
2023-10-07 00:46:19 +02:00
Dario Nieuwenhuis
8d112b7a93
rcc: add MCO enums for WB
2023-10-07 00:20:42 +02:00
Dario Nieuwenhuis
e701705d79
rcc: add MCOPRE enum for h5, h7.
2023-10-07 00:10:08 +02:00
Dario Nieuwenhuis
11256dc370
chiptool fmt.
2023-10-07 00:09:14 +02:00
Matt Ickstadt
2ceed56e94
RCC: add LSEDRV enums for WB and WL series
...
These are in the RMs but previously missing.
2023-10-05 11:18:49 -05:00
