rcc: add more missing enums.
This commit is contained in:
Dario Nieuwenhuis
parent
e89b8cfc30
commit
ff45aa382e
@ -857,9 +857,6 @@ enum/ADCPRE:
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enum/ADCPRES:
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bit_size: 5
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variants:
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- name: NoClock
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description: No clock
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value: 0
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- name: Div1
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description: PLL clock not divided
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value: 16
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@ -833,9 +833,6 @@ enum/ADCPRE:
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enum/ADCPRES:
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bit_size: 5
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variants:
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- name: NoClock
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description: No clock
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value: 0
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- name: Div1
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description: PLL clock not divided
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value: 16
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@ -3142,16 +3142,36 @@ enum/PLLM:
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bit_size: 4
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variants:
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- name: Div1
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description: division by 1 (bypass)
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value: 0
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- name: Div2
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description: division by 2
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value: 1
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- name: Div3
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description: division by 3
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value: 2
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- name: Div4
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value: 3
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- name: Div5
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value: 4
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- name: Div6
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value: 5
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- name: Div7
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value: 6
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- name: Div8
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value: 7
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- name: Div9
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value: 8
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- name: Div10
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value: 9
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- name: Div11
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value: 10
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- name: Div12
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value: 11
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- name: Div13
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value: 12
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- name: Div14
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value: 13
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- name: Div15
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value: 14
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- name: Div16
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description: division by 16
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value: 15
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enum/PLLMBOOST:
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bit_size: 4
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@ -1153,10 +1153,12 @@ fieldset/CFGR:
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description: System clock switch
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bit_offset: 0
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bit_size: 2
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enum: SW
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- name: SWS
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description: System clock switch status
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bit_offset: 2
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bit_size: 2
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enum: SW
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- name: HPRE
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description: AHB prescaler
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bit_offset: 4
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@ -1394,6 +1396,7 @@ fieldset/CR:
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description: HSE sysclk and PLL M divider prescaler
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bit_offset: 20
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bit_size: 1
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enum: HSEPRE
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- name: PLLON
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description: Main PLL enable
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bit_offset: 24
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@ -1503,10 +1506,12 @@ fieldset/EXTCFGR:
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description: Shared AHB prescaler
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bit_offset: 0
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bit_size: 4
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enum: HPRE
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- name: C2HPRE
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description: CPU2 AHB prescaler
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bit_offset: 4
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bit_size: 4
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enum: HPRE
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- name: SHDHPREF
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description: Shared AHB prescaler flag
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bit_offset: 16
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@ -1564,14 +1569,17 @@ fieldset/PLLCFGR:
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description: Main PLL, PLLSAI1 and PLLSAI2 entry clock source
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bit_offset: 0
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bit_size: 2
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enum: PLLSRC
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- name: PLLM
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description: Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
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bit_offset: 4
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bit_size: 3
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enum: PLLM
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- name: PLLN
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description: Main PLLSYS multiplication factor N
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bit_offset: 8
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bit_size: 7
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enum: PLLN
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- name: PLLPEN
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description: Main PLLSYSP output enable
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bit_offset: 16
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@ -1580,6 +1588,7 @@ fieldset/PLLCFGR:
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description: Main PLL division factor P for PPLSYSSAICLK
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bit_offset: 17
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bit_size: 5
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enum: PLLP
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- name: PLLQEN
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description: Main PLLSYSQ output enable
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bit_offset: 24
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@ -1588,6 +1597,7 @@ fieldset/PLLCFGR:
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description: Main PLLSYS division factor Q for PLLSYSUSBCLK
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bit_offset: 25
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bit_size: 3
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enum: PLLQ
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- name: PLLREN
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description: Main PLLSYSR PLLCLK output enable
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bit_offset: 28
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@ -1596,6 +1606,7 @@ fieldset/PLLCFGR:
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description: Main PLLSYS division factor R for SYSCLK (system clock)
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bit_offset: 29
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bit_size: 3
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enum: PLLR
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fieldset/PLLSAI1CFGR:
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description: PLLSAI1 configuration register
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fields:
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@ -1603,6 +1614,7 @@ fieldset/PLLSAI1CFGR:
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description: SAIPLL multiplication factor for VCO
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bit_offset: 8
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bit_size: 7
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enum: PLLN
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- name: PLLPEN
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description: SAIPLL PLLSAI1CLK output enable
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bit_offset: 16
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@ -1611,6 +1623,7 @@ fieldset/PLLSAI1CFGR:
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description: SAI1PLL division factor P for PLLSAICLK (SAI1clock)
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bit_offset: 17
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bit_size: 5
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enum: PLLP
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- name: PLLQEN
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description: SAIPLL PLLSAIUSBCLK output enable
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bit_offset: 24
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@ -1619,6 +1632,7 @@ fieldset/PLLSAI1CFGR:
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description: SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)
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bit_offset: 25
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bit_size: 3
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enum: PLLQ
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- name: PLLREN
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description: PLLSAI PLLADC1CLK output enable
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bit_offset: 28
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@ -1627,6 +1641,7 @@ fieldset/PLLSAI1CFGR:
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description: PLLSAI division factor R for PLLADC1CLK (ADC clock)
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bit_offset: 29
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bit_size: 3
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enum: PLLR
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fieldset/SMPSCR:
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description: Step Down converter control register
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fields:
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@ -1687,6 +1702,13 @@ enum/HPRE:
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- name: Div512
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description: hclk = SYSCLK divided by 256
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value: 15
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enum/HSEPRE:
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bit_size: 1
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variants:
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- name: Div1
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value: 0
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- name: Div2
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value: 1
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enum/LSEDRV:
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bit_size: 2
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variants:
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@ -1756,6 +1778,380 @@ enum/MCOSEL:
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- name: HSE_UNSTABLE
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description: HSE clock selected (before stabilization, after HSEON = 1)
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value: 12
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enum/PLLM:
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bit_size: 3
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variants:
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- name: Div1
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value: 0
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- name: Div2
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value: 1
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- name: Div3
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value: 2
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- name: Div4
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value: 3
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- name: Div5
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value: 4
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- name: Div6
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value: 5
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- name: Div7
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value: 6
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- name: Div8
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value: 7
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enum/PLLN:
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bit_size: 7
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variants:
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- name: Mul6
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value: 6
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- name: Mul7
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value: 7
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- name: Mul8
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value: 8
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- name: Mul9
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value: 9
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- name: Mul10
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value: 10
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- name: Mul11
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value: 11
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- name: Mul12
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value: 12
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- name: Mul13
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value: 13
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- name: Mul14
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value: 14
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- name: Mul15
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value: 15
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- name: Mul16
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value: 16
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- name: Mul17
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value: 17
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- name: Mul18
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value: 18
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- name: Mul19
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value: 19
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- name: Mul20
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value: 20
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- name: Mul21
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value: 21
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- name: Mul22
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value: 22
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- name: Mul23
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value: 23
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- name: Mul24
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value: 24
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- name: Mul25
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value: 25
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- name: Mul26
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value: 26
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- name: Mul27
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value: 27
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- name: Mul28
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value: 28
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- name: Mul29
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value: 29
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- name: Mul30
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value: 30
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- name: Mul31
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value: 31
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- name: Mul32
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value: 32
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- name: Mul33
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value: 33
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- name: Mul34
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value: 34
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- name: Mul35
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value: 35
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- name: Mul36
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value: 36
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- name: Mul37
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value: 37
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- name: Mul38
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value: 38
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- name: Mul39
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value: 39
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- name: Mul40
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value: 40
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- name: Mul41
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value: 41
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- name: Mul42
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value: 42
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- name: Mul43
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value: 43
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- name: Mul44
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value: 44
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- name: Mul45
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value: 45
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- name: Mul46
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value: 46
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- name: Mul47
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value: 47
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- name: Mul48
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value: 48
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- name: Mul49
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value: 49
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- name: Mul50
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value: 50
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- name: Mul51
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value: 51
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- name: Mul52
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value: 52
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- name: Mul53
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value: 53
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- name: Mul54
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value: 54
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- name: Mul55
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value: 55
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- name: Mul56
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value: 56
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- name: Mul57
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value: 57
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- name: Mul58
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value: 58
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- name: Mul59
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value: 59
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- name: Mul60
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value: 60
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- name: Mul61
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value: 61
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- name: Mul62
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value: 62
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- name: Mul63
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value: 63
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- name: Mul64
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value: 64
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- name: Mul65
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value: 65
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- name: Mul66
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value: 66
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- name: Mul67
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value: 67
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- name: Mul68
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value: 68
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- name: Mul69
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value: 69
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- name: Mul70
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value: 70
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- name: Mul71
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value: 71
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- name: Mul72
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value: 72
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- name: Mul73
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value: 73
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- name: Mul74
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value: 74
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- name: Mul75
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value: 75
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- name: Mul76
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value: 76
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- name: Mul77
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value: 77
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- name: Mul78
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value: 78
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- name: Mul79
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value: 79
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- name: Mul80
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value: 80
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- name: Mul81
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value: 81
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- name: Mul82
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value: 82
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- name: Mul83
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value: 83
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- name: Mul84
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value: 84
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- name: Mul85
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value: 85
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- name: Mul86
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value: 86
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- name: Mul87
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value: 87
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- name: Mul88
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value: 88
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- name: Mul89
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value: 89
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- name: Mul90
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value: 90
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- name: Mul91
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value: 91
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- name: Mul92
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value: 92
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- name: Mul93
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value: 93
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- name: Mul94
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value: 94
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- name: Mul95
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value: 95
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- name: Mul96
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value: 96
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- name: Mul97
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value: 97
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- name: Mul98
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value: 98
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- name: Mul99
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value: 99
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- name: Mul100
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value: 100
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- name: Mul101
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value: 101
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- name: Mul102
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value: 102
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- name: Mul103
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value: 103
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- name: Mul104
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value: 104
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- name: Mul105
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value: 105
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- name: Mul106
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value: 106
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- name: Mul107
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value: 107
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- name: Mul108
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value: 108
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- name: Mul109
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value: 109
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- name: Mul110
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value: 110
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- name: Mul111
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value: 111
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- name: Mul112
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value: 112
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- name: Mul113
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value: 113
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- name: Mul114
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value: 114
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- name: Mul115
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value: 115
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- name: Mul116
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value: 116
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- name: Mul117
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value: 117
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- name: Mul118
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value: 118
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- name: Mul119
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value: 119
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- name: Mul120
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value: 120
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- name: Mul121
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value: 121
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- name: Mul122
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value: 122
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- name: Mul123
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value: 123
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- name: Mul124
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value: 124
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- name: Mul125
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value: 125
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- name: Mul126
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value: 126
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- name: Mul127
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value: 127
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enum/PLLP:
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bit_size: 5
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variants:
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- name: Div2
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value: 1
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- name: Div3
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value: 2
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- name: Div4
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value: 3
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- name: Div5
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value: 4
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- name: Div6
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value: 5
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- name: Div7
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value: 6
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- name: Div8
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value: 7
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- name: Div9
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value: 8
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- name: Div10
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value: 9
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- name: Div11
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value: 10
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- name: Div12
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value: 11
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- name: Div13
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value: 12
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- name: Div14
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value: 13
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- name: Div15
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value: 14
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- name: Div16
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value: 15
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- name: Div17
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value: 16
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- name: Div18
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value: 17
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- name: Div19
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value: 18
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- name: Div20
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value: 19
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- name: Div21
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value: 20
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- name: Div22
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value: 21
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- name: Div23
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value: 22
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- name: Div24
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value: 23
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- name: Div25
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value: 24
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- name: Div26
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value: 25
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- name: Div27
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value: 26
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- name: Div28
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value: 27
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- name: Div29
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value: 28
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- name: Div30
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value: 29
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- name: Div31
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value: 30
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enum/PLLQ:
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bit_size: 3
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variants:
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- name: Div2
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value: 1
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- name: Div3
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value: 2
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- name: Div4
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value: 3
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- name: Div5
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value: 4
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- name: Div6
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value: 5
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- name: Div7
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value: 6
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enum/PLLR:
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bit_size: 3
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variants:
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- name: Div2
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value: 1
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- name: Div3
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value: 2
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- name: Div4
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value: 3
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- name: Div5
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value: 4
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- name: Div6
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value: 5
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- name: Div7
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value: 6
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enum/PLLSRC:
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bit_size: 2
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variants:
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- name: NoClock
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description: No clock selected as PLL entry clock source
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value: 0
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- name: MSI
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description: MSI selected as PLL entry clock source
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value: 1
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- name: HSI16
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description: HSI16 selected as PLL entry clock source
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value: 2
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- name: HSE
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description: HSE selected as PLL entry clock source
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value: 3
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enum/PPRE:
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bit_size: 3
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variants:
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@ -1789,3 +2185,14 @@ enum/RTCSEL:
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- name: HSE
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description: HSE oscillator clock divided by 32 selected
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value: 3
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enum/SW:
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bit_size: 2
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variants:
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- name: MSI
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value: 0
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- name: HSI16
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value: 1
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- name: HSE
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value: 2
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- name: PLL
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||||
value: 3
|
||||
|
||||
@ -1072,10 +1072,12 @@ fieldset/CFGR:
|
||||
description: System clock switch
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
enum: SW
|
||||
- name: SWS
|
||||
description: System clock switch status
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
enum: SW
|
||||
- name: HPRE
|
||||
description: HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)
|
||||
bit_offset: 4
|
||||
@ -1241,6 +1243,7 @@ fieldset/CR:
|
||||
description: MSI clock ranges
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
enum: MSIRANGE
|
||||
- name: HSION
|
||||
description: HSI16 clock enable
|
||||
bit_offset: 8
|
||||
@ -1359,10 +1362,12 @@ fieldset/EXTCFGR:
|
||||
description: HCLK3 shared prescaler (AHB3, Flash, and SRAM2)
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
enum: HPRE
|
||||
- name: C2HPRE
|
||||
description: '[dual core device only] HCLK2 prescaler (CPU2)'
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
enum: HPRE
|
||||
- name: SHDHPREF
|
||||
description: HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)
|
||||
bit_offset: 16
|
||||
@ -1397,14 +1402,17 @@ fieldset/PLLCFGR:
|
||||
description: Main PLL entry clock source
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
enum: PLLSRC
|
||||
- name: PLLM
|
||||
description: Division factor for the main PLL input clock
|
||||
bit_offset: 4
|
||||
bit_size: 3
|
||||
enum: PLLM
|
||||
- name: PLLN
|
||||
description: Main PLL multiplication factor for VCO
|
||||
bit_offset: 8
|
||||
bit_size: 7
|
||||
enum: PLLN
|
||||
- name: PLLPEN
|
||||
description: Main PLL PLLPCLK output enable
|
||||
bit_offset: 16
|
||||
@ -1413,6 +1421,7 @@ fieldset/PLLCFGR:
|
||||
description: Main PLL division factor for PLLPCLK.
|
||||
bit_offset: 17
|
||||
bit_size: 5
|
||||
enum: PLLP
|
||||
- name: PLLQEN
|
||||
description: Main PLL PLLQCLK output enable
|
||||
bit_offset: 24
|
||||
@ -1421,6 +1430,7 @@ fieldset/PLLCFGR:
|
||||
description: Main PLL division factor for PLLQCLK
|
||||
bit_offset: 25
|
||||
bit_size: 3
|
||||
enum: PLLQ
|
||||
- name: PLLREN
|
||||
description: Main PLL PLLRCLK output enable
|
||||
bit_offset: 28
|
||||
@ -1429,6 +1439,7 @@ fieldset/PLLCFGR:
|
||||
description: Main PLL division factor for PLLRCLK
|
||||
bit_offset: 29
|
||||
bit_size: 3
|
||||
enum: PLLR
|
||||
enum/ADCSEL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
@ -1552,6 +1563,419 @@ enum/MCOSEL:
|
||||
- name: PLLQCLK
|
||||
description: Main PLLQCLK oscillator clock selected
|
||||
value: 14
|
||||
enum/MSIRANGE:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Range100K
|
||||
description: range 0 around 100 kHz
|
||||
value: 0
|
||||
- name: Range200K
|
||||
description: range 1 around 200 kHz
|
||||
value: 1
|
||||
- name: Range400K
|
||||
description: range 2 around 400 kHz
|
||||
value: 2
|
||||
- name: Range800K
|
||||
description: range 3 around 800 kHz
|
||||
value: 3
|
||||
- name: Range1M
|
||||
description: range 4 around 1 MHz
|
||||
value: 4
|
||||
- name: Range2M
|
||||
description: range 5 around 2 MHz
|
||||
value: 5
|
||||
- name: Range4M
|
||||
description: range 6 around 4 MHz
|
||||
value: 6
|
||||
- name: Range8M
|
||||
description: range 7 around 8 MHz
|
||||
value: 7
|
||||
- name: Range16M
|
||||
description: range 8 around 16 MHz
|
||||
value: 8
|
||||
- name: Range24M
|
||||
description: range 9 around 24 MHz
|
||||
value: 9
|
||||
- name: Range32M
|
||||
description: range 10 around 32 MHz
|
||||
value: 10
|
||||
- name: Range48M
|
||||
description: range 11 around 48 MHz
|
||||
value: 11
|
||||
enum/PLLM:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Div1
|
||||
value: 0
|
||||
- name: Div2
|
||||
value: 1
|
||||
- name: Div3
|
||||
value: 2
|
||||
- name: Div4
|
||||
value: 3
|
||||
- name: Div5
|
||||
value: 4
|
||||
- name: Div6
|
||||
value: 5
|
||||
- name: Div7
|
||||
value: 6
|
||||
- name: Div8
|
||||
value: 7
|
||||
enum/PLLN:
|
||||
bit_size: 7
|
||||
variants:
|
||||
- name: Mul6
|
||||
value: 6
|
||||
- name: Mul7
|
||||
value: 7
|
||||
- name: Mul8
|
||||
value: 8
|
||||
- name: Mul9
|
||||
value: 9
|
||||
- name: Mul10
|
||||
value: 10
|
||||
- name: Mul11
|
||||
value: 11
|
||||
- name: Mul12
|
||||
value: 12
|
||||
- name: Mul13
|
||||
value: 13
|
||||
- name: Mul14
|
||||
value: 14
|
||||
- name: Mul15
|
||||
value: 15
|
||||
- name: Mul16
|
||||
value: 16
|
||||
- name: Mul17
|
||||
value: 17
|
||||
- name: Mul18
|
||||
value: 18
|
||||
- name: Mul19
|
||||
value: 19
|
||||
- name: Mul20
|
||||
value: 20
|
||||
- name: Mul21
|
||||
value: 21
|
||||
- name: Mul22
|
||||
value: 22
|
||||
- name: Mul23
|
||||
value: 23
|
||||
- name: Mul24
|
||||
value: 24
|
||||
- name: Mul25
|
||||
value: 25
|
||||
- name: Mul26
|
||||
value: 26
|
||||
- name: Mul27
|
||||
value: 27
|
||||
- name: Mul28
|
||||
value: 28
|
||||
- name: Mul29
|
||||
value: 29
|
||||
- name: Mul30
|
||||
value: 30
|
||||
- name: Mul31
|
||||
value: 31
|
||||
- name: Mul32
|
||||
value: 32
|
||||
- name: Mul33
|
||||
value: 33
|
||||
- name: Mul34
|
||||
value: 34
|
||||
- name: Mul35
|
||||
value: 35
|
||||
- name: Mul36
|
||||
value: 36
|
||||
- name: Mul37
|
||||
value: 37
|
||||
- name: Mul38
|
||||
value: 38
|
||||
- name: Mul39
|
||||
value: 39
|
||||
- name: Mul40
|
||||
value: 40
|
||||
- name: Mul41
|
||||
value: 41
|
||||
- name: Mul42
|
||||
value: 42
|
||||
- name: Mul43
|
||||
value: 43
|
||||
- name: Mul44
|
||||
value: 44
|
||||
- name: Mul45
|
||||
value: 45
|
||||
- name: Mul46
|
||||
value: 46
|
||||
- name: Mul47
|
||||
value: 47
|
||||
- name: Mul48
|
||||
value: 48
|
||||
- name: Mul49
|
||||
value: 49
|
||||
- name: Mul50
|
||||
value: 50
|
||||
- name: Mul51
|
||||
value: 51
|
||||
- name: Mul52
|
||||
value: 52
|
||||
- name: Mul53
|
||||
value: 53
|
||||
- name: Mul54
|
||||
value: 54
|
||||
- name: Mul55
|
||||
value: 55
|
||||
- name: Mul56
|
||||
value: 56
|
||||
- name: Mul57
|
||||
value: 57
|
||||
- name: Mul58
|
||||
value: 58
|
||||
- name: Mul59
|
||||
value: 59
|
||||
- name: Mul60
|
||||
value: 60
|
||||
- name: Mul61
|
||||
value: 61
|
||||
- name: Mul62
|
||||
value: 62
|
||||
- name: Mul63
|
||||
value: 63
|
||||
- name: Mul64
|
||||
value: 64
|
||||
- name: Mul65
|
||||
value: 65
|
||||
- name: Mul66
|
||||
value: 66
|
||||
- name: Mul67
|
||||
value: 67
|
||||
- name: Mul68
|
||||
value: 68
|
||||
- name: Mul69
|
||||
value: 69
|
||||
- name: Mul70
|
||||
value: 70
|
||||
- name: Mul71
|
||||
value: 71
|
||||
- name: Mul72
|
||||
value: 72
|
||||
- name: Mul73
|
||||
value: 73
|
||||
- name: Mul74
|
||||
value: 74
|
||||
- name: Mul75
|
||||
value: 75
|
||||
- name: Mul76
|
||||
value: 76
|
||||
- name: Mul77
|
||||
value: 77
|
||||
- name: Mul78
|
||||
value: 78
|
||||
- name: Mul79
|
||||
value: 79
|
||||
- name: Mul80
|
||||
value: 80
|
||||
- name: Mul81
|
||||
value: 81
|
||||
- name: Mul82
|
||||
value: 82
|
||||
- name: Mul83
|
||||
value: 83
|
||||
- name: Mul84
|
||||
value: 84
|
||||
- name: Mul85
|
||||
value: 85
|
||||
- name: Mul86
|
||||
value: 86
|
||||
- name: Mul87
|
||||
value: 87
|
||||
- name: Mul88
|
||||
value: 88
|
||||
- name: Mul89
|
||||
value: 89
|
||||
- name: Mul90
|
||||
value: 90
|
||||
- name: Mul91
|
||||
value: 91
|
||||
- name: Mul92
|
||||
value: 92
|
||||
- name: Mul93
|
||||
value: 93
|
||||
- name: Mul94
|
||||
value: 94
|
||||
- name: Mul95
|
||||
value: 95
|
||||
- name: Mul96
|
||||
value: 96
|
||||
- name: Mul97
|
||||
value: 97
|
||||
- name: Mul98
|
||||
value: 98
|
||||
- name: Mul99
|
||||
value: 99
|
||||
- name: Mul100
|
||||
value: 100
|
||||
- name: Mul101
|
||||
value: 101
|
||||
- name: Mul102
|
||||
value: 102
|
||||
- name: Mul103
|
||||
value: 103
|
||||
- name: Mul104
|
||||
value: 104
|
||||
- name: Mul105
|
||||
value: 105
|
||||
- name: Mul106
|
||||
value: 106
|
||||
- name: Mul107
|
||||
value: 107
|
||||
- name: Mul108
|
||||
value: 108
|
||||
- name: Mul109
|
||||
value: 109
|
||||
- name: Mul110
|
||||
value: 110
|
||||
- name: Mul111
|
||||
value: 111
|
||||
- name: Mul112
|
||||
value: 112
|
||||
- name: Mul113
|
||||
value: 113
|
||||
- name: Mul114
|
||||
value: 114
|
||||
- name: Mul115
|
||||
value: 115
|
||||
- name: Mul116
|
||||
value: 116
|
||||
- name: Mul117
|
||||
value: 117
|
||||
- name: Mul118
|
||||
value: 118
|
||||
- name: Mul119
|
||||
value: 119
|
||||
- name: Mul120
|
||||
value: 120
|
||||
- name: Mul121
|
||||
value: 121
|
||||
- name: Mul122
|
||||
value: 122
|
||||
- name: Mul123
|
||||
value: 123
|
||||
- name: Mul124
|
||||
value: 124
|
||||
- name: Mul125
|
||||
value: 125
|
||||
- name: Mul126
|
||||
value: 126
|
||||
- name: Mul127
|
||||
value: 127
|
||||
enum/PLLP:
|
||||
bit_size: 5
|
||||
variants:
|
||||
- name: Div2
|
||||
value: 1
|
||||
- name: Div3
|
||||
value: 2
|
||||
- name: Div4
|
||||
value: 3
|
||||
- name: Div5
|
||||
value: 4
|
||||
- name: Div6
|
||||
value: 5
|
||||
- name: Div7
|
||||
value: 6
|
||||
- name: Div8
|
||||
value: 7
|
||||
- name: Div9
|
||||
value: 8
|
||||
- name: Div10
|
||||
value: 9
|
||||
- name: Div11
|
||||
value: 10
|
||||
- name: Div12
|
||||
value: 11
|
||||
- name: Div13
|
||||
value: 12
|
||||
- name: Div14
|
||||
value: 13
|
||||
- name: Div15
|
||||
value: 14
|
||||
- name: Div16
|
||||
value: 15
|
||||
- name: Div17
|
||||
value: 16
|
||||
- name: Div18
|
||||
value: 17
|
||||
- name: Div19
|
||||
value: 18
|
||||
- name: Div20
|
||||
value: 19
|
||||
- name: Div21
|
||||
value: 20
|
||||
- name: Div22
|
||||
value: 21
|
||||
- name: Div23
|
||||
value: 22
|
||||
- name: Div24
|
||||
value: 23
|
||||
- name: Div25
|
||||
value: 24
|
||||
- name: Div26
|
||||
value: 25
|
||||
- name: Div27
|
||||
value: 26
|
||||
- name: Div28
|
||||
value: 27
|
||||
- name: Div29
|
||||
value: 28
|
||||
- name: Div30
|
||||
value: 29
|
||||
- name: Div31
|
||||
value: 30
|
||||
enum/PLLQ:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Div2
|
||||
value: 1
|
||||
- name: Div3
|
||||
value: 2
|
||||
- name: Div4
|
||||
value: 3
|
||||
- name: Div5
|
||||
value: 4
|
||||
- name: Div6
|
||||
value: 5
|
||||
- name: Div7
|
||||
value: 6
|
||||
enum/PLLR:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Div2
|
||||
value: 1
|
||||
- name: Div3
|
||||
value: 2
|
||||
- name: Div4
|
||||
value: 3
|
||||
- name: Div5
|
||||
value: 4
|
||||
- name: Div6
|
||||
value: 5
|
||||
- name: Div7
|
||||
value: 6
|
||||
enum/PLLSRC:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: NoClock
|
||||
description: No clock selected as PLL entry clock source
|
||||
value: 0
|
||||
- name: MSI
|
||||
description: MSI selected as PLL entry clock source
|
||||
value: 1
|
||||
- name: HSI16
|
||||
description: HSI16 selected as PLL entry clock source
|
||||
value: 2
|
||||
- name: HSE32
|
||||
description: HSE selected as PLL entry clock source
|
||||
value: 3
|
||||
enum/PPRE:
|
||||
bit_size: 3
|
||||
variants:
|
||||
@ -1585,3 +2009,14 @@ enum/RTCSEL:
|
||||
- name: HSE
|
||||
description: HSE oscillator clock divided by 32 selected
|
||||
value: 3
|
||||
enum/SW:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: MSI
|
||||
value: 0
|
||||
- name: HSI16
|
||||
value: 1
|
||||
- name: HSE32
|
||||
value: 2
|
||||
- name: PLLR
|
||||
value: 3
|
||||
|
||||
@ -702,10 +702,12 @@ fieldset/CFGR:
|
||||
description: System clock switch
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
enum: SW
|
||||
- name: SWS
|
||||
description: System clock switch status
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
enum: SW
|
||||
- name: HPRE
|
||||
description: HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)
|
||||
bit_offset: 4
|
||||
@ -871,6 +873,7 @@ fieldset/CR:
|
||||
description: MSI clock ranges
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
enum: MSIRANGE
|
||||
- name: HSION
|
||||
description: HSI16 clock enable
|
||||
bit_offset: 8
|
||||
@ -989,6 +992,7 @@ fieldset/EXTCFGR:
|
||||
description: HCLK3 shared prescaler (AHB3, Flash, and SRAM2)
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
enum: HPRE
|
||||
- name: SHDHPREF
|
||||
description: HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)
|
||||
bit_offset: 16
|
||||
@ -1019,14 +1023,17 @@ fieldset/PLLCFGR:
|
||||
description: Main PLL entry clock source
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
enum: PLLSRC
|
||||
- name: PLLM
|
||||
description: Division factor for the main PLL input clock
|
||||
bit_offset: 4
|
||||
bit_size: 3
|
||||
enum: PLLM
|
||||
- name: PLLN
|
||||
description: Main PLL multiplication factor for VCO
|
||||
bit_offset: 8
|
||||
bit_size: 7
|
||||
enum: PLLN
|
||||
- name: PLLPEN
|
||||
description: Main PLL PLLPCLK output enable
|
||||
bit_offset: 16
|
||||
@ -1035,6 +1042,7 @@ fieldset/PLLCFGR:
|
||||
description: Main PLL division factor for PLLPCLK.
|
||||
bit_offset: 17
|
||||
bit_size: 5
|
||||
enum: PLLP
|
||||
- name: PLLQEN
|
||||
description: Main PLL PLLQCLK output enable
|
||||
bit_offset: 24
|
||||
@ -1043,6 +1051,7 @@ fieldset/PLLCFGR:
|
||||
description: Main PLL division factor for PLLQCLK
|
||||
bit_offset: 25
|
||||
bit_size: 3
|
||||
enum: PLLQ
|
||||
- name: PLLREN
|
||||
description: Main PLL PLLRCLK output enable
|
||||
bit_offset: 28
|
||||
@ -1051,6 +1060,7 @@ fieldset/PLLCFGR:
|
||||
description: Main PLL division factor for PLLRCLK
|
||||
bit_offset: 29
|
||||
bit_size: 3
|
||||
enum: PLLR
|
||||
enum/ADCSEL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
@ -1174,6 +1184,419 @@ enum/MCOSEL:
|
||||
- name: PLLQCLK
|
||||
description: Main PLLQCLK oscillator clock selected
|
||||
value: 14
|
||||
enum/MSIRANGE:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Range100K
|
||||
description: range 0 around 100 kHz
|
||||
value: 0
|
||||
- name: Range200K
|
||||
description: range 1 around 200 kHz
|
||||
value: 1
|
||||
- name: Range400K
|
||||
description: range 2 around 400 kHz
|
||||
value: 2
|
||||
- name: Range800K
|
||||
description: range 3 around 800 kHz
|
||||
value: 3
|
||||
- name: Range1M
|
||||
description: range 4 around 1 MHz
|
||||
value: 4
|
||||
- name: Range2M
|
||||
description: range 5 around 2 MHz
|
||||
value: 5
|
||||
- name: Range4M
|
||||
description: range 6 around 4 MHz
|
||||
value: 6
|
||||
- name: Range8M
|
||||
description: range 7 around 8 MHz
|
||||
value: 7
|
||||
- name: Range16M
|
||||
description: range 8 around 16 MHz
|
||||
value: 8
|
||||
- name: Range24M
|
||||
description: range 9 around 24 MHz
|
||||
value: 9
|
||||
- name: Range32M
|
||||
description: range 10 around 32 MHz
|
||||
value: 10
|
||||
- name: Range48M
|
||||
description: range 11 around 48 MHz
|
||||
value: 11
|
||||
enum/PLLM:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Div1
|
||||
value: 0
|
||||
- name: Div2
|
||||
value: 1
|
||||
- name: Div3
|
||||
value: 2
|
||||
- name: Div4
|
||||
value: 3
|
||||
- name: Div5
|
||||
value: 4
|
||||
- name: Div6
|
||||
value: 5
|
||||
- name: Div7
|
||||
value: 6
|
||||
- name: Div8
|
||||
value: 7
|
||||
enum/PLLN:
|
||||
bit_size: 7
|
||||
variants:
|
||||
- name: Mul6
|
||||
value: 6
|
||||
- name: Mul7
|
||||
value: 7
|
||||
- name: Mul8
|
||||
value: 8
|
||||
- name: Mul9
|
||||
value: 9
|
||||
- name: Mul10
|
||||
value: 10
|
||||
- name: Mul11
|
||||
value: 11
|
||||
- name: Mul12
|
||||
value: 12
|
||||
- name: Mul13
|
||||
value: 13
|
||||
- name: Mul14
|
||||
value: 14
|
||||
- name: Mul15
|
||||
value: 15
|
||||
- name: Mul16
|
||||
value: 16
|
||||
- name: Mul17
|
||||
value: 17
|
||||
- name: Mul18
|
||||
value: 18
|
||||
- name: Mul19
|
||||
value: 19
|
||||
- name: Mul20
|
||||
value: 20
|
||||
- name: Mul21
|
||||
value: 21
|
||||
- name: Mul22
|
||||
value: 22
|
||||
- name: Mul23
|
||||
value: 23
|
||||
- name: Mul24
|
||||
value: 24
|
||||
- name: Mul25
|
||||
value: 25
|
||||
- name: Mul26
|
||||
value: 26
|
||||
- name: Mul27
|
||||
value: 27
|
||||
- name: Mul28
|
||||
value: 28
|
||||
- name: Mul29
|
||||
value: 29
|
||||
- name: Mul30
|
||||
value: 30
|
||||
- name: Mul31
|
||||
value: 31
|
||||
- name: Mul32
|
||||
value: 32
|
||||
- name: Mul33
|
||||
value: 33
|
||||
- name: Mul34
|
||||
value: 34
|
||||
- name: Mul35
|
||||
value: 35
|
||||
- name: Mul36
|
||||
value: 36
|
||||
- name: Mul37
|
||||
value: 37
|
||||
- name: Mul38
|
||||
value: 38
|
||||
- name: Mul39
|
||||
value: 39
|
||||
- name: Mul40
|
||||
value: 40
|
||||
- name: Mul41
|
||||
value: 41
|
||||
- name: Mul42
|
||||
value: 42
|
||||
- name: Mul43
|
||||
value: 43
|
||||
- name: Mul44
|
||||
value: 44
|
||||
- name: Mul45
|
||||
value: 45
|
||||
- name: Mul46
|
||||
value: 46
|
||||
- name: Mul47
|
||||
value: 47
|
||||
- name: Mul48
|
||||
value: 48
|
||||
- name: Mul49
|
||||
value: 49
|
||||
- name: Mul50
|
||||
value: 50
|
||||
- name: Mul51
|
||||
value: 51
|
||||
- name: Mul52
|
||||
value: 52
|
||||
- name: Mul53
|
||||
value: 53
|
||||
- name: Mul54
|
||||
value: 54
|
||||
- name: Mul55
|
||||
value: 55
|
||||
- name: Mul56
|
||||
value: 56
|
||||
- name: Mul57
|
||||
value: 57
|
||||
- name: Mul58
|
||||
value: 58
|
||||
- name: Mul59
|
||||
value: 59
|
||||
- name: Mul60
|
||||
value: 60
|
||||
- name: Mul61
|
||||
value: 61
|
||||
- name: Mul62
|
||||
value: 62
|
||||
- name: Mul63
|
||||
value: 63
|
||||
- name: Mul64
|
||||
value: 64
|
||||
- name: Mul65
|
||||
value: 65
|
||||
- name: Mul66
|
||||
value: 66
|
||||
- name: Mul67
|
||||
value: 67
|
||||
- name: Mul68
|
||||
value: 68
|
||||
- name: Mul69
|
||||
value: 69
|
||||
- name: Mul70
|
||||
value: 70
|
||||
- name: Mul71
|
||||
value: 71
|
||||
- name: Mul72
|
||||
value: 72
|
||||
- name: Mul73
|
||||
value: 73
|
||||
- name: Mul74
|
||||
value: 74
|
||||
- name: Mul75
|
||||
value: 75
|
||||
- name: Mul76
|
||||
value: 76
|
||||
- name: Mul77
|
||||
value: 77
|
||||
- name: Mul78
|
||||
value: 78
|
||||
- name: Mul79
|
||||
value: 79
|
||||
- name: Mul80
|
||||
value: 80
|
||||
- name: Mul81
|
||||
value: 81
|
||||
- name: Mul82
|
||||
value: 82
|
||||
- name: Mul83
|
||||
value: 83
|
||||
- name: Mul84
|
||||
value: 84
|
||||
- name: Mul85
|
||||
value: 85
|
||||
- name: Mul86
|
||||
value: 86
|
||||
- name: Mul87
|
||||
value: 87
|
||||
- name: Mul88
|
||||
value: 88
|
||||
- name: Mul89
|
||||
value: 89
|
||||
- name: Mul90
|
||||
value: 90
|
||||
- name: Mul91
|
||||
value: 91
|
||||
- name: Mul92
|
||||
value: 92
|
||||
- name: Mul93
|
||||
value: 93
|
||||
- name: Mul94
|
||||
value: 94
|
||||
- name: Mul95
|
||||
value: 95
|
||||
- name: Mul96
|
||||
value: 96
|
||||
- name: Mul97
|
||||
value: 97
|
||||
- name: Mul98
|
||||
value: 98
|
||||
- name: Mul99
|
||||
value: 99
|
||||
- name: Mul100
|
||||
value: 100
|
||||
- name: Mul101
|
||||
value: 101
|
||||
- name: Mul102
|
||||
value: 102
|
||||
- name: Mul103
|
||||
value: 103
|
||||
- name: Mul104
|
||||
value: 104
|
||||
- name: Mul105
|
||||
value: 105
|
||||
- name: Mul106
|
||||
value: 106
|
||||
- name: Mul107
|
||||
value: 107
|
||||
- name: Mul108
|
||||
value: 108
|
||||
- name: Mul109
|
||||
value: 109
|
||||
- name: Mul110
|
||||
value: 110
|
||||
- name: Mul111
|
||||
value: 111
|
||||
- name: Mul112
|
||||
value: 112
|
||||
- name: Mul113
|
||||
value: 113
|
||||
- name: Mul114
|
||||
value: 114
|
||||
- name: Mul115
|
||||
value: 115
|
||||
- name: Mul116
|
||||
value: 116
|
||||
- name: Mul117
|
||||
value: 117
|
||||
- name: Mul118
|
||||
value: 118
|
||||
- name: Mul119
|
||||
value: 119
|
||||
- name: Mul120
|
||||
value: 120
|
||||
- name: Mul121
|
||||
value: 121
|
||||
- name: Mul122
|
||||
value: 122
|
||||
- name: Mul123
|
||||
value: 123
|
||||
- name: Mul124
|
||||
value: 124
|
||||
- name: Mul125
|
||||
value: 125
|
||||
- name: Mul126
|
||||
value: 126
|
||||
- name: Mul127
|
||||
value: 127
|
||||
enum/PLLP:
|
||||
bit_size: 5
|
||||
variants:
|
||||
- name: Div2
|
||||
value: 1
|
||||
- name: Div3
|
||||
value: 2
|
||||
- name: Div4
|
||||
value: 3
|
||||
- name: Div5
|
||||
value: 4
|
||||
- name: Div6
|
||||
value: 5
|
||||
- name: Div7
|
||||
value: 6
|
||||
- name: Div8
|
||||
value: 7
|
||||
- name: Div9
|
||||
value: 8
|
||||
- name: Div10
|
||||
value: 9
|
||||
- name: Div11
|
||||
value: 10
|
||||
- name: Div12
|
||||
value: 11
|
||||
- name: Div13
|
||||
value: 12
|
||||
- name: Div14
|
||||
value: 13
|
||||
- name: Div15
|
||||
value: 14
|
||||
- name: Div16
|
||||
value: 15
|
||||
- name: Div17
|
||||
value: 16
|
||||
- name: Div18
|
||||
value: 17
|
||||
- name: Div19
|
||||
value: 18
|
||||
- name: Div20
|
||||
value: 19
|
||||
- name: Div21
|
||||
value: 20
|
||||
- name: Div22
|
||||
value: 21
|
||||
- name: Div23
|
||||
value: 22
|
||||
- name: Div24
|
||||
value: 23
|
||||
- name: Div25
|
||||
value: 24
|
||||
- name: Div26
|
||||
value: 25
|
||||
- name: Div27
|
||||
value: 26
|
||||
- name: Div28
|
||||
value: 27
|
||||
- name: Div29
|
||||
value: 28
|
||||
- name: Div30
|
||||
value: 29
|
||||
- name: Div31
|
||||
value: 30
|
||||
enum/PLLQ:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Div2
|
||||
value: 1
|
||||
- name: Div3
|
||||
value: 2
|
||||
- name: Div4
|
||||
value: 3
|
||||
- name: Div5
|
||||
value: 4
|
||||
- name: Div6
|
||||
value: 5
|
||||
- name: Div7
|
||||
value: 6
|
||||
enum/PLLR:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Div2
|
||||
value: 1
|
||||
- name: Div3
|
||||
value: 2
|
||||
- name: Div4
|
||||
value: 3
|
||||
- name: Div5
|
||||
value: 4
|
||||
- name: Div6
|
||||
value: 5
|
||||
- name: Div7
|
||||
value: 6
|
||||
enum/PLLSRC:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: NoClock
|
||||
description: No clock selected as PLL entry clock source
|
||||
value: 0
|
||||
- name: MSI
|
||||
description: MSI selected as PLL entry clock source
|
||||
value: 1
|
||||
- name: HSI16
|
||||
description: HSI16 selected as PLL entry clock source
|
||||
value: 2
|
||||
- name: HSE32
|
||||
description: HSE selected as PLL entry clock source
|
||||
value: 3
|
||||
enum/PPRE:
|
||||
bit_size: 3
|
||||
variants:
|
||||
@ -1207,3 +1630,14 @@ enum/RTCSEL:
|
||||
- name: HSE
|
||||
description: HSE oscillator clock divided by 32 selected
|
||||
value: 3
|
||||
enum/SW:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: MSI
|
||||
value: 0
|
||||
- name: HSI16
|
||||
value: 1
|
||||
- name: HSE32
|
||||
value: 2
|
||||
- name: PLLR
|
||||
value: 3
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user