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rcc/l5: unify clk48sel vs clk48msel

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This commit is contained in:
Dario Nieuwenhuis 2023-10-16 01:37:21 +02:00
parent 01a757e40d
commit f437c33b41
1 changed files with 5 additions and 5 deletions
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10
data/registers/rcc_l5.yaml
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@ -1374,7 +1374,7 @@ fieldset/CCIPR1:
description: FDCAN clock source selection
bit_offset: 24
bit_size: 2
- name: CLK48MSEL
- name: CLK48SEL
description: 48 MHz clock source selection
bit_offset: 26
bit_size: 2
@ -1900,8 +1900,8 @@ fieldset/SECCFGR:
description: PLLSAI2SEC
bit_offset: 9
bit_size: 1
- name: CLK48MSEC
description: CLK48MSEC
- name: CLK48SEC
description: CLK48SEC
bit_offset: 10
bit_size: 1
- name: HSI48SEC
@ -1955,8 +1955,8 @@ fieldset/SECSR:
description: PLLSAI2SECF
bit_offset: 9
bit_size: 1
- name: CLK48MSECF
description: CLK48MSECF
- name: CLK48SECF
description: CLK48SECF
bit_offset: 10
bit_size: 1
- name: HSI48SECF