From f437c33b4199c751194d592f90a3af598092d6c2 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 16 Oct 2023 01:37:21 +0200
Subject: [PATCH] rcc/l5: unify clk48sel vs clk48msel

---
 data/registers/rcc_l5.yaml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml
index 7aa51a5..33359c0 100644
--- a/data/registers/rcc_l5.yaml
+++ b/data/registers/rcc_l5.yaml
@@ -1374,7 +1374,7 @@ fieldset/CCIPR1:
     description: FDCAN clock source selection
     bit_offset: 24
     bit_size: 2
-  - name: CLK48MSEL
+  - name: CLK48SEL
     description: 48 MHz clock source selection
     bit_offset: 26
     bit_size: 2
@@ -1900,8 +1900,8 @@ fieldset/SECCFGR:
     description: PLLSAI2SEC
     bit_offset: 9
     bit_size: 1
-  - name: CLK48MSEC
-    description: CLK48MSEC
+  - name: CLK48SEC
+    description: CLK48SEC
     bit_offset: 10
     bit_size: 1
   - name: HSI48SEC
@@ -1955,8 +1955,8 @@ fieldset/SECSR:
     description: PLLSAI2SECF
     bit_offset: 9
     bit_size: 1
-  - name: CLK48MSECF
-    description: CLK48MSECF
+  - name: CLK48SECF
+    description: CLK48SECF
     bit_offset: 10
     bit_size: 1
   - name: HSI48SECF