Dario Nieuwenhuis
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e317d781d8
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Merge pull request #87 from mryndzionek/stm32f1_support
Updated register mapping for STM32 F1 AFIO
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2021-09-23 18:57:52 +02:00 |
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Mariusz Ryndzionek
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8dde100c15
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Updated register mapping for STM32 F1 AFIO
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2021-09-23 18:54:22 +02:00 |
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Dario Nieuwenhuis
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5dec590202
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Merge pull request #85 from mryndzionek/stm32f1_support
Add initial register mapping for STM32 F1 AFIO and FLASH
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2021-09-23 17:36:38 +02:00 |
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Ulf Lilleengen
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f1e7e9ef84
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Merge pull request #86 from lulf/stm32l1-pwr-and-fix
Add PWR register block and fix RCC register block
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2021-09-23 14:42:49 +02:00 |
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Ulf Lilleengen
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a302947e87
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Add PWR register block and fix RCC register block
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2021-09-23 14:40:59 +02:00 |
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Mariusz Ryndzionek
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fbea23bd00
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Added missing FLASH registers (generated automatically)
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2021-09-23 07:09:11 +02:00 |
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Mariusz Ryndzionek
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c0938c9102
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Add initial register mapping for STM32 F1 AFIO and FLASH
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2021-09-22 18:22:36 +02:00 |
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Dario Nieuwenhuis
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1d62ba5e14
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Merge pull request #84 from lulf/l1-regs
L1 regs
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2021-09-15 14:55:09 +02:00 |
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Ulf Lilleengen
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9f1bd7d0d0
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Update chip yaml
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2021-09-15 14:47:33 +02:00 |
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Ulf Lilleengen
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e2bf041808
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Add register mapping for STM32 L1 SYSCFG and DBGMCU
Add missing GPIO port mapping
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2021-09-15 14:47:01 +02:00 |
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Dario Nieuwenhuis
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616a2779d0
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Merge pull request #82 from bgamari/stm32g0
Fix ADC register layout on STM32G0
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2021-08-31 22:21:51 +02:00 |
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Dario Nieuwenhuis
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96c902c66c
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Merge pull request #83 from lulf/stm32wl55-pwr
Stm32wl55 pwr
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2021-08-31 22:18:57 +02:00 |
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Ulf Lilleengen
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201510407c
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Handle SUBGHZSPI peripheral so it is recognized as an SPI peripheral
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2021-08-31 14:43:02 +02:00 |
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Ulf Lilleengen
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902b9a6986
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Add PWR peripheral for STM32WL5
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2021-08-31 14:34:54 +02:00 |
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Ben Gamari
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3a88360dc6
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Add PWR registers for STM32G0
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2021-08-31 01:46:26 -04:00 |
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Ben Gamari
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5366833cbd
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Introduce ADC register set for STM32G0
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2021-08-31 01:46:02 -04:00 |
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Dario Nieuwenhuis
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deb37365d7
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exti: g0 and l5 are 8 bits per line...
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2021-08-20 01:26:33 +02:00 |
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Dario Nieuwenhuis
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8534ae884d
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rcc: make GPIO EN/RST regs naming consistent.
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2021-08-19 23:50:42 +02:00 |
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Dario Nieuwenhuis
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3b6363dffb
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wl rcc: rename SPI2S2 -> SPI2
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2021-08-19 22:37:07 +02:00 |
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Dario Nieuwenhuis
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49e579e97f
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Add F2 RCC
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2021-08-19 22:12:39 +02:00 |
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Dario Nieuwenhuis
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e289dd883f
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Cleanup EXTI
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2021-08-19 21:54:22 +02:00 |
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Dario Nieuwenhuis
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701ab04c2a
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Cleanup SYSCFG naming
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2021-08-19 21:28:32 +02:00 |
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Dario Nieuwenhuis
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31997049ea
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Fix wrong register offsets in WB SYSCFG
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2021-08-19 19:20:13 +02:00 |
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Dario Nieuwenhuis
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6af9f2c0d1
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Add RCC for F3, F7, G4, H7AB, L1, L5, WB*, WL5, WLE
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2021-08-19 19:13:30 +02:00 |
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Dario Nieuwenhuis
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bd402a58f2
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Merge pull request #72 from bgamari/stm32g0
STM32G0 support
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2021-08-19 16:05:29 +02:00 |
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Ben Gamari
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254c59c064
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Introduce STM32G0 ADC support
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2021-08-19 15:57:17 +02:00 |
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Ben Gamari
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f57a268b9f
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Add STM32G0 support
Includes manually specified register layouts for EXTI and SYSCFG.
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2021-08-19 15:57:00 +02:00 |
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Ben Gamari
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075d283354
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parse: Drop duplicate pin definitions
The STM32G0 SVDs contain duplicate pin declarations.
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2021-08-19 15:55:13 +02:00 |
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Ben Gamari
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9c753da57b
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Add a bit of documentation for register extraction process
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2021-08-19 15:54:36 +02:00 |
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Ben Gamari
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f5808de749
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Add RCC support for STM32G0
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2021-08-19 15:54:36 +02:00 |
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Ben Gamari
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e735ea9769
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Fix hash-bangs
/usr/bin/bash isn't portable.
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2021-08-19 15:54:36 +02:00 |
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Dario Nieuwenhuis
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8bb9c26d38
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Update README.md
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2021-08-18 22:17:16 +02:00 |
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Dario Nieuwenhuis
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f0e85a7e0d
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Merge pull request #81 from embassy-rs/add-wl55-radio-spi
Add wl55 radio spi
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2021-08-18 15:21:45 +02:00 |
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Ulf Lilleengen
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63d1af4eca
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Rerun parse.py
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2021-08-18 14:16:49 +02:00 |
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Ulf Lilleengen
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d9708f6bfc
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Use correct peripheral name for SUBGHZ SPI
* Add SPI2s1_v3_5 register block for SUBGHZSPI peripheral
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2021-08-18 14:00:14 +02:00 |
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Ulf Lilleengen
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04ae6ce25e
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Add SPI2s1_v3_5
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2021-08-18 13:59:51 +02:00 |
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Dario Nieuwenhuis
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80af84607a
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Merge pull request #80 from lulf/stm32wl55-regs
Stm32wl55 exti regs
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2021-08-17 15:51:18 +02:00 |
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Ulf Lilleengen
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919a61e847
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Add STM32WL5x exti block
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2021-08-17 13:02:49 +02:00 |
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Dario Nieuwenhuis
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32b5c5c890
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Merge pull request #79 from bobmcwhirter/h7_exti
H7 exti
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2021-08-16 21:30:12 +02:00 |
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Bob McWhirter
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541091cded
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Include the reg block.
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2021-08-16 15:12:17 -04:00 |
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Bob McWhirter
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2c7422ab76
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Special-case the H7 EXTI reg layout.
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2021-08-16 14:59:16 -04:00 |
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Ulf Lilleengen
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4c801c1234
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Merge pull request #78 from lulf/parse-bugfix
Parse bugfix and expose shared usart irqs
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2021-08-16 16:48:39 +02:00 |
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Ulf Lilleengen
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154d226f7a
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Handle shared USART IRQs
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2021-08-16 13:02:25 +02:00 |
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Ulf Lilleengen
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a84e7d8b8c
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Add ability to override peripheral address if bug in header sources
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2021-08-16 13:01:25 +02:00 |
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Ulf Lilleengen
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7489588564
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Give different names to secure and non-secure cores
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2021-08-16 12:38:33 +02:00 |
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Dario Nieuwenhuis
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a7bebbd2ef
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Merge pull request #77 from timokroeger/can-interrupts
CAN interrupts
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2021-08-15 13:20:09 +02:00 |
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Timo Kröger
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c5a86b0744
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CAN interrupts
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2021-08-15 11:13:26 +02:00 |
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Dario Nieuwenhuis
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8c392a059b
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Merge pull request #74 from timokroeger/bxcan
bxCAN Peripheral
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2021-08-15 00:10:26 +02:00 |
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Dario Nieuwenhuis
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946eb0bb59
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Merge pull request #76 from FrozenDroid/main
add UART:sci2_v2_1 to parser
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2021-08-13 16:35:11 +02:00 |
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Vincent Stakenburg
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67c16f80cf
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add UART:sci2_v2_1 to parser
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2021-08-13 16:02:12 +02:00 |
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