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fmt all register yamls

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This commit is contained in:
Dario Nieuwenhuis 2021-11-17 21:23:26 +01:00
parent e00ad29955
commit c6c5c099bb
61 changed files with 34425 additions and 34740 deletions
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30
data/registers/adc_g0.yaml
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@ -615,6 +615,21 @@ fieldset/VERR:
description: Major Revision number description: Major Revision number
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
enum/RES:
bit_size: 2
variants:
- name: TwelveBit
description: 12-bit resolution
value: 0
- name: TenBit
description: 10-bit resolution
value: 1
- name: EightBit
description: 8-bit resolution
value: 2
- name: SixBit
description: 6-bit resolution
value: 3
enum/SAMPLE_TIME: enum/SAMPLE_TIME:
bit_size: 3 bit_size: 3
variants: variants:
@ -642,18 +657,3 @@ enum/SAMPLE_TIME:
- name: Cycles160_5 - name: Cycles160_5
description: 160.5 ADC cycles description: 160.5 ADC cycles
value: 7 value: 7
enum/RES:
bit_size: 2
variants:
- name: TwelveBit
description: 12-bit resolution
value: 0
- name: TenBit
description: 10-bit resolution
value: 1
- name: EightBit
description: 8-bit resolution
value: 2
- name: SixBit
description: 6-bit resolution
value: 3

1382
data/registers/adc_v2.yaml
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File diff suppressed because it is too large Load Diff

34
data/registers/adc_v3.yaml
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@ -521,10 +521,10 @@ fieldset/SMPR1:
description: Channel 0 sampling time selection description: Channel 0 sampling time selection
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
enum: SAMPLE_TIME
array: array:
len: 10 len: 10
stride: 3 stride: 3
enum: SAMPLE_TIME
fieldset/SMPR2: fieldset/SMPR2:
description: sample time register 2 description: sample time register 2
fields: fields:
@ -532,10 +532,10 @@ fieldset/SMPR2:
description: Channel 10 sampling time selection description: Channel 10 sampling time selection
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
enum: SAMPLE_TIME
array: array:
len: 9 len: 9
stride: 3 stride: 3
enum: SAMPLE_TIME
fieldset/SQR1: fieldset/SQR1:
description: regular sequence register 1 description: regular sequence register 1
fields: fields:
@ -631,6 +631,21 @@ fieldset/TR3:
array: array:
len: 1 len: 1
stride: 0 stride: 0
enum/RES:
bit_size: 2
variants:
- name: TwelveBit
description: 12-bit resolution
value: 0
- name: TenBit
description: 10-bit resolution
value: 1
- name: EightBit
description: 8-bit resolution
value: 2
- name: SixBit
description: 6-bit resolution
value: 3
enum/SAMPLE_TIME: enum/SAMPLE_TIME:
bit_size: 3 bit_size: 3
variants: variants:
@ -658,18 +673,3 @@ enum/SAMPLE_TIME:
- name: Cycles640_5 - name: Cycles640_5
description: 640.5 ADC cycles description: 640.5 ADC cycles
value: 7 value: 7
enum/RES:
bit_size: 2
variants:
- name: TwelveBit
description: 12-bit resolution
value: 0
- name: TenBit
description: 10-bit resolution
value: 1
- name: EightBit
description: 8-bit resolution
value: 2
- name: SixBit
description: 6-bit resolution
value: 3

515
data/registers/adccommon_v2.yaml
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@ -2,271 +2,268 @@
block/ADC_COMMON: block/ADC_COMMON:
description: ADC common registers description: ADC common registers
items: items:
- access: Read - name: CSR
byte_offset: 0 description: ADC Common status register
description: ADC Common status register byte_offset: 0
fieldset: CSR access: Read
name: CSR fieldset: CSR
- byte_offset: 4 - name: CCR
description: ADC common control register description: ADC common control register
fieldset: CCR byte_offset: 4
name: CCR fieldset: CCR
- access: Read - name: CDR
byte_offset: 8 description: ADC common regular data register for dual and triple modes
description: ADC common regular data register for dual and triple modes byte_offset: 8
fieldset: CDR access: Read
name: CDR fieldset: CDR
enum/ADCPRE:
bit_size: 2
variants:
- description: PCLK2 divided by 2
name: Div2
value: 0
- description: PCLK2 divided by 4
name: Div4
value: 1
- description: PCLK2 divided by 6
name: Div6
value: 2
- description: PCLK2 divided by 8
name: Div8
value: 3
enum/AWD:
bit_size: 1
variants:
- description: No analog watchdog event occurred
name: NoEvent
value: 0
- description: Analog watchdog event occurred
name: Event
value: 1
enum/DDS:
bit_size: 1
variants:
- description: No new DMA request is issued after the last transfer
name: Single
value: 0
- description: DMA requests are issued as long as data are converted and DMA=01,
10 or 11
name: Continuous
value: 1
enum/DMA:
bit_size: 2
variants:
- description: DMA mode disabled
name: Disabled
value: 0
- description: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
name: Mode1
value: 1
- description: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then
3&2)
name: Mode2
value: 2
- description: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then
3&2)
name: Mode3
value: 3
enum/EOC:
bit_size: 1
variants:
- description: Conversion is not complete
name: NotComplete
value: 0
- description: Conversion complete
name: Complete
value: 1
enum/JEOC:
bit_size: 1
variants:
- description: Conversion is not complete
name: NotComplete
value: 0
- description: Conversion complete
name: Complete
value: 1
enum/JSTRT:
bit_size: 1
variants:
- description: No injected channel conversion started
name: NotStarted
value: 0
- description: Injected channel conversion has started
name: Started
value: 1
enum/MULTI:
bit_size: 5
variants:
- description: 'All the ADCs independent: independent mode'
name: Independent
value: 0
- description: Dual ADC1 and ADC2, combined regular and injected simultaneous mode
name: DualRJ
value: 1
- description: Dual ADC1 and ADC2, combined regular and alternate trigger mode
name: DualRA
value: 2
- description: Dual ADC1 and ADC2, injected simultaneous mode only
name: DualJ
value: 5
- description: Dual ADC1 and ADC2, regular simultaneous mode only
name: DualR
value: 6
- description: Dual ADC1 and ADC2, interleaved mode only
name: DualI
value: 7
- description: Dual ADC1 and ADC2, alternate trigger mode only
name: DualA
value: 9
- description: Triple ADC, regular and injected simultaneous mode
name: TripleRJ
value: 17
- description: Triple ADC, regular and alternate trigger mode
name: TripleRA
value: 18
- description: Triple ADC, injected simultaneous mode only
name: TripleJ
value: 21
- description: Triple ADC, regular simultaneous mode only
name: TripleR
value: 22
- description: Triple ADC, interleaved mode only
name: TripleI
value: 23
- description: Triple ADC, alternate trigger mode only
name: TripleA
value: 24
enum/OVR:
bit_size: 1
variants:
- description: No overrun occurred
name: NoOverrun
value: 0
- description: Overrun occurred
name: Overrun
value: 1
enum/STRT:
bit_size: 1
variants:
- description: No regular channel conversion started
name: NotStarted
value: 0
- description: Regular channel conversion has started
name: Started
value: 1
enum/TSVREFE:
bit_size: 1
variants:
- description: Temperature sensor and V_REFINT channel disabled
name: Disabled
value: 0
- description: Temperature sensor and V_REFINT channel enabled
name: Enabled
value: 1
enum/VBATE:
bit_size: 1
variants:
- description: V_BAT channel disabled
name: Disabled
value: 0
- description: V_BAT channel enabled
name: Enabled
value: 1
fieldset/CCR: fieldset/CCR:
description: ADC common control register description: ADC common control register
fields: fields:
- bit_offset: 0 - name: MULTI
bit_size: 5 description: Multi ADC mode selection
description: Multi ADC mode selection bit_offset: 0
enum: MULTI bit_size: 5
name: MULTI enum: MULTI
- bit_offset: 8 - name: DELAY
bit_size: 4 description: Delay between 2 sampling phases
description: Delay between 2 sampling phases bit_offset: 8
name: DELAY bit_size: 4
- bit_offset: 13 - name: DDS
bit_size: 1 description: DMA disable selection for multi-ADC mode
description: DMA disable selection for multi-ADC mode bit_offset: 13
enum: DDS bit_size: 1
name: DDS enum: DDS
- bit_offset: 14 - name: DMA
bit_size: 2 description: Direct memory access mode for multi ADC mode
description: Direct memory access mode for multi ADC mode bit_offset: 14
enum: DMA bit_size: 2
name: DMA enum: DMA
- bit_offset: 16 - name: ADCPRE
bit_size: 2 description: ADC prescaler
description: ADC prescaler bit_offset: 16
enum: ADCPRE bit_size: 2
name: ADCPRE enum: ADCPRE
- bit_offset: 22 - name: VBATE
bit_size: 1 description: VBAT enable
description: VBAT enable bit_offset: 22
enum: VBATE bit_size: 1
name: VBATE enum: VBATE
- bit_offset: 23 - name: TSVREFE
bit_size: 1 description: Temperature sensor and VREFINT enable
description: Temperature sensor and VREFINT enable bit_offset: 23
enum: TSVREFE bit_size: 1
name: TSVREFE enum: TSVREFE
fieldset/CDR: fieldset/CDR:
description: ADC common regular data register for dual and triple modes description: ADC common regular data register for dual and triple modes
fields: fields:
- array: - name: DATA
len: 2 description: 1st data item of a pair of regular conversions
stride: 16 bit_offset: 0
bit_offset: 0 bit_size: 16
bit_size: 16 array:
description: 1st data item of a pair of regular conversions len: 2
name: DATA stride: 16
fieldset/CSR: fieldset/CSR:
description: ADC common status register description: ADC common status register
fields: fields:
- array: - name: AWD
len: 3 description: Analog watchdog flag of ADC 1
stride: 8 bit_offset: 0
bit_offset: 0 bit_size: 1
bit_size: 1 array:
description: Analog watchdog flag of ADC 1 len: 3
enum: AWD stride: 8
name: AWD enum: AWD
- array: - name: EOC
len: 3 description: End of conversion of ADC 1
stride: 8 bit_offset: 1
bit_offset: 1 bit_size: 1
bit_size: 1 array:
description: End of conversion of ADC 1 len: 3
enum: EOC stride: 8
name: EOC enum: EOC
- array: - name: JEOC
len: 3 description: Injected channel end of conversion of ADC 1
stride: 8 bit_offset: 2
bit_offset: 2 bit_size: 1
bit_size: 1 array:
description: Injected channel end of conversion of ADC 1 len: 3
enum: JEOC stride: 8
name: JEOC enum: JEOC
- array: - name: JSTRT
len: 3 description: Injected channel Start flag of ADC 1
stride: 8 bit_offset: 3
bit_offset: 3 bit_size: 1
bit_size: 1 array:
description: Injected channel Start flag of ADC 1 len: 3
enum: JSTRT stride: 8
name: JSTRT enum: JSTRT
- array: - name: STRT
len: 3 description: Regular channel Start flag of ADC 1
stride: 8 bit_offset: 4
bit_offset: 4 bit_size: 1
bit_size: 1 array:
description: Regular channel Start flag of ADC 1 len: 3
enum: STRT stride: 8
name: STRT enum: STRT
- array: - name: OVR
len: 3 description: Overrun flag of ADC 1
stride: 8 bit_offset: 5
bit_offset: 5 bit_size: 1
bit_size: 1 array:
description: Overrun flag of ADC 1 len: 3
enum: OVR stride: 8
name: OVR enum: OVR
enum/ADCPRE:
bit_size: 2
variants:
- name: Div2
description: PCLK2 divided by 2
value: 0
- name: Div4
description: PCLK2 divided by 4
value: 1
- name: Div6
description: PCLK2 divided by 6
value: 2
- name: Div8
description: PCLK2 divided by 8
value: 3
enum/AWD:
bit_size: 1
variants:
- name: NoEvent
description: No analog watchdog event occurred
value: 0
- name: Event
description: Analog watchdog event occurred
value: 1
enum/DDS:
bit_size: 1
variants:
- name: Single
description: No new DMA request is issued after the last transfer
value: 0
- name: Continuous
description: "DMA requests are issued as long as data are converted and DMA=01, 10 or 11"
value: 1
enum/DMA:
bit_size: 2
variants:
- name: Disabled
description: DMA mode disabled
value: 0
- name: Mode1
description: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
value: 1
- name: Mode2
description: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
value: 2
- name: Mode3
description: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
value: 3
enum/EOC:
bit_size: 1
variants:
- name: NotComplete
description: Conversion is not complete
value: 0
- name: Complete
description: Conversion complete
value: 1
enum/JEOC:
bit_size: 1
variants:
- name: NotComplete
description: Conversion is not complete
value: 0
- name: Complete
description: Conversion complete
value: 1
enum/JSTRT:
bit_size: 1
variants:
- name: NotStarted
description: No injected channel conversion started
value: 0
- name: Started
description: Injected channel conversion has started
value: 1
enum/MULTI:
bit_size: 5
variants:
- name: Independent
description: "All the ADCs independent: independent mode"
value: 0
- name: DualRJ
description: "Dual ADC1 and ADC2, combined regular and injected simultaneous mode"
value: 1
- name: DualRA
description: "Dual ADC1 and ADC2, combined regular and alternate trigger mode"
value: 2
- name: DualJ
description: "Dual ADC1 and ADC2, injected simultaneous mode only"
value: 5
- name: DualR
description: "Dual ADC1 and ADC2, regular simultaneous mode only"
value: 6
- name: DualI
description: "Dual ADC1 and ADC2, interleaved mode only"
value: 7
- name: DualA
description: "Dual ADC1 and ADC2, alternate trigger mode only"
value: 9
- name: TripleRJ
description: "Triple ADC, regular and injected simultaneous mode"
value: 17
- name: TripleRA
description: "Triple ADC, regular and alternate trigger mode"
value: 18
- name: TripleJ
description: "Triple ADC, injected simultaneous mode only"
value: 21
- name: TripleR
description: "Triple ADC, regular simultaneous mode only"
value: 22
- name: TripleI
description: "Triple ADC, interleaved mode only"
value: 23
- name: TripleA
description: "Triple ADC, alternate trigger mode only"
value: 24
enum/OVR:
bit_size: 1
variants:
- name: NoOverrun
description: No overrun occurred
value: 0
- name: Overrun
description: Overrun occurred
value: 1
enum/STRT:
bit_size: 1
variants:
- name: NotStarted
description: No regular channel conversion started
value: 0
- name: Started
description: Regular channel conversion has started
value: 1
enum/TSVREFE:
bit_size: 1
variants:
- name: Disabled
description: Temperature sensor and V_REFINT channel disabled
value: 0
- name: Enabled
description: Temperature sensor and V_REFINT channel enabled
value: 1
enum/VBATE:
bit_size: 1
variants:
- name: Disabled
description: V_BAT channel disabled
value: 0
- name: Enabled
description: V_BAT channel enabled
value: 1

381
data/registers/afio_f1.yaml
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@ -1,205 +1,206 @@
---
block/AFIO: block/AFIO:
description: Alternate function I/O description: Alternate function I/O
items: items:
- byte_offset: 0 - name: EVCR
description: Event Control Register (AFIO_EVCR) description: Event Control Register (AFIO_EVCR)
fieldset: EVCR byte_offset: 0
name: EVCR fieldset: EVCR
- byte_offset: 4 - name: MAPR
description: AF remap and debug I/O configuration register (AFIO_MAPR) description: AF remap and debug I/O configuration register (AFIO_MAPR)
fieldset: MAPR byte_offset: 4
name: MAPR fieldset: MAPR
- array: - name: EXTICR
len: 4 description: External interrupt configuration register 1 (AFIO_EXTICR1)
stride: 4 array:
byte_offset: 8 len: 4
description: External interrupt configuration register 1 (AFIO_EXTICR1) stride: 4
fieldset: EXTICR byte_offset: 8
name: EXTICR fieldset: EXTICR
- byte_offset: 28 - name: MAPR2
description: AF remap and debug I/O configuration register description: AF remap and debug I/O configuration register
fieldset: MAPR2 byte_offset: 28
name: MAPR2 fieldset: MAPR2
fieldset/EVCR: fieldset/EVCR:
description: Event Control Register (AFIO_EVCR) description: Event Control Register (AFIO_EVCR)
fields: fields:
- bit_offset: 0 - name: PIN
bit_size: 4 description: Pin selection
description: Pin selection bit_offset: 0
name: PIN bit_size: 4
- bit_offset: 4 - name: PORT
bit_size: 3 description: Port selection
description: Port selection bit_offset: 4
name: PORT bit_size: 3
- bit_offset: 7 - name: EVOE
bit_size: 1 description: Event Output Enable
description: Event Output Enable bit_offset: 7
name: EVOE bit_size: 1
fieldset/EXTICR: fieldset/EXTICR:
description: External interrupt configuration register 3 (AFIO_EXTICR3) description: External interrupt configuration register 3 (AFIO_EXTICR3)
fields: fields:
- array: - name: EXTI
len: 4 description: EXTI12 configuration
stride: 4 bit_offset: 0
bit_offset: 0 bit_size: 4
bit_size: 4 array:
description: EXTI12 configuration len: 4
name: EXTI stride: 4
fieldset/MAPR: fieldset/MAPR:
description: AF remap and debug I/O configuration register (AFIO_MAPR) description: AF remap and debug I/O configuration register (AFIO_MAPR)
fields: fields:
- bit_offset: 0 - name: SPI1_REMAP
bit_size: 1 description: SPI1 remapping
description: SPI1 remapping bit_offset: 0
name: SPI1_REMAP bit_size: 1
- bit_offset: 1 - name: I2C1_REMAP
bit_size: 1 description: I2C1 remapping
description: I2C1 remapping bit_offset: 1
name: I2C1_REMAP bit_size: 1
- bit_offset: 2 - name: USART1_REMAP
bit_size: 1 description: USART1 remapping
description: USART1 remapping bit_offset: 2
name: USART1_REMAP bit_size: 1
- bit_offset: 3 - name: USART2_REMAP
bit_size: 1 description: USART2 remapping
description: USART2 remapping bit_offset: 3
name: USART2_REMAP bit_size: 1
- bit_offset: 4 - name: USART3_REMAP
bit_size: 2 description: USART3 remapping
description: USART3 remapping bit_offset: 4
name: USART3_REMAP bit_size: 2
- bit_offset: 6 - name: TIM1_REMAP
bit_size: 2 description: TIM1 remapping
description: TIM1 remapping bit_offset: 6
name: TIM1_REMAP bit_size: 2
- bit_offset: 8 - name: TIM2_REMAP
bit_size: 2 description: TIM2 remapping
description: TIM2 remapping bit_offset: 8
name: TIM2_REMAP bit_size: 2
- bit_offset: 10 - name: TIM3_REMAP
bit_size: 2 description: TIM3 remapping
description: TIM3 remapping bit_offset: 10
name: TIM3_REMAP bit_size: 2
- bit_offset: 12 - name: TIM4_REMAP
bit_size: 1 description: TIM4 remapping
description: TIM4 remapping bit_offset: 12
name: TIM4_REMAP bit_size: 1
- bit_offset: 13 - name: CAN_REMAP
bit_size: 2 description: CAN1 remapping
description: CAN1 remapping bit_offset: 13
name: CAN_REMAP bit_size: 2
- bit_offset: 13 - name: CAN1_REMAP
bit_size: 2 description: CAN1 remapping
description: CAN1 remapping bit_offset: 13
name: CAN1_REMAP bit_size: 2
- bit_offset: 15 - name: PD01_REMAP
bit_size: 1 description: Port D0/Port D1 mapping on OSCIN/OSCOUT
description: Port D0/Port D1 mapping on OSCIN/OSCOUT bit_offset: 15
name: PD01_REMAP bit_size: 1
- bit_offset: 16 - name: TIM5CH4_IREMAP
bit_size: 1 description: Set and cleared by software
description: Set and cleared by software bit_offset: 16
name: TIM5CH4_IREMAP bit_size: 1
- bit_offset: 17 - name: ADC1_ETRGINJ_REMAP
bit_size: 1 description: ADC 1 External trigger injected conversion remapping
description: ADC 1 External trigger injected conversion remapping bit_offset: 17
name: ADC1_ETRGINJ_REMAP bit_size: 1
- bit_offset: 18 - name: ADC1_ETRGREG_REMAP
bit_size: 1 description: ADC 1 external trigger regular conversion remapping
description: ADC 1 external trigger regular conversion remapping bit_offset: 18
name: ADC1_ETRGREG_REMAP bit_size: 1
- bit_offset: 19 - name: ADC2_ETRGINJ_REMAP
bit_size: 1 description: ADC 2 external trigger injected conversion remapping
description: ADC 2 external trigger injected conversion remapping bit_offset: 19
name: ADC2_ETRGINJ_REMAP bit_size: 1
- bit_offset: 20 - name: ADC2_ETRGREG_REMAP
bit_size: 1 description: ADC 2 external trigger regular conversion remapping
description: ADC 2 external trigger regular conversion remapping bit_offset: 20
name: ADC2_ETRGREG_REMAP bit_size: 1
- bit_offset: 21 - name: ETH_REMAP
bit_size: 1 description: Ethernet MAC I/O remapping
description: Ethernet MAC I/O remapping bit_offset: 21
name: ETH_REMAP bit_size: 1
- bit_offset: 22 - name: CAN2_REMAP
bit_size: 1 description: CAN2 I/O remapping
description: CAN2 I/O remapping bit_offset: 22
name: CAN2_REMAP bit_size: 1
- bit_offset: 23 - name: MII_RMII_SEL
bit_size: 1 description: MII or RMII selection
description: MII or RMII selection bit_offset: 23
name: MII_RMII_SEL bit_size: 1
- bit_offset: 24 - name: SWJ_CFG
bit_size: 3 description: Serial wire JTAG configuration
description: Serial wire JTAG configuration bit_offset: 24
name: SWJ_CFG bit_size: 3
- bit_offset: 28 - name: SPI3_REMAP
bit_size: 1 description: SPI3/I2S3 remapping
description: SPI3/I2S3 remapping bit_offset: 28
name: SPI3_REMAP bit_size: 1
- bit_offset: 29 - name: TIM2ITR1_IREMAP
bit_size: 1 description: TIM2 internal trigger 1 remapping
description: TIM2 internal trigger 1 remapping bit_offset: 29
name: TIM2ITR1_IREMAP bit_size: 1
- bit_offset: 30 - name: PTP_PPS_REMAP
bit_size: 1 description: Ethernet PTP PPS remapping
description: Ethernet PTP PPS remapping bit_offset: 30
name: PTP_PPS_REMAP bit_size: 1
fieldset/MAPR2: fieldset/MAPR2:
description: AF remap and debug I/O configuration register description: AF remap and debug I/O configuration register
fields: fields:
- bit_offset: 0 - name: TIM15_REMAP
bit_size: 1 description: TIM15 remapping
description: TIM15 remapping bit_offset: 0
name: TIM15_REMAP bit_size: 1
- bit_offset: 1 - name: TIM16_REMAP
bit_size: 1 description: TIM16 remapping
description: TIM16 remapping bit_offset: 1
name: TIM16_REMAP bit_size: 1
- bit_offset: 2 - name: TIM17_REMAP
bit_size: 1 description: TIM17 remapping
description: TIM17 remapping bit_offset: 2
name: TIM17_REMAP bit_size: 1
- bit_offset: 3 - name: CEC_REMAP
bit_size: 1 description: CEC remapping
description: CEC remapping bit_offset: 3
name: CEC_REMAP bit_size: 1
- bit_offset: 4 - name: TIM1_DMA_REMAP
bit_size: 1 description: TIM1 DMA remapping
description: TIM1 DMA remapping bit_offset: 4
name: TIM1_DMA_REMAP bit_size: 1
- bit_offset: 5 - name: TIM9_REMAP
bit_size: 1 description: TIM9 remapping
description: TIM9 remapping bit_offset: 5
name: TIM9_REMAP bit_size: 1
- bit_offset: 6 - name: TIM10_REMAP
bit_size: 1 description: TIM10 remapping
description: TIM10 remapping bit_offset: 6
name: TIM10_REMAP bit_size: 1
- bit_offset: 7 - name: TIM11_REMAP
bit_size: 1 description: TIM11 remapping
description: TIM11 remapping bit_offset: 7
name: TIM11_REMAP bit_size: 1
- bit_offset: 8 - name: TIM13_REMAP
bit_size: 1 description: TIM13 remapping
description: TIM13 remapping bit_offset: 8
name: TIM13_REMAP bit_size: 1
- bit_offset: 9 - name: TIM14_REMAP
bit_size: 1 description: TIM14 remapping
description: TIM14 remapping bit_offset: 9
name: TIM14_REMAP bit_size: 1
- bit_offset: 10 - name: FSMC_NADV
bit_size: 1 description: NADV connect/disconnect
description: NADV connect/disconnect bit_offset: 10
name: FSMC_NADV bit_size: 1
- bit_offset: 11 - name: TIM67_DAC_DMA_REMAP
bit_size: 1 description: TIM67_DAC DMA remapping
description: TIM67_DAC DMA remapping bit_offset: 11
name: TIM67_DAC_DMA_REMAP bit_size: 1
- bit_offset: 12 - name: TIM12_REMAP
bit_size: 1 description: TIM12 remapping
description: TIM12 remapping bit_offset: 12
name: TIM12_REMAP bit_size: 1
- bit_offset: 13 - name: MISC_REMAP
bit_size: 1 description: Miscellaneous features remapping
description: Miscellaneous features remapping bit_offset: 13
name: MISC_REMAP bit_size: 1

58
data/registers/bdma_v1.yaml
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@ -1,17 +1,32 @@
--- ---
block/CH:
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
items:
- name: CR
description: DMA channel configuration register (DMA_CCR)
byte_offset: 0
fieldset: CR
- name: NDTR
description: DMA channel 1 number of data register
byte_offset: 4
fieldset: NDTR
- name: PAR
description: DMA channel 1 peripheral address register
byte_offset: 8
- name: MAR
description: DMA channel 1 memory address register
byte_offset: 12
block/DMA: block/DMA:
description: DMA controller description: DMA controller
items: items:
- name: ISR - name: ISR
description: DMA interrupt status register (DMA_ISR) description: DMA interrupt status register (DMA_ISR)
byte_offset: 0 byte_offset: 0
reset_value: 0
access: Read access: Read
fieldset: ISR fieldset: ISR
- name: IFCR - name: IFCR
description: DMA interrupt flag clear register (DMA_IFCR) description: DMA interrupt flag clear register (DMA_IFCR)
byte_offset: 4 byte_offset: 4
reset_value: 0
access: Write access: Write
fieldset: ISR fieldset: ISR
- name: CH - name: CH
@ -21,27 +36,6 @@ block/DMA:
stride: 20 stride: 20
byte_offset: 8 byte_offset: 8
block: CH block: CH
block/CH:
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
items:
- name: CR
description: DMA channel configuration register (DMA_CCR)
byte_offset: 0
reset_value: 0
fieldset: CR
- name: NDTR
description: DMA channel 1 number of data register
byte_offset: 4
reset_value: 0
fieldset: NDTR
- name: PAR
description: DMA channel 1 peripheral address register
byte_offset: 8
reset_value: 0
- name: MAR
description: DMA channel 1 memory address register
byte_offset: 12
reset_value: 0
fieldset/CR: fieldset/CR:
description: DMA channel configuration register (DMA_CCR) description: DMA channel configuration register (DMA_CCR)
fields: fields:
@ -157,15 +151,6 @@ enum/DIR:
- name: FromMemory - name: FromMemory
description: Read from memory description: Read from memory
value: 1 value: 1
enum/MEMMEM:
bit_size: 1
variants:
- name: Disabled
description: Memory to memory mode disabled
value: 0
- name: Enabled
description: Memory to memory mode enabled
value: 1
enum/INC: enum/INC:
bit_size: 1 bit_size: 1
variants: variants:
@ -175,6 +160,15 @@ enum/INC:
- name: Enabled - name: Enabled
description: Increment mode enabled description: Increment mode enabled
value: 1 value: 1
enum/MEMMEM:
bit_size: 1
variants:
- name: Disabled
description: Memory to memory mode disabled
value: 0
- name: Enabled
description: Memory to memory mode enabled
value: 1
enum/PL: enum/PL:
bit_size: 2 bit_size: 2
variants: variants:

58
data/registers/bdma_v2.yaml
View File

@ -1,17 +1,32 @@
--- ---
block/CH:
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
items:
- name: CR
description: DMA channel configuration register (DMA_CCR)
byte_offset: 0
fieldset: CR
- name: NDTR
description: DMA channel 1 number of data register
byte_offset: 4
fieldset: NDTR
- name: PAR
description: DMA channel 1 peripheral address register
byte_offset: 8
- name: MAR
description: DMA channel 1 memory address register
byte_offset: 12
block/DMA: block/DMA:
description: DMA controller description: DMA controller
items: items:
- name: ISR - name: ISR
description: DMA interrupt status register (DMA_ISR) description: DMA interrupt status register (DMA_ISR)
byte_offset: 0 byte_offset: 0
reset_value: 0
access: Read access: Read
fieldset: ISR fieldset: ISR
- name: IFCR - name: IFCR
description: DMA interrupt flag clear register (DMA_IFCR) description: DMA interrupt flag clear register (DMA_IFCR)
byte_offset: 4 byte_offset: 4
reset_value: 0
access: Write access: Write
fieldset: ISR fieldset: ISR
- name: CH - name: CH
@ -25,27 +40,6 @@ block/DMA:
description: channel selection register description: channel selection register
byte_offset: 168 byte_offset: 168
fieldset: CSELR fieldset: CSELR
block/CH:
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
items:
- name: CR
description: DMA channel configuration register (DMA_CCR)
byte_offset: 0
reset_value: 0
fieldset: CR
- name: NDTR
description: DMA channel 1 number of data register
byte_offset: 4
reset_value: 0
fieldset: NDTR
- name: PAR
description: DMA channel 1 peripheral address register
byte_offset: 8
reset_value: 0
- name: MAR
description: DMA channel 1 memory address register
byte_offset: 12
reset_value: 0
fieldset/CR: fieldset/CR:
description: DMA channel configuration register (DMA_CCR) description: DMA channel configuration register (DMA_CCR)
fields: fields:
@ -171,15 +165,6 @@ enum/DIR:
- name: FromMemory - name: FromMemory
description: Read from memory description: Read from memory
value: 1 value: 1
enum/MEMMEM:
bit_size: 1
variants:
- name: Disabled
description: Memory to memory mode disabled
value: 0
- name: Enabled
description: Memory to memory mode enabled
value: 1
enum/INC: enum/INC:
bit_size: 1 bit_size: 1
variants: variants:
@ -189,6 +174,15 @@ enum/INC:
- name: Enabled - name: Enabled
description: Increment mode enabled description: Increment mode enabled
value: 1 value: 1
enum/MEMMEM:
bit_size: 1
variants:
- name: Disabled
description: Memory to memory mode disabled
value: 0
- name: Enabled
description: Memory to memory mode enabled
value: 1
enum/PL: enum/PL:
bit_size: 2 bit_size: 2
variants: variants:

1481
data/registers/can_bxcan.yaml
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File diff suppressed because it is too large Load Diff

640
data/registers/dac_v1.yaml
View File

@ -2,365 +2,365 @@
block/DAC: block/DAC:
description: Digital-to-analog converter description: Digital-to-analog converter
items: items:
- byte_offset: 0 - name: CR
description: control register description: control register
fieldset: CR byte_offset: 0
name: CR fieldset: CR
- access: Write - name: SWTRIGR
byte_offset: 4 description: software trigger register
description: software trigger register byte_offset: 4
fieldset: SWTRIGR access: Write
name: SWTRIGR fieldset: SWTRIGR
- byte_offset: 8 - name: DHR12R1
description: channel1 12-bit right-aligned data holding register description: channel1 12-bit right-aligned data holding register
fieldset: DHR12R1 byte_offset: 8
name: DHR12R1 fieldset: DHR12R1
- byte_offset: 12 - name: DHR12L1
description: channel1 12-bit left aligned data holding register description: channel1 12-bit left aligned data holding register
fieldset: DHR12L1 byte_offset: 12
name: DHR12L1 fieldset: DHR12L1
- byte_offset: 16 - name: DHR8R1
description: channel1 8-bit right aligned data holding register description: channel1 8-bit right aligned data holding register
fieldset: DHR8R1 byte_offset: 16
name: DHR8R1 fieldset: DHR8R1
- byte_offset: 20 - name: DHR12R2
description: channel2 12-bit right aligned data holding register description: channel2 12-bit right aligned data holding register
fieldset: DHR12R2 byte_offset: 20
name: DHR12R2 fieldset: DHR12R2
- byte_offset: 24 - name: DHR12L2
description: channel2 12-bit left aligned data holding register description: channel2 12-bit left aligned data holding register
fieldset: DHR12L2 byte_offset: 24
name: DHR12L2 fieldset: DHR12L2
- byte_offset: 28 - name: DHR8R2
description: channel2 8-bit right-aligned data holding register description: channel2 8-bit right-aligned data holding register
fieldset: DHR8R2 byte_offset: 28
name: DHR8R2 fieldset: DHR8R2
- byte_offset: 32 - name: DHR12RD
description: Dual DAC 12-bit right-aligned data holding register description: Dual DAC 12-bit right-aligned data holding register
fieldset: DHR12RD byte_offset: 32
name: DHR12RD fieldset: DHR12RD
- byte_offset: 36 - name: DHR12LD
description: DUAL DAC 12-bit left aligned data holding register description: DUAL DAC 12-bit left aligned data holding register
fieldset: DHR12LD byte_offset: 36
name: DHR12LD fieldset: DHR12LD
- byte_offset: 40 - name: DHR8RD
description: DUAL DAC 8-bit right aligned data holding register description: DUAL DAC 8-bit right aligned data holding register
fieldset: DHR8RD byte_offset: 40
name: DHR8RD fieldset: DHR8RD
- access: Read - name: DOR1
byte_offset: 44 description: channel1 data output register
description: channel1 data output register byte_offset: 44
fieldset: DOR1 access: Read
name: DOR1 fieldset: DOR1
- access: Read - name: DOR2
byte_offset: 48 description: channel2 data output register
description: channel2 data output register byte_offset: 48
fieldset: DOR2 access: Read
name: DOR2 fieldset: DOR2
- byte_offset: 52 - name: SR
description: status register description: status register
fieldset: SR byte_offset: 52
name: SR fieldset: SR
enum/BOFF:
bit_size: 1
variants:
- description: DAC channel X output buffer enabled
name: Enabled
value: 0
- description: DAC channel X output buffer disabled
name: Disabled
value: 1
enum/DMAEN:
bit_size: 1
variants:
- description: DAC channel X DMA mode disabled
name: Disabled
value: 0
- description: DAC channel X DMA mode enabled
name: Enabled
value: 1
enum/DMAUDR:
bit_size: 1
variants:
- description: No DMA underrun error condition occurred for DAC channel X
name: NoUnderrun
value: 0
- description: DMA underrun error condition occurred for DAC channel X
name: Underrun
value: 1
enum/DMAUDRIE:
bit_size: 1
variants:
- description: DAC channel X DMA Underrun Interrupt disabled
name: Disabled
value: 0
- description: DAC channel X DMA Underrun Interrupt enabled
name: Enabled
value: 1
enum/EN:
bit_size: 1
variants:
- description: DAC channel X disabled
name: Disabled
value: 0
- description: DAC channel X enabled
name: Enabled
value: 1
enum/SWTRIG:
bit_size: 1
variants:
- description: DAC channel X software trigger disabled
name: Disabled
value: 0
- description: DAC channel X software trigger enabled
name: Enabled
value: 1
enum/TEN:
bit_size: 1
variants:
- description: DAC channel X trigger disabled
name: Disabled
value: 0
- description: DAC channel X trigger enabled
name: Enabled
value: 1
enum/TSEL1:
bit_size: 3
variants:
- description: Timer 6 TRGO event
name: TIM6_TRGO
value: 0
- description: Timer 3 TRGO event
name: TIM3_TRGO
value: 1
- description: Timer 7 TRGO event
name: TIM7_TRGO
value: 2
- description: Timer 15 TRGO event
name: TIM15_TRGO
value: 3
- description: Timer 2 TRGO event
name: TIM2_TRGO
value: 4
- description: EXTI line9
name: EXTI9
value: 6
- description: Software trigger
name: SOFTWARE
value: 7
enum/TSEL2:
bit_size: 3
variants:
- description: Timer 6 TRGO event
name: TIM6_TRGO
value: 0
- description: Timer 8 TRGO event
name: TIM8_TRGO
value: 1
- description: Timer 7 TRGO event
name: TIM7_TRGO
value: 2
- description: Timer 5 TRGO event
name: TIM5_TRGO
value: 3
- description: Timer 2 TRGO event
name: TIM2_TRGO
value: 4
- description: Timer 4 TRGO event
name: TIM4_TRGO
value: 5
- description: EXTI line9
name: EXTI9
value: 6
- description: Software trigger
name: SOFTWARE
value: 7
enum/WAVE:
bit_size: 2
variants:
- description: Wave generation disabled
name: Disabled
value: 0
- description: Noise wave generation enabled
name: Noise
value: 1
- description: Triangle wave generation enabled
name: Triangle
value: 2
fieldset/CR: fieldset/CR:
description: control register description: control register
fields: fields:
- array: - name: EN
len: 2 description: DAC channel1 enable
stride: 16 bit_offset: 0
bit_offset: 0 bit_size: 1
bit_size: 1 array:
description: DAC channel1 enable len: 2
enum: EN stride: 16
name: EN enum: EN
- array: - name: BOFF
len: 2 description: DAC channel1 output buffer disable
stride: 16 bit_offset: 1
bit_offset: 1 bit_size: 1
bit_size: 1 array:
description: DAC channel1 output buffer disable len: 2
enum: BOFF stride: 16
name: BOFF enum: BOFF
- array: - name: TEN
len: 2 description: DAC channel1 trigger enable
stride: 16 bit_offset: 2
bit_offset: 2 bit_size: 1
bit_size: 1 array:
description: DAC channel1 trigger enable len: 2
enum: TEN stride: 16
name: TEN enum: TEN
- array: - name: TSEL
len: 2 description: DAC channel1 trigger selection
stride: 16 bit_offset: 3
bit_offset: 3 bit_size: 3
bit_size: 3 array:
description: DAC channel1 trigger selection len: 2
enum: TSEL1 stride: 16
name: TSEL enum: TSEL1
- array: - name: WAVE
len: 2 description: DAC channel1 noise/triangle wave generation enable
stride: 16 bit_offset: 6
bit_offset: 6 bit_size: 2
bit_size: 2 array:
description: DAC channel1 noise/triangle wave generation enable len: 2
enum: WAVE stride: 16
name: WAVE enum: WAVE
- array: - name: MAMP
len: 2 description: DAC channel1 mask/amplitude selector
stride: 16 bit_offset: 8
bit_offset: 8 bit_size: 4
bit_size: 4 array:
description: DAC channel1 mask/amplitude selector len: 2
name: MAMP stride: 16
- array: - name: DMAEN
len: 2 description: DAC channel1 DMA enable
stride: 16 bit_offset: 12
bit_offset: 12 bit_size: 1
bit_size: 1 array:
description: DAC channel1 DMA enable len: 2
enum: DMAEN stride: 16
name: DMAEN enum: DMAEN
- array: - name: DMAUDRIE
len: 2 description: DAC channel1 DMA Underrun Interrupt enable
stride: 16 bit_offset: 13
bit_offset: 13 bit_size: 1
bit_size: 1 array:
description: DAC channel1 DMA Underrun Interrupt enable len: 2
enum: DMAUDRIE stride: 16
name: DMAUDRIE enum: DMAUDRIE
fieldset/DHR12L1: fieldset/DHR12L1:
description: channel1 12-bit left aligned data holding register description: channel1 12-bit left aligned data holding register
fields: fields:
- bit_offset: 4 - name: DACC1DHR
bit_size: 12 description: DAC channel1 12-bit left-aligned data
description: DAC channel1 12-bit left-aligned data bit_offset: 4
name: DACC1DHR bit_size: 12
fieldset/DHR12L2: fieldset/DHR12L2:
description: channel2 12-bit left aligned data holding register description: channel2 12-bit left aligned data holding register
fields: fields:
- bit_offset: 4 - name: DACC2DHR
bit_size: 12 description: DAC channel2 12-bit left-aligned data
description: DAC channel2 12-bit left-aligned data bit_offset: 4
name: DACC2DHR bit_size: 12
fieldset/DHR12LD: fieldset/DHR12LD:
description: DUAL DAC 12-bit left aligned data holding register description: DUAL DAC 12-bit left aligned data holding register
fields: fields:
- bit_offset: 4 - name: DACC1DHR
bit_size: 12 description: DAC channel1 12-bit left-aligned data
description: DAC channel1 12-bit left-aligned data bit_offset: 4
name: DACC1DHR bit_size: 12
- bit_offset: 20 - name: DACC2DHR
bit_size: 12 description: DAC channel2 12-bit left-aligned data
description: DAC channel2 12-bit left-aligned data bit_offset: 20
name: DACC2DHR bit_size: 12
fieldset/DHR12R1: fieldset/DHR12R1:
description: channel1 12-bit right-aligned data holding register description: channel1 12-bit right-aligned data holding register
fields: fields:
- bit_offset: 0 - name: DACC1DHR
bit_size: 12 description: DAC channel1 12-bit right-aligned data
description: DAC channel1 12-bit right-aligned data bit_offset: 0
name: DACC1DHR bit_size: 12
fieldset/DHR12R2: fieldset/DHR12R2:
description: channel2 12-bit right aligned data holding register description: channel2 12-bit right aligned data holding register
fields: fields:
- bit_offset: 0 - name: DACC2DHR
bit_size: 12 description: DAC channel2 12-bit right-aligned data
description: DAC channel2 12-bit right-aligned data bit_offset: 0
name: DACC2DHR bit_size: 12
fieldset/DHR12RD: fieldset/DHR12RD:
description: Dual DAC 12-bit right-aligned data holding register description: Dual DAC 12-bit right-aligned data holding register
fields: fields:
- bit_offset: 0 - name: DACC1DHR
bit_size: 12 description: DAC channel1 12-bit right-aligned data
description: DAC channel1 12-bit right-aligned data bit_offset: 0
name: DACC1DHR bit_size: 12
- bit_offset: 16 - name: DACC2DHR
bit_size: 12 description: DAC channel2 12-bit right-aligned data
description: DAC channel2 12-bit right-aligned data bit_offset: 16
name: DACC2DHR bit_size: 12
fieldset/DHR8R1: fieldset/DHR8R1:
description: channel1 8-bit right aligned data holding register description: channel1 8-bit right aligned data holding register
fields: fields:
- bit_offset: 0 - name: DACC1DHR
bit_size: 8 description: DAC channel1 8-bit right-aligned data
description: DAC channel1 8-bit right-aligned data bit_offset: 0
name: DACC1DHR bit_size: 8
fieldset/DHR8R2: fieldset/DHR8R2:
description: channel2 8-bit right-aligned data holding register description: channel2 8-bit right-aligned data holding register
fields: fields:
- bit_offset: 0 - name: DACC2DHR
bit_size: 8 description: DAC channel2 8-bit right-aligned data
description: DAC channel2 8-bit right-aligned data bit_offset: 0
name: DACC2DHR bit_size: 8
fieldset/DHR8RD: fieldset/DHR8RD:
description: DUAL DAC 8-bit right aligned data holding register description: DUAL DAC 8-bit right aligned data holding register
fields: fields:
- bit_offset: 0 - name: DACC1DHR
bit_size: 8 description: DAC channel1 8-bit right-aligned data
description: DAC channel1 8-bit right-aligned data bit_offset: 0
name: DACC1DHR bit_size: 8
- bit_offset: 8 - name: DACC2DHR
bit_size: 8 description: DAC channel2 8-bit right-aligned data
description: DAC channel2 8-bit right-aligned data bit_offset: 8
name: DACC2DHR bit_size: 8
fieldset/DOR1: fieldset/DOR1:
description: channel1 data output register description: channel1 data output register
fields: fields:
- bit_offset: 0 - name: DACC1DOR
bit_size: 12 description: DAC channel1 data output
description: DAC channel1 data output bit_offset: 0
name: DACC1DOR bit_size: 12
fieldset/DOR2: fieldset/DOR2:
description: channel2 data output register description: channel2 data output register
fields: fields:
- bit_offset: 0 - name: DACC2DOR
bit_size: 12 description: DAC channel2 data output
description: DAC channel2 data output bit_offset: 0
name: DACC2DOR bit_size: 12
fieldset/SR: fieldset/SR:
description: status register description: status register
fields: fields:
- array: - name: DMAUDR
len: 2 description: DAC channel1 DMA underrun flag
stride: 16 bit_offset: 13
bit_offset: 13 bit_size: 1
bit_size: 1 array:
description: DAC channel1 DMA underrun flag len: 2
enum: DMAUDR stride: 16
name: DMAUDR enum: DMAUDR
fieldset/SWTRIGR: fieldset/SWTRIGR:
description: software trigger register description: software trigger register
fields: fields:
- array: - name: SWTRIG
len: 2 description: DAC channel1 software trigger
stride: 1 bit_offset: 0
bit_offset: 0 bit_size: 1
bit_size: 1 array:
description: DAC channel1 software trigger len: 2
enum: SWTRIG stride: 1
name: SWTRIG enum: SWTRIG
enum/BOFF:
bit_size: 1
variants:
- name: Enabled
description: DAC channel X output buffer enabled
value: 0
- name: Disabled
description: DAC channel X output buffer disabled
value: 1
enum/DMAEN:
bit_size: 1
variants:
- name: Disabled
description: DAC channel X DMA mode disabled
value: 0
- name: Enabled
description: DAC channel X DMA mode enabled
value: 1
enum/DMAUDR:
bit_size: 1
variants:
- name: NoUnderrun
description: No DMA underrun error condition occurred for DAC channel X
value: 0
- name: Underrun
description: DMA underrun error condition occurred for DAC channel X
value: 1
enum/DMAUDRIE:
bit_size: 1
variants:
- name: Disabled
description: DAC channel X DMA Underrun Interrupt disabled
value: 0
- name: Enabled
description: DAC channel X DMA Underrun Interrupt enabled
value: 1
enum/EN:
bit_size: 1
variants:
- name: Disabled
description: DAC channel X disabled
value: 0
- name: Enabled
description: DAC channel X enabled
value: 1
enum/SWTRIG:
bit_size: 1
variants:
- name: Disabled
description: DAC channel X software trigger disabled
value: 0
- name: Enabled
description: DAC channel X software trigger enabled
value: 1
enum/TEN:
bit_size: 1
variants:
- name: Disabled
description: DAC channel X trigger disabled
value: 0
- name: Enabled
description: DAC channel X trigger enabled
value: 1
enum/TSEL1:
bit_size: 3
variants:
- name: TIM6_TRGO
description: Timer 6 TRGO event
value: 0
- name: TIM3_TRGO
description: Timer 3 TRGO event
value: 1
- name: TIM7_TRGO
description: Timer 7 TRGO event
value: 2
- name: TIM15_TRGO
description: Timer 15 TRGO event
value: 3
- name: TIM2_TRGO
description: Timer 2 TRGO event
value: 4
- name: EXTI9
description: EXTI line9
value: 6
- name: SOFTWARE
description: Software trigger
value: 7
enum/TSEL2:
bit_size: 3
variants:
- name: TIM6_TRGO
description: Timer 6 TRGO event
value: 0
- name: TIM8_TRGO
description: Timer 8 TRGO event
value: 1
- name: TIM7_TRGO
description: Timer 7 TRGO event
value: 2
- name: TIM5_TRGO
description: Timer 5 TRGO event
value: 3
- name: TIM2_TRGO
description: Timer 2 TRGO event
value: 4
- name: TIM4_TRGO
description: Timer 4 TRGO event
value: 5
- name: EXTI9
description: EXTI line9
value: 6
- name: SOFTWARE
description: Software trigger
value: 7
enum/WAVE:
bit_size: 2
variants:
- name: Disabled
description: Wave generation disabled
value: 0
- name: Noise
description: Noise wave generation enabled
value: 1
- name: Triangle
description: Triangle wave generation enabled
value: 2

498
data/registers/dcmi_v1.yaml
View File

@ -2,285 +2,285 @@
block/DCMI: block/DCMI:
description: Digital camera interface description: Digital camera interface
items: items:
- byte_offset: 0 - name: CR
description: control register 1 description: control register 1
fieldset: CR byte_offset: 0
name: CR fieldset: CR
- access: Read - name: SR
byte_offset: 4 description: status register
description: status register byte_offset: 4
fieldset: SR access: Read
name: SR fieldset: SR
- access: Read - name: RIS
byte_offset: 8 description: raw interrupt status register
description: raw interrupt status register byte_offset: 8
fieldset: RIS access: Read
name: RIS fieldset: RIS
- byte_offset: 12 - name: IER
description: interrupt enable register description: interrupt enable register
fieldset: IER byte_offset: 12
name: IER fieldset: IER
- access: Read - name: MIS
byte_offset: 16 description: masked interrupt status register
description: masked interrupt status register byte_offset: 16
fieldset: MIS access: Read
name: MIS fieldset: MIS
- access: Write - name: ICR
byte_offset: 20 description: interrupt clear register
description: interrupt clear register byte_offset: 20
fieldset: ICR access: Write
name: ICR fieldset: ICR
- byte_offset: 24 - name: ESCR
description: embedded synchronization code register description: embedded synchronization code register
fieldset: ESCR byte_offset: 24
name: ESCR fieldset: ESCR
- byte_offset: 28 - name: ESUR
description: embedded synchronization unmask register description: embedded synchronization unmask register
fieldset: ESUR byte_offset: 28
name: ESUR fieldset: ESUR
- byte_offset: 32 - name: CWSTRT
description: crop window start description: crop window start
fieldset: CWSTRT byte_offset: 32
name: CWSTRT fieldset: CWSTRT
- byte_offset: 36 - name: CWSIZE
description: crop window size description: crop window size
fieldset: CWSIZE byte_offset: 36
name: CWSIZE fieldset: CWSIZE
- access: Read - name: DR
byte_offset: 40 description: data register
description: data register byte_offset: 40
fieldset: DR access: Read
name: DR fieldset: DR
fieldset/CR: fieldset/CR:
description: control register 1 description: control register 1
fields: fields:
- bit_offset: 0 - name: CAPTURE
bit_size: 1 description: Capture enable
description: Capture enable bit_offset: 0
name: CAPTURE bit_size: 1
- bit_offset: 1 - name: CM
bit_size: 1 description: Capture mode
description: Capture mode bit_offset: 1
name: CM bit_size: 1
- bit_offset: 2 - name: CROP
bit_size: 1 description: Crop feature
description: Crop feature bit_offset: 2
name: CROP bit_size: 1
- bit_offset: 3 - name: JPEG
bit_size: 1 description: JPEG format
description: JPEG format bit_offset: 3
name: JPEG bit_size: 1
- bit_offset: 4 - name: ESS
bit_size: 1 description: Embedded synchronization select
description: Embedded synchronization select bit_offset: 4
name: ESS bit_size: 1
- bit_offset: 5 - name: PCKPOL
bit_size: 1 description: Pixel clock polarity
description: Pixel clock polarity bit_offset: 5
name: PCKPOL bit_size: 1
- bit_offset: 6 - name: HSPOL
bit_size: 1 description: Horizontal synchronization polarity
description: Horizontal synchronization polarity bit_offset: 6
name: HSPOL bit_size: 1
- bit_offset: 7 - name: VSPOL
bit_size: 1 description: Vertical synchronization polarity
description: Vertical synchronization polarity bit_offset: 7
name: VSPOL bit_size: 1
- bit_offset: 8 - name: FCRC
bit_size: 2 description: Frame capture rate control
description: Frame capture rate control bit_offset: 8
name: FCRC bit_size: 2
- bit_offset: 10 - name: EDM
bit_size: 2 description: Extended data mode
description: Extended data mode bit_offset: 10
name: EDM bit_size: 2
- bit_offset: 14 - name: ENABLE
bit_size: 1 description: DCMI enable
description: DCMI enable bit_offset: 14
name: ENABLE bit_size: 1
fieldset/CWSIZE: fieldset/CWSIZE:
description: crop window size description: crop window size
fields: fields:
- bit_offset: 0 - name: CAPCNT
bit_size: 14 description: Capture count
description: Capture count bit_offset: 0
name: CAPCNT bit_size: 14
- bit_offset: 16 - name: VLINE
bit_size: 14 description: Vertical line count
description: Vertical line count bit_offset: 16
name: VLINE bit_size: 14
fieldset/CWSTRT: fieldset/CWSTRT:
description: crop window start description: crop window start
fields: fields:
- bit_offset: 0 - name: HOFFCNT
bit_size: 14 description: Horizontal offset count
description: Horizontal offset count bit_offset: 0
name: HOFFCNT bit_size: 14
- bit_offset: 16 - name: VST
bit_size: 13 description: Vertical start line count
description: Vertical start line count bit_offset: 16
name: VST bit_size: 13
fieldset/DR: fieldset/DR:
description: data register description: data register
fields: fields:
- bit_offset: 0 - name: Byte0
bit_size: 8 description: Data byte 0
description: Data byte 0 bit_offset: 0
name: Byte0 bit_size: 8
- bit_offset: 8 - name: Byte1
bit_size: 8 description: Data byte 1
description: Data byte 1 bit_offset: 8
name: Byte1 bit_size: 8
- bit_offset: 16 - name: Byte2
bit_size: 8 description: Data byte 2
description: Data byte 2 bit_offset: 16
name: Byte2 bit_size: 8
- bit_offset: 24 - name: Byte3
bit_size: 8 description: Data byte 3
description: Data byte 3 bit_offset: 24
name: Byte3 bit_size: 8
fieldset/ESCR: fieldset/ESCR:
description: embedded synchronization code register description: embedded synchronization code register
fields: fields:
- bit_offset: 0 - name: FSC
bit_size: 8 description: Frame start delimiter code
description: Frame start delimiter code bit_offset: 0
name: FSC bit_size: 8
- bit_offset: 8 - name: LSC
bit_size: 8 description: Line start delimiter code
description: Line start delimiter code bit_offset: 8
name: LSC bit_size: 8
- bit_offset: 16 - name: LEC
bit_size: 8 description: Line end delimiter code
description: Line end delimiter code bit_offset: 16
name: LEC bit_size: 8
- bit_offset: 24 - name: FEC
bit_size: 8 description: Frame end delimiter code
description: Frame end delimiter code bit_offset: 24
name: FEC bit_size: 8
fieldset/ESUR: fieldset/ESUR:
description: embedded synchronization unmask register description: embedded synchronization unmask register
fields: fields:
- bit_offset: 0 - name: FSU
bit_size: 8 description: Frame start delimiter unmask
description: Frame start delimiter unmask bit_offset: 0
name: FSU bit_size: 8
- bit_offset: 8 - name: LSU
bit_size: 8 description: Line start delimiter unmask
description: Line start delimiter unmask bit_offset: 8
name: LSU bit_size: 8
- bit_offset: 16 - name: LEU
bit_size: 8 description: Line end delimiter unmask
description: Line end delimiter unmask bit_offset: 16
name: LEU bit_size: 8
- bit_offset: 24 - name: FEU
bit_size: 8 description: Frame end delimiter unmask
description: Frame end delimiter unmask bit_offset: 24
name: FEU bit_size: 8
fieldset/ICR: fieldset/ICR:
description: interrupt clear register description: interrupt clear register
fields: fields:
- bit_offset: 0 - name: FRAME_ISC
bit_size: 1 description: Capture complete interrupt status clear
description: Capture complete interrupt status clear bit_offset: 0
name: FRAME_ISC bit_size: 1
- bit_offset: 1 - name: OVR_ISC
bit_size: 1 description: Overrun interrupt status clear
description: Overrun interrupt status clear bit_offset: 1
name: OVR_ISC bit_size: 1
- bit_offset: 2 - name: ERR_ISC
bit_size: 1 description: Synchronization error interrupt status clear
description: Synchronization error interrupt status clear bit_offset: 2
name: ERR_ISC bit_size: 1
- bit_offset: 3 - name: VSYNC_ISC
bit_size: 1 description: Vertical synch interrupt status clear
description: Vertical synch interrupt status clear bit_offset: 3
name: VSYNC_ISC bit_size: 1
- bit_offset: 4 - name: LINE_ISC
bit_size: 1 description: line interrupt status clear
description: line interrupt status clear bit_offset: 4
name: LINE_ISC bit_size: 1
fieldset/IER: fieldset/IER:
description: interrupt enable register description: interrupt enable register
fields: fields:
- bit_offset: 0 - name: FRAME_IE
bit_size: 1 description: Capture complete interrupt enable
description: Capture complete interrupt enable bit_offset: 0
name: FRAME_IE bit_size: 1
- bit_offset: 1 - name: OVR_IE
bit_size: 1 description: Overrun interrupt enable
description: Overrun interrupt enable bit_offset: 1
name: OVR_IE bit_size: 1
- bit_offset: 2 - name: ERR_IE
bit_size: 1 description: Synchronization error interrupt enable
description: Synchronization error interrupt enable bit_offset: 2
name: ERR_IE bit_size: 1
- bit_offset: 3 - name: VSYNC_IE
bit_size: 1 description: VSYNC interrupt enable
description: VSYNC interrupt enable bit_offset: 3
name: VSYNC_IE bit_size: 1
- bit_offset: 4 - name: LINE_IE
bit_size: 1 description: Line interrupt enable
description: Line interrupt enable bit_offset: 4
name: LINE_IE bit_size: 1
fieldset/MIS: fieldset/MIS:
description: masked interrupt status register description: masked interrupt status register
fields: fields:
- bit_offset: 0 - name: FRAME_MIS
bit_size: 1 description: Capture complete masked interrupt status
description: Capture complete masked interrupt status bit_offset: 0
name: FRAME_MIS bit_size: 1
- bit_offset: 1 - name: OVR_MIS
bit_size: 1 description: Overrun masked interrupt status
description: Overrun masked interrupt status bit_offset: 1
name: OVR_MIS bit_size: 1
- bit_offset: 2 - name: ERR_MIS
bit_size: 1 description: Synchronization error masked interrupt status
description: Synchronization error masked interrupt status bit_offset: 2
name: ERR_MIS bit_size: 1
- bit_offset: 3 - name: VSYNC_MIS
bit_size: 1 description: VSYNC masked interrupt status
description: VSYNC masked interrupt status bit_offset: 3
name: VSYNC_MIS bit_size: 1
- bit_offset: 4 - name: LINE_MIS
bit_size: 1 description: Line masked interrupt status
description: Line masked interrupt status bit_offset: 4
name: LINE_MIS bit_size: 1
fieldset/RIS: fieldset/RIS:
description: raw interrupt status register description: raw interrupt status register
fields: fields:
- bit_offset: 0 - name: FRAME_RIS
bit_size: 1 description: Capture complete raw interrupt status
description: Capture complete raw interrupt status bit_offset: 0
name: FRAME_RIS bit_size: 1
- bit_offset: 1 - name: OVR_RIS
bit_size: 1 description: Overrun raw interrupt status
description: Overrun raw interrupt status bit_offset: 1
name: OVR_RIS bit_size: 1
- bit_offset: 2 - name: ERR_RIS
bit_size: 1 description: Synchronization error raw interrupt status
description: Synchronization error raw interrupt status bit_offset: 2
name: ERR_RIS bit_size: 1
- bit_offset: 3 - name: VSYNC_RIS
bit_size: 1 description: VSYNC raw interrupt status
description: VSYNC raw interrupt status bit_offset: 3
name: VSYNC_RIS bit_size: 1
- bit_offset: 4 - name: LINE_RIS
bit_size: 1 description: Line raw interrupt status
description: Line raw interrupt status bit_offset: 4
name: LINE_RIS bit_size: 1
fieldset/SR: fieldset/SR:
description: status register description: status register
fields: fields:
- bit_offset: 0 - name: HSYNC
bit_size: 1 description: HSYNC
description: HSYNC bit_offset: 0
name: HSYNC bit_size: 1
- bit_offset: 1 - name: VSYNC
bit_size: 1 description: VSYNC
description: VSYNC bit_offset: 1
name: VSYNC bit_size: 1
- bit_offset: 2 - name: FNE
bit_size: 1 description: FIFO not empty
description: FIFO not empty bit_offset: 2
name: FNE bit_size: 1

1316
data/registers/dma2d_v1.yaml
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data/registers/dma2d_v2.yaml
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62
data/registers/dma_v1.yaml
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@ -8,7 +8,6 @@ block/DMA:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 0 byte_offset: 0
reset_value: 0
access: Read access: Read
fieldset: IXR fieldset: IXR
- name: IFCR - name: IFCR
@ -17,7 +16,6 @@ block/DMA:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 8 byte_offset: 8
reset_value: 0
access: Write access: Write
fieldset: IXR fieldset: IXR
- name: ST - name: ST
@ -33,29 +31,23 @@ block/ST:
- name: CR - name: CR
description: stream x configuration register description: stream x configuration register
byte_offset: 0 byte_offset: 0
reset_value: 0
fieldset: CR fieldset: CR
- name: NDTR - name: NDTR
description: stream x number of data register description: stream x number of data register
byte_offset: 4 byte_offset: 4
reset_value: 0
fieldset: NDTR fieldset: NDTR
- name: PAR - name: PAR
description: stream x peripheral address register description: stream x peripheral address register
byte_offset: 8 byte_offset: 8
reset_value: 0
- name: M0AR - name: M0AR
description: stream x memory 0 address register description: stream x memory 0 address register
byte_offset: 12 byte_offset: 12
reset_value: 0
- name: M1AR - name: M1AR
description: stream x memory 1 address register description: stream x memory 1 address register
byte_offset: 16 byte_offset: 16
reset_value: 0
- name: FCR - name: FCR
description: stream x FIFO control register description: stream x FIFO control register
byte_offset: 20 byte_offset: 20
reset_value: 33
fieldset: FCR fieldset: FCR
fieldset/CR: fieldset/CR:
description: stream x configuration register description: stream x configuration register
@ -231,6 +223,21 @@ fieldset/NDTR:
description: Number of data items to transfer description: Number of data items to transfer
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/BURST:
bit_size: 2
variants:
- name: Single
description: Single transfer
value: 0
- name: INCR4
description: Incremental burst of 4 beats
value: 1
- name: INCR8
description: Incremental burst of 8 beats
value: 2
- name: INCR16
description: Incremental burst of 16 beats
value: 3
enum/CIRC: enum/CIRC:
bit_size: 1 bit_size: 1
variants: variants:
@ -315,21 +322,6 @@ enum/FTH:
- name: Full - name: Full
description: Full FIFO description: Full FIFO
value: 3 value: 3
enum/BURST:
bit_size: 2
variants:
- name: Single
description: Single transfer
value: 0
- name: INCR4
description: Incremental burst of 4 beats
value: 1
- name: INCR8
description: Incremental burst of 8 beats
value: 2
- name: INCR16
description: Incremental burst of 16 beats
value: 3
enum/INC: enum/INC:
bit_size: 1 bit_size: 1
variants: variants:
@ -339,18 +331,6 @@ enum/INC:
- name: Incremented - name: Incremented
description: Address pointer is incremented after each data transfer description: Address pointer is incremented after each data transfer
value: 1 value: 1
enum/SIZE:
bit_size: 2
variants:
- name: Bits8
description: Byte (8-bit)
value: 0
- name: Bits16
description: Half-word (16-bit)
value: 1
- name: Bits32
description: Word (32-bit)
value: 2
enum/PFCTRL: enum/PFCTRL:
bit_size: 1 bit_size: 1
variants: variants:
@ -384,3 +364,15 @@ enum/PL:
- name: VeryHigh - name: VeryHigh
description: Very high description: Very high
value: 3 value: 3
enum/SIZE:
bit_size: 2
variants:
- name: Bits8
description: Byte (8-bit)
value: 0
- name: Bits16
description: Half-word (16-bit)
value: 1
- name: Bits32
description: Word (32-bit)
value: 2

62
data/registers/dma_v2.yaml
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@ -8,7 +8,6 @@ block/DMA:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 0 byte_offset: 0
reset_value: 0
access: Read access: Read
fieldset: IXR fieldset: IXR
- name: IFCR - name: IFCR
@ -17,7 +16,6 @@ block/DMA:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 8 byte_offset: 8
reset_value: 0
access: Write access: Write
fieldset: IXR fieldset: IXR
- name: ST - name: ST
@ -33,29 +31,23 @@ block/ST:
- name: CR - name: CR
description: stream x configuration register description: stream x configuration register
byte_offset: 0 byte_offset: 0
reset_value: 0
fieldset: CR fieldset: CR
- name: NDTR - name: NDTR
description: stream x number of data register description: stream x number of data register
byte_offset: 4 byte_offset: 4
reset_value: 0
fieldset: NDTR fieldset: NDTR
- name: PAR - name: PAR
description: stream x peripheral address register description: stream x peripheral address register
byte_offset: 8 byte_offset: 8
reset_value: 0
- name: M0AR - name: M0AR
description: stream x memory 0 address register description: stream x memory 0 address register
byte_offset: 12 byte_offset: 12
reset_value: 0
- name: M1AR - name: M1AR
description: stream x memory 1 address register description: stream x memory 1 address register
byte_offset: 16 byte_offset: 16
reset_value: 0
- name: FCR - name: FCR
description: stream x FIFO control register description: stream x FIFO control register
byte_offset: 20 byte_offset: 20
reset_value: 33
fieldset: FCR fieldset: FCR
fieldset/CR: fieldset/CR:
description: stream x configuration register description: stream x configuration register
@ -231,6 +223,21 @@ fieldset/NDTR:
description: Number of data items to transfer description: Number of data items to transfer
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/BURST:
bit_size: 2
variants:
- name: Single
description: Single transfer
value: 0
- name: INCR4
description: Incremental burst of 4 beats
value: 1
- name: INCR8
description: Incremental burst of 8 beats
value: 2
- name: INCR16
description: Incremental burst of 16 beats
value: 3
enum/CIRC: enum/CIRC:
bit_size: 1 bit_size: 1
variants: variants:
@ -315,21 +322,6 @@ enum/FTH:
- name: Full - name: Full
description: Full FIFO description: Full FIFO
value: 3 value: 3
enum/BURST:
bit_size: 2
variants:
- name: Single
description: Single transfer
value: 0
- name: INCR4
description: Incremental burst of 4 beats
value: 1
- name: INCR8
description: Incremental burst of 8 beats
value: 2
- name: INCR16
description: Incremental burst of 16 beats
value: 3
enum/INC: enum/INC:
bit_size: 1 bit_size: 1
variants: variants:
@ -339,18 +331,6 @@ enum/INC:
- name: Incremented - name: Incremented
description: Address pointer is incremented after each data transfer description: Address pointer is incremented after each data transfer
value: 1 value: 1
enum/SIZE:
bit_size: 2
variants:
- name: Bits8
description: Byte (8-bit)
value: 0
- name: Bits16
description: Half-word (16-bit)
value: 1
- name: Bits32
description: Word (32-bit)
value: 2
enum/PFCTRL: enum/PFCTRL:
bit_size: 1 bit_size: 1
variants: variants:
@ -384,3 +364,15 @@ enum/PL:
- name: VeryHigh - name: VeryHigh
description: Very high description: Very high
value: 3 value: 3
enum/SIZE:
bit_size: 2
variants:
- name: Bits8
description: Byte (8-bit)
value: 0
- name: Bits16
description: Half-word (16-bit)
value: 1
- name: Bits32
description: Word (32-bit)
value: 2

3692
data/registers/eth_v1c.yaml
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data/registers/eth_v2.yaml
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data/registers/exti_g0.yaml
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@ -48,7 +48,7 @@ block/EXTI:
description: Interrupt mask register description: Interrupt mask register
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 128 byte_offset: 128
fieldset: LINES fieldset: LINES
- name: EMR - name: EMR
@ -69,7 +69,7 @@ fieldset/EXTICR:
len: 4 len: 4
stride: 8 stride: 8
fieldset/LINES: fieldset/LINES:
description: EXTI lines register, 1 bit per line description: "EXTI lines register, 1 bit per line"
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line

2
data/registers/exti_h7.yaml
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@ -45,7 +45,7 @@ block/EXTI:
byte_offset: 136 byte_offset: 136
fieldset: LINES fieldset: LINES
fieldset/LINES: fieldset/LINES:
description: EXTI lines register, 1 bit per line description: "EXTI lines register, 1 bit per line"
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line

2
data/registers/exti_l5.yaml
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@ -87,7 +87,7 @@ fieldset/EXTICR:
len: 4 len: 4
stride: 8 stride: 8
fieldset/LINES: fieldset/LINES:
description: EXTI lines register, 1 bit per line description: "EXTI lines register, 1 bit per line"
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line

2
data/registers/exti_u5.yaml
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@ -87,7 +87,7 @@ fieldset/EXTICR:
len: 4 len: 4
stride: 8 stride: 8
fieldset/LINES: fieldset/LINES:
description: EXTI lines register, 1 bit per line description: "EXTI lines register, 1 bit per line"
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line

2
data/registers/exti_v1.yaml
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@ -45,7 +45,7 @@ block/EXTI:
byte_offset: 20 byte_offset: 20
fieldset: LINES fieldset: LINES
fieldset/LINES: fieldset/LINES:
description: EXTI lines register, 1 bit per line description: "EXTI lines register, 1 bit per line"
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line

40
data/registers/exti_w.yaml
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@ -1,4 +1,21 @@
--- ---
block/CPU:
description: CPU-specific registers
items:
- name: IMR
description: CPU x interrupt mask register
array:
len: 2
stride: 16
byte_offset: 0
fieldset: LINES
- name: EMR
description: CPU x event mask register
array:
len: 2
stride: 16
byte_offset: 4
fieldset: LINES
block/EXTI: block/EXTI:
description: External interrupt/event controller description: External interrupt/event controller
items: items:
@ -32,30 +49,13 @@ block/EXTI:
fieldset: LINES fieldset: LINES
- name: CPU - name: CPU
description: CPU specific registers description: CPU specific registers
byte_offset: 128
block: CPU
array: array:
len: 2 len: 2
stride: 64 stride: 64
block/CPU: byte_offset: 128
description: CPU-specific registers block: CPU
items:
- name: IMR
description: CPU x interrupt mask register
byte_offset: 0
fieldset: LINES
array:
len: 2
stride: 16
- name: EMR
description: CPU x event mask register
array:
len: 2
stride: 16
byte_offset: 4
fieldset: LINES
fieldset/LINES: fieldset/LINES:
description: EXTI lines register, 1 bit per line description: "EXTI lines register, 1 bit per line"
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line

2
data/registers/exti_wle.yaml
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@ -45,7 +45,7 @@ block/EXTI:
byte_offset: 132 byte_offset: 132
fieldset: LINES fieldset: LINES
fieldset/LINES: fieldset/LINES:
description: EXTI lines register, 1 bit per line description: "EXTI lines register, 1 bit per line"
fields: fields:
- name: LINE - name: LINE
description: EXTI line description: EXTI line

333
data/registers/flash_f1.yaml
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@ -1,193 +1,194 @@
---
block/FLASH: block/FLASH:
description: FLASH description: FLASH
items: items:
- byte_offset: 0 - name: ACR
description: Flash access control register description: Flash access control register
fieldset: ACR byte_offset: 0
name: ACR fieldset: ACR
- access: Write - name: KEYR
byte_offset: 4 description: Flash key register
description: Flash key register byte_offset: 4
fieldset: KEYR access: Write
name: KEYR fieldset: KEYR
- access: Write - name: OPTKEYR
byte_offset: 8 description: Flash option key register
description: Flash option key register byte_offset: 8
fieldset: OPTKEYR access: Write
name: OPTKEYR fieldset: OPTKEYR
- byte_offset: 12 - name: SR
description: Status register description: Status register
fieldset: SR byte_offset: 12
name: SR fieldset: SR
- byte_offset: 16 - name: CR
description: Control register description: Control register
fieldset: CR byte_offset: 16
name: CR fieldset: CR
- access: Write - name: AR
byte_offset: 20 description: Flash address register
description: Flash address register byte_offset: 20
fieldset: AR access: Write
name: AR fieldset: AR
- access: Read - name: OBR
byte_offset: 28 description: Option byte register
description: Option byte register byte_offset: 28
fieldset: OBR access: Read
name: OBR fieldset: OBR
- access: Read - name: WRPR
byte_offset: 32 description: Write protection register
description: Write protection register byte_offset: 32
fieldset: WRPR access: Read
name: WRPR fieldset: WRPR
enum/LATENCY:
bit_size: 3
variants:
- description: "Zero wait state, if 0 < SYSCLK\u2264 24 MHz"
name: WS0
value: 0
- description: "One wait state, if 24 MHz < SYSCLK \u2264 48 MHz"
name: WS1
value: 1
- description: "Two wait states, if 48 MHz < SYSCLK \u2264 72 MHz"
name: WS2
value: 2
fieldset/ACR: fieldset/ACR:
description: Flash access control register description: Flash access control register
fields: fields:
- bit_offset: 0 - name: LATENCY
bit_size: 3 description: Latency
description: Latency bit_offset: 0
enum: LATENCY bit_size: 3
name: LATENCY enum: LATENCY
- bit_offset: 3 - name: HLFCYA
bit_size: 1 description: Flash half cycle access enable
description: Flash half cycle access enable bit_offset: 3
name: HLFCYA bit_size: 1
- bit_offset: 4 - name: PRFTBE
bit_size: 1 description: Prefetch buffer enable
description: Prefetch buffer enable bit_offset: 4
name: PRFTBE bit_size: 1
- bit_offset: 5 - name: PRFTBS
bit_size: 1 description: Prefetch buffer status
description: Prefetch buffer status bit_offset: 5
name: PRFTBS bit_size: 1
fieldset/AR: fieldset/AR:
description: Flash address register description: Flash address register
fields: fields:
- bit_offset: 0 - name: FAR
bit_size: 32 description: Flash Address
description: Flash Address bit_offset: 0
name: FAR bit_size: 32
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
- bit_offset: 0 - name: PG
bit_size: 1 description: Programming
description: Programming bit_offset: 0
name: PG bit_size: 1
- bit_offset: 1 - name: PER
bit_size: 1 description: Page Erase
description: Page Erase bit_offset: 1
name: PER bit_size: 1
- bit_offset: 2 - name: MER
bit_size: 1 description: Mass Erase
description: Mass Erase bit_offset: 2
name: MER bit_size: 1
- bit_offset: 4 - name: OPTPG
bit_size: 1 description: Option byte programming
description: Option byte programming bit_offset: 4
name: OPTPG bit_size: 1
- bit_offset: 5 - name: OPTER
bit_size: 1 description: Option byte erase
description: Option byte erase bit_offset: 5
name: OPTER bit_size: 1
- bit_offset: 6 - name: STRT
bit_size: 1 description: Start
description: Start bit_offset: 6
name: STRT bit_size: 1
- bit_offset: 7 - name: LOCK
bit_size: 1 description: Lock
description: Lock bit_offset: 7
name: LOCK bit_size: 1
- bit_offset: 9 - name: OPTWRE
bit_size: 1 description: Option bytes write enable
description: Option bytes write enable bit_offset: 9
name: OPTWRE bit_size: 1
- bit_offset: 10 - name: ERRIE
bit_size: 1 description: Error interrupt enable
description: Error interrupt enable bit_offset: 10
name: ERRIE bit_size: 1
- bit_offset: 12 - name: EOPIE
bit_size: 1 description: End of operation interrupt enable
description: End of operation interrupt enable bit_offset: 12
name: EOPIE bit_size: 1
fieldset/KEYR: fieldset/KEYR:
description: Flash key register description: Flash key register
fields: fields:
- bit_offset: 0 - name: KEY
bit_size: 32 description: FPEC key
description: FPEC key bit_offset: 0
name: KEY bit_size: 32
fieldset/OBR: fieldset/OBR:
description: Option byte register description: Option byte register
fields: fields:
- bit_offset: 0 - name: OPTERR
bit_size: 1 description: Option byte error
description: Option byte error bit_offset: 0
name: OPTERR bit_size: 1
- bit_offset: 1 - name: RDPRT
bit_size: 1 description: Read protection
description: Read protection bit_offset: 1
name: RDPRT bit_size: 1
- bit_offset: 2 - name: WDG_SW
bit_size: 1 description: WDG_SW
description: WDG_SW bit_offset: 2
name: WDG_SW bit_size: 1
- bit_offset: 3 - name: nRST_STOP
bit_size: 1 description: nRST_STOP
description: nRST_STOP bit_offset: 3
name: nRST_STOP bit_size: 1
- bit_offset: 4 - name: nRST_STDBY
bit_size: 1 description: nRST_STDBY
description: nRST_STDBY bit_offset: 4
name: nRST_STDBY bit_size: 1
- bit_offset: 10 - name: Data0
bit_size: 8 description: Data0
description: Data0 bit_offset: 10
name: Data0 bit_size: 8
- bit_offset: 18 - name: Data1
bit_size: 8 description: Data1
description: Data1 bit_offset: 18
name: Data1 bit_size: 8
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Flash option key register description: Flash option key register
fields: fields:
- bit_offset: 0 - name: OPTKEY
bit_size: 32 description: Option byte key
description: Option byte key bit_offset: 0
name: OPTKEY bit_size: 32
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- bit_offset: 0 - name: BSY
bit_size: 1 description: Busy
description: Busy bit_offset: 0
name: BSY bit_size: 1
- bit_offset: 2 - name: PGERR
bit_size: 1 description: Programming error
description: Programming error bit_offset: 2
name: PGERR bit_size: 1
- bit_offset: 4 - name: WRPRTERR
bit_size: 1 description: Write protection error
description: Write protection error bit_offset: 4
name: WRPRTERR bit_size: 1
- bit_offset: 5 - name: EOP
bit_size: 1 description: End of operation
description: End of operation bit_offset: 5
name: EOP bit_size: 1
fieldset/WRPR: fieldset/WRPR:
description: Write protection register description: Write protection register
fields: fields:
- bit_offset: 0 - name: WRP
bit_size: 32 description: Write protect
description: Write protect bit_offset: 0
name: WRP bit_size: 32
enum/LATENCY:
bit_size: 3
variants:
- name: WS0
description: "Zero wait state, if 0 < SYSCLK≤ 24 MHz"
value: 0
- name: WS1
description: "One wait state, if 24 MHz < SYSCLK ≤ 48 MHz"
value: 1
- name: WS2
description: "Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz"
value: 2

708
data/registers/flash_f7.yaml
View File

@ -2,381 +2,381 @@
block/FLASH: block/FLASH:
description: FLASH description: FLASH
items: items:
- byte_offset: 0 - name: ACR
description: Flash access control register description: Flash access control register
fieldset: ACR byte_offset: 0
name: ACR fieldset: ACR
- access: Write - name: KEYR
byte_offset: 4 description: Flash key register
description: Flash key register byte_offset: 4
fieldset: KEYR access: Write
name: KEYR fieldset: KEYR
- access: Write - name: OPTKEYR
byte_offset: 8 description: Flash option key register
description: Flash option key register byte_offset: 8
fieldset: OPTKEYR access: Write
name: OPTKEYR fieldset: OPTKEYR
- byte_offset: 12 - name: SR
description: Status register description: Status register
fieldset: SR byte_offset: 12
name: SR fieldset: SR
- byte_offset: 16 - name: CR
description: Control register description: Control register
fieldset: CR byte_offset: 16
name: CR fieldset: CR
- byte_offset: 20 - name: OPTCR
description: Flash option control register description: Flash option control register
fieldset: OPTCR byte_offset: 20
name: OPTCR fieldset: OPTCR
- byte_offset: 24 - name: OPTCR1
description: Flash option control register 1 description: Flash option control register 1
fieldset: OPTCR1 byte_offset: 24
name: OPTCR1 fieldset: OPTCR1
- byte_offset: 28 - name: OPTCR2
description: Flash option control register description: Flash option control register
fieldset: OPTCR2 byte_offset: 28
name: OPTCR2 fieldset: OPTCR2
enum/ARTEN:
bit_size: 1
variants:
- description: ART Accelerator is disabled
name: Disabled
value: 0
- description: ART Accelerator is enabled
name: Enabled
value: 1
enum/ARTRST:
bit_size: 1
variants:
- description: Accelerator is not reset
name: NotReset
value: 0
- description: Accelerator is reset
name: Reset
value: 1
enum/EOPIE:
bit_size: 1
variants:
- description: End of operation interrupt disabled
name: Disabled
value: 0
- description: End of operation interrupt enabled
name: Enabled
value: 1
enum/ERRIE:
bit_size: 1
variants:
- description: Error interrupt generation disabled
name: Disabled
value: 0
- description: Error interrupt generation enabled
name: Enabled
value: 1
enum/LATENCY:
bit_size: 4
variants:
- description: 0 wait states
name: WS0
value: 0
- description: 1 wait states
name: WS1
value: 1
- description: 2 wait states
name: WS2
value: 2
- description: 3 wait states
name: WS3
value: 3
- description: 4 wait states
name: WS4
value: 4
- description: 5 wait states
name: WS5
value: 5
- description: 6 wait states
name: WS6
value: 6
- description: 7 wait states
name: WS7
value: 7
- description: 8 wait states
name: WS8
value: 8
- description: 9 wait states
name: WS9
value: 9
- description: 10 wait states
name: WS10
value: 10
- description: 11 wait states
name: WS11
value: 11
- description: 12 wait states
name: WS12
value: 12
- description: 13 wait states
name: WS13
value: 13
- description: 14 wait states
name: WS14
value: 14
- description: 15 wait states
name: WS15
value: 15
enum/LOCK:
bit_size: 1
variants:
- description: FLASH_CR register is unlocked
name: Unlocked
value: 0
- description: FLASH_CR register is locked
name: Locked
value: 1
enum/MER:
bit_size: 1
variants:
- description: Erase activated for all user sectors
name: MassErase
value: 1
enum/PG:
bit_size: 1
variants:
- description: Flash programming activated
name: Program
value: 1
enum/PRFTEN:
bit_size: 1
variants:
- description: Prefetch is disabled
name: Disabled
value: 0
- description: Prefetch is enabled
name: Enabled
value: 1
enum/PSIZE:
bit_size: 2
variants:
- description: Program x8
name: PSIZE8
value: 0
- description: Program x16
name: PSIZE16
value: 1
- description: Program x32
name: PSIZE32
value: 2
- description: Program x64
name: PSIZE64
value: 3
enum/SER:
bit_size: 1
variants:
- description: Erase activated for selected sector
name: SectorErase
value: 1
enum/STRT:
bit_size: 1
variants:
- description: Trigger an erase operation
name: Start
value: 1
fieldset/ACR: fieldset/ACR:
description: Flash access control register description: Flash access control register
fields: fields:
- bit_offset: 0 - name: LATENCY
bit_size: 4 description: Latency
description: Latency bit_offset: 0
enum: LATENCY bit_size: 4
name: LATENCY enum: LATENCY
- bit_offset: 8 - name: PRFTEN
bit_size: 1 description: Prefetch enable
description: Prefetch enable bit_offset: 8
enum: PRFTEN bit_size: 1
name: PRFTEN enum: PRFTEN
- bit_offset: 9 - name: ARTEN
bit_size: 1 description: ART Accelerator Enable
description: ART Accelerator Enable bit_offset: 9
enum: ARTEN bit_size: 1
name: ARTEN enum: ARTEN
- bit_offset: 11 - name: ARTRST
bit_size: 1 description: ART Accelerator reset
description: ART Accelerator reset bit_offset: 11
enum: ARTRST bit_size: 1
name: ARTRST enum: ARTRST
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
- bit_offset: 0 - name: PG
bit_size: 1 description: Programming
description: Programming bit_offset: 0
enum: PG bit_size: 1
name: PG enum: PG
- bit_offset: 1 - name: SER
bit_size: 1 description: Sector Erase
description: Sector Erase bit_offset: 1
enum: SER bit_size: 1
name: SER enum: SER
- bit_offset: 2 - name: MER
bit_size: 1 description: Mass Erase of sectors 0 to 11
description: Mass Erase of sectors 0 to 11 bit_offset: 2
enum: MER bit_size: 1
name: MER enum: MER
- bit_offset: 3 - name: SNB
bit_size: 4 description: Sector number
description: Sector number bit_offset: 3
name: SNB bit_size: 4
- bit_offset: 8 - name: PSIZE
bit_size: 2 description: Program size
description: Program size bit_offset: 8
enum: PSIZE bit_size: 2
name: PSIZE enum: PSIZE
- bit_offset: 16 - name: STRT
bit_size: 1 description: Start
description: Start bit_offset: 16
enum: STRT bit_size: 1
name: STRT enum: STRT
- bit_offset: 24 - name: EOPIE
bit_size: 1 description: End of operation interrupt enable
description: End of operation interrupt enable bit_offset: 24
enum: EOPIE bit_size: 1
name: EOPIE enum: EOPIE
- bit_offset: 25 - name: ERRIE
bit_size: 1 description: Error interrupt enable
description: Error interrupt enable bit_offset: 25
enum: ERRIE bit_size: 1
name: ERRIE enum: ERRIE
- bit_offset: 26 - name: RDERRIE
bit_size: 1 description: PCROP error interrupt enable
description: PCROP error interrupt enable bit_offset: 26
name: RDERRIE bit_size: 1
- bit_offset: 31 - name: LOCK
bit_size: 1 description: Lock
description: Lock bit_offset: 31
enum: LOCK bit_size: 1
name: LOCK enum: LOCK
fieldset/KEYR: fieldset/KEYR:
description: Flash key register description: Flash key register
fields: fields:
- bit_offset: 0 - name: KEY
bit_size: 32 description: FPEC key
description: FPEC key bit_offset: 0
name: KEY bit_size: 32
fieldset/OPTCR: fieldset/OPTCR:
description: Flash option control register description: Flash option control register
fields: fields:
- bit_offset: 0 - name: OPTLOCK
bit_size: 1 description: Option lock
description: Option lock bit_offset: 0
name: OPTLOCK bit_size: 1
- bit_offset: 1 - name: OPTSTRT
bit_size: 1 description: Option start
description: Option start bit_offset: 1
name: OPTSTRT bit_size: 1
- bit_offset: 2 - name: BOR_LEV
bit_size: 2 description: BOR reset Level
description: BOR reset Level bit_offset: 2
name: BOR_LEV bit_size: 2
- bit_offset: 4 - name: WWDG_SW
bit_size: 1 description: User option bytes
description: User option bytes bit_offset: 4
name: WWDG_SW bit_size: 1
- bit_offset: 5 - name: IWDG_SW
bit_size: 1 description: WDG_SW User option bytes
description: WDG_SW User option bytes bit_offset: 5
name: IWDG_SW bit_size: 1
- bit_offset: 6 - name: nRST_STOP
bit_size: 1 description: nRST_STOP User option bytes
description: nRST_STOP User option bytes bit_offset: 6
name: nRST_STOP bit_size: 1
- bit_offset: 7 - name: nRST_STDBY
bit_size: 1 description: nRST_STDBY User option bytes
description: nRST_STDBY User option bytes bit_offset: 7
name: nRST_STDBY bit_size: 1
- bit_offset: 8 - name: RDP
bit_size: 8 description: Read protect
description: Read protect bit_offset: 8
name: RDP bit_size: 8
- bit_offset: 16 - name: nWRP
bit_size: 8 description: Not write protect
description: Not write protect bit_offset: 16
name: nWRP bit_size: 8
- bit_offset: 28 - name: nDBOOT
bit_size: 1 description: Dual Boot mode (valid only when nDBANK=0)
description: Dual Boot mode (valid only when nDBANK=0) bit_offset: 28
name: nDBOOT bit_size: 1
- bit_offset: 29 - name: nDBANK
bit_size: 1 description: Not dual bank mode
description: Not dual bank mode bit_offset: 29
name: nDBANK bit_size: 1
- bit_offset: 30 - name: IWDG_STDBY
bit_size: 1 description: Independent watchdog counter freeze in standby mode
description: Independent watchdog counter freeze in standby mode bit_offset: 30
name: IWDG_STDBY bit_size: 1
- bit_offset: 31 - name: IWDG_STOP
bit_size: 1 description: Independent watchdog counter freeze in Stop mode
description: Independent watchdog counter freeze in Stop mode bit_offset: 31
name: IWDG_STOP bit_size: 1
fieldset/OPTCR1: fieldset/OPTCR1:
description: Flash option control register 1 description: Flash option control register 1
fields: fields:
- bit_offset: 0 - name: BOOT_ADD0
bit_size: 16 description: Boot base address when Boot pin =0
description: Boot base address when Boot pin =0 bit_offset: 0
name: BOOT_ADD0 bit_size: 16
- bit_offset: 16 - name: BOOT_ADD1
bit_size: 16 description: Boot base address when Boot pin =1
description: Boot base address when Boot pin =1 bit_offset: 16
name: BOOT_ADD1 bit_size: 16
fieldset/OPTCR2: fieldset/OPTCR2:
description: Flash option control register description: Flash option control register
fields: fields:
- bit_offset: 0 - name: PCROPi
bit_size: 8 description: PCROP option byte
description: PCROP option byte bit_offset: 0
name: PCROPi bit_size: 8
- bit_offset: 31 - name: PCROP_RDP
bit_size: 1 description: PCROP zone preserved when RDP level decreased
description: PCROP zone preserved when RDP level decreased bit_offset: 31
name: PCROP_RDP bit_size: 1
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Flash option key register description: Flash option key register
fields: fields:
- bit_offset: 0 - name: OPTKEYR
bit_size: 32 description: Option byte key
description: Option byte key bit_offset: 0
name: OPTKEYR bit_size: 32
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- bit_offset: 0 - name: EOP
bit_size: 1 description: End of operation
description: End of operation bit_offset: 0
name: EOP bit_size: 1
- bit_offset: 1 - name: OPERR
bit_size: 1 description: Operation error
description: Operation error bit_offset: 1
name: OPERR bit_size: 1
- bit_offset: 4 - name: WRPERR
bit_size: 1 description: Write protection error
description: Write protection error bit_offset: 4
name: WRPERR bit_size: 1
- bit_offset: 5 - name: PGAERR
bit_size: 1 description: Programming alignment error
description: Programming alignment error bit_offset: 5
name: PGAERR bit_size: 1
- bit_offset: 6 - name: PGPERR
bit_size: 1 description: Programming parallelism error
description: Programming parallelism error bit_offset: 6
name: PGPERR bit_size: 1
- bit_offset: 7 - name: ERSERR
bit_size: 1 description: Erase Sequence Error
description: Erase Sequence Error bit_offset: 7
name: ERSERR bit_size: 1
- bit_offset: 8 - name: RDERR
bit_size: 1 description: RDERR
description: RDERR bit_offset: 8
name: RDERR bit_size: 1
- bit_offset: 16 - name: BSY
bit_size: 1 description: Busy
description: Busy bit_offset: 16
name: BSY bit_size: 1
enum/ARTEN:
bit_size: 1
variants:
- name: Disabled
description: ART Accelerator is disabled
value: 0
- name: Enabled
description: ART Accelerator is enabled
value: 1
enum/ARTRST:
bit_size: 1
variants:
- name: NotReset
description: Accelerator is not reset
value: 0
- name: Reset
description: Accelerator is reset
value: 1
enum/EOPIE:
bit_size: 1
variants:
- name: Disabled
description: End of operation interrupt disabled
value: 0
- name: Enabled
description: End of operation interrupt enabled
value: 1
enum/ERRIE:
bit_size: 1
variants:
- name: Disabled
description: Error interrupt generation disabled
value: 0
- name: Enabled
description: Error interrupt generation enabled
value: 1
enum/LATENCY:
bit_size: 4
variants:
- name: WS0
description: 0 wait states
value: 0
- name: WS1
description: 1 wait states
value: 1
- name: WS2
description: 2 wait states
value: 2
- name: WS3
description: 3 wait states
value: 3
- name: WS4
description: 4 wait states
value: 4
- name: WS5
description: 5 wait states
value: 5
- name: WS6
description: 6 wait states
value: 6
- name: WS7
description: 7 wait states
value: 7
- name: WS8
description: 8 wait states
value: 8
- name: WS9
description: 9 wait states
value: 9
- name: WS10
description: 10 wait states
value: 10
- name: WS11
description: 11 wait states
value: 11
- name: WS12
description: 12 wait states
value: 12
- name: WS13
description: 13 wait states
value: 13
- name: WS14
description: 14 wait states
value: 14
- name: WS15
description: 15 wait states
value: 15
enum/LOCK:
bit_size: 1
variants:
- name: Unlocked
description: FLASH_CR register is unlocked
value: 0
- name: Locked
description: FLASH_CR register is locked
value: 1
enum/MER:
bit_size: 1
variants:
- name: MassErase
description: Erase activated for all user sectors
value: 1
enum/PG:
bit_size: 1
variants:
- name: Program
description: Flash programming activated
value: 1
enum/PRFTEN:
bit_size: 1
variants:
- name: Disabled
description: Prefetch is disabled
value: 0
- name: Enabled
description: Prefetch is enabled
value: 1
enum/PSIZE:
bit_size: 2
variants:
- name: PSIZE8
description: Program x8
value: 0
- name: PSIZE16
description: Program x16
value: 1
- name: PSIZE32
description: Program x32
value: 2
- name: PSIZE64
description: Program x64
value: 3
enum/SER:
bit_size: 1
variants:
- name: SectorErase
description: Erase activated for selected sector
value: 1
enum/STRT:
bit_size: 1
variants:
- name: Start
description: Trigger an erase operation
value: 1

715
data/registers/flash_l4.yaml
View File

@ -1,408 +1,409 @@
---
block/FLASH: block/FLASH:
description: Flash description: Flash
items: items:
- byte_offset: 0 - name: ACR
description: Access control register description: Access control register
fieldset: ACR byte_offset: 0
name: ACR fieldset: ACR
- access: Write - name: PDKEYR
byte_offset: 4 description: Power down key register
description: Power down key register byte_offset: 4
fieldset: PDKEYR access: Write
name: PDKEYR fieldset: PDKEYR
- access: Write - name: KEYR
byte_offset: 8 description: Flash key register
description: Flash key register byte_offset: 8
fieldset: KEYR access: Write
name: KEYR fieldset: KEYR
- access: Write - name: OPTKEYR
byte_offset: 12 description: Option byte key register
description: Option byte key register byte_offset: 12
fieldset: OPTKEYR access: Write
name: OPTKEYR fieldset: OPTKEYR
- byte_offset: 16 - name: SR
description: Status register description: Status register
fieldset: SR byte_offset: 16
name: SR fieldset: SR
- byte_offset: 20 - name: CR
description: Flash control register description: Flash control register
fieldset: CR byte_offset: 20
name: CR fieldset: CR
- byte_offset: 24 - name: ECCR
description: Flash ECC register description: Flash ECC register
fieldset: ECCR byte_offset: 24
name: ECCR fieldset: ECCR
- byte_offset: 32 - name: OPTR
description: Flash option register description: Flash option register
fieldset: OPTR byte_offset: 32
name: OPTR fieldset: OPTR
- byte_offset: 36 - name: PCROP1SR
description: Flash Bank 1 PCROP Start address register description: Flash Bank 1 PCROP Start address register
fieldset: PCROP1SR byte_offset: 36
name: PCROP1SR fieldset: PCROP1SR
- byte_offset: 40 - name: PCROP1ER
description: Flash Bank 1 PCROP End address register description: Flash Bank 1 PCROP End address register
fieldset: PCROP1ER byte_offset: 40
name: PCROP1ER fieldset: PCROP1ER
- byte_offset: 44 - name: WRP1AR
description: Flash Bank 1 WRP area A address register description: Flash Bank 1 WRP area A address register
fieldset: WRP1AR byte_offset: 44
name: WRP1AR fieldset: WRP1AR
- byte_offset: 48 - name: WRP1BR
description: Flash Bank 1 WRP area B address register description: Flash Bank 1 WRP area B address register
fieldset: WRP1BR byte_offset: 48
name: WRP1BR fieldset: WRP1BR
- byte_offset: 68 - name: PCROP2SR
description: Flash Bank 2 PCROP Start address register description: Flash Bank 2 PCROP Start address register
fieldset: PCROP2SR byte_offset: 68
name: PCROP2SR fieldset: PCROP2SR
- byte_offset: 72 - name: PCROP2ER
description: Flash Bank 2 PCROP End address register description: Flash Bank 2 PCROP End address register
fieldset: PCROP2ER byte_offset: 72
name: PCROP2ER fieldset: PCROP2ER
- byte_offset: 76 - name: WRP2AR
description: Flash Bank 2 WRP area A address register description: Flash Bank 2 WRP area A address register
fieldset: WRP2AR byte_offset: 76
name: WRP2AR fieldset: WRP2AR
- byte_offset: 80 - name: WRP2BR
description: Flash Bank 2 WRP area B address register description: Flash Bank 2 WRP area B address register
fieldset: WRP2BR byte_offset: 80
name: WRP2BR fieldset: WRP2BR
fieldset/ACR: fieldset/ACR:
description: Access control register description: Access control register
fields: fields:
- bit_offset: 0 - name: LATENCY
bit_size: 3 description: Latency
description: Latency bit_offset: 0
name: LATENCY bit_size: 3
- bit_offset: 8 - name: PRFTEN
bit_size: 1 description: Prefetch enable
description: Prefetch enable bit_offset: 8
name: PRFTEN bit_size: 1
- bit_offset: 9 - name: ICEN
bit_size: 1 description: Instruction cache enable
description: Instruction cache enable bit_offset: 9
name: ICEN bit_size: 1
- bit_offset: 10 - name: DCEN
bit_size: 1 description: Data cache enable
description: Data cache enable bit_offset: 10
name: DCEN bit_size: 1
- bit_offset: 11 - name: ICRST
bit_size: 1 description: Instruction cache reset
description: Instruction cache reset bit_offset: 11
name: ICRST bit_size: 1
- bit_offset: 12 - name: DCRST
bit_size: 1 description: Data cache reset
description: Data cache reset bit_offset: 12
name: DCRST bit_size: 1
- bit_offset: 13 - name: RUN_PD
bit_size: 1 description: Flash Power-down mode during Low-power run mode
description: Flash Power-down mode during Low-power run mode bit_offset: 13
name: RUN_PD bit_size: 1
- bit_offset: 14 - name: SLEEP_PD
bit_size: 1 description: Flash Power-down mode during Low-power sleep mode
description: Flash Power-down mode during Low-power sleep mode bit_offset: 14
name: SLEEP_PD bit_size: 1
fieldset/CR: fieldset/CR:
description: Flash control register description: Flash control register
fields: fields:
- bit_offset: 0 - name: PG
bit_size: 1 description: Programming
description: Programming bit_offset: 0
name: PG bit_size: 1
- bit_offset: 1 - name: PER
bit_size: 1 description: Page erase
description: Page erase bit_offset: 1
name: PER bit_size: 1
- array: - name: MER
len: 2 description: Bank 1 Mass erase
stride: 13 bit_offset: 2
bit_offset: 2 bit_size: 1
bit_size: 1 array:
description: Bank 1 Mass erase len: 2
name: MER stride: 13
- bit_offset: 3 - name: PNB
bit_size: 8 description: Page number
description: Page number bit_offset: 3
name: PNB bit_size: 8
- bit_offset: 11 - name: BKER
bit_size: 1 description: Bank erase
description: Bank erase bit_offset: 11
name: BKER bit_size: 1
- bit_offset: 16 - name: START
bit_size: 1 description: Start
description: Start bit_offset: 16
name: START bit_size: 1
- bit_offset: 17 - name: OPTSTRT
bit_size: 1 description: Options modification start
description: Options modification start bit_offset: 17
name: OPTSTRT bit_size: 1
- bit_offset: 18 - name: FSTPG
bit_size: 1 description: Fast programming
description: Fast programming bit_offset: 18
name: FSTPG bit_size: 1
- bit_offset: 24 - name: EOPIE
bit_size: 1 description: End of operation interrupt enable
description: End of operation interrupt enable bit_offset: 24
name: EOPIE bit_size: 1
- bit_offset: 25 - name: ERRIE
bit_size: 1 description: Error interrupt enable
description: Error interrupt enable bit_offset: 25
name: ERRIE bit_size: 1
- bit_offset: 26 - name: RDERRIE
bit_size: 1 description: PCROP read error interrupt enable
description: PCROP read error interrupt enable bit_offset: 26
name: RDERRIE bit_size: 1
- bit_offset: 27 - name: OBL_LAUNCH
bit_size: 1 description: Force the option byte loading
description: Force the option byte loading bit_offset: 27
name: OBL_LAUNCH bit_size: 1
- bit_offset: 30 - name: OPTLOCK
bit_size: 1 description: Options Lock
description: Options Lock bit_offset: 30
name: OPTLOCK bit_size: 1
- bit_offset: 31 - name: LOCK
bit_size: 1 description: FLASH_CR Lock
description: FLASH_CR Lock bit_offset: 31
name: LOCK bit_size: 1
fieldset/ECCR: fieldset/ECCR:
description: Flash ECC register description: Flash ECC register
fields: fields:
- bit_offset: 0 - name: ADDR_ECC
bit_size: 19 description: ECC fail address
description: ECC fail address bit_offset: 0
name: ADDR_ECC bit_size: 19
- bit_offset: 19 - name: BK_ECC
bit_size: 1 description: ECC fail bank
description: ECC fail bank bit_offset: 19
name: BK_ECC bit_size: 1
- bit_offset: 20 - name: SYSF_ECC
bit_size: 1 description: System Flash ECC fail
description: System Flash ECC fail bit_offset: 20
name: SYSF_ECC bit_size: 1
- bit_offset: 24 - name: ECCIE
bit_size: 1 description: ECC correction interrupt enable
description: ECC correction interrupt enable bit_offset: 24
name: ECCIE bit_size: 1
- bit_offset: 30 - name: ECCC
bit_size: 1 description: ECC correction
description: ECC correction bit_offset: 30
name: ECCC bit_size: 1
- bit_offset: 31 - name: ECCD
bit_size: 1 description: ECC detection
description: ECC detection bit_offset: 31
name: ECCD bit_size: 1
fieldset/KEYR: fieldset/KEYR:
description: Flash key register description: Flash key register
fields: fields:
- bit_offset: 0 - name: KEYR
bit_size: 32 description: KEYR
description: KEYR bit_offset: 0
name: KEYR bit_size: 32
fieldset/OPTKEYR: fieldset/OPTKEYR:
description: Option byte key register description: Option byte key register
fields: fields:
- bit_offset: 0 - name: OPTKEYR
bit_size: 32 description: Option byte key
description: Option byte key bit_offset: 0
name: OPTKEYR bit_size: 32
fieldset/OPTR: fieldset/OPTR:
description: Flash option register description: Flash option register
fields: fields:
- bit_offset: 0 - name: RDP
bit_size: 8 description: Read protection level
description: Read protection level bit_offset: 0
name: RDP bit_size: 8
- bit_offset: 8 - name: BOR_LEV
bit_size: 3 description: BOR reset Level
description: BOR reset Level bit_offset: 8
name: BOR_LEV bit_size: 3
- bit_offset: 12 - name: nRST_STOP
bit_size: 1 description: nRST_STOP
description: nRST_STOP bit_offset: 12
name: nRST_STOP bit_size: 1
- bit_offset: 13 - name: nRST_STDBY
bit_size: 1 description: nRST_STDBY
description: nRST_STDBY bit_offset: 13
name: nRST_STDBY bit_size: 1
- bit_offset: 16 - name: IDWG_SW
bit_size: 1 description: Independent watchdog selection
description: Independent watchdog selection bit_offset: 16
name: IDWG_SW bit_size: 1
- bit_offset: 17 - name: IWDG_STOP
bit_size: 1 description: Independent watchdog counter freeze in Stop mode
description: Independent watchdog counter freeze in Stop mode bit_offset: 17
name: IWDG_STOP bit_size: 1
- bit_offset: 18 - name: IWDG_STDBY
bit_size: 1 description: Independent watchdog counter freeze in Standby mode
description: Independent watchdog counter freeze in Standby mode bit_offset: 18
name: IWDG_STDBY bit_size: 1
- bit_offset: 19 - name: WWDG_SW
bit_size: 1 description: Window watchdog selection
description: Window watchdog selection bit_offset: 19
name: WWDG_SW bit_size: 1
- array: - name: BFB
len: 1 description: Dual-bank boot
stride: 0 bit_offset: 20
bit_offset: 20 bit_size: 1
bit_size: 1 array:
description: Dual-bank boot len: 1
name: BFB stride: 0
- bit_offset: 21 - name: DUALBANK
bit_size: 1 description: Dual-Bank on 512 KB or 256 KB Flash memory devices
description: Dual-Bank on 512 KB or 256 KB Flash memory devices bit_offset: 21
name: DUALBANK bit_size: 1
- bit_offset: 23 - name: nBOOT1
bit_size: 1 description: Boot configuration
description: Boot configuration bit_offset: 23
name: nBOOT1 bit_size: 1
- bit_offset: 24 - name: SRAM2_PE
bit_size: 1 description: SRAM2 parity check enable
description: SRAM2 parity check enable bit_offset: 24
name: SRAM2_PE bit_size: 1
- bit_offset: 25 - name: SRAM2_RST
bit_size: 1 description: SRAM2 Erase when system reset
description: SRAM2 Erase when system reset bit_offset: 25
name: SRAM2_RST bit_size: 1
- bit_offset: 26 - name: nSWBOOT0
bit_size: 1 description: Software BOOT0
description: Software BOOT0 bit_offset: 26
name: nSWBOOT0 bit_size: 1
- bit_offset: 27 - name: nBOOT0
bit_size: 1 description: nBOOT0 option bit
description: nBOOT0 option bit bit_offset: 27
name: nBOOT0 bit_size: 1
fieldset/PCROP1ER: fieldset/PCROP1ER:
description: Flash Bank 1 PCROP End address register description: Flash Bank 1 PCROP End address register
fields: fields:
- bit_offset: 0 - name: PCROP1_END
bit_size: 16 description: Bank 1 PCROP area end offset
description: Bank 1 PCROP area end offset bit_offset: 0
name: PCROP1_END bit_size: 16
- bit_offset: 31 - name: PCROP_RDP
bit_size: 1 description: PCROP area preserved when RDP level decreased
description: PCROP area preserved when RDP level decreased bit_offset: 31
name: PCROP_RDP bit_size: 1
fieldset/PCROP1SR: fieldset/PCROP1SR:
description: Flash Bank 1 PCROP Start address register description: Flash Bank 1 PCROP Start address register
fields: fields:
- bit_offset: 0 - name: PCROP1_STRT
bit_size: 16 description: Bank 1 PCROP area start offset
description: Bank 1 PCROP area start offset bit_offset: 0
name: PCROP1_STRT bit_size: 16
fieldset/PCROP2ER: fieldset/PCROP2ER:
description: Flash Bank 2 PCROP End address register description: Flash Bank 2 PCROP End address register
fields: fields:
- bit_offset: 0 - name: PCROP2_END
bit_size: 16 description: Bank 2 PCROP area end offset
description: Bank 2 PCROP area end offset bit_offset: 0
name: PCROP2_END bit_size: 16
fieldset/PCROP2SR: fieldset/PCROP2SR:
description: Flash Bank 2 PCROP Start address register description: Flash Bank 2 PCROP Start address register
fields: fields:
- bit_offset: 0 - name: PCROP2_STRT
bit_size: 16 description: Bank 2 PCROP area start offset
description: Bank 2 PCROP area start offset bit_offset: 0
name: PCROP2_STRT bit_size: 16
fieldset/PDKEYR: fieldset/PDKEYR:
description: Power down key register description: Power down key register
fields: fields:
- bit_offset: 0 - name: PDKEYR
bit_size: 32 description: RUN_PD in FLASH_ACR key
description: RUN_PD in FLASH_ACR key bit_offset: 0
name: PDKEYR bit_size: 32
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- bit_offset: 0 - name: EOP
bit_size: 1 description: End of operation
description: End of operation bit_offset: 0
name: EOP bit_size: 1
- bit_offset: 1 - name: OPERR
bit_size: 1 description: Operation error
description: Operation error bit_offset: 1
name: OPERR bit_size: 1
- bit_offset: 3 - name: PROGERR
bit_size: 1 description: Programming error
description: Programming error bit_offset: 3
name: PROGERR bit_size: 1
- bit_offset: 4 - name: WRPERR
bit_size: 1 description: Write protected error
description: Write protected error bit_offset: 4
name: WRPERR bit_size: 1
- bit_offset: 5 - name: PGAERR
bit_size: 1 description: Programming alignment error
description: Programming alignment error bit_offset: 5
name: PGAERR bit_size: 1
- bit_offset: 6 - name: SIZERR
bit_size: 1 description: Size error
description: Size error bit_offset: 6
name: SIZERR bit_size: 1
- bit_offset: 7 - name: PGSERR
bit_size: 1 description: Programming sequence error
description: Programming sequence error bit_offset: 7
name: PGSERR bit_size: 1
- bit_offset: 8 - name: MISERR
bit_size: 1 description: Fast programming data miss error
description: Fast programming data miss error bit_offset: 8
name: MISERR bit_size: 1
- bit_offset: 9 - name: FASTERR
bit_size: 1 description: Fast programming error
description: Fast programming error bit_offset: 9
name: FASTERR bit_size: 1
- bit_offset: 14 - name: RDERR
bit_size: 1 description: PCROP read error
description: PCROP read error bit_offset: 14
name: RDERR bit_size: 1
- bit_offset: 15 - name: OPTVERR
bit_size: 1 description: Option validity error
description: Option validity error bit_offset: 15
name: OPTVERR bit_size: 1
- bit_offset: 16 - name: BSY
bit_size: 1 description: Busy
description: Busy bit_offset: 16
name: BSY bit_size: 1
fieldset/WRP1AR: fieldset/WRP1AR:
description: Flash Bank 1 WRP area A address register description: Flash Bank 1 WRP area A address register
fields: fields:
- bit_offset: 0 - name: WRP1A_STRT
bit_size: 8 description: Bank 1 WRP first area tart offset
description: Bank 1 WRP first area tart offset bit_offset: 0
name: WRP1A_STRT bit_size: 8
- bit_offset: 16 - name: WRP1A_END
bit_size: 8 description: Bank 1 WRP first area A end offset
description: Bank 1 WRP first area A end offset bit_offset: 16
name: WRP1A_END bit_size: 8
fieldset/WRP1BR: fieldset/WRP1BR:
description: Flash Bank 1 WRP area B address register description: Flash Bank 1 WRP area B address register
fields: fields:
- bit_offset: 0 - name: WRP1B_STRT
bit_size: 8 description: Bank 1 WRP second area B start offset
description: Bank 1 WRP second area B start offset bit_offset: 0
name: WRP1B_STRT bit_size: 8
- bit_offset: 16 - name: WRP1B_END
bit_size: 8 description: Bank 1 WRP second area B end offset
description: Bank 1 WRP second area B end offset bit_offset: 16
name: WRP1B_END bit_size: 8
fieldset/WRP2AR: fieldset/WRP2AR:
description: Flash Bank 2 WRP area A address register description: Flash Bank 2 WRP area A address register
fields: fields:
- bit_offset: 0 - name: WRP2A_STRT
bit_size: 8 description: Bank 2 WRP first area A start offset
description: Bank 2 WRP first area A start offset bit_offset: 0
name: WRP2A_STRT bit_size: 8
- bit_offset: 16 - name: WRP2A_END
bit_size: 8 description: Bank 2 WRP first area A end offset
description: Bank 2 WRP first area A end offset bit_offset: 16
name: WRP2A_END bit_size: 8
fieldset/WRP2BR: fieldset/WRP2BR:
description: Flash Bank 2 WRP area B address register description: Flash Bank 2 WRP area B address register
fields: fields:
- bit_offset: 0 - name: WRP2B_STRT
bit_size: 8 description: Bank 2 WRP second area B start offset
description: Bank 2 WRP second area B start offset bit_offset: 0
name: WRP2B_STRT bit_size: 8
- bit_offset: 16 - name: WRP2B_END
bit_size: 8 description: Bank 2 WRP second area B end offset
description: Bank 2 WRP second area B end offset bit_offset: 16
name: WRP2B_END bit_size: 8

10
data/registers/gpio_v1.yaml
View File

@ -4,39 +4,33 @@ block/GPIO:
items: items:
- name: CR - name: CR
description: Port configuration register low (GPIOn_CRL) description: Port configuration register low (GPIOn_CRL)
byte_offset: 0
reset_value: 1145324612
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 0
fieldset: CR fieldset: CR
- name: IDR - name: IDR
description: Port input data register (GPIOn_IDR) description: Port input data register (GPIOn_IDR)
byte_offset: 8 byte_offset: 8
reset_value: 0
access: Read access: Read
fieldset: IDR fieldset: IDR
- name: ODR - name: ODR
description: Port output data register (GPIOn_ODR) description: Port output data register (GPIOn_ODR)
byte_offset: 12 byte_offset: 12
reset_value: 0
fieldset: ODR fieldset: ODR
- name: BSRR - name: BSRR
description: Port bit set/reset register (GPIOn_BSRR) description: Port bit set/reset register (GPIOn_BSRR)
byte_offset: 16 byte_offset: 16
reset_value: 0
access: Write access: Write
fieldset: BSRR fieldset: BSRR
- name: BRR - name: BRR
description: Port bit reset register (GPIOn_BRR) description: Port bit reset register (GPIOn_BRR)
byte_offset: 20 byte_offset: 20
reset_value: 0
access: Write access: Write
fieldset: BRR fieldset: BRR
- name: LCKR - name: LCKR
description: Port configuration lock register description: Port configuration lock register
byte_offset: 24 byte_offset: 24
reset_value: 0
fieldset: LCKR fieldset: LCKR
fieldset/BRR: fieldset/BRR:
description: Port bit reset register (GPIOn_BRR) description: Port bit reset register (GPIOn_BRR)
@ -208,4 +202,4 @@ enum/ODR:
value: 1 value: 1
- name: Low - name: Low
description: Set output to logic low description: Set output to logic low
value: 0 value: 0

15
data/registers/gpio_v2.yaml
View File

@ -5,52 +5,43 @@ block/GPIO:
- name: MODER - name: MODER
description: GPIO port mode register description: GPIO port mode register
byte_offset: 0 byte_offset: 0
reset_value: 2818572288
fieldset: MODER fieldset: MODER
- name: OTYPER - name: OTYPER
description: GPIO port output type register description: GPIO port output type register
byte_offset: 4 byte_offset: 4
reset_value: 0
fieldset: OTYPER fieldset: OTYPER
- name: OSPEEDR - name: OSPEEDR
description: GPIO port output speed register description: GPIO port output speed register
byte_offset: 8 byte_offset: 8
reset_value: 0
fieldset: OSPEEDR fieldset: OSPEEDR
- name: PUPDR - name: PUPDR
description: GPIO port pull-up/pull-down register description: GPIO port pull-up/pull-down register
byte_offset: 12 byte_offset: 12
reset_value: 1677721600
fieldset: PUPDR fieldset: PUPDR
- name: IDR - name: IDR
description: GPIO port input data register description: GPIO port input data register
byte_offset: 16 byte_offset: 16
reset_value: 0
access: Read access: Read
fieldset: IDR fieldset: IDR
- name: ODR - name: ODR
description: GPIO port output data register description: GPIO port output data register
byte_offset: 20 byte_offset: 20
reset_value: 0
fieldset: ODR fieldset: ODR
- name: BSRR - name: BSRR
description: GPIO port bit set/reset register description: GPIO port bit set/reset register
byte_offset: 24 byte_offset: 24
reset_value: 0
access: Write access: Write
fieldset: BSRR fieldset: BSRR
- name: LCKR - name: LCKR
description: GPIO port configuration lock register description: GPIO port configuration lock register
byte_offset: 28 byte_offset: 28
reset_value: 0
fieldset: LCKR fieldset: LCKR
- name: AFR - name: AFR
description: GPIO alternate function register (low, high) description: "GPIO alternate function register (low, high)"
byte_offset: 32
reset_value: 0
array: array:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 32
fieldset: AFR fieldset: AFR
fieldset/AFR: fieldset/AFR:
description: GPIO alternate function register description: GPIO alternate function register
@ -313,4 +304,4 @@ enum/PUPDR:
value: 1 value: 1
- name: PullDown - name: PullDown
description: Pull-down description: Pull-down
value: 2 value: 2

3
data/registers/ipcc_v1.yaml
View File

@ -4,11 +4,10 @@ block/IPCC:
items: items:
- name: CPU - name: CPU
description: CPU specific registers description: CPU specific registers
byte_offset: 0
array: array:
len: 2 len: 2
stride: 16 stride: 16
byte_offset: 0
block/IPCC_CPU: block/IPCC_CPU:
description: IPCC description: IPCC
items: items:

182
data/registers/iwdg_v2.yaml
View File

@ -2,109 +2,109 @@
block/IWDG: block/IWDG:
description: Independent watchdog description: Independent watchdog
items: items:
- access: Write - name: KR
byte_offset: 0 description: Key register
description: Key register byte_offset: 0
fieldset: KR access: Write
name: KR fieldset: KR
- byte_offset: 4 - name: PR
description: Prescaler register description: Prescaler register
fieldset: PR byte_offset: 4
name: PR fieldset: PR
- byte_offset: 8 - name: RLR
description: Reload register description: Reload register
fieldset: RLR byte_offset: 8
name: RLR fieldset: RLR
- access: Read - name: SR
byte_offset: 12 description: Status register
description: Status register byte_offset: 12
fieldset: SR access: Read
name: SR fieldset: SR
- byte_offset: 16 - name: WINR
description: Window register description: Window register
fieldset: WINR byte_offset: 16
name: WINR fieldset: WINR
enum/KEY:
bit_size: 16
variants:
- description: Enable access to PR, RLR and WINR registers (0x5555)
name: Enable
value: 21845
- description: Reset the watchdog value (0xAAAA)
name: Reset
value: 43690
- description: Start the watchdog (0xCCCC)
name: Start
value: 52428
enum/PR:
bit_size: 3
variants:
- description: Divider /4
name: DivideBy4
value: 0
- description: Divider /8
name: DivideBy8
value: 1
- description: Divider /16
name: DivideBy16
value: 2
- description: Divider /32
name: DivideBy32
value: 3
- description: Divider /64
name: DivideBy64
value: 4
- description: Divider /128
name: DivideBy128
value: 5
- description: Divider /256
name: DivideBy256
value: 6
- description: Divider /256
name: DivideBy256bis
value: 7
fieldset/KR: fieldset/KR:
description: Key register description: Key register
fields: fields:
- bit_offset: 0 - name: KEY
bit_size: 16 description: "Key value (write only, read 0000h)"
description: Key value (write only, read 0000h) bit_offset: 0
enum: KEY bit_size: 16
name: KEY enum: KEY
fieldset/PR: fieldset/PR:
description: Prescaler register description: Prescaler register
fields: fields:
- bit_offset: 0 - name: PR
bit_size: 3 description: Prescaler divider
description: Prescaler divider bit_offset: 0
enum: PR bit_size: 3
name: PR enum: PR
fieldset/RLR: fieldset/RLR:
description: Reload register description: Reload register
fields: fields:
- bit_offset: 0 - name: RL
bit_size: 12 description: Watchdog counter reload value
description: Watchdog counter reload value bit_offset: 0
name: RL bit_size: 12
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- bit_offset: 0 - name: PVU
bit_size: 1 description: Watchdog prescaler value update
description: Watchdog prescaler value update bit_offset: 0
name: PVU bit_size: 1
- bit_offset: 1 - name: RVU
bit_size: 1 description: Watchdog counter reload value update
description: Watchdog counter reload value update bit_offset: 1
name: RVU bit_size: 1
- bit_offset: 2 - name: WVU
bit_size: 1 description: Watchdog counter window value update
description: Watchdog counter window value update bit_offset: 2
name: WVU bit_size: 1
fieldset/WINR: fieldset/WINR:
description: Window register description: Window register
fields: fields:
- bit_offset: 0 - name: WIN
bit_size: 12 description: Watchdog counter window value
description: Watchdog counter window value bit_offset: 0
name: WIN bit_size: 12
enum/KEY:
bit_size: 16
variants:
- name: Enable
description: "Enable access to PR, RLR and WINR registers (0x5555)"
value: 21845
- name: Reset
description: Reset the watchdog value (0xAAAA)
value: 43690
- name: Start
description: Start the watchdog (0xCCCC)
value: 52428
enum/PR:
bit_size: 3
variants:
- name: DivideBy4
description: Divider /4
value: 0
- name: DivideBy8
description: Divider /8
value: 1
- name: DivideBy16
description: Divider /16
value: 2
- name: DivideBy32
description: Divider /32
value: 3
- name: DivideBy64
description: Divider /64
value: 4
- name: DivideBy128
description: Divider /128
value: 5
- name: DivideBy256
description: Divider /256
value: 6
- name: DivideBy256bis
description: Divider /256
value: 7

9050
data/registers/jpeg_v1.yaml
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24
data/registers/lptim_g0.yaml
View File

@ -260,33 +260,33 @@ enum/PRESC:
bit_size: 3 bit_size: 3
variants: variants:
- name: DIV_BY_1 - name: DIV_BY_1
value: 0x0 value: 0
- name: DIV_BY_2 - name: DIV_BY_2
value: 0x1 value: 1
- name: DIV_BY_4 - name: DIV_BY_4
value: 0x2 value: 2
- name: DIV_BY_8 - name: DIV_BY_8
value: 0x3 value: 3
- name: DIV_BY_16 - name: DIV_BY_16
value: 0x4 value: 4
- name: DIV_BY_32 - name: DIV_BY_32
value: 0x5 value: 5
- name: DIV_BY_64 - name: DIV_BY_64
value: 0x6 value: 6
- name: DIV_BY_128 - name: DIV_BY_128
value: 0x7 value: 7
enum/TRIGEN: enum/TRIGEN:
bit_size: 2 bit_size: 2
variants: variants:
- name: SOFTWARE - name: SOFTWARE
description: software trigger (counting start is initiated by software) description: software trigger (counting start is initiated by software)
value: 0x0 value: 0
- name: RISING - name: RISING
description: rising edge is the active edge description: rising edge is the active edge
value: 0x1 value: 1
- name: FALLING - name: FALLING
description: rising edge is the active edge description: rising edge is the active edge
value: 0x2 value: 2
- name: BOTH - name: BOTH
description: both edges are active edges description: both edges are active edges
value: 0x3 value: 3

390
data/registers/lptim_v1.yaml
View File

@ -2,222 +2,222 @@
block/LPTIM: block/LPTIM:
description: Low power timer description: Low power timer
items: items:
- access: Read - name: ISR
byte_offset: 0 description: Interrupt and Status Register
description: Interrupt and Status Register byte_offset: 0
fieldset: ISR access: Read
name: ISR fieldset: ISR
- access: Write - name: ICR
byte_offset: 4 description: Interrupt Clear Register
description: Interrupt Clear Register byte_offset: 4
fieldset: ICR access: Write
name: ICR fieldset: ICR
- byte_offset: 8 - name: IER
description: Interrupt Enable Register description: Interrupt Enable Register
fieldset: IER byte_offset: 8
name: IER fieldset: IER
- byte_offset: 12 - name: CFGR
description: Configuration Register description: Configuration Register
fieldset: CFGR byte_offset: 12
name: CFGR fieldset: CFGR
- byte_offset: 16 - name: CR
description: Control Register description: Control Register
fieldset: CR byte_offset: 16
name: CR fieldset: CR
- byte_offset: 20 - name: CMP
description: Compare Register description: Compare Register
fieldset: CMP byte_offset: 20
name: CMP fieldset: CMP
- byte_offset: 24 - name: ARR
description: Autoreload Register description: Autoreload Register
fieldset: ARR byte_offset: 24
name: ARR fieldset: ARR
- access: Read - name: CNT
byte_offset: 28 description: Counter Register
description: Counter Register byte_offset: 28
fieldset: CNT access: Read
name: CNT fieldset: CNT
fieldset/ARR: fieldset/ARR:
description: Autoreload Register description: Autoreload Register
fields: fields:
- bit_offset: 0 - name: ARR
bit_size: 16 description: Auto reload value
description: Auto reload value bit_offset: 0
name: ARR bit_size: 16
fieldset/CFGR: fieldset/CFGR:
description: Configuration Register description: Configuration Register
fields: fields:
- bit_offset: 0 - name: CKSEL
bit_size: 1 description: Clock selector
description: Clock selector bit_offset: 0
name: CKSEL bit_size: 1
- bit_offset: 1 - name: CKPOL
bit_size: 2 description: Clock Polarity
description: Clock Polarity bit_offset: 1
name: CKPOL bit_size: 2
- bit_offset: 3 - name: CKFLT
bit_size: 2 description: Configurable digital filter for external clock
description: Configurable digital filter for external clock bit_offset: 3
name: CKFLT bit_size: 2
- bit_offset: 6 - name: TRGFLT
bit_size: 2 description: Configurable digital filter for trigger
description: Configurable digital filter for trigger bit_offset: 6
name: TRGFLT bit_size: 2
- bit_offset: 9 - name: PRESC
bit_size: 3 description: Clock prescaler
description: Clock prescaler bit_offset: 9
name: PRESC bit_size: 3
- bit_offset: 13 - name: TRIGSEL
bit_size: 3 description: Trigger selector
description: Trigger selector bit_offset: 13
name: TRIGSEL bit_size: 3
- bit_offset: 17 - name: TRIGEN
bit_size: 2 description: Trigger enable and polarity
description: Trigger enable and polarity bit_offset: 17
name: TRIGEN bit_size: 2
- bit_offset: 19 - name: TIMOUT
bit_size: 1 description: Timeout enable
description: Timeout enable bit_offset: 19
name: TIMOUT bit_size: 1
- bit_offset: 20 - name: WAVE
bit_size: 1 description: Waveform shape
description: Waveform shape bit_offset: 20
name: WAVE bit_size: 1
- bit_offset: 21 - name: WAVPOL
bit_size: 1 description: Waveform shape polarity
description: Waveform shape polarity bit_offset: 21
name: WAVPOL bit_size: 1
- bit_offset: 22 - name: PRELOAD
bit_size: 1 description: Registers update mode
description: Registers update mode bit_offset: 22
name: PRELOAD bit_size: 1
- bit_offset: 23 - name: COUNTMODE
bit_size: 1 description: counter mode enabled
description: counter mode enabled bit_offset: 23
name: COUNTMODE bit_size: 1
- bit_offset: 24 - name: ENC
bit_size: 1 description: Encoder mode enable
description: Encoder mode enable bit_offset: 24
name: ENC bit_size: 1
fieldset/CMP: fieldset/CMP:
description: Compare Register description: Compare Register
fields: fields:
- bit_offset: 0 - name: CMP
bit_size: 16 description: Compare value
description: Compare value bit_offset: 0
name: CMP bit_size: 16
fieldset/CNT: fieldset/CNT:
description: Counter Register description: Counter Register
fields: fields:
- bit_offset: 0 - name: CNT
bit_size: 16 description: Counter value
description: Counter value bit_offset: 0
name: CNT bit_size: 16
fieldset/CR: fieldset/CR:
description: Control Register description: Control Register
fields: fields:
- bit_offset: 0 - name: ENABLE
bit_size: 1 description: LPTIM Enable
description: LPTIM Enable bit_offset: 0
name: ENABLE bit_size: 1
- bit_offset: 1 - name: SNGSTRT
bit_size: 1 description: LPTIM start in single mode
description: LPTIM start in single mode bit_offset: 1
name: SNGSTRT bit_size: 1
- bit_offset: 2 - name: CNTSTRT
bit_size: 1 description: Timer start in continuous mode
description: Timer start in continuous mode bit_offset: 2
name: CNTSTRT bit_size: 1
fieldset/ICR: fieldset/ICR:
description: Interrupt Clear Register description: Interrupt Clear Register
fields: fields:
- bit_offset: 0 - name: CMPMCF
bit_size: 1 description: compare match Clear Flag
description: compare match Clear Flag bit_offset: 0
name: CMPMCF bit_size: 1
- bit_offset: 1 - name: ARRMCF
bit_size: 1 description: Autoreload match Clear Flag
description: Autoreload match Clear Flag bit_offset: 1
name: ARRMCF bit_size: 1
- bit_offset: 2 - name: EXTTRIGCF
bit_size: 1 description: External trigger valid edge Clear Flag
description: External trigger valid edge Clear Flag bit_offset: 2
name: EXTTRIGCF bit_size: 1
- bit_offset: 3 - name: CMPOKCF
bit_size: 1 description: Compare register update OK Clear Flag
description: Compare register update OK Clear Flag bit_offset: 3
name: CMPOKCF bit_size: 1
- bit_offset: 4 - name: ARROKCF
bit_size: 1 description: Autoreload register update OK Clear Flag
description: Autoreload register update OK Clear Flag bit_offset: 4
name: ARROKCF bit_size: 1
- bit_offset: 5 - name: UPCF
bit_size: 1 description: Direction change to UP Clear Flag
description: Direction change to UP Clear Flag bit_offset: 5
name: UPCF bit_size: 1
- bit_offset: 6 - name: DOWNCF
bit_size: 1 description: Direction change to down Clear Flag
description: Direction change to down Clear Flag bit_offset: 6
name: DOWNCF bit_size: 1
fieldset/IER: fieldset/IER:
description: Interrupt Enable Register description: Interrupt Enable Register
fields: fields:
- bit_offset: 0 - name: CMPMIE
bit_size: 1 description: Compare match Interrupt Enable
description: Compare match Interrupt Enable bit_offset: 0
name: CMPMIE bit_size: 1
- bit_offset: 1 - name: ARRMIE
bit_size: 1 description: Autoreload match Interrupt Enable
description: Autoreload match Interrupt Enable bit_offset: 1
name: ARRMIE bit_size: 1
- bit_offset: 2 - name: EXTTRIGIE
bit_size: 1 description: External trigger valid edge Interrupt Enable
description: External trigger valid edge Interrupt Enable bit_offset: 2
name: EXTTRIGIE bit_size: 1
- bit_offset: 3 - name: CMPOKIE
bit_size: 1 description: Compare register update OK Interrupt Enable
description: Compare register update OK Interrupt Enable bit_offset: 3
name: CMPOKIE bit_size: 1
- bit_offset: 4 - name: ARROKIE
bit_size: 1 description: Autoreload register update OK Interrupt Enable
description: Autoreload register update OK Interrupt Enable bit_offset: 4
name: ARROKIE bit_size: 1
- bit_offset: 5 - name: UPIE
bit_size: 1 description: Direction change to UP Interrupt Enable
description: Direction change to UP Interrupt Enable bit_offset: 5
name: UPIE bit_size: 1
- bit_offset: 6 - name: DOWNIE
bit_size: 1 description: Direction change to down Interrupt Enable
description: Direction change to down Interrupt Enable bit_offset: 6
name: DOWNIE bit_size: 1
fieldset/ISR: fieldset/ISR:
description: Interrupt and Status Register description: Interrupt and Status Register
fields: fields:
- bit_offset: 0 - name: CMPM
bit_size: 1 description: Compare match
description: Compare match bit_offset: 0
name: CMPM bit_size: 1
- bit_offset: 1 - name: ARRM
bit_size: 1 description: Autoreload match
description: Autoreload match bit_offset: 1
name: ARRM bit_size: 1
- bit_offset: 2 - name: EXTTRIG
bit_size: 1 description: External trigger edge event
description: External trigger edge event bit_offset: 2
name: EXTTRIG bit_size: 1
- bit_offset: 3 - name: CMPOK
bit_size: 1 description: Compare register update OK
description: Compare register update OK bit_offset: 3
name: CMPOK bit_size: 1
- bit_offset: 4 - name: ARROK
bit_size: 1 description: Autoreload register update OK
description: Autoreload register update OK bit_offset: 4
name: ARROK bit_size: 1
- bit_offset: 5 - name: UP
bit_size: 1 description: Counter direction change down to up
description: Counter direction change down to up bit_offset: 5
name: UP bit_size: 1
- bit_offset: 6 - name: DOWN
bit_size: 1 description: Counter direction change up to down
description: Counter direction change up to down bit_offset: 6
name: DOWN bit_size: 1

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data/registers/pwr_f7.yaml
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@ -2,181 +2,181 @@
block/PWR: block/PWR:
description: Power control description: Power control
items: items:
- byte_offset: 0 - name: CR1
description: power control register description: power control register
fieldset: CR1 byte_offset: 0
name: CR1 fieldset: CR1
- byte_offset: 4 - name: CSR1
description: power control/status register description: power control/status register
fieldset: CSR1 byte_offset: 4
name: CSR1 fieldset: CSR1
- byte_offset: 8 - name: CR2
description: power control register description: power control register
fieldset: CR2 byte_offset: 8
name: CR2 fieldset: CR2
- byte_offset: 12 - name: CSR2
description: power control/status register description: power control/status register
fieldset: CSR2 byte_offset: 12
name: CSR2 fieldset: CSR2
enum/PDDS:
bit_size: 1
variants:
- description: Enter Stop mode when the CPU enters deepsleep
name: STOP_MODE
value: 0
- description: Enter Standby mode when the CPU enters deepsleep
name: STANDBY_MODE
value: 1
enum/VOS:
bit_size: 2
variants:
- description: Scale 3 mode
name: SCALE3
value: 1
- description: Scale 2 mode
name: SCALE2
value: 2
- description: Scale 1 mode (reset value)
name: SCALE1
value: 3
fieldset/CR1: fieldset/CR1:
description: power control register description: power control register
fields: fields:
- bit_offset: 0 - name: LPDS
bit_size: 1 description: Low-power deep sleep
description: Low-power deep sleep bit_offset: 0
name: LPDS bit_size: 1
- bit_offset: 1 - name: PDDS
bit_size: 1 description: Power down deepsleep
description: Power down deepsleep bit_offset: 1
enum: PDDS bit_size: 1
name: PDDS enum: PDDS
- bit_offset: 3 - name: CSBF
bit_size: 1 description: Clear standby flag
description: Clear standby flag bit_offset: 3
name: CSBF bit_size: 1
- bit_offset: 4 - name: PVDE
bit_size: 1 description: Power voltage detector enable
description: Power voltage detector enable bit_offset: 4
name: PVDE bit_size: 1
- bit_offset: 5 - name: PLS
bit_size: 3 description: PVD level selection
description: PVD level selection bit_offset: 5
name: PLS bit_size: 3
- bit_offset: 8 - name: DBP
bit_size: 1 description: Disable backup domain write protection
description: Disable backup domain write protection bit_offset: 8
name: DBP bit_size: 1
- bit_offset: 9 - name: FPDS
bit_size: 1 description: Flash power down in Stop mode
description: Flash power down in Stop mode bit_offset: 9
name: FPDS bit_size: 1
- bit_offset: 10 - name: LPUDS
bit_size: 1 description: Low-power regulator in deepsleep under-drive mode
description: Low-power regulator in deepsleep under-drive mode bit_offset: 10
name: LPUDS bit_size: 1
- bit_offset: 11 - name: MRUDS
bit_size: 1 description: Main regulator in deepsleep under-drive mode
description: Main regulator in deepsleep under-drive mode bit_offset: 11
name: MRUDS bit_size: 1
- array: - name: ADCDC
len: 1 description: ADCDC1
stride: 0 bit_offset: 13
bit_offset: 13 bit_size: 1
bit_size: 1 array:
description: ADCDC1 len: 1
name: ADCDC stride: 0
- bit_offset: 14 - name: VOS
bit_size: 2 description: Regulator voltage scaling output selection
description: Regulator voltage scaling output selection bit_offset: 14
enum: VOS bit_size: 2
name: VOS enum: VOS
- bit_offset: 16 - name: ODEN
bit_size: 1 description: Over-drive enable
description: Over-drive enable bit_offset: 16
name: ODEN bit_size: 1
- bit_offset: 17 - name: ODSWEN
bit_size: 1 description: Over-drive switching enabled
description: Over-drive switching enabled bit_offset: 17
name: ODSWEN bit_size: 1
- bit_offset: 18 - name: UDEN
bit_size: 2 description: Under-drive enable in stop mode
description: Under-drive enable in stop mode bit_offset: 18
name: UDEN bit_size: 2
fieldset/CR2: fieldset/CR2:
description: power control register description: power control register
fields: fields:
- array: - name: CWUPF
len: 6 description: Clear Wakeup Pin flag for PA0
stride: 1 bit_offset: 0
bit_offset: 0 bit_size: 1
bit_size: 1 array:
description: Clear Wakeup Pin flag for PA0 len: 6
name: CWUPF stride: 1
- array: - name: WUPP
len: 6 description: Wakeup pin polarity bit for PA0
stride: 1 bit_offset: 8
bit_offset: 8 bit_size: 1
bit_size: 1 array:
description: Wakeup pin polarity bit for PA0 len: 6
name: WUPP stride: 1
fieldset/CSR1: fieldset/CSR1:
description: power control/status register description: power control/status register
fields: fields:
- bit_offset: 0 - name: WUIF
bit_size: 1 description: Wakeup internal flag
description: Wakeup internal flag bit_offset: 0
name: WUIF bit_size: 1
- bit_offset: 1 - name: SBF
bit_size: 1 description: Standby flag
description: Standby flag bit_offset: 1
name: SBF bit_size: 1
- bit_offset: 2 - name: PVDO
bit_size: 1 description: PVD output
description: PVD output bit_offset: 2
name: PVDO bit_size: 1
- bit_offset: 3 - name: BRR
bit_size: 1 description: Backup regulator ready
description: Backup regulator ready bit_offset: 3
name: BRR bit_size: 1
- bit_offset: 8 - name: EIWUP
bit_size: 1 description: Enable internal wakeup
description: Enable internal wakeup bit_offset: 8
name: EIWUP bit_size: 1
- bit_offset: 9 - name: BRE
bit_size: 1 description: Backup regulator enable
description: Backup regulator enable bit_offset: 9
name: BRE bit_size: 1
- bit_offset: 14 - name: VOSRDY
bit_size: 1 description: Regulator voltage scaling output selection ready bit
description: Regulator voltage scaling output selection ready bit bit_offset: 14
name: VOSRDY bit_size: 1
- bit_offset: 16 - name: ODRDY
bit_size: 1 description: Over-drive mode ready
description: Over-drive mode ready bit_offset: 16
name: ODRDY bit_size: 1
- bit_offset: 17 - name: ODSWRDY
bit_size: 1 description: Over-drive mode switching ready
description: Over-drive mode switching ready bit_offset: 17
name: ODSWRDY bit_size: 1
- bit_offset: 18 - name: UDRDY
bit_size: 2 description: Under-drive ready flag
description: Under-drive ready flag bit_offset: 18
name: UDRDY bit_size: 2
fieldset/CSR2: fieldset/CSR2:
description: power control/status register description: power control/status register
fields: fields:
- array: - name: WUPF
len: 6 description: Wakeup Pin flag for PA0
stride: 1 bit_offset: 0
bit_offset: 0 bit_size: 1
bit_size: 1 array:
description: Wakeup Pin flag for PA0 len: 6
name: WUPF stride: 1
- array: - name: EWUP
len: 6 description: Enable Wakeup pin for PA0
stride: 1 bit_offset: 8
bit_offset: 8 bit_size: 1
bit_size: 1 array:
description: Enable Wakeup pin for PA0 len: 6
name: EWUP stride: 1
enum/PDDS:
bit_size: 1
variants:
- name: STOP_MODE
description: Enter Stop mode when the CPU enters deepsleep
value: 0
- name: STANDBY_MODE
description: Enter Standby mode when the CPU enters deepsleep
value: 1
enum/VOS:
bit_size: 2
variants:
- name: SCALE3
description: Scale 3 mode
value: 1
- name: SCALE2
description: Scale 2 mode
value: 2
- name: SCALE1
description: Scale 1 mode (reset value)
value: 3

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data/registers/quadspi_v1.yaml
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@ -2,295 +2,295 @@
block/QUADSPI: block/QUADSPI:
description: QuadSPI interface description: QuadSPI interface
items: items:
- byte_offset: 0 - name: CR
description: control register description: control register
fieldset: CR byte_offset: 0
name: CR fieldset: CR
- byte_offset: 4 - name: DCR
description: device configuration register description: device configuration register
fieldset: DCR byte_offset: 4
name: DCR fieldset: DCR
- access: Read - name: SR
byte_offset: 8 description: status register
description: status register byte_offset: 8
fieldset: SR access: Read
name: SR fieldset: SR
- byte_offset: 12 - name: FCR
description: flag clear register description: flag clear register
fieldset: FCR byte_offset: 12
name: FCR fieldset: FCR
- byte_offset: 16 - name: DLR
description: data length register description: data length register
fieldset: DLR byte_offset: 16
name: DLR fieldset: DLR
- byte_offset: 20 - name: CCR
description: communication configuration register description: communication configuration register
fieldset: CCR byte_offset: 20
name: CCR fieldset: CCR
- byte_offset: 24 - name: AR
description: address register description: address register
fieldset: AR byte_offset: 24
name: AR fieldset: AR
- byte_offset: 28 - name: ABR
description: ABR description: ABR
fieldset: ABR byte_offset: 28
name: ABR fieldset: ABR
- byte_offset: 32 - name: DR
description: data register description: data register
fieldset: DR byte_offset: 32
name: DR fieldset: DR
- byte_offset: 36 - name: PSMKR
description: polling status mask register description: polling status mask register
fieldset: PSMKR byte_offset: 36
name: PSMKR fieldset: PSMKR
- byte_offset: 40 - name: PSMAR
description: polling status match register description: polling status match register
fieldset: PSMAR byte_offset: 40
name: PSMAR fieldset: PSMAR
- byte_offset: 44 - name: PIR
description: polling interval register description: polling interval register
fieldset: PIR byte_offset: 44
name: PIR fieldset: PIR
- byte_offset: 48 - name: LPTR
description: low-power timeout register description: low-power timeout register
fieldset: LPTR byte_offset: 48
name: LPTR fieldset: LPTR
fieldset/ABR: fieldset/ABR:
description: ABR description: ABR
fields: fields:
- bit_offset: 0 - name: ALTERNATE
bit_size: 32 description: ALTERNATE
description: ALTERNATE bit_offset: 0
name: ALTERNATE bit_size: 32
fieldset/AR: fieldset/AR:
description: address register description: address register
fields: fields:
- bit_offset: 0 - name: ADDRESS
bit_size: 32 description: Address
description: Address bit_offset: 0
name: ADDRESS bit_size: 32
fieldset/CCR: fieldset/CCR:
description: communication configuration register description: communication configuration register
fields: fields:
- bit_offset: 0 - name: INSTRUCTION
bit_size: 8 description: Instruction
description: Instruction bit_offset: 0
name: INSTRUCTION bit_size: 8
- bit_offset: 8 - name: IMODE
bit_size: 2 description: Instruction mode
description: Instruction mode bit_offset: 8
name: IMODE bit_size: 2
- bit_offset: 10 - name: ADMODE
bit_size: 2 description: Address mode
description: Address mode bit_offset: 10
name: ADMODE bit_size: 2
- bit_offset: 12 - name: ADSIZE
bit_size: 2 description: Address size
description: Address size bit_offset: 12
name: ADSIZE bit_size: 2
- bit_offset: 14 - name: ABMODE
bit_size: 2 description: Alternate bytes mode
description: Alternate bytes mode bit_offset: 14
name: ABMODE bit_size: 2
- bit_offset: 16 - name: ABSIZE
bit_size: 2 description: Alternate bytes size
description: Alternate bytes size bit_offset: 16
name: ABSIZE bit_size: 2
- bit_offset: 18 - name: DCYC
bit_size: 5 description: Number of dummy cycles
description: Number of dummy cycles bit_offset: 18
name: DCYC bit_size: 5
- bit_offset: 24 - name: DMODE
bit_size: 2 description: Data mode
description: Data mode bit_offset: 24
name: DMODE bit_size: 2
- bit_offset: 26 - name: FMODE
bit_size: 2 description: Functional mode
description: Functional mode bit_offset: 26
name: FMODE bit_size: 2
- bit_offset: 28 - name: SIOO
bit_size: 1 description: Send instruction only once mode
description: Send instruction only once mode bit_offset: 28
name: SIOO bit_size: 1
- bit_offset: 30 - name: DHHC
bit_size: 1 description: DDR hold half cycle
description: DDR hold half cycle bit_offset: 30
name: DHHC bit_size: 1
- bit_offset: 31 - name: DDRM
bit_size: 1 description: Double data rate mode
description: Double data rate mode bit_offset: 31
name: DDRM bit_size: 1
fieldset/CR: fieldset/CR:
description: control register description: control register
fields: fields:
- bit_offset: 0 - name: EN
bit_size: 1 description: Enable
description: Enable bit_offset: 0
name: EN bit_size: 1
- bit_offset: 1 - name: ABORT
bit_size: 1 description: Abort request
description: Abort request bit_offset: 1
name: ABORT bit_size: 1
- bit_offset: 2 - name: DMAEN
bit_size: 1 description: DMA enable
description: DMA enable bit_offset: 2
name: DMAEN bit_size: 1
- bit_offset: 3 - name: TCEN
bit_size: 1 description: Timeout counter enable
description: Timeout counter enable bit_offset: 3
name: TCEN bit_size: 1
- bit_offset: 4 - name: SSHIFT
bit_size: 1 description: Sample shift
description: Sample shift bit_offset: 4
name: SSHIFT bit_size: 1
- bit_offset: 6 - name: DFM
bit_size: 1 description: Dual-flash mode
description: Dual-flash mode bit_offset: 6
name: DFM bit_size: 1
- bit_offset: 7 - name: FSEL
bit_size: 1 description: FLASH memory selection
description: FLASH memory selection bit_offset: 7
name: FSEL bit_size: 1
- bit_offset: 8 - name: FTHRES
bit_size: 5 description: IFO threshold level
description: IFO threshold level bit_offset: 8
name: FTHRES bit_size: 5
- bit_offset: 16 - name: TEIE
bit_size: 1 description: Transfer error interrupt enable
description: Transfer error interrupt enable bit_offset: 16
name: TEIE bit_size: 1
- bit_offset: 17 - name: TCIE
bit_size: 1 description: Transfer complete interrupt enable
description: Transfer complete interrupt enable bit_offset: 17
name: TCIE bit_size: 1
- bit_offset: 18 - name: FTIE
bit_size: 1 description: FIFO threshold interrupt enable
description: FIFO threshold interrupt enable bit_offset: 18
name: FTIE bit_size: 1
- bit_offset: 19 - name: SMIE
bit_size: 1 description: Status match interrupt enable
description: Status match interrupt enable bit_offset: 19
name: SMIE bit_size: 1
- bit_offset: 20 - name: TOIE
bit_size: 1 description: TimeOut interrupt enable
description: TimeOut interrupt enable bit_offset: 20
name: TOIE bit_size: 1
- bit_offset: 22 - name: APMS
bit_size: 1 description: Automatic poll mode stop
description: Automatic poll mode stop bit_offset: 22
name: APMS bit_size: 1
- bit_offset: 23 - name: PMM
bit_size: 1 description: Polling match mode
description: Polling match mode bit_offset: 23
name: PMM bit_size: 1
- bit_offset: 24 - name: PRESCALER
bit_size: 8 description: Clock prescaler
description: Clock prescaler bit_offset: 24
name: PRESCALER bit_size: 8
fieldset/DCR: fieldset/DCR:
description: device configuration register description: device configuration register
fields: fields:
- bit_offset: 0 - name: CKMODE
bit_size: 1 description: Mode 0 / mode 3
description: Mode 0 / mode 3 bit_offset: 0
name: CKMODE bit_size: 1
- bit_offset: 8 - name: CSHT
bit_size: 3 description: Chip select high time
description: Chip select high time bit_offset: 8
name: CSHT bit_size: 3
- bit_offset: 16 - name: FSIZE
bit_size: 5 description: FLASH memory size
description: FLASH memory size bit_offset: 16
name: FSIZE bit_size: 5
fieldset/DLR: fieldset/DLR:
description: data length register description: data length register
fields: fields:
- bit_offset: 0 - name: DL
bit_size: 32 description: Data length
description: Data length bit_offset: 0
name: DL bit_size: 32
fieldset/DR: fieldset/DR:
description: data register description: data register
fields: fields:
- bit_offset: 0 - name: DATA
bit_size: 32 description: Data
description: Data bit_offset: 0
name: DATA bit_size: 32
fieldset/FCR: fieldset/FCR:
description: flag clear register description: flag clear register
fields: fields:
- bit_offset: 0 - name: CTEF
bit_size: 1 description: Clear transfer error flag
description: Clear transfer error flag bit_offset: 0
name: CTEF bit_size: 1
- bit_offset: 1 - name: CTCF
bit_size: 1 description: Clear transfer complete flag
description: Clear transfer complete flag bit_offset: 1
name: CTCF bit_size: 1
- bit_offset: 3 - name: CSMF
bit_size: 1 description: Clear status match flag
description: Clear status match flag bit_offset: 3
name: CSMF bit_size: 1
- bit_offset: 4 - name: CTOF
bit_size: 1 description: Clear timeout flag
description: Clear timeout flag bit_offset: 4
name: CTOF bit_size: 1
fieldset/LPTR: fieldset/LPTR:
description: low-power timeout register description: low-power timeout register
fields: fields:
- bit_offset: 0 - name: TIMEOUT
bit_size: 16 description: Timeout period
description: Timeout period bit_offset: 0
name: TIMEOUT bit_size: 16
fieldset/PIR: fieldset/PIR:
description: polling interval register description: polling interval register
fields: fields:
- bit_offset: 0 - name: INTERVAL
bit_size: 16 description: Polling interval
description: Polling interval bit_offset: 0
name: INTERVAL bit_size: 16
fieldset/PSMAR: fieldset/PSMAR:
description: polling status match register description: polling status match register
fields: fields:
- bit_offset: 0 - name: MATCH
bit_size: 32 description: Status match
description: Status match bit_offset: 0
name: MATCH bit_size: 32
fieldset/PSMKR: fieldset/PSMKR:
description: polling status mask register description: polling status mask register
fields: fields:
- bit_offset: 0 - name: MASK
bit_size: 32 description: Status mask
description: Status mask bit_offset: 0
name: MASK bit_size: 32
fieldset/SR: fieldset/SR:
description: status register description: status register
fields: fields:
- bit_offset: 0 - name: TEF
bit_size: 1 description: Transfer error flag
description: Transfer error flag bit_offset: 0
name: TEF bit_size: 1
- bit_offset: 1 - name: TCF
bit_size: 1 description: Transfer complete flag
description: Transfer complete flag bit_offset: 1
name: TCF bit_size: 1
- bit_offset: 2 - name: FTF
bit_size: 1 description: FIFO threshold flag
description: FIFO threshold flag bit_offset: 2
name: FTF bit_size: 1
- bit_offset: 3 - name: SMF
bit_size: 1 description: Status match flag
description: Status match flag bit_offset: 3
name: SMF bit_size: 1
- bit_offset: 4 - name: TOF
bit_size: 1 description: Timeout flag
description: Timeout flag bit_offset: 4
name: TOF bit_size: 1
- bit_offset: 5 - name: BUSY
bit_size: 1 description: Busy
description: Busy bit_offset: 5
name: BUSY bit_size: 1
- bit_offset: 8 - name: FLEVEL
bit_size: 7 description: FIFO level
description: FIFO level bit_offset: 8
name: FLEVEL bit_size: 7

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@ -1,3 +1,4 @@
---
block/RCC: block/RCC:
description: Reset and clock control description: Reset and clock control
items: items:

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data/registers/rcc_u5.yaml
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@ -2560,6 +2560,24 @@ enum/MSIBIAS:
- name: SAMPLING - name: SAMPLING
description: MSI bias sampling mode (ultra-low-power mode) description: MSI bias sampling mode (ultra-low-power mode)
value: 1 value: 1
enum/MSIPLLFAST:
bit_size: 1
variants:
- name: NORMAL
description: MSI PLL normal start-up
value: 0
- name: FAST
description: MSI PLL fast start-up
value: 1
enum/MSIPLLSEL:
bit_size: 1
variants:
- name: MSIK
description: "PLL mode applied to MSIK (MSI kernel) clock output "
value: 0
- name: MSIS
description: PLL mode applied to MSIS (MSI system) clock output
value: 1
enum/MSIRANGE: enum/MSIRANGE:
bit_size: 4 bit_size: 4
variants: variants:
@ -2611,6 +2629,15 @@ enum/MSIRANGE:
- name: RANGE_100KHZ - name: RANGE_100KHZ
description: "range 15 around 100 kHz " description: "range 15 around 100 kHz "
value: 15 value: 15
enum/MSIRGSEL:
bit_size: 1
variants:
- name: RCC_CSR
description: "MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR"
value: 0
- name: RCC_ICSCR1
description: "MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1"
value: 1
enum/MSIXSRANGE: enum/MSIXSRANGE:
bit_size: 4 bit_size: 4
variants: variants:
@ -2629,33 +2656,6 @@ enum/MSIXSRANGE:
- name: RANGE_3_072MHZ - name: RANGE_3_072MHZ
description: "range 8 around 3.072 MHz " description: "range 8 around 3.072 MHz "
value: 8 value: 8
enum/MSIPLLFAST:
bit_size: 1
variants:
- name: NORMAL
description: MSI PLL normal start-up
value: 0
- name: FAST
description: MSI PLL fast start-up
value: 1
enum/MSIPLLSEL:
bit_size: 1
variants:
- name: MSIK
description: "PLL mode applied to MSIK (MSI kernel) clock output "
value: 0
- name: MSIS
description: PLL mode applied to MSIS (MSI system) clock output
value: 1
enum/MSIRGSEL:
bit_size: 1
variants:
- name: RCC_CSR
description: "MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR"
value: 0
- name: RCC_ICSCR1
description: "MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1"
value: 1
enum/OCTOSPISEL: enum/OCTOSPISEL:
bit_size: 2 bit_size: 2
variants: variants:
@ -2758,6 +2758,15 @@ enum/PPRE:
- name: DIV16 - name: DIV16
description: HCLK divided by 16 description: HCLK divided by 16
value: 7 value: 7
enum/PRIV:
bit_size: 1
variants:
- name: UNPRIVILEGED
description: Read and write to secure functions can be done by privileged or unprivileged access.
value: 0
- name: PRIVILEGED
description: Read and write to secure functions can be done by privileged access only.
value: 1
enum/RNGSEL: enum/RNGSEL:
bit_size: 2 bit_size: 2
variants: variants:
@ -2821,6 +2830,15 @@ enum/SDMMCSEL:
- name: PLL1_P - name: PLL1_P
description: "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) " description: "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) "
value: 1 value: 1
enum/SECURITY:
bit_size: 1
variants:
- name: NON_SECURE
description: non secure
value: 0
- name: SECURE
description: secure
value: 1
enum/SPISEL: enum/SPISEL:
bit_size: 2 bit_size: 2
variants: variants:
@ -2929,21 +2947,3 @@ enum/USARTSEL:
- name: LSE - name: LSE
description: LSE selected description: LSE selected
value: 3 value: 3
enum/SECURITY:
bit_size: 1
variants:
- name: NON_SECURE
description: non secure
value: 0
- name: SECURE
description: secure
value: 1
enum/PRIV:
bit_size: 1
variants:
- name: UNPRIVILEGED
description: Read and write to secure functions can be done by privileged or unprivileged access.
value: 0
- name: PRIVILEGED
description: Read and write to secure functions can be done by privileged access only.
value: 1

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data/registers/rtc_v2.yaml
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data/registers/sai_v1.yaml
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897
data/registers/sdmmc_v1.yaml
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@ -2,506 +2,505 @@
block/SDMMC: block/SDMMC:
description: Secure digital input/output interface description: Secure digital input/output interface
items: items:
- byte_offset: 0 - name: POWER
description: power control register description: power control register
fieldset: POWER byte_offset: 0
name: POWER fieldset: POWER
- byte_offset: 4 - name: CLKCR
description: SDI clock control register description: SDI clock control register
fieldset: CLKCR byte_offset: 4
name: CLKCR fieldset: CLKCR
- byte_offset: 8 - name: ARG
description: argument register description: argument register
fieldset: ARG byte_offset: 8
name: ARG fieldset: ARG
- byte_offset: 12 - name: CMD
description: command register description: command register
fieldset: CMD byte_offset: 12
name: CMD fieldset: CMD
- access: Read - name: RESPCMD
byte_offset: 16 description: command response register
description: command response register byte_offset: 16
fieldset: RESPCMD access: Read
name: RESPCMD fieldset: RESPCMD
- access: Read - name: RESP1
byte_offset: 20 description: response 1..4 register
description: response 1..4 register byte_offset: 20
fieldset: RESP1 access: Read
name: RESP1 fieldset: RESP1
- access: Read - name: RESP2
byte_offset: 24 description: response 1..4 register
description: response 1..4 register byte_offset: 24
fieldset: RESP2 access: Read
name: RESP2 fieldset: RESP2
- access: Read - name: RESP3
byte_offset: 28 description: response 1..4 register
description: response 1..4 register byte_offset: 28
fieldset: RESP3 access: Read
name: RESP3 fieldset: RESP3
- access: Read - name: RESP4
byte_offset: 32 description: response 1..4 register
description: response 1..4 register byte_offset: 32
fieldset: RESP4 access: Read
name: RESP4 fieldset: RESP4
- byte_offset: 36 - name: DTIMER
description: data timer register description: data timer register
fieldset: DTIMER byte_offset: 36
name: DTIMER fieldset: DTIMER
- byte_offset: 40 - name: DLEN
description: data length register description: data length register
fieldset: DLEN byte_offset: 40
name: DLEN fieldset: DLEN
- byte_offset: 44 - name: DCTRL
description: data control register description: data control register
fieldset: DCTRL byte_offset: 44
name: DCTRL fieldset: DCTRL
- access: Read - name: DCOUNT
byte_offset: 48 description: data counter register
description: data counter register byte_offset: 48
fieldset: DCOUNT access: Read
name: DCOUNT fieldset: DCOUNT
- access: Read - name: STA
byte_offset: 52 description: status register
description: status register byte_offset: 52
fieldset: STA access: Read
name: STA fieldset: STA
- byte_offset: 56 - name: ICR
description: interrupt clear register description: interrupt clear register
fieldset: ICR byte_offset: 56
name: ICR fieldset: ICR
- byte_offset: 60 - name: MASK
description: mask register description: mask register
fieldset: MASK byte_offset: 60
name: MASK fieldset: MASK
- access: Read - name: FIFOCNT
byte_offset: 72 description: FIFO counter register
description: FIFO counter register byte_offset: 72
fieldset: FIFOCNT access: Read
name: FIFOCNT fieldset: FIFOCNT
- byte_offset: 128 - name: FIFO
description: data FIFO register description: data FIFO register
fieldset: FIFO byte_offset: 128
name: FIFO fieldset: FIFO
fieldset/ARG: fieldset/ARG:
description: argument register description: argument register
fields: fields:
- bit_offset: 0 - name: CMDARG
bit_size: 32 description: Command argument
description: Command argument bit_offset: 0
name: CMDARG bit_size: 32
fieldset/CLKCR: fieldset/CLKCR:
description: SDI clock control register description: SDI clock control register
fields: fields:
- bit_offset: 0 - name: CLKDIV
bit_size: 8 description: Clock divide factor
description: Clock divide factor bit_offset: 0
name: CLKDIV bit_size: 8
- bit_offset: 8 - name: CLKEN
bit_size: 1 description: Clock enable bit
description: Clock enable bit bit_offset: 8
name: CLKEN bit_size: 1
- bit_offset: 9 - name: PWRSAV
bit_size: 1 description: Power saving configuration bit
description: Power saving configuration bit bit_offset: 9
name: PWRSAV bit_size: 1
- bit_offset: 10 - name: BYPASS
bit_size: 1 description: Clock divider bypass enable bit
description: Clock divider bypass enable bit bit_offset: 10
name: BYPASS bit_size: 1
- bit_offset: 11 - name: WIDBUS
bit_size: 2 description: Wide bus mode enable bit
description: Wide bus mode enable bit bit_offset: 11
name: WIDBUS bit_size: 2
- bit_offset: 13 - name: NEGEDGE
bit_size: 1 description: SDIO_CK dephasing selection bit
description: SDIO_CK dephasing selection bit bit_offset: 13
name: NEGEDGE bit_size: 1
- bit_offset: 14 - name: HWFC_EN
bit_size: 1 description: HW Flow Control enable
description: HW Flow Control enable bit_offset: 14
name: HWFC_EN bit_size: 1
fieldset/CMD: fieldset/CMD:
description: command register description: command register
fields: fields:
- bit_offset: 0 - name: CMDINDEX
bit_size: 6 description: Command index
description: Command index bit_offset: 0
name: CMDINDEX bit_size: 6
- bit_offset: 6 - name: WAITRESP
bit_size: 2 description: Wait for response bits
description: Wait for response bits bit_offset: 6
name: WAITRESP bit_size: 2
- bit_offset: 8 - name: WAITINT
bit_size: 1 description: CPSM waits for interrupt request
description: CPSM waits for interrupt request bit_offset: 8
name: WAITINT bit_size: 1
- bit_offset: 9 - name: WAITPEND
bit_size: 1 description: CPSM Waits for ends of data transfer (CmdPend internal signal)
description: CPSM Waits for ends of data transfer (CmdPend internal signal) bit_offset: 9
name: WAITPEND bit_size: 1
- bit_offset: 10 - name: CPSMEN
bit_size: 1 description: Command path state machine (CPSM) Enable bit
description: Command path state machine (CPSM) Enable bit bit_offset: 10
name: CPSMEN bit_size: 1
- bit_offset: 11 - name: SDIOSuspend
bit_size: 1 description: SD I/O suspend command
description: SD I/O suspend command bit_offset: 11
name: SDIOSuspend bit_size: 1
fieldset/DCOUNT: fieldset/DCOUNT:
description: data counter register description: data counter register
fields: fields:
- bit_offset: 0 - name: DATACOUNT
bit_size: 25 description: Data count value
description: Data count value bit_offset: 0
name: DATACOUNT bit_size: 25
fieldset/DCTRL: fieldset/DCTRL:
description: data control register description: data control register
fields: fields:
- bit_offset: 0 - name: DTEN
bit_size: 1 description: DTEN
description: DTEN bit_offset: 0
name: DTEN bit_size: 1
- bit_offset: 1 - name: DTDIR
bit_size: 1 description: Data transfer direction selection
description: Data transfer direction selection bit_offset: 1
name: DTDIR bit_size: 1
- bit_offset: 2 - name: DTMODE
bit_size: 1 description: "Data transfer mode selection 1: Stream or SDIO multibyte data transfer"
description: 'Data transfer mode selection 1: Stream or SDIO multibyte data transfer' bit_offset: 2
name: DTMODE bit_size: 1
- bit_offset: 3 - name: DMAEN
bit_size: 1 description: DMA enable bit
description: DMA enable bit bit_offset: 3
name: DMAEN bit_size: 1
- bit_offset: 4 - name: DBLOCKSIZE
bit_size: 4 description: Data block size
description: Data block size bit_offset: 4
name: DBLOCKSIZE bit_size: 4
- bit_offset: 8 - name: RWSTART
bit_size: 1 description: Read wait start
description: Read wait start bit_offset: 8
name: RWSTART bit_size: 1
- bit_offset: 9 - name: RWSTOP
bit_size: 1 description: Read wait stop
description: Read wait stop bit_offset: 9
name: RWSTOP bit_size: 1
- bit_offset: 10 - name: RWMOD
bit_size: 1 description: Read wait mode
description: Read wait mode bit_offset: 10
name: RWMOD bit_size: 1
- bit_offset: 11 - name: SDIOEN
bit_size: 1 description: SD I/O enable functions
description: SD I/O enable functions bit_offset: 11
name: SDIOEN bit_size: 1
fieldset/DLEN: fieldset/DLEN:
description: data length register description: data length register
fields: fields:
- bit_offset: 0 - name: DATALENGTH
bit_size: 25 description: Data length value
description: Data length value bit_offset: 0
name: DATALENGTH bit_size: 25
fieldset/DTIMER: fieldset/DTIMER:
description: data timer register description: data timer register
fields: fields:
- bit_offset: 0 - name: DATATIME
bit_size: 32 description: Data timeout period
description: Data timeout period bit_offset: 0
name: DATATIME bit_size: 32
fieldset/FIFO: fieldset/FIFO:
description: data FIFO register description: data FIFO register
fields: fields:
- bit_offset: 0 - name: FIFOData
bit_size: 32 description: Receive and transmit FIFO data
description: Receive and transmit FIFO data bit_offset: 0
name: FIFOData bit_size: 32
fieldset/FIFOCNT: fieldset/FIFOCNT:
description: FIFO counter register description: FIFO counter register
fields: fields:
- bit_offset: 0 - name: FIFOCOUNT
bit_size: 24 description: Remaining number of words to be written to or read from the FIFO
description: Remaining number of words to be written to or read from the FIFO bit_offset: 0
name: FIFOCOUNT bit_size: 24
fieldset/ICR: fieldset/ICR:
description: interrupt clear register description: interrupt clear register
fields: fields:
- bit_offset: 0 - name: CCRCFAILC
bit_size: 1 description: CCRCFAIL flag clear bit
description: CCRCFAIL flag clear bit bit_offset: 0
name: CCRCFAILC bit_size: 1
- bit_offset: 1 - name: DCRCFAILC
bit_size: 1 description: DCRCFAIL flag clear bit
description: DCRCFAIL flag clear bit bit_offset: 1
name: DCRCFAILC bit_size: 1
- bit_offset: 2 - name: CTIMEOUTC
bit_size: 1 description: CTIMEOUT flag clear bit
description: CTIMEOUT flag clear bit bit_offset: 2
name: CTIMEOUTC bit_size: 1
- bit_offset: 3 - name: DTIMEOUTC
bit_size: 1 description: DTIMEOUT flag clear bit
description: DTIMEOUT flag clear bit bit_offset: 3
name: DTIMEOUTC bit_size: 1
- bit_offset: 4 - name: TXUNDERRC
bit_size: 1 description: TXUNDERR flag clear bit
description: TXUNDERR flag clear bit bit_offset: 4
name: TXUNDERRC bit_size: 1
- bit_offset: 5 - name: RXOVERRC
bit_size: 1 description: RXOVERR flag clear bit
description: RXOVERR flag clear bit bit_offset: 5
name: RXOVERRC bit_size: 1
- bit_offset: 6 - name: CMDRENDC
bit_size: 1 description: CMDREND flag clear bit
description: CMDREND flag clear bit bit_offset: 6
name: CMDRENDC bit_size: 1
- bit_offset: 7 - name: CMDSENTC
bit_size: 1 description: CMDSENT flag clear bit
description: CMDSENT flag clear bit bit_offset: 7
name: CMDSENTC bit_size: 1
- bit_offset: 8 - name: DATAENDC
bit_size: 1 description: DATAEND flag clear bit
description: DATAEND flag clear bit bit_offset: 8
name: DATAENDC bit_size: 1
- bit_offset: 10 - name: DBCKENDC
bit_size: 1 description: DBCKEND flag clear bit
description: DBCKEND flag clear bit bit_offset: 10
name: DBCKENDC bit_size: 1
- bit_offset: 22 - name: SDIOITC
bit_size: 1 description: SDIOIT flag clear bit
description: SDIOIT flag clear bit bit_offset: 22
name: SDIOITC bit_size: 1
fieldset/MASK: fieldset/MASK:
description: mask register description: mask register
fields: fields:
- bit_offset: 0 - name: CCRCFAILIE
bit_size: 1 description: Command CRC fail interrupt enable
description: Command CRC fail interrupt enable bit_offset: 0
name: CCRCFAILIE bit_size: 1
- bit_offset: 1 - name: DCRCFAILIE
bit_size: 1 description: Data CRC fail interrupt enable
description: Data CRC fail interrupt enable bit_offset: 1
name: DCRCFAILIE bit_size: 1
- bit_offset: 2 - name: CTIMEOUTIE
bit_size: 1 description: Command timeout interrupt enable
description: Command timeout interrupt enable bit_offset: 2
name: CTIMEOUTIE bit_size: 1
- bit_offset: 3 - name: DTIMEOUTIE
bit_size: 1 description: Data timeout interrupt enable
description: Data timeout interrupt enable bit_offset: 3
name: DTIMEOUTIE bit_size: 1
- bit_offset: 4 - name: TXUNDERRIE
bit_size: 1 description: Tx FIFO underrun error interrupt enable
description: Tx FIFO underrun error interrupt enable bit_offset: 4
name: TXUNDERRIE bit_size: 1
- bit_offset: 5 - name: RXOVERRIE
bit_size: 1 description: Rx FIFO overrun error interrupt enable
description: Rx FIFO overrun error interrupt enable bit_offset: 5
name: RXOVERRIE bit_size: 1
- bit_offset: 6 - name: CMDRENDIE
bit_size: 1 description: Command response received interrupt enable
description: Command response received interrupt enable bit_offset: 6
name: CMDRENDIE bit_size: 1
- bit_offset: 7 - name: CMDSENTIE
bit_size: 1 description: Command sent interrupt enable
description: Command sent interrupt enable bit_offset: 7
name: CMDSENTIE bit_size: 1
- bit_offset: 8 - name: DATAENDIE
bit_size: 1 description: Data end interrupt enable
description: Data end interrupt enable bit_offset: 8
name: DATAENDIE bit_size: 1
- bit_offset: 10 - name: DBCKENDIE
bit_size: 1 description: Data block end interrupt enable
description: Data block end interrupt enable bit_offset: 10
name: DBCKENDIE bit_size: 1
- bit_offset: 11 - name: CMDACTIE
bit_size: 1 description: Command acting interrupt enable
description: Command acting interrupt enable bit_offset: 11
name: CMDACTIE bit_size: 1
- bit_offset: 12 - name: TXACTIE
bit_size: 1 description: Data transmit acting interrupt enable
description: Data transmit acting interrupt enable bit_offset: 12
name: TXACTIE bit_size: 1
- bit_offset: 13 - name: RXACTIE
bit_size: 1 description: Data receive acting interrupt enable
description: Data receive acting interrupt enable bit_offset: 13
name: RXACTIE bit_size: 1
- bit_offset: 14 - name: TXFIFOHEIE
bit_size: 1 description: Tx FIFO half empty interrupt enable
description: Tx FIFO half empty interrupt enable bit_offset: 14
name: TXFIFOHEIE bit_size: 1
- bit_offset: 15 - name: RXFIFOHFIE
bit_size: 1 description: Rx FIFO half full interrupt enable
description: Rx FIFO half full interrupt enable bit_offset: 15
name: RXFIFOHFIE bit_size: 1
- bit_offset: 16 - name: TXFIFOFIE
bit_size: 1 description: Tx FIFO full interrupt enable
description: Tx FIFO full interrupt enable bit_offset: 16
name: TXFIFOFIE bit_size: 1
- bit_offset: 17 - name: RXFIFOFIE
bit_size: 1 description: Rx FIFO full interrupt enable
description: Rx FIFO full interrupt enable bit_offset: 17
name: RXFIFOFIE bit_size: 1
- bit_offset: 18 - name: TXFIFOEIE
bit_size: 1 description: Tx FIFO empty interrupt enable
description: Tx FIFO empty interrupt enable bit_offset: 18
name: TXFIFOEIE bit_size: 1
- bit_offset: 19 - name: RXFIFOEIE
bit_size: 1 description: Rx FIFO empty interrupt enable
description: Rx FIFO empty interrupt enable bit_offset: 19
name: RXFIFOEIE bit_size: 1
- bit_offset: 20 - name: TXDAVLIE
bit_size: 1 description: Data available in Tx FIFO interrupt enable
description: Data available in Tx FIFO interrupt enable bit_offset: 20
name: TXDAVLIE bit_size: 1
- bit_offset: 21 - name: RXDAVLIE
bit_size: 1 description: Data available in Rx FIFO interrupt enable
description: Data available in Rx FIFO interrupt enable bit_offset: 21
name: RXDAVLIE bit_size: 1
- bit_offset: 22 - name: SDIOITIE
bit_size: 1 description: SDIO mode interrupt received interrupt enable
description: SDIO mode interrupt received interrupt enable bit_offset: 22
name: SDIOITIE bit_size: 1
fieldset/POWER: fieldset/POWER:
description: power control register description: power control register
fields: fields:
- bit_offset: 0 - name: PWRCTRL
bit_size: 2 description: PWRCTRL
description: PWRCTRL bit_offset: 0
name: PWRCTRL bit_size: 2
fieldset/RESP1: fieldset/RESP1:
description: response 1..4 register description: response 1..4 register
fields: fields:
- array: - name: CARDSTATUS
len: 1 description: see Table 132
stride: 0 bit_offset: 0
bit_offset: 0 bit_size: 32
bit_size: 32 array:
description: see Table 132 len: 1
name: CARDSTATUS stride: 0
fieldset/RESP2: fieldset/RESP2:
description: response 1..4 register description: response 1..4 register
fields: fields:
- array: - name: CARDSTATUS
len: 1 description: see Table 132
stride: 0 bit_offset: 0
bit_offset: 0 bit_size: 32
bit_size: 32 array:
description: see Table 132 len: 1
name: CARDSTATUS stride: 0
fieldset/RESP3: fieldset/RESP3:
description: response 1..4 register description: response 1..4 register
fields: fields:
- array: - name: CARDSTATUS
len: 1 description: see Table 132
stride: 0 bit_offset: 0
bit_offset: 0 bit_size: 32
bit_size: 32 array:
description: see Table 132 len: 1
name: CARDSTATUS stride: 0
fieldset/RESP4: fieldset/RESP4:
description: response 1..4 register description: response 1..4 register
fields: fields:
- array: - name: CARDSTATUS
len: 1 description: see Table 132
stride: 0 bit_offset: 0
bit_offset: 0 bit_size: 32
bit_size: 32 array:
description: see Table 132 len: 1
name: CARDSTATUS stride: 0
fieldset/RESPCMD: fieldset/RESPCMD:
description: command response register description: command response register
fields: fields:
- bit_offset: 0 - name: RESPCMD
bit_size: 6 description: Response command index
description: Response command index bit_offset: 0
name: RESPCMD bit_size: 6
fieldset/STA: fieldset/STA:
description: status register description: status register
fields: fields:
- bit_offset: 0 - name: CCRCFAIL
bit_size: 1 description: Command response received (CRC check failed)
description: Command response received (CRC check failed) bit_offset: 0
name: CCRCFAIL bit_size: 1
- bit_offset: 1 - name: DCRCFAIL
bit_size: 1 description: Data block sent/received (CRC check failed)
description: Data block sent/received (CRC check failed) bit_offset: 1
name: DCRCFAIL bit_size: 1
- bit_offset: 2 - name: CTIMEOUT
bit_size: 1 description: Command response timeout
description: Command response timeout bit_offset: 2
name: CTIMEOUT bit_size: 1
- bit_offset: 3 - name: DTIMEOUT
bit_size: 1 description: Data timeout
description: Data timeout bit_offset: 3
name: DTIMEOUT bit_size: 1
- bit_offset: 4 - name: TXUNDERR
bit_size: 1 description: Transmit FIFO underrun error
description: Transmit FIFO underrun error bit_offset: 4
name: TXUNDERR bit_size: 1
- bit_offset: 5 - name: RXOVERR
bit_size: 1 description: Received FIFO overrun error
description: Received FIFO overrun error bit_offset: 5
name: RXOVERR bit_size: 1
- bit_offset: 6 - name: CMDREND
bit_size: 1 description: Command response received (CRC check passed)
description: Command response received (CRC check passed) bit_offset: 6
name: CMDREND bit_size: 1
- bit_offset: 7 - name: CMDSENT
bit_size: 1 description: Command sent (no response required)
description: Command sent (no response required) bit_offset: 7
name: CMDSENT bit_size: 1
- bit_offset: 8 - name: DATAEND
bit_size: 1 description: "Data end (data counter, SDIDCOUNT, is zero)"
description: Data end (data counter, SDIDCOUNT, is zero) bit_offset: 8
name: DATAEND bit_size: 1
- bit_offset: 10 - name: DBCKEND
bit_size: 1 description: Data block sent/received (CRC check passed)
description: Data block sent/received (CRC check passed) bit_offset: 10
name: DBCKEND bit_size: 1
- bit_offset: 11 - name: CMDACT
bit_size: 1 description: Command transfer in progress
description: Command transfer in progress bit_offset: 11
name: CMDACT bit_size: 1
- bit_offset: 12 - name: TXACT
bit_size: 1 description: Data transmit in progress
description: Data transmit in progress bit_offset: 12
name: TXACT bit_size: 1
- bit_offset: 13 - name: RXACT
bit_size: 1 description: Data receive in progress
description: Data receive in progress bit_offset: 13
name: RXACT bit_size: 1
- bit_offset: 14 - name: TXFIFOHE
bit_size: 1 description: "Transmit FIFO half empty: at least 8 words can be written into the FIFO"
description: 'Transmit FIFO half empty: at least 8 words can be written into the bit_offset: 14
FIFO' bit_size: 1
name: TXFIFOHE - name: RXFIFOHF
- bit_offset: 15 description: "Receive FIFO half full: there are at least 8 words in the FIFO"
bit_size: 1 bit_offset: 15
description: 'Receive FIFO half full: there are at least 8 words in the FIFO' bit_size: 1
name: RXFIFOHF - name: TXFIFOF
- bit_offset: 16 description: Transmit FIFO full
bit_size: 1 bit_offset: 16
description: Transmit FIFO full bit_size: 1
name: TXFIFOF - name: RXFIFOF
- bit_offset: 17 description: Receive FIFO full
bit_size: 1 bit_offset: 17
description: Receive FIFO full bit_size: 1
name: RXFIFOF - name: TXFIFOE
- bit_offset: 18 description: Transmit FIFO empty
bit_size: 1 bit_offset: 18
description: Transmit FIFO empty bit_size: 1
name: TXFIFOE - name: RXFIFOE
- bit_offset: 19 description: Receive FIFO empty
bit_size: 1 bit_offset: 19
description: Receive FIFO empty bit_size: 1
name: RXFIFOE - name: TXDAVL
- bit_offset: 20 description: Data available in transmit FIFO
bit_size: 1 bit_offset: 20
description: Data available in transmit FIFO bit_size: 1
name: TXDAVL - name: RXDAVL
- bit_offset: 21 description: Data available in receive FIFO
bit_size: 1 bit_offset: 21
description: Data available in receive FIFO bit_size: 1
name: RXDAVL - name: SDIOIT
- bit_offset: 22 description: SDIO interrupt received
bit_size: 1 bit_offset: 22
description: SDIO interrupt received bit_size: 1
name: SDIOIT

432
data/registers/spdifrx_v1.yaml
View File

@ -2,240 +2,240 @@
block/SPDIFRX: block/SPDIFRX:
description: Receiver Interface description: Receiver Interface
items: items:
- byte_offset: 0 - name: CR
description: Control register description: Control register
fieldset: CR byte_offset: 0
name: CR fieldset: CR
- byte_offset: 4 - name: IMR
description: Interrupt mask register description: Interrupt mask register
fieldset: IMR byte_offset: 4
name: IMR fieldset: IMR
- access: Read - name: SR
byte_offset: 8 description: Status register
description: Status register byte_offset: 8
fieldset: SR access: Read
name: SR fieldset: SR
- access: Write - name: IFCR
byte_offset: 12 description: Interrupt Flag Clear register
description: Interrupt Flag Clear register byte_offset: 12
fieldset: IFCR access: Write
name: IFCR fieldset: IFCR
- access: Read - name: DR
byte_offset: 16 description: Data input register
description: Data input register byte_offset: 16
fieldset: DR access: Read
name: DR fieldset: DR
- access: Read - name: CSR
byte_offset: 20 description: Channel Status register
description: Channel Status register byte_offset: 20
fieldset: CSR access: Read
name: CSR fieldset: CSR
- access: Read - name: DIR
byte_offset: 24 description: Debug Information register
description: Debug Information register byte_offset: 24
fieldset: DIR access: Read
name: DIR fieldset: DIR
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
- bit_offset: 0 - name: SPDIFEN
bit_size: 2 description: Peripheral Block Enable
description: Peripheral Block Enable bit_offset: 0
name: SPDIFEN bit_size: 2
- bit_offset: 2 - name: RXDMAEN
bit_size: 1 description: Receiver DMA ENable for data flow
description: Receiver DMA ENable for data flow bit_offset: 2
name: RXDMAEN bit_size: 1
- bit_offset: 3 - name: RXSTEO
bit_size: 1 description: STerEO Mode
description: STerEO Mode bit_offset: 3
name: RXSTEO bit_size: 1
- bit_offset: 4 - name: DRFMT
bit_size: 2 description: RX Data format
description: RX Data format bit_offset: 4
name: DRFMT bit_size: 2
- bit_offset: 6 - name: PMSK
bit_size: 1 description: Mask Parity error bit
description: Mask Parity error bit bit_offset: 6
name: PMSK bit_size: 1
- bit_offset: 7 - name: VMSK
bit_size: 1 description: Mask of Validity bit
description: Mask of Validity bit bit_offset: 7
name: VMSK bit_size: 1
- bit_offset: 8 - name: CUMSK
bit_size: 1 description: Mask of channel status and user bits
description: Mask of channel status and user bits bit_offset: 8
name: CUMSK bit_size: 1
- bit_offset: 9 - name: PTMSK
bit_size: 1 description: Mask of Preamble Type bits
description: Mask of Preamble Type bits bit_offset: 9
name: PTMSK bit_size: 1
- bit_offset: 10 - name: CBDMAEN
bit_size: 1 description: Control Buffer DMA ENable for control flow
description: Control Buffer DMA ENable for control flow bit_offset: 10
name: CBDMAEN bit_size: 1
- bit_offset: 11 - name: CHSEL
bit_size: 1 description: Channel Selection
description: Channel Selection bit_offset: 11
name: CHSEL bit_size: 1
- bit_offset: 12 - name: NBTR
bit_size: 2 description: Maximum allowed re-tries during synchronization phase
description: Maximum allowed re-tries during synchronization phase bit_offset: 12
name: NBTR bit_size: 2
- bit_offset: 14 - name: WFA
bit_size: 1 description: Wait For Activity
description: Wait For Activity bit_offset: 14
name: WFA bit_size: 1
- bit_offset: 16 - name: INSEL
bit_size: 3 description: input selection
description: input selection bit_offset: 16
name: INSEL bit_size: 3
fieldset/CSR: fieldset/CSR:
description: Channel Status register description: Channel Status register
fields: fields:
- bit_offset: 0 - name: USR
bit_size: 16 description: User data information
description: User data information bit_offset: 0
name: USR bit_size: 16
- bit_offset: 16 - name: CS
bit_size: 8 description: Channel A status information
description: Channel A status information bit_offset: 16
name: CS bit_size: 8
- bit_offset: 24 - name: SOB
bit_size: 1 description: Start Of Block
description: Start Of Block bit_offset: 24
name: SOB bit_size: 1
fieldset/DIR: fieldset/DIR:
description: Debug Information register description: Debug Information register
fields: fields:
- bit_offset: 0 - name: THI
bit_size: 13 description: Threshold HIGH
description: Threshold HIGH bit_offset: 0
name: THI bit_size: 13
- bit_offset: 16 - name: TLO
bit_size: 13 description: Threshold LOW
description: Threshold LOW bit_offset: 16
name: TLO bit_size: 13
fieldset/DR: fieldset/DR:
description: Data input register description: Data input register
fields: fields:
- bit_offset: 0 - name: DR
bit_size: 24 description: Parity Error bit
description: Parity Error bit bit_offset: 0
name: DR bit_size: 24
- bit_offset: 24 - name: PE
bit_size: 1 description: Parity Error bit
description: Parity Error bit bit_offset: 24
name: PE bit_size: 1
- bit_offset: 25 - name: V
bit_size: 1 description: Validity bit
description: Validity bit bit_offset: 25
name: V bit_size: 1
- bit_offset: 26 - name: U
bit_size: 1 description: User bit
description: User bit bit_offset: 26
name: U bit_size: 1
- bit_offset: 27 - name: C
bit_size: 1 description: Channel Status bit
description: Channel Status bit bit_offset: 27
name: C bit_size: 1
- bit_offset: 28 - name: PT
bit_size: 2 description: Preamble Type
description: Preamble Type bit_offset: 28
name: PT bit_size: 2
fieldset/IFCR: fieldset/IFCR:
description: Interrupt Flag Clear register description: Interrupt Flag Clear register
fields: fields:
- bit_offset: 2 - name: PERRCF
bit_size: 1 description: Clears the Parity error flag
description: Clears the Parity error flag bit_offset: 2
name: PERRCF bit_size: 1
- bit_offset: 3 - name: OVRCF
bit_size: 1 description: Clears the Overrun error flag
description: Clears the Overrun error flag bit_offset: 3
name: OVRCF bit_size: 1
- bit_offset: 4 - name: SBDCF
bit_size: 1 description: Clears the Synchronization Block Detected flag
description: Clears the Synchronization Block Detected flag bit_offset: 4
name: SBDCF bit_size: 1
- bit_offset: 5 - name: SYNCDCF
bit_size: 1 description: Clears the Synchronization Done flag
description: Clears the Synchronization Done flag bit_offset: 5
name: SYNCDCF bit_size: 1
fieldset/IMR: fieldset/IMR:
description: Interrupt mask register description: Interrupt mask register
fields: fields:
- bit_offset: 0 - name: RXNEIE
bit_size: 1 description: RXNE interrupt enable
description: RXNE interrupt enable bit_offset: 0
name: RXNEIE bit_size: 1
- bit_offset: 1 - name: CSRNEIE
bit_size: 1 description: Control Buffer Ready Interrupt Enable
description: Control Buffer Ready Interrupt Enable bit_offset: 1
name: CSRNEIE bit_size: 1
- bit_offset: 2 - name: PERRIE
bit_size: 1 description: Parity error interrupt enable
description: Parity error interrupt enable bit_offset: 2
name: PERRIE bit_size: 1
- bit_offset: 3 - name: OVRIE
bit_size: 1 description: Overrun error Interrupt Enable
description: Overrun error Interrupt Enable bit_offset: 3
name: OVRIE bit_size: 1
- bit_offset: 4 - name: SBLKIE
bit_size: 1 description: Synchronization Block Detected Interrupt Enable
description: Synchronization Block Detected Interrupt Enable bit_offset: 4
name: SBLKIE bit_size: 1
- bit_offset: 5 - name: SYNCDIE
bit_size: 1 description: Synchronization Done
description: Synchronization Done bit_offset: 5
name: SYNCDIE bit_size: 1
- bit_offset: 6 - name: IFEIE
bit_size: 1 description: Serial Interface Error Interrupt Enable
description: Serial Interface Error Interrupt Enable bit_offset: 6
name: IFEIE bit_size: 1
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- bit_offset: 0 - name: RXNE
bit_size: 1 description: Read data register not empty
description: Read data register not empty bit_offset: 0
name: RXNE bit_size: 1
- bit_offset: 1 - name: CSRNE
bit_size: 1 description: Control Buffer register is not empty
description: Control Buffer register is not empty bit_offset: 1
name: CSRNE bit_size: 1
- bit_offset: 2 - name: PERR
bit_size: 1 description: Parity error
description: Parity error bit_offset: 2
name: PERR bit_size: 1
- bit_offset: 3 - name: OVR
bit_size: 1 description: Overrun error
description: Overrun error bit_offset: 3
name: OVR bit_size: 1
- bit_offset: 4 - name: SBD
bit_size: 1 description: Synchronization Block Detected
description: Synchronization Block Detected bit_offset: 4
name: SBD bit_size: 1
- bit_offset: 5 - name: SYNCD
bit_size: 1 description: Synchronization Done
description: Synchronization Done bit_offset: 5
name: SYNCD bit_size: 1
- bit_offset: 6 - name: FERR
bit_size: 1 description: Framing error
description: Framing error bit_offset: 6
name: FERR bit_size: 1
- bit_offset: 7 - name: SERR
bit_size: 1 description: Synchronization error
description: Synchronization error bit_offset: 7
name: SERR bit_size: 1
- bit_offset: 8 - name: TERR
bit_size: 1 description: Time-out error
description: Time-out error bit_offset: 8
name: TERR bit_size: 1
- array: - name: WIDTH
len: 1 description: Duration of 5 symbols counted with SPDIF_CLK
stride: 0 bit_offset: 16
bit_offset: 16 bit_size: 15
bit_size: 15 array:
description: Duration of 5 symbols counted with SPDIF_CLK len: 1
name: WIDTH stride: 0

906
data/registers/spi_f1.yaml
View File

@ -2,483 +2,483 @@
block/SPI: block/SPI:
description: Serial peripheral interface description: Serial peripheral interface
items: items:
- byte_offset: 0 - name: CR1
description: control register 1 description: control register 1
fieldset: CR1 byte_offset: 0
name: CR1 fieldset: CR1
- byte_offset: 4 - name: CR2
description: control register 2 description: control register 2
fieldset: CR2 byte_offset: 4
name: CR2 fieldset: CR2
- byte_offset: 8 - name: SR
description: status register description: status register
fieldset: SR byte_offset: 8
name: SR fieldset: SR
- byte_offset: 12 - name: DR
description: data register description: data register
fieldset: DR byte_offset: 12
name: DR fieldset: DR
- byte_offset: 16 - name: CRCPR
description: CRC polynomial register description: CRC polynomial register
fieldset: CRCPR byte_offset: 16
name: CRCPR fieldset: CRCPR
- access: Read - name: RXCRCR
byte_offset: 20 description: RX CRC register
description: RX CRC register byte_offset: 20
fieldset: RXCRCR access: Read
name: RXCRCR fieldset: RXCRCR
- access: Read - name: TXCRCR
byte_offset: 24 description: TX CRC register
description: TX CRC register byte_offset: 24
fieldset: TXCRCR access: Read
name: TXCRCR fieldset: TXCRCR
- byte_offset: 28 - name: I2SCFGR
description: I2S configuration register description: I2S configuration register
fieldset: I2SCFGR byte_offset: 28
name: I2SCFGR fieldset: I2SCFGR
- byte_offset: 32 - name: I2SPR
description: I2S prescaler register description: I2S prescaler register
fieldset: I2SPR byte_offset: 32
name: I2SPR fieldset: I2SPR
enum/BIDIMODE:
bit_size: 1
variants:
- description: 2-line unidirectional data mode selected
name: Unidirectional
value: 0
- description: 1-line bidirectional data mode selected
name: Bidirectional
value: 1
enum/BIDIOE:
bit_size: 1
variants:
- description: Output disabled (receive-only mode)
name: OutputDisabled
value: 0
- description: Output enabled (transmit-only mode)
name: OutputEnabled
value: 1
enum/BR:
bit_size: 3
variants:
- description: f_PCLK / 2
name: Div2
value: 0
- description: f_PCLK / 4
name: Div4
value: 1
- description: f_PCLK / 8
name: Div8
value: 2
- description: f_PCLK / 16
name: Div16
value: 3
- description: f_PCLK / 32
name: Div32
value: 4
- description: f_PCLK / 64
name: Div64
value: 5
- description: f_PCLK / 128
name: Div128
value: 6
- description: f_PCLK / 256
name: Div256
value: 7
enum/CHLEN:
bit_size: 1
variants:
- description: 16-bit wide
name: SixteenBit
value: 0
- description: 32-bit wide
name: ThirtyTwoBit
value: 1
enum/CHSIDE:
bit_size: 1
variants:
- description: Channel left has to be transmitted or has been received
name: Left
value: 0
- description: Channel right has to be transmitted or has been received
name: Right
value: 1
enum/CKPOL:
bit_size: 1
variants:
- description: I2S clock inactive state is low level
name: IdleLow
value: 0
- description: I2S clock inactive state is high level
name: IdleHigh
value: 1
enum/CPHA:
bit_size: 1
variants:
- description: The first clock transition is the first data capture edge
name: FirstEdge
value: 0
- description: The second clock transition is the first data capture edge
name: SecondEdge
value: 1
enum/CPOL:
bit_size: 1
variants:
- description: CK to 0 when idle
name: IdleLow
value: 0
- description: CK to 1 when idle
name: IdleHigh
value: 1
enum/CRCNEXT:
bit_size: 1
variants:
- description: Next transmit value is from Tx buffer
name: TxBuffer
value: 0
- description: Next transmit value is from Tx CRC register
name: CRC
value: 1
enum/DATLEN:
bit_size: 2
variants:
- description: 16-bit data length
name: SixteenBit
value: 0
- description: 24-bit data length
name: TwentyFourBit
value: 1
- description: 32-bit data length
name: ThirtyTwoBit
value: 2
enum/DFF:
bit_size: 1
variants:
- description: 8-bit data frame format is selected for transmission/reception
name: EightBit
value: 0
- description: 16-bit data frame format is selected for transmission/reception
name: SixteenBit
value: 1
enum/ERRIE:
bit_size: 1
variants:
- description: Error interrupt masked
name: Masked
value: 0
- description: Error interrupt not masked
name: NotMasked
value: 1
enum/ISCFG:
bit_size: 2
variants:
- description: Slave - transmit
name: SlaveTx
value: 0
- description: Slave - receive
name: SlaveRx
value: 1
- description: Master - transmit
name: MasterTx
value: 2
- description: Master - receive
name: MasterRx
value: 3
enum/ISMOD:
bit_size: 1
variants:
- description: SPI mode is selected
name: SPIMode
value: 0
- description: I2S mode is selected
name: I2SMode
value: 1
enum/ISSTD:
bit_size: 2
variants:
- description: I2S Philips standard
name: Philips
value: 0
- description: MSB justified standard
name: MSB
value: 1
- description: LSB justified standard
name: LSB
value: 2
- description: PCM standard
name: PCM
value: 3
enum/LSBFIRST:
bit_size: 1
variants:
- description: Data is transmitted/received with the MSB first
name: MSBFirst
value: 0
- description: Data is transmitted/received with the LSB first
name: LSBFirst
value: 1
enum/MSTR:
bit_size: 1
variants:
- description: Slave configuration
name: Slave
value: 0
- description: Master configuration
name: Master
value: 1
enum/ODD:
bit_size: 1
variants:
- description: Real divider value is I2SDIV * 2
name: Even
value: 0
- description: Real divider value is (I2SDIV * 2) + 1
name: Odd
value: 1
enum/OVRR:
bit_size: 1
variants:
- description: No overrun occurred
name: NoOverrun
value: 0
- description: Overrun occurred
name: Overrun
value: 1
enum/PCMSYNC:
bit_size: 1
variants:
- description: Short frame synchronisation
name: Short
value: 0
- description: Long frame synchronisation
name: Long
value: 1
enum/RXONLY:
bit_size: 1
variants:
- description: Full duplex (Transmit and receive)
name: FullDuplex
value: 0
- description: Output disabled (Receive-only mode)
name: OutputDisabled
value: 1
fieldset/CR1: fieldset/CR1:
description: control register 1 description: control register 1
fields: fields:
- bit_offset: 0 - name: CPHA
bit_size: 1 description: Clock phase
description: Clock phase bit_offset: 0
enum: CPHA bit_size: 1
name: CPHA enum: CPHA
- bit_offset: 1 - name: CPOL
bit_size: 1 description: Clock polarity
description: Clock polarity bit_offset: 1
enum: CPOL bit_size: 1
name: CPOL enum: CPOL
- bit_offset: 2 - name: MSTR
bit_size: 1 description: Master selection
description: Master selection bit_offset: 2
enum: MSTR bit_size: 1
name: MSTR enum: MSTR
- bit_offset: 3 - name: BR
bit_size: 3 description: Baud rate control
description: Baud rate control bit_offset: 3
enum: BR bit_size: 3
name: BR enum: BR
- bit_offset: 6 - name: SPE
bit_size: 1 description: SPI enable
description: SPI enable bit_offset: 6
name: SPE bit_size: 1
- bit_offset: 7 - name: LSBFIRST
bit_size: 1 description: Frame format
description: Frame format bit_offset: 7
enum: LSBFIRST bit_size: 1
name: LSBFIRST enum: LSBFIRST
- bit_offset: 8 - name: SSI
bit_size: 1 description: Internal slave select
description: Internal slave select bit_offset: 8
name: SSI bit_size: 1
- bit_offset: 9 - name: SSM
bit_size: 1 description: Software slave management
description: Software slave management bit_offset: 9
name: SSM bit_size: 1
- bit_offset: 10 - name: RXONLY
bit_size: 1 description: Receive only
description: Receive only bit_offset: 10
enum: RXONLY bit_size: 1
name: RXONLY enum: RXONLY
- bit_offset: 11 - name: DFF
bit_size: 1 description: Data frame format
description: Data frame format bit_offset: 11
enum: DFF bit_size: 1
name: DFF enum: DFF
- bit_offset: 12 - name: CRCNEXT
bit_size: 1 description: CRC transfer next
description: CRC transfer next bit_offset: 12
enum: CRCNEXT bit_size: 1
name: CRCNEXT enum: CRCNEXT
- bit_offset: 13 - name: CRCEN
bit_size: 1 description: Hardware CRC calculation enable
description: Hardware CRC calculation enable bit_offset: 13
name: CRCEN bit_size: 1
- bit_offset: 14 - name: BIDIOE
bit_size: 1 description: Output enable in bidirectional mode
description: Output enable in bidirectional mode bit_offset: 14
enum: BIDIOE bit_size: 1
name: BIDIOE enum: BIDIOE
- bit_offset: 15 - name: BIDIMODE
bit_size: 1 description: Bidirectional data mode enable
description: Bidirectional data mode enable bit_offset: 15
enum: BIDIMODE bit_size: 1
name: BIDIMODE enum: BIDIMODE
fieldset/CR2: fieldset/CR2:
description: control register 2 description: control register 2
fields: fields:
- bit_offset: 0 - name: RXDMAEN
bit_size: 1 description: Rx buffer DMA enable
description: Rx buffer DMA enable bit_offset: 0
name: RXDMAEN bit_size: 1
- bit_offset: 1 - name: TXDMAEN
bit_size: 1 description: Tx buffer DMA enable
description: Tx buffer DMA enable bit_offset: 1
name: TXDMAEN bit_size: 1
- bit_offset: 2 - name: SSOE
bit_size: 1 description: SS output enable
description: SS output enable bit_offset: 2
name: SSOE bit_size: 1
- bit_offset: 5 - name: ERRIE
bit_size: 1 description: Error interrupt enable
description: Error interrupt enable bit_offset: 5
enum: ERRIE bit_size: 1
name: ERRIE enum: ERRIE
- bit_offset: 6 - name: RXNEIE
bit_size: 1 description: RX buffer not empty interrupt enable
description: RX buffer not empty interrupt enable bit_offset: 6
name: RXNEIE bit_size: 1
- bit_offset: 7 - name: TXEIE
bit_size: 1 description: Tx buffer empty interrupt enable
description: Tx buffer empty interrupt enable bit_offset: 7
name: TXEIE bit_size: 1
fieldset/CRCPR: fieldset/CRCPR:
description: CRC polynomial register description: CRC polynomial register
fields: fields:
- bit_offset: 0 - name: CRCPOLY
bit_size: 16 description: CRC polynomial register
description: CRC polynomial register bit_offset: 0
name: CRCPOLY bit_size: 16
fieldset/DR: fieldset/DR:
description: data register description: data register
fields: fields:
- bit_offset: 0 - name: DR
bit_size: 16 description: Data register
description: Data register bit_offset: 0
name: DR bit_size: 16
fieldset/I2SCFGR: fieldset/I2SCFGR:
description: I2S configuration register description: I2S configuration register
fields: fields:
- bit_offset: 0 - name: CHLEN
bit_size: 1 description: Channel length (number of bits per audio channel)
description: Channel length (number of bits per audio channel) bit_offset: 0
enum: CHLEN bit_size: 1
name: CHLEN enum: CHLEN
- bit_offset: 1 - name: DATLEN
bit_size: 2 description: Data length to be transferred
description: Data length to be transferred bit_offset: 1
enum: DATLEN bit_size: 2
name: DATLEN enum: DATLEN
- bit_offset: 3 - name: CKPOL
bit_size: 1 description: Steady state clock polarity
description: Steady state clock polarity bit_offset: 3
enum: CKPOL bit_size: 1
name: CKPOL enum: CKPOL
- bit_offset: 4 - name: I2SSTD
bit_size: 2 description: I2S standard selection
description: I2S standard selection bit_offset: 4
enum: ISSTD bit_size: 2
name: I2SSTD enum: ISSTD
- bit_offset: 7 - name: PCMSYNC
bit_size: 1 description: PCM frame synchronization
description: PCM frame synchronization bit_offset: 7
enum: PCMSYNC bit_size: 1
name: PCMSYNC enum: PCMSYNC
- bit_offset: 8 - name: I2SCFG
bit_size: 2 description: I2S configuration mode
description: I2S configuration mode bit_offset: 8
enum: ISCFG bit_size: 2
name: I2SCFG enum: ISCFG
- bit_offset: 10 - name: I2SE
bit_size: 1 description: I2S Enable
description: I2S Enable bit_offset: 10
name: I2SE bit_size: 1
- bit_offset: 11 - name: I2SMOD
bit_size: 1 description: I2S mode selection
description: I2S mode selection bit_offset: 11
enum: ISMOD bit_size: 1
name: I2SMOD enum: ISMOD
fieldset/I2SPR: fieldset/I2SPR:
description: I2S prescaler register description: I2S prescaler register
fields: fields:
- bit_offset: 0 - name: I2SDIV
bit_size: 8 description: I2S Linear prescaler
description: I2S Linear prescaler bit_offset: 0
name: I2SDIV bit_size: 8
- bit_offset: 8 - name: ODD
bit_size: 1 description: Odd factor for the prescaler
description: Odd factor for the prescaler bit_offset: 8
enum: ODD bit_size: 1
name: ODD enum: ODD
- bit_offset: 9 - name: MCKOE
bit_size: 1 description: Master clock output enable
description: Master clock output enable bit_offset: 9
name: MCKOE bit_size: 1
fieldset/RXCRCR: fieldset/RXCRCR:
description: RX CRC register description: RX CRC register
fields: fields:
- bit_offset: 0 - name: RxCRC
bit_size: 16 description: Rx CRC register
description: Rx CRC register bit_offset: 0
name: RxCRC bit_size: 16
fieldset/SR: fieldset/SR:
description: status register description: status register
fields: fields:
- bit_offset: 0 - name: RXNE
bit_size: 1 description: Receive buffer not empty
description: Receive buffer not empty bit_offset: 0
name: RXNE bit_size: 1
- bit_offset: 1 - name: TXE
bit_size: 1 description: Transmit buffer empty
description: Transmit buffer empty bit_offset: 1
name: TXE bit_size: 1
- bit_offset: 2 - name: CHSIDE
bit_size: 1 description: Channel side
description: Channel side bit_offset: 2
enum: CHSIDE bit_size: 1
name: CHSIDE enum: CHSIDE
- bit_offset: 3 - name: UDR
bit_size: 1 description: Underrun flag
description: Underrun flag bit_offset: 3
name: UDR bit_size: 1
- bit_offset: 4 - name: CRCERR
bit_size: 1 description: CRC error flag
description: CRC error flag bit_offset: 4
name: CRCERR bit_size: 1
- bit_offset: 5 - name: MODF
bit_size: 1 description: Mode fault
description: Mode fault bit_offset: 5
name: MODF bit_size: 1
- bit_offset: 6 - name: OVR
bit_size: 1 description: Overrun flag
description: Overrun flag bit_offset: 6
enum_read: OVRR bit_size: 1
name: OVR enum_read: OVRR
- bit_offset: 7 - name: BSY
bit_size: 1 description: Busy flag
description: Busy flag bit_offset: 7
name: BSY bit_size: 1
fieldset/TXCRCR: fieldset/TXCRCR:
description: TX CRC register description: TX CRC register
fields: fields:
- bit_offset: 0 - name: TxCRC
bit_size: 16 description: Tx CRC register
description: Tx CRC register bit_offset: 0
name: TxCRC bit_size: 16
enum/BIDIMODE:
bit_size: 1
variants:
- name: Unidirectional
description: 2-line unidirectional data mode selected
value: 0
- name: Bidirectional
description: 1-line bidirectional data mode selected
value: 1
enum/BIDIOE:
bit_size: 1
variants:
- name: OutputDisabled
description: Output disabled (receive-only mode)
value: 0
- name: OutputEnabled
description: Output enabled (transmit-only mode)
value: 1
enum/BR:
bit_size: 3
variants:
- name: Div2
description: f_PCLK / 2
value: 0
- name: Div4
description: f_PCLK / 4
value: 1
- name: Div8
description: f_PCLK / 8
value: 2
- name: Div16
description: f_PCLK / 16
value: 3
- name: Div32
description: f_PCLK / 32
value: 4
- name: Div64
description: f_PCLK / 64
value: 5
- name: Div128
description: f_PCLK / 128
value: 6
- name: Div256
description: f_PCLK / 256
value: 7
enum/CHLEN:
bit_size: 1
variants:
- name: SixteenBit
description: 16-bit wide
value: 0
- name: ThirtyTwoBit
description: 32-bit wide
value: 1
enum/CHSIDE:
bit_size: 1
variants:
- name: Left
description: Channel left has to be transmitted or has been received
value: 0
- name: Right
description: Channel right has to be transmitted or has been received
value: 1
enum/CKPOL:
bit_size: 1
variants:
- name: IdleLow
description: I2S clock inactive state is low level
value: 0
- name: IdleHigh
description: I2S clock inactive state is high level
value: 1
enum/CPHA:
bit_size: 1
variants:
- name: FirstEdge
description: The first clock transition is the first data capture edge
value: 0
- name: SecondEdge
description: The second clock transition is the first data capture edge
value: 1
enum/CPOL:
bit_size: 1
variants:
- name: IdleLow
description: CK to 0 when idle
value: 0
- name: IdleHigh
description: CK to 1 when idle
value: 1
enum/CRCNEXT:
bit_size: 1
variants:
- name: TxBuffer
description: Next transmit value is from Tx buffer
value: 0
- name: CRC
description: Next transmit value is from Tx CRC register
value: 1
enum/DATLEN:
bit_size: 2
variants:
- name: SixteenBit
description: 16-bit data length
value: 0
- name: TwentyFourBit
description: 24-bit data length
value: 1
- name: ThirtyTwoBit
description: 32-bit data length
value: 2
enum/DFF:
bit_size: 1
variants:
- name: EightBit
description: 8-bit data frame format is selected for transmission/reception
value: 0
- name: SixteenBit
description: 16-bit data frame format is selected for transmission/reception
value: 1
enum/ERRIE:
bit_size: 1
variants:
- name: Masked
description: Error interrupt masked
value: 0
- name: NotMasked
description: Error interrupt not masked
value: 1
enum/ISCFG:
bit_size: 2
variants:
- name: SlaveTx
description: Slave - transmit
value: 0
- name: SlaveRx
description: Slave - receive
value: 1
- name: MasterTx
description: Master - transmit
value: 2
- name: MasterRx
description: Master - receive
value: 3
enum/ISMOD:
bit_size: 1
variants:
- name: SPIMode
description: SPI mode is selected
value: 0
- name: I2SMode
description: I2S mode is selected
value: 1
enum/ISSTD:
bit_size: 2
variants:
- name: Philips
description: I2S Philips standard
value: 0
- name: MSB
description: MSB justified standard
value: 1
- name: LSB
description: LSB justified standard
value: 2
- name: PCM
description: PCM standard
value: 3
enum/LSBFIRST:
bit_size: 1
variants:
- name: MSBFirst
description: Data is transmitted/received with the MSB first
value: 0
- name: LSBFirst
description: Data is transmitted/received with the LSB first
value: 1
enum/MSTR:
bit_size: 1
variants:
- name: Slave
description: Slave configuration
value: 0
- name: Master
description: Master configuration
value: 1
enum/ODD:
bit_size: 1
variants:
- name: Even
description: Real divider value is I2SDIV * 2
value: 0
- name: Odd
description: Real divider value is (I2SDIV * 2) + 1
value: 1
enum/OVRR:
bit_size: 1
variants:
- name: NoOverrun
description: No overrun occurred
value: 0
- name: Overrun
description: Overrun occurred
value: 1
enum/PCMSYNC:
bit_size: 1
variants:
- name: Short
description: Short frame synchronisation
value: 0
- name: Long
description: Long frame synchronisation
value: 1
enum/RXONLY:
bit_size: 1
variants:
- name: FullDuplex
description: Full duplex (Transmit and receive)
value: 0
- name: OutputDisabled
description: Output disabled (Receive-only mode)
value: 1

930
data/registers/spi_v2.yaml
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6
data/registers/syscfg_f4.yaml
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@ -5,12 +5,10 @@ block/SYSCFG:
- name: MEMRM - name: MEMRM
description: memory remap register description: memory remap register
byte_offset: 0 byte_offset: 0
reset_value: 0
fieldset: MEMRM fieldset: MEMRM
- name: PMC - name: PMC
description: peripheral mode configuration register description: peripheral mode configuration register
byte_offset: 4 byte_offset: 4
reset_value: 0
fieldset: PMC fieldset: PMC
- name: EXTICR - name: EXTICR
description: external interrupt configuration register description: external interrupt configuration register
@ -18,12 +16,10 @@ block/SYSCFG:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 8 byte_offset: 8
reset_value: 0
fieldset: EXTICR fieldset: EXTICR
- name: CMPCR - name: CMPCR
description: Compensation cell control register description: Compensation cell control register
byte_offset: 32 byte_offset: 32
reset_value: 0
access: Read access: Read
fieldset: CMPCR fieldset: CMPCR
fieldset/CMPCR: fieldset/CMPCR:
@ -80,4 +76,4 @@ fieldset/PMC:
- name: MII_RMII_SEL - name: MII_RMII_SEL
description: Ethernet PHY interface selection description: Ethernet PHY interface selection
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1

190
data/registers/syscfg_f7.yaml
View File

@ -2,110 +2,110 @@
block/SYSCFG: block/SYSCFG:
description: System configuration controller description: System configuration controller
items: items:
- byte_offset: 0 - name: MEMRMP
description: memory remap register description: memory remap register
fieldset: MEMRMP byte_offset: 0
name: MEMRMP fieldset: MEMRMP
- byte_offset: 4 - name: PMC
description: peripheral mode configuration register description: peripheral mode configuration register
fieldset: PMC byte_offset: 4
name: PMC fieldset: PMC
- array: - name: EXTICR
len: 4 description: external interrupt configuration register 1
stride: 4 array:
byte_offset: 8 len: 4
description: external interrupt configuration register 1 stride: 4
fieldset: EXTICR byte_offset: 8
name: EXTICR fieldset: EXTICR
- access: Read - name: CMPCR
byte_offset: 32 description: Compensation cell control register
description: Compensation cell control register byte_offset: 32
fieldset: CMPCR access: Read
name: CMPCR fieldset: CMPCR
fieldset/CMPCR: fieldset/CMPCR:
description: Compensation cell control register description: Compensation cell control register
fields: fields:
- bit_offset: 0 - name: CMP_PD
bit_size: 1 description: Compensation cell power-down
description: Compensation cell power-down bit_offset: 0
name: CMP_PD bit_size: 1
- bit_offset: 8 - name: READY
bit_size: 1 description: READY
description: READY bit_offset: 8
name: READY bit_size: 1
fieldset/EXTICR: fieldset/EXTICR:
description: external interrupt configuration register 1 description: external interrupt configuration register 1
fields: fields:
- array: - name: EXTI
len: 4 description: EXTI x configuration (x = 0 to 3)
stride: 4 bit_offset: 0
bit_offset: 0 bit_size: 4
bit_size: 4 array:
description: EXTI x configuration (x = 0 to 3) len: 4
name: EXTI stride: 4
fieldset/MEMRMP: fieldset/MEMRMP:
description: memory remap register description: memory remap register
fields: fields:
- bit_offset: 0 - name: MEM_BOOT
bit_size: 1 description: Memory boot mapping
description: Memory boot mapping bit_offset: 0
name: MEM_BOOT bit_size: 1
- bit_offset: 8 - name: FB_MODE
bit_size: 1 description: Flash bank mode selection
description: Flash bank mode selection bit_offset: 8
name: FB_MODE bit_size: 1
- bit_offset: 10 - name: SWP_FMC
bit_size: 2 description: FMC memory mapping swap
description: FMC memory mapping swap bit_offset: 10
name: SWP_FMC bit_size: 2
fieldset/PMC: fieldset/PMC:
description: peripheral mode configuration register description: peripheral mode configuration register
fields: fields:
- bit_offset: 0 - name: I2C1_FMP
bit_size: 1 description: I2C1_FMP I2C1 Fast Mode + Enable
description: I2C1_FMP I2C1 Fast Mode + Enable bit_offset: 0
name: I2C1_FMP bit_size: 1
- bit_offset: 1 - name: I2C2_FMP
bit_size: 1 description: I2C2_FMP I2C2 Fast Mode + Enable
description: I2C2_FMP I2C2 Fast Mode + Enable bit_offset: 1
name: I2C2_FMP bit_size: 1
- bit_offset: 2 - name: I2C3_FMP
bit_size: 1 description: I2C3_FMP I2C3 Fast Mode + Enable
description: I2C3_FMP I2C3 Fast Mode + Enable bit_offset: 2
name: I2C3_FMP bit_size: 1
- bit_offset: 3 - name: I2C4_FMP
bit_size: 1 description: I2C4 Fast Mode + Enable
description: I2C4 Fast Mode + Enable bit_offset: 3
name: I2C4_FMP bit_size: 1
- bit_offset: 4 - name: PB6_FMP
bit_size: 1 description: PB6_FMP Fast Mode
description: PB6_FMP Fast Mode bit_offset: 4
name: PB6_FMP bit_size: 1
- bit_offset: 5 - name: PB7_FMP
bit_size: 1 description: PB7_FMP Fast Mode + Enable
description: PB7_FMP Fast Mode + Enable bit_offset: 5
name: PB7_FMP bit_size: 1
- bit_offset: 6 - name: PB8_FMP
bit_size: 1 description: PB8_FMP Fast Mode + Enable
description: PB8_FMP Fast Mode + Enable bit_offset: 6
name: PB8_FMP bit_size: 1
- bit_offset: 7 - name: PB9_FMP
bit_size: 1 description: Fast Mode + Enable
description: Fast Mode + Enable bit_offset: 7
name: PB9_FMP bit_size: 1
- bit_offset: 16 - name: ADC1DC2
bit_size: 1 description: ADC3DC2
description: ADC3DC2 bit_offset: 16
name: ADC1DC2 bit_size: 1
- bit_offset: 17 - name: ADC2DC2
bit_size: 1 description: ADC2DC2
description: ADC2DC2 bit_offset: 17
name: ADC2DC2 bit_size: 1
- bit_offset: 18 - name: ADC3DC2
bit_size: 1 description: ADC3DC2
description: ADC3DC2 bit_offset: 18
name: ADC3DC2 bit_size: 1
- bit_offset: 23 - name: MII_RMII_SEL
bit_size: 1 description: Ethernet PHY interface selection
description: Ethernet PHY interface selection bit_offset: 23
name: MII_RMII_SEL bit_size: 1

1093
data/registers/syscfg_g0.yaml
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309
data/registers/timer_v1.yaml
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@ -1,47 +1,72 @@
--- ---
block/TIM_ADV:
extends: TIM_GP16
description: Advanced-timers
items:
- name: RCR
description: repetition counter register
byte_offset: 48
fieldset: RCR
- name: BDTR
description: break and dead-time register
byte_offset: 68
fieldset: BDTR
- name: CCER
description: capture/compare enable register
byte_offset: 32
fieldset: CCER_ADV
- name: CR2
description: control register 2
byte_offset: 4
fieldset: CR2_ADV
- name: DIER
description: DMA/Interrupt enable register
byte_offset: 12
fieldset: DIER_ADV
- name: SR
description: status register
byte_offset: 16
fieldset: SR_ADV
- name: EGR
description: event generation register
byte_offset: 20
access: Write
fieldset: EGR_ADV
block/TIM_BASIC: block/TIM_BASIC:
description: Basic timer description: Basic timer
items: items:
- name: CR1 - name: CR1
description: control register 1 description: control register 1
byte_offset: 0 byte_offset: 0
reset_value: 0
fieldset: CR1_BASIC fieldset: CR1_BASIC
- name: CR2 - name: CR2
description: control register 2 description: control register 2
byte_offset: 4 byte_offset: 4
reset_value: 0
fieldset: CR2_BASIC fieldset: CR2_BASIC
- name: DIER - name: DIER
description: DMA/Interrupt enable register description: DMA/Interrupt enable register
byte_offset: 12 byte_offset: 12
reset_value: 0
fieldset: DIER_BASIC fieldset: DIER_BASIC
- name: SR - name: SR
description: status register description: status register
byte_offset: 16 byte_offset: 16
reset_value: 0
fieldset: SR_BASIC fieldset: SR_BASIC
- name: EGR - name: EGR
description: event generation register description: event generation register
byte_offset: 20 byte_offset: 20
reset_value: 0
access: Write access: Write
fieldset: EGR_BASIC fieldset: EGR_BASIC
- name: CNT - name: CNT
description: counter description: counter
byte_offset: 36 byte_offset: 36
reset_value: 0
fieldset: CNT_16 fieldset: CNT_16
- name: PSC - name: PSC
description: prescaler description: prescaler
byte_offset: 40 byte_offset: 40
reset_value: 0
fieldset: PSC fieldset: PSC
- name: ARR - name: ARR
description: auto-reload register description: auto-reload register
byte_offset: 44 byte_offset: 44
reset_value: 0
fieldset: ARR_16 fieldset: ARR_16
block/TIM_GP16: block/TIM_GP16:
extends: TIM_BASIC extends: TIM_BASIC
@ -50,32 +75,26 @@ block/TIM_GP16:
- name: CR1 - name: CR1
description: control register 1 description: control register 1
byte_offset: 0 byte_offset: 0
reset_value: 0
fieldset: CR1_GP fieldset: CR1_GP
- name: CR2 - name: CR2
description: control register 2 description: control register 2
byte_offset: 4 byte_offset: 4
reset_value: 0
fieldset: CR2_GP fieldset: CR2_GP
- name: SMCR - name: SMCR
description: slave mode control register description: slave mode control register
byte_offset: 8 byte_offset: 8
reset_value: 0
fieldset: SMCR fieldset: SMCR
- name: DIER - name: DIER
description: DMA/Interrupt enable register description: DMA/Interrupt enable register
byte_offset: 12 byte_offset: 12
reset_value: 0
fieldset: DIER_GP fieldset: DIER_GP
- name: SR - name: SR
description: status register description: status register
byte_offset: 16 byte_offset: 16
reset_value: 0
fieldset: SR_GP fieldset: SR_GP
- name: EGR - name: EGR
description: event generation register description: event generation register
byte_offset: 20 byte_offset: 20
reset_value: 0
access: Write access: Write
fieldset: EGR_GP fieldset: EGR_GP
- name: CCMR_Input - name: CCMR_Input
@ -84,7 +103,6 @@ block/TIM_GP16:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 24 byte_offset: 24
reset_value: 0
fieldset: CCMR_Input fieldset: CCMR_Input
- name: CCMR_Output - name: CCMR_Output
description: capture/compare mode register 1 (output mode) description: capture/compare mode register 1 (output mode)
@ -92,27 +110,22 @@ block/TIM_GP16:
len: 2 len: 2
stride: 4 stride: 4
byte_offset: 24 byte_offset: 24
reset_value: 0
fieldset: CCMR_Output fieldset: CCMR_Output
- name: CCER - name: CCER
description: capture/compare enable register description: capture/compare enable register
byte_offset: 32 byte_offset: 32
reset_value: 0
fieldset: CCER_GP fieldset: CCER_GP
- name: PSC - name: PSC
description: prescaler description: prescaler
byte_offset: 40 byte_offset: 40
reset_value: 0
fieldset: PSC fieldset: PSC
- name: DCR - name: DCR
description: DMA control register description: DMA control register
byte_offset: 72 byte_offset: 72
reset_value: 0
fieldset: DCR fieldset: DCR
- name: DMAR - name: DMAR
description: DMA address for full transfer description: DMA address for full transfer
byte_offset: 76 byte_offset: 76
reset_value: 0
fieldset: DMAR fieldset: DMAR
- name: CCR - name: CCR
description: capture/compare register description: capture/compare register
@ -120,7 +133,6 @@ block/TIM_GP16:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 52 byte_offset: 52
reset_value: 0
fieldset: CCR_16 fieldset: CCR_16
block/TIM_GP32: block/TIM_GP32:
extends: TIM_GP16 extends: TIM_GP16
@ -129,12 +141,10 @@ block/TIM_GP32:
- name: CNT - name: CNT
description: counter description: counter
byte_offset: 36 byte_offset: 36
reset_value: 0
fieldset: CNT_32 fieldset: CNT_32
- name: ARR - name: ARR
description: auto-reload register description: auto-reload register
byte_offset: 44 byte_offset: 44
reset_value: 0
fieldset: ARR_32 fieldset: ARR_32
- name: CCR - name: CCR
description: capture/compare register description: capture/compare register
@ -142,55 +152,7 @@ block/TIM_GP32:
len: 4 len: 4
stride: 4 stride: 4
byte_offset: 52 byte_offset: 52
reset_value: 0
fieldset: CCR_32 fieldset: CCR_32
block/TIM_ADV:
extends: TIM_GP16
description: Advanced-timers
items:
- name: RCR
description: repetition counter register
byte_offset: 48
reset_value: 0
fieldset: RCR
- name: BDTR
description: break and dead-time register
byte_offset: 68
reset_value: 0
fieldset: BDTR
- name: CCER
description: capture/compare enable register
byte_offset: 32
reset_value: 0
fieldset: CCER_ADV
- name: CR2
description: control register 2
byte_offset: 4
reset_value: 0
fieldset: CR2_ADV
- name: DIER
description: DMA/Interrupt enable register
byte_offset: 12
reset_value: 0
fieldset: DIER_ADV
- name: SR
description: status register
byte_offset: 16
reset_value: 0
fieldset: SR_ADV
- name: EGR
description: event generation register
byte_offset: 20
reset_value: 0
access: Write
fieldset: EGR_ADV
fieldset/ARR_32:
description: auto-reload register
fields:
- name: ARR
description: Auto-reload value
bit_offset: 0
bit_size: 32
fieldset/ARR_16: fieldset/ARR_16:
description: auto-reload register description: auto-reload register
fields: fields:
@ -198,34 +160,13 @@ fieldset/ARR_16:
description: Auto-reload value description: Auto-reload value
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
fieldset/CCR_32: fieldset/ARR_32:
description: capture/compare register 1 description: auto-reload register
fields: fields:
- name: CCR - name: ARR
description: Capture/Compare 1 value description: Auto-reload value
bit_offset: 0 bit_offset: 0
bit_size: 32 bit_size: 32
fieldset/CCR_16:
description: capture/compare register 1
fields:
- name: CCR
description: Capture/Compare 1 value
bit_offset: 0
bit_size: 16
fieldset/CNT_32:
description: counter
fields:
- name: CNT
description: counter value
bit_offset: 0
bit_size: 32
fieldset/CNT_16:
description: counter
fields:
- name: CNT
description: counter value
bit_offset: 0
bit_size: 16
fieldset/BDTR: fieldset/BDTR:
description: break and dead-time register description: break and dead-time register
fields: fields:
@ -263,6 +204,17 @@ fieldset/BDTR:
description: Main output enable description: Main output enable
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
fieldset/CCER_ADV:
extends: CCER_GP
description: capture/compare enable register
fields:
- name: CCNE
description: Capture/Compare 1 complementary output enable
bit_offset: 2
bit_size: 1
array:
len: 4
stride: 4
fieldset/CCER_GP: fieldset/CCER_GP:
description: capture/compare enable register description: capture/compare enable register
fields: fields:
@ -287,17 +239,6 @@ fieldset/CCER_GP:
array: array:
len: 4 len: 4
stride: 4 stride: 4
fieldset/CCER_ADV:
extends: CCER_GP
description: capture/compare enable register
fields:
- name: CCNE
description: Capture/Compare 1 complementary output enable
bit_offset: 2
bit_size: 1
array:
len: 4
stride: 4
fieldset/CCMR_Input: fieldset/CCMR_Input:
description: capture/compare mode register 1 (input mode) description: capture/compare mode register 1 (input mode)
fields: fields:
@ -365,6 +306,34 @@ fieldset/CCMR_Output:
array: array:
len: 2 len: 2
stride: 8 stride: 8
fieldset/CCR_16:
description: capture/compare register 1
fields:
- name: CCR
description: Capture/Compare 1 value
bit_offset: 0
bit_size: 16
fieldset/CCR_32:
description: capture/compare register 1
fields:
- name: CCR
description: Capture/Compare 1 value
bit_offset: 0
bit_size: 32
fieldset/CNT_16:
description: counter
fields:
- name: CNT
description: counter value
bit_offset: 0
bit_size: 16
fieldset/CNT_32:
description: counter
fields:
- name: CNT
description: counter value
bit_offset: 0
bit_size: 32
fieldset/CR1_BASIC: fieldset/CR1_BASIC:
description: control register 1 description: control register 1
fields: fields:
@ -410,28 +379,6 @@ fieldset/CR1_GP:
bit_offset: 8 bit_offset: 8
bit_size: 2 bit_size: 2
enum: CKD enum: CKD
fieldset/CR2_BASIC:
description: control register 2
fields:
- name: MMS
description: Master mode selection
bit_offset: 4
bit_size: 3
enum: MMS
fieldset/CR2_GP:
extends: CR2_BASIC
description: control register 2
fields:
- name: CCDS
description: Capture/compare DMA selection
bit_offset: 3
bit_size: 1
enum: CCDS
- name: TI1S
description: TI1 selection
bit_offset: 7
bit_size: 1
enum: TIS
fieldset/CR2_ADV: fieldset/CR2_ADV:
extends: CR2_GP extends: CR2_GP
description: control register 2 description: control register 2
@ -463,6 +410,28 @@ fieldset/CR2_ADV:
description: Output Idle state 3 description: Output Idle state 3
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
fieldset/CR2_BASIC:
description: control register 2
fields:
- name: MMS
description: Master mode selection
bit_offset: 4
bit_size: 3
enum: MMS
fieldset/CR2_GP:
extends: CR2_BASIC
description: control register 2
fields:
- name: CCDS
description: Capture/compare DMA selection
bit_offset: 3
bit_size: 1
enum: CCDS
- name: TI1S
description: TI1 selection
bit_offset: 7
bit_size: 1
enum: TIS
fieldset/DCR: fieldset/DCR:
description: DMA control register description: DMA control register
fields: fields:
@ -474,6 +443,22 @@ fieldset/DCR:
description: DMA burst length description: DMA burst length
bit_offset: 8 bit_offset: 8
bit_size: 5 bit_size: 5
fieldset/DIER_ADV:
extends: DIER_GP
description: DMA/Interrupt enable register
fields:
- name: COMIE
description: COM interrupt enable
bit_offset: 5
bit_size: 1
- name: BIE
description: Break interrupt enable
bit_offset: 7
bit_size: 1
- name: COMDE
description: COM DMA request enable
bit_offset: 13
bit_size: 1
fieldset/DIER_BASIC: fieldset/DIER_BASIC:
description: DMA/Interrupt enable register description: DMA/Interrupt enable register
fields: fields:
@ -511,22 +496,6 @@ fieldset/DIER_GP:
description: Trigger DMA request enable description: Trigger DMA request enable
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
fieldset/DIER_ADV:
extends: DIER_GP
description: DMA/Interrupt enable register
fields:
- name: COMIE
description: COM interrupt enable
bit_offset: 5
bit_size: 1
- name: BIE
description: Break interrupt enable
bit_offset: 7
bit_size: 1
- name: COMDE
description: COM DMA request enable
bit_offset: 13
bit_size: 1
fieldset/DMAR: fieldset/DMAR:
description: DMA address for full transfer description: DMA address for full transfer
fields: fields:
@ -534,6 +503,18 @@ fieldset/DMAR:
description: DMA register for burst accesses description: DMA register for burst accesses
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
fieldset/EGR_ADV:
extends: EGR_GP
description: event generation register
fields:
- name: COMG
description: Capture/Compare control update generation
bit_offset: 5
bit_size: 1
- name: BG
description: Break generation
bit_offset: 7
bit_size: 1
fieldset/EGR_BASIC: fieldset/EGR_BASIC:
description: event generation register description: event generation register
fields: fields:
@ -564,18 +545,6 @@ fieldset/EGR_GP:
description: Break generation description: Break generation
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
fieldset/EGR_ADV:
extends: EGR_GP
description: event generation register
fields:
- name: COMG
description: Capture/Compare control update generation
bit_offset: 5
bit_size: 1
- name: BG
description: Break generation
bit_offset: 7
bit_size: 1
fieldset/PSC: fieldset/PSC:
description: prescaler description: prescaler
fields: fields:
@ -628,6 +597,18 @@ fieldset/SMCR:
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
enum: ETP enum: ETP
fieldset/SR_ADV:
extends: SR_GP
description: status register
fields:
- name: COMIF
description: COM interrupt flag
bit_offset: 5
bit_size: 1
- name: BIF
description: Break interrupt flag
bit_offset: 7
bit_size: 1
fieldset/SR_BASIC: fieldset/SR_BASIC:
description: status register description: status register
fields: fields:
@ -665,18 +646,6 @@ fieldset/SR_GP:
array: array:
len: 4 len: 4
stride: 1 stride: 1
fieldset/SR_ADV:
extends: SR_GP
description: status register
fields:
- name: COMIF
description: COM interrupt flag
bit_offset: 5
bit_size: 1
- name: BIF
description: Break interrupt flag
bit_offset: 7
bit_size: 1
enum/ARPE: enum/ARPE:
bit_size: 1 bit_size: 1
variants: variants:
@ -1051,4 +1020,4 @@ enum/URS:
value: 0 value: 0
- name: CounterOnly - name: CounterOnly
description: Only counter overflow/underflow generates an update interrupt or DMA request description: Only counter overflow/underflow generates an update interrupt or DMA request
value: 1 value: 1

11
data/registers/usart_v1.yaml
View File

@ -5,32 +5,26 @@ block/UART:
- name: SR - name: SR
description: Status register description: Status register
byte_offset: 0 byte_offset: 0
reset_value: 192
fieldset: SR fieldset: SR
- name: DR - name: DR
description: Data register description: Data register
byte_offset: 4 byte_offset: 4
reset_value: 0
fieldset: DR fieldset: DR
- name: BRR - name: BRR
description: Baud rate register description: Baud rate register
byte_offset: 8 byte_offset: 8
reset_value: 0
fieldset: BRR fieldset: BRR
- name: CR1 - name: CR1
description: Control register 1 description: Control register 1
byte_offset: 12 byte_offset: 12
reset_value: 0
fieldset: CR1 fieldset: CR1
- name: CR2 - name: CR2
description: Control register 2 description: Control register 2
byte_offset: 16 byte_offset: 16
reset_value: 0
fieldset: CR2 fieldset: CR2
- name: CR3 - name: CR3
description: Control register 3 description: Control register 3
byte_offset: 20 byte_offset: 20
reset_value: 0
fieldset: CR3 fieldset: CR3
block/USART: block/USART:
extends: UART extends: UART
@ -39,17 +33,14 @@ block/USART:
- name: CR2 - name: CR2
description: Control register 2 description: Control register 2
byte_offset: 16 byte_offset: 16
reset_value: 0
fieldset: CR2_USART fieldset: CR2_USART
- name: CR3 - name: CR3
description: Control register 3 description: Control register 3
byte_offset: 20 byte_offset: 20
reset_value: 0
fieldset: CR3_USART fieldset: CR3_USART
- name: GTPR - name: GTPR
description: Guard time and prescaler register description: Guard time and prescaler register
byte_offset: 24 byte_offset: 24
reset_value: 0
fieldset: GTPR fieldset: GTPR
fieldset/BRR: fieldset/BRR:
description: Baud rate register description: Baud rate register
@ -395,4 +386,4 @@ enum/WAKE:
value: 0 value: 0
- name: AddressMark - name: AddressMark
description: USART wakeup on address mark description: USART wakeup on address mark
value: 1 value: 1

18
data/registers/usart_v2.yaml
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@ -327,6 +327,13 @@ fieldset/CR3:
description: Wakeup from Stop mode interrupt enable description: Wakeup from Stop mode interrupt enable
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
fieldset/DR:
description: Data register
fields:
- name: DR
description: Data value
bit_offset: 0
bit_size: 9
fieldset/GTPR: fieldset/GTPR:
description: Guard time and prescaler register description: Guard time and prescaler register
fields: fields:
@ -429,13 +436,6 @@ fieldset/IXR:
description: Receive enable acknowledge flag description: Receive enable acknowledge flag
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
fieldset/DR:
description: Data register
fields:
- name: DR
description: Data value
bit_offset: 0
bit_size: 9
fieldset/RQR: fieldset/RQR:
description: Request register description: Request register
fields: fields:
@ -444,7 +444,7 @@ fieldset/RQR:
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: SBKRQ - name: SBKRQ
description: Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available description: "Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available"
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: MMRQ - name: MMRQ
@ -452,7 +452,7 @@ fieldset/RQR:
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: RXFRQ - name: RXFRQ
description: Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition description: "Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition"
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: TXFRQ - name: TXFRQ

172
data/registers/wwdg_v1.yaml
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@ -2,98 +2,98 @@
block/WWDG: block/WWDG:
description: Window watchdog description: Window watchdog
items: items:
- byte_offset: 0 - name: CR
description: Control register description: Control register
fieldset: CR byte_offset: 0
name: CR fieldset: CR
- byte_offset: 4 - name: CFR
description: Configuration register description: Configuration register
fieldset: CFR byte_offset: 4
name: CFR fieldset: CFR
- byte_offset: 8 - name: SR
description: Status register description: Status register
fieldset: SR byte_offset: 8
name: SR fieldset: SR
enum/EWIFR:
bit_size: 1
variants:
- description: The EWI Interrupt Service Routine has been serviced
name: Finished
value: 0
- description: The EWI Interrupt Service Routine has been triggered
name: Pending
value: 1
enum/EWIFW:
bit_size: 1
variants:
- description: The EWI Interrupt Service Routine has been serviced
name: Finished
value: 0
enum/EWIW:
bit_size: 1
variants:
- description: interrupt occurs whenever the counter reaches the value 0x40
name: Enable
value: 1
enum/WDGA:
bit_size: 1
variants:
- description: Watchdog disabled
name: Disabled
value: 0
- description: Watchdog enabled
name: Enabled
value: 1
enum/WDGTB:
bit_size: 2
variants:
- description: Counter clock (PCLK1 div 4096) div 1
name: Div1
value: 0
- description: Counter clock (PCLK1 div 4096) div 2
name: Div2
value: 1
- description: Counter clock (PCLK1 div 4096) div 4
name: Div4
value: 2
- description: Counter clock (PCLK1 div 4096) div 8
name: Div8
value: 3
fieldset/CFR: fieldset/CFR:
description: Configuration register description: Configuration register
fields: fields:
- bit_offset: 0 - name: W
bit_size: 7 description: 7-bit window value
description: 7-bit window value bit_offset: 0
name: W bit_size: 7
- bit_offset: 7 - name: WDGTB
bit_size: 2 description: Timer base
description: Timer base bit_offset: 7
enum: WDGTB bit_size: 2
name: WDGTB enum: WDGTB
- bit_offset: 9 - name: EWI
bit_size: 1 description: Early wakeup interrupt
description: Early wakeup interrupt bit_offset: 9
enum_write: EWIW bit_size: 1
name: EWI enum_write: EWIW
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
- bit_offset: 0 - name: T
bit_size: 7 description: 7-bit counter (MSB to LSB)
description: 7-bit counter (MSB to LSB) bit_offset: 0
name: T bit_size: 7
- bit_offset: 7 - name: WDGA
bit_size: 1 description: Activation bit
description: Activation bit bit_offset: 7
enum: WDGA bit_size: 1
name: WDGA enum: WDGA
fieldset/SR: fieldset/SR:
description: Status register description: Status register
fields: fields:
- bit_offset: 0 - name: EWIF
bit_size: 1 description: Early wakeup interrupt flag
description: Early wakeup interrupt flag bit_offset: 0
enum_read: EWIFR bit_size: 1
enum_write: EWIFW enum_read: EWIFR
name: EWIF enum_write: EWIFW
enum/EWIFR:
bit_size: 1
variants:
- name: Finished
description: The EWI Interrupt Service Routine has been serviced
value: 0
- name: Pending
description: The EWI Interrupt Service Routine has been triggered
value: 1
enum/EWIFW:
bit_size: 1
variants:
- name: Finished
description: The EWI Interrupt Service Routine has been serviced
value: 0
enum/EWIW:
bit_size: 1
variants:
- name: Enable
description: interrupt occurs whenever the counter reaches the value 0x40
value: 1
enum/WDGA:
bit_size: 1
variants:
- name: Disabled
description: Watchdog disabled
value: 0
- name: Enabled
description: Watchdog enabled
value: 1
enum/WDGTB:
bit_size: 2
variants:
- name: Div1
description: Counter clock (PCLK1 div 4096) div 1
value: 0
- name: Div2
description: Counter clock (PCLK1 div 4096) div 2
value: 1
- name: Div4
description: Counter clock (PCLK1 div 4096) div 4
value: 2
- name: Div8
description: Counter clock (PCLK1 div 4096) div 8
value: 3