chiptool fmt

data/registers/afio_f1.yaml

@@ -85,10 +85,6 @@ fieldset/MAPR:
       description: TIM4 remapping
       bit_offset: 12
       bit_size: 1
-    - name: CAN_REMAP
-      description: CAN1 remapping
-      bit_offset: 13
-      bit_size: 2
     - name: CAN1_REMAP
       description: CAN1 remapping
       bit_offset: 13

data/registers/flash_f3.yaml

@@ -1,492 +1,493 @@
+---
 block/FLASH:
   description: Flash
   items:
-  - byte_offset: 0
+    - name: ACR
       description: Flash access control register
+      byte_offset: 0
       fieldset: ACR
-    name: ACR
+    - name: KEYR
-  - access: Write
-    byte_offset: 4
       description: Flash key register
+      byte_offset: 4
+      access: Write
       fieldset: KEYR
-    name: KEYR
+    - name: OPTKEYR
-  - access: Write
-    byte_offset: 8
       description: Flash option key register
+      byte_offset: 8
+      access: Write
       fieldset: OPTKEYR
-    name: OPTKEYR
+    - name: SR
-  - byte_offset: 12
       description: Flash status register
+      byte_offset: 12
       fieldset: SR
-    name: SR
+    - name: CR
-  - byte_offset: 16
       description: Flash control register
+      byte_offset: 16
       fieldset: CR
-    name: CR
+    - name: AR
-  - access: Write
-    byte_offset: 20
       description: Flash address register
+      byte_offset: 20
+      access: Write
       fieldset: AR
-    name: AR
+    - name: OBR
-  - access: Read
-    byte_offset: 28
       description: Option byte register
+      byte_offset: 28
+      access: Read
       fieldset: OBR
-    name: OBR
+    - name: WRPR
-  - access: Read
-    byte_offset: 32
       description: Write protection register
+      byte_offset: 32
+      access: Read
       fieldset: WRPR
-    name: WRPR
+fieldset/ACR:
+  description: Flash access control register
+  fields:
+    - name: LATENCY
+      description: LATENCY
+      bit_offset: 0
+      bit_size: 3
+      enum: LATENCY
+    - name: HLFCYA
+      description: Flash half cycle access enable
+      bit_offset: 3
+      bit_size: 1
+      enum: HLFCYA
+    - name: PRFTBE
+      description: PRFTBE
+      bit_offset: 4
+      bit_size: 1
+      enum: PRFTBE
+    - name: PRFTBS
+      description: PRFTBS
+      bit_offset: 5
+      bit_size: 1
+      enum: PRFTBS
+fieldset/AR:
+  description: Flash address register
+  fields:
+    - name: FAR
+      description: Flash address
+      bit_offset: 0
+      bit_size: 32
+fieldset/CR:
+  description: Flash control register
+  fields:
+    - name: PG
+      description: Programming
+      bit_offset: 0
+      bit_size: 1
+      enum: PG
+    - name: PER
+      description: Page erase
+      bit_offset: 1
+      bit_size: 1
+      enum: PER
+    - name: MER
+      description: Mass erase
+      bit_offset: 2
+      bit_size: 1
+      enum: MER
+    - name: OPTPG
+      description: Option byte programming
+      bit_offset: 4
+      bit_size: 1
+      enum: OPTPG
+    - name: OPTER
+      description: Option byte erase
+      bit_offset: 5
+      bit_size: 1
+      enum: OPTER
+    - name: STRT
+      description: Start
+      bit_offset: 6
+      bit_size: 1
+      enum: STRT
+    - name: LOCK
+      description: Lock
+      bit_offset: 7
+      bit_size: 1
+      enum_read: LOCKR
+      enum_write: LOCKW
+    - name: OPTWRE
+      description: Option bytes write enable
+      bit_offset: 9
+      bit_size: 1
+      enum: OPTWRE
+    - name: ERRIE
+      description: Error interrupt enable
+      bit_offset: 10
+      bit_size: 1
+      enum: ERRIE
+    - name: EOPIE
+      description: End of operation interrupt enable
+      bit_offset: 12
+      bit_size: 1
+      enum: EOPIE
+    - name: OBL_LAUNCH
+      description: Force option byte loading
+      bit_offset: 13
+      bit_size: 1
+      enum: OBL_LAUNCH
+fieldset/KEYR:
+  description: Flash key register
+  fields:
+    - name: FKEYR
+      description: Flash Key
+      bit_offset: 0
+      bit_size: 32
+fieldset/OBR:
+  description: Option byte register
+  fields:
+    - name: OPTERR
+      description: Option byte error
+      bit_offset: 0
+      bit_size: 1
+      enum: OPTERR
+    - name: RDPRT
+      description: Read protection Level status
+      bit_offset: 1
+      bit_size: 2
+      enum: RDPRT
+    - name: WDG_SW
+      description: WDG_SW
+      bit_offset: 8
+      bit_size: 1
+      enum: WDG_SW
+    - name: nRST_STOP
+      description: nRST_STOP
+      bit_offset: 9
+      bit_size: 1
+      enum: nRST_STOP
+    - name: nRST_STDBY
+      description: nRST_STDBY
+      bit_offset: 10
+      bit_size: 1
+      enum: nRST_STDBY
+    - name: nBOOT1
+      description: BOOT1
+      bit_offset: 12
+      bit_size: 1
+      enum: nBOOT
+    - name: VDDA_MONITOR
+      description: VDDA_MONITOR
+      bit_offset: 13
+      bit_size: 1
+      enum: VDDA_MONITOR
+    - name: SRAM_PARITY_CHECK
+      description: SRAM_PARITY_CHECK
+      bit_offset: 14
+      bit_size: 1
+    - name: SDADC12_VDD_MONITOR
+      description: SDADC12_VDD_MONITOR
+      bit_offset: 15
+      bit_size: 1
+      enum: SDADC_VDD_MONITOR
+    - name: Data0
+      description: Data0
+      bit_offset: 16
+      bit_size: 8
+    - name: Data1
+      description: Data1
+      bit_offset: 24
+      bit_size: 8
+fieldset/OPTKEYR:
+  description: Flash option key register
+  fields:
+    - name: OPTKEYR
+      description: Option byte key
+      bit_offset: 0
+      bit_size: 32
+fieldset/SR:
+  description: Flash status register
+  fields:
+    - name: BSY
+      description: Busy
+      bit_offset: 0
+      bit_size: 1
+      enum_read: BSYR
+    - name: PGERR
+      description: Programming error
+      bit_offset: 2
+      bit_size: 1
+      enum_read: PGERRR
+      enum_write: PGERRW
+    - name: WRPRTERR
+      description: Write protection error
+      bit_offset: 4
+      bit_size: 1
+      enum_read: WRPRTERRR
+      enum_write: WRPRTERRW
+    - name: EOP
+      description: End of operation
+      bit_offset: 5
+      bit_size: 1
+      enum_read: EOPR
+      enum_write: EOPW
+fieldset/WRPR:
+  description: Write protection register
+  fields:
+    - name: WRP
+      description: Write protect
+      bit_offset: 0
+      bit_size: 32
 enum/BSYR:
   bit_size: 1
   variants:
-  - description: No write/erase operation is in progress
+    - name: Inactive
-    name: Inactive
+      description: No write/erase operation is in progress
       value: 0
-  - description: No write/erase operation is in progress
+    - name: Active
-    name: Active
+      description: No write/erase operation is in progress
       value: 1
 enum/EOPIE:
   bit_size: 1
   variants:
-  - description: End of operation interrupt disabled
+    - name: Disabled
-    name: Disabled
+      description: End of operation interrupt disabled
       value: 0
-  - description: End of operation interrupt enabled
+    - name: Enabled
-    name: Enabled
+      description: End of operation interrupt enabled
       value: 1
 enum/EOPR:
   bit_size: 1
   variants:
-  - description: No EOP event occurred
+    - name: NoEvent
-    name: NoEvent
+      description: No EOP event occurred
       value: 0
-  - description: An EOP event occurred
+    - name: Event
-    name: Event
+      description: An EOP event occurred
       value: 1
 enum/EOPW:
   bit_size: 1
   variants:
-  - description: Reset EOP event
+    - name: Reset
-    name: Reset
+      description: Reset EOP event
       value: 1
 enum/ERRIE:
   bit_size: 1
   variants:
-  - description: Error interrupt generation disabled
+    - name: Disabled
-    name: Disabled
+      description: Error interrupt generation disabled
       value: 0
-  - description: Error interrupt generation enabled
+    - name: Enabled
-    name: Enabled
+      description: Error interrupt generation enabled
       value: 1
 enum/HLFCYA:
   bit_size: 1
   variants:
-  - description: Half cycle is disabled
+    - name: Disabled
-    name: Disabled
+      description: Half cycle is disabled
       value: 0
-  - description: Half cycle is enabled
+    - name: Enabled
-    name: Enabled
+      description: Half cycle is enabled
       value: 1
 enum/LATENCY:
   bit_size: 3
   variants:
-  - description: 0 wait states, if 0 < HCLK <= 24 MHz
+    - name: WS0
-    name: WS0
+      description: "0 wait states, if 0 < HCLK <= 24 MHz"
       value: 0
-  - description: 1 wait state, if 24 < HCLK <= 48 MHz
+    - name: WS1
-    name: WS1
+      description: "1 wait state, if 24 < HCLK <= 48 MHz"
       value: 1
-  - description: 2 wait states, if 48 < HCLK <= 72 MHz
+    - name: WS2
-    name: WS2
+      description: "2 wait states, if 48 < HCLK <= 72 MHz"
       value: 2
 enum/LOCKR:
   bit_size: 1
   variants:
-  - description: FLASH_CR register is unlocked
+    - name: Unlocked
-    name: Unlocked
+      description: FLASH_CR register is unlocked
       value: 0
-  - description: FLASH_CR register is locked
+    - name: Locked
-    name: Locked
+      description: FLASH_CR register is locked
       value: 1
 enum/LOCKW:
   bit_size: 1
   variants:
-  - description: Lock the FLASH_CR register
+    - name: Lock
-    name: Lock
+      description: Lock the FLASH_CR register
       value: 1
 enum/MER:
   bit_size: 1
   variants:
-  - description: Erase activated for all user sectors
+    - name: MassErase
-    name: MassErase
+      description: Erase activated for all user sectors
       value: 1
 enum/OBL_LAUNCH:
   bit_size: 1
   variants:
-  - description: Force option byte loading inactive
+    - name: Inactive
-    name: Inactive
+      description: Force option byte loading inactive
       value: 0
-  - description: Force option byte loading active
+    - name: Active
-    name: Active
+      description: Force option byte loading active
       value: 1
 enum/OPTER:
   bit_size: 1
   variants:
-  - description: Erase option byte activated
+    - name: OptionByteErase
-    name: OptionByteErase
+      description: Erase option byte activated
       value: 1
 enum/OPTERR:
   bit_size: 1
   variants:
-  - description: The loaded option byte and its complement do not match
+    - name: OptionByteError
-    name: OptionByteError
+      description: The loaded option byte and its complement do not match
       value: 1
 enum/OPTPG:
   bit_size: 1
   variants:
-  - description: Program option byte activated
+    - name: OptionByteProgramming
-    name: OptionByteProgramming
+      description: Program option byte activated
       value: 1
 enum/OPTWRE:
   bit_size: 1
   variants:
-  - description: Option byte write enabled
+    - name: Disabled
-    name: Disabled
+      description: Option byte write enabled
       value: 0
-  - description: Option byte write disabled
+    - name: Enabled
-    name: Enabled
+      description: Option byte write disabled
       value: 1
 enum/PER:
   bit_size: 1
   variants:
-  - description: Erase activated for selected page
+    - name: PageErase
-    name: PageErase
+      description: Erase activated for selected page
       value: 1
 enum/PG:
   bit_size: 1
   variants:
-  - description: Flash programming activated
+    - name: Program
-    name: Program
+      description: Flash programming activated
       value: 1
 enum/PGERRR:
   bit_size: 1
   variants:
-  - description: No programming error occurred
+    - name: NoError
-    name: NoError
+      description: No programming error occurred
       value: 0
-  - description: A programming error occurred
+    - name: Error
-    name: Error
+      description: A programming error occurred
       value: 1
 enum/PGERRW:
   bit_size: 1
   variants:
-  - description: Reset programming error
+    - name: Reset
-    name: Reset
+      description: Reset programming error
       value: 1
 enum/PRFTBE:
   bit_size: 1
   variants:
-  - description: Prefetch is disabled
+    - name: Disabled
-    name: Disabled
+      description: Prefetch is disabled
       value: 0
-  - description: Prefetch is enabled
+    - name: Enabled
-    name: Enabled
+      description: Prefetch is enabled
       value: 1
 enum/PRFTBS:
   bit_size: 1
   variants:
-  - description: Prefetch buffer is disabled
+    - name: Disabled
-    name: Disabled
+      description: Prefetch buffer is disabled
       value: 0
-  - description: Prefetch buffer is enabled
+    - name: Enabled
-    name: Enabled
+      description: Prefetch buffer is enabled
       value: 1
 enum/RDPRT:
   bit_size: 2
   variants:
-  - description: Level 0
+    - name: Level0
-    name: Level0
+      description: Level 0
       value: 0
-  - description: Level 1
+    - name: Level1
-    name: Level1
+      description: Level 1
       value: 1
-  - description: Level 2
+    - name: Level2
-    name: Level2
+      description: Level 2
       value: 3
 enum/SDADC_VDD_MONITOR:
   bit_size: 1
   variants:
-  - description: VDDSD12 monitoring disabled
+    - name: Disabled
-    name: Disabled
+      description: VDDSD12 monitoring disabled
       value: 0
-  - description: VDDSD12 monitoring enabled
+    - name: Enabled
-    name: Enabled
+      description: VDDSD12 monitoring enabled
       value: 1
 enum/SRAM_PARITY_CHECK:
   bit_size: 1
   variants:
-  - description: RAM parity check disabled
+    - name: Disabled
-    name: Disabled
+      description: RAM parity check disabled
       value: 0
-  - description: RAM parity check enabled
+    - name: Enabled
-    name: Enabled
+      description: RAM parity check enabled
       value: 1
 enum/STRT:
   bit_size: 1
   variants:
-  - description: Trigger an erase operation
+    - name: Start
-    name: Start
+      description: Trigger an erase operation
       value: 1
 enum/VDDA_MONITOR:
   bit_size: 1
   variants:
-  - description: VDDA power supply supervisor disabled
+    - name: Disabled
-    name: Disabled
+      description: VDDA power supply supervisor disabled
       value: 0
-  - description: VDDA power supply supervisor enabled
+    - name: Enabled
-    name: Enabled
+      description: VDDA power supply supervisor enabled
       value: 1
 enum/WDG_SW:
   bit_size: 1
   variants:
-  - description: Hardware watchdog
+    - name: Hardware
-    name: Hardware
+      description: Hardware watchdog
       value: 0
-  - description: Software watchdog
+    - name: Software
-    name: Software
+      description: Software watchdog
       value: 1
 enum/WRPRTERRR:
   bit_size: 1
   variants:
-  - description: No write protection error occurred
+    - name: NoError
-    name: NoError
+      description: No write protection error occurred
       value: 0
-  - description: A write protection error occurred
+    - name: Error
-    name: Error
+      description: A write protection error occurred
       value: 1
 enum/WRPRTERRW:
   bit_size: 1
   variants:
-  - description: Reset write protection error
+    - name: Reset
-    name: Reset
+      description: Reset write protection error
       value: 1
 enum/nBOOT:
   bit_size: 1
   variants:
-  - description: Together with BOOT0, select the device boot mode
+    - name: Disabled
-    name: Disabled
+      description: "Together with BOOT0, select the device boot mode"
       value: 0
-  - description: Together with BOOT0, select the device boot mode
+    - name: Enabled
-    name: Enabled
+      description: "Together with BOOT0, select the device boot mode"
       value: 1
 enum/nRST_STDBY:
   bit_size: 1
   variants:
-  - description: Reset generated when entering Standby mode
+    - name: Reset
-    name: Reset
+      description: Reset generated when entering Standby mode
       value: 0
-  - description: No reset generated
+    - name: NoReset
-    name: NoReset
+      description: No reset generated
       value: 1
 enum/nRST_STOP:
   bit_size: 1
   variants:
-  - description: Reset generated when entering Stop mode
+    - name: Reset
-    name: Reset
+      description: Reset generated when entering Stop mode
       value: 0
-  - description: No reset generated
+    - name: NoReset
-    name: NoReset
+      description: No reset generated
       value: 1
-fieldset/ACR:
-  description: Flash access control register
-  fields:
-  - bit_offset: 0
-    bit_size: 3
-    description: LATENCY
-    enum: LATENCY
-    name: LATENCY
-  - bit_offset: 3
-    bit_size: 1
-    description: Flash half cycle access enable
-    enum: HLFCYA
-    name: HLFCYA
-  - bit_offset: 4
-    bit_size: 1
-    description: PRFTBE
-    enum: PRFTBE
-    name: PRFTBE
-  - bit_offset: 5
-    bit_size: 1
-    description: PRFTBS
-    enum: PRFTBS
-    name: PRFTBS
-fieldset/AR:
-  description: Flash address register
-  fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Flash address
-    name: FAR
-fieldset/CR:
-  description: Flash control register
-  fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Programming
-    enum: PG
-    name: PG
-  - bit_offset: 1
-    bit_size: 1
-    description: Page erase
-    enum: PER
-    name: PER
-  - bit_offset: 2
-    bit_size: 1
-    description: Mass erase
-    enum: MER
-    name: MER
-  - bit_offset: 4
-    bit_size: 1
-    description: Option byte programming
-    enum: OPTPG
-    name: OPTPG
-  - bit_offset: 5
-    bit_size: 1
-    description: Option byte erase
-    enum: OPTER
-    name: OPTER
-  - bit_offset: 6
-    bit_size: 1
-    description: Start
-    enum: STRT
-    name: STRT
-  - bit_offset: 7
-    bit_size: 1
-    description: Lock
-    enum_read: LOCKR
-    enum_write: LOCKW
-    name: LOCK
-  - bit_offset: 9
-    bit_size: 1
-    description: Option bytes write enable
-    enum: OPTWRE
-    name: OPTWRE
-  - bit_offset: 10
-    bit_size: 1
-    description: Error interrupt enable
-    enum: ERRIE
-    name: ERRIE
-  - bit_offset: 12
-    bit_size: 1
-    description: End of operation interrupt enable
-    enum: EOPIE
-    name: EOPIE
-  - bit_offset: 13
-    bit_size: 1
-    description: Force option byte loading
-    enum: OBL_LAUNCH
-    name: OBL_LAUNCH
-fieldset/KEYR:
-  description: Flash key register
-  fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Flash Key
-    name: FKEYR
-fieldset/OBR:
-  description: Option byte register
-  fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Option byte error
-    enum: OPTERR
-    name: OPTERR
-  - bit_offset: 1
-    bit_size: 2
-    description: Read protection Level status
-    enum: RDPRT
-    name: RDPRT
-  - bit_offset: 8
-    bit_size: 1
-    description: WDG_SW
-    enum: WDG_SW
-    name: WDG_SW
-  - bit_offset: 9
-    bit_size: 1
-    description: nRST_STOP
-    enum: nRST_STOP
-    name: nRST_STOP
-  - bit_offset: 10
-    bit_size: 1
-    description: nRST_STDBY
-    enum: nRST_STDBY
-    name: nRST_STDBY
-  - bit_offset: 12
-    bit_size: 1
-    description: BOOT1
-    enum: nBOOT
-    name: nBOOT1
-  - bit_offset: 13
-    bit_size: 1
-    description: VDDA_MONITOR
-    enum: VDDA_MONITOR
-    name: VDDA_MONITOR
-  - bit_offset: 14
-    bit_size: 1
-    description: SRAM_PARITY_CHECK
-    name: SRAM_PARITY_CHECK
-  - bit_offset: 15
-    bit_size: 1
-    description: SDADC12_VDD_MONITOR
-    enum: SDADC_VDD_MONITOR
-    name: SDADC12_VDD_MONITOR
-  - bit_offset: 16
-    bit_size: 8
-    description: Data0
-    name: Data0
-  - bit_offset: 24
-    bit_size: 8
-    description: Data1
-    name: Data1
-fieldset/OPTKEYR:
-  description: Flash option key register
-  fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Option byte key
-    name: OPTKEYR
-fieldset/SR:
-  description: Flash status register
-  fields:
-  - bit_offset: 0
-    bit_size: 1
-    description: Busy
-    enum_read: BSYR
-    name: BSY
-  - bit_offset: 2
-    bit_size: 1
-    description: Programming error
-    enum_read: PGERRR
-    enum_write: PGERRW
-    name: PGERR
-  - bit_offset: 4
-    bit_size: 1
-    description: Write protection error
-    enum_read: WRPRTERRR
-    enum_write: WRPRTERRW
-    name: WRPRTERR
-  - bit_offset: 5
-    bit_size: 1
-    description: End of operation
-    enum_read: EOPR
-    enum_write: EOPW
-    name: EOP
-fieldset/WRPR:
-  description: Write protection register
-  fields:
-  - bit_offset: 0
-    bit_size: 32
-    description: Write protect
-    name: WRP

data/registers/flash_l1.yaml

@@ -1,241 +1,242 @@
+---
 block/FLASH:
   description: Flash
   items:
-  - byte_offset: 0
+    - name: ACR
       description: Access control register
+      byte_offset: 0
       fieldset: ACR
-    name: ACR
+    - name: PECR
-  - byte_offset: 4
       description: Program/erase control register
+      byte_offset: 4
       fieldset: PECR
-    name: PECR
+    - name: PDKEYR
-  - access: Write
-    byte_offset: 8
       description: Power down key register
+      byte_offset: 8
+      access: Write
       fieldset: PDKEYR
-    name: PDKEYR
+    - name: PEKEYR
-  - access: Write
-    byte_offset: 12
       description: Program/erase key register
+      byte_offset: 12
+      access: Write
       fieldset: PEKEYR
-    name: PEKEYR
+    - name: PRGKEYR
-  - access: Write
-    byte_offset: 16
       description: Program memory key register
+      byte_offset: 16
+      access: Write
       fieldset: PRGKEYR
-    name: PRGKEYR
+    - name: OPTKEYR
-  - access: Write
-    byte_offset: 20
       description: Option byte key register
+      byte_offset: 20
+      access: Write
       fieldset: OPTKEYR
-    name: OPTKEYR
+    - name: SR
-  - byte_offset: 24
       description: Status register
+      byte_offset: 24
       fieldset: SR
-    name: SR
+    - name: OBR
-  - access: Read
-    byte_offset: 28
       description: Option byte register
+      byte_offset: 28
+      access: Read
       fieldset: OBR
-    name: OBR
+    - name: WRPR1
-  - byte_offset: 32
       description: Write protection register
+      byte_offset: 32
       fieldset: WRPR1
-    name: WRPR1
+    - name: WRPR2
-  - byte_offset: 128
       description: Write protection register
+      byte_offset: 128
       fieldset: WRPR2
-    name: WRPR2
+    - name: WRPR3
-  - byte_offset: 132
       description: Write protection register
+      byte_offset: 132
       fieldset: WRPR3
-    name: WRPR3
 fieldset/ACR:
   description: Access control register
   fields:
-  - bit_offset: 0
+    - name: LATENCY
-    bit_size: 1
       description: Latency
-    name: LATENCY
+      bit_offset: 0
-  - bit_offset: 1
       bit_size: 1
+    - name: PRFTEN
       description: Prefetch enable
-    name: PRFTEN
+      bit_offset: 1
-  - bit_offset: 2
       bit_size: 1
+    - name: ACC64
       description: 64-bit access
-    name: ACC64
+      bit_offset: 2
-  - bit_offset: 3
       bit_size: 1
+    - name: SLEEP_PD
       description: Flash mode during Sleep
-    name: SLEEP_PD
+      bit_offset: 3
-  - bit_offset: 4
       bit_size: 1
+    - name: RUN_PD
       description: Flash mode during Run
-    name: RUN_PD
+      bit_offset: 4
+      bit_size: 1
 fieldset/OBR:
   description: Option byte register
   fields:
-  - bit_offset: 0
+    - name: RDPRT
-    bit_size: 8
       description: Read protection
-    name: RDPRT
+      bit_offset: 0
-  - bit_offset: 16
+      bit_size: 8
-    bit_size: 4
+    - name: BOR_LEV
       description: BOR_LEV
-    name: BOR_LEV
+      bit_offset: 16
-  - bit_offset: 20
+      bit_size: 4
-    bit_size: 1
+    - name: IWDG_SW
       description: IWDG_SW
-    name: IWDG_SW
+      bit_offset: 20
-  - bit_offset: 21
       bit_size: 1
+    - name: nRTS_STOP
       description: nRTS_STOP
-    name: nRTS_STOP
+      bit_offset: 21
-  - bit_offset: 22
       bit_size: 1
+    - name: nRST_STDBY
       description: nRST_STDBY
-    name: nRST_STDBY
+      bit_offset: 22
-  - bit_offset: 23
       bit_size: 1
+    - name: BFB2
       description: Boot From Bank 2
-    name: BFB2
+      bit_offset: 23
+      bit_size: 1
 fieldset/OPTKEYR:
   description: Option byte key register
   fields:
-  - bit_offset: 0
+    - name: OPTKEYR
-    bit_size: 32
       description: Option byte key
-    name: OPTKEYR
+      bit_offset: 0
+      bit_size: 32
 fieldset/PDKEYR:
   description: Power down key register
   fields:
-  - bit_offset: 0
+    - name: PDKEYR
-    bit_size: 32
       description: RUN_PD in FLASH_ACR key
-    name: PDKEYR
+      bit_offset: 0
+      bit_size: 32
 fieldset/PECR:
   description: Program/erase control register
   fields:
-  - bit_offset: 0
+    - name: PELOCK
-    bit_size: 1
       description: FLASH_PECR and data EEPROM lock
-    name: PELOCK
+      bit_offset: 0
-  - bit_offset: 1
       bit_size: 1
+    - name: PRGLOCK
       description: Program memory lock
-    name: PRGLOCK
+      bit_offset: 1
-  - bit_offset: 2
       bit_size: 1
+    - name: OPTLOCK
       description: Option bytes block lock
-    name: OPTLOCK
+      bit_offset: 2
-  - bit_offset: 3
       bit_size: 1
+    - name: PROG
       description: Program memory selection
-    name: PROG
+      bit_offset: 3
-  - bit_offset: 4
       bit_size: 1
+    - name: DATA
       description: Data EEPROM selection
-    name: DATA
+      bit_offset: 4
-  - bit_offset: 8
       bit_size: 1
-    description: Fixed time data write for Byte, Half Word and Word programming
+    - name: FTDW
-    name: FTDW
+      description: "Fixed time data write for Byte, Half Word and Word programming"
-  - bit_offset: 9
+      bit_offset: 8
       bit_size: 1
+    - name: ERASE
       description: Page or Double Word erase mode
-    name: ERASE
+      bit_offset: 9
-  - bit_offset: 10
       bit_size: 1
+    - name: FPRG
       description: Half Page/Double Word programming mode
-    name: FPRG
+      bit_offset: 10
-  - bit_offset: 15
       bit_size: 1
+    - name: PARALLELBANK
       description: Parallel bank mode
-    name: PARALLELBANK
+      bit_offset: 15
-  - bit_offset: 16
       bit_size: 1
+    - name: EOPIE
       description: End of programming interrupt enable
-    name: EOPIE
+      bit_offset: 16
-  - bit_offset: 17
       bit_size: 1
+    - name: ERRIE
       description: Error interrupt enable
-    name: ERRIE
+      bit_offset: 17
-  - bit_offset: 18
       bit_size: 1
+    - name: OBL_LAUNCH
       description: Launch the option byte loading
-    name: OBL_LAUNCH
+      bit_offset: 18
+      bit_size: 1
 fieldset/PEKEYR:
   description: Program/erase key register
   fields:
-  - bit_offset: 0
+    - name: PEKEYR
-    bit_size: 32
       description: FLASH_PEC and data EEPROM key
-    name: PEKEYR
+      bit_offset: 0
+      bit_size: 32
 fieldset/PRGKEYR:
   description: Program memory key register
   fields:
-  - bit_offset: 0
+    - name: PRGKEYR
-    bit_size: 32
       description: Program memory key
-    name: PRGKEYR
+      bit_offset: 0
+      bit_size: 32
 fieldset/SR:
   description: Status register
   fields:
-  - bit_offset: 0
+    - name: BSY
-    bit_size: 1
       description: Write/erase operations in progress
-    name: BSY
+      bit_offset: 0
-  - bit_offset: 1
       bit_size: 1
+    - name: EOP
       description: End of operation
-    name: EOP
+      bit_offset: 1
-  - bit_offset: 2
       bit_size: 1
+    - name: ENDHV
       description: End of high voltage
-    name: ENDHV
+      bit_offset: 2
-  - bit_offset: 3
       bit_size: 1
+    - name: READY
       description: Flash memory module ready after low power mode
-    name: READY
+      bit_offset: 3
-  - bit_offset: 8
       bit_size: 1
+    - name: WRPERR
       description: Write protected error
-    name: WRPERR
+      bit_offset: 8
-  - bit_offset: 9
       bit_size: 1
+    - name: PGAERR
       description: Programming alignment error
-    name: PGAERR
+      bit_offset: 9
-  - bit_offset: 10
       bit_size: 1
+    - name: SIZERR
       description: Size error
-    name: SIZERR
+      bit_offset: 10
-  - bit_offset: 11
       bit_size: 1
+    - name: OPTVERR
       description: Option validity error
-    name: OPTVERR
+      bit_offset: 11
-  - bit_offset: 12
       bit_size: 1
+    - name: OPTVERRUSR
       description: Option UserValidity Error
-    name: OPTVERRUSR
+      bit_offset: 12
+      bit_size: 1
 fieldset/WRPR1:
   description: Write protection register
   fields:
-  - bit_offset: 0
+    - name: WRP1
-    bit_size: 32
       description: Write protection
-    name: WRP1
+      bit_offset: 0
+      bit_size: 32
 fieldset/WRPR2:
   description: Write protection register
   fields:
-  - bit_offset: 0
+    - name: WRP2
-    bit_size: 32
       description: WRP2
-    name: WRP2
+      bit_offset: 0
+      bit_size: 32
 fieldset/WRPR3:
   description: Write protection register
   fields:
-  - bit_offset: 0
+    - name: WRP3
-    bit_size: 32
       description: WRP3
-    name: WRP3
+      bit_offset: 0
+      bit_size: 32

data/registers/flash_wb55.yaml

@@ -2,558 +2,558 @@
 block/FLASH:
   description: Flash
   items:
-  - byte_offset: 0
+    - name: ACR
       description: Access control register
+      byte_offset: 0
       fieldset: ACR
-    name: ACR
+    - name: KEYR
-  - access: Write
-    byte_offset: 8
       description: Flash key register
+      byte_offset: 8
+      access: Write
       fieldset: KEYR
-    name: KEYR
+    - name: OPTKEYR
-  - access: Write
-    byte_offset: 12
       description: Option byte key register
+      byte_offset: 12
+      access: Write
       fieldset: OPTKEYR
-    name: OPTKEYR
+    - name: SR
-  - byte_offset: 16
       description: Status register
+      byte_offset: 16
       fieldset: SR
-    name: SR
+    - name: CR
-  - byte_offset: 20
       description: Flash control register
+      byte_offset: 20
       fieldset: CR
-    name: CR
+    - name: ECCR
-  - byte_offset: 24
       description: Flash ECC register
+      byte_offset: 24
       fieldset: ECCR
-    name: ECCR
+    - name: OPTR
-  - byte_offset: 32
       description: Flash option register
+      byte_offset: 32
       fieldset: OPTR
-    name: OPTR
+    - name: PCROP1ASR
-  - byte_offset: 36
       description: Flash Bank 1 PCROP Start address zone A register
+      byte_offset: 36
       fieldset: PCROP1ASR
-    name: PCROP1ASR
+    - name: PCROP1AER
-  - byte_offset: 40
       description: Flash Bank 1 PCROP End address zone A register
+      byte_offset: 40
       fieldset: PCROP1AER
-    name: PCROP1AER
+    - name: WRP1AR
-  - byte_offset: 44
       description: Flash Bank 1 WRP area A address register
+      byte_offset: 44
       fieldset: WRP1AR
-    name: WRP1AR
+    - name: WRP1BR
-  - byte_offset: 48
       description: Flash Bank 1 WRP area B address register
+      byte_offset: 48
       fieldset: WRP1BR
-    name: WRP1BR
+    - name: PCROP1BSR
-  - byte_offset: 52
       description: Flash Bank 1 PCROP Start address area B register
+      byte_offset: 52
       fieldset: PCROP1BSR
-    name: PCROP1BSR
+    - name: PCROP1BER
-  - byte_offset: 56
       description: Flash Bank 1 PCROP End address area B register
+      byte_offset: 56
       fieldset: PCROP1BER
-    name: PCROP1BER
+    - name: IPCCBR
-  - byte_offset: 60
       description: IPCC mailbox data buffer address register
+      byte_offset: 60
       fieldset: IPCCBR
-    name: IPCCBR
+    - name: C2ACR
-  - byte_offset: 92
       description: CPU2 cortex M0 access control register
+      byte_offset: 92
       fieldset: C2ACR
-    name: C2ACR
+    - name: C2SR
-  - byte_offset: 96
       description: CPU2 cortex M0 status register
+      byte_offset: 96
       fieldset: C2SR
-    name: C2SR
+    - name: C2CR
-  - byte_offset: 100
       description: CPU2 cortex M0 control register
+      byte_offset: 100
       fieldset: C2CR
-    name: C2CR
+    - name: SFR
-  - byte_offset: 128
       description: Secure flash start address register
+      byte_offset: 128
       fieldset: SFR
-    name: SFR
+    - name: SRRVR
-  - byte_offset: 132
       description: Secure SRAM2 start address and cortex M0 reset vector register
+      byte_offset: 132
       fieldset: SRRVR
-    name: SRRVR
 fieldset/ACR:
   description: Access control register
   fields:
-  - bit_offset: 0
+    - name: LATENCY
-    bit_size: 3
       description: Latency
-    name: LATENCY
+      bit_offset: 0
-  - bit_offset: 8
+      bit_size: 3
-    bit_size: 1
+    - name: PRFTEN
       description: Prefetch enable
-    name: PRFTEN
+      bit_offset: 8
-  - bit_offset: 9
       bit_size: 1
+    - name: ICEN
       description: Instruction cache enable
-    name: ICEN
+      bit_offset: 9
-  - bit_offset: 10
       bit_size: 1
+    - name: DCEN
       description: Data cache enable
-    name: DCEN
+      bit_offset: 10
-  - bit_offset: 11
       bit_size: 1
+    - name: ICRST
       description: Instruction cache reset
-    name: ICRST
+      bit_offset: 11
-  - bit_offset: 12
       bit_size: 1
+    - name: DCRST
       description: Data cache reset
-    name: DCRST
+      bit_offset: 12
-  - bit_offset: 15
       bit_size: 1
+    - name: PES
       description: CPU1 CortexM4 program erase suspend request
-    name: PES
+      bit_offset: 15
-  - bit_offset: 16
       bit_size: 1
+    - name: EMPTY
       description: Flash User area empty
-    name: EMPTY
+      bit_offset: 16
+      bit_size: 1
 fieldset/C2ACR:
   description: CPU2 cortex M0 access control register
   fields:
-  - bit_offset: 8
+    - name: PRFTEN
-    bit_size: 1
       description: CPU2 cortex M0 prefetch enable
-    name: PRFTEN
+      bit_offset: 8
-  - bit_offset: 9
       bit_size: 1
+    - name: ICEN
       description: CPU2 cortex M0 instruction cache enable
-    name: ICEN
+      bit_offset: 9
-  - bit_offset: 11
       bit_size: 1
+    - name: ICRST
       description: CPU2 cortex M0 instruction cache reset
-    name: ICRST
+      bit_offset: 11
-  - bit_offset: 15
       bit_size: 1
+    - name: PES
       description: CPU2 cortex M0 program erase suspend request
-    name: PES
+      bit_offset: 15
+      bit_size: 1
 fieldset/C2CR:
   description: CPU2 cortex M0 control register
   fields:
-  - bit_offset: 0
+    - name: PG
-    bit_size: 1
       description: Programming
-    name: PG
+      bit_offset: 0
-  - bit_offset: 1
       bit_size: 1
+    - name: PER
       description: Page erase
-    name: PER
+      bit_offset: 1
-  - bit_offset: 2
       bit_size: 1
+    - name: MER
       description: Masse erase
-    name: MER
+      bit_offset: 2
-  - bit_offset: 3
+      bit_size: 1
-    bit_size: 8
+    - name: PNB
       description: Page Number selection
-    name: PNB
+      bit_offset: 3
-  - bit_offset: 16
+      bit_size: 8
-    bit_size: 1
+    - name: STRT
       description: Start
-    name: STRT
+      bit_offset: 16
-  - bit_offset: 18
       bit_size: 1
+    - name: FSTPG
       description: Fast programming
-    name: FSTPG
+      bit_offset: 18
-  - bit_offset: 24
       bit_size: 1
+    - name: EOPIE
       description: End of operation interrupt enable
-    name: EOPIE
+      bit_offset: 24
-  - bit_offset: 25
       bit_size: 1
+    - name: ERRIE
       description: Error interrupt enable
-    name: ERRIE
+      bit_offset: 25
-  - bit_offset: 26
       bit_size: 1
+    - name: RDERRIE
       description: PCROP read error interrupt enable
-    name: RDERRIE
+      bit_offset: 26
+      bit_size: 1
 fieldset/C2SR:
   description: CPU2 cortex M0 status register
   fields:
-  - bit_offset: 0
+    - name: EOP
-    bit_size: 1
       description: End of operation
-    name: EOP
+      bit_offset: 0
-  - bit_offset: 1
       bit_size: 1
+    - name: OPERR
       description: Operation error
-    name: OPERR
+      bit_offset: 1
-  - bit_offset: 3
       bit_size: 1
+    - name: PROGERR
       description: Programming error
-    name: PROGERR
+      bit_offset: 3
-  - bit_offset: 4
       bit_size: 1
+    - name: WRPERR
       description: write protection error
-    name: WRPERR
+      bit_offset: 4
-  - bit_offset: 5
       bit_size: 1
+    - name: PGAERR
       description: Programming alignment error
-    name: PGAERR
+      bit_offset: 5
-  - bit_offset: 6
       bit_size: 1
+    - name: SIZERR
       description: Size error
-    name: SIZERR
+      bit_offset: 6
-  - bit_offset: 7
       bit_size: 1
+    - name: PGSERR
       description: Programming sequence error
-    name: PGSERR
+      bit_offset: 7
-  - bit_offset: 8
       bit_size: 1
+    - name: MISSERR
       description: Fast programming data miss error
-    name: MISSERR
+      bit_offset: 8
-  - bit_offset: 9
       bit_size: 1
+    - name: FASTERR
       description: Fast programming error
-    name: FASTERR
+      bit_offset: 9
-  - bit_offset: 14
       bit_size: 1
+    - name: RDERR
       description: PCROP read error
-    name: RDERR
+      bit_offset: 14
-  - bit_offset: 16
       bit_size: 1
+    - name: BSY
       description: Busy
-    name: BSY
+      bit_offset: 16
-  - bit_offset: 18
       bit_size: 1
+    - name: CFGBSY
       description: Programming or erase configuration busy
-    name: CFGBSY
+      bit_offset: 18
-  - bit_offset: 19
       bit_size: 1
+    - name: PESD
       description: Programming or erase operation suspended
-    name: PESD
+      bit_offset: 19
+      bit_size: 1
 fieldset/CR:
   description: Flash control register
   fields:
-  - bit_offset: 0
+    - name: PG
-    bit_size: 1
       description: Programming
-    name: PG
+      bit_offset: 0
-  - bit_offset: 1
       bit_size: 1
+    - name: PER
       description: Page erase
-    name: PER
+      bit_offset: 1
-  - bit_offset: 2
       bit_size: 1
+    - name: MER
       description: This bit triggers the mass erase (all user pages) when set
-    name: MER
+      bit_offset: 2
-  - bit_offset: 3
+      bit_size: 1
-    bit_size: 8
+    - name: PNB
       description: Page number selection
-    name: PNB
+      bit_offset: 3
-  - bit_offset: 16
+      bit_size: 8
-    bit_size: 1
+    - name: STRT
       description: Start
-    name: STRT
+      bit_offset: 16
-  - bit_offset: 17
       bit_size: 1
+    - name: OPTSTRT
       description: Options modification start
-    name: OPTSTRT
+      bit_offset: 17
-  - bit_offset: 18
       bit_size: 1
+    - name: FSTPG
       description: Fast programming
-    name: FSTPG
+      bit_offset: 18
-  - bit_offset: 24
       bit_size: 1
+    - name: EOPIE
       description: End of operation interrupt enable
-    name: EOPIE
+      bit_offset: 24
-  - bit_offset: 25
       bit_size: 1
+    - name: ERRIE
       description: Error interrupt enable
-    name: ERRIE
+      bit_offset: 25
-  - bit_offset: 26
       bit_size: 1
+    - name: RDERRIE
       description: PCROP read error interrupt enable
-    name: RDERRIE
+      bit_offset: 26
-  - bit_offset: 27
       bit_size: 1
+    - name: OBL_LAUNCH
       description: Force the option byte loading
-    name: OBL_LAUNCH
+      bit_offset: 27
-  - bit_offset: 30
       bit_size: 1
+    - name: OPTLOCK
       description: Options Lock
-    name: OPTLOCK
+      bit_offset: 30
-  - bit_offset: 31
       bit_size: 1
+    - name: LOCK
       description: FLASH_CR Lock
-    name: LOCK
+      bit_offset: 31
+      bit_size: 1
 fieldset/ECCR:
   description: Flash ECC register
   fields:
-  - bit_offset: 0
+    - name: ADDR_ECC
-    bit_size: 17
       description: ECC fail address
-    name: ADDR_ECC
+      bit_offset: 0
-  - bit_offset: 20
+      bit_size: 17
-    bit_size: 1
+    - name: SYSF_ECC
       description: System Flash ECC fail
-    name: SYSF_ECC
+      bit_offset: 20
-  - bit_offset: 24
       bit_size: 1
+    - name: ECCCIE
       description: ECC correction interrupt enable
-    name: ECCCIE
+      bit_offset: 24
-  - bit_offset: 26
+      bit_size: 1
-    bit_size: 3
+    - name: CPUID
       description: CPU identification
-    name: CPUID
+      bit_offset: 26
-  - bit_offset: 30
+      bit_size: 3
-    bit_size: 1
+    - name: ECCC
       description: ECC correction
-    name: ECCC
+      bit_offset: 30
-  - bit_offset: 31
       bit_size: 1
+    - name: ECCD
       description: ECC detection
-    name: ECCD
+      bit_offset: 31
+      bit_size: 1
 fieldset/IPCCBR:
   description: IPCC mailbox data buffer address register
   fields:
-  - bit_offset: 0
+    - name: IPCCDBA
-    bit_size: 14
       description: PCC mailbox data buffer base address
-    name: IPCCDBA
+      bit_offset: 0
+      bit_size: 14
 fieldset/KEYR:
   description: Flash key register
   fields:
-  - bit_offset: 0
+    - name: KEYR
-    bit_size: 32
       description: KEYR
-    name: KEYR
+      bit_offset: 0
+      bit_size: 32
 fieldset/OPTKEYR:
   description: Option byte key register
   fields:
-  - bit_offset: 0
+    - name: OPTKEYR
-    bit_size: 32
       description: Option byte key
-    name: OPTKEYR
+      bit_offset: 0
+      bit_size: 32
 fieldset/OPTR:
   description: Flash option register
   fields:
-  - bit_offset: 0
+    - name: RDP
-    bit_size: 8
       description: Read protection level
-    name: RDP
+      bit_offset: 0
-  - bit_offset: 8
+      bit_size: 8
-    bit_size: 1
+    - name: ESE
       description: Security enabled
-    name: ESE
+      bit_offset: 8
-  - bit_offset: 9
+      bit_size: 1
-    bit_size: 3
+    - name: BOR_LEV
       description: BOR reset Level
-    name: BOR_LEV
+      bit_offset: 9
-  - bit_offset: 12
-    bit_size: 1
-    description: nRST_STOP
-    name: nRST_STOP
-  - bit_offset: 13
-    bit_size: 1
-    description: nRST_STDBY
-    name: nRST_STDBY
-  - bit_offset: 14
-    bit_size: 1
-    description: nRST_SHDW
-    name: nRST_SHDW
-  - bit_offset: 16
-    bit_size: 1
-    description: Independent watchdog selection
-    name: IDWG_SW
-  - bit_offset: 17
-    bit_size: 1
-    description: Independent watchdog counter freeze in Stop mode
-    name: IWDG_STOP
-  - bit_offset: 18
-    bit_size: 1
-    description: Independent watchdog counter freeze in Standby mode
-    name: IWDG_STDBY
-  - bit_offset: 19
-    bit_size: 1
-    description: Window watchdog selection
-    name: WWDG_SW
-  - bit_offset: 23
-    bit_size: 1
-    description: Boot configuration
-    name: nBOOT1
-  - bit_offset: 24
-    bit_size: 1
-    description: SRAM2 parity check enable
-    name: SRAM2_PE
-  - bit_offset: 25
-    bit_size: 1
-    description: SRAM2 Erase when system reset
-    name: SRAM2_RST
-  - bit_offset: 26
-    bit_size: 1
-    description: Software Boot0
-    name: nSWBOOT0
-  - bit_offset: 27
-    bit_size: 1
-    description: nBoot0 option bit
-    name: nBOOT0
-  - bit_offset: 29
       bit_size: 3
+    - name: nRST_STOP
+      description: nRST_STOP
+      bit_offset: 12
+      bit_size: 1
+    - name: nRST_STDBY
+      description: nRST_STDBY
+      bit_offset: 13
+      bit_size: 1
+    - name: nRST_SHDW
+      description: nRST_SHDW
+      bit_offset: 14
+      bit_size: 1
+    - name: IDWG_SW
+      description: Independent watchdog selection
+      bit_offset: 16
+      bit_size: 1
+    - name: IWDG_STOP
+      description: Independent watchdog counter freeze in Stop mode
+      bit_offset: 17
+      bit_size: 1
+    - name: IWDG_STDBY
+      description: Independent watchdog counter freeze in Standby mode
+      bit_offset: 18
+      bit_size: 1
+    - name: WWDG_SW
+      description: Window watchdog selection
+      bit_offset: 19
+      bit_size: 1
+    - name: nBOOT1
+      description: Boot configuration
+      bit_offset: 23
+      bit_size: 1
+    - name: SRAM2_PE
+      description: SRAM2 parity check enable
+      bit_offset: 24
+      bit_size: 1
+    - name: SRAM2_RST
+      description: SRAM2 Erase when system reset
+      bit_offset: 25
+      bit_size: 1
+    - name: nSWBOOT0
+      description: Software Boot0
+      bit_offset: 26
+      bit_size: 1
+    - name: nBOOT0
+      description: nBoot0 option bit
+      bit_offset: 27
+      bit_size: 1
+    - name: AGC_TRIM
       description: Radio Automatic Gain Control Trimming
-    name: AGC_TRIM
+      bit_offset: 29
+      bit_size: 3
 fieldset/PCROP1AER:
   description: Flash Bank 1 PCROP End address zone A register
   fields:
-  - bit_offset: 0
+    - name: PCROP1A_END
-    bit_size: 9
       description: Bank 1 PCROP area end offset
-    name: PCROP1A_END
+      bit_offset: 0
-  - bit_offset: 31
+      bit_size: 9
-    bit_size: 1
+    - name: PCROP_RDP
       description: PCROP area preserved when RDP level decreased
-    name: PCROP_RDP
+      bit_offset: 31
+      bit_size: 1
 fieldset/PCROP1ASR:
   description: Flash Bank 1 PCROP Start address zone A register
   fields:
-  - bit_offset: 0
+    - name: PCROP1A_STRT
-    bit_size: 9
       description: Bank 1 PCROPQ area start offset
-    name: PCROP1A_STRT
+      bit_offset: 0
+      bit_size: 9
 fieldset/PCROP1BER:
   description: Flash Bank 1 PCROP End address area B register
   fields:
-  - bit_offset: 0
+    - name: PCROP1B_END
-    bit_size: 9
       description: Bank 1 PCROP area end area B offset
-    name: PCROP1B_END
+      bit_offset: 0
+      bit_size: 9
 fieldset/PCROP1BSR:
   description: Flash Bank 1 PCROP Start address area B register
   fields:
-  - bit_offset: 0
+    - name: PCROP1B_STRT
-    bit_size: 9
       description: Bank 1 PCROP area B start offset
-    name: PCROP1B_STRT
+      bit_offset: 0
+      bit_size: 9
 fieldset/SFR:
   description: Secure flash start address register
   fields:
-  - bit_offset: 0
+    - name: SFSA
-    bit_size: 8
       description: Secure flash start address
-    name: SFSA
+      bit_offset: 0
-  - bit_offset: 8
+      bit_size: 8
-    bit_size: 1
+    - name: FSD
       description: Flash security disable
-    name: FSD
+      bit_offset: 8
-  - bit_offset: 12
       bit_size: 1
+    - name: DDS
       description: Disable Cortex M0 debug access
-    name: DDS
+      bit_offset: 12
+      bit_size: 1
 fieldset/SR:
   description: Status register
   fields:
-  - bit_offset: 0
+    - name: EOP
-    bit_size: 1
       description: End of operation
-    name: EOP
+      bit_offset: 0
-  - bit_offset: 1
       bit_size: 1
+    - name: OPERR
       description: Operation error
-    name: OPERR
+      bit_offset: 1
-  - bit_offset: 3
       bit_size: 1
+    - name: PROGERR
       description: Programming error
-    name: PROGERR
+      bit_offset: 3
-  - bit_offset: 4
       bit_size: 1
+    - name: WRPERR
       description: Write protected error
-    name: WRPERR
+      bit_offset: 4
-  - bit_offset: 5
       bit_size: 1
+    - name: PGAERR
       description: Programming alignment error
-    name: PGAERR
+      bit_offset: 5
-  - bit_offset: 6
       bit_size: 1
+    - name: SIZERR
       description: Size error
-    name: SIZERR
+      bit_offset: 6
-  - bit_offset: 7
       bit_size: 1
+    - name: PGSERR
       description: Programming sequence error
-    name: PGSERR
+      bit_offset: 7
-  - bit_offset: 8
       bit_size: 1
+    - name: MISERR
       description: Fast programming data miss error
-    name: MISERR
+      bit_offset: 8
-  - bit_offset: 9
       bit_size: 1
+    - name: FASTERR
       description: Fast programming error
-    name: FASTERR
+      bit_offset: 9
-  - bit_offset: 13
       bit_size: 1
+    - name: OPTNV
       description: User Option OPTVAL indication
-    name: OPTNV
+      bit_offset: 13
-  - bit_offset: 14
       bit_size: 1
+    - name: RDERR
       description: PCROP read error
-    name: RDERR
+      bit_offset: 14
-  - bit_offset: 15
       bit_size: 1
+    - name: OPTVERR
       description: Option validity error
-    name: OPTVERR
+      bit_offset: 15
-  - bit_offset: 16
       bit_size: 1
+    - name: BSY
       description: Busy
-    name: BSY
+      bit_offset: 16
-  - bit_offset: 18
       bit_size: 1
+    - name: CFGBSY
       description: Programming or erase configuration busy
-    name: CFGBSY
+      bit_offset: 18
-  - bit_offset: 19
       bit_size: 1
+    - name: PESD
       description: Programming or erase operation suspended
-    name: PESD
+      bit_offset: 19
+      bit_size: 1
 fieldset/SRRVR:
   description: Secure SRAM2 start address and cortex M0 reset vector register
   fields:
-  - bit_offset: 0
+    - name: SBRV
-    bit_size: 18
       description: cortex M0 access control register
-    name: SBRV
+      bit_offset: 0
-  - bit_offset: 18
+      bit_size: 18
-    bit_size: 5
+    - name: SBRSA
       description: Secure backup SRAM2a start address
-    name: SBRSA
+      bit_offset: 18
-  - bit_offset: 23
-    bit_size: 1
-    description: backup SRAM2a security disable
-    name: BRSD
-  - bit_offset: 25
       bit_size: 5
+    - name: BRSD
+      description: backup SRAM2a security disable
+      bit_offset: 23
+      bit_size: 1
+    - name: SNBRSA
       description: Secure non backup SRAM2a start address
-    name: SNBRSA
+      bit_offset: 25
-  - bit_offset: 30
+      bit_size: 5
-    bit_size: 1
+    - name: NBRSD
       description: non-backup SRAM2b security disable
-    name: NBRSD
+      bit_offset: 30
-  - bit_offset: 31
       bit_size: 1
+    - name: C2OPT
       description: CPU2 cortex M0 boot reset vector memory selection
-    name: C2OPT
+      bit_offset: 31
+      bit_size: 1
 fieldset/WRP1AR:
   description: Flash Bank 1 WRP area A address register
   fields:
-  - bit_offset: 0
+    - name: WRP1A_STRT
-    bit_size: 8
       description: Bank 1 WRP first area A start offset
-    name: WRP1A_STRT
+      bit_offset: 0
-  - bit_offset: 16
       bit_size: 8
+    - name: WRP1A_END
       description: Bank 1 WRP first area A end offset
-    name: WRP1A_END
+      bit_offset: 16
+      bit_size: 8
 fieldset/WRP1BR:
   description: Flash Bank 1 WRP area B address register
   fields:
-  - bit_offset: 0
+    - name: WRP1B_END
-    bit_size: 8
       description: Bank 1 WRP second area B start offset
-    name: WRP1B_END
+      bit_offset: 0
-  - bit_offset: 16
       bit_size: 8
+    - name: WRP1B_STRT
       description: Bank 1 WRP second area B end offset
-    name: WRP1B_STRT
+      bit_offset: 16
+      bit_size: 8

data/registers/gpio_v1.yaml

@@ -65,14 +65,6 @@ fieldset/BSRR:
 fieldset/CR:
   description: Port configuration register (GPIOn_CRx)
   fields:
-    - name: CNF
-      description: Port n configuration bits
-      bit_offset: 2
-      bit_size: 2
-      array:
-        len: 8
-        stride: 4
-      enum: CNF
     - name: MODE
       description: Port n mode bits
       bit_offset: 0
@@ -81,6 +73,14 @@ fieldset/CR:
         len: 8
         stride: 4
       enum: MODE
+    - name: CNF
+      description: Port n configuration bits
+      bit_offset: 2
+      bit_size: 2
+      array:
+        len: 8
+        stride: 4
+      enum: CNF
 fieldset/IDR:
   description: Port input data register (GPIOn_IDR)
   fields:
@@ -95,11 +95,6 @@ fieldset/IDR:
 fieldset/LCKR:
   description: Port configuration lock register
   fields:
-    - name: LCKK
-      description: Lock key
-      bit_offset: 16
-      bit_size: 1
-      enum: LCKK
     - name: LCK
       description: Port A Lock bit
       bit_offset: 0
@@ -108,6 +103,11 @@ fieldset/LCKR:
         len: 16
         stride: 1
       enum: LCK
+    - name: LCKK
+      description: Lock key
+      bit_offset: 16
+      bit_size: 1
+      enum: LCKK
 fieldset/ODR:
   description: Port output data register (GPIOn_ODR)
   fields:
@@ -155,12 +155,12 @@ enum/CNF:
 enum/IDR:
   bit_size: 1
   variants:
-    - name: High
-      description: Input is logic high
-      value: 1
     - name: Low
       description: Input is logic low
       value: 0
+    - name: High
+      description: Input is logic high
+      value: 1
 enum/LCK:
   bit_size: 1
   variants:
@@ -197,9 +197,9 @@ enum/MODE:
 enum/ODR:
   bit_size: 1
   variants:
-    - name: High
-      description: Set output to logic high
-      value: 1
     - name: Low
       description: Set output to logic low
       value: 0
+    - name: High
+      description: Set output to logic high
+      value: 1

data/registers/gpio_v2.yaml

@@ -57,14 +57,6 @@ fieldset/AFR:
 fieldset/BSRR:
   description: GPIO port bit set/reset register
   fields:
-    - name: BR
-      description: Port x set bit y (y= 0..15)
-      bit_offset: 16
-      bit_size: 1
-      array:
-        len: 16
-        stride: 1
-      enum_write: BRW
     - name: BS
       description: Port x set bit y (y= 0..15)
       bit_offset: 0
@@ -73,6 +65,14 @@ fieldset/BSRR:
         len: 16
         stride: 1
       enum_write: BSW
+    - name: BR
+      description: Port x set bit y (y= 0..15)
+      bit_offset: 16
+      bit_size: 1
+      array:
+        len: 16
+        stride: 1
+      enum_write: BRW
 fieldset/IDR:
   description: GPIO port input data register
   fields:
@@ -87,11 +87,6 @@ fieldset/IDR:
 fieldset/LCKR:
   description: GPIO port configuration lock register
   fields:
-    - name: LCKK
-      description: Port x lock bit y (y= 0..15)
-      bit_offset: 16
-      bit_size: 1
-      enum: LCKK
     - name: LCK
       description: Port x lock bit y (y= 0..15)
       bit_offset: 0
@@ -100,6 +95,11 @@ fieldset/LCKR:
         len: 16
         stride: 1
       enum: LCK
+    - name: LCKK
+      description: Port x lock bit y (y= 0..15)
+      bit_offset: 16
+      bit_size: 1
+      enum: LCKK
 fieldset/MODER:
   description: GPIO port mode register
   fields:
@@ -221,12 +221,12 @@ enum/BSW:
 enum/IDR:
   bit_size: 1
   variants:
-    - name: High
-      description: Input is logic high
-      value: 1
     - name: Low
       description: Input is logic low
       value: 0
+    - name: High
+      description: Input is logic high
+      value: 1
 enum/LCK:
   bit_size: 1
   variants:
@@ -263,12 +263,12 @@ enum/MODER:
 enum/ODR:
   bit_size: 1
   variants:
-    - name: High
-      description: Set output to logic high
-      value: 1
     - name: Low
       description: Set output to logic low
       value: 0
+    - name: High
+      description: Set output to logic high
+      value: 1
 enum/OSPEEDR:
   bit_size: 2
   variants:

data/registers/mdios_v1.yaml

@@ -2,14 +2,14 @@
 block/MDIOS:
   description: Management data input/output slave
   items:
-    - name: MDIOS_CR
-      description: MDIOS configuration register
-      byte_offset: 0
-      fieldset: MDIOS_CR
     - name: CR
       description: MDIOS configuration register
       byte_offset: 0
       fieldset: CR
+    - name: MDIOS_CR
+      description: MDIOS configuration register
+      byte_offset: 0
+      fieldset: MDIOS_CR
     - name: MDIOS_WRFR
       description: MDIOS write flag register
       byte_offset: 4
@@ -20,14 +20,14 @@ block/MDIOS:
       byte_offset: 4
       access: Read
       fieldset: WRFR
-    - name: MDIOS_CWRFR
-      description: MDIOS clear write flag register
-      byte_offset: 8
-      fieldset: MDIOS_CWRFR
     - name: CWRFR
       description: MDIOS clear write flag register
       byte_offset: 8
       fieldset: CWRFR
+    - name: MDIOS_CWRFR
+      description: MDIOS clear write flag register
+      byte_offset: 8
+      fieldset: MDIOS_CWRFR
     - name: MDIOS_RDFR
       description: MDIOS read flag register
       byte_offset: 12
@@ -38,14 +38,14 @@ block/MDIOS:
       byte_offset: 12
       access: Read
       fieldset: RDFR
-    - name: MDIOS_CRDFR
-      description: MDIOS clear read flag register
-      byte_offset: 16
-      fieldset: MDIOS_CRDFR
     - name: CRDFR
       description: MDIOS clear read flag register
       byte_offset: 16
       fieldset: CRDFR
+    - name: MDIOS_CRDFR
+      description: MDIOS clear read flag register
+      byte_offset: 16
+      fieldset: MDIOS_CRDFR
     - name: MDIOS_SR
       description: MDIOS status register
       byte_offset: 20
@@ -56,19 +56,14 @@ block/MDIOS:
       byte_offset: 20
       access: Read
       fieldset: SR
-    - name: MDIOS_CLRFR
-      description: MDIOS clear flag register
-      byte_offset: 24
-      fieldset: MDIOS_CLRFR
     - name: CLRFR
       description: MDIOS clear flag register
       byte_offset: 24
       fieldset: CLRFR
-    - name: MDIOS_DINR0
+    - name: MDIOS_CLRFR
-      description: MDIOS input data register 0
+      description: MDIOS clear flag register
-      byte_offset: 28
+      byte_offset: 24
-      access: Read
+      fieldset: MDIOS_CLRFR
-      fieldset: MDIOS_DINR0
     - name: DINR
       description: MDIOS input data register %s
       array:
@@ -77,6 +72,11 @@ block/MDIOS:
       byte_offset: 28
       access: Read
       fieldset: DINR
+    - name: MDIOS_DINR0
+      description: MDIOS input data register 0
+      byte_offset: 28
+      access: Read
+      fieldset: MDIOS_DINR0
     - name: MDIOS_DINR1
       description: MDIOS input data register 1
       byte_offset: 32
@@ -232,10 +232,6 @@ block/MDIOS:
       byte_offset: 152
       access: Read
       fieldset: MDIOS_DINR31
-    - name: MDIOS_DOUTR0
-      description: MDIOS output data register 0
-      byte_offset: 156
-      fieldset: MDIOS_DOUTR0
     - name: DOUTR
       description: MDIOS output data register %s
       array:
@@ -243,6 +239,10 @@ block/MDIOS:
         stride: 4
       byte_offset: 156
       fieldset: DOUTR
+    - name: MDIOS_DOUTR0
+      description: MDIOS output data register 0
+      byte_offset: 156
+      fieldset: MDIOS_DOUTR0
     - name: MDIOS_DOUTR1
       description: MDIOS output data register 1
       byte_offset: 160

data/registers/otghs_v1.yaml

@@ -62,16 +62,16 @@ block/OTG_HS:
       description: OTG_HS nonperiodic transmit FIFO size register (host mode)
       byte_offset: 40
       fieldset: OTG_HS_HNPTXFSIZ_Host
-    - name: OTG_HS_HNPTXSTS
-      description: OTG_HS nonperiodic transmit FIFO/queue status register
-      byte_offset: 44
-      access: Read
-      fieldset: OTG_HS_HNPTXSTS
     - name: OTG_HS_GNPTXSTS
       description: OTG_HS nonperiodic transmit FIFO/queue status register
       byte_offset: 44
       access: Read
       fieldset: OTG_HS_GNPTXSTS
+    - name: OTG_HS_HNPTXSTS
+      description: OTG_HS nonperiodic transmit FIFO/queue status register
+      byte_offset: 44
+      access: Read
+      fieldset: OTG_HS_HNPTXSTS
     - name: OTG_HS_GI2CCTL
       description: OTG I2C access register
       byte_offset: 48

data/registers/pwr_f3.yaml

@@ -1,85 +1,86 @@
+---
 block/PWR:
   description: Power control
   items:
-  - byte_offset: 0
+    - name: CR
       description: power control register
+      byte_offset: 0
       fieldset: CR
-    name: CR
+    - name: CSR
-  - byte_offset: 4
       description: power control/status register
+      byte_offset: 4
       fieldset: CSR
-    name: CSR
-enum/PDDS:
-  bit_size: 1
-  variants:
-  - description: Enter Stop mode when the CPU enters deepsleep
-    name: STOP_MODE
-    value: 0
-  - description: Enter Standby mode when the CPU enters deepsleep
-    name: STANDBY_MODE
-    value: 1
 fieldset/CR:
   description: power control register
   fields:
-  - bit_offset: 0
+    - name: LPDS
-    bit_size: 1
       description: Low-power deep sleep
-    name: LPDS
+      bit_offset: 0
-  - bit_offset: 1
       bit_size: 1
+    - name: PDDS
       description: Power down deepsleep
+      bit_offset: 1
+      bit_size: 1
       enum: PDDS
-    name: PDDS
+    - name: CWUF
-  - bit_offset: 2
-    bit_size: 1
       description: Clear wakeup flag
-    name: CWUF
+      bit_offset: 2
-  - bit_offset: 3
       bit_size: 1
+    - name: CSBF
       description: Clear standby flag
-    name: CSBF
+      bit_offset: 3
-  - bit_offset: 4
       bit_size: 1
+    - name: PVDE
       description: Power voltage detector enable
-    name: PVDE
+      bit_offset: 4
-  - bit_offset: 5
-    bit_size: 3
-    description: PVD level selection
-    name: PLS
-  - bit_offset: 8
       bit_size: 1
+    - name: PLS
+      description: PVD level selection
+      bit_offset: 5
+      bit_size: 3
+    - name: DBP
       description: Disable backup domain write protection
-    name: DBP
+      bit_offset: 8
-  - array:
+      bit_size: 1
-      len: 3
+    - name: ENSD
-      stride: 1
+      description: ENable SD1 ADC
       bit_offset: 9
       bit_size: 1
-    description: ENable SD1 ADC
+      array:
-    name: ENSD
+        len: 3
+        stride: 1
 fieldset/CSR:
   description: power control/status register
   fields:
-  - bit_offset: 0
+    - name: WUF
-    bit_size: 1
       description: Wakeup flag
-    name: WUF
+      bit_offset: 0
-  - bit_offset: 1
       bit_size: 1
+    - name: SBF
       description: Standby flag
-    name: SBF
+      bit_offset: 1
-  - bit_offset: 2
       bit_size: 1
+    - name: PVDO
       description: PVD output
-    name: PVDO
+      bit_offset: 2
-  - bit_offset: 3
       bit_size: 1
+    - name: VREFINTRDYF
       description: Internal voltage reference ready flag
-    name: VREFINTRDYF
+      bit_offset: 3
-  - array:
+      bit_size: 1
-      len: 2
+    - name: EWUP
-      stride: 1
+      description: Enable WKUP1 pin
       bit_offset: 8
       bit_size: 1
-    description: Enable WKUP1 pin
+      array:
-    name: EWUP
+        len: 2
+        stride: 1
+enum/PDDS:
+  bit_size: 1
+  variants:
+    - name: STOP_MODE
+      description: Enter Stop mode when the CPU enters deepsleep
+      value: 0
+    - name: STANDBY_MODE
+      description: Enter Standby mode when the CPU enters deepsleep
+      value: 1

data/registers/pwr_f4.yaml

@@ -64,15 +64,15 @@ fieldset/CR1:
       bit_size: 2
       enum: VOS
     - name: ODEN
-      description: Over-drive enable (STM32F4[23] ONLY)
+      description: "Over-drive enable (STM32F4[23] ONLY)"
       bit_offset: 16
       bit_size: 1
     - name: ODSWEN
-      description: Over-drive switching enabled (STM32F4[23] ONLY)
+      description: "Over-drive switching enabled (STM32F4[23] ONLY)"
       bit_offset: 17
       bit_size: 1
     - name: UDEN
-      description: Under-drive enable in stop mode (STM32F4[23] ONLY)
+      description: "Under-drive enable in stop mode (STM32F4[23] ONLY)"
       bit_offset: 18
       bit_size: 2
     - name: FMSSR
@@ -115,15 +115,15 @@ fieldset/CSR1:
       bit_offset: 9
       bit_size: 1
     - name: VOSRDY
-      description: Regulator voltage scaling output selection ready bit (STM32F4[23] ONLY)
+      description: "Regulator voltage scaling output selection ready bit (STM32F4[23] ONLY)"
       bit_offset: 14
       bit_size: 1
     - name: ODRDY
-      description: Over-drive mode ready (STM32F4[23] ONLY)
+      description: "Over-drive mode ready (STM32F4[23] ONLY)"
       bit_offset: 16
       bit_size: 1
     - name: ODSWRDY
-      description: Over-drive mode switching ready (STM32F4[23] ONLY)
+      description: "Over-drive mode switching ready (STM32F4[23] ONLY)"
       bit_offset: 17
       bit_size: 1
     - name: UDRDY
@@ -143,7 +143,7 @@ enum/VOS:
   bit_size: 2
   variants:
     - name: SCALE3
-      description: Scale 3 mode (STM32F4[23] ONLY)
+      description: "Scale 3 mode (STM32F4[23] ONLY)"
       value: 1
     - name: SCALE2
       description: Scale 2 mode

data/registers/pwr_g0.yaml

@@ -35,18 +35,18 @@ block/PWR:
       fieldset: SCR
     - name: PUCR
       description: Power Port pull-up control register
+      array:
+        len: 6
+        stride: 8
       byte_offset: 32
       fieldset: PCR
-      array:
-        len: 6
-        stride: 8
     - name: PDCR
       description: Power Port pull-down control register
-      byte_offset: 36
-      fieldset: PCR
       array:
         len: 6
         stride: 8
+      byte_offset: 36
+      fieldset: PCR
 fieldset/CR1:
   description: Power control register 1
   fields:

data/registers/pwr_g4.yaml

@@ -35,18 +35,18 @@ block/PWR:
       fieldset: SCR
     - name: PUCR
       description: Power Port pull-up control register
+      array:
+        len: 7
+        stride: 8
       byte_offset: 32
       fieldset: PCR
-      array:
-        len: 7
-        stride: 8
     - name: PDCR
       description: Power Port pull-down control register
-      byte_offset: 36
-      fieldset: PCR
       array:
         len: 7
         stride: 8
+      byte_offset: 36
+      fieldset: PCR
     - name: CR5
       description: Power control register 5
       byte_offset: 128

data/registers/pwr_u5.yaml

@@ -83,18 +83,18 @@ block/PWR:
       fieldset: APCR
     - name: PUCR
       description: Power Port pull-up control register
+      array:
+        len: 9
+        stride: 8
       byte_offset: 80
       fieldset: PCR
-      array:
-        len: 9
-        stride: 8
     - name: PDCR
       description: Power Port pull-down control register
-      byte_offset: 84
-      fieldset: PCR
       array:
         len: 9
         stride: 8
+      byte_offset: 84
+      fieldset: PCR
 fieldset/APCR:
   description: "PWR apply pull configuration register "
   fields:

data/registers/pwr_wl5.yaml

@@ -39,18 +39,18 @@ block/PWR:
       fieldset: CR5
     - name: PUCR
       description: Power Port pull-up control register
+      array:
+        len: 8
+        stride: 8
       byte_offset: 32
       fieldset: PCR
-      array:
-        len: 8
-        stride: 8
     - name: PDCR
       description: Power Port pull-down control register
-      byte_offset: 36
-      fieldset: PCR
       array:
         len: 8
         stride: 8
+      byte_offset: 36
+      fieldset: PCR
     - name: C2CR1
       description: "Power CPU2 control register 1 [dual core device only]"
       byte_offset: 128

data/registers/rcc_f1.yaml

@@ -187,14 +187,14 @@ fieldset/APB1ENR:
       description: USB clock enable
       bit_offset: 23
       bit_size: 1
-    - name: CANEN
-      description: CAN clock enable
-      bit_offset: 25
-      bit_size: 1
     - name: CAN1EN
       description: CAN1 clock enable
       bit_offset: 25
       bit_size: 1
+    - name: CANEN
+      description: CAN clock enable
+      bit_offset: 25
+      bit_size: 1
     - name: CAN2EN
       description: CAN2 clock enable
       bit_offset: 26
@@ -294,14 +294,14 @@ fieldset/APB1RSTR:
       description: USB reset
       bit_offset: 23
       bit_size: 1
-    - name: CANRST
-      description: CAN reset
-      bit_offset: 25
-      bit_size: 1
     - name: CAN1RST
       description: CAN1 reset
       bit_offset: 25
       bit_size: 1
+    - name: CANRST
+      description: CAN reset
+      bit_offset: 25
+      bit_size: 1
     - name: CAN2RST
       description: CAN2 reset
       bit_offset: 26
@@ -572,16 +572,16 @@ fieldset/CFGR:
       bit_offset: 18
       bit_size: 4
       enum: PLLMUL
-    - name: USBPRE
-      description: USB prescaler
-      bit_offset: 22
-      bit_size: 1
-      enum: USBPRE
     - name: OTGFSPRE
       description: USB OTG FS prescaler
       bit_offset: 22
       bit_size: 1
       enum: OTGFSPRE
+    - name: USBPRE
+      description: USB prescaler
+      bit_offset: 22
+      bit_size: 1
+      enum: USBPRE
     - name: MCO
       description: Microcontroller clock output
       bit_offset: 24

data/registers/rcc_f3.yaml

@@ -117,14 +117,14 @@ fieldset/AHBENR:
       description: Touch sensing controller clock enable
       bit_offset: 24
       bit_size: 1
-    - name: ADC1EN
-      description: ADC 1
-      bit_offset: 28
-      bit_size: 1
     - name: ADC12EN
       description: ADC1 and ADC2 clock enable
       bit_offset: 28
       bit_size: 1
+    - name: ADC1EN
+      description: ADC 1
+      bit_offset: 28
+      bit_size: 1
     - name: ADC34EN
       description: ADC3 and ADC4 clock enable
       bit_offset: 29
@@ -172,14 +172,14 @@ fieldset/AHBRSTR:
       description: Touch sensing controller reset
       bit_offset: 24
       bit_size: 1
-    - name: ADC1RST
-      description: ADC1 reset
-      bit_offset: 28
-      bit_size: 1
     - name: ADC12RST
       description: ADC1 and ADC2 reset
       bit_offset: 28
       bit_size: 1
+    - name: ADC1RST
+      description: ADC1 reset
+      bit_offset: 28
+      bit_size: 1
     - name: ADC34RST
       description: ADC3 and ADC4 reset
       bit_offset: 29
@@ -283,14 +283,14 @@ fieldset/APB1ENR:
       description: DAC interface clock enable
       bit_offset: 29
       bit_size: 1
-    - name: I2C3EN
-      description: I2C3 clock enable
-      bit_offset: 30
-      bit_size: 1
     - name: CECEN
       description: HDMI CEC interface clock enable
       bit_offset: 30
       bit_size: 1
+    - name: I2C3EN
+      description: I2C3 clock enable
+      bit_offset: 30
+      bit_size: 1
 fieldset/APB1RSTR:
   description: APB1 peripheral reset register (RCC_APB1RSTR)
   fields:
@@ -390,14 +390,14 @@ fieldset/APB1RSTR:
       description: DAC interface reset
       bit_offset: 29
       bit_size: 1
-    - name: I2C3RST
-      description: I2C3 reset
-      bit_offset: 30
-      bit_size: 1
     - name: CECRST
       description: HDMI CEC reset
       bit_offset: 30
       bit_size: 1
+    - name: I2C3RST
+      description: I2C3 reset
+      bit_offset: 30
+      bit_size: 1
 fieldset/APB2ENR:
   description: APB2 peripheral clock enable register (RCC_APB2ENR)
   fields:
@@ -655,13 +655,13 @@ fieldset/CFGR2:
       bit_offset: 0
       bit_size: 4
       enum: PREDIV
-    - name: ADC1PRES
+    - name: ADC12PRES
-      description: ADC1 prescaler
+      description: ADC1 and ADC2 prescaler
       bit_offset: 4
       bit_size: 5
       enum: ADCPRES
-    - name: ADC12PRES
+    - name: ADC1PRES
-      description: ADC1 and ADC2 prescaler
+      description: ADC1 prescaler
       bit_offset: 4
       bit_size: 5
       enum: ADCPRES
@@ -688,16 +688,16 @@ fieldset/CFGR3:
       bit_offset: 5
       bit_size: 1
       enum: ICSW
-    - name: I2C3SW
-      description: I2C3 clock source selection
-      bit_offset: 6
-      bit_size: 1
-      enum: ICSW
     - name: CECSW
       description: HDMI CEC clock source selection
       bit_offset: 6
       bit_size: 1
       enum: CECSW
+    - name: I2C3SW
+      description: I2C3 clock source selection
+      bit_offset: 6
+      bit_size: 1
+      enum: ICSW
     - name: TIM1SW
       description: Timer1 clock source selection
       bit_offset: 8

data/registers/rcc_l0.yaml

@@ -10,6 +10,10 @@ block/RCC:
       description: Internal clock sources calibration register
       byte_offset: 4
       fieldset: ICSCR
+    - name: CRRCR
+      description: Clock recovery RC register
+      byte_offset: 8
+      fieldset: CRRCR
     - name: CFGR
       description: Clock configuration register
       byte_offset: 12
@@ -85,10 +89,6 @@ block/RCC:
       description: Control and status register
       byte_offset: 80
       fieldset: CSR
-    - name: CRRCR
-      description: Clock recovery RC register
-      byte_offset: 8
-      fieldset: CRRCR
 fieldset/AHBENR:
   description: AHB peripheral clock enable register
   fields:
@@ -104,10 +104,6 @@ fieldset/AHBENR:
       description: CRC clock enable
       bit_offset: 12
       bit_size: 1
-    - name: CRYPEN
-      description: Crypto clock enable
-      bit_offset: 24
-      bit_size: 1
     - name: TOUCHEN
       description: Touch Sensing clock enable
       bit_offset: 16
@@ -116,6 +112,10 @@ fieldset/AHBENR:
       description: Random Number Generator clock enable
       bit_offset: 20
       bit_size: 1
+    - name: CRYPEN
+      description: Crypto clock enable
+      bit_offset: 24
+      bit_size: 1
 fieldset/AHBRSTR:
   description: AHB peripheral reset register
   fields:
@@ -131,10 +131,6 @@ fieldset/AHBRSTR:
       description: Test integration module reset
       bit_offset: 12
       bit_size: 1
-    - name: CRYPRST
-      description: Crypto module reset
-      bit_offset: 24
-      bit_size: 1
     - name: TOUCHRST
       description: Touch Sensing reset
       bit_offset: 16
@@ -143,6 +139,10 @@ fieldset/AHBRSTR:
       description: Random Number Generator module reset
       bit_offset: 20
       bit_size: 1
+    - name: CRYPRST
+      description: Crypto module reset
+      bit_offset: 24
+      bit_size: 1
 fieldset/AHBSMENR:
   description: AHB peripheral clock enable in sleep mode register
   fields:
@@ -162,10 +162,6 @@ fieldset/AHBSMENR:
       description: CRC clock enable during sleep mode
       bit_offset: 12
       bit_size: 1
-    - name: CRYPSMEN
-      description: Crypto clock enable during sleep mode
-      bit_offset: 24
-      bit_size: 1
     - name: TOUCHSMEN
       description: Touch Sensing clock enable during sleep mode
       bit_offset: 16
@@ -174,6 +170,10 @@ fieldset/AHBSMENR:
       description: Random Number Generator clock enable during sleep mode
       bit_offset: 20
       bit_size: 1
+    - name: CRYPSMEN
+      description: Crypto clock enable during sleep mode
+      bit_offset: 24
+      bit_size: 1
 fieldset/APB1ENR:
   description: APB1 peripheral clock enable register
   fields:
@@ -181,6 +181,10 @@ fieldset/APB1ENR:
       description: Timer2 clock enable
       bit_offset: 0
       bit_size: 1
+    - name: TIM3EN
+      description: Timer 3 clock enbale
+      bit_offset: 1
+      bit_size: 1
     - name: TIM6EN
       description: Timer 6 clock enable
       bit_offset: 4
@@ -221,22 +225,6 @@ fieldset/APB1ENR:
       description: I2C2 clock enable
       bit_offset: 22
       bit_size: 1
-    - name: PWREN
-      description: Power interface clock enable
-      bit_offset: 28
-      bit_size: 1
-    - name: I2C3EN
-      description: I2C3 clock enable
-      bit_offset: 30
-      bit_size: 1
-    - name: LPTIM1EN
-      description: Low power timer clock enable
-      bit_offset: 31
-      bit_size: 1
-    - name: TIM3EN
-      description: Timer 3 clock enbale
-      bit_offset: 1
-      bit_size: 1
     - name: USBEN
       description: USB clock enable
       bit_offset: 23
@@ -245,10 +233,22 @@ fieldset/APB1ENR:
       description: Clock recovery system clock enable
       bit_offset: 27
       bit_size: 1
+    - name: PWREN
+      description: Power interface clock enable
+      bit_offset: 28
+      bit_size: 1
     - name: DACEN
       description: DAC interface clock enable
       bit_offset: 29
       bit_size: 1
+    - name: I2C3EN
+      description: I2C3 clock enable
+      bit_offset: 30
+      bit_size: 1
+    - name: LPTIM1EN
+      description: Low power timer clock enable
+      bit_offset: 31
+      bit_size: 1
 fieldset/APB1RSTR:
   description: APB1 peripheral reset register
   fields:
@@ -300,18 +300,6 @@ fieldset/APB1RSTR:
       description: I2C2 reset
       bit_offset: 22
       bit_size: 1
-    - name: PWRRST
-      description: Power interface reset
-      bit_offset: 28
-      bit_size: 1
-    - name: LPTIM1RST
-      description: Low power timer reset
-      bit_offset: 31
-      bit_size: 1
-    - name: I2C3RST
-      description: I2C3 reset
-      bit_offset: 30
-      bit_size: 1
     - name: USBRST
       description: USB reset
       bit_offset: 23
@@ -320,10 +308,22 @@ fieldset/APB1RSTR:
       description: Clock recovery system reset
       bit_offset: 27
       bit_size: 1
+    - name: PWRRST
+      description: Power interface reset
+      bit_offset: 28
+      bit_size: 1
     - name: DACRST
       description: DAC interface reset
       bit_offset: 29
       bit_size: 1
+    - name: I2C3RST
+      description: I2C3 reset
+      bit_offset: 30
+      bit_size: 1
+    - name: LPTIM1RST
+      description: Low power timer reset
+      bit_offset: 31
+      bit_size: 1
 fieldset/APB1SMENR:
   description: APB1 peripheral clock enable in sleep mode register
   fields:
@@ -375,6 +375,10 @@ fieldset/APB1SMENR:
       description: I2C2 clock enable during sleep mode
       bit_offset: 22
       bit_size: 1
+    - name: USBSMEN
+      description: USB clock enable during sleep mode
+      bit_offset: 23
+      bit_size: 1
     - name: CRSSMEN
       description: Clock recovery system clock enable during sleep mode
       bit_offset: 27
@@ -383,6 +387,10 @@ fieldset/APB1SMENR:
       description: Power interface clock enable during sleep mode
       bit_offset: 28
       bit_size: 1
+    - name: DACSMEN
+      description: DAC interface clock enable during sleep mode
+      bit_offset: 29
+      bit_size: 1
     - name: I2C3SMEN
       description: I2C3 clock enable during sleep mode
       bit_offset: 30
@@ -391,14 +399,6 @@ fieldset/APB1SMENR:
       description: Low power timer clock enable during sleep mode
       bit_offset: 31
       bit_size: 1
-    - name: USBSMEN
-      description: USB clock enable during sleep mode
-      bit_offset: 23
-      bit_size: 1
-    - name: DACSMEN
-      description: DAC interface clock enable during sleep mode
-      bit_offset: 29
-      bit_size: 1
 fieldset/APB2ENR:
   description: APB2 peripheral clock enable register
   fields:
@@ -418,6 +418,10 @@ fieldset/APB2ENR:
       description: Firewall clock enable
       bit_offset: 7
       bit_size: 1
+    - name: MIFIEN
+      description: MiFaRe Firewall clock enable
+      bit_offset: 7
+      bit_size: 1
     - name: ADCEN
       description: ADC clock enable
       bit_offset: 9
@@ -434,10 +438,6 @@ fieldset/APB2ENR:
       description: DBG clock enable
       bit_offset: 22
       bit_size: 1
-    - name: MIFIEN
-      description: MiFaRe Firewall clock enable
-      bit_offset: 7
-      bit_size: 1
 fieldset/APB2RSTR:
   description: APB2 peripheral reset register
   fields:
@@ -622,6 +622,10 @@ fieldset/CICR:
       description: MSI ready Interrupt clear
       bit_offset: 5
       bit_size: 1
+    - name: HSI48RDYC
+      description: HSI48 ready Interrupt clear
+      bit_offset: 6
+      bit_size: 1
     - name: CSSLSEC
       description: LSE Clock Security System Interrupt clear
       bit_offset: 7
@@ -630,10 +634,6 @@ fieldset/CICR:
       description: Clock Security System Interrupt clear
       bit_offset: 8
       bit_size: 1
-    - name: HSI48RDYC
-      description: HSI48 ready Interrupt clear
-      bit_offset: 6
-      bit_size: 1
 fieldset/CIER:
   description: Clock interrupt enable register
   fields:
@@ -661,14 +661,14 @@ fieldset/CIER:
       description: MSI ready interrupt flag
       bit_offset: 5
       bit_size: 1
-    - name: CSSLSE
-      description: LSE CSS interrupt flag
-      bit_offset: 7
-      bit_size: 1
     - name: HSI48RDYIE
       description: HSI48 ready interrupt flag
       bit_offset: 6
       bit_size: 1
+    - name: CSSLSE
+      description: LSE CSS interrupt flag
+      bit_offset: 7
+      bit_size: 1
 fieldset/CIFR:
   description: Clock interrupt flag register
   fields:
@@ -696,6 +696,10 @@ fieldset/CIFR:
       description: MSI ready interrupt flag
       bit_offset: 5
       bit_size: 1
+    - name: HSI48RDYF
+      description: HSI48 ready interrupt flag
+      bit_offset: 6
+      bit_size: 1
     - name: CSSLSEF
       description: LSE Clock Security System Interrupt flag
       bit_offset: 7
@@ -704,10 +708,6 @@ fieldset/CIFR:
       description: Clock Security System Interrupt flag
       bit_offset: 8
       bit_size: 1
-    - name: HSI48RDYF
-      description: HSI48 ready interrupt flag
-      bit_offset: 6
-      bit_size: 1
 fieldset/CR:
   description: Clock control register
   fields:

data/registers/rcc_l4.yaml

@@ -446,11 +446,11 @@ fieldset/AHB2SMENR:
       description: AES accelerator clocks enable during Sleep and Stop modes
       bit_offset: 16
       bit_size: 1
-    - name: HASHSMEN
+    - name: HASH1SMEN
       description: HASH clock enable during Sleep and Stop modes
       bit_offset: 17
       bit_size: 1
-    - name: HASH1SMEN
+    - name: HASHSMEN
       description: HASH clock enable during Sleep and Stop modes
       bit_offset: 17
       bit_size: 1
@@ -594,14 +594,14 @@ fieldset/APB1ENR1:
       description: CAN1 clock enable
       bit_offset: 25
       bit_size: 1
-    - name: USBFSEN
-      description: USB FS clock enable
-      bit_offset: 26
-      bit_size: 1
     - name: CAN2EN
       description: CAN2 clock enable
       bit_offset: 26
       bit_size: 1
+    - name: USBFSEN
+      description: USB FS clock enable
+      bit_offset: 26
+      bit_size: 1
     - name: PWREN
       description: Power interface clock enable
       bit_offset: 28
@@ -716,14 +716,14 @@ fieldset/APB1RSTR1:
       description: CAN1 reset
       bit_offset: 25
       bit_size: 1
-    - name: USBFSRST
-      description: USB FS reset
-      bit_offset: 26
-      bit_size: 1
     - name: CAN2RST
       description: CAN2 reset
       bit_offset: 26
       bit_size: 1
+    - name: USBFSRST
+      description: USB FS reset
+      bit_offset: 26
+      bit_size: 1
     - name: PWRRST
       description: Power interface reset
       bit_offset: 28
@@ -842,14 +842,14 @@ fieldset/APB1SMENR1:
       description: CAN1 clocks enable during Sleep and Stop modes
       bit_offset: 25
       bit_size: 1
-    - name: USBFSSMEN
-      description: USB FS clock enable during Sleep and Stop modes
-      bit_offset: 26
-      bit_size: 1
     - name: CAN2SMEN
       description: CAN2 clocks enable during Sleep and Stop modes
       bit_offset: 26
       bit_size: 1
+    - name: USBFSSMEN
+      description: USB FS clock enable during Sleep and Stop modes
+      bit_offset: 26
+      bit_size: 1
     - name: PWRSMEN
       description: Power interface clocks enable during Sleep and Stop modes
       bit_offset: 28
@@ -892,11 +892,11 @@ fieldset/APB2ENR:
       description: SYSCFG clock enable
       bit_offset: 0
       bit_size: 1
-    - name: FWEN
+    - name: FIREWALLEN
       description: Firewall clock enable
       bit_offset: 7
       bit_size: 1
-    - name: FIREWALLEN
+    - name: FWEN
       description: Firewall clock enable
       bit_offset: 7
       bit_size: 1
@@ -1535,11 +1535,11 @@ fieldset/CSR:
       description: Remove reset flag
       bit_offset: 23
       bit_size: 1
-    - name: FWRSTF
+    - name: FIREWALLRSTF
       description: Firewall reset flag
       bit_offset: 24
       bit_size: 1
-    - name: FIREWALLRSTF
+    - name: FWRSTF
       description: Firewall reset flag
       bit_offset: 24
       bit_size: 1

data/registers/rtc_v2.yaml

@@ -488,14 +488,14 @@ fieldset/ISR:
 fieldset/OR:
   description: option register
   fields:
-    - name: TSINSEL
-      description: TIMESTAMP mapping
-      bit_offset: 1
-      bit_size: 1
     - name: RTC_OUT_RMP
       description: RTC_OUT remap
       bit_offset: 1
       bit_size: 1
+    - name: TSINSEL
+      description: TIMESTAMP mapping
+      bit_offset: 1
+      bit_size: 1
     - name: RTC_ALARM_TYPE
       description: RTC_ALARM on PC13 output type
       bit_offset: 3

data/registers/timer_v1.yaml

@@ -3,18 +3,6 @@ block/TIM_ADV:
   extends: TIM_GP16
   description: Advanced-timers
   items:
-    - name: RCR
-      description: repetition counter register
-      byte_offset: 48
-      fieldset: RCR
-    - name: BDTR
-      description: break and dead-time register
-      byte_offset: 68
-      fieldset: BDTR
-    - name: CCER
-      description: capture/compare enable register
-      byte_offset: 32
-      fieldset: CCER_ADV
     - name: CR2
       description: control register 2
       byte_offset: 4
@@ -32,6 +20,18 @@ block/TIM_ADV:
       byte_offset: 20
       access: Write
       fieldset: EGR_ADV
+    - name: CCER
+      description: capture/compare enable register
+      byte_offset: 32
+      fieldset: CCER_ADV
+    - name: RCR
+      description: repetition counter register
+      byte_offset: 48
+      fieldset: RCR
+    - name: BDTR
+      description: break and dead-time register
+      byte_offset: 68
+      fieldset: BDTR
 block/TIM_BASIC:
   description: Basic timer
   items:
@@ -119,6 +119,13 @@ block/TIM_GP16:
       description: prescaler
       byte_offset: 40
       fieldset: PSC
+    - name: CCR
+      description: capture/compare register
+      array:
+        len: 4
+        stride: 4
+      byte_offset: 52
+      fieldset: CCR_16
     - name: DCR
       description: DMA control register
       byte_offset: 72
@@ -127,13 +134,6 @@ block/TIM_GP16:
       description: DMA address for full transfer
       byte_offset: 76
       fieldset: DMAR
-    - name: CCR
-      description: capture/compare register
-      array:
-        len: 4
-        stride: 4
-      byte_offset: 52
-      fieldset: CCR_16
 block/TIM_GP32:
   extends: TIM_GP16
   description: General purpose 32-bit timer

data/registers/usart_v2.yaml

@@ -116,6 +116,11 @@ fieldset/CR1:
       bit_offset: 12
       bit_size: 1
       enum: M0
+    - name: M1
+      description: Word length
+      bit_offset: 12
+      bit_size: 1
+      enum: M1
     - name: MME
       description: Mute mode enable
       bit_offset: 13
@@ -148,11 +153,6 @@ fieldset/CR1:
       description: End of Block interrupt enable
       bit_offset: 27
       bit_size: 1
-    - name: M1
-      description: Word length
-      bit_offset: 12
-      bit_size: 1
-      enum: M1
 fieldset/CR2:
   description: Control register 2
   fields: