1285 lines
37 KiB
YAML
1285 lines
37 KiB
YAML
---
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block/SYSCFG:
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description: System configuration controller
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items:
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- name: CFGR1
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description: configuration register 1
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byte_offset: 0
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fieldset: CFGR1
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- name: RCR
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description: CCM SRAM protection register
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byte_offset: 4
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fieldset: RCR
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- name: EXTICR
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description: external interrupt configuration register
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array:
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len: 4
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stride: 4
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byte_offset: 8
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fieldset: EXTICR
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- name: CFGR2
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description: configuration register 2
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byte_offset: 24
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fieldset: CFGR2
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- name: CFGR4
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description: configuration register 4
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byte_offset: 72
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fieldset: CFGR4
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- name: CFGR3
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description: configuration register 3
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byte_offset: 80
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fieldset: CFGR3
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fieldset/CFGR1:
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description: configuration register 1
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fields:
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- name: MEM_MODE
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description: Memory mapping selection bits
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bit_offset: 0
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bit_size: 2
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enum: MEM_MODE
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- name: USB_IT_RMP
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description: USB interrupt remap
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bit_offset: 5
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bit_size: 1
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enum: USB_IT_RMP
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- name: TIM1_ITR3_RMP
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description: Timer 1 ITR3 selection
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bit_offset: 6
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bit_size: 1
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enum: TIM1_ITR3_RMP
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- name: DAC1_TRIG_RMP
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description: DAC trigger remap (when TSEL = 001)
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bit_offset: 7
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bit_size: 1
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enum: DAC1_TRIG_RMP
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- name: DAC_TRIG_RMP
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description: DAC trigger remap (when TSEL = 001)
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bit_offset: 7
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bit_size: 1
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enum: DAC_TRIG_RMP
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- name: ADC2_DMA_RMP
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description: ADC24 DMA remapping bit
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bit_offset: 8
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bit_size: 1
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enum: ADC2_DMA_RMP
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- name: TIM16_DMA_RMP
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description: TIM16 DMA request remapping bit
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bit_offset: 11
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bit_size: 1
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enum: TIM16_DMA_RMP
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- name: TIM17_DMA_RMP
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description: TIM17 DMA request remapping bit
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bit_offset: 12
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bit_size: 1
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enum: TIM17_DMA_RMP
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- name: TIM6_DAC1_CH1_DMA_RMP
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description: TIM6 and DAC1 DMA request remapping bit
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bit_offset: 13
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bit_size: 1
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enum: TIM6_DAC1_CH1_DMA_RMP
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- name: TIM6_DAC1_DMA_RMP
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description: TIM6 and DAC1 DMA request remapping bit
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bit_offset: 13
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bit_size: 1
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enum: TIM6_DAC1_DMA_RMP
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- name: TIM6_DAC1_OUT1_DMA_RMP
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description: TIM6 and DAC1 DMA request remapping bit
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bit_offset: 13
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bit_size: 1
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enum: TIM6_DAC1_OUT1_DMA_RMP
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- name: TIM7_DAC1_CH2_DMA_RMP
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description: TIM7 and DAC2 DMA request remapping bit
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bit_offset: 14
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bit_size: 1
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enum: TIM7_DAC1_CH2_DMA_RMP
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- name: TIM7_DAC1_OUT2_DMA_RMP
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description: TIM7 and DAC2 DMA request remapping bit
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bit_offset: 14
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bit_size: 1
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enum: TIM7_DAC1_OUT2_DMA_RMP
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- name: DAC2_CH1_DMA_RMP
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description: DAC2 channel1 DMA remap
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bit_offset: 15
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bit_size: 1
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enum: DAC2_CH1_DMA_RMP
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- name: TIM18_DAC2_OUT1_DMA_RMP
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description: TIM18 and DAC2_OUT1 DMA request remapping bit
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bit_offset: 15
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bit_size: 1
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enum: TIM18_DAC2_OUT1_DMA_RMP
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- name: I2C_PB6_FMP
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description: Fast Mode Plus (FM+) driving capability activation bits.
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bit_offset: 16
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bit_size: 1
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enum: I2C_PB6_FMP
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- name: I2C_PB7_FMP
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description: Fast Mode Plus (FM+) driving capability activation bits.
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bit_offset: 17
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bit_size: 1
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enum: I2C_PB7_FMP
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- name: I2C_PB8_FMP
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description: Fast Mode Plus (FM+) driving capability activation bits.
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bit_offset: 18
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bit_size: 1
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enum: I2C_PB8_FMP
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- name: I2C_PB9_FMP
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description: Fast Mode Plus (FM+) driving capability activation bits.
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bit_offset: 19
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bit_size: 1
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enum: I2C_PB9_FMP
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- name: I2C1_FMP
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description: I2C1 Fast Mode Plus
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bit_offset: 20
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bit_size: 1
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enum: I2C1_FMP
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- name: I2C2_FMP
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description: I2C2 Fast Mode Plus
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bit_offset: 21
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bit_size: 1
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enum: I2C2_FMP
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- name: ENCODER_MODE
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description: Encoder mode
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bit_offset: 22
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bit_size: 2
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enum: ENCODER_MODE
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- name: I2C3_FMP
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description: I2C3 Fast Mode Plus
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bit_offset: 24
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bit_size: 1
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enum: I2C3_FMP
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- name: VBAT_MON
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description: VBAT monitoring enable
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bit_offset: 24
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bit_size: 1
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enum: VBAT_MON
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- name: FPU_IE0
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description: Invalid operation interrupt enable
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bit_offset: 26
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bit_size: 1
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enum: FPU_IE0
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- name: FPU_IE1
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description: Devide-by-zero interrupt enable
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bit_offset: 27
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bit_size: 1
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enum: FPU_IE1
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- name: FPU_IE2
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description: Underflow interrupt enable
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bit_offset: 28
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bit_size: 1
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enum: FPU_IE2
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- name: FPU_IE3
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description: Overflow interrupt enable
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bit_offset: 29
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bit_size: 1
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enum: FPU_IE3
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- name: FPU_IE4
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description: Input denormal interrupt enable
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bit_offset: 30
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bit_size: 1
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enum: FPU_IE4
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- name: FPU_IE5
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description: Inexact interrupt enable
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bit_offset: 31
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bit_size: 1
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enum: FPU_IE5
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fieldset/CFGR2:
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description: configuration register 2
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fields:
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- name: LOCKUP_LOCK
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description: Cortex-M0 LOCKUP bit enable bit
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bit_offset: 0
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bit_size: 1
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enum: LOCKUP_LOCK
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- name: SRAM_PARITY_LOCK
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description: SRAM parity lock bit
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bit_offset: 1
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bit_size: 1
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enum: SRAM_PARITY_LOCK
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- name: PVD_LOCK
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description: PVD lock enable bit
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bit_offset: 2
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bit_size: 1
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enum: PVD_LOCK
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- name: BYP_ADDR_PAR
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description: Bypass address bit 29 in parity calculation
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bit_offset: 4
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bit_size: 1
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enum: BYP_ADDR_PAR
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- name: SRAM_PEF
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description: SRAM parity flag
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bit_offset: 8
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bit_size: 1
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enum_read: SRAM_PEFR
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enum_write: SRAM_PEFW
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fieldset/CFGR3:
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description: configuration register 3
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fields:
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- name: SPI1_RX_DMA_RMP
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description: SPI1_RX DMA remapping bit
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bit_offset: 0
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bit_size: 2
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enum: SPI1_RX_DMA_RMP
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- name: SPI1_TX_DMA_RMP
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description: SPI1_TX DMA remapping bit
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bit_offset: 2
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bit_size: 2
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enum: SPI1_TX_DMA_RMP
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- name: I2C1_RX_DMA_RMP
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description: I2C1_RX DMA remapping bit
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bit_offset: 4
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bit_size: 2
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enum: I2C1_RX_DMA_RMP
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- name: I2C1_TX_DMA_RMP
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description: I2C1_TX DMA remapping bit
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bit_offset: 6
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bit_size: 2
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enum: I2C1_TX_DMA_RMP
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- name: ADC2_DMA_RMP
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description: ADC2 DMA remapping bit
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bit_offset: 8
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bit_size: 2
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enum: ADC2_DMA_RMP
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- name: DAC1_TRIG3_RMP
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description: DAC1_CH1 / DAC1_CH2 Trigger remap
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bit_offset: 16
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bit_size: 1
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enum: DAC1_TRIG3_RMP
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- name: DAC1_TRIG5_RMP
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description: DAC1_CH1 / DAC1_CH2 Trigger remap
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bit_offset: 17
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bit_size: 1
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enum: DAC1_TRIG5_RMP
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fieldset/CFGR4:
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description: configuration register 4
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fields:
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- name: ADC12_EXT2_RMP
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description: Controls the Input trigger of ADC12 regular channel EXT2
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bit_offset: 0
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bit_size: 1
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enum: ADC12_EXT2_RMP
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- name: ADC12_EXT3_RMP
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description: Controls the Input trigger of ADC12 regular channel EXT3
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bit_offset: 1
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bit_size: 1
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enum: ADC12_EXT3_RMP
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- name: ADC12_EXT5_RMP
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description: Controls the Input trigger of ADC12 regular channel EXT5
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bit_offset: 2
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bit_size: 1
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enum: ADC12_EXT5_RMP
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- name: ADC12_EXT13_RMP
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description: Controls the Input trigger of ADC12 regular channel EXT13
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bit_offset: 3
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bit_size: 1
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enum: ADC12_EXT13_RMP
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- name: ADC12_EXT15_RMP
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description: Controls the Input trigger of ADC12 regular channel EXT15
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bit_offset: 4
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bit_size: 1
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enum: ADC12_EXT15_RMP
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- name: ADC12_JEXT3_RMP
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description: Controls the Input trigger of ADC12 injected channel JEXT3
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bit_offset: 5
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bit_size: 1
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enum: ADC12_JEXT3_RMP
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- name: ADC12_JEXT6_RMP
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description: Controls the Input trigger of ADC12 injected channel JEXT6
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bit_offset: 6
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bit_size: 1
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enum: ADC12_JEXT6_RMP
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- name: ADC12_JEXT13_RMP
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description: Controls the Input trigger of ADC12 injected channel JEXT13
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bit_offset: 7
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bit_size: 1
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enum: ADC12_JEXT13_RMP
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- name: ADC34_EXT5_RMP
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description: Controls the Input trigger of ADC34 regular channel EXT5
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bit_offset: 8
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bit_size: 1
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enum: ADC34_EXT5_RMP
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- name: ADC34_EXT6_RMP
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description: Controls the Input trigger of ADC34 regular channel EXT6
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bit_offset: 9
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bit_size: 1
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enum: ADC34_EXT6_RMP
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- name: ADC34_EXT15_RMP
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description: Controls the Input trigger of ADC34 regular channel EXT15
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bit_offset: 10
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bit_size: 1
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enum: ADC34_EXT15_RMP
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- name: ADC34_JEXT5_RMP
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description: Controls the Input trigger of ADC34 injected channel JEXT5
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bit_offset: 11
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bit_size: 1
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enum: ADC34_JEXT5_RMP
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- name: ADC34_JEXT11_RMP
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description: Controls the Input trigger of ADC34 injected channel JEXT11
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bit_offset: 12
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bit_size: 1
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enum: ADC34_JEXT11_RMP
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- name: ADC34_JEXT14_RMP
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description: Controls the Input trigger of ADC34 injected channel JEXT14
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bit_offset: 13
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bit_size: 1
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enum: ADC34_JEXT14_RMP
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fieldset/EXTICR:
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description: external interrupt configuration register
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fields:
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- name: EXTI
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description: EXTI x configuration
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bit_offset: 0
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bit_size: 4
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array:
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len: 4
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stride: 4
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fieldset/RCR:
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description: CCM SRAM protection register
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fields:
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- name: PAGE0_WP
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description: CCM SRAM page write protection bit
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bit_offset: 0
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE1_WP
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description: CCM SRAM page write protection bit
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bit_offset: 1
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE2_WP
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description: CCM SRAM page write protection bit
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bit_offset: 2
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE3_WP
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description: CCM SRAM page write protection bit
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bit_offset: 3
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE4_WP
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description: CCM SRAM page write protection bit
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bit_offset: 4
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE5_WP
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description: CCM SRAM page write protection bit
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bit_offset: 5
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE6_WP
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description: CCM SRAM page write protection bit
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bit_offset: 6
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE7_WP
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description: CCM SRAM page write protection bit
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bit_offset: 7
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE8_WP
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description: CCM SRAM page write protection bit
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bit_offset: 8
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE9_WP
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description: CCM SRAM page write protection bit
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bit_offset: 9
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE10_WP
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description: CCM SRAM page write protection bit
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bit_offset: 10
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE11_WP
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description: CCM SRAM page write protection bit
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bit_offset: 11
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE12_WP
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description: CCM SRAM page write protection bit
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bit_offset: 12
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE13_WP
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description: CCM SRAM page write protection bit
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bit_offset: 13
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE14_WP
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description: CCM SRAM page write protection bit
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bit_offset: 14
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bit_size: 1
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enum: PAGE0_WP
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- name: PAGE15_WP
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description: CCM SRAM page write protection bit
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bit_offset: 15
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bit_size: 1
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enum: PAGE0_WP
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enum/ADC12_EXT13_RMP:
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bit_size: 1
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variants:
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- name: Tim6
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description: Trigger source is TIM6_TRGO
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_CC2
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value: 1
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enum/ADC12_EXT15_RMP:
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bit_size: 1
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variants:
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- name: Tim3
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description: Trigger source is TIM3_CC4
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_CC3
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value: 1
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enum/ADC12_EXT2_RMP:
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bit_size: 1
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variants:
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- name: Tim1
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description: Trigger source is TIM3_CC3
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value: 0
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- name: Tim20
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description: rigger source is TIM20_TRGO
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value: 1
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enum/ADC12_EXT3_RMP:
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bit_size: 1
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variants:
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- name: Tim2
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description: Trigger source is TIM2_CC2
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value: 0
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- name: Tim20
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description: rigger source is TIM20_TRGO2
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value: 1
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enum/ADC12_EXT5_RMP:
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bit_size: 1
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variants:
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- name: Tim4
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description: Trigger source is TIM4_CC4
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_CC1
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value: 1
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enum/ADC12_JEXT13_RMP:
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bit_size: 1
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variants:
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- name: Tim3
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description: Trigger source is TIM3_CC1
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_CC4
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value: 1
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enum/ADC12_JEXT3_RMP:
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bit_size: 1
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variants:
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- name: Tim2
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description: Trigger source is TIM2_CC1
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_TRGO
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value: 1
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enum/ADC12_JEXT6_RMP:
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bit_size: 1
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variants:
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- name: Exti15
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description: Trigger source is EXTI line 15
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_TRGO2
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value: 1
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enum/ADC2_DMA_RMP:
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bit_size: 1
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variants:
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- name: MapDma2
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description: ADC2 mapped on DMA2
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value: 0
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- name: MapDma1Ch2
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description: ADC2 mapped on DMA1 channel 2
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value: 2
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- name: MapDma1Ch4
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description: ADC2 mapped on DMA1 channel 4
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value: 3
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enum/ADC34_EXT15_RMP:
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bit_size: 1
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variants:
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- name: Tim2
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description: Trigger source is TIM2_CC1
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_CC1
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value: 1
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enum/ADC34_EXT5_RMP:
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bit_size: 1
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variants:
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- name: Exti2
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description: Trigger source is EXTI line 2 when reset at 0
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_TRGO
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value: 1
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enum/ADC34_EXT6_RMP:
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bit_size: 1
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variants:
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- name: Tim4
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description: Trigger source is TIM4_CC1
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_TRGO2
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value: 1
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enum/ADC34_JEXT11_RMP:
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bit_size: 1
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variants:
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- name: Tim1
|
|
description: Trigger source is TIM1_CC3
|
|
value: 0
|
|
- name: Tim20
|
|
description: Trigger source is TIM20_TRGO2
|
|
value: 1
|
|
enum/ADC34_JEXT14_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Tim7
|
|
description: Trigger source is TIM7_TRGO
|
|
value: 0
|
|
- name: Tim20
|
|
description: Trigger source is TIM20_CC2
|
|
value: 1
|
|
enum/ADC34_JEXT5_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Tim4
|
|
description: Trigger source is TIM4_CC3
|
|
value: 0
|
|
- name: Tim20
|
|
description: Trigger source is TIM20_TRGO
|
|
value: 1
|
|
enum/BYP_ADDR_PAR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoBypass
|
|
description: The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated
|
|
value: 0
|
|
- name: Bypass
|
|
description: The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated
|
|
value: 1
|
|
enum/CFGR1_ADC2_DMA_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: ADC24 DMA requests mapped on DMA2 channels 1 and 2
|
|
value: 0
|
|
- name: Remapped
|
|
description: ADC24 DMA requests mapped on DMA2 channels 3 and 4
|
|
value: 1
|
|
enum/CFGR3_ADC2_DMA_RMP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MapDma2
|
|
description: ADC2 mapped on DMA2
|
|
value: 0
|
|
- name: MapDma1Ch2
|
|
description: ADC2 mapped on DMA1 channel 2
|
|
value: 2
|
|
- name: MapDma1Ch4
|
|
description: ADC2 mapped on DMA1 channel 4
|
|
value: 3
|
|
enum/DAC1_TRIG3_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Tim15
|
|
description: DAC trigger is TIM15_TRGO
|
|
value: 0
|
|
- name: HrTim1
|
|
description: DAC trigger is HRTIM1_DAC1_TRIG1
|
|
value: 1
|
|
enum/DAC1_TRIG5_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: Not remapped
|
|
value: 0
|
|
- name: Remapped
|
|
description: DAC trigger is HRTIM1_DAC1_TRIG2
|
|
value: 1
|
|
enum/DAC1_TRIG_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices
|
|
value: 0
|
|
- name: Remapped
|
|
description: DAC trigger is TIM3_TRGO
|
|
value: 1
|
|
enum/DAC2_CH1_DMA_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: Not remapped
|
|
value: 0
|
|
- name: Remapped
|
|
description: DAC2_CH1 DMA requests mapped on DMA1 channel 5
|
|
value: 1
|
|
enum/DAC_TRIG_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: Not remapped
|
|
value: 0
|
|
- name: Remapped
|
|
description: DAC trigger is TIM3_TRGO
|
|
value: 1
|
|
enum/ENCODER_MODE:
|
|
bit_size: 2
|
|
variants:
|
|
- name: NoRedirection
|
|
description: No redirection
|
|
value: 0
|
|
- name: MapTim2Tim15
|
|
description: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
|
|
value: 1
|
|
- name: MapTim3Tim15
|
|
description: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
|
|
value: 2
|
|
enum/EXTI0:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA0
|
|
description: Select PA0 as the source input for the EXTI0 external interrupt
|
|
value: 0
|
|
- name: PB0
|
|
description: Select PB0 as the source input for the EXTI0 external interrupt
|
|
value: 1
|
|
- name: PC0
|
|
description: Select PC0 as the source input for the EXTI0 external interrupt
|
|
value: 2
|
|
- name: PD0
|
|
description: Select PD0 as the source input for the EXTI0 external interrupt
|
|
value: 3
|
|
- name: PE0
|
|
description: Select PE0 as the source input for the EXTI0 external interrupt
|
|
value: 4
|
|
- name: PF0
|
|
description: Select PF0 as the source input for the EXTI0 external interrupt
|
|
value: 5
|
|
enum/EXTI1:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA1
|
|
description: Select PA1 as the source input for the EXTI1 external interrupt
|
|
value: 0
|
|
- name: PB1
|
|
description: Select PB1 as the source input for the EXTI1 external interrupt
|
|
value: 1
|
|
- name: PC1
|
|
description: Select PC1 as the source input for the EXTI1 external interrupt
|
|
value: 2
|
|
- name: PD1
|
|
description: Select PD1 as the source input for the EXTI1 external interrupt
|
|
value: 3
|
|
- name: PE1
|
|
description: Select PE1 as the source input for the EXTI1 external interrupt
|
|
value: 4
|
|
- name: PF1
|
|
description: Select PF1 as the source input for the EXTI1 external interrupt
|
|
value: 5
|
|
enum/EXTI10:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA10
|
|
description: Select PA10 as the source input for the EXTI10 external interrupt
|
|
value: 0
|
|
- name: PB10
|
|
description: Select PB10 as the source input for the EXTI10 external interrupt
|
|
value: 1
|
|
- name: PC10
|
|
description: Select PC10 as the source input for the EXTI10 external interrupt
|
|
value: 2
|
|
- name: PD10
|
|
description: Select PD10 as the source input for the EXTI10 external interrupt
|
|
value: 3
|
|
- name: PE10
|
|
description: Select PE10 as the source input for the EXTI10 external interrupt
|
|
value: 4
|
|
- name: PF10
|
|
description: Select PF10 as the source input for the EXTI10 external interrupt
|
|
value: 5
|
|
enum/EXTI11:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA11
|
|
description: Select PA11 as the source input for the EXTI11 external interrupt
|
|
value: 0
|
|
- name: PB11
|
|
description: Select PB11 as the source input for the EXTI11 external interrupt
|
|
value: 1
|
|
- name: PC11
|
|
description: Select PC11 as the source input for the EXTI11 external interrupt
|
|
value: 2
|
|
- name: PD11
|
|
description: Select PD11 as the source input for the EXTI11 external interrupt
|
|
value: 3
|
|
- name: PE11
|
|
description: Select PE11 as the source input for the EXTI11 external interrupt
|
|
value: 4
|
|
enum/EXTI12:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA12
|
|
description: Select PA12 as the source input for the EXTI12 external interrupt
|
|
value: 0
|
|
- name: PB12
|
|
description: Select PB12 as the source input for the EXTI12 external interrupt
|
|
value: 1
|
|
- name: PC12
|
|
description: Select PC12 as the source input for the EXTI12 external interrupt
|
|
value: 2
|
|
- name: PD12
|
|
description: Select PD12 as the source input for the EXTI12 external interrupt
|
|
value: 3
|
|
- name: PE12
|
|
description: Select PE12 as the source input for the EXTI12 external interrupt
|
|
value: 4
|
|
enum/EXTI13:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA13
|
|
description: Select PA13 as the source input for the EXTI13 external interrupt
|
|
value: 0
|
|
- name: PB13
|
|
description: Select PB13 as the source input for the EXTI13 external interrupt
|
|
value: 1
|
|
- name: PC13
|
|
description: Select PC13 as the source input for the EXTI13 external interrupt
|
|
value: 2
|
|
- name: PD13
|
|
description: Select PD13 as the source input for the EXTI13 external interrupt
|
|
value: 3
|
|
- name: PE13
|
|
description: Select PE13 as the source input for the EXTI13 external interrupt
|
|
value: 4
|
|
enum/EXTI14:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA14
|
|
description: Select PA14 as the source input for the EXTI14 external interrupt
|
|
value: 0
|
|
- name: PB14
|
|
description: Select PB14 as the source input for the EXTI14 external interrupt
|
|
value: 1
|
|
- name: PC14
|
|
description: Select PC14 as the source input for the EXTI14 external interrupt
|
|
value: 2
|
|
- name: PD14
|
|
description: Select PD14 as the source input for the EXTI14 external interrupt
|
|
value: 3
|
|
- name: PE14
|
|
description: Select PE14 as the source input for the EXTI14 external interrupt
|
|
value: 4
|
|
enum/EXTI15:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA15
|
|
description: Select PA15 as the source input for the EXTI15 external interrupt
|
|
value: 0
|
|
- name: PB15
|
|
description: Select PB15 as the source input for the EXTI15 external interrupt
|
|
value: 1
|
|
- name: PC15
|
|
description: Select PC15 as the source input for the EXTI15 external interrupt
|
|
value: 2
|
|
- name: PD15
|
|
description: Select PD15 as the source input for the EXTI15 external interrupt
|
|
value: 3
|
|
- name: PE15
|
|
description: Select PE15 as the source input for the EXTI15 external interrupt
|
|
value: 4
|
|
enum/EXTI2:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA2
|
|
description: Select PA2 as the source input for the EXTI2 external interrupt
|
|
value: 0
|
|
- name: PB2
|
|
description: Select PB2 as the source input for the EXTI2 external interrupt
|
|
value: 1
|
|
- name: PC2
|
|
description: Select PC2 as the source input for the EXTI2 external interrupt
|
|
value: 2
|
|
- name: PD2
|
|
description: Select PD2 as the source input for the EXTI2 external interrupt
|
|
value: 3
|
|
- name: PE2
|
|
description: Select PE2 as the source input for the EXTI2 external interrupt
|
|
value: 4
|
|
- name: PF2
|
|
description: Select PF2 as the source input for the EXTI2 external interrupt
|
|
value: 5
|
|
enum/EXTI3:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA3
|
|
description: Select PA3 as the source input for the EXTI3 external interrupt
|
|
value: 0
|
|
- name: PB3
|
|
description: Select PB3 as the source input for the EXTI3 external interrupt
|
|
value: 1
|
|
- name: PC3
|
|
description: Select PC3 as the source input for the EXTI3 external interrupt
|
|
value: 2
|
|
- name: PD3
|
|
description: Select PD3 as the source input for the EXTI3 external interrupt
|
|
value: 3
|
|
- name: PE3
|
|
description: Select PE3 as the source input for the EXTI3 external interrupt
|
|
value: 4
|
|
enum/EXTI4:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA4
|
|
description: Select PA4 as the source input for the EXTI4 external interrupt
|
|
value: 0
|
|
- name: PB4
|
|
description: Select PB4 as the source input for the EXTI4 external interrupt
|
|
value: 1
|
|
- name: PC4
|
|
description: Select PC4 as the source input for the EXTI4 external interrupt
|
|
value: 2
|
|
- name: PD4
|
|
description: Select PD4 as the source input for the EXTI4 external interrupt
|
|
value: 3
|
|
- name: PE4
|
|
description: Select PE4 as the source input for the EXTI4 external interrupt
|
|
value: 4
|
|
- name: PF4
|
|
description: Select PF4 as the source input for the EXTI4 external interrupt
|
|
value: 5
|
|
enum/EXTI5:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA5
|
|
description: Select PA5 as the source input for the EXTI5 external interrupt
|
|
value: 0
|
|
- name: PB5
|
|
description: Select PB5 as the source input for the EXTI5 external interrupt
|
|
value: 1
|
|
- name: PC5
|
|
description: Select PC5 as the source input for the EXTI5 external interrupt
|
|
value: 2
|
|
- name: PD5
|
|
description: Select PD5 as the source input for the EXTI5 external interrupt
|
|
value: 3
|
|
- name: PE5
|
|
description: Select PE5 as the source input for the EXTI5 external interrupt
|
|
value: 4
|
|
- name: PF5
|
|
description: Select PF5 as the source input for the EXTI5 external interrupt
|
|
value: 5
|
|
enum/EXTI6:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA6
|
|
description: Select PA6 as the source input for the EXTI6 external interrupt
|
|
value: 0
|
|
- name: PB6
|
|
description: Select PB6 as the source input for the EXTI6 external interrupt
|
|
value: 1
|
|
- name: PC6
|
|
description: Select PC6 as the source input for the EXTI6 external interrupt
|
|
value: 2
|
|
- name: PD6
|
|
description: Select PD6 as the source input for the EXTI6 external interrupt
|
|
value: 3
|
|
- name: PE6
|
|
description: Select PE6 as the source input for the EXTI6 external interrupt
|
|
value: 4
|
|
- name: PF6
|
|
description: Select PF6 as the source input for the EXTI6 external interrupt
|
|
value: 5
|
|
enum/EXTI7:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA7
|
|
description: Select PA7 as the source input for the EXTI7 external interrupt
|
|
value: 0
|
|
- name: PB7
|
|
description: Select PB7 as the source input for the EXTI7 external interrupt
|
|
value: 1
|
|
- name: PC7
|
|
description: Select PC7 as the source input for the EXTI7 external interrupt
|
|
value: 2
|
|
- name: PD7
|
|
description: Select PD7 as the source input for the EXTI7 external interrupt
|
|
value: 3
|
|
- name: PE7
|
|
description: Select PE7 as the source input for the EXTI7 external interrupt
|
|
value: 4
|
|
enum/EXTI8:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA8
|
|
description: Select PA8 as the source input for the EXTI8 external interrupt
|
|
value: 0
|
|
- name: PB8
|
|
description: Select PB8 as the source input for the EXTI8 external interrupt
|
|
value: 1
|
|
- name: PC8
|
|
description: Select PC8 as the source input for the EXTI8 external interrupt
|
|
value: 2
|
|
- name: PD8
|
|
description: Select PD8 as the source input for the EXTI8 external interrupt
|
|
value: 3
|
|
- name: PE8
|
|
description: Select PE8 as the source input for the EXTI8 external interrupt
|
|
value: 4
|
|
enum/EXTI9:
|
|
bit_size: 4
|
|
variants:
|
|
- name: PA9
|
|
description: Select PA9 as the source input for the EXTI9 external interrupt
|
|
value: 0
|
|
- name: PB9
|
|
description: Select PB9 as the source input for the EXTI9 external interrupt
|
|
value: 1
|
|
- name: PC9
|
|
description: Select PC9 as the source input for the EXTI9 external interrupt
|
|
value: 2
|
|
- name: PD9
|
|
description: Select PD9 as the source input for the EXTI9 external interrupt
|
|
value: 3
|
|
- name: PE9
|
|
description: Select PE9 as the source input for the EXTI9 external interrupt
|
|
value: 4
|
|
- name: PF9
|
|
description: Select PF9 as the source input for the EXTI9 external interrupt
|
|
value: 5
|
|
enum/FPU_IE0:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Invalid operation interrupt disable
|
|
value: 0
|
|
- name: Enabled
|
|
description: Invalid operation interrupt enable
|
|
value: 1
|
|
enum/FPU_IE1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Devide-by-zero interrupt disable
|
|
value: 0
|
|
- name: Enabled
|
|
description: Devide-by-zero interrupt enable
|
|
value: 1
|
|
enum/FPU_IE2:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Underflow interrupt disable
|
|
value: 0
|
|
- name: Enabled
|
|
description: Underflow interrupt enable
|
|
value: 1
|
|
enum/FPU_IE3:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Overflow interrupt disable
|
|
value: 0
|
|
- name: Enabled
|
|
description: Overflow interrupt enable
|
|
value: 1
|
|
enum/FPU_IE4:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Input denormal interrupt disable
|
|
value: 0
|
|
- name: Enabled
|
|
description: Input denormal interrupt enable
|
|
value: 1
|
|
enum/FPU_IE5:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Inexact interrupt disable
|
|
value: 0
|
|
- name: Enabled
|
|
description: Inexact interrupt enable
|
|
value: 1
|
|
enum/I2C1_FMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Standard
|
|
description: FM+ mode is controlled by I2C_Pxx_FMP bits only
|
|
value: 0
|
|
- name: FMP
|
|
description: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits
|
|
value: 1
|
|
enum/I2C1_RX_DMA_RMP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MapDma1Ch7
|
|
description: I2C1_RX mapped on DMA1 CH7
|
|
value: 0
|
|
- name: MapDma1Ch3
|
|
description: I2C1_RX mapped on DMA1 CH3
|
|
value: 1
|
|
- name: MapDma1Ch5
|
|
description: I2C1_RX mapped on DMA1 CH5
|
|
value: 2
|
|
enum/I2C1_TX_DMA_RMP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MapDma1Ch6
|
|
description: I2C1_TX mapped on DMA1 CH6
|
|
value: 0
|
|
- name: MapDma1Ch2
|
|
description: I2C1_TX mapped on DMA1 CH2
|
|
value: 1
|
|
- name: MapDma1Ch4
|
|
description: I2C1_TX mapped on DMA1 CH4
|
|
value: 2
|
|
enum/I2C2_FMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Standard
|
|
description: FM+ mode is controlled by I2C_Pxx_FMP bits only
|
|
value: 0
|
|
- name: FMP
|
|
description: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits
|
|
value: 1
|
|
enum/I2C3_FMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Standard
|
|
description: FM+ mode is controlled by I2C_Pxx_FMP bits only
|
|
value: 0
|
|
- name: FMP
|
|
description: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits
|
|
value: 1
|
|
enum/I2C_PB6_FMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Standard
|
|
description: PB6 pin operate in standard mode
|
|
value: 0
|
|
- name: FMP
|
|
description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed
|
|
value: 1
|
|
enum/I2C_PB7_FMP:
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|
bit_size: 1
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|
variants:
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|
- name: Standard
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|
description: PB7 pin operate in standard mode
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|
value: 0
|
|
- name: FMP
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|
description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed
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|
value: 1
|
|
enum/I2C_PB8_FMP:
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|
bit_size: 1
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|
variants:
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|
- name: Standard
|
|
description: PB8 pin operate in standard mode
|
|
value: 0
|
|
- name: FMP
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|
description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed
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|
value: 1
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|
enum/I2C_PB9_FMP:
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|
bit_size: 1
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|
variants:
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|
- name: Standard
|
|
description: PB9 pin operate in standard mode
|
|
value: 0
|
|
- name: FMP
|
|
description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed
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|
value: 1
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|
enum/LOCKUP_LOCK:
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|
bit_size: 1
|
|
variants:
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|
- name: Disconnected
|
|
description: Cortex-M4 LOCKUP output disconnected from TIM1/15/16/17 Break inputs and HRTIM1 SYSFLT.
|
|
value: 0
|
|
- name: Connected
|
|
description: Cortex-M4 LOCKUP output connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs
|
|
value: 1
|
|
enum/MEM_MODE:
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|
bit_size: 2
|
|
variants:
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|
- name: MainFlash
|
|
description: Main Flash memory mapped at 0x0000_0000
|
|
value: 0
|
|
- name: SystemFlash
|
|
description: System Flash memory mapped at 0x0000_0000
|
|
value: 1
|
|
- name: MainFlash2
|
|
description: Main Flash memory mapped at 0x0000_0000
|
|
value: 2
|
|
- name: SRAM
|
|
description: Embedded SRAM mapped at 0x0000_0000
|
|
value: 3
|
|
enum/PAGE0_WP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Write protection of pagex is disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Write protection of pagex is enabled
|
|
value: 1
|
|
enum/PVD_LOCK:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disconnected
|
|
description: PVD interrupt disconnected from TIM15/16/17 Break input
|
|
value: 0
|
|
- name: Connected
|
|
description: PVD interrupt connected to TIM15/16/17 Break input
|
|
value: 1
|
|
enum/SPI1_RX_DMA_RMP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MapDma1Ch3
|
|
description: SPI1_RX mapped on DMA1 CH2
|
|
value: 0
|
|
- name: MapDma1Ch5
|
|
description: SPI1_RX mapped on DMA1 CH4
|
|
value: 1
|
|
- name: MapDma1Ch7
|
|
description: SPI1_RX mapped on DMA1 CH6
|
|
value: 2
|
|
enum/SPI1_TX_DMA_RMP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MapDma1Ch3
|
|
description: SPI1_TX mapped on DMA1 CH3
|
|
value: 0
|
|
- name: MapDma1Ch5
|
|
description: SPI1_TX mapped on DMA1 CH5
|
|
value: 1
|
|
- name: MapDma1Ch7
|
|
description: SPI1_TX mapped on DMA1 CH7
|
|
value: 2
|
|
enum/SRAM_PARITY_LOCK:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disconnected
|
|
description: SRAM parity error signal disconnected from TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs
|
|
value: 0
|
|
- name: Connected
|
|
description: SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs
|
|
value: 1
|
|
enum/SRAM_PEFR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoParityError
|
|
description: No SRAM parity error detected
|
|
value: 0
|
|
- name: ParityErrorDetected
|
|
description: SRAM parity error detected
|
|
value: 1
|
|
enum/SRAM_PEFW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clear SRAM parity error flag
|
|
value: 1
|
|
enum/TIM16_DMA_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3
|
|
value: 0
|
|
- name: Remapped
|
|
description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4
|
|
value: 1
|
|
enum/TIM17_DMA_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
|
|
value: 0
|
|
- name: Remapped
|
|
description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2
|
|
value: 1
|
|
enum/TIM18_DAC2_OUT1_DMA_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5
|
|
value: 0
|
|
- name: Remapped
|
|
description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5
|
|
value: 1
|
|
enum/TIM1_ITR3_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: Not remapped
|
|
value: 0
|
|
- name: Remapped
|
|
description: TIM1_ITR3 = TIM17_OC
|
|
value: 1
|
|
enum/TIM6_DAC1_CH1_DMA_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3
|
|
value: 0
|
|
- name: Remapped
|
|
description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3
|
|
value: 1
|
|
enum/TIM6_DAC1_DMA_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3
|
|
value: 0
|
|
- name: Remapped
|
|
description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3
|
|
value: 1
|
|
enum/TIM6_DAC1_OUT1_DMA_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3
|
|
value: 0
|
|
- name: Remapped
|
|
description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3
|
|
value: 1
|
|
enum/TIM7_DAC1_CH2_DMA_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: Not remapped
|
|
value: 0
|
|
- name: Remapped
|
|
description: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4
|
|
value: 1
|
|
enum/TIM7_DAC1_OUT2_DMA_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4
|
|
value: 0
|
|
- name: Remapped
|
|
description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4
|
|
value: 1
|
|
enum/USB_IT_RMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotRemapped
|
|
description: "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively"
|
|
value: 0
|
|
- name: Remapped
|
|
description: "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively"
|
|
value: 1
|
|
enum/VBAT_MON:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disable
|
|
description: Disable the power switch to not deliver VBAT voltage on ADC channel 18 input
|
|
value: 0
|
|
- name: Enable
|
|
description: Enable the power switch to deliver VBAT voltage on ADC channel 18 input
|
|
value: 1
|