diff --git a/data/registers/afio_f1.yaml b/data/registers/afio_f1.yaml index e804f23..c822d98 100644 --- a/data/registers/afio_f1.yaml +++ b/data/registers/afio_f1.yaml @@ -85,10 +85,6 @@ fieldset/MAPR: description: TIM4 remapping bit_offset: 12 bit_size: 1 - - name: CAN_REMAP - description: CAN1 remapping - bit_offset: 13 - bit_size: 2 - name: CAN1_REMAP description: CAN1 remapping bit_offset: 13 diff --git a/data/registers/flash_f3.yaml b/data/registers/flash_f3.yaml index 0edc574..b8cdd2b 100644 --- a/data/registers/flash_f3.yaml +++ b/data/registers/flash_f3.yaml @@ -1,492 +1,493 @@ +--- block/FLASH: description: Flash items: - - byte_offset: 0 - description: Flash access control register - fieldset: ACR - name: ACR - - access: Write - byte_offset: 4 - description: Flash key register - fieldset: KEYR - name: KEYR - - access: Write - byte_offset: 8 - description: Flash option key register - fieldset: OPTKEYR - name: OPTKEYR - - byte_offset: 12 - description: Flash status register - fieldset: SR - name: SR - - byte_offset: 16 - description: Flash control register - fieldset: CR - name: CR - - access: Write - byte_offset: 20 - description: Flash address register - fieldset: AR - name: AR - - access: Read - byte_offset: 28 - description: Option byte register - fieldset: OBR - name: OBR - - access: Read - byte_offset: 32 - description: Write protection register - fieldset: WRPR - name: WRPR -enum/BSYR: - bit_size: 1 - variants: - - description: No write/erase operation is in progress - name: Inactive - value: 0 - - description: No write/erase operation is in progress - name: Active - value: 1 -enum/EOPIE: - bit_size: 1 - variants: - - description: End of operation interrupt disabled - name: Disabled - value: 0 - - description: End of operation interrupt enabled - name: Enabled - value: 1 -enum/EOPR: - bit_size: 1 - variants: - - description: No EOP event occurred - name: NoEvent - value: 0 - - description: An EOP event occurred - name: Event - value: 1 -enum/EOPW: - bit_size: 1 - variants: - - description: Reset EOP event - name: Reset - value: 1 -enum/ERRIE: - bit_size: 1 - variants: - - description: Error interrupt generation disabled - name: Disabled - value: 0 - - description: Error interrupt generation enabled - name: Enabled - value: 1 -enum/HLFCYA: - bit_size: 1 - variants: - - description: Half cycle is disabled - name: Disabled - value: 0 - - description: Half cycle is enabled - name: Enabled - value: 1 -enum/LATENCY: - bit_size: 3 - variants: - - description: 0 wait states, if 0 < HCLK <= 24 MHz - name: WS0 - value: 0 - - description: 1 wait state, if 24 < HCLK <= 48 MHz - name: WS1 - value: 1 - - description: 2 wait states, if 48 < HCLK <= 72 MHz - name: WS2 - value: 2 -enum/LOCKR: - bit_size: 1 - variants: - - description: FLASH_CR register is unlocked - name: Unlocked - value: 0 - - description: FLASH_CR register is locked - name: Locked - value: 1 -enum/LOCKW: - bit_size: 1 - variants: - - description: Lock the FLASH_CR register - name: Lock - value: 1 -enum/MER: - bit_size: 1 - variants: - - description: Erase activated for all user sectors - name: MassErase - value: 1 -enum/OBL_LAUNCH: - bit_size: 1 - variants: - - description: Force option byte loading inactive - name: Inactive - value: 0 - - description: Force option byte loading active - name: Active - value: 1 -enum/OPTER: - bit_size: 1 - variants: - - description: Erase option byte activated - name: OptionByteErase - value: 1 -enum/OPTERR: - bit_size: 1 - variants: - - description: The loaded option byte and its complement do not match - name: OptionByteError - value: 1 -enum/OPTPG: - bit_size: 1 - variants: - - description: Program option byte activated - name: OptionByteProgramming - value: 1 -enum/OPTWRE: - bit_size: 1 - variants: - - description: Option byte write enabled - name: Disabled - value: 0 - - description: Option byte write disabled - name: Enabled - value: 1 -enum/PER: - bit_size: 1 - variants: - - description: Erase activated for selected page - name: PageErase - value: 1 -enum/PG: - bit_size: 1 - variants: - - description: Flash programming activated - name: Program - value: 1 -enum/PGERRR: - bit_size: 1 - variants: - - description: No programming error occurred - name: NoError - value: 0 - - description: A programming error occurred - name: Error - value: 1 -enum/PGERRW: - bit_size: 1 - variants: - - description: Reset programming error - name: Reset - value: 1 -enum/PRFTBE: - bit_size: 1 - variants: - - description: Prefetch is disabled - name: Disabled - value: 0 - - description: Prefetch is enabled - name: Enabled - value: 1 -enum/PRFTBS: - bit_size: 1 - variants: - - description: Prefetch buffer is disabled - name: Disabled - value: 0 - - description: Prefetch buffer is enabled - name: Enabled - value: 1 -enum/RDPRT: - bit_size: 2 - variants: - - description: Level 0 - name: Level0 - value: 0 - - description: Level 1 - name: Level1 - value: 1 - - description: Level 2 - name: Level2 - value: 3 -enum/SDADC_VDD_MONITOR: - bit_size: 1 - variants: - - description: VDDSD12 monitoring disabled - name: Disabled - value: 0 - - description: VDDSD12 monitoring enabled - name: Enabled - value: 1 -enum/SRAM_PARITY_CHECK: - bit_size: 1 - variants: - - description: RAM parity check disabled - name: Disabled - value: 0 - - description: RAM parity check enabled - name: Enabled - value: 1 -enum/STRT: - bit_size: 1 - variants: - - description: Trigger an erase operation - name: Start - value: 1 -enum/VDDA_MONITOR: - bit_size: 1 - variants: - - description: VDDA power supply supervisor disabled - name: Disabled - value: 0 - - description: VDDA power supply supervisor enabled - name: Enabled - value: 1 -enum/WDG_SW: - bit_size: 1 - variants: - - description: Hardware watchdog - name: Hardware - value: 0 - - description: Software watchdog - name: Software - value: 1 -enum/WRPRTERRR: - bit_size: 1 - variants: - - description: No write protection error occurred - name: NoError - value: 0 - - description: A write protection error occurred - name: Error - value: 1 -enum/WRPRTERRW: - bit_size: 1 - variants: - - description: Reset write protection error - name: Reset - value: 1 -enum/nBOOT: - bit_size: 1 - variants: - - description: Together with BOOT0, select the device boot mode - name: Disabled - value: 0 - - description: Together with BOOT0, select the device boot mode - name: Enabled - value: 1 -enum/nRST_STDBY: - bit_size: 1 - variants: - - description: Reset generated when entering Standby mode - name: Reset - value: 0 - - description: No reset generated - name: NoReset - value: 1 -enum/nRST_STOP: - bit_size: 1 - variants: - - description: Reset generated when entering Stop mode - name: Reset - value: 0 - - description: No reset generated - name: NoReset - value: 1 + - name: ACR + description: Flash access control register + byte_offset: 0 + fieldset: ACR + - name: KEYR + description: Flash key register + byte_offset: 4 + access: Write + fieldset: KEYR + - name: OPTKEYR + description: Flash option key register + byte_offset: 8 + access: Write + fieldset: OPTKEYR + - name: SR + description: Flash status register + byte_offset: 12 + fieldset: SR + - name: CR + description: Flash control register + byte_offset: 16 + fieldset: CR + - name: AR + description: Flash address register + byte_offset: 20 + access: Write + fieldset: AR + - name: OBR + description: Option byte register + byte_offset: 28 + access: Read + fieldset: OBR + - name: WRPR + description: Write protection register + byte_offset: 32 + access: Read + fieldset: WRPR fieldset/ACR: description: Flash access control register fields: - - bit_offset: 0 - bit_size: 3 - description: LATENCY - enum: LATENCY - name: LATENCY - - bit_offset: 3 - bit_size: 1 - description: Flash half cycle access enable - enum: HLFCYA - name: HLFCYA - - bit_offset: 4 - bit_size: 1 - description: PRFTBE - enum: PRFTBE - name: PRFTBE - - bit_offset: 5 - bit_size: 1 - description: PRFTBS - enum: PRFTBS - name: PRFTBS + - name: LATENCY + description: LATENCY + bit_offset: 0 + bit_size: 3 + enum: LATENCY + - name: HLFCYA + description: Flash half cycle access enable + bit_offset: 3 + bit_size: 1 + enum: HLFCYA + - name: PRFTBE + description: PRFTBE + bit_offset: 4 + bit_size: 1 + enum: PRFTBE + - name: PRFTBS + description: PRFTBS + bit_offset: 5 + bit_size: 1 + enum: PRFTBS fieldset/AR: description: Flash address register fields: - - bit_offset: 0 - bit_size: 32 - description: Flash address - name: FAR + - name: FAR + description: Flash address + bit_offset: 0 + bit_size: 32 fieldset/CR: description: Flash control register fields: - - bit_offset: 0 - bit_size: 1 - description: Programming - enum: PG - name: PG - - bit_offset: 1 - bit_size: 1 - description: Page erase - enum: PER - name: PER - - bit_offset: 2 - bit_size: 1 - description: Mass erase - enum: MER - name: MER - - bit_offset: 4 - bit_size: 1 - description: Option byte programming - enum: OPTPG - name: OPTPG - - bit_offset: 5 - bit_size: 1 - description: Option byte erase - enum: OPTER - name: OPTER - - bit_offset: 6 - bit_size: 1 - description: Start - enum: STRT - name: STRT - - bit_offset: 7 - bit_size: 1 - description: Lock - enum_read: LOCKR - enum_write: LOCKW - name: LOCK - - bit_offset: 9 - bit_size: 1 - description: Option bytes write enable - enum: OPTWRE - name: OPTWRE - - bit_offset: 10 - bit_size: 1 - description: Error interrupt enable - enum: ERRIE - name: ERRIE - - bit_offset: 12 - bit_size: 1 - description: End of operation interrupt enable - enum: EOPIE - name: EOPIE - - bit_offset: 13 - bit_size: 1 - description: Force option byte loading - enum: OBL_LAUNCH - name: OBL_LAUNCH + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + enum: PG + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + enum: PER + - name: MER + description: Mass erase + bit_offset: 2 + bit_size: 1 + enum: MER + - name: OPTPG + description: Option byte programming + bit_offset: 4 + bit_size: 1 + enum: OPTPG + - name: OPTER + description: Option byte erase + bit_offset: 5 + bit_size: 1 + enum: OPTER + - name: STRT + description: Start + bit_offset: 6 + bit_size: 1 + enum: STRT + - name: LOCK + description: Lock + bit_offset: 7 + bit_size: 1 + enum_read: LOCKR + enum_write: LOCKW + - name: OPTWRE + description: Option bytes write enable + bit_offset: 9 + bit_size: 1 + enum: OPTWRE + - name: ERRIE + description: Error interrupt enable + bit_offset: 10 + bit_size: 1 + enum: ERRIE + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 12 + bit_size: 1 + enum: EOPIE + - name: OBL_LAUNCH + description: Force option byte loading + bit_offset: 13 + bit_size: 1 + enum: OBL_LAUNCH fieldset/KEYR: description: Flash key register fields: - - bit_offset: 0 - bit_size: 32 - description: Flash Key - name: FKEYR + - name: FKEYR + description: Flash Key + bit_offset: 0 + bit_size: 32 fieldset/OBR: description: Option byte register fields: - - bit_offset: 0 - bit_size: 1 - description: Option byte error - enum: OPTERR - name: OPTERR - - bit_offset: 1 - bit_size: 2 - description: Read protection Level status - enum: RDPRT - name: RDPRT - - bit_offset: 8 - bit_size: 1 - description: WDG_SW - enum: WDG_SW - name: WDG_SW - - bit_offset: 9 - bit_size: 1 - description: nRST_STOP - enum: nRST_STOP - name: nRST_STOP - - bit_offset: 10 - bit_size: 1 - description: nRST_STDBY - enum: nRST_STDBY - name: nRST_STDBY - - bit_offset: 12 - bit_size: 1 - description: BOOT1 - enum: nBOOT - name: nBOOT1 - - bit_offset: 13 - bit_size: 1 - description: VDDA_MONITOR - enum: VDDA_MONITOR - name: VDDA_MONITOR - - bit_offset: 14 - bit_size: 1 - description: SRAM_PARITY_CHECK - name: SRAM_PARITY_CHECK - - bit_offset: 15 - bit_size: 1 - description: SDADC12_VDD_MONITOR - enum: SDADC_VDD_MONITOR - name: SDADC12_VDD_MONITOR - - bit_offset: 16 - bit_size: 8 - description: Data0 - name: Data0 - - bit_offset: 24 - bit_size: 8 - description: Data1 - name: Data1 + - name: OPTERR + description: Option byte error + bit_offset: 0 + bit_size: 1 + enum: OPTERR + - name: RDPRT + description: Read protection Level status + bit_offset: 1 + bit_size: 2 + enum: RDPRT + - name: WDG_SW + description: WDG_SW + bit_offset: 8 + bit_size: 1 + enum: WDG_SW + - name: nRST_STOP + description: nRST_STOP + bit_offset: 9 + bit_size: 1 + enum: nRST_STOP + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 10 + bit_size: 1 + enum: nRST_STDBY + - name: nBOOT1 + description: BOOT1 + bit_offset: 12 + bit_size: 1 + enum: nBOOT + - name: VDDA_MONITOR + description: VDDA_MONITOR + bit_offset: 13 + bit_size: 1 + enum: VDDA_MONITOR + - name: SRAM_PARITY_CHECK + description: SRAM_PARITY_CHECK + bit_offset: 14 + bit_size: 1 + - name: SDADC12_VDD_MONITOR + description: SDADC12_VDD_MONITOR + bit_offset: 15 + bit_size: 1 + enum: SDADC_VDD_MONITOR + - name: Data0 + description: Data0 + bit_offset: 16 + bit_size: 8 + - name: Data1 + description: Data1 + bit_offset: 24 + bit_size: 8 fieldset/OPTKEYR: description: Flash option key register fields: - - bit_offset: 0 - bit_size: 32 - description: Option byte key - name: OPTKEYR + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 fieldset/SR: description: Flash status register fields: - - bit_offset: 0 - bit_size: 1 - description: Busy - enum_read: BSYR - name: BSY - - bit_offset: 2 - bit_size: 1 - description: Programming error - enum_read: PGERRR - enum_write: PGERRW - name: PGERR - - bit_offset: 4 - bit_size: 1 - description: Write protection error - enum_read: WRPRTERRR - enum_write: WRPRTERRW - name: WRPRTERR - - bit_offset: 5 - bit_size: 1 - description: End of operation - enum_read: EOPR - enum_write: EOPW - name: EOP + - name: BSY + description: Busy + bit_offset: 0 + bit_size: 1 + enum_read: BSYR + - name: PGERR + description: Programming error + bit_offset: 2 + bit_size: 1 + enum_read: PGERRR + enum_write: PGERRW + - name: WRPRTERR + description: Write protection error + bit_offset: 4 + bit_size: 1 + enum_read: WRPRTERRR + enum_write: WRPRTERRW + - name: EOP + description: End of operation + bit_offset: 5 + bit_size: 1 + enum_read: EOPR + enum_write: EOPW fieldset/WRPR: description: Write protection register fields: - - bit_offset: 0 - bit_size: 32 - description: Write protect - name: WRP + - name: WRP + description: Write protect + bit_offset: 0 + bit_size: 32 +enum/BSYR: + bit_size: 1 + variants: + - name: Inactive + description: No write/erase operation is in progress + value: 0 + - name: Active + description: No write/erase operation is in progress + value: 1 +enum/EOPIE: + bit_size: 1 + variants: + - name: Disabled + description: End of operation interrupt disabled + value: 0 + - name: Enabled + description: End of operation interrupt enabled + value: 1 +enum/EOPR: + bit_size: 1 + variants: + - name: NoEvent + description: No EOP event occurred + value: 0 + - name: Event + description: An EOP event occurred + value: 1 +enum/EOPW: + bit_size: 1 + variants: + - name: Reset + description: Reset EOP event + value: 1 +enum/ERRIE: + bit_size: 1 + variants: + - name: Disabled + description: Error interrupt generation disabled + value: 0 + - name: Enabled + description: Error interrupt generation enabled + value: 1 +enum/HLFCYA: + bit_size: 1 + variants: + - name: Disabled + description: Half cycle is disabled + value: 0 + - name: Enabled + description: Half cycle is enabled + value: 1 +enum/LATENCY: + bit_size: 3 + variants: + - name: WS0 + description: "0 wait states, if 0 < HCLK <= 24 MHz" + value: 0 + - name: WS1 + description: "1 wait state, if 24 < HCLK <= 48 MHz" + value: 1 + - name: WS2 + description: "2 wait states, if 48 < HCLK <= 72 MHz" + value: 2 +enum/LOCKR: + bit_size: 1 + variants: + - name: Unlocked + description: FLASH_CR register is unlocked + value: 0 + - name: Locked + description: FLASH_CR register is locked + value: 1 +enum/LOCKW: + bit_size: 1 + variants: + - name: Lock + description: Lock the FLASH_CR register + value: 1 +enum/MER: + bit_size: 1 + variants: + - name: MassErase + description: Erase activated for all user sectors + value: 1 +enum/OBL_LAUNCH: + bit_size: 1 + variants: + - name: Inactive + description: Force option byte loading inactive + value: 0 + - name: Active + description: Force option byte loading active + value: 1 +enum/OPTER: + bit_size: 1 + variants: + - name: OptionByteErase + description: Erase option byte activated + value: 1 +enum/OPTERR: + bit_size: 1 + variants: + - name: OptionByteError + description: The loaded option byte and its complement do not match + value: 1 +enum/OPTPG: + bit_size: 1 + variants: + - name: OptionByteProgramming + description: Program option byte activated + value: 1 +enum/OPTWRE: + bit_size: 1 + variants: + - name: Disabled + description: Option byte write enabled + value: 0 + - name: Enabled + description: Option byte write disabled + value: 1 +enum/PER: + bit_size: 1 + variants: + - name: PageErase + description: Erase activated for selected page + value: 1 +enum/PG: + bit_size: 1 + variants: + - name: Program + description: Flash programming activated + value: 1 +enum/PGERRR: + bit_size: 1 + variants: + - name: NoError + description: No programming error occurred + value: 0 + - name: Error + description: A programming error occurred + value: 1 +enum/PGERRW: + bit_size: 1 + variants: + - name: Reset + description: Reset programming error + value: 1 +enum/PRFTBE: + bit_size: 1 + variants: + - name: Disabled + description: Prefetch is disabled + value: 0 + - name: Enabled + description: Prefetch is enabled + value: 1 +enum/PRFTBS: + bit_size: 1 + variants: + - name: Disabled + description: Prefetch buffer is disabled + value: 0 + - name: Enabled + description: Prefetch buffer is enabled + value: 1 +enum/RDPRT: + bit_size: 2 + variants: + - name: Level0 + description: Level 0 + value: 0 + - name: Level1 + description: Level 1 + value: 1 + - name: Level2 + description: Level 2 + value: 3 +enum/SDADC_VDD_MONITOR: + bit_size: 1 + variants: + - name: Disabled + description: VDDSD12 monitoring disabled + value: 0 + - name: Enabled + description: VDDSD12 monitoring enabled + value: 1 +enum/SRAM_PARITY_CHECK: + bit_size: 1 + variants: + - name: Disabled + description: RAM parity check disabled + value: 0 + - name: Enabled + description: RAM parity check enabled + value: 1 +enum/STRT: + bit_size: 1 + variants: + - name: Start + description: Trigger an erase operation + value: 1 +enum/VDDA_MONITOR: + bit_size: 1 + variants: + - name: Disabled + description: VDDA power supply supervisor disabled + value: 0 + - name: Enabled + description: VDDA power supply supervisor enabled + value: 1 +enum/WDG_SW: + bit_size: 1 + variants: + - name: Hardware + description: Hardware watchdog + value: 0 + - name: Software + description: Software watchdog + value: 1 +enum/WRPRTERRR: + bit_size: 1 + variants: + - name: NoError + description: No write protection error occurred + value: 0 + - name: Error + description: A write protection error occurred + value: 1 +enum/WRPRTERRW: + bit_size: 1 + variants: + - name: Reset + description: Reset write protection error + value: 1 +enum/nBOOT: + bit_size: 1 + variants: + - name: Disabled + description: "Together with BOOT0, select the device boot mode" + value: 0 + - name: Enabled + description: "Together with BOOT0, select the device boot mode" + value: 1 +enum/nRST_STDBY: + bit_size: 1 + variants: + - name: Reset + description: Reset generated when entering Standby mode + value: 0 + - name: NoReset + description: No reset generated + value: 1 +enum/nRST_STOP: + bit_size: 1 + variants: + - name: Reset + description: Reset generated when entering Stop mode + value: 0 + - name: NoReset + description: No reset generated + value: 1 diff --git a/data/registers/flash_l1.yaml b/data/registers/flash_l1.yaml index 495dfe8..ce0585a 100644 --- a/data/registers/flash_l1.yaml +++ b/data/registers/flash_l1.yaml @@ -1,241 +1,242 @@ +--- block/FLASH: description: Flash items: - - byte_offset: 0 - description: Access control register - fieldset: ACR - name: ACR - - byte_offset: 4 - description: Program/erase control register - fieldset: PECR - name: PECR - - access: Write - byte_offset: 8 - description: Power down key register - fieldset: PDKEYR - name: PDKEYR - - access: Write - byte_offset: 12 - description: Program/erase key register - fieldset: PEKEYR - name: PEKEYR - - access: Write - byte_offset: 16 - description: Program memory key register - fieldset: PRGKEYR - name: PRGKEYR - - access: Write - byte_offset: 20 - description: Option byte key register - fieldset: OPTKEYR - name: OPTKEYR - - byte_offset: 24 - description: Status register - fieldset: SR - name: SR - - access: Read - byte_offset: 28 - description: Option byte register - fieldset: OBR - name: OBR - - byte_offset: 32 - description: Write protection register - fieldset: WRPR1 - name: WRPR1 - - byte_offset: 128 - description: Write protection register - fieldset: WRPR2 - name: WRPR2 - - byte_offset: 132 - description: Write protection register - fieldset: WRPR3 - name: WRPR3 + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: PECR + description: Program/erase control register + byte_offset: 4 + fieldset: PECR + - name: PDKEYR + description: Power down key register + byte_offset: 8 + access: Write + fieldset: PDKEYR + - name: PEKEYR + description: Program/erase key register + byte_offset: 12 + access: Write + fieldset: PEKEYR + - name: PRGKEYR + description: Program memory key register + byte_offset: 16 + access: Write + fieldset: PRGKEYR + - name: OPTKEYR + description: Option byte key register + byte_offset: 20 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 24 + fieldset: SR + - name: OBR + description: Option byte register + byte_offset: 28 + access: Read + fieldset: OBR + - name: WRPR1 + description: Write protection register + byte_offset: 32 + fieldset: WRPR1 + - name: WRPR2 + description: Write protection register + byte_offset: 128 + fieldset: WRPR2 + - name: WRPR3 + description: Write protection register + byte_offset: 132 + fieldset: WRPR3 fieldset/ACR: description: Access control register fields: - - bit_offset: 0 - bit_size: 1 - description: Latency - name: LATENCY - - bit_offset: 1 - bit_size: 1 - description: Prefetch enable - name: PRFTEN - - bit_offset: 2 - bit_size: 1 - description: 64-bit access - name: ACC64 - - bit_offset: 3 - bit_size: 1 - description: Flash mode during Sleep - name: SLEEP_PD - - bit_offset: 4 - bit_size: 1 - description: Flash mode during Run - name: RUN_PD + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 1 + - name: PRFTEN + description: Prefetch enable + bit_offset: 1 + bit_size: 1 + - name: ACC64 + description: 64-bit access + bit_offset: 2 + bit_size: 1 + - name: SLEEP_PD + description: Flash mode during Sleep + bit_offset: 3 + bit_size: 1 + - name: RUN_PD + description: Flash mode during Run + bit_offset: 4 + bit_size: 1 fieldset/OBR: description: Option byte register fields: - - bit_offset: 0 - bit_size: 8 - description: Read protection - name: RDPRT - - bit_offset: 16 - bit_size: 4 - description: BOR_LEV - name: BOR_LEV - - bit_offset: 20 - bit_size: 1 - description: IWDG_SW - name: IWDG_SW - - bit_offset: 21 - bit_size: 1 - description: nRTS_STOP - name: nRTS_STOP - - bit_offset: 22 - bit_size: 1 - description: nRST_STDBY - name: nRST_STDBY - - bit_offset: 23 - bit_size: 1 - description: Boot From Bank 2 - name: BFB2 + - name: RDPRT + description: Read protection + bit_offset: 0 + bit_size: 8 + - name: BOR_LEV + description: BOR_LEV + bit_offset: 16 + bit_size: 4 + - name: IWDG_SW + description: IWDG_SW + bit_offset: 20 + bit_size: 1 + - name: nRTS_STOP + description: nRTS_STOP + bit_offset: 21 + bit_size: 1 + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 22 + bit_size: 1 + - name: BFB2 + description: Boot From Bank 2 + bit_offset: 23 + bit_size: 1 fieldset/OPTKEYR: description: Option byte key register fields: - - bit_offset: 0 - bit_size: 32 - description: Option byte key - name: OPTKEYR + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 fieldset/PDKEYR: description: Power down key register fields: - - bit_offset: 0 - bit_size: 32 - description: RUN_PD in FLASH_ACR key - name: PDKEYR + - name: PDKEYR + description: RUN_PD in FLASH_ACR key + bit_offset: 0 + bit_size: 32 fieldset/PECR: description: Program/erase control register fields: - - bit_offset: 0 - bit_size: 1 - description: FLASH_PECR and data EEPROM lock - name: PELOCK - - bit_offset: 1 - bit_size: 1 - description: Program memory lock - name: PRGLOCK - - bit_offset: 2 - bit_size: 1 - description: Option bytes block lock - name: OPTLOCK - - bit_offset: 3 - bit_size: 1 - description: Program memory selection - name: PROG - - bit_offset: 4 - bit_size: 1 - description: Data EEPROM selection - name: DATA - - bit_offset: 8 - bit_size: 1 - description: Fixed time data write for Byte, Half Word and Word programming - name: FTDW - - bit_offset: 9 - bit_size: 1 - description: Page or Double Word erase mode - name: ERASE - - bit_offset: 10 - bit_size: 1 - description: Half Page/Double Word programming mode - name: FPRG - - bit_offset: 15 - bit_size: 1 - description: Parallel bank mode - name: PARALLELBANK - - bit_offset: 16 - bit_size: 1 - description: End of programming interrupt enable - name: EOPIE - - bit_offset: 17 - bit_size: 1 - description: Error interrupt enable - name: ERRIE - - bit_offset: 18 - bit_size: 1 - description: Launch the option byte loading - name: OBL_LAUNCH + - name: PELOCK + description: FLASH_PECR and data EEPROM lock + bit_offset: 0 + bit_size: 1 + - name: PRGLOCK + description: Program memory lock + bit_offset: 1 + bit_size: 1 + - name: OPTLOCK + description: Option bytes block lock + bit_offset: 2 + bit_size: 1 + - name: PROG + description: Program memory selection + bit_offset: 3 + bit_size: 1 + - name: DATA + description: Data EEPROM selection + bit_offset: 4 + bit_size: 1 + - name: FTDW + description: "Fixed time data write for Byte, Half Word and Word programming" + bit_offset: 8 + bit_size: 1 + - name: ERASE + description: Page or Double Word erase mode + bit_offset: 9 + bit_size: 1 + - name: FPRG + description: Half Page/Double Word programming mode + bit_offset: 10 + bit_size: 1 + - name: PARALLELBANK + description: Parallel bank mode + bit_offset: 15 + bit_size: 1 + - name: EOPIE + description: End of programming interrupt enable + bit_offset: 16 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 17 + bit_size: 1 + - name: OBL_LAUNCH + description: Launch the option byte loading + bit_offset: 18 + bit_size: 1 fieldset/PEKEYR: description: Program/erase key register fields: - - bit_offset: 0 - bit_size: 32 - description: FLASH_PEC and data EEPROM key - name: PEKEYR + - name: PEKEYR + description: FLASH_PEC and data EEPROM key + bit_offset: 0 + bit_size: 32 fieldset/PRGKEYR: description: Program memory key register fields: - - bit_offset: 0 - bit_size: 32 - description: Program memory key - name: PRGKEYR + - name: PRGKEYR + description: Program memory key + bit_offset: 0 + bit_size: 32 fieldset/SR: description: Status register fields: - - bit_offset: 0 - bit_size: 1 - description: Write/erase operations in progress - name: BSY - - bit_offset: 1 - bit_size: 1 - description: End of operation - name: EOP - - bit_offset: 2 - bit_size: 1 - description: End of high voltage - name: ENDHV - - bit_offset: 3 - bit_size: 1 - description: Flash memory module ready after low power mode - name: READY - - bit_offset: 8 - bit_size: 1 - description: Write protected error - name: WRPERR - - bit_offset: 9 - bit_size: 1 - description: Programming alignment error - name: PGAERR - - bit_offset: 10 - bit_size: 1 - description: Size error - name: SIZERR - - bit_offset: 11 - bit_size: 1 - description: Option validity error - name: OPTVERR - - bit_offset: 12 - bit_size: 1 - description: Option UserValidity Error - name: OPTVERRUSR + - name: BSY + description: Write/erase operations in progress + bit_offset: 0 + bit_size: 1 + - name: EOP + description: End of operation + bit_offset: 1 + bit_size: 1 + - name: ENDHV + description: End of high voltage + bit_offset: 2 + bit_size: 1 + - name: READY + description: Flash memory module ready after low power mode + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: Write protected error + bit_offset: 8 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 9 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 10 + bit_size: 1 + - name: OPTVERR + description: Option validity error + bit_offset: 11 + bit_size: 1 + - name: OPTVERRUSR + description: Option UserValidity Error + bit_offset: 12 + bit_size: 1 fieldset/WRPR1: description: Write protection register fields: - - bit_offset: 0 - bit_size: 32 - description: Write protection - name: WRP1 + - name: WRP1 + description: Write protection + bit_offset: 0 + bit_size: 32 fieldset/WRPR2: description: Write protection register fields: - - bit_offset: 0 - bit_size: 32 - description: WRP2 - name: WRP2 + - name: WRP2 + description: WRP2 + bit_offset: 0 + bit_size: 32 fieldset/WRPR3: description: Write protection register fields: - - bit_offset: 0 - bit_size: 32 - description: WRP3 - name: WRP3 + - name: WRP3 + description: WRP3 + bit_offset: 0 + bit_size: 32 diff --git a/data/registers/flash_wb55.yaml b/data/registers/flash_wb55.yaml index 60cc8a2..da253b4 100644 --- a/data/registers/flash_wb55.yaml +++ b/data/registers/flash_wb55.yaml @@ -2,558 +2,558 @@ block/FLASH: description: Flash items: - - byte_offset: 0 - description: Access control register - fieldset: ACR - name: ACR - - access: Write - byte_offset: 8 - description: Flash key register - fieldset: KEYR - name: KEYR - - access: Write - byte_offset: 12 - description: Option byte key register - fieldset: OPTKEYR - name: OPTKEYR - - byte_offset: 16 - description: Status register - fieldset: SR - name: SR - - byte_offset: 20 - description: Flash control register - fieldset: CR - name: CR - - byte_offset: 24 - description: Flash ECC register - fieldset: ECCR - name: ECCR - - byte_offset: 32 - description: Flash option register - fieldset: OPTR - name: OPTR - - byte_offset: 36 - description: Flash Bank 1 PCROP Start address zone A register - fieldset: PCROP1ASR - name: PCROP1ASR - - byte_offset: 40 - description: Flash Bank 1 PCROP End address zone A register - fieldset: PCROP1AER - name: PCROP1AER - - byte_offset: 44 - description: Flash Bank 1 WRP area A address register - fieldset: WRP1AR - name: WRP1AR - - byte_offset: 48 - description: Flash Bank 1 WRP area B address register - fieldset: WRP1BR - name: WRP1BR - - byte_offset: 52 - description: Flash Bank 1 PCROP Start address area B register - fieldset: PCROP1BSR - name: PCROP1BSR - - byte_offset: 56 - description: Flash Bank 1 PCROP End address area B register - fieldset: PCROP1BER - name: PCROP1BER - - byte_offset: 60 - description: IPCC mailbox data buffer address register - fieldset: IPCCBR - name: IPCCBR - - byte_offset: 92 - description: CPU2 cortex M0 access control register - fieldset: C2ACR - name: C2ACR - - byte_offset: 96 - description: CPU2 cortex M0 status register - fieldset: C2SR - name: C2SR - - byte_offset: 100 - description: CPU2 cortex M0 control register - fieldset: C2CR - name: C2CR - - byte_offset: 128 - description: Secure flash start address register - fieldset: SFR - name: SFR - - byte_offset: 132 - description: Secure SRAM2 start address and cortex M0 reset vector register - fieldset: SRRVR - name: SRRVR + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: KEYR + description: Flash key register + byte_offset: 8 + access: Write + fieldset: KEYR + - name: OPTKEYR + description: Option byte key register + byte_offset: 12 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 16 + fieldset: SR + - name: CR + description: Flash control register + byte_offset: 20 + fieldset: CR + - name: ECCR + description: Flash ECC register + byte_offset: 24 + fieldset: ECCR + - name: OPTR + description: Flash option register + byte_offset: 32 + fieldset: OPTR + - name: PCROP1ASR + description: Flash Bank 1 PCROP Start address zone A register + byte_offset: 36 + fieldset: PCROP1ASR + - name: PCROP1AER + description: Flash Bank 1 PCROP End address zone A register + byte_offset: 40 + fieldset: PCROP1AER + - name: WRP1AR + description: Flash Bank 1 WRP area A address register + byte_offset: 44 + fieldset: WRP1AR + - name: WRP1BR + description: Flash Bank 1 WRP area B address register + byte_offset: 48 + fieldset: WRP1BR + - name: PCROP1BSR + description: Flash Bank 1 PCROP Start address area B register + byte_offset: 52 + fieldset: PCROP1BSR + - name: PCROP1BER + description: Flash Bank 1 PCROP End address area B register + byte_offset: 56 + fieldset: PCROP1BER + - name: IPCCBR + description: IPCC mailbox data buffer address register + byte_offset: 60 + fieldset: IPCCBR + - name: C2ACR + description: CPU2 cortex M0 access control register + byte_offset: 92 + fieldset: C2ACR + - name: C2SR + description: CPU2 cortex M0 status register + byte_offset: 96 + fieldset: C2SR + - name: C2CR + description: CPU2 cortex M0 control register + byte_offset: 100 + fieldset: C2CR + - name: SFR + description: Secure flash start address register + byte_offset: 128 + fieldset: SFR + - name: SRRVR + description: Secure SRAM2 start address and cortex M0 reset vector register + byte_offset: 132 + fieldset: SRRVR fieldset/ACR: description: Access control register fields: - - bit_offset: 0 - bit_size: 3 - description: Latency - name: LATENCY - - bit_offset: 8 - bit_size: 1 - description: Prefetch enable - name: PRFTEN - - bit_offset: 9 - bit_size: 1 - description: Instruction cache enable - name: ICEN - - bit_offset: 10 - bit_size: 1 - description: Data cache enable - name: DCEN - - bit_offset: 11 - bit_size: 1 - description: Instruction cache reset - name: ICRST - - bit_offset: 12 - bit_size: 1 - description: Data cache reset - name: DCRST - - bit_offset: 15 - bit_size: 1 - description: CPU1 CortexM4 program erase suspend request - name: PES - - bit_offset: 16 - bit_size: 1 - description: Flash User area empty - name: EMPTY + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 3 + - name: PRFTEN + description: Prefetch enable + bit_offset: 8 + bit_size: 1 + - name: ICEN + description: Instruction cache enable + bit_offset: 9 + bit_size: 1 + - name: DCEN + description: Data cache enable + bit_offset: 10 + bit_size: 1 + - name: ICRST + description: Instruction cache reset + bit_offset: 11 + bit_size: 1 + - name: DCRST + description: Data cache reset + bit_offset: 12 + bit_size: 1 + - name: PES + description: CPU1 CortexM4 program erase suspend request + bit_offset: 15 + bit_size: 1 + - name: EMPTY + description: Flash User area empty + bit_offset: 16 + bit_size: 1 fieldset/C2ACR: description: CPU2 cortex M0 access control register fields: - - bit_offset: 8 - bit_size: 1 - description: CPU2 cortex M0 prefetch enable - name: PRFTEN - - bit_offset: 9 - bit_size: 1 - description: CPU2 cortex M0 instruction cache enable - name: ICEN - - bit_offset: 11 - bit_size: 1 - description: CPU2 cortex M0 instruction cache reset - name: ICRST - - bit_offset: 15 - bit_size: 1 - description: CPU2 cortex M0 program erase suspend request - name: PES + - name: PRFTEN + description: CPU2 cortex M0 prefetch enable + bit_offset: 8 + bit_size: 1 + - name: ICEN + description: CPU2 cortex M0 instruction cache enable + bit_offset: 9 + bit_size: 1 + - name: ICRST + description: CPU2 cortex M0 instruction cache reset + bit_offset: 11 + bit_size: 1 + - name: PES + description: CPU2 cortex M0 program erase suspend request + bit_offset: 15 + bit_size: 1 fieldset/C2CR: description: CPU2 cortex M0 control register fields: - - bit_offset: 0 - bit_size: 1 - description: Programming - name: PG - - bit_offset: 1 - bit_size: 1 - description: Page erase - name: PER - - bit_offset: 2 - bit_size: 1 - description: Masse erase - name: MER - - bit_offset: 3 - bit_size: 8 - description: Page Number selection - name: PNB - - bit_offset: 16 - bit_size: 1 - description: Start - name: STRT - - bit_offset: 18 - bit_size: 1 - description: Fast programming - name: FSTPG - - bit_offset: 24 - bit_size: 1 - description: End of operation interrupt enable - name: EOPIE - - bit_offset: 25 - bit_size: 1 - description: Error interrupt enable - name: ERRIE - - bit_offset: 26 - bit_size: 1 - description: PCROP read error interrupt enable - name: RDERRIE + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: Masse erase + bit_offset: 2 + bit_size: 1 + - name: PNB + description: Page Number selection + bit_offset: 3 + bit_size: 8 + - name: STRT + description: Start + bit_offset: 16 + bit_size: 1 + - name: FSTPG + description: Fast programming + bit_offset: 18 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 25 + bit_size: 1 + - name: RDERRIE + description: PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 fieldset/C2SR: description: CPU2 cortex M0 status register fields: - - bit_offset: 0 - bit_size: 1 - description: End of operation - name: EOP - - bit_offset: 1 - bit_size: 1 - description: Operation error - name: OPERR - - bit_offset: 3 - bit_size: 1 - description: Programming error - name: PROGERR - - bit_offset: 4 - bit_size: 1 - description: write protection error - name: WRPERR - - bit_offset: 5 - bit_size: 1 - description: Programming alignment error - name: PGAERR - - bit_offset: 6 - bit_size: 1 - description: Size error - name: SIZERR - - bit_offset: 7 - bit_size: 1 - description: Programming sequence error - name: PGSERR - - bit_offset: 8 - bit_size: 1 - description: Fast programming data miss error - name: MISSERR - - bit_offset: 9 - bit_size: 1 - description: Fast programming error - name: FASTERR - - bit_offset: 14 - bit_size: 1 - description: PCROP read error - name: RDERR - - bit_offset: 16 - bit_size: 1 - description: Busy - name: BSY - - bit_offset: 18 - bit_size: 1 - description: Programming or erase configuration busy - name: CFGBSY - - bit_offset: 19 - bit_size: 1 - description: Programming or erase operation suspended - name: PESD + - name: EOP + description: End of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Programming error + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: write protection error + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Programming sequence error + bit_offset: 7 + bit_size: 1 + - name: MISSERR + description: Fast programming data miss error + bit_offset: 8 + bit_size: 1 + - name: FASTERR + description: Fast programming error + bit_offset: 9 + bit_size: 1 + - name: RDERR + description: PCROP read error + bit_offset: 14 + bit_size: 1 + - name: BSY + description: Busy + bit_offset: 16 + bit_size: 1 + - name: CFGBSY + description: Programming or erase configuration busy + bit_offset: 18 + bit_size: 1 + - name: PESD + description: Programming or erase operation suspended + bit_offset: 19 + bit_size: 1 fieldset/CR: description: Flash control register fields: - - bit_offset: 0 - bit_size: 1 - description: Programming - name: PG - - bit_offset: 1 - bit_size: 1 - description: Page erase - name: PER - - bit_offset: 2 - bit_size: 1 - description: This bit triggers the mass erase (all user pages) when set - name: MER - - bit_offset: 3 - bit_size: 8 - description: Page number selection - name: PNB - - bit_offset: 16 - bit_size: 1 - description: Start - name: STRT - - bit_offset: 17 - bit_size: 1 - description: Options modification start - name: OPTSTRT - - bit_offset: 18 - bit_size: 1 - description: Fast programming - name: FSTPG - - bit_offset: 24 - bit_size: 1 - description: End of operation interrupt enable - name: EOPIE - - bit_offset: 25 - bit_size: 1 - description: Error interrupt enable - name: ERRIE - - bit_offset: 26 - bit_size: 1 - description: PCROP read error interrupt enable - name: RDERRIE - - bit_offset: 27 - bit_size: 1 - description: Force the option byte loading - name: OBL_LAUNCH - - bit_offset: 30 - bit_size: 1 - description: Options Lock - name: OPTLOCK - - bit_offset: 31 - bit_size: 1 - description: FLASH_CR Lock - name: LOCK + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: This bit triggers the mass erase (all user pages) when set + bit_offset: 2 + bit_size: 1 + - name: PNB + description: Page number selection + bit_offset: 3 + bit_size: 8 + - name: STRT + description: Start + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: Options modification start + bit_offset: 17 + bit_size: 1 + - name: FSTPG + description: Fast programming + bit_offset: 18 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 25 + bit_size: 1 + - name: RDERRIE + description: PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 + - name: OBL_LAUNCH + description: Force the option byte loading + bit_offset: 27 + bit_size: 1 + - name: OPTLOCK + description: Options Lock + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: FLASH_CR Lock + bit_offset: 31 + bit_size: 1 fieldset/ECCR: description: Flash ECC register fields: - - bit_offset: 0 - bit_size: 17 - description: ECC fail address - name: ADDR_ECC - - bit_offset: 20 - bit_size: 1 - description: System Flash ECC fail - name: SYSF_ECC - - bit_offset: 24 - bit_size: 1 - description: ECC correction interrupt enable - name: ECCCIE - - bit_offset: 26 - bit_size: 3 - description: CPU identification - name: CPUID - - bit_offset: 30 - bit_size: 1 - description: ECC correction - name: ECCC - - bit_offset: 31 - bit_size: 1 - description: ECC detection - name: ECCD + - name: ADDR_ECC + description: ECC fail address + bit_offset: 0 + bit_size: 17 + - name: SYSF_ECC + description: System Flash ECC fail + bit_offset: 20 + bit_size: 1 + - name: ECCCIE + description: ECC correction interrupt enable + bit_offset: 24 + bit_size: 1 + - name: CPUID + description: CPU identification + bit_offset: 26 + bit_size: 3 + - name: ECCC + description: ECC correction + bit_offset: 30 + bit_size: 1 + - name: ECCD + description: ECC detection + bit_offset: 31 + bit_size: 1 fieldset/IPCCBR: description: IPCC mailbox data buffer address register fields: - - bit_offset: 0 - bit_size: 14 - description: PCC mailbox data buffer base address - name: IPCCDBA + - name: IPCCDBA + description: PCC mailbox data buffer base address + bit_offset: 0 + bit_size: 14 fieldset/KEYR: description: Flash key register fields: - - bit_offset: 0 - bit_size: 32 - description: KEYR - name: KEYR + - name: KEYR + description: KEYR + bit_offset: 0 + bit_size: 32 fieldset/OPTKEYR: description: Option byte key register fields: - - bit_offset: 0 - bit_size: 32 - description: Option byte key - name: OPTKEYR + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 fieldset/OPTR: description: Flash option register fields: - - bit_offset: 0 - bit_size: 8 - description: Read protection level - name: RDP - - bit_offset: 8 - bit_size: 1 - description: Security enabled - name: ESE - - bit_offset: 9 - bit_size: 3 - description: BOR reset Level - name: BOR_LEV - - bit_offset: 12 - bit_size: 1 - description: nRST_STOP - name: nRST_STOP - - bit_offset: 13 - bit_size: 1 - description: nRST_STDBY - name: nRST_STDBY - - bit_offset: 14 - bit_size: 1 - description: nRST_SHDW - name: nRST_SHDW - - bit_offset: 16 - bit_size: 1 - description: Independent watchdog selection - name: IDWG_SW - - bit_offset: 17 - bit_size: 1 - description: Independent watchdog counter freeze in Stop mode - name: IWDG_STOP - - bit_offset: 18 - bit_size: 1 - description: Independent watchdog counter freeze in Standby mode - name: IWDG_STDBY - - bit_offset: 19 - bit_size: 1 - description: Window watchdog selection - name: WWDG_SW - - bit_offset: 23 - bit_size: 1 - description: Boot configuration - name: nBOOT1 - - bit_offset: 24 - bit_size: 1 - description: SRAM2 parity check enable - name: SRAM2_PE - - bit_offset: 25 - bit_size: 1 - description: SRAM2 Erase when system reset - name: SRAM2_RST - - bit_offset: 26 - bit_size: 1 - description: Software Boot0 - name: nSWBOOT0 - - bit_offset: 27 - bit_size: 1 - description: nBoot0 option bit - name: nBOOT0 - - bit_offset: 29 - bit_size: 3 - description: Radio Automatic Gain Control Trimming - name: AGC_TRIM + - name: RDP + description: Read protection level + bit_offset: 0 + bit_size: 8 + - name: ESE + description: Security enabled + bit_offset: 8 + bit_size: 1 + - name: BOR_LEV + description: BOR reset Level + bit_offset: 9 + bit_size: 3 + - name: nRST_STOP + description: nRST_STOP + bit_offset: 12 + bit_size: 1 + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 13 + bit_size: 1 + - name: nRST_SHDW + description: nRST_SHDW + bit_offset: 14 + bit_size: 1 + - name: IDWG_SW + description: Independent watchdog selection + bit_offset: 16 + bit_size: 1 + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 17 + bit_size: 1 + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode + bit_offset: 18 + bit_size: 1 + - name: WWDG_SW + description: Window watchdog selection + bit_offset: 19 + bit_size: 1 + - name: nBOOT1 + description: Boot configuration + bit_offset: 23 + bit_size: 1 + - name: SRAM2_PE + description: SRAM2 parity check enable + bit_offset: 24 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 Erase when system reset + bit_offset: 25 + bit_size: 1 + - name: nSWBOOT0 + description: Software Boot0 + bit_offset: 26 + bit_size: 1 + - name: nBOOT0 + description: nBoot0 option bit + bit_offset: 27 + bit_size: 1 + - name: AGC_TRIM + description: Radio Automatic Gain Control Trimming + bit_offset: 29 + bit_size: 3 fieldset/PCROP1AER: description: Flash Bank 1 PCROP End address zone A register fields: - - bit_offset: 0 - bit_size: 9 - description: Bank 1 PCROP area end offset - name: PCROP1A_END - - bit_offset: 31 - bit_size: 1 - description: PCROP area preserved when RDP level decreased - name: PCROP_RDP + - name: PCROP1A_END + description: Bank 1 PCROP area end offset + bit_offset: 0 + bit_size: 9 + - name: PCROP_RDP + description: PCROP area preserved when RDP level decreased + bit_offset: 31 + bit_size: 1 fieldset/PCROP1ASR: description: Flash Bank 1 PCROP Start address zone A register fields: - - bit_offset: 0 - bit_size: 9 - description: Bank 1 PCROPQ area start offset - name: PCROP1A_STRT + - name: PCROP1A_STRT + description: Bank 1 PCROPQ area start offset + bit_offset: 0 + bit_size: 9 fieldset/PCROP1BER: description: Flash Bank 1 PCROP End address area B register fields: - - bit_offset: 0 - bit_size: 9 - description: Bank 1 PCROP area end area B offset - name: PCROP1B_END + - name: PCROP1B_END + description: Bank 1 PCROP area end area B offset + bit_offset: 0 + bit_size: 9 fieldset/PCROP1BSR: description: Flash Bank 1 PCROP Start address area B register fields: - - bit_offset: 0 - bit_size: 9 - description: Bank 1 PCROP area B start offset - name: PCROP1B_STRT + - name: PCROP1B_STRT + description: Bank 1 PCROP area B start offset + bit_offset: 0 + bit_size: 9 fieldset/SFR: description: Secure flash start address register fields: - - bit_offset: 0 - bit_size: 8 - description: Secure flash start address - name: SFSA - - bit_offset: 8 - bit_size: 1 - description: Flash security disable - name: FSD - - bit_offset: 12 - bit_size: 1 - description: Disable Cortex M0 debug access - name: DDS + - name: SFSA + description: Secure flash start address + bit_offset: 0 + bit_size: 8 + - name: FSD + description: Flash security disable + bit_offset: 8 + bit_size: 1 + - name: DDS + description: Disable Cortex M0 debug access + bit_offset: 12 + bit_size: 1 fieldset/SR: description: Status register fields: - - bit_offset: 0 - bit_size: 1 - description: End of operation - name: EOP - - bit_offset: 1 - bit_size: 1 - description: Operation error - name: OPERR - - bit_offset: 3 - bit_size: 1 - description: Programming error - name: PROGERR - - bit_offset: 4 - bit_size: 1 - description: Write protected error - name: WRPERR - - bit_offset: 5 - bit_size: 1 - description: Programming alignment error - name: PGAERR - - bit_offset: 6 - bit_size: 1 - description: Size error - name: SIZERR - - bit_offset: 7 - bit_size: 1 - description: Programming sequence error - name: PGSERR - - bit_offset: 8 - bit_size: 1 - description: Fast programming data miss error - name: MISERR - - bit_offset: 9 - bit_size: 1 - description: Fast programming error - name: FASTERR - - bit_offset: 13 - bit_size: 1 - description: User Option OPTVAL indication - name: OPTNV - - bit_offset: 14 - bit_size: 1 - description: PCROP read error - name: RDERR - - bit_offset: 15 - bit_size: 1 - description: Option validity error - name: OPTVERR - - bit_offset: 16 - bit_size: 1 - description: Busy - name: BSY - - bit_offset: 18 - bit_size: 1 - description: Programming or erase configuration busy - name: CFGBSY - - bit_offset: 19 - bit_size: 1 - description: Programming or erase operation suspended - name: PESD + - name: EOP + description: End of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Programming error + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: Write protected error + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Programming sequence error + bit_offset: 7 + bit_size: 1 + - name: MISERR + description: Fast programming data miss error + bit_offset: 8 + bit_size: 1 + - name: FASTERR + description: Fast programming error + bit_offset: 9 + bit_size: 1 + - name: OPTNV + description: User Option OPTVAL indication + bit_offset: 13 + bit_size: 1 + - name: RDERR + description: PCROP read error + bit_offset: 14 + bit_size: 1 + - name: OPTVERR + description: Option validity error + bit_offset: 15 + bit_size: 1 + - name: BSY + description: Busy + bit_offset: 16 + bit_size: 1 + - name: CFGBSY + description: Programming or erase configuration busy + bit_offset: 18 + bit_size: 1 + - name: PESD + description: Programming or erase operation suspended + bit_offset: 19 + bit_size: 1 fieldset/SRRVR: description: Secure SRAM2 start address and cortex M0 reset vector register fields: - - bit_offset: 0 - bit_size: 18 - description: cortex M0 access control register - name: SBRV - - bit_offset: 18 - bit_size: 5 - description: Secure backup SRAM2a start address - name: SBRSA - - bit_offset: 23 - bit_size: 1 - description: backup SRAM2a security disable - name: BRSD - - bit_offset: 25 - bit_size: 5 - description: Secure non backup SRAM2a start address - name: SNBRSA - - bit_offset: 30 - bit_size: 1 - description: non-backup SRAM2b security disable - name: NBRSD - - bit_offset: 31 - bit_size: 1 - description: CPU2 cortex M0 boot reset vector memory selection - name: C2OPT + - name: SBRV + description: cortex M0 access control register + bit_offset: 0 + bit_size: 18 + - name: SBRSA + description: Secure backup SRAM2a start address + bit_offset: 18 + bit_size: 5 + - name: BRSD + description: backup SRAM2a security disable + bit_offset: 23 + bit_size: 1 + - name: SNBRSA + description: Secure non backup SRAM2a start address + bit_offset: 25 + bit_size: 5 + - name: NBRSD + description: non-backup SRAM2b security disable + bit_offset: 30 + bit_size: 1 + - name: C2OPT + description: CPU2 cortex M0 boot reset vector memory selection + bit_offset: 31 + bit_size: 1 fieldset/WRP1AR: description: Flash Bank 1 WRP area A address register fields: - - bit_offset: 0 - bit_size: 8 - description: Bank 1 WRP first area A start offset - name: WRP1A_STRT - - bit_offset: 16 - bit_size: 8 - description: Bank 1 WRP first area A end offset - name: WRP1A_END + - name: WRP1A_STRT + description: Bank 1 WRP first area A start offset + bit_offset: 0 + bit_size: 8 + - name: WRP1A_END + description: Bank 1 WRP first area A end offset + bit_offset: 16 + bit_size: 8 fieldset/WRP1BR: description: Flash Bank 1 WRP area B address register fields: - - bit_offset: 0 - bit_size: 8 - description: Bank 1 WRP second area B start offset - name: WRP1B_END - - bit_offset: 16 - bit_size: 8 - description: Bank 1 WRP second area B end offset - name: WRP1B_STRT + - name: WRP1B_END + description: Bank 1 WRP second area B start offset + bit_offset: 0 + bit_size: 8 + - name: WRP1B_STRT + description: Bank 1 WRP second area B end offset + bit_offset: 16 + bit_size: 8 diff --git a/data/registers/fmc_h7.yaml b/data/registers/fmc_h7.yaml index 4b1b235..da827bd 100644 --- a/data/registers/fmc_h7.yaml +++ b/data/registers/fmc_h7.yaml @@ -1,1581 +1,850 @@ +--- block/FMC: description: FMC items: - - byte_offset: 0 - description: This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories. - fieldset: BCR1 - name: BCR1 - - byte_offset: 4 - description: 'This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the - FMC_BCRx register, then this register is partitioned for write and read access, - that is, 2 registers are available: one to configure read accesses (this register) - and one to configure write accesses (FMC_BWTRx registers).' - fieldset: BTR1 - name: BTR1 - - byte_offset: 8 - description: This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories. - fieldset: BCR2 - name: BCR2 - - byte_offset: 12 - description: 'This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the - FMC_BCRx register, then this register is partitioned for write and read access, - that is, 2 registers are available: one to configure read accesses (this register) - and one to configure write accesses (FMC_BWTRx registers).' - fieldset: BTR2 - name: BTR2 - - byte_offset: 16 - description: This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories. - fieldset: BCR3 - name: BCR3 - - byte_offset: 20 - description: 'This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the - FMC_BCRx register, then this register is partitioned for write and read access, - that is, 2 registers are available: one to configure read accesses (this register) - and one to configure write accesses (FMC_BWTRx registers).' - fieldset: BTR3 - name: BTR3 - - byte_offset: 24 - description: This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories. - fieldset: BCR4 - name: BCR4 - - byte_offset: 28 - description: 'This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the - FMC_BCRx register, then this register is partitioned for write and read access, - that is, 2 registers are available: one to configure read accesses (this register) - and one to configure write accesses (FMC_BWTRx registers).' - fieldset: BTR4 - name: BTR4 - - byte_offset: 128 - description: NAND Flash control registers - fieldset: PCR - name: PCR - - byte_offset: 132 - description: This register contains information about the FIFO status and interrupt. - The FMC features a FIFO that is used when writing to memories to transfer up - to 16 words of data.This is used to quickly write to the FIFO and free the AXI - bus for transactions to peripherals other than the FMC, while the FMC is draining - its FIFO into the memory. One of these register bits indicates the status of - the FIFO, for ECC purposes.The ECC is calculated while the data are written - to the memory. To read the correct ECC, the software must consequently wait - until the FIFO is empty. - fieldset: SR - name: SR - - byte_offset: 136 - description: The FMC_PMEM read/write register contains the timing information - for NAND Flash memory bank. This information is used to access either the common - memory space of the NAND Flash for command, address write access and data read/write - access. - fieldset: PMEM - name: PMEM - - byte_offset: 140 - description: 'The FMC_PATT read/write register contains the timing information - for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory - space of the NAND Flash for the last address write access if the timing must - differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: - NAND Flash prewait feature).' - fieldset: PATT - name: PATT - - access: Read - byte_offset: 148 - description: 'This register contain the current error correction code value computed - by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes - the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: - Computation of the error correction code (ECC) in NAND Flash memory), the data - read/written from/to the NAND Flash memory are processed automatically by the - ECC computation module. When X bytes have been read (according to the ECCPS - field in the FMC_PCR registers), the CPU must read the computed ECC value from - the FMC_ECC registers. It then verifies if these computed parity data are the - same as the parity value recorded in the spare area, to determine whether a - page is valid, and, to correct it otherwise. The FMC_ECCR register should be - cleared after being read by setting the ECCEN bit to 0. To compute a new data - block, the ECCEN bit must be set to 1.' - fieldset: ECCR - name: ECCR - - byte_offset: 260 - description: This register contains the control information of each memory bank. - It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is - set in the FMC_BCRx register, then this register is active for write access. - fieldset: BWTR1 - name: BWTR1 - - byte_offset: 268 - description: This register contains the control information of each memory bank. - It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is - set in the FMC_BCRx register, then this register is active for write access. - fieldset: BWTR2 - name: BWTR2 - - byte_offset: 276 - description: This register contains the control information of each memory bank. - It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is - set in the FMC_BCRx register, then this register is active for write access. - fieldset: BWTR3 - name: BWTR3 - - byte_offset: 284 - description: This register contains the control information of each memory bank. - It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is - set in the FMC_BCRx register, then this register is active for write access. - fieldset: BWTR4 - name: BWTR4 - - array: - len: 2 - stride: 4 - block: SDBANK - byte_offset: 320 - description: Cluster SDBANK%s, containing SDTR?, SDCR? - name: SDBANK - - byte_offset: 336 - description: This register contains the command issued when the SDRAM device is - accessed. This register is used to initialize the SDRAM device, and to activate - the Self-refresh and the Power-down modes. As soon as the MODE field is written, - the command will be issued only to one or to both SDRAM banks according to CTB1 - and CTB2 command bits. This register is the same for both SDRAM banks. - fieldset: SDCMR - name: SDCMR - - byte_offset: 340 - description: This register sets the refresh rate in number of SDCLK clock cycles - between the refresh cycles by configuring the Refresh Timer Count value.Examplewhere - 64 ms is the SDRAM refresh period.The refresh rate must be increased by 20 SDRAM - clock cycles (as in the above example) to obtain a safe margin if an internal - refresh request occurs when a read request has been accepted. It corresponds - to a COUNT value of 0000111000000 (448). This 13-bit field is loaded into a - timer which is decremented using the SDRAM clock. This timer generates a refresh - pulse when zero is reached. The COUNT value must be set at least to 41 SDRAM - clock cycles.As soon as the FMC_SDRTR register is programmed, the timer starts - counting. If the value programmed in the register is 0, no refresh is carried - out. This register must not be reprogrammed after the initialization procedure - to avoid modifying the refresh rate.Each time a refresh pulse is generated, - this 13-bit COUNT field is reloaded into the counter.If a memory access is in - progress, the Auto-refresh request is delayed. However, if the memory access - and Auto-refresh requests are generated simultaneously, the Auto-refresh takes - precedence. If the memory access occurs during a refresh operation, the request - is buffered to be processed when the refresh is complete.This register is common - to SDRAM bank 1 and bank 2. - fieldset: SDRTR - name: SDRTR - - access: Read - byte_offset: 344 - description: SDRAM Status register - fieldset: SDSR - name: SDSR + - name: BCR1 + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories." + byte_offset: 0 + fieldset: BCR1 + - name: BTR1 + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers)." + byte_offset: 4 + fieldset: BTR1 + - name: BCR2 + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories." + byte_offset: 8 + fieldset: BCR2 + - name: BTR2 + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers)." + byte_offset: 12 + fieldset: BTR2 + - name: BCR3 + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories." + byte_offset: 16 + fieldset: BCR3 + - name: BTR3 + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers)." + byte_offset: 20 + fieldset: BTR3 + - name: BCR4 + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories." + byte_offset: 24 + fieldset: BCR4 + - name: BTR4 + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers)." + byte_offset: 28 + fieldset: BTR4 + - name: PCR + description: NAND Flash control registers + byte_offset: 128 + fieldset: PCR + - name: SR + description: "This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty." + byte_offset: 132 + fieldset: SR + - name: PMEM + description: "The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access." + byte_offset: 136 + fieldset: PMEM + - name: PATT + description: "The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature)." + byte_offset: 140 + fieldset: PATT + - name: ECCR + description: "This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1." + byte_offset: 148 + access: Read + fieldset: ECCR + - name: BWTR1 + description: "This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access." + byte_offset: 260 + fieldset: BWTR1 + - name: BWTR2 + description: "This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access." + byte_offset: 268 + fieldset: BWTR2 + - name: BWTR3 + description: "This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access." + byte_offset: 276 + fieldset: BWTR3 + - name: BWTR4 + description: "This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access." + byte_offset: 284 + fieldset: BWTR4 + - name: SDBANK + description: "Cluster SDBANK%s, containing SDTR?, SDCR?" + array: + len: 2 + stride: 4 + byte_offset: 320 + block: SDBANK + - name: SDCMR + description: "This register contains the command issued when the SDRAM device is accessed. This register is used to initialize the SDRAM device, and to activate the Self-refresh and the Power-down modes. As soon as the MODE field is written, the command will be issued only to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register is the same for both SDRAM banks." + byte_offset: 336 + fieldset: SDCMR + - name: SDRTR + description: "This register sets the refresh rate in number of SDCLK clock cycles between the refresh cycles by configuring the Refresh Timer Count value.Examplewhere 64 ms is the SDRAM refresh period.The refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to obtain a safe margin if an internal refresh request occurs when a read request has been accepted. It corresponds to a COUNT value of 0000111000000 (448). This 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This timer generates a refresh pulse when zero is reached. The COUNT value must be set at least to 41 SDRAM clock cycles.As soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value programmed in the register is 0, no refresh is carried out. This register must not be reprogrammed after the initialization procedure to avoid modifying the refresh rate.Each time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.If a memory access is in progress, the Auto-refresh request is delayed. However, if the memory access and Auto-refresh requests are generated simultaneously, the Auto-refresh takes precedence. If the memory access occurs during a refresh operation, the request is buffered to be processed when the refresh is complete.This register is common to SDRAM bank 1 and bank 2." + byte_offset: 340 + fieldset: SDRTR + - name: SDSR + description: SDRAM Status register + byte_offset: 344 + access: Read + fieldset: SDSR block/SDBANK: - description: Cluster SDBANK%s, containing SDTR?, SDCR? + description: "Cluster SDBANK%s, containing SDTR?, SDCR?" items: - - byte_offset: 0 - description: This register contains the control parameters for each SDRAM memory - bank - fieldset: SDCR - name: SDCR - - byte_offset: 8 - description: This register contains the timing parameters of each SDRAM bank - fieldset: SDTR - name: SDTR + - name: SDCR + description: This register contains the control parameters for each SDRAM memory bank + byte_offset: 0 + fieldset: SDCR + - name: SDTR + description: This register contains the timing parameters of each SDRAM bank + byte_offset: 8 + fieldset: SDTR fieldset/BCR1: - description: This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories. + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories." fields: - - bit_offset: 0 - bit_size: 1 - description: Memory bank enable bit This bit enables the memory bank. After reset - Bank1 is enabled, all others are disabled. Accessing a disabled bank causes - an ERROR on AXI bus. - name: MBKEN - - bit_offset: 1 - bit_size: 1 - description: 'Address/data multiplexing enable bit When this bit is set, the address - and data values are multiplexed on the data bus, valid only with NOR and PSRAM - memories:' - name: MUXEN - - bit_offset: 2 - bit_size: 2 - description: 'Memory type These bits define the type of external memory attached - to the corresponding memory bank:' - name: MTYP - - bit_offset: 4 - bit_size: 2 - description: Memory data bus width Defines the external memory device width, valid - for all type of memories. - name: MWID - - bit_offset: 6 - bit_size: 1 - description: Flash access enable This bit enables NOR Flash memory access operations. - name: FACCEN - - bit_offset: 8 - bit_size: 1 - description: 'Burst enable bit This bit enables/disables synchronous accesses - during read operations. It is valid only for synchronous memories operating - in Burst mode:' - name: BURSTEN - - bit_offset: 9 - bit_size: 1 - description: 'Wait signal polarity bit This bit defines the polarity of the wait - signal from memory used for either in synchronous or asynchronous mode:' - name: WAITPOL - - bit_offset: 11 - bit_size: 1 - description: 'Wait timing configuration The NWAIT signal indicates whether the - data from the memory are valid or if a wait state must be inserted when accessing - the memory in synchronous mode. This configuration bit determines if NWAIT is - asserted by the memory one clock cycle before the wait state or during the wait - state:' - name: WAITCFG - - bit_offset: 12 - bit_size: 1 - description: 'Write enable bit This bit indicates whether write operations are - enabled/disabled in the bank by the FMC:' - name: WREN - - bit_offset: 13 - bit_size: 1 - description: Wait enable bit This bit enables/disables wait-state insertion via - the NWAIT signal when accessing the memory in synchronous mode. - name: WAITEN - - bit_offset: 14 - bit_size: 1 - description: 'Extended mode enable. This bit enables the FMC to program the write - timings for asynchronous accesses inside the FMC_BWTR register, thus resulting - in different timings for read and write operations. Note: When the extended - mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode - 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 - or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected - (MTYP = 0x10).' - name: EXTMOD - - bit_offset: 15 - bit_size: 1 - description: Wait signal during asynchronous transfers This bit enables/disables - the FMC to use the wait signal even during an asynchronous protocol. - name: ASYNCWAIT - - bit_offset: 16 - bit_size: 3 - description: 'CRAM Page Size These are used for Cellular RAM 1.5 which does not - allow burst access to cross the address boundaries between pages. When these - bits are configured, the FMC controller splits automatically the burst access - when the memory page size is reached (refer to memory datasheet for page size). - Other configuration: reserved.' - name: CPSIZE - - bit_offset: 19 - bit_size: 1 - description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the - bit enables synchronous accesses during write operations. The enable bit for - synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. - name: CBURSTRW - - bit_offset: 20 - bit_size: 1 - description: 'Continuous Clock Enable This bit enables the FMC_CLK clock output - to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers - is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must - be configured in synchronous mode to generate the FMC_CLK continuous clock. - If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in - the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous - mode is used and CCLKEN bit is set, the synchronous memories connected to other - banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 - and FMC_BWTR2..4 registers for other banks has no effect.)' - name: CCLKEN - - bit_offset: 21 - bit_size: 1 - description: 'Write FIFO Disable This bit disables the Write FIFO used by the - FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. - It is only enabled through the FMC_BCR1 register.' - name: WFDIS - - bit_offset: 24 - bit_size: 2 - description: 'FMC bank mapping These bits allows different to remap SDRAM bank2 - or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP - bits of the FMC_BCR2..4 registers are dont care. It is only enabled through - the FMC_BCR1 register.' - name: BMAP - - bit_offset: 31 - bit_size: 1 - description: 'FMC controller Enable This bit enables/disables the FMC controller. - Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled - through the FMC_BCR1 register.' - name: FMCEN + - name: MBKEN + description: "Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus." + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: "Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:" + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: "Memory type These bits define the type of external memory attached to the corresponding memory bank:" + bit_offset: 2 + bit_size: 2 + - name: MWID + description: "Memory data bus width Defines the external memory device width, valid for all type of memories." + bit_offset: 4 + bit_size: 2 + - name: FACCEN + description: Flash access enable This bit enables NOR Flash memory access operations. + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: "Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:" + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: "Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:" + bit_offset: 9 + bit_size: 1 + - name: WAITCFG + description: "Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:" + bit_offset: 11 + bit_size: 1 + - name: WREN + description: "Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:" + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: "Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)." + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: "CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved." + bit_offset: 16 + bit_size: 3 + - name: CBURSTRW + description: "Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register." + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: "Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)" + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: "Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." + bit_offset: 21 + bit_size: 1 + - name: BMAP + description: "FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register." + bit_offset: 24 + bit_size: 2 + - name: FMCEN + description: "FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." + bit_offset: 31 + bit_size: 1 fieldset/BCR2: - description: This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories. + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories." fields: - - bit_offset: 0 - bit_size: 1 - description: Memory bank enable bit This bit enables the memory bank. After reset - Bank1 is enabled, all others are disabled. Accessing a disabled bank causes - an ERROR on AXI bus. - name: MBKEN - - bit_offset: 1 - bit_size: 1 - description: 'Address/data multiplexing enable bit When this bit is set, the address - and data values are multiplexed on the data bus, valid only with NOR and PSRAM - memories:' - name: MUXEN - - bit_offset: 2 - bit_size: 2 - description: 'Memory type These bits define the type of external memory attached - to the corresponding memory bank:' - name: MTYP - - bit_offset: 4 - bit_size: 2 - description: Memory data bus width Defines the external memory device width, valid - for all type of memories. - name: MWID - - bit_offset: 6 - bit_size: 1 - description: Flash access enable This bit enables NOR Flash memory access operations. - name: FACCEN - - bit_offset: 8 - bit_size: 1 - description: 'Burst enable bit This bit enables/disables synchronous accesses - during read operations. It is valid only for synchronous memories operating - in Burst mode:' - name: BURSTEN - - bit_offset: 9 - bit_size: 1 - description: 'Wait signal polarity bit This bit defines the polarity of the wait - signal from memory used for either in synchronous or asynchronous mode:' - name: WAITPOL - - bit_offset: 11 - bit_size: 1 - description: 'Wait timing configuration The NWAIT signal indicates whether the - data from the memory are valid or if a wait state must be inserted when accessing - the memory in synchronous mode. This configuration bit determines if NWAIT is - asserted by the memory one clock cycle before the wait state or during the wait - state:' - name: WAITCFG - - bit_offset: 12 - bit_size: 1 - description: 'Write enable bit This bit indicates whether write operations are - enabled/disabled in the bank by the FMC:' - name: WREN - - bit_offset: 13 - bit_size: 1 - description: Wait enable bit This bit enables/disables wait-state insertion via - the NWAIT signal when accessing the memory in synchronous mode. - name: WAITEN - - bit_offset: 14 - bit_size: 1 - description: 'Extended mode enable. This bit enables the FMC to program the write - timings for asynchronous accesses inside the FMC_BWTR register, thus resulting - in different timings for read and write operations. Note: When the extended - mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode - 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 - or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected - (MTYP = 0x10).' - name: EXTMOD - - bit_offset: 15 - bit_size: 1 - description: Wait signal during asynchronous transfers This bit enables/disables - the FMC to use the wait signal even during an asynchronous protocol. - name: ASYNCWAIT - - bit_offset: 16 - bit_size: 3 - description: 'CRAM Page Size These are used for Cellular RAM 1.5 which does not - allow burst access to cross the address boundaries between pages. When these - bits are configured, the FMC controller splits automatically the burst access - when the memory page size is reached (refer to memory datasheet for page size). - Other configuration: reserved.' - name: CPSIZE - - bit_offset: 19 - bit_size: 1 - description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the - bit enables synchronous accesses during write operations. The enable bit for - synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. - name: CBURSTRW - - bit_offset: 20 - bit_size: 1 - description: 'Continuous Clock Enable This bit enables the FMC_CLK clock output - to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers - is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must - be configured in synchronous mode to generate the FMC_CLK continuous clock. - If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in - the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous - mode is used and CCLKEN bit is set, the synchronous memories connected to other - banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 - and FMC_BWTR2..4 registers for other banks has no effect.)' - name: CCLKEN - - bit_offset: 21 - bit_size: 1 - description: 'Write FIFO Disable This bit disables the Write FIFO used by the - FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. - It is only enabled through the FMC_BCR1 register.' - name: WFDIS - - bit_offset: 24 - bit_size: 2 - description: 'FMC bank mapping These bits allows different to remap SDRAM bank2 - or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP - bits of the FMC_BCR2..4 registers are dont care. It is only enabled through - the FMC_BCR1 register.' - name: BMAP - - bit_offset: 31 - bit_size: 1 - description: 'FMC controller Enable This bit enables/disables the FMC controller. - Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled - through the FMC_BCR1 register.' - name: FMCEN + - name: MBKEN + description: "Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus." + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: "Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:" + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: "Memory type These bits define the type of external memory attached to the corresponding memory bank:" + bit_offset: 2 + bit_size: 2 + - name: MWID + description: "Memory data bus width Defines the external memory device width, valid for all type of memories." + bit_offset: 4 + bit_size: 2 + - name: FACCEN + description: Flash access enable This bit enables NOR Flash memory access operations. + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: "Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:" + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: "Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:" + bit_offset: 9 + bit_size: 1 + - name: WAITCFG + description: "Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:" + bit_offset: 11 + bit_size: 1 + - name: WREN + description: "Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:" + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: "Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)." + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: "CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved." + bit_offset: 16 + bit_size: 3 + - name: CBURSTRW + description: "Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register." + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: "Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)" + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: "Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." + bit_offset: 21 + bit_size: 1 + - name: BMAP + description: "FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register." + bit_offset: 24 + bit_size: 2 + - name: FMCEN + description: "FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." + bit_offset: 31 + bit_size: 1 fieldset/BCR3: - description: This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories. + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories." fields: - - bit_offset: 0 - bit_size: 1 - description: Memory bank enable bit This bit enables the memory bank. After reset - Bank1 is enabled, all others are disabled. Accessing a disabled bank causes - an ERROR on AXI bus. - name: MBKEN - - bit_offset: 1 - bit_size: 1 - description: 'Address/data multiplexing enable bit When this bit is set, the address - and data values are multiplexed on the data bus, valid only with NOR and PSRAM - memories:' - name: MUXEN - - bit_offset: 2 - bit_size: 2 - description: 'Memory type These bits define the type of external memory attached - to the corresponding memory bank:' - name: MTYP - - bit_offset: 4 - bit_size: 2 - description: Memory data bus width Defines the external memory device width, valid - for all type of memories. - name: MWID - - bit_offset: 6 - bit_size: 1 - description: Flash access enable This bit enables NOR Flash memory access operations. - name: FACCEN - - bit_offset: 8 - bit_size: 1 - description: 'Burst enable bit This bit enables/disables synchronous accesses - during read operations. It is valid only for synchronous memories operating - in Burst mode:' - name: BURSTEN - - bit_offset: 9 - bit_size: 1 - description: 'Wait signal polarity bit This bit defines the polarity of the wait - signal from memory used for either in synchronous or asynchronous mode:' - name: WAITPOL - - bit_offset: 11 - bit_size: 1 - description: 'Wait timing configuration The NWAIT signal indicates whether the - data from the memory are valid or if a wait state must be inserted when accessing - the memory in synchronous mode. This configuration bit determines if NWAIT is - asserted by the memory one clock cycle before the wait state or during the wait - state:' - name: WAITCFG - - bit_offset: 12 - bit_size: 1 - description: 'Write enable bit This bit indicates whether write operations are - enabled/disabled in the bank by the FMC:' - name: WREN - - bit_offset: 13 - bit_size: 1 - description: Wait enable bit This bit enables/disables wait-state insertion via - the NWAIT signal when accessing the memory in synchronous mode. - name: WAITEN - - bit_offset: 14 - bit_size: 1 - description: 'Extended mode enable. This bit enables the FMC to program the write - timings for asynchronous accesses inside the FMC_BWTR register, thus resulting - in different timings for read and write operations. Note: When the extended - mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode - 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 - or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected - (MTYP = 0x10).' - name: EXTMOD - - bit_offset: 15 - bit_size: 1 - description: Wait signal during asynchronous transfers This bit enables/disables - the FMC to use the wait signal even during an asynchronous protocol. - name: ASYNCWAIT - - bit_offset: 16 - bit_size: 3 - description: 'CRAM Page Size These are used for Cellular RAM 1.5 which does not - allow burst access to cross the address boundaries between pages. When these - bits are configured, the FMC controller splits automatically the burst access - when the memory page size is reached (refer to memory datasheet for page size). - Other configuration: reserved.' - name: CPSIZE - - bit_offset: 19 - bit_size: 1 - description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the - bit enables synchronous accesses during write operations. The enable bit for - synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. - name: CBURSTRW - - bit_offset: 20 - bit_size: 1 - description: 'Continuous Clock Enable This bit enables the FMC_CLK clock output - to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers - is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must - be configured in synchronous mode to generate the FMC_CLK continuous clock. - If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in - the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous - mode is used and CCLKEN bit is set, the synchronous memories connected to other - banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 - and FMC_BWTR2..4 registers for other banks has no effect.)' - name: CCLKEN - - bit_offset: 21 - bit_size: 1 - description: 'Write FIFO Disable This bit disables the Write FIFO used by the - FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. - It is only enabled through the FMC_BCR1 register.' - name: WFDIS - - bit_offset: 24 - bit_size: 2 - description: 'FMC bank mapping These bits allows different to remap SDRAM bank2 - or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP - bits of the FMC_BCR2..4 registers are dont care. It is only enabled through - the FMC_BCR1 register.' - name: BMAP - - bit_offset: 31 - bit_size: 1 - description: 'FMC controller Enable This bit enables/disables the FMC controller. - Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled - through the FMC_BCR1 register.' - name: FMCEN + - name: MBKEN + description: "Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus." + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: "Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:" + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: "Memory type These bits define the type of external memory attached to the corresponding memory bank:" + bit_offset: 2 + bit_size: 2 + - name: MWID + description: "Memory data bus width Defines the external memory device width, valid for all type of memories." + bit_offset: 4 + bit_size: 2 + - name: FACCEN + description: Flash access enable This bit enables NOR Flash memory access operations. + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: "Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:" + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: "Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:" + bit_offset: 9 + bit_size: 1 + - name: WAITCFG + description: "Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:" + bit_offset: 11 + bit_size: 1 + - name: WREN + description: "Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:" + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: "Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)." + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: "CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved." + bit_offset: 16 + bit_size: 3 + - name: CBURSTRW + description: "Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register." + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: "Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)" + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: "Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." + bit_offset: 21 + bit_size: 1 + - name: BMAP + description: "FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register." + bit_offset: 24 + bit_size: 2 + - name: FMCEN + description: "FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." + bit_offset: 31 + bit_size: 1 fieldset/BCR4: - description: This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories. + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories." fields: - - bit_offset: 0 - bit_size: 1 - description: Memory bank enable bit This bit enables the memory bank. After reset - Bank1 is enabled, all others are disabled. Accessing a disabled bank causes - an ERROR on AXI bus. - name: MBKEN - - bit_offset: 1 - bit_size: 1 - description: 'Address/data multiplexing enable bit When this bit is set, the address - and data values are multiplexed on the data bus, valid only with NOR and PSRAM - memories:' - name: MUXEN - - bit_offset: 2 - bit_size: 2 - description: 'Memory type These bits define the type of external memory attached - to the corresponding memory bank:' - name: MTYP - - bit_offset: 4 - bit_size: 2 - description: Memory data bus width Defines the external memory device width, valid - for all type of memories. - name: MWID - - bit_offset: 6 - bit_size: 1 - description: Flash access enable This bit enables NOR Flash memory access operations. - name: FACCEN - - bit_offset: 8 - bit_size: 1 - description: 'Burst enable bit This bit enables/disables synchronous accesses - during read operations. It is valid only for synchronous memories operating - in Burst mode:' - name: BURSTEN - - bit_offset: 9 - bit_size: 1 - description: 'Wait signal polarity bit This bit defines the polarity of the wait - signal from memory used for either in synchronous or asynchronous mode:' - name: WAITPOL - - bit_offset: 11 - bit_size: 1 - description: 'Wait timing configuration The NWAIT signal indicates whether the - data from the memory are valid or if a wait state must be inserted when accessing - the memory in synchronous mode. This configuration bit determines if NWAIT is - asserted by the memory one clock cycle before the wait state or during the wait - state:' - name: WAITCFG - - bit_offset: 12 - bit_size: 1 - description: 'Write enable bit This bit indicates whether write operations are - enabled/disabled in the bank by the FMC:' - name: WREN - - bit_offset: 13 - bit_size: 1 - description: Wait enable bit This bit enables/disables wait-state insertion via - the NWAIT signal when accessing the memory in synchronous mode. - name: WAITEN - - bit_offset: 14 - bit_size: 1 - description: 'Extended mode enable. This bit enables the FMC to program the write - timings for asynchronous accesses inside the FMC_BWTR register, thus resulting - in different timings for read and write operations. Note: When the extended - mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode - 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 - or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected - (MTYP = 0x10).' - name: EXTMOD - - bit_offset: 15 - bit_size: 1 - description: Wait signal during asynchronous transfers This bit enables/disables - the FMC to use the wait signal even during an asynchronous protocol. - name: ASYNCWAIT - - bit_offset: 16 - bit_size: 3 - description: 'CRAM Page Size These are used for Cellular RAM 1.5 which does not - allow burst access to cross the address boundaries between pages. When these - bits are configured, the FMC controller splits automatically the burst access - when the memory page size is reached (refer to memory datasheet for page size). - Other configuration: reserved.' - name: CPSIZE - - bit_offset: 19 - bit_size: 1 - description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the - bit enables synchronous accesses during write operations. The enable bit for - synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. - name: CBURSTRW - - bit_offset: 20 - bit_size: 1 - description: 'Continuous Clock Enable This bit enables the FMC_CLK clock output - to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers - is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must - be configured in synchronous mode to generate the FMC_CLK continuous clock. - If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in - the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous - mode is used and CCLKEN bit is set, the synchronous memories connected to other - banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 - and FMC_BWTR2..4 registers for other banks has no effect.)' - name: CCLKEN - - bit_offset: 21 - bit_size: 1 - description: 'Write FIFO Disable This bit disables the Write FIFO used by the - FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. - It is only enabled through the FMC_BCR1 register.' - name: WFDIS - - bit_offset: 24 - bit_size: 2 - description: 'FMC bank mapping These bits allows different to remap SDRAM bank2 - or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP - bits of the FMC_BCR2..4 registers are dont care. It is only enabled through - the FMC_BCR1 register.' - name: BMAP - - bit_offset: 31 - bit_size: 1 - description: 'FMC controller Enable This bit enables/disables the FMC controller. - Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled - through the FMC_BCR1 register.' - name: FMCEN + - name: MBKEN + description: "Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus." + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: "Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:" + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: "Memory type These bits define the type of external memory attached to the corresponding memory bank:" + bit_offset: 2 + bit_size: 2 + - name: MWID + description: "Memory data bus width Defines the external memory device width, valid for all type of memories." + bit_offset: 4 + bit_size: 2 + - name: FACCEN + description: Flash access enable This bit enables NOR Flash memory access operations. + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: "Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:" + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: "Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:" + bit_offset: 9 + bit_size: 1 + - name: WAITCFG + description: "Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:" + bit_offset: 11 + bit_size: 1 + - name: WREN + description: "Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:" + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: "Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)." + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: "CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved." + bit_offset: 16 + bit_size: 3 + - name: CBURSTRW + description: "Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register." + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: "Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)" + bit_offset: 20 + bit_size: 1 + - name: WFDIS + description: "Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." + bit_offset: 21 + bit_size: 1 + - name: BMAP + description: "FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register." + bit_offset: 24 + bit_size: 2 + - name: FMCEN + description: "FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." + bit_offset: 31 + bit_size: 1 fieldset/BTR1: - description: 'This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx - register, then this register is partitioned for write and read access, that is, - 2 registers are available: one to configure read accesses (this register) and - one to configure write accesses (FMC_BWTRx registers).' + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers)." fields: - - bit_offset: 0 - bit_size: 4 - description: 'Address setup phase duration These bits are written by software - to define the duration of the address setup phase (refer to Figure81 to Figure93), - used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address - setup phase duration, please refer to the respective figure (refer to Figure81 - to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed - mode or Mode D, the minimum value for ADDSET is 1.' - name: ADDSET - - bit_offset: 4 - bit_size: 4 - description: 'Address-hold phase duration These bits are written by software to - define the duration of the address hold phase (refer to Figure81 to Figure93), - used in mode D or multiplexed accesses: For each access mode address-hold phase - duration, please refer to the respective figure (Figure81 to Figure93). Note: - In synchronous accesses, this value is not used, the address hold phase is always - 1 memory clock period duration.' - name: ADDHLD - - bit_offset: 8 - bit_size: 8 - description: 'Data-phase duration These bits are written by software to define - the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous - accesses: For each memory type and access mode data-phase duration, please refer - to the respective figure (Figure81 to Figure93). Example: Mode1, write access, - DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous - accesses, this value is dont care.' - name: DATAST - - bit_offset: 16 - bit_size: 4 - description: 'Bus turnaround phase duration These bits are written by software - to add a delay at the end of a write-to-read or read-to write transaction. The - programmed bus turnaround delay is inserted between an asynchronous read (in - muxed or mode D) or write transaction and any other asynchronous /synchronous - read/write from/to a static bank. If a read operation is performed, the bank - can be the same or a different one, whereas it must be different in case of - write operation to the bank, except in muxed mode or mode D. In some cases, - whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as - follows: The bus turnaround delay is not inserted between two consecutive asynchronous - write transfers to the same static memory bank except in muxed mode and mode - D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive - asynchronous read transfers to the same static memory bank except for modes - muxed and D. An asynchronous read to an asynchronous or synchronous write to - any static bank or dynamic bank except in modes muxed and D mode. There is a - bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous - write operations (in Burst or Single mode) to the same bank. A synchronous write - (burst or single) access and an asynchronous write or read transfer to or from - static memory bank (the bank can be the same or a different one in case of a - read operation. Two consecutive synchronous read operations (in Burst or Single - mode) followed by any synchronous/asynchronous read or write from/to another - static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: - Two consecutive synchronous write operations (in Burst or Single mode) to different - static banks. A synchronous write access (in Burst or Single mode) and a synchronous - read from the same or a different bank. The bus turnaround delay allows to match - the minimum time between consecutive transactions (tEHEL from NEx high to NEx - low) and the maximum time required by the memory to free the data bus after - a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN - + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period - ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ...' - name: BUSTURN - - bit_offset: 20 - bit_size: 4 - description: 'Clock divide ratio (for FMC_CLK signal) These bits define the period - of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous - NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: - Synchronous transactions for FMC_CLK divider ratio formula)' - name: CLKDIV - - bit_offset: 24 - bit_size: 4 - description: Data latency for synchronous memory For synchronous access with read - write burst mode enabled these bits define the number of memory clock cycles - name: DATLAT - - bit_offset: 28 - bit_size: 2 - description: Access mode These bits specify the asynchronous access modes as shown - in the timing diagrams. They are taken into account only when the EXTMOD bit - in the FMC_BCRx register is 1. - name: ACCMOD + - name: ADDSET + description: "Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1." + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: "Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration." + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: "Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care." + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: "Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ..." + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: "Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula)" + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 fieldset/BTR2: - description: 'This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx - register, then this register is partitioned for write and read access, that is, - 2 registers are available: one to configure read accesses (this register) and - one to configure write accesses (FMC_BWTRx registers).' + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers)." fields: - - bit_offset: 0 - bit_size: 4 - description: 'Address setup phase duration These bits are written by software - to define the duration of the address setup phase (refer to Figure81 to Figure93), - used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address - setup phase duration, please refer to the respective figure (refer to Figure81 - to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed - mode or Mode D, the minimum value for ADDSET is 1.' - name: ADDSET - - bit_offset: 4 - bit_size: 4 - description: 'Address-hold phase duration These bits are written by software to - define the duration of the address hold phase (refer to Figure81 to Figure93), - used in mode D or multiplexed accesses: For each access mode address-hold phase - duration, please refer to the respective figure (Figure81 to Figure93). Note: - In synchronous accesses, this value is not used, the address hold phase is always - 1 memory clock period duration.' - name: ADDHLD - - bit_offset: 8 - bit_size: 8 - description: 'Data-phase duration These bits are written by software to define - the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous - accesses: For each memory type and access mode data-phase duration, please refer - to the respective figure (Figure81 to Figure93). Example: Mode1, write access, - DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous - accesses, this value is dont care.' - name: DATAST - - bit_offset: 16 - bit_size: 4 - description: 'Bus turnaround phase duration These bits are written by software - to add a delay at the end of a write-to-read or read-to write transaction. The - programmed bus turnaround delay is inserted between an asynchronous read (in - muxed or mode D) or write transaction and any other asynchronous /synchronous - read/write from/to a static bank. If a read operation is performed, the bank - can be the same or a different one, whereas it must be different in case of - write operation to the bank, except in muxed mode or mode D. In some cases, - whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as - follows: The bus turnaround delay is not inserted between two consecutive asynchronous - write transfers to the same static memory bank except in muxed mode and mode - D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive - asynchronous read transfers to the same static memory bank except for modes - muxed and D. An asynchronous read to an asynchronous or synchronous write to - any static bank or dynamic bank except in modes muxed and D mode. There is a - bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous - write operations (in Burst or Single mode) to the same bank. A synchronous write - (burst or single) access and an asynchronous write or read transfer to or from - static memory bank (the bank can be the same or a different one in case of a - read operation. Two consecutive synchronous read operations (in Burst or Single - mode) followed by any synchronous/asynchronous read or write from/to another - static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: - Two consecutive synchronous write operations (in Burst or Single mode) to different - static banks. A synchronous write access (in Burst or Single mode) and a synchronous - read from the same or a different bank. The bus turnaround delay allows to match - the minimum time between consecutive transactions (tEHEL from NEx high to NEx - low) and the maximum time required by the memory to free the data bus after - a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN - + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period - ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 1. ...' - name: BUSTURN - - bit_offset: 20 - bit_size: 4 - description: 'Clock divide ratio (for FMC_CLK signal) These bits define the period - of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous - NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: - Synchronous transactions for FMC_CLK divider ratio formula)' - name: CLKDIV - - bit_offset: 24 - bit_size: 4 - description: Data latency for synchronous memory For synchronous access with read - write burst mode enabled these bits define the number of memory clock cycles - name: DATLAT - - bit_offset: 28 - bit_size: 2 - description: Access mode These bits specify the asynchronous access modes as shown - in the timing diagrams. They are taken into account only when the EXTMOD bit - in the FMC_BCRx register is 1. - name: ACCMOD + - name: ADDSET + description: "Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1." + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: "Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration." + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: "Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care." + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: "Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 1. ..." + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: "Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula)" + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 fieldset/BTR3: - description: 'This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx - register, then this register is partitioned for write and read access, that is, - 2 registers are available: one to configure read accesses (this register) and - one to configure write accesses (FMC_BWTRx registers).' + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers)." fields: - - bit_offset: 0 - bit_size: 4 - description: 'Address setup phase duration These bits are written by software - to define the duration of the address setup phase (refer to Figure81 to Figure93), - used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address - setup phase duration, please refer to the respective figure (refer to Figure81 - to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed - mode or Mode D, the minimum value for ADDSET is 1.' - name: ADDSET - - bit_offset: 4 - bit_size: 4 - description: 'Address-hold phase duration These bits are written by software to - define the duration of the address hold phase (refer to Figure81 to Figure93), - used in mode D or multiplexed accesses: For each access mode address-hold phase - duration, please refer to the respective figure (Figure81 to Figure93). Note: - In synchronous accesses, this value is not used, the address hold phase is always - 1 memory clock period duration.' - name: ADDHLD - - bit_offset: 8 - bit_size: 8 - description: 'Data-phase duration These bits are written by software to define - the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous - accesses: For each memory type and access mode data-phase duration, please refer - to the respective figure (Figure81 to Figure93). Example: Mode1, write access, - DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous - accesses, this value is dont care.' - name: DATAST - - bit_offset: 16 - bit_size: 4 - description: 'Bus turnaround phase duration These bits are written by software - to add a delay at the end of a write-to-read or read-to write transaction. The - programmed bus turnaround delay is inserted between an asynchronous read (in - muxed or mode D) or write transaction and any other asynchronous /synchronous - read/write from/to a static bank. If a read operation is performed, the bank - can be the same or a different one, whereas it must be different in case of - write operation to the bank, except in muxed mode or mode D. In some cases, - whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as - follows: The bus turnaround delay is not inserted between two consecutive asynchronous - write transfers to the same static memory bank except in muxed mode and mode - D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive - asynchronous read transfers to the same static memory bank except for modes - muxed and D. An asynchronous read to an asynchronous or synchronous write to - any static bank or dynamic bank except in modes muxed and D mode. There is a - bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous - write operations (in Burst or Single mode) to the same bank. A synchronous write - (burst or single) access and an asynchronous write or read transfer to or from - static memory bank (the bank can be the same or a different one in case of a - read operation. Two consecutive synchronous read operations (in Burst or Single - mode) followed by any synchronous/asynchronous read or write from/to another - static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: - Two consecutive synchronous write operations (in Burst or Single mode) to different - static banks. A synchronous write access (in Burst or Single mode) and a synchronous - read from the same or a different bank. The bus turnaround delay allows to match - the minimum time between consecutive transactions (tEHEL from NEx high to NEx - low) and the maximum time required by the memory to free the data bus after - a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN - + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period - ≥ max (tEHELmin, tEHQZmax) if EXTMOD =1. ...' - name: BUSTURN - - bit_offset: 20 - bit_size: 4 - description: 'Clock divide ratio (for FMC_CLK signal) These bits define the period - of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous - NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: - Synchronous transactions for FMC_CLK divider ratio formula)' - name: CLKDIV - - bit_offset: 24 - bit_size: 4 - description: Data latency for synchronous memory For synchronous access with read - write burst mode enabled these bits define the number of memory clock cycles - name: DATLAT - - bit_offset: 28 - bit_size: 2 - description: Access mode These bits specify the asynchronous access modes as shown - in the timing diagrams. They are taken into account only when the EXTMOD bit - in the FMC_BCRx register is 1. - name: ACCMOD + - name: ADDSET + description: "Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1." + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: "Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration." + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: "Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care." + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: "Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD =1. ..." + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: "Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula)" + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 fieldset/BTR4: - description: 'This register contains the control information of each memory bank, - used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx - register, then this register is partitioned for write and read access, that is, - 2 registers are available: one to configure read accesses (this register) and - one to configure write accesses (FMC_BWTRx registers).' + description: "This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers)." fields: - - bit_offset: 0 - bit_size: 4 - description: 'Address setup phase duration These bits are written by software - to define the duration of the address setup phase (refer to Figure81 to Figure93), - used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address - setup phase duration, please refer to the respective figure (refer to Figure81 - to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed - mode or Mode D, the minimum value for ADDSET is 1.' - name: ADDSET - - bit_offset: 4 - bit_size: 4 - description: 'Address-hold phase duration These bits are written by software to - define the duration of the address hold phase (refer to Figure81 to Figure93), - used in mode D or multiplexed accesses: For each access mode address-hold phase - duration, please refer to the respective figure (Figure81 to Figure93). Note: - In synchronous accesses, this value is not used, the address hold phase is always - 1 memory clock period duration.' - name: ADDHLD - - bit_offset: 8 - bit_size: 8 - description: 'Data-phase duration These bits are written by software to define - the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous - accesses: For each memory type and access mode data-phase duration, please refer - to the respective figure (Figure81 to Figure93). Example: Mode1, write access, - DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous - accesses, this value is dont care.' - name: DATAST - - bit_offset: 16 - bit_size: 4 - description: 'Bus turnaround phase duration These bits are written by software - to add a delay at the end of a write-to-read or read-to write transaction. The - programmed bus turnaround delay is inserted between an asynchronous read (in - muxed or mode D) or write transaction and any other asynchronous /synchronous - read/write from/to a static bank. If a read operation is performed, the bank - can be the same or a different one, whereas it must be different in case of - write operation to the bank, except in muxed mode or mode D. In some cases, - whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as - follows: The bus turnaround delay is not inserted between two consecutive asynchronous - write transfers to the same static memory bank except in muxed mode and mode - D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive - asynchronous read transfers to the same static memory bank except for modes - muxed and D. An asynchronous read to an asynchronous or synchronous write to - any static bank or dynamic bank except in modes muxed and D mode. There is a - bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous - write operations (in Burst or Single mode) to the same bank. A synchronous write - (burst or single) access and an asynchronous write or read transfer to or from - static memory bank (the bank can be the same or a different one in case of a - read operation. Two consecutive synchronous read operations (in Burst or Single - mode) followed by any synchronous/asynchronous read or write from/to another - static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: - Two consecutive synchronous write operations (in Burst or Single mode) to different - static banks. A synchronous write access (in Burst or Single mode) and a synchronous - read from the same or a different bank. The bus turnaround delay allows to match - the minimum time between consecutive transactions (tEHEL from NEx high to NEx - low) and the maximum time required by the memory to free the data bus after - a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN - + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period - ≥ max (tEHELmin, tEHQZmax) if EXTMOD =1. ...' - name: BUSTURN - - bit_offset: 20 - bit_size: 4 - description: 'Clock divide ratio (for FMC_CLK signal) These bits define the period - of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous - NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: - Synchronous transactions for FMC_CLK divider ratio formula)' - name: CLKDIV - - bit_offset: 24 - bit_size: 4 - description: Data latency for synchronous memory For synchronous access with read - write burst mode enabled these bits define the number of memory clock cycles - name: DATLAT - - bit_offset: 28 - bit_size: 2 - description: Access mode These bits specify the asynchronous access modes as shown - in the timing diagrams. They are taken into account only when the EXTMOD bit - in the FMC_BCRx register is 1. - name: ACCMOD + - name: ADDSET + description: "Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1." + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: "Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration." + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: "Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care." + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: "Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD =1. ..." + bit_offset: 16 + bit_size: 4 + - name: CLKDIV + description: "Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula)" + bit_offset: 20 + bit_size: 4 + - name: DATLAT + description: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles + bit_offset: 24 + bit_size: 4 + - name: ACCMOD + description: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 fieldset/BWTR1: - description: This register contains the control information of each memory bank. - It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set - in the FMC_BCRx register, then this register is active for write access. + description: "This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access." fields: - - bit_offset: 0 - bit_size: 4 - description: 'Address setup phase duration. These bits are written by software - to define the duration of the address setup phase in KCK_FMC cycles (refer to - Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous - accesses, this value is not used, the address setup phase is always 1 Flash - clock period duration. In muxed mode, the minimum ADDSET value is 1.' - name: ADDSET - - bit_offset: 4 - bit_size: 4 - description: 'Address-hold phase duration. These bits are written by software - to define the duration of the address hold phase (refer to Figure81 to Figure93), - used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash - accesses, this value is not used, the address hold phase is always 1 Flash clock - period duration.' - name: ADDHLD - - bit_offset: 8 - bit_size: 8 - description: 'Data-phase duration. These bits are written by software to define - the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous - SRAM, PSRAM and NOR Flash memory accesses:' - name: DATAST - - bit_offset: 16 - bit_size: 4 - description: 'Bus turnaround phase duration These bits are written by software - to add a delay at the end of a write transaction to match the minimum time between - consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC - period ≥ tEHELmin. The programmed bus turnaround delay is inserted between - a an asynchronous write transfer and any other asynchronous /synchronous read - or write transfer to or from a static bank. If a read operation is performed, - the bank can be the same or a different one, whereas it must be different in - case of write operation to the bank, except in muxed mode or mode D. In some - cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed - as follows: The bus turnaround delay is not inserted between two consecutive - asynchronous write transfers to the same static memory bank except for muxed - mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: - Two consecutive synchronous write operations (in Burst or Single mode) to the - same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous - write or read transfer to or from static memory bank. There is a bus turnaround - delay of 3 FMC clock cycle between: Two consecutive synchronous write operations - (in Burst or Single mode) to different static banks. A synchronous write transfer - (in Burst or Single mode) and a synchronous read from the same or a different - bank. ...' - name: BUSTURN - - bit_offset: 28 - bit_size: 2 - description: Access mode. These bits specify the asynchronous access modes as - shown in the next timing diagrams.These bits are taken into account only when - the EXTMOD bit in the FMC_BCRx register is 1. - name: ACCMOD + - name: ADDSET + description: "Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1." + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: "Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration." + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: "Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:" + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: "Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ..." + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 fieldset/BWTR2: - description: This register contains the control information of each memory bank. - It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set - in the FMC_BCRx register, then this register is active for write access. + description: "This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access." fields: - - bit_offset: 0 - bit_size: 4 - description: 'Address setup phase duration. These bits are written by software - to define the duration of the address setup phase in KCK_FMC cycles (refer to - Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous - accesses, this value is not used, the address setup phase is always 1 Flash - clock period duration. In muxed mode, the minimum ADDSET value is 1.' - name: ADDSET - - bit_offset: 4 - bit_size: 4 - description: 'Address-hold phase duration. These bits are written by software - to define the duration of the address hold phase (refer to Figure81 to Figure93), - used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash - accesses, this value is not used, the address hold phase is always 1 Flash clock - period duration.' - name: ADDHLD - - bit_offset: 8 - bit_size: 8 - description: 'Data-phase duration. These bits are written by software to define - the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous - SRAM, PSRAM and NOR Flash memory accesses:' - name: DATAST - - bit_offset: 16 - bit_size: 4 - description: 'Bus turnaround phase duration These bits are written by software - to add a delay at the end of a write transaction to match the minimum time between - consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC - period ≥ tEHELmin. The programmed bus turnaround delay is inserted between - a an asynchronous write transfer and any other asynchronous /synchronous read - or write transfer to or from a static bank. If a read operation is performed, - the bank can be the same or a different one, whereas it must be different in - case of write operation to the bank, except in muxed mode or mode D. In some - cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed - as follows: The bus turnaround delay is not inserted between two consecutive - asynchronous write transfers to the same static memory bank except for muxed - mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: - Two consecutive synchronous write operations (in Burst or Single mode) to the - same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous - write or read transfer to or from static memory bank. There is a bus turnaround - delay of 3 FMC clock cycle between: Two consecutive synchronous write operations - (in Burst or Single mode) to different static banks. A synchronous write transfer - (in Burst or Single mode) and a synchronous read from the same or a different - bank. ...' - name: BUSTURN - - bit_offset: 28 - bit_size: 2 - description: Access mode. These bits specify the asynchronous access modes as - shown in the next timing diagrams.These bits are taken into account only when - the EXTMOD bit in the FMC_BCRx register is 1. - name: ACCMOD + - name: ADDSET + description: "Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1." + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: "Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration." + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: "Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:" + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: "Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ..." + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 fieldset/BWTR3: - description: This register contains the control information of each memory bank. - It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set - in the FMC_BCRx register, then this register is active for write access. + description: "This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access." fields: - - bit_offset: 0 - bit_size: 4 - description: 'Address setup phase duration. These bits are written by software - to define the duration of the address setup phase in KCK_FMC cycles (refer to - Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous - accesses, this value is not used, the address setup phase is always 1 Flash - clock period duration. In muxed mode, the minimum ADDSET value is 1.' - name: ADDSET - - bit_offset: 4 - bit_size: 4 - description: 'Address-hold phase duration. These bits are written by software - to define the duration of the address hold phase (refer to Figure81 to Figure93), - used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash - accesses, this value is not used, the address hold phase is always 1 Flash clock - period duration.' - name: ADDHLD - - bit_offset: 8 - bit_size: 8 - description: 'Data-phase duration. These bits are written by software to define - the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous - SRAM, PSRAM and NOR Flash memory accesses:' - name: DATAST - - bit_offset: 16 - bit_size: 4 - description: 'Bus turnaround phase duration These bits are written by software - to add a delay at the end of a write transaction to match the minimum time between - consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC - period ≥ tEHELmin. The programmed bus turnaround delay is inserted between - a an asynchronous write transfer and any other asynchronous /synchronous read - or write transfer to or from a static bank. If a read operation is performed, - the bank can be the same or a different one, whereas it must be different in - case of write operation to the bank, except in muxed mode or mode D. In some - cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed - as follows: The bus turnaround delay is not inserted between two consecutive - asynchronous write transfers to the same static memory bank except for muxed - mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: - Two consecutive synchronous write operations (in Burst or Single mode) to the - same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous - write or read transfer to or from static memory bank. There is a bus turnaround - delay of 3 FMC clock cycle between: Two consecutive synchronous write operations - (in Burst or Single mode) to different static banks. A synchronous write transfer - (in Burst or Single mode) and a synchronous read from the same or a different - bank. ...' - name: BUSTURN - - bit_offset: 28 - bit_size: 2 - description: Access mode. These bits specify the asynchronous access modes as - shown in the next timing diagrams.These bits are taken into account only when - the EXTMOD bit in the FMC_BCRx register is 1. - name: ACCMOD + - name: ADDSET + description: "Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1." + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: "Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration." + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: "Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:" + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: "Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ..." + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 fieldset/BWTR4: - description: This register contains the control information of each memory bank. - It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set - in the FMC_BCRx register, then this register is active for write access. + description: "This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access." fields: - - bit_offset: 0 - bit_size: 4 - description: 'Address setup phase duration. These bits are written by software - to define the duration of the address setup phase in KCK_FMC cycles (refer to - Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous - accesses, this value is not used, the address setup phase is always 1 Flash - clock period duration. In muxed mode, the minimum ADDSET value is 1.' - name: ADDSET - - bit_offset: 4 - bit_size: 4 - description: 'Address-hold phase duration. These bits are written by software - to define the duration of the address hold phase (refer to Figure81 to Figure93), - used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash - accesses, this value is not used, the address hold phase is always 1 Flash clock - period duration.' - name: ADDHLD - - bit_offset: 8 - bit_size: 8 - description: 'Data-phase duration. These bits are written by software to define - the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous - SRAM, PSRAM and NOR Flash memory accesses:' - name: DATAST - - bit_offset: 16 - bit_size: 4 - description: 'Bus turnaround phase duration These bits are written by software - to add a delay at the end of a write transaction to match the minimum time between - consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC - period ≥ tEHELmin. The programmed bus turnaround delay is inserted between - a an asynchronous write transfer and any other asynchronous /synchronous read - or write transfer to or from a static bank. If a read operation is performed, - the bank can be the same or a different one, whereas it must be different in - case of write operation to the bank, except in muxed mode or mode D. In some - cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed - as follows: The bus turnaround delay is not inserted between two consecutive - asynchronous write transfers to the same static memory bank except for muxed - mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: - Two consecutive synchronous write operations (in Burst or Single mode) to the - same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous - write or read transfer to or from static memory bank. There is a bus turnaround - delay of 3 FMC clock cycle between: Two consecutive synchronous write operations - (in Burst or Single mode) to different static banks. A synchronous write transfer - (in Burst or Single mode) and a synchronous read from the same or a different - bank. ...' - name: BUSTURN - - bit_offset: 28 - bit_size: 2 - description: Access mode. These bits specify the asynchronous access modes as - shown in the next timing diagrams.These bits are taken into account only when - the EXTMOD bit in the FMC_BCRx register is 1. - name: ACCMOD + - name: ADDSET + description: "Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1." + bit_offset: 0 + bit_size: 4 + - name: ADDHLD + description: "Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration." + bit_offset: 4 + bit_size: 4 + - name: DATAST + description: "Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:" + bit_offset: 8 + bit_size: 8 + - name: BUSTURN + description: "Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ..." + bit_offset: 16 + bit_size: 4 + - name: ACCMOD + description: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + bit_offset: 28 + bit_size: 2 fieldset/ECCR: - description: 'This register contain the current error correction code value computed - by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes - the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: - Computation of the error correction code (ECC) in NAND Flash memory), the data - read/written from/to the NAND Flash memory are processed automatically by the - ECC computation module. When X bytes have been read (according to the ECCPS field - in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC - registers. It then verifies if these computed parity data are the same as the - parity value recorded in the spare area, to determine whether a page is valid, - and, to correct it otherwise. The FMC_ECCR register should be cleared after being - read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit - must be set to 1.' + description: "This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1." fields: - - bit_offset: 0 - bit_size: 32 - description: ECC result This field contains the value computed by the ECC computation - logic. Table167 describes the contents of these bit fields. - name: ECC + - name: ECC + description: ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields. + bit_offset: 0 + bit_size: 32 fieldset/PATT: - description: 'The FMC_PATT read/write register contains the timing information for - NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory - space of the NAND Flash for the last address write access if the timing must differ - from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: - NAND Flash prewait feature).' + description: "The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature)." fields: - - bit_offset: 0 - bit_size: 8 - description: 'Attribute memory setup time These bits define the number of KCK_FMC - (+1) clock cycles to set up address before the command assertion (NWE, NOE), - for NAND Flash read or write access to attribute memory space:' - name: ATTSET - - bit_offset: 8 - bit_size: 8 - description: 'Attribute memory wait time These bits define the minimum number - of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash - read or write access to attribute memory space. The duration for command assertion - is extended if the wait signal (NWAIT) is active (low) at the end of the programmed - value of KCK_FMC:' - name: ATTWAIT - - bit_offset: 16 - bit_size: 8 - description: 'Attribute memory hold time These bits define the number of KCK_FMC - clock cycles during which the address is held (and data for write access) after - the command de-assertion (NWE, NOE), for NAND Flash read or write access to - attribute memory space:' - name: ATTHOLD - - bit_offset: 24 - bit_size: 8 - description: 'Attribute memory data bus Hi-Z time These bits define the number - of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the - start of a NAND Flash write access to attribute memory space on socket. Only - valid for writ transaction:' - name: ATTHIZ + - name: ATTSET + description: "Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:" + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: "Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:" + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: "Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:" + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: "Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:" + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: NAND Flash control registers fields: - - bit_offset: 1 - bit_size: 1 - description: 'Wait feature enable bit. This bit enables the Wait feature for the - NAND Flash memory bank:' - name: PWAITEN - - bit_offset: 2 - bit_size: 1 - description: NAND Flash memory bank enable bit. This bit enables the memory bank. - Accessing a disabled memory bank causes an ERROR on AXI bus - name: PBKEN - - bit_offset: 4 - bit_size: 2 - description: Data bus width. These bits define the external memory device width. - name: PWID - - bit_offset: 6 - bit_size: 1 - description: ECC computation logic enable bit - name: ECCEN - - bit_offset: 9 - bit_size: 4 - description: 'CLE to RE delay. These bits set time from CLE low to RE low in number - of KCK_FMC clock cycles. The time is give by the following formula: t_clr = - (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set - is MEMSET or ATTSET according to the addressed space.' - name: TCLR - - bit_offset: 13 - bit_size: 4 - description: 'ALE to RE delay. These bits set time from ALE low to RE low in number - of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC - is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed - space.' - name: TAR - - bit_offset: 17 - bit_size: 3 - description: 'ECC page size. These bits define the page size for the extended - ECC:' - name: ECCPS + - name: PWAITEN + description: "Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank:" + bit_offset: 1 + bit_size: 1 + - name: PBKEN + description: NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus + bit_offset: 2 + bit_size: 1 + - name: PWID + description: Data bus width. These bits define the external memory device width. + bit_offset: 4 + bit_size: 2 + - name: ECCEN + description: ECC computation logic enable bit + bit_offset: 6 + bit_size: 1 + - name: TCLR + description: "CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space." + bit_offset: 9 + bit_size: 4 + - name: TAR + description: "ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space." + bit_offset: 13 + bit_size: 4 + - name: ECCPS + description: "ECC page size. These bits define the page size for the extended ECC:" + bit_offset: 17 + bit_size: 3 fieldset/PMEM: - description: The FMC_PMEM read/write register contains the timing information for - NAND Flash memory bank. This information is used to access either the common memory - space of the NAND Flash for command, address write access and data read/write - access. + description: "The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access." fields: - - bit_offset: 0 - bit_size: 8 - description: 'Common memory x setup time These bits define the number of KCK_FMC - (+1) clock cycles to set up the address before the command assertion (NWE, NOE), - for NAND Flash read or write access to common memory space:' - name: MEMSET - - bit_offset: 8 - bit_size: 8 - description: 'Common memory wait time These bits define the minimum number of - KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read - or write access to common memory space. The duration of command assertion is - extended if the wait signal (NWAIT) is active (low) at the end of the programmed - value of KCK_FMC:' - name: MEMWAIT - - bit_offset: 16 - bit_size: 8 - description: 'Common memory hold time These bits define the number of KCK_FMC - clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses - during which the address is held (and data for write accesses) after the command - is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory - space:' - name: MEMHOLD - - bit_offset: 24 - bit_size: 8 - description: 'Common memory x data bus Hi-Z time These bits define the number - of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start - of a NAND Flash write access to common memory space. This is only valid for - write transactions:' - name: MEMHIZ + - name: MEMSET + description: "Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space:" + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: "Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:" + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: "Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space:" + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: "Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions:" + bit_offset: 24 + bit_size: 8 fieldset/SDCMR: - description: This register contains the command issued when the SDRAM device is - accessed. This register is used to initialize the SDRAM device, and to activate - the Self-refresh and the Power-down modes. As soon as the MODE field is written, - the command will be issued only to one or to both SDRAM banks according to CTB1 - and CTB2 command bits. This register is the same for both SDRAM banks. + description: "This register contains the command issued when the SDRAM device is accessed. This register is used to initialize the SDRAM device, and to activate the Self-refresh and the Power-down modes. As soon as the MODE field is written, the command will be issued only to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register is the same for both SDRAM banks." fields: - - bit_offset: 0 - bit_size: 3 - description: 'Command mode These bits define the command issued to the SDRAM device. - Note: When a command is issued, at least one Command Target Bank bit ( CTB1 - or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM - banks are used, the Auto-refresh and PALL command must be issued simultaneously - to the two devices with CTB1 and CTB2 bits set otherwise the command will be - ignored. Note: If only one SDRAM bank is used and a command is issued with its - associated CTB bit set, the other CTB bit of the unused bank must be kept to - 0.' - name: MODE - - bit_offset: 3 - bit_size: 1 - description: Command Target Bank 2 This bit indicates whether the command will - be issued to SDRAM Bank 2 or not. - name: CTB2 - - bit_offset: 4 - bit_size: 1 - description: Command Target Bank 1 This bit indicates whether the command will - be issued to SDRAM Bank 1 or not. - name: CTB1 - - bit_offset: 5 - bit_size: 4 - description: Number of Auto-refresh These bits define the number of consecutive - Auto-refresh commands issued when MODE = 011. .... - name: NRFS - - bit_offset: 9 - bit_size: 14 - description: Mode Register definition This 14-bit field defines the SDRAM Mode - Register content. The Mode Register is programmed using the Load Mode Register - command. The MRD[13:0] bits are also used to program the extended mode register - for mobile SDRAM. - name: MRD + - name: MODE + description: "Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with its associated CTB bit set, the other CTB bit of the unused bank must be kept to 0." + bit_offset: 0 + bit_size: 3 + - name: CTB2 + description: Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not. + bit_offset: 3 + bit_size: 1 + - name: CTB1 + description: Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not. + bit_offset: 4 + bit_size: 1 + - name: NRFS + description: Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = 011. .... + bit_offset: 5 + bit_size: 4 + - name: MRD + description: "Mode Register definition This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. The MRD[13:0] bits are also used to program the extended mode register for mobile SDRAM." + bit_offset: 9 + bit_size: 14 fieldset/SDCR: - description: This register contains the control parameters for each SDRAM memory - bank + description: This register contains the control parameters for each SDRAM memory bank fields: - - bit_offset: 0 - bit_size: 2 - description: Number of column address bits These bits define the number of bits - of a column address. - name: NC - - bit_offset: 2 - bit_size: 2 - description: Number of row address bits These bits define the number of bits of - a row address. - name: NR - - bit_offset: 4 - bit_size: 2 - description: Memory data bus width. These bits define the memory device width. - name: MWID - - bit_offset: 6 - bit_size: 1 - description: Number of internal banks This bit sets the number of internal banks. - name: NB - - bit_offset: 7 - bit_size: 2 - description: CAS Latency This bits sets the SDRAM CAS latency in number of memory - clock cycles - name: CAS - - bit_offset: 9 - bit_size: 1 - description: Write protection This bit enables write mode access to the SDRAM - bank. - name: WP - - bit_offset: 10 - bit_size: 2 - description: 'SDRAM clock configuration These bits define the SDRAM clock period - for both SDRAM banks and allow disabling the clock before changing the frequency. - In this case the SDRAM must be re-initialized. Note: The corresponding bits - in the FMC_SDCR2 register is read only.' - name: SDCLK - - bit_offset: 12 - bit_size: 1 - description: 'Burst read This bit enables burst read mode. The SDRAM controller - anticipates the next read commands during the CAS latency and stores data in - the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read - only.' - name: RBURST - - bit_offset: 13 - bit_size: 2 - description: 'Read pipe These bits define the delay, in KCK_FMC clock cycles, - for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 - register is read only.' - name: RPIPE + - name: NC + description: Number of column address bits These bits define the number of bits of a column address. + bit_offset: 0 + bit_size: 2 + - name: NR + description: Number of row address bits These bits define the number of bits of a row address. + bit_offset: 2 + bit_size: 2 + - name: MWID + description: Memory data bus width. These bits define the memory device width. + bit_offset: 4 + bit_size: 2 + - name: NB + description: Number of internal banks This bit sets the number of internal banks. + bit_offset: 6 + bit_size: 1 + - name: CAS + description: CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles + bit_offset: 7 + bit_size: 2 + - name: WP + description: Write protection This bit enables write mode access to the SDRAM bank. + bit_offset: 9 + bit_size: 1 + - name: SDCLK + description: "SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only." + bit_offset: 10 + bit_size: 2 + - name: RBURST + description: "Burst read This bit enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only." + bit_offset: 12 + bit_size: 1 + - name: RPIPE + description: "Read pipe These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only." + bit_offset: 13 + bit_size: 2 fieldset/SDRTR: - description: This register sets the refresh rate in number of SDCLK clock cycles - between the refresh cycles by configuring the Refresh Timer Count value.Examplewhere - 64 ms is the SDRAM refresh period.The refresh rate must be increased by 20 SDRAM - clock cycles (as in the above example) to obtain a safe margin if an internal - refresh request occurs when a read request has been accepted. It corresponds to - a COUNT value of 0000111000000 (448). This 13-bit field is loaded into a timer - which is decremented using the SDRAM clock. This timer generates a refresh pulse - when zero is reached. The COUNT value must be set at least to 41 SDRAM clock cycles.As - soon as the FMC_SDRTR register is programmed, the timer starts counting. If the - value programmed in the register is 0, no refresh is carried out. This register - must not be reprogrammed after the initialization procedure to avoid modifying - the refresh rate.Each time a refresh pulse is generated, this 13-bit COUNT field - is reloaded into the counter.If a memory access is in progress, the Auto-refresh - request is delayed. However, if the memory access and Auto-refresh requests are - generated simultaneously, the Auto-refresh takes precedence. If the memory access - occurs during a refresh operation, the request is buffered to be processed when - the refresh is complete.This register is common to SDRAM bank 1 and bank 2. + description: "This register sets the refresh rate in number of SDCLK clock cycles between the refresh cycles by configuring the Refresh Timer Count value.Examplewhere 64 ms is the SDRAM refresh period.The refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to obtain a safe margin if an internal refresh request occurs when a read request has been accepted. It corresponds to a COUNT value of 0000111000000 (448). This 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This timer generates a refresh pulse when zero is reached. The COUNT value must be set at least to 41 SDRAM clock cycles.As soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value programmed in the register is 0, no refresh is carried out. This register must not be reprogrammed after the initialization procedure to avoid modifying the refresh rate.Each time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.If a memory access is in progress, the Auto-refresh request is delayed. However, if the memory access and Auto-refresh requests are generated simultaneously, the Auto-refresh takes precedence. If the memory access occurs during a refresh operation, the request is buffered to be processed when the refresh is complete.This register is common to SDRAM bank 1 and bank 2." fields: - - bit_offset: 0 - bit_size: 1 - description: Clear Refresh error flag This bit is used to clear the Refresh Error - Flag (RE) in the Status Register. - name: CRE - - bit_offset: 1 - bit_size: 13 - description: Refresh Timer Count This 13-bit field defines the refresh rate of - the SDRAM device. It is expressed in number of memory clock cycles. It must - be set at least to 41 SDRAM clock cycles (0x29). Refresh rate = (COUNT + 1) - x SDRAM frequency clock COUNT = (SDRAM refresh period / Number of rows) - 20 - name: COUNT - - bit_offset: 14 - bit_size: 1 - description: RES Interrupt Enable - name: REIE + - name: CRE + description: Clear Refresh error flag This bit is used to clear the Refresh Error Flag (RE) in the Status Register. + bit_offset: 0 + bit_size: 1 + - name: COUNT + description: Refresh Timer Count This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29). Refresh rate = (COUNT + 1) x SDRAM frequency clock COUNT = (SDRAM refresh period / Number of rows) - 20 + bit_offset: 1 + bit_size: 13 + - name: REIE + description: RES Interrupt Enable + bit_offset: 14 + bit_size: 1 fieldset/SDSR: description: SDRAM Status register fields: - - bit_offset: 0 - bit_size: 1 - description: Refresh error flag An interrupt is generated if REIE = 1 and RE = - 1 - name: RE - - bit_offset: 1 - bit_size: 2 - description: Status Mode for Bank 1 These bits define the Status Mode of SDRAM - Bank 1. - name: MODES1 - - bit_offset: 3 - bit_size: 2 - description: Status Mode for Bank 2 These bits define the Status Mode of SDRAM - Bank 2. - name: MODES2 + - name: RE + description: Refresh error flag An interrupt is generated if REIE = 1 and RE = 1 + bit_offset: 0 + bit_size: 1 + - name: MODES1 + description: Status Mode for Bank 1 These bits define the Status Mode of SDRAM Bank 1. + bit_offset: 1 + bit_size: 2 + - name: MODES2 + description: Status Mode for Bank 2 These bits define the Status Mode of SDRAM Bank 2. + bit_offset: 3 + bit_size: 2 fieldset/SDTR: description: This register contains the timing parameters of each SDRAM bank fields: - - bit_offset: 0 - bit_size: 4 - description: Load Mode Register to Active These bits define the delay between - a Load Mode Register command and an Active or Refresh command in number of memory - clock cycles. .... - name: TMRD - - bit_offset: 4 - bit_size: 4 - description: 'Exit Self-refresh delay These bits define the delay from releasing - the Self-refresh command to issuing the Activate command in number of memory - clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 - must be programmed with the same TXSR timing corresponding to the slowest SDRAM - device.' - name: TXSR - - bit_offset: 8 - bit_size: 4 - description: Self refresh time These bits define the minimum Self-refresh period - in number of memory clock cycles. .... - name: TRAS - - bit_offset: 12 - bit_size: 4 - description: 'Row cycle delay These bits define the delay between the Refresh - command and the Activate command, as well as the delay between two consecutive - Refresh commands. It is expressed in number of memory clock cycles. The TRC - timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are - used, the TRC must be programmed with the timings of the slowest device. .... - Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined - in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 - register are dont care.' - name: TRC - - bit_offset: 16 - bit_size: 4 - description: 'Recovery delay These bits define the delay between a Write and a - Precharge command in number of memory clock cycles. .... Note: TWR must be programmed - to match the write recovery time (tWR) defined in the SDRAM datasheet, and to - guarantee that: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Example: - TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed - to 0x1. If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed - with the same TWR timing corresponding to the slowest SDRAM device.' - name: TWR - - bit_offset: 20 - bit_size: 4 - description: 'Row precharge delay These bits define the delay between a Precharge - command and another command in number of memory clock cycles. The TRP timing - is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, - the TRP must be programmed with the timing of the slowest device. .... Note: - The corresponding bits in the FMC_SDTR2 register are dont care.' - name: TRP - - bit_offset: 24 - bit_size: 4 - description: Row to column delay These bits define the delay between the Activate - command and a Read/Write command in number of memory clock cycles. .... - name: TRCD + - name: TMRD + description: Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. .... + bit_offset: 0 + bit_size: 4 + - name: TXSR + description: "Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device." + bit_offset: 4 + bit_size: 4 + - name: TRAS + description: Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. .... + bit_offset: 8 + bit_size: 4 + - name: TRC + description: "Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. .... Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are dont care." + bit_offset: 12 + bit_size: 4 + - name: TWR + description: "Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. .... Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device." + bit_offset: 16 + bit_size: 4 + - name: TRP + description: "Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. .... Note: The corresponding bits in the FMC_SDTR2 register are dont care." + bit_offset: 20 + bit_size: 4 + - name: TRCD + description: Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. .... + bit_offset: 24 + bit_size: 4 fieldset/SR: - description: This register contains information about the FIFO status and interrupt. - The FMC features a FIFO that is used when writing to memories to transfer up to - 16 words of data.This is used to quickly write to the FIFO and free the AXI bus - for transactions to peripherals other than the FMC, while the FMC is draining - its FIFO into the memory. One of these register bits indicates the status of the - FIFO, for ECC purposes.The ECC is calculated while the data are written to the - memory. To read the correct ECC, the software must consequently wait until the - FIFO is empty. + description: "This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty." fields: - - bit_offset: 0 - bit_size: 1 - description: 'Interrupt rising edge status The flag is set by hardware and reset - by software. Note: If this bit is written by software to 1 it will be set.' - name: IRS - - bit_offset: 1 - bit_size: 1 - description: Interrupt high-level status The flag is set by hardware and reset - by software. - name: ILS - - bit_offset: 2 - bit_size: 1 - description: 'Interrupt falling edge status The flag is set by hardware and reset - by software. Note: If this bit is written by software to 1 it will be set.' - name: IFS - - bit_offset: 3 - bit_size: 1 - description: Interrupt rising edge detection enable bit - name: IREN - - bit_offset: 4 - bit_size: 1 - description: Interrupt high-level detection enable bit - name: ILEN - - bit_offset: 5 - bit_size: 1 - description: Interrupt falling edge detection enable bit - name: IFEN - - bit_offset: 6 - bit_size: 1 - description: FIFO empty. Read-only bit that provides the status of the FIFO - name: FEMPT + - name: IRS + description: "Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set." + bit_offset: 0 + bit_size: 1 + - name: ILS + description: Interrupt high-level status The flag is set by hardware and reset by software. + bit_offset: 1 + bit_size: 1 + - name: IFS + description: "Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set." + bit_offset: 2 + bit_size: 1 + - name: IREN + description: Interrupt rising edge detection enable bit + bit_offset: 3 + bit_size: 1 + - name: ILEN + description: Interrupt high-level detection enable bit + bit_offset: 4 + bit_size: 1 + - name: IFEN + description: Interrupt falling edge detection enable bit + bit_offset: 5 + bit_size: 1 + - name: FEMPT + description: FIFO empty. Read-only bit that provides the status of the FIFO + bit_offset: 6 + bit_size: 1 diff --git a/data/registers/gpio_v1.yaml b/data/registers/gpio_v1.yaml index 386d4c0..d53f35e 100644 --- a/data/registers/gpio_v1.yaml +++ b/data/registers/gpio_v1.yaml @@ -65,14 +65,6 @@ fieldset/BSRR: fieldset/CR: description: Port configuration register (GPIOn_CRx) fields: - - name: CNF - description: Port n configuration bits - bit_offset: 2 - bit_size: 2 - array: - len: 8 - stride: 4 - enum: CNF - name: MODE description: Port n mode bits bit_offset: 0 @@ -81,6 +73,14 @@ fieldset/CR: len: 8 stride: 4 enum: MODE + - name: CNF + description: Port n configuration bits + bit_offset: 2 + bit_size: 2 + array: + len: 8 + stride: 4 + enum: CNF fieldset/IDR: description: Port input data register (GPIOn_IDR) fields: @@ -95,11 +95,6 @@ fieldset/IDR: fieldset/LCKR: description: Port configuration lock register fields: - - name: LCKK - description: Lock key - bit_offset: 16 - bit_size: 1 - enum: LCKK - name: LCK description: Port A Lock bit bit_offset: 0 @@ -108,6 +103,11 @@ fieldset/LCKR: len: 16 stride: 1 enum: LCK + - name: LCKK + description: Lock key + bit_offset: 16 + bit_size: 1 + enum: LCKK fieldset/ODR: description: Port output data register (GPIOn_ODR) fields: @@ -155,12 +155,12 @@ enum/CNF: enum/IDR: bit_size: 1 variants: - - name: High - description: Input is logic high - value: 1 - name: Low description: Input is logic low value: 0 + - name: High + description: Input is logic high + value: 1 enum/LCK: bit_size: 1 variants: @@ -197,9 +197,9 @@ enum/MODE: enum/ODR: bit_size: 1 variants: - - name: High - description: Set output to logic high - value: 1 - name: Low description: Set output to logic low value: 0 + - name: High + description: Set output to logic high + value: 1 diff --git a/data/registers/gpio_v2.yaml b/data/registers/gpio_v2.yaml index cd9f3c5..22b52b7 100644 --- a/data/registers/gpio_v2.yaml +++ b/data/registers/gpio_v2.yaml @@ -57,14 +57,6 @@ fieldset/AFR: fieldset/BSRR: description: GPIO port bit set/reset register fields: - - name: BR - description: Port x set bit y (y= 0..15) - bit_offset: 16 - bit_size: 1 - array: - len: 16 - stride: 1 - enum_write: BRW - name: BS description: Port x set bit y (y= 0..15) bit_offset: 0 @@ -73,6 +65,14 @@ fieldset/BSRR: len: 16 stride: 1 enum_write: BSW + - name: BR + description: Port x set bit y (y= 0..15) + bit_offset: 16 + bit_size: 1 + array: + len: 16 + stride: 1 + enum_write: BRW fieldset/IDR: description: GPIO port input data register fields: @@ -87,11 +87,6 @@ fieldset/IDR: fieldset/LCKR: description: GPIO port configuration lock register fields: - - name: LCKK - description: Port x lock bit y (y= 0..15) - bit_offset: 16 - bit_size: 1 - enum: LCKK - name: LCK description: Port x lock bit y (y= 0..15) bit_offset: 0 @@ -100,6 +95,11 @@ fieldset/LCKR: len: 16 stride: 1 enum: LCK + - name: LCKK + description: Port x lock bit y (y= 0..15) + bit_offset: 16 + bit_size: 1 + enum: LCKK fieldset/MODER: description: GPIO port mode register fields: @@ -221,12 +221,12 @@ enum/BSW: enum/IDR: bit_size: 1 variants: - - name: High - description: Input is logic high - value: 1 - name: Low description: Input is logic low value: 0 + - name: High + description: Input is logic high + value: 1 enum/LCK: bit_size: 1 variants: @@ -263,12 +263,12 @@ enum/MODER: enum/ODR: bit_size: 1 variants: - - name: High - description: Set output to logic high - value: 1 - name: Low description: Set output to logic low value: 0 + - name: High + description: Set output to logic high + value: 1 enum/OSPEEDR: bit_size: 2 variants: diff --git a/data/registers/mdios_v1.yaml b/data/registers/mdios_v1.yaml index 23d33f1..973624a 100644 --- a/data/registers/mdios_v1.yaml +++ b/data/registers/mdios_v1.yaml @@ -2,14 +2,14 @@ block/MDIOS: description: Management data input/output slave items: - - name: MDIOS_CR - description: MDIOS configuration register - byte_offset: 0 - fieldset: MDIOS_CR - name: CR description: MDIOS configuration register byte_offset: 0 fieldset: CR + - name: MDIOS_CR + description: MDIOS configuration register + byte_offset: 0 + fieldset: MDIOS_CR - name: MDIOS_WRFR description: MDIOS write flag register byte_offset: 4 @@ -20,14 +20,14 @@ block/MDIOS: byte_offset: 4 access: Read fieldset: WRFR - - name: MDIOS_CWRFR - description: MDIOS clear write flag register - byte_offset: 8 - fieldset: MDIOS_CWRFR - name: CWRFR description: MDIOS clear write flag register byte_offset: 8 fieldset: CWRFR + - name: MDIOS_CWRFR + description: MDIOS clear write flag register + byte_offset: 8 + fieldset: MDIOS_CWRFR - name: MDIOS_RDFR description: MDIOS read flag register byte_offset: 12 @@ -38,14 +38,14 @@ block/MDIOS: byte_offset: 12 access: Read fieldset: RDFR - - name: MDIOS_CRDFR - description: MDIOS clear read flag register - byte_offset: 16 - fieldset: MDIOS_CRDFR - name: CRDFR description: MDIOS clear read flag register byte_offset: 16 fieldset: CRDFR + - name: MDIOS_CRDFR + description: MDIOS clear read flag register + byte_offset: 16 + fieldset: MDIOS_CRDFR - name: MDIOS_SR description: MDIOS status register byte_offset: 20 @@ -56,19 +56,14 @@ block/MDIOS: byte_offset: 20 access: Read fieldset: SR - - name: MDIOS_CLRFR - description: MDIOS clear flag register - byte_offset: 24 - fieldset: MDIOS_CLRFR - name: CLRFR description: MDIOS clear flag register byte_offset: 24 fieldset: CLRFR - - name: MDIOS_DINR0 - description: MDIOS input data register 0 - byte_offset: 28 - access: Read - fieldset: MDIOS_DINR0 + - name: MDIOS_CLRFR + description: MDIOS clear flag register + byte_offset: 24 + fieldset: MDIOS_CLRFR - name: DINR description: MDIOS input data register %s array: @@ -77,6 +72,11 @@ block/MDIOS: byte_offset: 28 access: Read fieldset: DINR + - name: MDIOS_DINR0 + description: MDIOS input data register 0 + byte_offset: 28 + access: Read + fieldset: MDIOS_DINR0 - name: MDIOS_DINR1 description: MDIOS input data register 1 byte_offset: 32 @@ -232,10 +232,6 @@ block/MDIOS: byte_offset: 152 access: Read fieldset: MDIOS_DINR31 - - name: MDIOS_DOUTR0 - description: MDIOS output data register 0 - byte_offset: 156 - fieldset: MDIOS_DOUTR0 - name: DOUTR description: MDIOS output data register %s array: @@ -243,6 +239,10 @@ block/MDIOS: stride: 4 byte_offset: 156 fieldset: DOUTR + - name: MDIOS_DOUTR0 + description: MDIOS output data register 0 + byte_offset: 156 + fieldset: MDIOS_DOUTR0 - name: MDIOS_DOUTR1 description: MDIOS output data register 1 byte_offset: 160 diff --git a/data/registers/otghs_v1.yaml b/data/registers/otghs_v1.yaml index b1adb8e..0564824 100644 --- a/data/registers/otghs_v1.yaml +++ b/data/registers/otghs_v1.yaml @@ -62,16 +62,16 @@ block/OTG_HS: description: OTG_HS nonperiodic transmit FIFO size register (host mode) byte_offset: 40 fieldset: OTG_HS_HNPTXFSIZ_Host - - name: OTG_HS_HNPTXSTS - description: OTG_HS nonperiodic transmit FIFO/queue status register - byte_offset: 44 - access: Read - fieldset: OTG_HS_HNPTXSTS - name: OTG_HS_GNPTXSTS description: OTG_HS nonperiodic transmit FIFO/queue status register byte_offset: 44 access: Read fieldset: OTG_HS_GNPTXSTS + - name: OTG_HS_HNPTXSTS + description: OTG_HS nonperiodic transmit FIFO/queue status register + byte_offset: 44 + access: Read + fieldset: OTG_HS_HNPTXSTS - name: OTG_HS_GI2CCTL description: OTG I2C access register byte_offset: 48 diff --git a/data/registers/pwr_f3.yaml b/data/registers/pwr_f3.yaml index 021007b..d83cca3 100644 --- a/data/registers/pwr_f3.yaml +++ b/data/registers/pwr_f3.yaml @@ -1,85 +1,86 @@ +--- block/PWR: description: Power control items: - - byte_offset: 0 - description: power control register - fieldset: CR - name: CR - - byte_offset: 4 - description: power control/status register - fieldset: CSR - name: CSR -enum/PDDS: - bit_size: 1 - variants: - - description: Enter Stop mode when the CPU enters deepsleep - name: STOP_MODE - value: 0 - - description: Enter Standby mode when the CPU enters deepsleep - name: STANDBY_MODE - value: 1 + - name: CR + description: power control register + byte_offset: 0 + fieldset: CR + - name: CSR + description: power control/status register + byte_offset: 4 + fieldset: CSR fieldset/CR: description: power control register fields: - - bit_offset: 0 - bit_size: 1 - description: Low-power deep sleep - name: LPDS - - bit_offset: 1 - bit_size: 1 - description: Power down deepsleep - enum: PDDS - name: PDDS - - bit_offset: 2 - bit_size: 1 - description: Clear wakeup flag - name: CWUF - - bit_offset: 3 - bit_size: 1 - description: Clear standby flag - name: CSBF - - bit_offset: 4 - bit_size: 1 - description: Power voltage detector enable - name: PVDE - - bit_offset: 5 - bit_size: 3 - description: PVD level selection - name: PLS - - bit_offset: 8 - bit_size: 1 - description: Disable backup domain write protection - name: DBP - - array: - len: 3 - stride: 1 - bit_offset: 9 - bit_size: 1 - description: ENable SD1 ADC - name: ENSD + - name: LPDS + description: Low-power deep sleep + bit_offset: 0 + bit_size: 1 + - name: PDDS + description: Power down deepsleep + bit_offset: 1 + bit_size: 1 + enum: PDDS + - name: CWUF + description: Clear wakeup flag + bit_offset: 2 + bit_size: 1 + - name: CSBF + description: Clear standby flag + bit_offset: 3 + bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: PVD level selection + bit_offset: 5 + bit_size: 3 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: ENSD + description: ENable SD1 ADC + bit_offset: 9 + bit_size: 1 + array: + len: 3 + stride: 1 fieldset/CSR: description: power control/status register fields: - - bit_offset: 0 - bit_size: 1 - description: Wakeup flag - name: WUF - - bit_offset: 1 - bit_size: 1 - description: Standby flag - name: SBF - - bit_offset: 2 - bit_size: 1 - description: PVD output - name: PVDO - - bit_offset: 3 - bit_size: 1 - description: Internal voltage reference ready flag - name: VREFINTRDYF - - array: - len: 2 - stride: 1 - bit_offset: 8 - bit_size: 1 - description: Enable WKUP1 pin - name: EWUP + - name: WUF + description: Wakeup flag + bit_offset: 0 + bit_size: 1 + - name: SBF + description: Standby flag + bit_offset: 1 + bit_size: 1 + - name: PVDO + description: PVD output + bit_offset: 2 + bit_size: 1 + - name: VREFINTRDYF + description: Internal voltage reference ready flag + bit_offset: 3 + bit_size: 1 + - name: EWUP + description: Enable WKUP1 pin + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 +enum/PDDS: + bit_size: 1 + variants: + - name: STOP_MODE + description: Enter Stop mode when the CPU enters deepsleep + value: 0 + - name: STANDBY_MODE + description: Enter Standby mode when the CPU enters deepsleep + value: 1 diff --git a/data/registers/pwr_f4.yaml b/data/registers/pwr_f4.yaml index faa1c8d..9a9d68e 100644 --- a/data/registers/pwr_f4.yaml +++ b/data/registers/pwr_f4.yaml @@ -64,15 +64,15 @@ fieldset/CR1: bit_size: 2 enum: VOS - name: ODEN - description: Over-drive enable (STM32F4[23] ONLY) + description: "Over-drive enable (STM32F4[23] ONLY)" bit_offset: 16 bit_size: 1 - name: ODSWEN - description: Over-drive switching enabled (STM32F4[23] ONLY) + description: "Over-drive switching enabled (STM32F4[23] ONLY)" bit_offset: 17 bit_size: 1 - name: UDEN - description: Under-drive enable in stop mode (STM32F4[23] ONLY) + description: "Under-drive enable in stop mode (STM32F4[23] ONLY)" bit_offset: 18 bit_size: 2 - name: FMSSR @@ -115,15 +115,15 @@ fieldset/CSR1: bit_offset: 9 bit_size: 1 - name: VOSRDY - description: Regulator voltage scaling output selection ready bit (STM32F4[23] ONLY) + description: "Regulator voltage scaling output selection ready bit (STM32F4[23] ONLY)" bit_offset: 14 bit_size: 1 - name: ODRDY - description: Over-drive mode ready (STM32F4[23] ONLY) + description: "Over-drive mode ready (STM32F4[23] ONLY)" bit_offset: 16 bit_size: 1 - name: ODSWRDY - description: Over-drive mode switching ready (STM32F4[23] ONLY) + description: "Over-drive mode switching ready (STM32F4[23] ONLY)" bit_offset: 17 bit_size: 1 - name: UDRDY @@ -143,7 +143,7 @@ enum/VOS: bit_size: 2 variants: - name: SCALE3 - description: Scale 3 mode (STM32F4[23] ONLY) + description: "Scale 3 mode (STM32F4[23] ONLY)" value: 1 - name: SCALE2 description: Scale 2 mode diff --git a/data/registers/pwr_g0.yaml b/data/registers/pwr_g0.yaml index a9fa62c..669a3a3 100644 --- a/data/registers/pwr_g0.yaml +++ b/data/registers/pwr_g0.yaml @@ -35,18 +35,18 @@ block/PWR: fieldset: SCR - name: PUCR description: Power Port pull-up control register + array: + len: 6 + stride: 8 byte_offset: 32 fieldset: PCR - array: - len: 6 - stride: 8 - name: PDCR description: Power Port pull-down control register - byte_offset: 36 - fieldset: PCR array: len: 6 stride: 8 + byte_offset: 36 + fieldset: PCR fieldset/CR1: description: Power control register 1 fields: diff --git a/data/registers/pwr_g4.yaml b/data/registers/pwr_g4.yaml index 7609d69..f942f95 100644 --- a/data/registers/pwr_g4.yaml +++ b/data/registers/pwr_g4.yaml @@ -35,18 +35,18 @@ block/PWR: fieldset: SCR - name: PUCR description: Power Port pull-up control register + array: + len: 7 + stride: 8 byte_offset: 32 fieldset: PCR - array: - len: 7 - stride: 8 - name: PDCR description: Power Port pull-down control register - byte_offset: 36 - fieldset: PCR array: len: 7 stride: 8 + byte_offset: 36 + fieldset: PCR - name: CR5 description: Power control register 5 byte_offset: 128 diff --git a/data/registers/pwr_u5.yaml b/data/registers/pwr_u5.yaml index 7f2cb26..fd5e25b 100644 --- a/data/registers/pwr_u5.yaml +++ b/data/registers/pwr_u5.yaml @@ -83,18 +83,18 @@ block/PWR: fieldset: APCR - name: PUCR description: Power Port pull-up control register + array: + len: 9 + stride: 8 byte_offset: 80 fieldset: PCR - array: - len: 9 - stride: 8 - name: PDCR description: Power Port pull-down control register - byte_offset: 84 - fieldset: PCR array: len: 9 stride: 8 + byte_offset: 84 + fieldset: PCR fieldset/APCR: description: "PWR apply pull configuration register " fields: diff --git a/data/registers/pwr_wb55.yaml b/data/registers/pwr_wb55.yaml index bb32aa4..2d237ab 100644 --- a/data/registers/pwr_wb55.yaml +++ b/data/registers/pwr_wb55.yaml @@ -1,1116 +1,1116 @@ +--- block/PWR: description: Power control items: - - byte_offset: 0 - description: Power control register 1 - fieldset: CR1 - name: CR1 - - byte_offset: 4 - description: Power control register 2 - fieldset: CR2 - name: CR2 - - byte_offset: 8 - description: Power control register 3 - fieldset: CR3 - name: CR3 - - byte_offset: 12 - description: Power control register 4 - fieldset: CR4 - name: CR4 - - access: Read - byte_offset: 16 - description: Power status register 1 - fieldset: SR1 - name: SR1 - - access: Read - byte_offset: 20 - description: Power status register 2 - fieldset: SR2 - name: SR2 - - access: Write - byte_offset: 24 - description: Power status clear register - fieldset: SCR - name: SCR - - byte_offset: 28 - description: Power control register 5 - fieldset: CR5 - name: CR5 - - byte_offset: 32 - description: Power Port A pull-up control register - fieldset: PUCRA - name: PUCRA - - byte_offset: 36 - description: Power Port A pull-down control register - fieldset: PDCRA - name: PDCRA - - byte_offset: 40 - description: Power Port B pull-up control register - fieldset: PUCRB - name: PUCRB - - byte_offset: 44 - description: Power Port B pull-down control register - fieldset: PDCRB - name: PDCRB - - byte_offset: 48 - description: Power Port C pull-up control register - fieldset: PUCRC - name: PUCRC - - byte_offset: 52 - description: Power Port C pull-down control register - fieldset: PDCRC - name: PDCRC - - byte_offset: 56 - description: Power Port D pull-up control register - fieldset: PUCRD - name: PUCRD - - byte_offset: 60 - description: Power Port D pull-down control register - fieldset: PDCRD - name: PDCRD - - byte_offset: 64 - description: Power Port E pull-up control register - fieldset: PUCRE - name: PUCRE - - byte_offset: 68 - description: Power Port E pull-down control register - fieldset: PDCRE - name: PDCRE - - byte_offset: 88 - description: Power Port H pull-up control register - fieldset: PUCRH - name: PUCRH - - byte_offset: 92 - description: Power Port H pull-down control register - fieldset: PDCRH - name: PDCRH - - byte_offset: 128 - description: CPU2 Power control register 1 - fieldset: C2CR1 - name: C2CR1 - - byte_offset: 132 - description: CPU2 Power control register 3 - fieldset: C2CR3 - name: C2CR3 - - byte_offset: 136 - description: Power status clear register - fieldset: EXTSCR - name: EXTSCR + - name: CR1 + description: Power control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Power control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Power control register 3 + byte_offset: 8 + fieldset: CR3 + - name: CR4 + description: Power control register 4 + byte_offset: 12 + fieldset: CR4 + - name: SR1 + description: Power status register 1 + byte_offset: 16 + access: Read + fieldset: SR1 + - name: SR2 + description: Power status register 2 + byte_offset: 20 + access: Read + fieldset: SR2 + - name: SCR + description: Power status clear register + byte_offset: 24 + access: Write + fieldset: SCR + - name: CR5 + description: Power control register 5 + byte_offset: 28 + fieldset: CR5 + - name: PUCRA + description: Power Port A pull-up control register + byte_offset: 32 + fieldset: PUCRA + - name: PDCRA + description: Power Port A pull-down control register + byte_offset: 36 + fieldset: PDCRA + - name: PUCRB + description: Power Port B pull-up control register + byte_offset: 40 + fieldset: PUCRB + - name: PDCRB + description: Power Port B pull-down control register + byte_offset: 44 + fieldset: PDCRB + - name: PUCRC + description: Power Port C pull-up control register + byte_offset: 48 + fieldset: PUCRC + - name: PDCRC + description: Power Port C pull-down control register + byte_offset: 52 + fieldset: PDCRC + - name: PUCRD + description: Power Port D pull-up control register + byte_offset: 56 + fieldset: PUCRD + - name: PDCRD + description: Power Port D pull-down control register + byte_offset: 60 + fieldset: PDCRD + - name: PUCRE + description: Power Port E pull-up control register + byte_offset: 64 + fieldset: PUCRE + - name: PDCRE + description: Power Port E pull-down control register + byte_offset: 68 + fieldset: PDCRE + - name: PUCRH + description: Power Port H pull-up control register + byte_offset: 88 + fieldset: PUCRH + - name: PDCRH + description: Power Port H pull-down control register + byte_offset: 92 + fieldset: PDCRH + - name: C2CR1 + description: CPU2 Power control register 1 + byte_offset: 128 + fieldset: C2CR1 + - name: C2CR3 + description: CPU2 Power control register 3 + byte_offset: 132 + fieldset: C2CR3 + - name: EXTSCR + description: Power status clear register + byte_offset: 136 + fieldset: EXTSCR fieldset/C2CR1: description: CPU2 Power control register 1 fields: - - bit_offset: 0 - bit_size: 3 - description: Low-power mode selection for CPU2 - name: LPMS - - bit_offset: 4 - bit_size: 1 - description: Flash power down mode during LPRun for CPU2 - name: FPDR - - bit_offset: 5 - bit_size: 1 - description: Flash power down mode during LPSleep for CPU2 - name: FPDS - - bit_offset: 14 - bit_size: 1 - description: BLE external wakeup signal - name: BLEEWKUP - - bit_offset: 15 - bit_size: 1 - description: 802.15.4 external wakeup signal - name: _802EWKUP + - name: LPMS + description: Low-power mode selection for CPU2 + bit_offset: 0 + bit_size: 3 + - name: FPDR + description: Flash power down mode during LPRun for CPU2 + bit_offset: 4 + bit_size: 1 + - name: FPDS + description: Flash power down mode during LPSleep for CPU2 + bit_offset: 5 + bit_size: 1 + - name: BLEEWKUP + description: BLE external wakeup signal + bit_offset: 14 + bit_size: 1 + - name: _802EWKUP + description: 802.15.4 external wakeup signal + bit_offset: 15 + bit_size: 1 fieldset/C2CR3: description: CPU2 Power control register 3 fields: - - bit_offset: 0 - bit_size: 1 - description: Enable Wakeup pin WKUP1 for CPU2 - name: EWUP1 - - bit_offset: 1 - bit_size: 1 - description: Enable Wakeup pin WKUP2 for CPU2 - name: EWUP2 - - bit_offset: 2 - bit_size: 1 - description: Enable Wakeup pin WKUP3 for CPU2 - name: EWUP3 - - bit_offset: 3 - bit_size: 1 - description: Enable Wakeup pin WKUP4 for CPU2 - name: EWUP4 - - bit_offset: 4 - bit_size: 1 - description: Enable Wakeup pin WKUP5 for CPU2 - name: EWUP5 - - bit_offset: 9 - bit_size: 1 - description: Enable BLE host wakeup interrupt for CPU2 - name: EBLEWUP - - bit_offset: 10 - bit_size: 1 - description: Enable 802.15.4 host wakeup interrupt for CPU2 - name: E802WUP - - bit_offset: 12 - bit_size: 1 - description: Apply pull-up and pull-down configuration for CPU2 - name: APC - - bit_offset: 15 - bit_size: 1 - description: Enable internal wakeup line for CPU2 - name: EIWUL + - name: EWUP1 + description: Enable Wakeup pin WKUP1 for CPU2 + bit_offset: 0 + bit_size: 1 + - name: EWUP2 + description: Enable Wakeup pin WKUP2 for CPU2 + bit_offset: 1 + bit_size: 1 + - name: EWUP3 + description: Enable Wakeup pin WKUP3 for CPU2 + bit_offset: 2 + bit_size: 1 + - name: EWUP4 + description: Enable Wakeup pin WKUP4 for CPU2 + bit_offset: 3 + bit_size: 1 + - name: EWUP5 + description: Enable Wakeup pin WKUP5 for CPU2 + bit_offset: 4 + bit_size: 1 + - name: EBLEWUP + description: Enable BLE host wakeup interrupt for CPU2 + bit_offset: 9 + bit_size: 1 + - name: E802WUP + description: Enable 802.15.4 host wakeup interrupt for CPU2 + bit_offset: 10 + bit_size: 1 + - name: APC + description: Apply pull-up and pull-down configuration for CPU2 + bit_offset: 12 + bit_size: 1 + - name: EIWUL + description: Enable internal wakeup line for CPU2 + bit_offset: 15 + bit_size: 1 fieldset/CR1: description: Power control register 1 fields: - - bit_offset: 0 - bit_size: 3 - description: Low-power mode selection for CPU1 - name: LPMS - - bit_offset: 4 - bit_size: 1 - description: Flash power down mode during LPRun for CPU1 - name: FPDR - - bit_offset: 5 - bit_size: 1 - description: Flash power down mode during LPsSleep for CPU1 - name: FPDS - - bit_offset: 8 - bit_size: 1 - description: Disable backup domain write protection - name: DBP - - bit_offset: 9 - bit_size: 2 - description: Voltage scaling range selection - name: VOS - - bit_offset: 14 - bit_size: 1 - description: Low-power run - name: LPR + - name: LPMS + description: Low-power mode selection for CPU1 + bit_offset: 0 + bit_size: 3 + - name: FPDR + description: Flash power down mode during LPRun for CPU1 + bit_offset: 4 + bit_size: 1 + - name: FPDS + description: Flash power down mode during LPsSleep for CPU1 + bit_offset: 5 + bit_size: 1 + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: VOS + description: Voltage scaling range selection + bit_offset: 9 + bit_size: 2 + - name: LPR + description: Low-power run + bit_offset: 14 + bit_size: 1 fieldset/CR2: description: Power control register 2 fields: - - bit_offset: 0 - bit_size: 1 - description: Power voltage detector enable - name: PVDE - - bit_offset: 1 - bit_size: 3 - description: Power voltage detector level selection - name: PLS - - bit_offset: 4 - bit_size: 1 - description: 'Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V' - name: PVME1 - - bit_offset: 6 - bit_size: 1 - description: 'Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V' - name: PVME3 - - bit_offset: 10 - bit_size: 1 - description: VDDUSB USB supply valid - name: USV + - name: PVDE + description: Power voltage detector enable + bit_offset: 0 + bit_size: 1 + - name: PLS + description: Power voltage detector level selection + bit_offset: 1 + bit_size: 3 + - name: PVME1 + description: "Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" + bit_offset: 4 + bit_size: 1 + - name: PVME3 + description: "Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" + bit_offset: 6 + bit_size: 1 + - name: USV + description: VDDUSB USB supply valid + bit_offset: 10 + bit_size: 1 fieldset/CR3: description: Power control register 3 fields: - - bit_offset: 0 - bit_size: 1 - description: Enable Wakeup pin WKUP1 - name: EWUP1 - - bit_offset: 1 - bit_size: 1 - description: Enable Wakeup pin WKUP2 - name: EWUP2 - - bit_offset: 2 - bit_size: 1 - description: Enable Wakeup pin WKUP3 - name: EWUP3 - - bit_offset: 3 - bit_size: 1 - description: Enable Wakeup pin WKUP4 - name: EWUP4 - - bit_offset: 4 - bit_size: 1 - description: Enable Wakeup pin WKUP5 - name: EWUP5 - - bit_offset: 8 - bit_size: 1 - description: Enable BORH and Step Down counverter forced in Bypass interrups for - CPU1 - name: EBORHSDFB - - bit_offset: 9 - bit_size: 1 - description: SRAM2a retention in Standby mode - name: RRS - - bit_offset: 10 - bit_size: 1 - description: Apply pull-up and pull-down configuration - name: APC - - bit_offset: 11 - bit_size: 1 - description: Enable BLE end of activity interrupt for CPU1 - name: EBLEA - - bit_offset: 12 - bit_size: 1 - description: Enable critical radio phase end of activity interrupt for CPU1 - name: ECRPE - - bit_offset: 13 - bit_size: 1 - description: Enable end of activity interrupt for CPU1 - name: E802A - - bit_offset: 14 - bit_size: 1 - description: Enable CPU2 Hold interrupt for CPU1 - name: EC2H - - bit_offset: 15 - bit_size: 1 - description: Enable internal wakeup line for CPU1 - name: EIWUL + - name: EWUP1 + description: Enable Wakeup pin WKUP1 + bit_offset: 0 + bit_size: 1 + - name: EWUP2 + description: Enable Wakeup pin WKUP2 + bit_offset: 1 + bit_size: 1 + - name: EWUP3 + description: Enable Wakeup pin WKUP3 + bit_offset: 2 + bit_size: 1 + - name: EWUP4 + description: Enable Wakeup pin WKUP4 + bit_offset: 3 + bit_size: 1 + - name: EWUP5 + description: Enable Wakeup pin WKUP5 + bit_offset: 4 + bit_size: 1 + - name: EBORHSDFB + description: Enable BORH and Step Down counverter forced in Bypass interrups for CPU1 + bit_offset: 8 + bit_size: 1 + - name: RRS + description: SRAM2a retention in Standby mode + bit_offset: 9 + bit_size: 1 + - name: APC + description: Apply pull-up and pull-down configuration + bit_offset: 10 + bit_size: 1 + - name: EBLEA + description: Enable BLE end of activity interrupt for CPU1 + bit_offset: 11 + bit_size: 1 + - name: ECRPE + description: Enable critical radio phase end of activity interrupt for CPU1 + bit_offset: 12 + bit_size: 1 + - name: E802A + description: Enable end of activity interrupt for CPU1 + bit_offset: 13 + bit_size: 1 + - name: EC2H + description: Enable CPU2 Hold interrupt for CPU1 + bit_offset: 14 + bit_size: 1 + - name: EIWUL + description: Enable internal wakeup line for CPU1 + bit_offset: 15 + bit_size: 1 fieldset/CR4: description: Power control register 4 fields: - - bit_offset: 0 - bit_size: 1 - description: Wakeup pin WKUP1 polarity - name: WP1 - - bit_offset: 1 - bit_size: 1 - description: Wakeup pin WKUP2 polarity - name: WP2 - - bit_offset: 2 - bit_size: 1 - description: Wakeup pin WKUP3 polarity - name: WP3 - - bit_offset: 3 - bit_size: 1 - description: Wakeup pin WKUP4 polarity - name: WP4 - - bit_offset: 4 - bit_size: 1 - description: Wakeup pin WKUP5 polarity - name: WP5 - - bit_offset: 8 - bit_size: 1 - description: VBAT battery charging enable - name: VBE - - bit_offset: 9 - bit_size: 1 - description: VBAT battery charging resistor selection - name: VBRS - - bit_offset: 15 - bit_size: 1 - description: BOOT CPU2 after reset or wakeup from Stop or Standby modes - name: C2BOOT + - name: WP1 + description: Wakeup pin WKUP1 polarity + bit_offset: 0 + bit_size: 1 + - name: WP2 + description: Wakeup pin WKUP2 polarity + bit_offset: 1 + bit_size: 1 + - name: WP3 + description: Wakeup pin WKUP3 polarity + bit_offset: 2 + bit_size: 1 + - name: WP4 + description: Wakeup pin WKUP4 polarity + bit_offset: 3 + bit_size: 1 + - name: WP5 + description: Wakeup pin WKUP5 polarity + bit_offset: 4 + bit_size: 1 + - name: VBE + description: VBAT battery charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT battery charging resistor selection + bit_offset: 9 + bit_size: 1 + - name: C2BOOT + description: BOOT CPU2 after reset or wakeup from Stop or Standby modes + bit_offset: 15 + bit_size: 1 fieldset/CR5: description: Power control register 5 fields: - - bit_offset: 0 - bit_size: 4 - description: Step Down converter voltage output scaling - name: SDVOS - - bit_offset: 4 - bit_size: 3 - description: Step Down converter supplt startup current selection - name: SDSC - - bit_offset: 8 - bit_size: 1 - description: BORH configuration selection - name: BORHC - - bit_offset: 9 - bit_size: 1 - description: VOS configuration selection (non user) - name: SMPSCFG - - bit_offset: 14 - bit_size: 1 - description: Enable Step Down converter Bypass mode enabled - name: SDBEN - - bit_offset: 15 - bit_size: 1 - description: Enable Step Down converter SMPS mode enabled - name: SDEB + - name: SDVOS + description: Step Down converter voltage output scaling + bit_offset: 0 + bit_size: 4 + - name: SDSC + description: Step Down converter supplt startup current selection + bit_offset: 4 + bit_size: 3 + - name: BORHC + description: BORH configuration selection + bit_offset: 8 + bit_size: 1 + - name: SMPSCFG + description: VOS configuration selection (non user) + bit_offset: 9 + bit_size: 1 + - name: SDBEN + description: Enable Step Down converter Bypass mode enabled + bit_offset: 14 + bit_size: 1 + - name: SDEB + description: Enable Step Down converter SMPS mode enabled + bit_offset: 15 + bit_size: 1 fieldset/EXTSCR: description: Power status clear register fields: - - bit_offset: 0 - bit_size: 1 - description: Clear CPU1 Stop Standby flags - name: C1CSSF - - bit_offset: 1 - bit_size: 1 - description: Clear CPU2 Stop Standby flags - name: C2CSSF - - bit_offset: 2 - bit_size: 1 - description: Clear Critical Radio system phase - name: CCRPF - - bit_offset: 8 - bit_size: 1 - description: System Standby flag for CPU1 - name: C1SBF - - bit_offset: 9 - bit_size: 1 - description: System Stop flag for CPU1 - name: C1STOPF - - bit_offset: 10 - bit_size: 1 - description: System Standby flag for CPU2 - name: C2SBF - - bit_offset: 11 - bit_size: 1 - description: System Stop flag for CPU2 - name: C2STOPF - - bit_offset: 13 - bit_size: 1 - description: Critical Radio system phase - name: CRPF - - bit_offset: 14 - bit_size: 1 - description: CPU1 deepsleep mode - name: C1DS - - bit_offset: 15 - bit_size: 1 - description: CPU2 deepsleep mode - name: C2DS + - name: C1CSSF + description: Clear CPU1 Stop Standby flags + bit_offset: 0 + bit_size: 1 + - name: C2CSSF + description: Clear CPU2 Stop Standby flags + bit_offset: 1 + bit_size: 1 + - name: CCRPF + description: Clear Critical Radio system phase + bit_offset: 2 + bit_size: 1 + - name: C1SBF + description: System Standby flag for CPU1 + bit_offset: 8 + bit_size: 1 + - name: C1STOPF + description: System Stop flag for CPU1 + bit_offset: 9 + bit_size: 1 + - name: C2SBF + description: System Standby flag for CPU2 + bit_offset: 10 + bit_size: 1 + - name: C2STOPF + description: System Stop flag for CPU2 + bit_offset: 11 + bit_size: 1 + - name: CRPF + description: Critical Radio system phase + bit_offset: 13 + bit_size: 1 + - name: C1DS + description: CPU1 deepsleep mode + bit_offset: 14 + bit_size: 1 + - name: C2DS + description: CPU2 deepsleep mode + bit_offset: 15 + bit_size: 1 fieldset/PDCRA: description: Power Port A pull-down control register fields: - - bit_offset: 0 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD0 - - bit_offset: 1 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD1 - - bit_offset: 2 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD2 - - bit_offset: 3 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD3 - - bit_offset: 4 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD4 - - bit_offset: 5 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD5 - - bit_offset: 6 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD6 - - bit_offset: 7 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD7 - - bit_offset: 8 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD8 - - bit_offset: 9 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD9 - - bit_offset: 10 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD10 - - bit_offset: 11 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD11 - - bit_offset: 12 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD12 - - bit_offset: 14 - bit_size: 1 - description: Port A pull-down bit y (y=0..15) - name: PD14 + - name: PD0 + description: Port A pull-down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port A pull-down bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: Port A pull-down bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: Port A pull-down bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: Port A pull-down bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: Port A pull-down bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: Port A pull-down bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: Port A pull-down bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: Port A pull-down bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: Port A pull-down bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: Port A pull-down bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: Port A pull-down bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: Port A pull-down bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PD14 + description: Port A pull-down bit y (y=0..15) + bit_offset: 14 + bit_size: 1 fieldset/PDCRB: description: Power Port B pull-down control register fields: - - bit_offset: 0 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD0 - - bit_offset: 1 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD1 - - bit_offset: 2 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD2 - - bit_offset: 3 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD3 - - bit_offset: 5 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD5 - - bit_offset: 6 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD6 - - bit_offset: 7 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD7 - - bit_offset: 8 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD8 - - bit_offset: 9 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD9 - - bit_offset: 10 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD10 - - bit_offset: 11 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD11 - - bit_offset: 12 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD12 - - bit_offset: 13 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD13 - - bit_offset: 14 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD14 - - bit_offset: 15 - bit_size: 1 - description: Port B pull-down bit y (y=0..15) - name: PD15 + - name: PD0 + description: Port B pull-down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port B pull-down bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: Port B pull-down bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: Port B pull-down bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PD5 + description: Port B pull-down bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: Port B pull-down bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: Port B pull-down bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: Port B pull-down bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: Port B pull-down bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: Port B pull-down bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: Port B pull-down bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: Port B pull-down bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: Port B pull-down bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: Port B pull-down bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: Port B pull-down bit y (y=0..15) + bit_offset: 15 + bit_size: 1 fieldset/PDCRC: description: Power Port C pull-down control register fields: - - bit_offset: 0 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD0 - - bit_offset: 1 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD1 - - bit_offset: 2 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD2 - - bit_offset: 3 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD3 - - bit_offset: 4 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD4 - - bit_offset: 5 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD5 - - bit_offset: 6 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD6 - - bit_offset: 7 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD7 - - bit_offset: 8 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD8 - - bit_offset: 9 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD9 - - bit_offset: 10 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD10 - - bit_offset: 11 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD11 - - bit_offset: 12 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD12 - - bit_offset: 13 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD13 - - bit_offset: 14 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD14 - - bit_offset: 15 - bit_size: 1 - description: Port C pull-down bit y (y=0..15) - name: PD15 + - name: PD0 + description: Port C pull-down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port C pull-down bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: Port C pull-down bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: Port C pull-down bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: Port C pull-down bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: Port C pull-down bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: Port C pull-down bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: Port C pull-down bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: Port C pull-down bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: Port C pull-down bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: Port C pull-down bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: Port C pull-down bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: Port C pull-down bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: Port C pull-down bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: Port C pull-down bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: Port C pull-down bit y (y=0..15) + bit_offset: 15 + bit_size: 1 fieldset/PDCRD: description: Power Port D pull-down control register fields: - - bit_offset: 0 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD0 - - bit_offset: 1 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD1 - - bit_offset: 2 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD2 - - bit_offset: 3 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD3 - - bit_offset: 4 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD4 - - bit_offset: 5 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD5 - - bit_offset: 6 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD6 - - bit_offset: 7 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD7 - - bit_offset: 8 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD8 - - bit_offset: 9 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD9 - - bit_offset: 10 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD10 - - bit_offset: 11 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD11 - - bit_offset: 12 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD12 - - bit_offset: 13 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD13 - - bit_offset: 14 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD14 - - bit_offset: 15 - bit_size: 1 - description: Port D pull-down bit y (y=0..15) - name: PD15 + - name: PD0 + description: Port D pull-down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port D pull-down bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: Port D pull-down bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: Port D pull-down bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: Port D pull-down bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PD5 + description: Port D pull-down bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PD6 + description: Port D pull-down bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PD7 + description: Port D pull-down bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PD8 + description: Port D pull-down bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PD9 + description: Port D pull-down bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PD10 + description: Port D pull-down bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PD11 + description: Port D pull-down bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PD12 + description: Port D pull-down bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PD13 + description: Port D pull-down bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PD14 + description: Port D pull-down bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PD15 + description: Port D pull-down bit y (y=0..15) + bit_offset: 15 + bit_size: 1 fieldset/PDCRE: description: Power Port E pull-down control register fields: - - bit_offset: 0 - bit_size: 1 - description: Port E pull-down bit y (y=0..15) - name: PD0 - - bit_offset: 1 - bit_size: 1 - description: Port E pull-down bit y (y=0..15) - name: PD1 - - bit_offset: 2 - bit_size: 1 - description: Port E pull-down bit y (y=0..15) - name: PD2 - - bit_offset: 3 - bit_size: 1 - description: Port E pull-down bit y (y=0..15) - name: PD3 - - bit_offset: 4 - bit_size: 1 - description: Port E pull-down bit y (y=0..15) - name: PD4 + - name: PD0 + description: Port E pull-down bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port E pull-down bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PD2 + description: Port E pull-down bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PD3 + description: Port E pull-down bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PD4 + description: Port E pull-down bit y (y=0..15) + bit_offset: 4 + bit_size: 1 fieldset/PDCRH: description: Power Port H pull-down control register fields: - - bit_offset: 0 - bit_size: 1 - description: Port H pull-down bit y (y=0..1) - name: PD0 - - bit_offset: 1 - bit_size: 1 - description: Port H pull-down bit y (y=0..1) - name: PD1 - - bit_offset: 3 - bit_size: 1 - description: Port H pull-down bit y (y=0..1) - name: PD3 + - name: PD0 + description: Port H pull-down bit y (y=0..1) + bit_offset: 0 + bit_size: 1 + - name: PD1 + description: Port H pull-down bit y (y=0..1) + bit_offset: 1 + bit_size: 1 + - name: PD3 + description: Port H pull-down bit y (y=0..1) + bit_offset: 3 + bit_size: 1 fieldset/PUCRA: description: Power Port A pull-up control register fields: - - bit_offset: 0 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU0 - - bit_offset: 1 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU1 - - bit_offset: 2 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU2 - - bit_offset: 3 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU3 - - bit_offset: 4 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU4 - - bit_offset: 5 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU5 - - bit_offset: 6 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU6 - - bit_offset: 7 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU7 - - bit_offset: 8 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU8 - - bit_offset: 9 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU9 - - bit_offset: 10 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU10 - - bit_offset: 11 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU11 - - bit_offset: 12 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU12 - - bit_offset: 13 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU13 - - bit_offset: 15 - bit_size: 1 - description: Port A pull-up bit y (y=0..15) - name: PU15 + - name: PU0 + description: Port A pull-up bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port A pull-up bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: Port A pull-up bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: Port A pull-up bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: Port A pull-up bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: Port A pull-up bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: Port A pull-up bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: Port A pull-up bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: Port A pull-up bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: Port A pull-up bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: Port A pull-up bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: Port A pull-up bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: Port A pull-up bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: Port A pull-up bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PU15 + description: Port A pull-up bit y (y=0..15) + bit_offset: 15 + bit_size: 1 fieldset/PUCRB: description: Power Port B pull-up control register fields: - - bit_offset: 0 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU0 - - bit_offset: 1 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU1 - - bit_offset: 2 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU2 - - bit_offset: 3 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU3 - - bit_offset: 4 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU4 - - bit_offset: 5 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU5 - - bit_offset: 6 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU6 - - bit_offset: 7 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU7 - - bit_offset: 8 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU8 - - bit_offset: 9 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU9 - - bit_offset: 10 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU10 - - bit_offset: 11 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU11 - - bit_offset: 12 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU12 - - bit_offset: 13 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU13 - - bit_offset: 14 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU14 - - bit_offset: 15 - bit_size: 1 - description: Port B pull-up bit y (y=0..15) - name: PU15 + - name: PU0 + description: Port B pull-up bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port B pull-up bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: Port B pull-up bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: Port B pull-up bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: Port B pull-up bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: Port B pull-up bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: Port B pull-up bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: Port B pull-up bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: Port B pull-up bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: Port B pull-up bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: Port B pull-up bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: Port B pull-up bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: Port B pull-up bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: Port B pull-up bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: Port B pull-up bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: Port B pull-up bit y (y=0..15) + bit_offset: 15 + bit_size: 1 fieldset/PUCRC: description: Power Port C pull-up control register fields: - - bit_offset: 0 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU0 - - bit_offset: 1 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU1 - - bit_offset: 2 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU2 - - bit_offset: 3 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU3 - - bit_offset: 4 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU4 - - bit_offset: 5 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU5 - - bit_offset: 6 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU6 - - bit_offset: 7 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU7 - - bit_offset: 8 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU8 - - bit_offset: 9 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU9 - - bit_offset: 10 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU10 - - bit_offset: 11 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU11 - - bit_offset: 12 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU12 - - bit_offset: 13 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU13 - - bit_offset: 14 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU14 - - bit_offset: 15 - bit_size: 1 - description: Port C pull-up bit y (y=0..15) - name: PU15 + - name: PU0 + description: Port C pull-up bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port C pull-up bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: Port C pull-up bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: Port C pull-up bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: Port C pull-up bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: Port C pull-up bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: Port C pull-up bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: Port C pull-up bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: Port C pull-up bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: Port C pull-up bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: Port C pull-up bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: Port C pull-up bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: Port C pull-up bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: Port C pull-up bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: Port C pull-up bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: Port C pull-up bit y (y=0..15) + bit_offset: 15 + bit_size: 1 fieldset/PUCRD: description: Power Port D pull-up control register fields: - - bit_offset: 0 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU0 - - bit_offset: 1 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU1 - - bit_offset: 2 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU2 - - bit_offset: 3 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU3 - - bit_offset: 4 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU4 - - bit_offset: 5 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU5 - - bit_offset: 6 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU6 - - bit_offset: 7 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU7 - - bit_offset: 8 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU8 - - bit_offset: 9 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU9 - - bit_offset: 10 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU10 - - bit_offset: 11 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU11 - - bit_offset: 12 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU12 - - bit_offset: 13 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU13 - - bit_offset: 14 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU14 - - bit_offset: 15 - bit_size: 1 - description: Port D pull-up bit y (y=0..15) - name: PU15 + - name: PU0 + description: Port D pull-up bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port D pull-up bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: Port D pull-up bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: Port D pull-up bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: Port D pull-up bit y (y=0..15) + bit_offset: 4 + bit_size: 1 + - name: PU5 + description: Port D pull-up bit y (y=0..15) + bit_offset: 5 + bit_size: 1 + - name: PU6 + description: Port D pull-up bit y (y=0..15) + bit_offset: 6 + bit_size: 1 + - name: PU7 + description: Port D pull-up bit y (y=0..15) + bit_offset: 7 + bit_size: 1 + - name: PU8 + description: Port D pull-up bit y (y=0..15) + bit_offset: 8 + bit_size: 1 + - name: PU9 + description: Port D pull-up bit y (y=0..15) + bit_offset: 9 + bit_size: 1 + - name: PU10 + description: Port D pull-up bit y (y=0..15) + bit_offset: 10 + bit_size: 1 + - name: PU11 + description: Port D pull-up bit y (y=0..15) + bit_offset: 11 + bit_size: 1 + - name: PU12 + description: Port D pull-up bit y (y=0..15) + bit_offset: 12 + bit_size: 1 + - name: PU13 + description: Port D pull-up bit y (y=0..15) + bit_offset: 13 + bit_size: 1 + - name: PU14 + description: Port D pull-up bit y (y=0..15) + bit_offset: 14 + bit_size: 1 + - name: PU15 + description: Port D pull-up bit y (y=0..15) + bit_offset: 15 + bit_size: 1 fieldset/PUCRE: description: Power Port E pull-up control register fields: - - bit_offset: 0 - bit_size: 1 - description: Port E pull-up bit y (y=0..15) - name: PU0 - - bit_offset: 1 - bit_size: 1 - description: Port E pull-up bit y (y=0..15) - name: PU1 - - bit_offset: 2 - bit_size: 1 - description: Port E pull-up bit y (y=0..15) - name: PU2 - - bit_offset: 3 - bit_size: 1 - description: Port E pull-up bit y (y=0..15) - name: PU3 - - bit_offset: 4 - bit_size: 1 - description: Port E pull-up bit y (y=0..15) - name: PU4 + - name: PU0 + description: Port E pull-up bit y (y=0..15) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port E pull-up bit y (y=0..15) + bit_offset: 1 + bit_size: 1 + - name: PU2 + description: Port E pull-up bit y (y=0..15) + bit_offset: 2 + bit_size: 1 + - name: PU3 + description: Port E pull-up bit y (y=0..15) + bit_offset: 3 + bit_size: 1 + - name: PU4 + description: Port E pull-up bit y (y=0..15) + bit_offset: 4 + bit_size: 1 fieldset/PUCRH: description: Power Port H pull-up control register fields: - - bit_offset: 0 - bit_size: 1 - description: Port H pull-up bit y (y=0..1) - name: PU0 - - bit_offset: 1 - bit_size: 1 - description: Port H pull-up bit y (y=0..1) - name: PU1 - - bit_offset: 3 - bit_size: 1 - description: Port H pull-up bit y (y=0..1) - name: PU3 + - name: PU0 + description: Port H pull-up bit y (y=0..1) + bit_offset: 0 + bit_size: 1 + - name: PU1 + description: Port H pull-up bit y (y=0..1) + bit_offset: 1 + bit_size: 1 + - name: PU3 + description: Port H pull-up bit y (y=0..1) + bit_offset: 3 + bit_size: 1 fieldset/SCR: description: Power status clear register fields: - - bit_offset: 0 - bit_size: 1 - description: Clear wakeup flag 1 - name: CWUF1 - - bit_offset: 1 - bit_size: 1 - description: Clear wakeup flag 2 - name: CWUF2 - - bit_offset: 2 - bit_size: 1 - description: Clear wakeup flag 3 - name: CWUF3 - - bit_offset: 3 - bit_size: 1 - description: Clear wakeup flag 4 - name: CWUF4 - - bit_offset: 4 - bit_size: 1 - description: Clear wakeup flag 5 - name: CWUF5 - - bit_offset: 7 - bit_size: 1 - description: Clear SMPS Step Down converter forced in Bypass interrupt flag - name: CSMPSFBF - - bit_offset: 8 - bit_size: 1 - description: Clear BORH interrupt flag - name: CBORHF - - bit_offset: 9 - bit_size: 1 - description: Clear BLE wakeup interrupt flag - name: CBLEWUF - - bit_offset: 10 - bit_size: 1 - description: Clear 802.15.4 wakeup interrupt flag - name: C802WUF - - bit_offset: 11 - bit_size: 1 - description: Clear critical radio phase end of activity interrupt flag - name: CCRPEF - - bit_offset: 12 - bit_size: 1 - description: Clear BLE end of activity interrupt flag - name: CBLEAF - - bit_offset: 13 - bit_size: 1 - description: Clear 802.15.4 end of activity interrupt flag - name: C802AF - - bit_offset: 14 - bit_size: 1 - description: Clear CPU2 Hold interrupt flag - name: CC2HF + - name: CWUF1 + description: Clear wakeup flag 1 + bit_offset: 0 + bit_size: 1 + - name: CWUF2 + description: Clear wakeup flag 2 + bit_offset: 1 + bit_size: 1 + - name: CWUF3 + description: Clear wakeup flag 3 + bit_offset: 2 + bit_size: 1 + - name: CWUF4 + description: Clear wakeup flag 4 + bit_offset: 3 + bit_size: 1 + - name: CWUF5 + description: Clear wakeup flag 5 + bit_offset: 4 + bit_size: 1 + - name: CSMPSFBF + description: Clear SMPS Step Down converter forced in Bypass interrupt flag + bit_offset: 7 + bit_size: 1 + - name: CBORHF + description: Clear BORH interrupt flag + bit_offset: 8 + bit_size: 1 + - name: CBLEWUF + description: Clear BLE wakeup interrupt flag + bit_offset: 9 + bit_size: 1 + - name: C802WUF + description: Clear 802.15.4 wakeup interrupt flag + bit_offset: 10 + bit_size: 1 + - name: CCRPEF + description: Clear critical radio phase end of activity interrupt flag + bit_offset: 11 + bit_size: 1 + - name: CBLEAF + description: Clear BLE end of activity interrupt flag + bit_offset: 12 + bit_size: 1 + - name: C802AF + description: Clear 802.15.4 end of activity interrupt flag + bit_offset: 13 + bit_size: 1 + - name: CC2HF + description: Clear CPU2 Hold interrupt flag + bit_offset: 14 + bit_size: 1 fieldset/SR1: description: Power status register 1 fields: - - bit_offset: 0 - bit_size: 1 - description: Wakeup flag 1 - name: CWUF1 - - bit_offset: 1 - bit_size: 1 - description: Wakeup flag 2 - name: CWUF2 - - bit_offset: 2 - bit_size: 1 - description: Wakeup flag 3 - name: CWUF3 - - bit_offset: 3 - bit_size: 1 - description: Wakeup flag 4 - name: CWUF4 - - bit_offset: 4 - bit_size: 1 - description: Wakeup flag 5 - name: CWUF5 - - bit_offset: 7 - bit_size: 1 - description: Step Down converter forced in Bypass interrupt flag - name: SDFBF - - bit_offset: 8 - bit_size: 1 - description: BORH interrupt flag - name: BORHF - - bit_offset: 9 - bit_size: 1 - description: BLE wakeup interrupt flag - name: BLEWUF - - bit_offset: 10 - bit_size: 1 - description: 802.15.4 wakeup interrupt flag - name: _802WUF - - bit_offset: 11 - bit_size: 1 - description: Enable critical radio phase end of activity interrupt flag - name: CRPEF - - bit_offset: 12 - bit_size: 1 - description: BLE end of activity interrupt flag - name: BLEAF - - bit_offset: 13 - bit_size: 1 - description: 802.15.4 end of activity interrupt flag - name: AF802 - - bit_offset: 14 - bit_size: 1 - description: CPU2 Hold interrupt flag - name: C2HF - - bit_offset: 15 - bit_size: 1 - description: Internal Wakeup interrupt flag - name: WUFI + - name: CWUF1 + description: Wakeup flag 1 + bit_offset: 0 + bit_size: 1 + - name: CWUF2 + description: Wakeup flag 2 + bit_offset: 1 + bit_size: 1 + - name: CWUF3 + description: Wakeup flag 3 + bit_offset: 2 + bit_size: 1 + - name: CWUF4 + description: Wakeup flag 4 + bit_offset: 3 + bit_size: 1 + - name: CWUF5 + description: Wakeup flag 5 + bit_offset: 4 + bit_size: 1 + - name: SDFBF + description: Step Down converter forced in Bypass interrupt flag + bit_offset: 7 + bit_size: 1 + - name: BORHF + description: BORH interrupt flag + bit_offset: 8 + bit_size: 1 + - name: BLEWUF + description: BLE wakeup interrupt flag + bit_offset: 9 + bit_size: 1 + - name: _802WUF + description: 802.15.4 wakeup interrupt flag + bit_offset: 10 + bit_size: 1 + - name: CRPEF + description: Enable critical radio phase end of activity interrupt flag + bit_offset: 11 + bit_size: 1 + - name: BLEAF + description: BLE end of activity interrupt flag + bit_offset: 12 + bit_size: 1 + - name: AF802 + description: 802.15.4 end of activity interrupt flag + bit_offset: 13 + bit_size: 1 + - name: C2HF + description: CPU2 Hold interrupt flag + bit_offset: 14 + bit_size: 1 + - name: WUFI + description: Internal Wakeup interrupt flag + bit_offset: 15 + bit_size: 1 fieldset/SR2: description: Power status register 2 fields: - - bit_offset: 0 - bit_size: 1 - description: Step Down converter Bypass mode flag - name: SDBF - - bit_offset: 1 - bit_size: 1 - description: Step Down converter SMPS mode flag - name: SDSMPSF - - bit_offset: 8 - bit_size: 1 - description: Low-power regulator started - name: REGLPS - - bit_offset: 9 - bit_size: 1 - description: Low-power regulator flag - name: REGLPF - - bit_offset: 10 - bit_size: 1 - description: Voltage scaling flag - name: VOSF - - bit_offset: 11 - bit_size: 1 - description: Power voltage detector output - name: PVDO - - bit_offset: 12 - bit_size: 1 - description: 'Peripheral voltage monitoring output: VDDUSB vs. 1.2 V' - name: PVMO1 - - bit_offset: 14 - bit_size: 1 - description: 'Peripheral voltage monitoring output: VDDA vs. 1.62 V' - name: PVMO3 + - name: SDBF + description: Step Down converter Bypass mode flag + bit_offset: 0 + bit_size: 1 + - name: SDSMPSF + description: Step Down converter SMPS mode flag + bit_offset: 1 + bit_size: 1 + - name: REGLPS + description: Low-power regulator started + bit_offset: 8 + bit_size: 1 + - name: REGLPF + description: Low-power regulator flag + bit_offset: 9 + bit_size: 1 + - name: VOSF + description: Voltage scaling flag + bit_offset: 10 + bit_size: 1 + - name: PVDO + description: Power voltage detector output + bit_offset: 11 + bit_size: 1 + - name: PVMO1 + description: "Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" + bit_offset: 12 + bit_size: 1 + - name: PVMO3 + description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V" + bit_offset: 14 + bit_size: 1 diff --git a/data/registers/pwr_wl5.yaml b/data/registers/pwr_wl5.yaml index 97348b2..b4809d1 100644 --- a/data/registers/pwr_wl5.yaml +++ b/data/registers/pwr_wl5.yaml @@ -39,18 +39,18 @@ block/PWR: fieldset: CR5 - name: PUCR description: Power Port pull-up control register + array: + len: 8 + stride: 8 byte_offset: 32 fieldset: PCR - array: - len: 8 - stride: 8 - name: PDCR description: Power Port pull-down control register - byte_offset: 36 - fieldset: PCR array: len: 8 stride: 8 + byte_offset: 36 + fieldset: PCR - name: C2CR1 description: "Power CPU2 control register 1 [dual core device only]" byte_offset: 128 diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index 7bd3c81..3ce88bc 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -187,14 +187,14 @@ fieldset/APB1ENR: description: USB clock enable bit_offset: 23 bit_size: 1 - - name: CANEN - description: CAN clock enable - bit_offset: 25 - bit_size: 1 - name: CAN1EN description: CAN1 clock enable bit_offset: 25 bit_size: 1 + - name: CANEN + description: CAN clock enable + bit_offset: 25 + bit_size: 1 - name: CAN2EN description: CAN2 clock enable bit_offset: 26 @@ -294,14 +294,14 @@ fieldset/APB1RSTR: description: USB reset bit_offset: 23 bit_size: 1 - - name: CANRST - description: CAN reset - bit_offset: 25 - bit_size: 1 - name: CAN1RST description: CAN1 reset bit_offset: 25 bit_size: 1 + - name: CANRST + description: CAN reset + bit_offset: 25 + bit_size: 1 - name: CAN2RST description: CAN2 reset bit_offset: 26 @@ -572,16 +572,16 @@ fieldset/CFGR: bit_offset: 18 bit_size: 4 enum: PLLMUL - - name: USBPRE - description: USB prescaler - bit_offset: 22 - bit_size: 1 - enum: USBPRE - name: OTGFSPRE description: USB OTG FS prescaler bit_offset: 22 bit_size: 1 enum: OTGFSPRE + - name: USBPRE + description: USB prescaler + bit_offset: 22 + bit_size: 1 + enum: USBPRE - name: MCO description: Microcontroller clock output bit_offset: 24 diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3.yaml index 844bcd5..a709c25 100644 --- a/data/registers/rcc_f3.yaml +++ b/data/registers/rcc_f3.yaml @@ -117,14 +117,14 @@ fieldset/AHBENR: description: Touch sensing controller clock enable bit_offset: 24 bit_size: 1 - - name: ADC1EN - description: ADC 1 - bit_offset: 28 - bit_size: 1 - name: ADC12EN description: ADC1 and ADC2 clock enable bit_offset: 28 bit_size: 1 + - name: ADC1EN + description: ADC 1 + bit_offset: 28 + bit_size: 1 - name: ADC34EN description: ADC3 and ADC4 clock enable bit_offset: 29 @@ -172,14 +172,14 @@ fieldset/AHBRSTR: description: Touch sensing controller reset bit_offset: 24 bit_size: 1 - - name: ADC1RST - description: ADC1 reset - bit_offset: 28 - bit_size: 1 - name: ADC12RST description: ADC1 and ADC2 reset bit_offset: 28 bit_size: 1 + - name: ADC1RST + description: ADC1 reset + bit_offset: 28 + bit_size: 1 - name: ADC34RST description: ADC3 and ADC4 reset bit_offset: 29 @@ -283,14 +283,14 @@ fieldset/APB1ENR: description: DAC interface clock enable bit_offset: 29 bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable - bit_offset: 30 - bit_size: 1 - name: CECEN description: HDMI CEC interface clock enable bit_offset: 30 bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 30 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register (RCC_APB1RSTR) fields: @@ -390,14 +390,14 @@ fieldset/APB1RSTR: description: DAC interface reset bit_offset: 29 bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 30 - bit_size: 1 - name: CECRST description: HDMI CEC reset bit_offset: 30 bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 30 + bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register (RCC_APB2ENR) fields: @@ -655,13 +655,13 @@ fieldset/CFGR2: bit_offset: 0 bit_size: 4 enum: PREDIV - - name: ADC1PRES - description: ADC1 prescaler + - name: ADC12PRES + description: ADC1 and ADC2 prescaler bit_offset: 4 bit_size: 5 enum: ADCPRES - - name: ADC12PRES - description: ADC1 and ADC2 prescaler + - name: ADC1PRES + description: ADC1 prescaler bit_offset: 4 bit_size: 5 enum: ADCPRES @@ -688,16 +688,16 @@ fieldset/CFGR3: bit_offset: 5 bit_size: 1 enum: ICSW - - name: I2C3SW - description: I2C3 clock source selection - bit_offset: 6 - bit_size: 1 - enum: ICSW - name: CECSW description: HDMI CEC clock source selection bit_offset: 6 bit_size: 1 enum: CECSW + - name: I2C3SW + description: I2C3 clock source selection + bit_offset: 6 + bit_size: 1 + enum: ICSW - name: TIM1SW description: Timer1 clock source selection bit_offset: 8 diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index bbbbc59..1d3aae5 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -26,6 +26,10 @@ block/RCC: description: AHB2 peripheral reset register byte_offset: 20 fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 24 + fieldset: AHB3RSTR - name: APB1RSTR description: APB1 peripheral reset register byte_offset: 32 @@ -42,6 +46,10 @@ block/RCC: description: AHB2 peripheral clock enable register byte_offset: 52 fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 56 + fieldset: AHB3ENR - name: APB1ENR description: APB1 peripheral clock enable register byte_offset: 64 @@ -58,6 +66,10 @@ block/RCC: description: AHB2 peripheral clock enable in low power mode register byte_offset: 84 fieldset: AHB2LPENR + - name: AHB3LPENR + description: AHB3 peripheral clock enable in low power mode register + byte_offset: 88 + fieldset: AHB3LPENR - name: APB1LPENR description: APB1 peripheral clock enable in low power mode register byte_offset: 96 @@ -82,34 +94,22 @@ block/RCC: description: PLLI2S configuration register byte_offset: 132 fieldset: PLLI2SCFGR - - name: DCKCFGR - description: RCC Dedicated Clock Configuration Register - byte_offset: 140 - fieldset: DCKCFGR - - name: AHB3RSTR - description: AHB3 peripheral reset register - byte_offset: 24 - fieldset: AHB3RSTR - - name: AHB3ENR - description: AHB3 peripheral clock enable register - byte_offset: 56 - fieldset: AHB3ENR - - name: AHB3LPENR - description: AHB3 peripheral clock enable in low power mode register - byte_offset: 88 - fieldset: AHB3LPENR - - name: DCKCFGR2 - description: DCKCFGR2 register - byte_offset: 148 - fieldset: DCKCFGR2 - - name: CKGATENR - description: Clocks gated enable register - byte_offset: 144 - fieldset: CKGATENR - name: PLLSAICFGR description: RCC PLL configuration register byte_offset: 136 fieldset: PLLSAICFGR + - name: DCKCFGR + description: RCC Dedicated Clock Configuration Register + byte_offset: 140 + fieldset: DCKCFGR + - name: CKGATENR + description: Clocks gated enable register + byte_offset: 144 + fieldset: CKGATENR + - name: DCKCFGR2 + description: DCKCFGR2 register + byte_offset: 148 + fieldset: DCKCFGR2 fieldset/AHB1ENR: description: AHB1 peripheral clock register fields: @@ -133,14 +133,42 @@ fieldset/AHB1ENR: description: IO port E clock enable bit_offset: 4 bit_size: 1 + - name: GPIOFEN + description: IO port F clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 6 + bit_size: 1 - name: GPIOHEN description: IO port H clock enable bit_offset: 7 bit_size: 1 + - name: GPIOIEN + description: IO port I clock enable + bit_offset: 8 + bit_size: 1 + - name: GPIOJEN + description: IO port J clock enable + bit_offset: 9 + bit_size: 1 + - name: GPIOKEN + description: IO port K clock enable + bit_offset: 10 + bit_size: 1 - name: CRCEN description: CRC clock enable bit_offset: 12 bit_size: 1 + - name: BKPSRAMEN + description: Backup SRAM interface clock enable + bit_offset: 18 + bit_size: 1 + - name: CCMDATARAMEN + description: CCM data RAM clock enable + bit_offset: 20 + bit_size: 1 - name: DMA1EN description: DMA1 clock enable bit_offset: 21 @@ -149,21 +177,9 @@ fieldset/AHB1ENR: description: DMA2 clock enable bit_offset: 22 bit_size: 1 - - name: GPIOFEN - description: IO port F clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: IO port G clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOIEN - description: IO port I clock enable - bit_offset: 8 - bit_size: 1 - - name: BKPSRAMEN - description: Backup SRAM interface clock enable - bit_offset: 18 + - name: DMA2DEN + description: DMA2D clock enable + bit_offset: 23 bit_size: 1 - name: ETHMACEN description: Ethernet MAC clock enable @@ -189,22 +205,6 @@ fieldset/AHB1ENR: description: USB OTG HSULPI clock enable bit_offset: 30 bit_size: 1 - - name: GPIOJEN - description: IO port J clock enable - bit_offset: 9 - bit_size: 1 - - name: GPIOKEN - description: IO port K clock enable - bit_offset: 10 - bit_size: 1 - - name: DMA2DEN - description: DMA2D clock enable - bit_offset: 23 - bit_size: 1 - - name: CCMDATARAMEN - description: CCM data RAM clock enable - bit_offset: 20 - bit_size: 1 fieldset/AHB1LPENR: description: AHB1 peripheral clock enable in low power mode register fields: @@ -228,10 +228,30 @@ fieldset/AHB1LPENR: description: IO port E clock enable during Sleep mode bit_offset: 4 bit_size: 1 + - name: GPIOFLPEN + description: IO port F clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: IO port G clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 - name: GPIOHLPEN description: IO port H clock enable during Sleep mode bit_offset: 7 bit_size: 1 + - name: GPIOILPEN + description: IO port I clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: GPIOJLPEN + description: IO port J clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: GPIOKLPEN + description: IO port K clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 - name: CRCLPEN description: CRC clock enable during Sleep mode bit_offset: 12 @@ -244,6 +264,18 @@ fieldset/AHB1LPENR: description: SRAM 1interface clock enable during Sleep mode bit_offset: 16 bit_size: 1 + - name: SRAM2LPEN + description: SRAM 2 interface clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: BKPSRAMLPEN + description: Backup SRAM interface clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: SRAM3LPEN + description: SRAM 3 interface clock enable during Sleep mode + bit_offset: 19 + bit_size: 1 - name: DMA1LPEN description: DMA1 clock enable during Sleep mode bit_offset: 21 @@ -252,25 +284,9 @@ fieldset/AHB1LPENR: description: DMA2 clock enable during Sleep mode bit_offset: 22 bit_size: 1 - - name: GPIOFLPEN - description: IO port F clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: GPIOGLPEN - description: IO port G clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: GPIOILPEN - description: IO port I clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: SRAM2LPEN - description: SRAM 2 interface clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: BKPSRAMLPEN - description: Backup SRAM interface clock enable during Sleep mode - bit_offset: 18 + - name: DMA2DLPEN + description: DMA2D clock enable during Sleep mode + bit_offset: 23 bit_size: 1 - name: ETHMACLPEN description: Ethernet MAC clock enable during Sleep mode @@ -300,22 +316,6 @@ fieldset/AHB1LPENR: description: RNG clock enable during sleep mode bit_offset: 31 bit_size: 1 - - name: GPIOJLPEN - description: IO port J clock enable during Sleep mode - bit_offset: 9 - bit_size: 1 - - name: GPIOKLPEN - description: IO port K clock enable during Sleep mode - bit_offset: 10 - bit_size: 1 - - name: SRAM3LPEN - description: SRAM 3 interface clock enable during Sleep mode - bit_offset: 19 - bit_size: 1 - - name: DMA2DLPEN - description: DMA2D clock enable during Sleep mode - bit_offset: 23 - bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: @@ -339,10 +339,30 @@ fieldset/AHB1RSTR: description: IO port E reset bit_offset: 4 bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 6 + bit_size: 1 - name: GPIOHRST description: IO port H reset bit_offset: 7 bit_size: 1 + - name: GPIOIRST + description: IO port I reset + bit_offset: 8 + bit_size: 1 + - name: GPIOJRST + description: IO port J reset + bit_offset: 9 + bit_size: 1 + - name: GPIOKRST + description: IO port K reset + bit_offset: 10 + bit_size: 1 - name: CRCRST description: CRC reset bit_offset: 12 @@ -355,17 +375,9 @@ fieldset/AHB1RSTR: description: DMA2 reset bit_offset: 22 bit_size: 1 - - name: GPIOFRST - description: IO port F reset - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 6 - bit_size: 1 - - name: GPIOIRST - description: IO port I reset - bit_offset: 8 + - name: DMA2DRST + description: DMA2D reset + bit_offset: 23 bit_size: 1 - name: ETHMACRST description: Ethernet MAC reset @@ -375,33 +387,13 @@ fieldset/AHB1RSTR: description: USB OTG HS module reset bit_offset: 29 bit_size: 1 - - name: GPIOJRST - description: IO port J reset - bit_offset: 9 - bit_size: 1 - - name: GPIOKRST - description: IO port K reset - bit_offset: 10 - bit_size: 1 - - name: DMA2DRST - description: DMA2D reset - bit_offset: 23 - bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - - name: USB_OTG_FSEN - description: USB OTG FS clock enable - bit_offset: 7 - bit_size: 1 - name: DCMIEN description: Camera interface enable bit_offset: 0 bit_size: 1 - - name: RNGEN - description: Random number generator clock enable - bit_offset: 6 - bit_size: 1 - name: CRYPEN description: CRYP clock enable bit_offset: 4 @@ -410,21 +402,21 @@ fieldset/AHB2ENR: description: Hash modules clock enable bit_offset: 5 bit_size: 1 + - name: RNGEN + description: Random number generator clock enable + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSEN + description: USB OTG FS clock enable + bit_offset: 7 + bit_size: 1 fieldset/AHB2LPENR: description: AHB2 peripheral clock enable in low power mode register fields: - - name: USB_OTG_FSLPEN - description: USB OTG FS clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - name: DCMILPEN description: Camera interface enable during Sleep mode bit_offset: 0 bit_size: 1 - - name: RNGLPEN - description: Random number generator clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - name: FSMCLPEN description: Flexible memory controller module clock enable during Sleep mode bit_offset: 0 @@ -441,21 +433,21 @@ fieldset/AHB2LPENR: description: Hash modules clock enable during Sleep mode bit_offset: 5 bit_size: 1 + - name: RNGLPEN + description: Random number generator clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSLPEN + description: USB OTG FS clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - - name: USB_OTG_FSRST - description: USB OTG FS module reset - bit_offset: 7 - bit_size: 1 - name: DCMIRST description: Camera interface reset bit_offset: 0 bit_size: 1 - - name: RNGRST - description: Random number generator module reset - bit_offset: 6 - bit_size: 1 - name: CRYPRST description: CRYP module reset bit_offset: 4 @@ -464,9 +456,21 @@ fieldset/AHB2RSTR: description: Hash module reset bit_offset: 5 bit_size: 1 + - name: RNGRST + description: Random number generator module reset + bit_offset: 6 + bit_size: 1 + - name: USB_OTG_FSRST + description: USB OTG FS module reset + bit_offset: 7 + bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: + - name: FMCEN + description: Flexible static memory controller module clock enable + bit_offset: 0 + bit_size: 1 - name: FSMCEN description: Flexible static memory controller module clock enable bit_offset: 0 @@ -475,13 +479,13 @@ fieldset/AHB3ENR: description: QUADSPI memory controller module clock enable bit_offset: 1 bit_size: 1 - - name: FMCEN - description: Flexible static memory controller module clock enable - bit_offset: 0 - bit_size: 1 fieldset/AHB3LPENR: description: AHB3 peripheral clock enable in low power mode register fields: + - name: FMCLPEN + description: Flexible static memory controller module clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 - name: FSMCLPEN description: Flexible static memory controller module clock enable during Sleep mode bit_offset: 0 @@ -490,13 +494,13 @@ fieldset/AHB3LPENR: description: QUADSPI memory controller module clock enable during Sleep mode bit_offset: 1 bit_size: 1 - - name: FMCLPEN - description: Flexible static memory controller module clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: + - name: FMCRST + description: Flexible static memory controller module reset + bit_offset: 0 + bit_size: 1 - name: FSMCRST description: Flexible static memory controller module reset bit_offset: 0 @@ -505,10 +509,6 @@ fieldset/AHB3RSTR: description: QUADSPI module reset bit_offset: 1 bit_size: 1 - - name: FMCRST - description: Flexible static memory controller module reset - bit_offset: 0 - bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: @@ -528,38 +528,6 @@ fieldset/APB1ENR: description: TIM5 clock enable bit_offset: 3 bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI3 clock enable - bit_offset: 15 - bit_size: 1 - - name: USART2EN - description: USART 2 clock enable - bit_offset: 17 - bit_size: 1 - - name: I2C1EN - description: I2C1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 clock enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable - bit_offset: 23 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - name: TIM6EN description: TIM6 clock enable bit_offset: 4 @@ -580,6 +548,34 @@ fieldset/APB1ENR: description: TIM14 clock enable bit_offset: 8 bit_size: 1 + - name: LPTIM1EN + description: LPTIM1 clock enable + bit_offset: 9 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 clock enable + bit_offset: 15 + bit_size: 1 + - name: SPDIFEN + description: SPDIF-IN clock enable + bit_offset: 16 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 - name: USART3EN description: USART3 clock enable bit_offset: 18 @@ -592,6 +588,22 @@ fieldset/APB1ENR: description: UART5 clock enable bit_offset: 20 bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 23 + bit_size: 1 + - name: FMPI2C1EN + description: FMPI2C1 clock enable + bit_offset: 24 + bit_size: 1 - name: CAN1EN description: CAN 1 clock enable bit_offset: 25 @@ -600,26 +612,22 @@ fieldset/APB1ENR: description: CAN 2 clock enable bit_offset: 26 bit_size: 1 - - name: DACEN - description: DAC interface clock enable - bit_offset: 29 - bit_size: 1 - - name: LPTIM1EN - description: LPTIM1 clock enable - bit_offset: 9 - bit_size: 1 - - name: RTCAPBEN - description: RTC APB clock enable - bit_offset: 10 - bit_size: 1 - - name: FMPI2C1EN - description: FMPI2C1 clock enable - bit_offset: 24 - bit_size: 1 - name: CAN3EN description: CAN 3 clock enable bit_offset: 27 bit_size: 1 + - name: CECEN + description: CEC interface clock enable + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 - name: UART7EN description: UART7 clock enable bit_offset: 30 @@ -628,14 +636,6 @@ fieldset/APB1ENR: description: UART8 clock enable bit_offset: 31 bit_size: 1 - - name: SPDIFEN - description: SPDIF-IN clock enable - bit_offset: 16 - bit_size: 1 - - name: CECEN - description: CEC interface clock enable - bit_offset: 27 - bit_size: 1 fieldset/APB1LPENR: description: APB1 peripheral clock enable in low power mode register fields: @@ -655,38 +655,6 @@ fieldset/APB1LPENR: description: TIM5 clock enable during Sleep mode bit_offset: 3 bit_size: 1 - - name: WWDGLPEN - description: Window watchdog clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI2LPEN - description: SPI2 clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: SPI3LPEN - description: SPI3 clock enable during Sleep mode - bit_offset: 15 - bit_size: 1 - - name: USART2LPEN - description: USART2 clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: I2C1LPEN - description: I2C1 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: I2C2LPEN - description: I2C2 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: I2C3LPEN - description: I2C3 clock enable during Sleep mode - bit_offset: 23 - bit_size: 1 - - name: PWRLPEN - description: Power interface clock enable during Sleep mode - bit_offset: 28 - bit_size: 1 - name: TIM6LPEN description: TIM6 clock enable during Sleep mode bit_offset: 4 @@ -707,6 +675,34 @@ fieldset/APB1LPENR: description: TIM14 clock enable during Sleep mode bit_offset: 8 bit_size: 1 + - name: LPTIM1LPEN + description: LPTIM1 clock enable during sleep mode + bit_offset: 9 + bit_size: 1 + - name: RTCAPBLPEN + description: RTC APB clock enable during sleep mode + bit_offset: 10 + bit_size: 1 + - name: WWDGLPEN + description: Window watchdog clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: SPI3 clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: SPDIFLPEN + description: SPDIF clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: USART2LPEN + description: USART2 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 - name: USART3LPEN description: USART3 clock enable during Sleep mode bit_offset: 18 @@ -719,6 +715,22 @@ fieldset/APB1LPENR: description: UART5 clock enable during Sleep mode bit_offset: 20 bit_size: 1 + - name: I2C1LPEN + description: I2C1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: I2C3LPEN + description: I2C3 clock enable during Sleep mode + bit_offset: 23 + bit_size: 1 + - name: FMPI2C1LPEN + description: FMPI2C1 clock enable during Sleep + bit_offset: 24 + bit_size: 1 - name: CAN1LPEN description: CAN 1 clock enable during Sleep mode bit_offset: 25 @@ -727,26 +739,22 @@ fieldset/APB1LPENR: description: CAN 2 clock enable during Sleep mode bit_offset: 26 bit_size: 1 - - name: DACLPEN - description: DAC interface clock enable during Sleep mode - bit_offset: 29 - bit_size: 1 - - name: LPTIM1LPEN - description: LPTIM1 clock enable during sleep mode - bit_offset: 9 - bit_size: 1 - - name: RTCAPBLPEN - description: RTC APB clock enable during sleep mode - bit_offset: 10 - bit_size: 1 - - name: FMPI2C1LPEN - description: FMPI2C1 clock enable during Sleep - bit_offset: 24 - bit_size: 1 - name: CAN3LPEN description: CAN3 clock enable during Sleep mode bit_offset: 27 bit_size: 1 + - name: CECLPEN + description: CEC clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: PWRLPEN + description: Power interface clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: DACLPEN + description: DAC interface clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 - name: UART7LPEN description: UART7 clock enable during Sleep mode bit_offset: 30 @@ -755,14 +763,6 @@ fieldset/APB1LPENR: description: UART8 clock enable during Sleep mode bit_offset: 31 bit_size: 1 - - name: SPDIFLPEN - description: SPDIF clock enable during Sleep mode - bit_offset: 16 - bit_size: 1 - - name: CECLPEN - description: CEC clock enable during Sleep mode - bit_offset: 27 - bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: @@ -782,38 +782,6 @@ fieldset/APB1RSTR: description: TIM5 reset bit_offset: 3 bit_size: 1 - - name: WWDGRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - - name: SPI2RST - description: SPI 2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI 3 reset - bit_offset: 15 - bit_size: 1 - - name: USART2RST - description: USART 2 reset - bit_offset: 17 - bit_size: 1 - - name: I2C1RST - description: I2C 1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C 2 reset - bit_offset: 22 - bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 23 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - name: TIM6RST description: TIM6 reset bit_offset: 4 @@ -834,6 +802,30 @@ fieldset/APB1RSTR: description: TIM14 reset bit_offset: 8 bit_size: 1 + - name: LPTIM1RST + description: LPTIM1 reset + bit_offset: 9 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI 2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI 3 reset + bit_offset: 15 + bit_size: 1 + - name: SPDIFRST + description: SPDIF-IN reset + bit_offset: 16 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 - name: USART3RST description: USART 3 reset bit_offset: 18 @@ -846,6 +838,22 @@ fieldset/APB1RSTR: description: UART 5 reset bit_offset: 20 bit_size: 1 + - name: I2C1RST + description: I2C 1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C 2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: FMPI2C1RST + description: FMPI2C1 reset + bit_offset: 24 + bit_size: 1 - name: CAN1RST description: CAN1 reset bit_offset: 25 @@ -854,22 +862,18 @@ fieldset/APB1RSTR: description: CAN2 reset bit_offset: 26 bit_size: 1 - - name: DACRST - description: DAC reset - bit_offset: 29 - bit_size: 1 - - name: LPTIM1RST - description: LPTIM1 reset - bit_offset: 9 - bit_size: 1 - - name: FMPI2C1RST - description: FMPI2C1 reset - bit_offset: 24 - bit_size: 1 - name: CAN3RST description: CAN 3 reset bit_offset: 27 bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC reset + bit_offset: 29 + bit_size: 1 - name: UART7RST description: UART 7 reset bit_offset: 30 @@ -878,10 +882,6 @@ fieldset/APB1RSTR: description: UART 8 reset bit_offset: 31 bit_size: 1 - - name: SPDIFRST - description: SPDIF-IN reset - bit_offset: 16 - bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: @@ -889,6 +889,10 @@ fieldset/APB2ENR: description: TIM1 clock enable bit_offset: 0 bit_size: 1 + - name: TIM8EN + description: TIM8 clock enable + bit_offset: 1 + bit_size: 1 - name: USART1EN description: USART1 clock enable bit_offset: 4 @@ -897,10 +901,26 @@ fieldset/APB2ENR: description: USART6 clock enable bit_offset: 5 bit_size: 1 + - name: UART9EN + description: UART9 clock enable + bit_offset: 6 + bit_size: 1 + - name: UART10EN + description: UART10 clock enable + bit_offset: 7 + bit_size: 1 - name: ADC1EN description: ADC1 clock enable bit_offset: 8 bit_size: 1 + - name: ADC2EN + description: ADC2 clock enable + bit_offset: 9 + bit_size: 1 + - name: ADC3EN + description: ADC3 clock enable + bit_offset: 10 + bit_size: 1 - name: SDIOEN description: SDIO clock enable bit_offset: 11 @@ -917,6 +937,10 @@ fieldset/APB2ENR: description: System configuration controller clock enable bit_offset: 14 bit_size: 1 + - name: EXTITEN + description: EXTI ans external IT clock enable + bit_offset: 15 + bit_size: 1 - name: TIM9EN description: TIM9 clock enable bit_offset: 16 @@ -929,58 +953,34 @@ fieldset/APB2ENR: description: TIM11 clock enable bit_offset: 18 bit_size: 1 - - name: TIM8EN - description: TIM8 clock enable - bit_offset: 1 - bit_size: 1 - - name: ADC2EN - description: ADC2 clock enable - bit_offset: 9 - bit_size: 1 - - name: ADC3EN - description: ADC3 clock enable - bit_offset: 10 - bit_size: 1 - - name: EXTITEN - description: EXTI ans external IT clock enable - bit_offset: 15 - bit_size: 1 - name: SPI5EN description: SPI5 clock enable bit_offset: 20 bit_size: 1 - - name: DFSDMEN - description: DFSDMEN - bit_offset: 24 - bit_size: 1 - - name: UART9EN - description: UART9 clock enable - bit_offset: 6 - bit_size: 1 - - name: UART10EN - description: UART10 clock enable - bit_offset: 7 - bit_size: 1 - - name: SAI1EN - description: SAI 1 clock enable - bit_offset: 22 - bit_size: 1 - - name: DFSDM2EN - description: DFSDM2 clock enable - bit_offset: 25 - bit_size: 1 - name: SPI6EN description: SPI6 clock enable bit_offset: 21 bit_size: 1 - - name: LTDCEN - description: LTDC clock enable - bit_offset: 26 + - name: SAI1EN + description: SAI 1 clock enable + bit_offset: 22 bit_size: 1 - name: SAI2EN description: SAI2 clock enable bit_offset: 23 bit_size: 1 + - name: DFSDMEN + description: DFSDMEN + bit_offset: 24 + bit_size: 1 + - name: DFSDM2EN + description: DFSDM2 clock enable + bit_offset: 25 + bit_size: 1 + - name: LTDCEN + description: LTDC clock enable + bit_offset: 26 + bit_size: 1 - name: DSIEN description: DSI clocks enable bit_offset: 27 @@ -992,6 +992,10 @@ fieldset/APB2LPENR: description: TIM1 clock enable during Sleep mode bit_offset: 0 bit_size: 1 + - name: TIM8LPEN + description: TIM8 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 - name: USART1LPEN description: USART1 clock enable during Sleep mode bit_offset: 4 @@ -1000,10 +1004,26 @@ fieldset/APB2LPENR: description: USART6 clock enable during Sleep mode bit_offset: 5 bit_size: 1 + - name: UART9LPEN + description: UART9 clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: UART10LPEN + description: UART10 clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 - name: ADC1LPEN description: ADC1 clock enable during Sleep mode bit_offset: 8 bit_size: 1 + - name: ADC2LPEN + description: ADC2 clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: ADC3LPEN + description: ADC 3 clock enable during Sleep mode + bit_offset: 10 + bit_size: 1 - name: SDIOLPEN description: SDIO clock enable during Sleep mode bit_offset: 11 @@ -1020,6 +1040,10 @@ fieldset/APB2LPENR: description: System configuration controller clock enable during Sleep mode bit_offset: 14 bit_size: 1 + - name: EXTITLPEN + description: EXTI and External IT clock enable during sleep mode + bit_offset: 15 + bit_size: 1 - name: TIM9LPEN description: TIM9 clock enable during sleep mode bit_offset: 16 @@ -1032,58 +1056,34 @@ fieldset/APB2LPENR: description: TIM11 clock enable during Sleep mode bit_offset: 18 bit_size: 1 - - name: TIM8LPEN - description: TIM8 clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: ADC2LPEN - description: ADC2 clock enable during Sleep mode - bit_offset: 9 - bit_size: 1 - - name: ADC3LPEN - description: ADC 3 clock enable during Sleep mode - bit_offset: 10 - bit_size: 1 - - name: EXTITLPEN - description: EXTI and External IT clock enable during sleep mode - bit_offset: 15 - bit_size: 1 - name: SPI5LPEN description: SPI5 clock enable during Sleep mode bit_offset: 20 bit_size: 1 - - name: DFSDMLPEN - description: DFSDMLPEN - bit_offset: 24 - bit_size: 1 - - name: UART9LPEN - description: UART9 clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: UART10LPEN - description: UART10 clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - - name: SAI1LPEN - description: SAI1 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: DFSDM2LPEN - description: DFSDM2 clock enable during Sleep mode - bit_offset: 25 - bit_size: 1 - name: SPI6LPEN description: SPI 6 clock enable during Sleep mode bit_offset: 21 bit_size: 1 - - name: LTDCLPEN - description: LTDC clock enable during Sleep mode - bit_offset: 26 + - name: SAI1LPEN + description: SAI1 clock enable during Sleep mode + bit_offset: 22 bit_size: 1 - name: SAI2LPEN description: SAI2 clock enable bit_offset: 23 bit_size: 1 + - name: DFSDMLPEN + description: DFSDMLPEN + bit_offset: 24 + bit_size: 1 + - name: DFSDM2LPEN + description: DFSDM2 clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: LTDCLPEN + description: LTDC clock enable during Sleep mode + bit_offset: 26 + bit_size: 1 - name: DSILPEN description: DSI clocks enable during Sleep mode bit_offset: 27 @@ -1095,6 +1095,10 @@ fieldset/APB2RSTR: description: TIM1 reset bit_offset: 0 bit_size: 1 + - name: TIM8RST + description: TIM8 reset + bit_offset: 1 + bit_size: 1 - name: USART1RST description: USART1 reset bit_offset: 4 @@ -1103,6 +1107,14 @@ fieldset/APB2RSTR: description: USART6 reset bit_offset: 5 bit_size: 1 + - name: UART9RST + description: UART9 reset + bit_offset: 6 + bit_size: 1 + - name: UART10RST + description: UART10 reset + bit_offset: 7 + bit_size: 1 - name: ADCRST description: ADC interface reset (common to all ADCs) bit_offset: 8 @@ -1135,46 +1147,34 @@ fieldset/APB2RSTR: description: TIM11 reset bit_offset: 18 bit_size: 1 - - name: TIM8RST - description: TIM8 reset - bit_offset: 1 - bit_size: 1 - name: SPI5RST description: SPI5 reset bit_offset: 20 bit_size: 1 - - name: DFSDMRST - description: DFSDMRST - bit_offset: 24 - bit_size: 1 - - name: UART9RST - description: UART9 reset - bit_offset: 6 - bit_size: 1 - - name: UART10RST - description: UART10 reset - bit_offset: 7 - bit_size: 1 - - name: SAI1RST - description: SAI1 reset - bit_offset: 22 - bit_size: 1 - - name: DFSDM2RST - description: DFSDM2 reset - bit_offset: 25 - bit_size: 1 - name: SPI6RST description: SPI6 reset bit_offset: 21 bit_size: 1 - - name: LTDCRST - description: LTDC reset - bit_offset: 26 + - name: SAI1RST + description: SAI1 reset + bit_offset: 22 bit_size: 1 - name: SAI2RST description: SAI2 reset bit_offset: 23 bit_size: 1 + - name: DFSDMRST + description: DFSDMRST + bit_offset: 24 + bit_size: 1 + - name: DFSDM2RST + description: DFSDM2 reset + bit_offset: 25 + bit_size: 1 + - name: LTDCRST + description: LTDC reset + bit_offset: 26 + bit_size: 1 - name: DSIRST description: DSI host reset bit_offset: 27 @@ -1194,6 +1194,11 @@ fieldset/BDCR: description: External low-speed oscillator bypass bit_offset: 2 bit_size: 1 + - name: LSEMOD + description: External low-speed oscillator bypass + bit_offset: 3 + bit_size: 1 + enum: LSEMOD - name: RTCSEL description: RTC clock source selection bit_offset: 8 @@ -1207,11 +1212,6 @@ fieldset/BDCR: description: Backup domain software reset bit_offset: 16 bit_size: 1 - - name: LSEMOD - description: External low-speed oscillator bypass - bit_offset: 3 - bit_size: 1 - enum: LSEMOD fieldset/CFGR: description: clock configuration register fields: @@ -1230,6 +1230,14 @@ fieldset/CFGR: bit_offset: 4 bit_size: 4 enum: HPRE + - name: MCO1EN + description: MCO output enable + bit_offset: 8 + bit_size: 1 + - name: MCO2EN + description: MCO output enable + bit_offset: 9 + bit_size: 1 - name: PPRE1 description: APB Low speed prescaler (APB1) bit_offset: 10 @@ -1269,14 +1277,6 @@ fieldset/CFGR: bit_offset: 30 bit_size: 2 enum: MCO2 - - name: MCO1EN - description: MCO output enable - bit_offset: 8 - bit_size: 1 - - name: MCO2EN - description: MCO output enable - bit_offset: 9 - bit_size: 1 fieldset/CIR: description: clock interrupt register fields: @@ -1304,6 +1304,10 @@ fieldset/CIR: description: PLLI2S ready interrupt flag bit_offset: 5 bit_size: 1 + - name: PLLSAIRDYF + description: PLLSAI ready interrupt flag + bit_offset: 6 + bit_size: 1 - name: CSSF description: Clock security system interrupt flag bit_offset: 7 @@ -1332,6 +1336,10 @@ fieldset/CIR: description: PLLI2S ready interrupt enable bit_offset: 13 bit_size: 1 + - name: PLLSAIRDYIE + description: PLLSAI Ready Interrupt Enable + bit_offset: 14 + bit_size: 1 - name: LSIRDYC description: LSI ready interrupt clear bit_offset: 16 @@ -1356,22 +1364,14 @@ fieldset/CIR: description: PLLI2S ready interrupt clear bit_offset: 21 bit_size: 1 - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 23 - bit_size: 1 - - name: PLLSAIRDYF - description: PLLSAI ready interrupt flag - bit_offset: 6 - bit_size: 1 - - name: PLLSAIRDYIE - description: PLLSAI Ready Interrupt Enable - bit_offset: 14 - bit_size: 1 - name: PLLSAIRDYC description: PLLSAI Ready Interrupt Clear bit_offset: 22 bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 fieldset/CKGATENR: description: clocks gated enable register fields: @@ -1512,36 +1512,11 @@ fieldset/CSR: fieldset/DCKCFGR: description: Dedicated Clock Configuration Register fields: - - name: TIMPRE - description: Timers clocks prescalers selection - bit_offset: 24 - bit_size: 1 - enum: TIMPRE - - name: I2SSRC - description: I2SSRC - bit_offset: 25 - bit_size: 2 - enum: ISSRC - - name: CKDFSDM1ASEL - description: DFSDM1 audio clock selection - bit_offset: 15 + - name: PLLI2SDIVQ + description: PLLI2S division factor for SAI1 clock + bit_offset: 0 bit_size: 5 - enum: CKDFSDMASEL - - name: I2S1SRC - description: I2S APB1 clocks source selection (I2S2/3) - bit_offset: 25 - bit_size: 2 - enum: I2S1SRC - - name: I2S2SRC - description: I2S APB2 clocks source selection (I2S1/4/5) - bit_offset: 27 - bit_size: 2 - enum: I2S1SRC - - name: CKDFSDM1SEL - description: DFSDM1 Kernel clock selection - bit_offset: 31 - bit_size: 1 - enum: CKDFSDMSEL + enum: PLLISDIVQ - name: PLLI2SDIVR description: PLLI2S division factor for SAI1 A/B clock bit_offset: 0 @@ -1552,51 +1527,71 @@ fieldset/DCKCFGR: bit_offset: 8 bit_size: 5 enum: PLLDIVR - - name: CKDFSDM2ASEL - description: DFSDM2 audio clock selection - bit_offset: 14 - bit_size: 1 - enum: CKDFSDMASEL - - name: SAI1ASRC - description: SAI1-A clock source selection - bit_offset: 20 - bit_size: 2 - enum: SAIASRC - - name: SAI1BSRC - description: SAI1-B clock source selection - bit_offset: 22 - bit_size: 2 - enum: SAIBSRC - - name: PLLI2SDIVQ - description: PLLI2S division factor for SAI1 clock - bit_offset: 0 - bit_size: 5 - enum: PLLISDIVQ - name: PLLSAIDIVQ description: PLLSAI division factor for SAI1 clock bit_offset: 8 bit_size: 5 enum: PLLSAIDIVQ + - name: CKDFSDM2ASEL + description: DFSDM2 audio clock selection + bit_offset: 14 + bit_size: 1 + enum: CKDFSDMASEL + - name: CKDFSDM1ASEL + description: DFSDM1 audio clock selection + bit_offset: 15 + bit_size: 5 + enum: CKDFSDMASEL - name: PLLSAIDIVR description: division factor for LCD_CLK bit_offset: 16 bit_size: 2 enum: PLLSAIDIVR + - name: SAI1ASRC + description: SAI1-A clock source selection + bit_offset: 20 + bit_size: 2 + enum: SAIASRC - name: SAI1SRC description: SAI1 clock source selection bit_offset: 20 bit_size: 2 enum: SAI1SRC + - name: SAI1BSRC + description: SAI1-B clock source selection + bit_offset: 22 + bit_size: 2 + enum: SAIBSRC - name: SAI2SRC description: SAI2 clock source selection bit_offset: 22 bit_size: 2 enum: SAI2SRC + - name: TIMPRE + description: Timers clocks prescalers selection + bit_offset: 24 + bit_size: 1 + enum: TIMPRE + - name: I2S1SRC + description: I2S APB1 clocks source selection (I2S2/3) + bit_offset: 25 + bit_size: 2 + enum: I2S1SRC + - name: I2SSRC + description: I2SSRC + bit_offset: 25 + bit_size: 2 + enum: ISSRC - name: CK48MSEL description: 48 MHz clock source selection bit_offset: 27 bit_size: 1 enum: CKMSEL + - name: I2S2SRC + description: I2S APB2 clocks source selection (I2S1/4/5) + bit_offset: 27 + bit_size: 2 + enum: I2S1SRC - name: SDIOSEL description: SDIO clock source selection bit_offset: 28 @@ -1607,6 +1602,11 @@ fieldset/DCKCFGR: bit_offset: 29 bit_size: 1 enum: DSISEL + - name: CKDFSDM1SEL + description: DFSDM1 Kernel clock selection + bit_offset: 31 + bit_size: 1 + enum: CKDFSDMSEL fieldset/DCKCFGR2: description: dedicated clocks configuration register 2 fields: @@ -1615,11 +1615,11 @@ fieldset/DCKCFGR2: bit_offset: 22 bit_size: 2 enum: FMPICSEL - - name: LPTIM1SEL - description: LPTIM1SEL - bit_offset: 30 - bit_size: 2 - enum: LPTIMSEL + - name: CECSEL + description: HDMI CEC clock source selection + bit_offset: 26 + bit_size: 1 + enum: CECSEL - name: CK48MSEL description: SDIO/USBFS clock selection bit_offset: 27 @@ -1630,16 +1630,16 @@ fieldset/DCKCFGR2: bit_offset: 28 bit_size: 1 enum: SDIOSEL - - name: CECSEL - description: HDMI CEC clock source selection - bit_offset: 26 - bit_size: 1 - enum: CECSEL - name: SPDIFRXSEL description: SPDIF clock selection bit_offset: 29 bit_size: 1 enum: SPDIFRXSEL + - name: LPTIM1SEL + description: LPTIM1SEL + bit_offset: 30 + bit_size: 2 + enum: LPTIMSEL fieldset/PLLCFGR: description: PLL configuration register fields: @@ -1672,18 +1672,19 @@ fieldset/PLLCFGR: fieldset/PLLI2SCFGR: description: PLLI2S configuration register fields: - - name: PLLI2SN - description: PLLI2S multiplication factor for VCO - bit_offset: 6 - bit_size: 9 - - name: PLLI2SR - description: PLLI2S division factor for I2S clocks - bit_offset: 28 - bit_size: 3 - name: PLLI2SM description: Division factor for the audio PLL (PLLI2S) input clock bit_offset: 0 bit_size: 6 + - name: PLLI2SN + description: PLLI2S multiplication factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLI2SP + description: PLLI2S division factor for SPDIF-IN clock + bit_offset: 16 + bit_size: 2 + enum: PLLISP - name: PLLI2SSRC description: PLLI2S entry clock source bit_offset: 22 @@ -1693,18 +1694,26 @@ fieldset/PLLI2SCFGR: description: PLLI2S division factor for USB OTG FS/SDIO/RNG clock bit_offset: 24 bit_size: 4 - - name: PLLI2SP - description: PLLI2S division factor for SPDIF-IN clock - bit_offset: 16 - bit_size: 2 - enum: PLLISP + - name: PLLI2SR + description: PLLI2S division factor for I2S clocks + bit_offset: 28 + bit_size: 3 fieldset/PLLSAICFGR: description: PLL configuration register fields: + - name: PLLSAIM + description: Division factor for audio PLLSAI input clock + bit_offset: 0 + bit_size: 6 - name: PLLSAIN description: PLLSAI division factor for VCO bit_offset: 6 bit_size: 9 + - name: PLLSAIP + description: PLLSAI division factor for 48 MHz clock + bit_offset: 16 + bit_size: 2 + enum: PLLSAIP - name: PLLSAIQ description: PLLSAI division factor for SAI1 clock bit_offset: 24 @@ -1713,15 +1722,6 @@ fieldset/PLLSAICFGR: description: PLLSAI division factor for LCD clock bit_offset: 28 bit_size: 3 - - name: PLLSAIM - description: Division factor for audio PLLSAI input clock - bit_offset: 0 - bit_size: 6 - - name: PLLSAIP - description: PLLSAI division factor for 48 MHz clock - bit_offset: 16 - bit_size: 2 - enum: PLLSAIP fieldset/SSCGR: description: spread spectrum clock generation register fields: diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index 2b990b1..cbdb4cc 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -10,6 +10,10 @@ block/RCC: description: Internal clock sources calibration register byte_offset: 4 fieldset: ICSCR + - name: CRRCR + description: Clock recovery RC register + byte_offset: 8 + fieldset: CRRCR - name: CFGR description: Clock configuration register byte_offset: 12 @@ -85,10 +89,6 @@ block/RCC: description: Control and status register byte_offset: 80 fieldset: CSR - - name: CRRCR - description: Clock recovery RC register - byte_offset: 8 - fieldset: CRRCR fieldset/AHBENR: description: AHB peripheral clock enable register fields: @@ -104,10 +104,6 @@ fieldset/AHBENR: description: CRC clock enable bit_offset: 12 bit_size: 1 - - name: CRYPEN - description: Crypto clock enable - bit_offset: 24 - bit_size: 1 - name: TOUCHEN description: Touch Sensing clock enable bit_offset: 16 @@ -116,6 +112,10 @@ fieldset/AHBENR: description: Random Number Generator clock enable bit_offset: 20 bit_size: 1 + - name: CRYPEN + description: Crypto clock enable + bit_offset: 24 + bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral reset register fields: @@ -131,10 +131,6 @@ fieldset/AHBRSTR: description: Test integration module reset bit_offset: 12 bit_size: 1 - - name: CRYPRST - description: Crypto module reset - bit_offset: 24 - bit_size: 1 - name: TOUCHRST description: Touch Sensing reset bit_offset: 16 @@ -143,6 +139,10 @@ fieldset/AHBRSTR: description: Random Number Generator module reset bit_offset: 20 bit_size: 1 + - name: CRYPRST + description: Crypto module reset + bit_offset: 24 + bit_size: 1 fieldset/AHBSMENR: description: AHB peripheral clock enable in sleep mode register fields: @@ -162,10 +162,6 @@ fieldset/AHBSMENR: description: CRC clock enable during sleep mode bit_offset: 12 bit_size: 1 - - name: CRYPSMEN - description: Crypto clock enable during sleep mode - bit_offset: 24 - bit_size: 1 - name: TOUCHSMEN description: Touch Sensing clock enable during sleep mode bit_offset: 16 @@ -174,6 +170,10 @@ fieldset/AHBSMENR: description: Random Number Generator clock enable during sleep mode bit_offset: 20 bit_size: 1 + - name: CRYPSMEN + description: Crypto clock enable during sleep mode + bit_offset: 24 + bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: @@ -181,6 +181,10 @@ fieldset/APB1ENR: description: Timer2 clock enable bit_offset: 0 bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enbale + bit_offset: 1 + bit_size: 1 - name: TIM6EN description: Timer 6 clock enable bit_offset: 4 @@ -221,22 +225,6 @@ fieldset/APB1ENR: description: I2C2 clock enable bit_offset: 22 bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable - bit_offset: 30 - bit_size: 1 - - name: LPTIM1EN - description: Low power timer clock enable - bit_offset: 31 - bit_size: 1 - - name: TIM3EN - description: Timer 3 clock enbale - bit_offset: 1 - bit_size: 1 - name: USBEN description: USB clock enable bit_offset: 23 @@ -245,10 +233,22 @@ fieldset/APB1ENR: description: Clock recovery system clock enable bit_offset: 27 bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 - name: DACEN description: DAC interface clock enable bit_offset: 29 bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 30 + bit_size: 1 + - name: LPTIM1EN + description: Low power timer clock enable + bit_offset: 31 + bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: @@ -300,18 +300,6 @@ fieldset/APB1RSTR: description: I2C2 reset bit_offset: 22 bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: LPTIM1RST - description: Low power timer reset - bit_offset: 31 - bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 30 - bit_size: 1 - name: USBRST description: USB reset bit_offset: 23 @@ -320,10 +308,22 @@ fieldset/APB1RSTR: description: Clock recovery system reset bit_offset: 27 bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 - name: DACRST description: DAC interface reset bit_offset: 29 bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 30 + bit_size: 1 + - name: LPTIM1RST + description: Low power timer reset + bit_offset: 31 + bit_size: 1 fieldset/APB1SMENR: description: APB1 peripheral clock enable in sleep mode register fields: @@ -375,6 +375,10 @@ fieldset/APB1SMENR: description: I2C2 clock enable during sleep mode bit_offset: 22 bit_size: 1 + - name: USBSMEN + description: USB clock enable during sleep mode + bit_offset: 23 + bit_size: 1 - name: CRSSMEN description: Clock recovery system clock enable during sleep mode bit_offset: 27 @@ -383,6 +387,10 @@ fieldset/APB1SMENR: description: Power interface clock enable during sleep mode bit_offset: 28 bit_size: 1 + - name: DACSMEN + description: DAC interface clock enable during sleep mode + bit_offset: 29 + bit_size: 1 - name: I2C3SMEN description: I2C3 clock enable during sleep mode bit_offset: 30 @@ -391,14 +399,6 @@ fieldset/APB1SMENR: description: Low power timer clock enable during sleep mode bit_offset: 31 bit_size: 1 - - name: USBSMEN - description: USB clock enable during sleep mode - bit_offset: 23 - bit_size: 1 - - name: DACSMEN - description: DAC interface clock enable during sleep mode - bit_offset: 29 - bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: @@ -418,6 +418,10 @@ fieldset/APB2ENR: description: Firewall clock enable bit_offset: 7 bit_size: 1 + - name: MIFIEN + description: MiFaRe Firewall clock enable + bit_offset: 7 + bit_size: 1 - name: ADCEN description: ADC clock enable bit_offset: 9 @@ -434,10 +438,6 @@ fieldset/APB2ENR: description: DBG clock enable bit_offset: 22 bit_size: 1 - - name: MIFIEN - description: MiFaRe Firewall clock enable - bit_offset: 7 - bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: @@ -622,6 +622,10 @@ fieldset/CICR: description: MSI ready Interrupt clear bit_offset: 5 bit_size: 1 + - name: HSI48RDYC + description: HSI48 ready Interrupt clear + bit_offset: 6 + bit_size: 1 - name: CSSLSEC description: LSE Clock Security System Interrupt clear bit_offset: 7 @@ -630,10 +634,6 @@ fieldset/CICR: description: Clock Security System Interrupt clear bit_offset: 8 bit_size: 1 - - name: HSI48RDYC - description: HSI48 ready Interrupt clear - bit_offset: 6 - bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: @@ -661,14 +661,14 @@ fieldset/CIER: description: MSI ready interrupt flag bit_offset: 5 bit_size: 1 - - name: CSSLSE - description: LSE CSS interrupt flag - bit_offset: 7 - bit_size: 1 - name: HSI48RDYIE description: HSI48 ready interrupt flag bit_offset: 6 bit_size: 1 + - name: CSSLSE + description: LSE CSS interrupt flag + bit_offset: 7 + bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: @@ -696,6 +696,10 @@ fieldset/CIFR: description: MSI ready interrupt flag bit_offset: 5 bit_size: 1 + - name: HSI48RDYF + description: HSI48 ready interrupt flag + bit_offset: 6 + bit_size: 1 - name: CSSLSEF description: LSE Clock Security System Interrupt flag bit_offset: 7 @@ -704,10 +708,6 @@ fieldset/CIFR: description: Clock Security System Interrupt flag bit_offset: 8 bit_size: 1 - - name: HSI48RDYF - description: HSI48 ready interrupt flag - bit_offset: 6 - bit_size: 1 fieldset/CR: description: Clock control register fields: diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml index cc9568e..50af48b 100644 --- a/data/registers/rcc_l4.yaml +++ b/data/registers/rcc_l4.yaml @@ -446,11 +446,11 @@ fieldset/AHB2SMENR: description: AES accelerator clocks enable during Sleep and Stop modes bit_offset: 16 bit_size: 1 - - name: HASHSMEN + - name: HASH1SMEN description: HASH clock enable during Sleep and Stop modes bit_offset: 17 bit_size: 1 - - name: HASH1SMEN + - name: HASHSMEN description: HASH clock enable during Sleep and Stop modes bit_offset: 17 bit_size: 1 @@ -594,14 +594,14 @@ fieldset/APB1ENR1: description: CAN1 clock enable bit_offset: 25 bit_size: 1 - - name: USBFSEN - description: USB FS clock enable - bit_offset: 26 - bit_size: 1 - name: CAN2EN description: CAN2 clock enable bit_offset: 26 bit_size: 1 + - name: USBFSEN + description: USB FS clock enable + bit_offset: 26 + bit_size: 1 - name: PWREN description: Power interface clock enable bit_offset: 28 @@ -716,14 +716,14 @@ fieldset/APB1RSTR1: description: CAN1 reset bit_offset: 25 bit_size: 1 - - name: USBFSRST - description: USB FS reset - bit_offset: 26 - bit_size: 1 - name: CAN2RST description: CAN2 reset bit_offset: 26 bit_size: 1 + - name: USBFSRST + description: USB FS reset + bit_offset: 26 + bit_size: 1 - name: PWRRST description: Power interface reset bit_offset: 28 @@ -842,14 +842,14 @@ fieldset/APB1SMENR1: description: CAN1 clocks enable during Sleep and Stop modes bit_offset: 25 bit_size: 1 - - name: USBFSSMEN - description: USB FS clock enable during Sleep and Stop modes - bit_offset: 26 - bit_size: 1 - name: CAN2SMEN description: CAN2 clocks enable during Sleep and Stop modes bit_offset: 26 bit_size: 1 + - name: USBFSSMEN + description: USB FS clock enable during Sleep and Stop modes + bit_offset: 26 + bit_size: 1 - name: PWRSMEN description: Power interface clocks enable during Sleep and Stop modes bit_offset: 28 @@ -892,11 +892,11 @@ fieldset/APB2ENR: description: SYSCFG clock enable bit_offset: 0 bit_size: 1 - - name: FWEN + - name: FIREWALLEN description: Firewall clock enable bit_offset: 7 bit_size: 1 - - name: FIREWALLEN + - name: FWEN description: Firewall clock enable bit_offset: 7 bit_size: 1 @@ -1535,11 +1535,11 @@ fieldset/CSR: description: Remove reset flag bit_offset: 23 bit_size: 1 - - name: FWRSTF + - name: FIREWALLRSTF description: Firewall reset flag bit_offset: 24 bit_size: 1 - - name: FIREWALLRSTF + - name: FWRSTF description: Firewall reset flag bit_offset: 24 bit_size: 1 diff --git a/data/registers/rtc_v2.yaml b/data/registers/rtc_v2.yaml index 55834e7..20ada52 100644 --- a/data/registers/rtc_v2.yaml +++ b/data/registers/rtc_v2.yaml @@ -488,14 +488,14 @@ fieldset/ISR: fieldset/OR: description: option register fields: - - name: TSINSEL - description: TIMESTAMP mapping - bit_offset: 1 - bit_size: 1 - name: RTC_OUT_RMP description: RTC_OUT remap bit_offset: 1 bit_size: 1 + - name: TSINSEL + description: TIMESTAMP mapping + bit_offset: 1 + bit_size: 1 - name: RTC_ALARM_TYPE description: RTC_ALARM on PC13 output type bit_offset: 3 diff --git a/data/registers/rtc_wb.yaml b/data/registers/rtc_wb.yaml index c734e4e..2afb3ed 100644 --- a/data/registers/rtc_wb.yaml +++ b/data/registers/rtc_wb.yaml @@ -2,890 +2,890 @@ block/RTC: description: Real-time clock items: - - name: TR - description: time register - byte_offset: 0 - fieldset: TR - - name: DR - description: date register - byte_offset: 4 - fieldset: DR - - name: CR - description: control register - byte_offset: 8 - fieldset: CR - - byte_offset: 12 - description: initialization and status register - fieldset: ISR - name: ISR - - byte_offset: 16 - description: prescaler register - fieldset: PRER - name: PRER - - byte_offset: 20 - description: wakeup timer register - fieldset: WUTR - name: WUTR - - byte_offset: 28 - description: alarm A register - fieldset: ALRMAR - name: ALRMAR - - byte_offset: 32 - description: alarm B register - fieldset: ALRMBR - name: ALRMBR - - access: Write - byte_offset: 36 - description: write protection register - fieldset: WPR - name: WPR - - access: Read - byte_offset: 40 - description: sub second register - fieldset: SSR - name: SSR - - access: Write - byte_offset: 44 - description: shift control register - fieldset: SHIFTR - name: SHIFTR - - access: Read - byte_offset: 48 - description: time stamp time register - fieldset: TSTR - name: TSTR - - access: Read - byte_offset: 52 - description: time stamp date register - fieldset: TSDR - name: TSDR - - access: Read - byte_offset: 56 - description: timestamp sub second register - fieldset: TSSSR - name: TSSSR - - byte_offset: 60 - description: calibration register - fieldset: CALR - name: CALR - - byte_offset: 64 - description: tamper configuration register - fieldset: TAMPCR - name: TAMPCR - - byte_offset: 68 - description: alarm A sub second register - fieldset: ALRMASSR - name: ALRMASSR - - byte_offset: 72 - description: alarm B sub second register - fieldset: ALRMBSSR - name: ALRMBSSR - - byte_offset: 76 - description: option register - fieldset: OR - name: OR - - byte_offset: 80 - description: backup register - fieldset: BKP0R - name: BKP0R - - byte_offset: 84 - description: backup register - fieldset: BKP1R - name: BKP1R - - byte_offset: 88 - description: backup register - fieldset: BKP2R - name: BKP2R - - byte_offset: 92 - description: backup register - fieldset: BKP3R - name: BKP3R - - byte_offset: 96 - description: backup register - fieldset: BKP4R - name: BKP4R - - byte_offset: 100 - description: backup register - fieldset: BKP5R - name: BKP5R - - byte_offset: 104 - description: backup register - fieldset: BKP6R - name: BKP6R - - byte_offset: 108 - description: backup register - fieldset: BKP7R - name: BKP7R - - byte_offset: 112 - description: backup register - fieldset: BKP8R - name: BKP8R - - byte_offset: 116 - description: backup register - fieldset: BKP9R - name: BKP9R - - byte_offset: 120 - description: backup register - fieldset: BKP10R - name: BKP10R - - byte_offset: 124 - description: backup register - fieldset: BKP11R - name: BKP11R - - byte_offset: 128 - description: backup register - fieldset: BKP12R - name: BKP12R - - byte_offset: 132 - description: backup register - fieldset: BKP13R - name: BKP13R - - byte_offset: 136 - description: backup register - fieldset: BKP14R - name: BKP14R - - byte_offset: 140 - description: backup register - fieldset: BKP15R - name: BKP15R - - byte_offset: 144 - description: backup register - fieldset: BKP16R - name: BKP16R - - byte_offset: 148 - description: backup register - fieldset: BKP17R - name: BKP17R - - byte_offset: 152 - description: backup register - fieldset: BKP18R - name: BKP18R - - byte_offset: 156 - description: backup register - fieldset: BKP19R - name: BKP19R + - name: TR + description: time register + byte_offset: 0 + fieldset: TR + - name: DR + description: date register + byte_offset: 4 + fieldset: DR + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMAR + description: alarm A register + byte_offset: 28 + fieldset: ALRMAR + - name: ALRMBR + description: alarm B register + byte_offset: 32 + fieldset: ALRMBR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: time stamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: time stamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMASSR + description: alarm A sub second register + byte_offset: 68 + fieldset: ALRMASSR + - name: ALRMBSSR + description: alarm B sub second register + byte_offset: 72 + fieldset: ALRMBSSR + - name: OR + description: option register + byte_offset: 76 + fieldset: OR + - name: BKP0R + description: backup register + byte_offset: 80 + fieldset: BKP0R + - name: BKP1R + description: backup register + byte_offset: 84 + fieldset: BKP1R + - name: BKP2R + description: backup register + byte_offset: 88 + fieldset: BKP2R + - name: BKP3R + description: backup register + byte_offset: 92 + fieldset: BKP3R + - name: BKP4R + description: backup register + byte_offset: 96 + fieldset: BKP4R + - name: BKP5R + description: backup register + byte_offset: 100 + fieldset: BKP5R + - name: BKP6R + description: backup register + byte_offset: 104 + fieldset: BKP6R + - name: BKP7R + description: backup register + byte_offset: 108 + fieldset: BKP7R + - name: BKP8R + description: backup register + byte_offset: 112 + fieldset: BKP8R + - name: BKP9R + description: backup register + byte_offset: 116 + fieldset: BKP9R + - name: BKP10R + description: backup register + byte_offset: 120 + fieldset: BKP10R + - name: BKP11R + description: backup register + byte_offset: 124 + fieldset: BKP11R + - name: BKP12R + description: backup register + byte_offset: 128 + fieldset: BKP12R + - name: BKP13R + description: backup register + byte_offset: 132 + fieldset: BKP13R + - name: BKP14R + description: backup register + byte_offset: 136 + fieldset: BKP14R + - name: BKP15R + description: backup register + byte_offset: 140 + fieldset: BKP15R + - name: BKP16R + description: backup register + byte_offset: 144 + fieldset: BKP16R + - name: BKP17R + description: backup register + byte_offset: 148 + fieldset: BKP17R + - name: BKP18R + description: backup register + byte_offset: 152 + fieldset: BKP18R + - name: BKP19R + description: backup register + byte_offset: 156 + fieldset: BKP19R fieldset/ALRMAR: description: alarm A register fields: - - bit_offset: 0 - bit_size: 4 - description: Second units in BCD format - name: SU - - bit_offset: 4 - bit_size: 3 - description: Second tens in BCD format - name: ST - - bit_offset: 7 - bit_size: 1 - description: Alarm A seconds mask - name: MSK1 - - bit_offset: 8 - bit_size: 4 - description: Minute units in BCD format - name: MNU - - bit_offset: 12 - bit_size: 3 - description: Minute tens in BCD format - name: MNT - - bit_offset: 15 - bit_size: 1 - description: Alarm A minutes mask - name: MSK2 - - bit_offset: 16 - bit_size: 4 - description: Hour units in BCD format - name: HU - - bit_offset: 20 - bit_size: 2 - description: Hour tens in BCD format - name: HT - - bit_offset: 22 - bit_size: 1 - description: AM/PM notation - name: PM - - bit_offset: 23 - bit_size: 1 - description: Alarm A hours mask - name: MSK3 - - bit_offset: 24 - bit_size: 4 - description: Date units or day in BCD format - name: DU - - bit_offset: 28 - bit_size: 2 - description: Date tens in BCD format - name: DT - - bit_offset: 30 - bit_size: 1 - description: Week day selection - name: WDSEL - - bit_offset: 31 - bit_size: 1 - description: Alarm A date mask - name: MSK4 + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 fieldset/ALRMASSR: description: alarm A sub second register fields: - - bit_offset: 0 - bit_size: 15 - description: Sub seconds value - name: SS - - bit_offset: 24 - bit_size: 4 - description: Mask the most-significant bits starting at this bit - name: MASKSS + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 fieldset/ALRMBR: description: alarm B register fields: - - bit_offset: 0 - bit_size: 4 - description: Second units in BCD format - name: SU - - bit_offset: 4 - bit_size: 3 - description: Second tens in BCD format - name: ST - - bit_offset: 7 - bit_size: 1 - description: Alarm B seconds mask - name: MSK1 - - bit_offset: 8 - bit_size: 4 - description: Minute units in BCD format - name: MNU - - bit_offset: 12 - bit_size: 3 - description: Minute tens in BCD format - name: MNT - - bit_offset: 15 - bit_size: 1 - description: Alarm B minutes mask - name: MSK2 - - bit_offset: 16 - bit_size: 4 - description: Hour units in BCD format - name: HU - - bit_offset: 20 - bit_size: 2 - description: Hour tens in BCD format - name: HT - - bit_offset: 22 - bit_size: 1 - description: AM/PM notation - name: PM - - bit_offset: 23 - bit_size: 1 - description: Alarm B hours mask - name: MSK3 - - bit_offset: 24 - bit_size: 4 - description: Date units or day in BCD format - name: DU - - bit_offset: 28 - bit_size: 2 - description: Date tens in BCD format - name: DT - - bit_offset: 30 - bit_size: 1 - description: Week day selection - name: WDSEL - - bit_offset: 31 - bit_size: 1 - description: Alarm B date mask - name: MSK4 + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 fieldset/ALRMBSSR: description: alarm B sub second register fields: - - bit_offset: 0 - bit_size: 15 - description: Sub seconds value - name: SS - - bit_offset: 24 - bit_size: 4 - description: Mask the most-significant bits starting at this bit - name: MASKSS + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 fieldset/BKP0R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP10R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP11R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP12R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP13R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP14R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP15R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP16R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP17R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP18R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP19R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP1R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP2R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP3R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP4R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP5R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP6R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP7R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP8R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/BKP9R: description: backup register fields: - - bit_offset: 0 - bit_size: 32 - description: BKP - name: BKP + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 fieldset/CALR: description: calibration register fields: - - bit_offset: 0 - bit_size: 9 - description: Calibration minus - name: CALM - - bit_offset: 13 - bit_size: 1 - description: Use a 16-second calibration cycle period - name: CALW16 - - bit_offset: 14 - bit_size: 1 - description: Use an 8-second calibration cycle period - name: CALW8 - - bit_offset: 15 - bit_size: 1 - description: Increase frequency of RTC by 488.5 ppm - name: CALP + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 fieldset/CR: description: control register fields: - - bit_offset: 0 - bit_size: 3 - description: Wakeup clock selection - name: WUCKSEL - - bit_offset: 3 - bit_size: 1 - description: Time-stamp event active edge - name: TSEDGE - - bit_offset: 4 - bit_size: 1 - description: Reference clock detection enable (50 or 60 Hz) - name: REFCKON - - bit_offset: 5 - bit_size: 1 - description: Bypass the shadow registers - name: BYPSHAD - - bit_offset: 6 - bit_size: 1 - description: Hour format - name: FMT - - bit_offset: 8 - bit_size: 1 - description: Alarm A enable - name: ALRAE - - bit_offset: 9 - bit_size: 1 - description: Alarm B enable - name: ALRBE - - bit_offset: 10 - bit_size: 1 - description: Wakeup timer enable - name: WUTE - - bit_offset: 11 - bit_size: 1 - description: Time stamp enable - name: TSE - - bit_offset: 12 - bit_size: 1 - description: Alarm A interrupt enable - name: ALRAIE - - bit_offset: 13 - bit_size: 1 - description: Alarm B interrupt enable - name: ALRBIE - - bit_offset: 14 - bit_size: 1 - description: Wakeup timer interrupt enable - name: WUTIE - - bit_offset: 15 - bit_size: 1 - description: Time-stamp interrupt enable - name: TSIE - - bit_offset: 16 - bit_size: 1 - description: Add 1 hour (summer time change) - name: ADD1H - - bit_offset: 17 - bit_size: 1 - description: Subtract 1 hour (winter time change) - name: SUB1H - - bit_offset: 18 - bit_size: 1 - description: Backup - name: BKP - - bit_offset: 19 - bit_size: 1 - description: Calibration output selection - name: COSEL - - bit_offset: 20 - bit_size: 1 - description: Output polarity - name: POL - - bit_offset: 21 - bit_size: 2 - description: Output selection - name: OSEL - - bit_offset: 23 - bit_size: 1 - description: Calibration output enable - name: COE - - bit_offset: 24 - bit_size: 1 - description: timestamp on internal event enable - name: ITSE + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + - name: TSEDGE + description: Time-stamp event active edge + bit_offset: 3 + bit_size: 1 + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + - name: ALRAE + description: Alarm A enable + bit_offset: 8 + bit_size: 1 + - name: ALRBE + description: Alarm B enable + bit_offset: 9 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Time stamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRAIE + description: Alarm A interrupt enable + bit_offset: 12 + bit_size: 1 + - name: ALRBIE + description: Alarm B interrupt enable + bit_offset: 13 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Time-stamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: timestamp on internal event enable + bit_offset: 24 + bit_size: 1 fieldset/DR: description: date register fields: - - bit_offset: 0 - bit_size: 4 - description: Date units in BCD format - name: DU - - bit_offset: 4 - bit_size: 2 - description: Date tens in BCD format - name: DT - - bit_offset: 8 - bit_size: 4 - description: Month units in BCD format - name: MU - - bit_offset: 12 - bit_size: 1 - description: Month tens in BCD format - name: MT - - bit_offset: 13 - bit_size: 3 - description: Week day units - name: WDU - - bit_offset: 16 - bit_size: 4 - description: Year units in BCD format - name: YU - - bit_offset: 20 - bit_size: 4 - description: Year tens in BCD format - name: YT + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 fieldset/ISR: description: initialization and status register fields: - - bit_offset: 0 - bit_size: 1 - description: Alarm A write flag - name: ALRAWF - - bit_offset: 1 - bit_size: 1 - description: Alarm B write flag - name: ALRBWF - - bit_offset: 2 - bit_size: 1 - description: Wakeup timer write flag - name: WUTWF - - bit_offset: 3 - bit_size: 1 - description: Shift operation pending - name: SHPF - - bit_offset: 4 - bit_size: 1 - description: Initialization status flag - name: INITS - - bit_offset: 5 - bit_size: 1 - description: Registers synchronization flag - name: RSF - - bit_offset: 6 - bit_size: 1 - description: Initialization flag - name: INITF - - bit_offset: 7 - bit_size: 1 - description: Initialization mode - name: INIT - - bit_offset: 8 - bit_size: 1 - description: Alarm A flag - name: ALRAF - - bit_offset: 9 - bit_size: 1 - description: Alarm B flag - name: ALRBF - - bit_offset: 10 - bit_size: 1 - description: Wakeup timer flag - name: WUTF - - bit_offset: 11 - bit_size: 1 - description: Time-stamp flag - name: TSF - - bit_offset: 12 - bit_size: 1 - description: Time-stamp overflow flag - name: TSOVF - - bit_offset: 13 - bit_size: 1 - description: Tamper detection flag - name: TAMP1F - - bit_offset: 14 - bit_size: 1 - description: RTC_TAMP2 detection flag - name: TAMP2F - - bit_offset: 15 - bit_size: 1 - description: RTC_TAMP3 detection flag - name: TAMP3F - - bit_offset: 16 - bit_size: 1 - description: Recalibration pending Flag - name: RECALPF - - bit_offset: 17 - bit_size: 1 - description: INTERNAL TIME-STAMP FLAG - name: ITSF + - name: ALRAWF + description: Alarm A write flag + bit_offset: 0 + bit_size: 1 + - name: ALRBWF + description: Alarm B write flag + bit_offset: 1 + bit_size: 1 + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + - name: ALRAF + description: Alarm A flag + bit_offset: 8 + bit_size: 1 + - name: ALRBF + description: Alarm B flag + bit_offset: 9 + bit_size: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Time-stamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Time-stamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMP1F + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + - name: TAMP2F + description: RTC_TAMP2 detection flag + bit_offset: 14 + bit_size: 1 + - name: TAMP3F + description: RTC_TAMP3 detection flag + bit_offset: 15 + bit_size: 1 + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + - name: ITSF + description: INTERNAL TIME-STAMP FLAG + bit_offset: 17 + bit_size: 1 fieldset/OR: description: option register fields: - - bit_offset: 0 - bit_size: 1 - description: RTC_ALARM on PC13 output type - name: RTC_ALARM_TYPE - - bit_offset: 1 - bit_size: 1 - description: RTC_OUT remap - name: RTC_OUT_RMP + - name: RTC_ALARM_TYPE + description: RTC_ALARM on PC13 output type + bit_offset: 0 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_OUT remap + bit_offset: 1 + bit_size: 1 fieldset/PRER: description: prescaler register fields: - - bit_offset: 0 - bit_size: 15 - description: Synchronous prescaler factor - name: PREDIV_S - - bit_offset: 16 - bit_size: 7 - description: Asynchronous prescaler factor - name: PREDIV_A + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 fieldset/SHIFTR: description: shift control register fields: - - bit_offset: 0 - bit_size: 15 - description: Subtract a fraction of a second - name: SUBFS - - bit_offset: 31 - bit_size: 1 - description: Add one second - name: ADD1S + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 fieldset/SSR: description: sub second register fields: - - bit_offset: 0 - bit_size: 16 - description: Sub second value - name: SS + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TAMPCR: description: tamper configuration register fields: - - bit_offset: 0 - bit_size: 1 - description: Tamper 1 detection enable - name: TAMP1E - - bit_offset: 1 - bit_size: 1 - description: Active level for tamper 1 - name: TAMP1TRG - - bit_offset: 2 - bit_size: 1 - description: Tamper interrupt enable - name: TAMPIE - - bit_offset: 3 - bit_size: 1 - description: Tamper 2 detection enable - name: TAMP2E - - bit_offset: 4 - bit_size: 1 - description: Active level for tamper 2 - name: TAMP2TRG - - bit_offset: 5 - bit_size: 1 - description: Tamper 3 detection enable - name: TAMP3E - - bit_offset: 6 - bit_size: 1 - description: Active level for tamper 3 - name: TAMP3TRG - - bit_offset: 7 - bit_size: 1 - description: Activate timestamp on tamper detection event - name: TAMPTS - - bit_offset: 8 - bit_size: 3 - description: Tamper sampling frequency - name: TAMPFREQ - - bit_offset: 11 - bit_size: 2 - description: Tamper filter count - name: TAMPFLT - - bit_offset: 13 - bit_size: 2 - description: Tamper precharge duration - name: TAMPPRCH - - bit_offset: 15 - bit_size: 1 - description: TAMPER pull-up disable - name: TAMPPUDIS - - bit_offset: 16 - bit_size: 1 - description: Tamper 1 interrupt enable - name: TAMP1IE - - bit_offset: 17 - bit_size: 1 - description: Tamper 1 no erase - name: TAMP1NOERASE - - bit_offset: 18 - bit_size: 1 - description: Tamper 1 mask flag - name: TAMP1MF - - bit_offset: 19 - bit_size: 1 - description: Tamper 2 interrupt enable - name: TAMP2IE - - bit_offset: 20 - bit_size: 1 - description: Tamper 2 no erase - name: TAMP2NOERASE - - bit_offset: 21 - bit_size: 1 - description: Tamper 2 mask flag - name: TAMP2MF - - bit_offset: 22 - bit_size: 1 - description: Tamper 3 interrupt enable - name: TAMP3IE - - bit_offset: 23 - bit_size: 1 - description: Tamper 3 no erase - name: TAMP3NOERASE - - bit_offset: 24 - bit_size: 1 - description: Tamper 3 mask flag - name: TAMP3MF + - name: TAMP1E + description: Tamper 1 detection enable + bit_offset: 0 + bit_size: 1 + - name: TAMP1TRG + description: Active level for tamper 1 + bit_offset: 1 + bit_size: 1 + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMP2E + description: Tamper 2 detection enable + bit_offset: 3 + bit_size: 1 + - name: TAMP2TRG + description: Active level for tamper 2 + bit_offset: 4 + bit_size: 1 + - name: TAMP3E + description: Tamper 3 detection enable + bit_offset: 5 + bit_size: 1 + - name: TAMP3TRG + description: Active level for tamper 3 + bit_offset: 6 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + - name: TAMPPUDIS + description: TAMPER pull-up disable + bit_offset: 15 + bit_size: 1 + - name: TAMP1IE + description: Tamper 1 interrupt enable + bit_offset: 16 + bit_size: 1 + - name: TAMP1NOERASE + description: Tamper 1 no erase + bit_offset: 17 + bit_size: 1 + - name: TAMP1MF + description: Tamper 1 mask flag + bit_offset: 18 + bit_size: 1 + - name: TAMP2IE + description: Tamper 2 interrupt enable + bit_offset: 19 + bit_size: 1 + - name: TAMP2NOERASE + description: Tamper 2 no erase + bit_offset: 20 + bit_size: 1 + - name: TAMP2MF + description: Tamper 2 mask flag + bit_offset: 21 + bit_size: 1 + - name: TAMP3IE + description: Tamper 3 interrupt enable + bit_offset: 22 + bit_size: 1 + - name: TAMP3NOERASE + description: Tamper 3 no erase + bit_offset: 23 + bit_size: 1 + - name: TAMP3MF + description: Tamper 3 mask flag + bit_offset: 24 + bit_size: 1 fieldset/TR: description: time register fields: - - bit_offset: 0 - bit_size: 4 - description: Second units in BCD format - name: SU - - bit_offset: 4 - bit_size: 3 - description: Second tens in BCD format - name: ST - - bit_offset: 8 - bit_size: 4 - description: Minute units in BCD format - name: MNU - - bit_offset: 12 - bit_size: 3 - description: Minute tens in BCD format - name: MNT - - bit_offset: 16 - bit_size: 4 - description: Hour units in BCD format - name: HU - - bit_offset: 20 - bit_size: 2 - description: Hour tens in BCD format - name: HT - - bit_offset: 22 - bit_size: 1 - description: AM/PM notation - name: PM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 fieldset/TSDR: description: time stamp date register fields: - - bit_offset: 0 - bit_size: 4 - description: Date units in BCD format - name: DU - - bit_offset: 4 - bit_size: 2 - description: Date tens in BCD format - name: DT - - bit_offset: 8 - bit_size: 4 - description: Month units in BCD format - name: MU - - bit_offset: 12 - bit_size: 1 - description: Month tens in BCD format - name: MT - - bit_offset: 13 - bit_size: 3 - description: Week day units - name: WDU + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 fieldset/TSSSR: description: timestamp sub second register fields: - - bit_offset: 0 - bit_size: 16 - description: Sub second value - name: SS + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 fieldset/TSTR: description: time stamp time register fields: - - bit_offset: 0 - bit_size: 4 - description: Second units in BCD format - name: SU - - bit_offset: 4 - bit_size: 3 - description: Second tens in BCD format - name: ST - - bit_offset: 8 - bit_size: 4 - description: Minute units in BCD format - name: MNU - - bit_offset: 12 - bit_size: 3 - description: Minute tens in BCD format - name: MNT - - bit_offset: 16 - bit_size: 4 - description: Hour units in BCD format - name: HU - - bit_offset: 20 - bit_size: 2 - description: Hour tens in BCD format - name: HT - - bit_offset: 22 - bit_size: 1 - description: AM/PM notation - name: PM + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 fieldset/WPR: description: write protection register fields: - - bit_offset: 0 - bit_size: 8 - description: Write protection key - name: KEY + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 fieldset/WUTR: description: wakeup timer register fields: - - bit_offset: 0 - bit_size: 16 - description: Wakeup auto-reload value bits - name: WUT + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 diff --git a/data/registers/syscfg_f3.yaml b/data/registers/syscfg_f3.yaml index 5b31ae6..94dc85f 100644 --- a/data/registers/syscfg_f3.yaml +++ b/data/registers/syscfg_f3.yaml @@ -1,1296 +1,1284 @@ +--- block/SYSCFG: description: System configuration controller items: - - byte_offset: 0 - description: configuration register 1 - fieldset: CFGR1 - name: CFGR1 - - byte_offset: 4 - description: CCM SRAM protection register - fieldset: RCR - name: RCR - - byte_offset: 8 - description: external interrupt configuration register - fieldset: EXTICR - name: EXTICR - array: - len: 4 - stride: 4 - - byte_offset: 24 - description: configuration register 2 - fieldset: CFGR2 - name: CFGR2 - - byte_offset: 72 - description: configuration register 4 - fieldset: CFGR4 - name: CFGR4 - - byte_offset: 80 - description: configuration register 3 - fieldset: CFGR3 - name: CFGR3 -enum/ADC12_EXT13_RMP: - bit_size: 1 - variants: - - description: Trigger source is TIM6_TRGO - name: Tim6 - value: 0 - - description: Trigger source is TIM20_CC2 - name: Tim20 - value: 1 -enum/ADC12_EXT15_RMP: - bit_size: 1 - variants: - - description: Trigger source is TIM3_CC4 - name: Tim3 - value: 0 - - description: Trigger source is TIM20_CC3 - name: Tim20 - value: 1 -enum/ADC12_EXT2_RMP: - bit_size: 1 - variants: - - description: Trigger source is TIM3_CC3 - name: Tim1 - value: 0 - - description: rigger source is TIM20_TRGO - name: Tim20 - value: 1 -enum/ADC12_EXT3_RMP: - bit_size: 1 - variants: - - description: Trigger source is TIM2_CC2 - name: Tim2 - value: 0 - - description: rigger source is TIM20_TRGO2 - name: Tim20 - value: 1 -enum/ADC12_EXT5_RMP: - bit_size: 1 - variants: - - description: Trigger source is TIM4_CC4 - name: Tim4 - value: 0 - - description: Trigger source is TIM20_CC1 - name: Tim20 - value: 1 -enum/ADC12_JEXT13_RMP: - bit_size: 1 - variants: - - description: Trigger source is TIM3_CC1 - name: Tim3 - value: 0 - - description: Trigger source is TIM20_CC4 - name: Tim20 - value: 1 -enum/ADC12_JEXT3_RMP: - bit_size: 1 - variants: - - description: Trigger source is TIM2_CC1 - name: Tim2 - value: 0 - - description: Trigger source is TIM20_TRGO - name: Tim20 - value: 1 -enum/ADC12_JEXT6_RMP: - bit_size: 1 - variants: - - description: Trigger source is EXTI line 15 - name: Exti15 - value: 0 - - description: Trigger source is TIM20_TRGO2 - name: Tim20 - value: 1 -enum/ADC2_DMA_RMP: - bit_size: 1 - variants: - - description: ADC2 mapped on DMA2 - name: MapDma2 - value: 0 - - description: ADC2 mapped on DMA1 channel 2 - name: MapDma1Ch2 - value: 2 - - description: ADC2 mapped on DMA1 channel 4 - name: MapDma1Ch4 - value: 3 -enum/ADC34_EXT15_RMP: - bit_size: 1 - variants: - - description: Trigger source is TIM2_CC1 - name: Tim2 - value: 0 - - description: Trigger source is TIM20_CC1 - name: Tim20 - value: 1 -enum/ADC34_EXT5_RMP: - bit_size: 1 - variants: - - description: Trigger source is EXTI line 2 when reset at 0 - name: Exti2 - value: 0 - - description: Trigger source is TIM20_TRGO - name: Tim20 - value: 1 -enum/ADC34_EXT6_RMP: - bit_size: 1 - variants: - - description: Trigger source is TIM4_CC1 - name: Tim4 - value: 0 - - description: Trigger source is TIM20_TRGO2 - name: Tim20 - value: 1 -enum/ADC34_JEXT11_RMP: - bit_size: 1 - variants: - - description: Trigger source is TIM1_CC3 - name: Tim1 - value: 0 - - description: Trigger source is TIM20_TRGO2 - name: Tim20 - value: 1 -enum/ADC34_JEXT14_RMP: - bit_size: 1 - variants: - - description: Trigger source is TIM7_TRGO - name: Tim7 - value: 0 - - description: Trigger source is TIM20_CC2 - name: Tim20 - value: 1 -enum/ADC34_JEXT5_RMP: - bit_size: 1 - variants: - - description: Trigger source is TIM4_CC3 - name: Tim4 - value: 0 - - description: Trigger source is TIM20_TRGO - name: Tim20 - value: 1 -enum/BYP_ADDR_PAR: - bit_size: 1 - variants: - - description: The ramload operation is performed taking into consideration bit - 29 of the address when the parity is calculated - name: NoBypass - value: 0 - - description: The ramload operation is performed without taking into consideration - bit 29 of the address when the parity is calculated - name: Bypass - value: 1 -enum/CFGR1_ADC2_DMA_RMP: - bit_size: 1 - variants: - - description: ADC24 DMA requests mapped on DMA2 channels 1 and 2 - name: NotRemapped - value: 0 - - description: ADC24 DMA requests mapped on DMA2 channels 3 and 4 - name: Remapped - value: 1 -enum/CFGR3_ADC2_DMA_RMP: - bit_size: 2 - variants: - - description: ADC2 mapped on DMA2 - name: MapDma2 - value: 0 - - description: ADC2 mapped on DMA1 channel 2 - name: MapDma1Ch2 - value: 2 - - description: ADC2 mapped on DMA1 channel 4 - name: MapDma1Ch4 - value: 3 -enum/DAC1_TRIG3_RMP: - bit_size: 1 - variants: - - description: DAC trigger is TIM15_TRGO - name: Tim15 - value: 0 - - description: DAC trigger is HRTIM1_DAC1_TRIG1 - name: HrTim1 - value: 1 -enum/DAC1_TRIG5_RMP: - bit_size: 1 - variants: - - description: Not remapped - name: NotRemapped - value: 0 - - description: DAC trigger is HRTIM1_DAC1_TRIG2 - name: Remapped - value: 1 -enum/DAC1_TRIG_RMP: - bit_size: 1 - variants: - - description: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices - name: NotRemapped - value: 0 - - description: DAC trigger is TIM3_TRGO - name: Remapped - value: 1 -enum/DAC2_CH1_DMA_RMP: - bit_size: 1 - variants: - - description: Not remapped - name: NotRemapped - value: 0 - - description: DAC2_CH1 DMA requests mapped on DMA1 channel 5 - name: Remapped - value: 1 -enum/DAC_TRIG_RMP: - bit_size: 1 - variants: - - description: Not remapped - name: NotRemapped - value: 0 - - description: DAC trigger is TIM3_TRGO - name: Remapped - value: 1 -enum/ENCODER_MODE: - bit_size: 2 - variants: - - description: No redirection - name: NoRedirection - value: 0 - - description: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively - name: MapTim2Tim15 - value: 1 - - description: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively - name: MapTim3Tim15 - value: 2 -enum/EXTI0: - bit_size: 4 - variants: - - description: Select PA0 as the source input for the EXTI0 external interrupt - name: PA0 - value: 0 - - description: Select PB0 as the source input for the EXTI0 external interrupt - name: PB0 - value: 1 - - description: Select PC0 as the source input for the EXTI0 external interrupt - name: PC0 - value: 2 - - description: Select PD0 as the source input for the EXTI0 external interrupt - name: PD0 - value: 3 - - description: Select PE0 as the source input for the EXTI0 external interrupt - name: PE0 - value: 4 - - description: Select PF0 as the source input for the EXTI0 external interrupt - name: PF0 - value: 5 -enum/EXTI1: - bit_size: 4 - variants: - - description: Select PA1 as the source input for the EXTI1 external interrupt - name: PA1 - value: 0 - - description: Select PB1 as the source input for the EXTI1 external interrupt - name: PB1 - value: 1 - - description: Select PC1 as the source input for the EXTI1 external interrupt - name: PC1 - value: 2 - - description: Select PD1 as the source input for the EXTI1 external interrupt - name: PD1 - value: 3 - - description: Select PE1 as the source input for the EXTI1 external interrupt - name: PE1 - value: 4 - - description: Select PF1 as the source input for the EXTI1 external interrupt - name: PF1 - value: 5 -enum/EXTI10: - bit_size: 4 - variants: - - description: Select PA10 as the source input for the EXTI10 external interrupt - name: PA10 - value: 0 - - description: Select PB10 as the source input for the EXTI10 external interrupt - name: PB10 - value: 1 - - description: Select PC10 as the source input for the EXTI10 external interrupt - name: PC10 - value: 2 - - description: Select PD10 as the source input for the EXTI10 external interrupt - name: PD10 - value: 3 - - description: Select PE10 as the source input for the EXTI10 external interrupt - name: PE10 - value: 4 - - description: Select PF10 as the source input for the EXTI10 external interrupt - name: PF10 - value: 5 -enum/EXTI11: - bit_size: 4 - variants: - - description: Select PA11 as the source input for the EXTI11 external interrupt - name: PA11 - value: 0 - - description: Select PB11 as the source input for the EXTI11 external interrupt - name: PB11 - value: 1 - - description: Select PC11 as the source input for the EXTI11 external interrupt - name: PC11 - value: 2 - - description: Select PD11 as the source input for the EXTI11 external interrupt - name: PD11 - value: 3 - - description: Select PE11 as the source input for the EXTI11 external interrupt - name: PE11 - value: 4 -enum/EXTI12: - bit_size: 4 - variants: - - description: Select PA12 as the source input for the EXTI12 external interrupt - name: PA12 - value: 0 - - description: Select PB12 as the source input for the EXTI12 external interrupt - name: PB12 - value: 1 - - description: Select PC12 as the source input for the EXTI12 external interrupt - name: PC12 - value: 2 - - description: Select PD12 as the source input for the EXTI12 external interrupt - name: PD12 - value: 3 - - description: Select PE12 as the source input for the EXTI12 external interrupt - name: PE12 - value: 4 -enum/EXTI13: - bit_size: 4 - variants: - - description: Select PA13 as the source input for the EXTI13 external interrupt - name: PA13 - value: 0 - - description: Select PB13 as the source input for the EXTI13 external interrupt - name: PB13 - value: 1 - - description: Select PC13 as the source input for the EXTI13 external interrupt - name: PC13 - value: 2 - - description: Select PD13 as the source input for the EXTI13 external interrupt - name: PD13 - value: 3 - - description: Select PE13 as the source input for the EXTI13 external interrupt - name: PE13 - value: 4 -enum/EXTI14: - bit_size: 4 - variants: - - description: Select PA14 as the source input for the EXTI14 external interrupt - name: PA14 - value: 0 - - description: Select PB14 as the source input for the EXTI14 external interrupt - name: PB14 - value: 1 - - description: Select PC14 as the source input for the EXTI14 external interrupt - name: PC14 - value: 2 - - description: Select PD14 as the source input for the EXTI14 external interrupt - name: PD14 - value: 3 - - description: Select PE14 as the source input for the EXTI14 external interrupt - name: PE14 - value: 4 -enum/EXTI15: - bit_size: 4 - variants: - - description: Select PA15 as the source input for the EXTI15 external interrupt - name: PA15 - value: 0 - - description: Select PB15 as the source input for the EXTI15 external interrupt - name: PB15 - value: 1 - - description: Select PC15 as the source input for the EXTI15 external interrupt - name: PC15 - value: 2 - - description: Select PD15 as the source input for the EXTI15 external interrupt - name: PD15 - value: 3 - - description: Select PE15 as the source input for the EXTI15 external interrupt - name: PE15 - value: 4 -enum/EXTI2: - bit_size: 4 - variants: - - description: Select PA2 as the source input for the EXTI2 external interrupt - name: PA2 - value: 0 - - description: Select PB2 as the source input for the EXTI2 external interrupt - name: PB2 - value: 1 - - description: Select PC2 as the source input for the EXTI2 external interrupt - name: PC2 - value: 2 - - description: Select PD2 as the source input for the EXTI2 external interrupt - name: PD2 - value: 3 - - description: Select PE2 as the source input for the EXTI2 external interrupt - name: PE2 - value: 4 - - description: Select PF2 as the source input for the EXTI2 external interrupt - name: PF2 - value: 5 -enum/EXTI3: - bit_size: 4 - variants: - - description: Select PA3 as the source input for the EXTI3 external interrupt - name: PA3 - value: 0 - - description: Select PB3 as the source input for the EXTI3 external interrupt - name: PB3 - value: 1 - - description: Select PC3 as the source input for the EXTI3 external interrupt - name: PC3 - value: 2 - - description: Select PD3 as the source input for the EXTI3 external interrupt - name: PD3 - value: 3 - - description: Select PE3 as the source input for the EXTI3 external interrupt - name: PE3 - value: 4 -enum/EXTI4: - bit_size: 4 - variants: - - description: Select PA4 as the source input for the EXTI4 external interrupt - name: PA4 - value: 0 - - description: Select PB4 as the source input for the EXTI4 external interrupt - name: PB4 - value: 1 - - description: Select PC4 as the source input for the EXTI4 external interrupt - name: PC4 - value: 2 - - description: Select PD4 as the source input for the EXTI4 external interrupt - name: PD4 - value: 3 - - description: Select PE4 as the source input for the EXTI4 external interrupt - name: PE4 - value: 4 - - description: Select PF4 as the source input for the EXTI4 external interrupt - name: PF4 - value: 5 -enum/EXTI5: - bit_size: 4 - variants: - - description: Select PA5 as the source input for the EXTI5 external interrupt - name: PA5 - value: 0 - - description: Select PB5 as the source input for the EXTI5 external interrupt - name: PB5 - value: 1 - - description: Select PC5 as the source input for the EXTI5 external interrupt - name: PC5 - value: 2 - - description: Select PD5 as the source input for the EXTI5 external interrupt - name: PD5 - value: 3 - - description: Select PE5 as the source input for the EXTI5 external interrupt - name: PE5 - value: 4 - - description: Select PF5 as the source input for the EXTI5 external interrupt - name: PF5 - value: 5 -enum/EXTI6: - bit_size: 4 - variants: - - description: Select PA6 as the source input for the EXTI6 external interrupt - name: PA6 - value: 0 - - description: Select PB6 as the source input for the EXTI6 external interrupt - name: PB6 - value: 1 - - description: Select PC6 as the source input for the EXTI6 external interrupt - name: PC6 - value: 2 - - description: Select PD6 as the source input for the EXTI6 external interrupt - name: PD6 - value: 3 - - description: Select PE6 as the source input for the EXTI6 external interrupt - name: PE6 - value: 4 - - description: Select PF6 as the source input for the EXTI6 external interrupt - name: PF6 - value: 5 -enum/EXTI7: - bit_size: 4 - variants: - - description: Select PA7 as the source input for the EXTI7 external interrupt - name: PA7 - value: 0 - - description: Select PB7 as the source input for the EXTI7 external interrupt - name: PB7 - value: 1 - - description: Select PC7 as the source input for the EXTI7 external interrupt - name: PC7 - value: 2 - - description: Select PD7 as the source input for the EXTI7 external interrupt - name: PD7 - value: 3 - - description: Select PE7 as the source input for the EXTI7 external interrupt - name: PE7 - value: 4 -enum/EXTI8: - bit_size: 4 - variants: - - description: Select PA8 as the source input for the EXTI8 external interrupt - name: PA8 - value: 0 - - description: Select PB8 as the source input for the EXTI8 external interrupt - name: PB8 - value: 1 - - description: Select PC8 as the source input for the EXTI8 external interrupt - name: PC8 - value: 2 - - description: Select PD8 as the source input for the EXTI8 external interrupt - name: PD8 - value: 3 - - description: Select PE8 as the source input for the EXTI8 external interrupt - name: PE8 - value: 4 -enum/EXTI9: - bit_size: 4 - variants: - - description: Select PA9 as the source input for the EXTI9 external interrupt - name: PA9 - value: 0 - - description: Select PB9 as the source input for the EXTI9 external interrupt - name: PB9 - value: 1 - - description: Select PC9 as the source input for the EXTI9 external interrupt - name: PC9 - value: 2 - - description: Select PD9 as the source input for the EXTI9 external interrupt - name: PD9 - value: 3 - - description: Select PE9 as the source input for the EXTI9 external interrupt - name: PE9 - value: 4 - - description: Select PF9 as the source input for the EXTI9 external interrupt - name: PF9 - value: 5 -enum/FPU_IE0: - bit_size: 1 - variants: - - description: Invalid operation interrupt disable - name: Disabled - value: 0 - - description: Invalid operation interrupt enable - name: Enabled - value: 1 -enum/FPU_IE1: - bit_size: 1 - variants: - - description: Devide-by-zero interrupt disable - name: Disabled - value: 0 - - description: Devide-by-zero interrupt enable - name: Enabled - value: 1 -enum/FPU_IE2: - bit_size: 1 - variants: - - description: Underflow interrupt disable - name: Disabled - value: 0 - - description: Underflow interrupt enable - name: Enabled - value: 1 -enum/FPU_IE3: - bit_size: 1 - variants: - - description: Overflow interrupt disable - name: Disabled - value: 0 - - description: Overflow interrupt enable - name: Enabled - value: 1 -enum/FPU_IE4: - bit_size: 1 - variants: - - description: Input denormal interrupt disable - name: Disabled - value: 0 - - description: Input denormal interrupt enable - name: Enabled - value: 1 -enum/FPU_IE5: - bit_size: 1 - variants: - - description: Inexact interrupt disable - name: Disabled - value: 0 - - description: Inexact interrupt enable - name: Enabled - value: 1 -enum/I2C1_FMP: - bit_size: 1 - variants: - - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - name: Standard - value: 0 - - description: FM+ mode is enabled on all I2C1 pins selected through selection through - IOPORT control registers AF selection bits - name: FMP - value: 1 -enum/I2C1_RX_DMA_RMP: - bit_size: 2 - variants: - - description: I2C1_RX mapped on DMA1 CH7 - name: MapDma1Ch7 - value: 0 - - description: I2C1_RX mapped on DMA1 CH3 - name: MapDma1Ch3 - value: 1 - - description: I2C1_RX mapped on DMA1 CH5 - name: MapDma1Ch5 - value: 2 -enum/I2C1_TX_DMA_RMP: - bit_size: 2 - variants: - - description: I2C1_TX mapped on DMA1 CH6 - name: MapDma1Ch6 - value: 0 - - description: I2C1_TX mapped on DMA1 CH2 - name: MapDma1Ch2 - value: 1 - - description: I2C1_TX mapped on DMA1 CH4 - name: MapDma1Ch4 - value: 2 -enum/I2C2_FMP: - bit_size: 1 - variants: - - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - name: Standard - value: 0 - - description: FM+ mode is enabled on all I2C2 pins selected through selection through - IOPORT control registers AF selection bits - name: FMP - value: 1 -enum/I2C3_FMP: - bit_size: 1 - variants: - - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - name: Standard - value: 0 - - description: FM+ mode is enabled on all I2C3 pins selected through selection trhough - IOPORT control registers AF selection bits - name: FMP - value: 1 -enum/I2C_PB6_FMP: - bit_size: 1 - variants: - - description: PB6 pin operate in standard mode - name: Standard - value: 0 - - description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed - name: FMP - value: 1 -enum/I2C_PB7_FMP: - bit_size: 1 - variants: - - description: PB7 pin operate in standard mode - name: Standard - value: 0 - - description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed - name: FMP - value: 1 -enum/I2C_PB8_FMP: - bit_size: 1 - variants: - - description: PB8 pin operate in standard mode - name: Standard - value: 0 - - description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed - name: FMP - value: 1 -enum/I2C_PB9_FMP: - bit_size: 1 - variants: - - description: PB9 pin operate in standard mode - name: Standard - value: 0 - - description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed - name: FMP - value: 1 -enum/LOCKUP_LOCK: - bit_size: 1 - variants: - - description: Cortex-M4 LOCKUP output disconnected from TIM1/15/16/17 Break inputs - and HRTIM1 SYSFLT. - name: Disconnected - value: 0 - - description: Cortex-M4 LOCKUP output connected to TIM1/15/16/17 and HRTIM1 SYSFLT - Break inputs - name: Connected - value: 1 -enum/MEM_MODE: - bit_size: 2 - variants: - - description: Main Flash memory mapped at 0x0000_0000 - name: MainFlash - value: 0 - - description: System Flash memory mapped at 0x0000_0000 - name: SystemFlash - value: 1 - - description: Main Flash memory mapped at 0x0000_0000 - name: MainFlash2 - value: 2 - - description: Embedded SRAM mapped at 0x0000_0000 - name: SRAM - value: 3 -enum/PAGE0_WP: - bit_size: 1 - variants: - - description: Write protection of pagex is disabled - name: Disabled - value: 0 - - description: Write protection of pagex is enabled - name: Enabled - value: 1 -enum/PVD_LOCK: - bit_size: 1 - variants: - - description: PVD interrupt disconnected from TIM15/16/17 Break input - name: Disconnected - value: 0 - - description: PVD interrupt connected to TIM15/16/17 Break input - name: Connected - value: 1 -enum/SPI1_RX_DMA_RMP: - bit_size: 2 - variants: - - description: SPI1_RX mapped on DMA1 CH2 - name: MapDma1Ch3 - value: 0 - - description: SPI1_RX mapped on DMA1 CH4 - name: MapDma1Ch5 - value: 1 - - description: SPI1_RX mapped on DMA1 CH6 - name: MapDma1Ch7 - value: 2 -enum/SPI1_TX_DMA_RMP: - bit_size: 2 - variants: - - description: SPI1_TX mapped on DMA1 CH3 - name: MapDma1Ch3 - value: 0 - - description: SPI1_TX mapped on DMA1 CH5 - name: MapDma1Ch5 - value: 1 - - description: SPI1_TX mapped on DMA1 CH7 - name: MapDma1Ch7 - value: 2 -enum/SRAM_PARITY_LOCK: - bit_size: 1 - variants: - - description: SRAM parity error signal disconnected from TIM1/15/16/17 and HRTIM1 - SYSFLT Break inputs - name: Disconnected - value: 0 - - description: SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT - Break inputs - name: Connected - value: 1 -enum/SRAM_PEFR: - bit_size: 1 - variants: - - description: No SRAM parity error detected - name: NoParityError - value: 0 - - description: SRAM parity error detected - name: ParityErrorDetected - value: 1 -enum/SRAM_PEFW: - bit_size: 1 - variants: - - description: Clear SRAM parity error flag - name: Clear - value: 1 -enum/TIM16_DMA_RMP: - bit_size: 1 - variants: - - description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 - name: NotRemapped - value: 0 - - description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 - name: Remapped - value: 1 -enum/TIM17_DMA_RMP: - bit_size: 1 - variants: - - description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 - name: NotRemapped - value: 0 - - description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 - name: Remapped - value: 1 -enum/TIM18_DAC2_OUT1_DMA_RMP: - bit_size: 1 - variants: - - description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5 - name: NotRemapped - value: 0 - - description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5 - name: Remapped - value: 1 -enum/TIM1_ITR3_RMP: - bit_size: 1 - variants: - - description: Not remapped - name: NotRemapped - value: 0 - - description: TIM1_ITR3 = TIM17_OC - name: Remapped - value: 1 -enum/TIM6_DAC1_CH1_DMA_RMP: - bit_size: 1 - variants: - - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 - name: NotRemapped - value: 0 - - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 - name: Remapped - value: 1 -enum/TIM6_DAC1_DMA_RMP: - bit_size: 1 - variants: - - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 - name: NotRemapped - value: 0 - - description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 - name: Remapped - value: 1 -enum/TIM6_DAC1_OUT1_DMA_RMP: - bit_size: 1 - variants: - - description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3 - name: NotRemapped - value: 0 - - description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3 - name: Remapped - value: 1 -enum/TIM7_DAC1_CH2_DMA_RMP: - bit_size: 1 - variants: - - description: Not remapped - name: NotRemapped - value: 0 - - description: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4 - name: Remapped - value: 1 -enum/TIM7_DAC1_OUT2_DMA_RMP: - bit_size: 1 - variants: - - description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4 - name: NotRemapped - value: 0 - - description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4 - name: Remapped - value: 1 -enum/USB_IT_RMP: - bit_size: 1 - variants: - - description: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt - lines 19, 20 and 42 respectively - name: NotRemapped - value: 0 - - description: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt - lines 74, 75 and 76 respectively - name: Remapped - value: 1 -enum/VBAT_MON: - bit_size: 1 - variants: - - description: Disable the power switch to not deliver VBAT voltage on ADC channel - 18 input - name: Disable - value: 0 - - description: Enable the power switch to deliver VBAT voltage on ADC channel 18 - input - name: Enable - value: 1 + - name: CFGR1 + description: configuration register 1 + byte_offset: 0 + fieldset: CFGR1 + - name: RCR + description: CCM SRAM protection register + byte_offset: 4 + fieldset: RCR + - name: EXTICR + description: external interrupt configuration register + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CFGR2 + description: configuration register 2 + byte_offset: 24 + fieldset: CFGR2 + - name: CFGR4 + description: configuration register 4 + byte_offset: 72 + fieldset: CFGR4 + - name: CFGR3 + description: configuration register 3 + byte_offset: 80 + fieldset: CFGR3 fieldset/CFGR1: description: configuration register 1 fields: - - bit_offset: 0 - bit_size: 2 - description: Memory mapping selection bits - enum: MEM_MODE - name: MEM_MODE - - bit_offset: 5 - bit_size: 1 - description: USB interrupt remap - enum: USB_IT_RMP - name: USB_IT_RMP - - bit_offset: 6 - bit_size: 1 - description: Timer 1 ITR3 selection - enum: TIM1_ITR3_RMP - name: TIM1_ITR3_RMP - - bit_offset: 7 - bit_size: 1 - description: DAC trigger remap (when TSEL = 001) - enum: DAC_TRIG_RMP - name: DAC_TRIG_RMP - - bit_offset: 7 - bit_size: 1 - description: DAC trigger remap (when TSEL = 001) - enum: DAC1_TRIG_RMP - name: DAC1_TRIG_RMP - - bit_offset: 8 - bit_size: 1 - description: ADC24 DMA remapping bit - enum: ADC2_DMA_RMP - name: ADC2_DMA_RMP - - bit_offset: 11 - bit_size: 1 - description: TIM16 DMA request remapping bit - enum: TIM16_DMA_RMP - name: TIM16_DMA_RMP - - bit_offset: 12 - bit_size: 1 - description: TIM17 DMA request remapping bit - enum: TIM17_DMA_RMP - name: TIM17_DMA_RMP - - bit_offset: 13 - bit_size: 1 - description: TIM6 and DAC1 DMA request remapping bit - enum: TIM6_DAC1_CH1_DMA_RMP - name: TIM6_DAC1_CH1_DMA_RMP - - bit_offset: 13 - bit_size: 1 - description: TIM6 and DAC1 DMA request remapping bit - enum: TIM6_DAC1_DMA_RMP - name: TIM6_DAC1_DMA_RMP - - bit_offset: 13 - bit_size: 1 - description: TIM6 and DAC1 DMA request remapping bit - enum: TIM6_DAC1_OUT1_DMA_RMP - name: TIM6_DAC1_OUT1_DMA_RMP - - bit_offset: 14 - bit_size: 1 - description: TIM7 and DAC2 DMA request remapping bit - enum: TIM7_DAC1_CH2_DMA_RMP - name: TIM7_DAC1_CH2_DMA_RMP - - bit_offset: 14 - bit_size: 1 - description: TIM7 and DAC2 DMA request remapping bit - enum: TIM7_DAC1_OUT2_DMA_RMP - name: TIM7_DAC1_OUT2_DMA_RMP - - bit_offset: 15 - bit_size: 1 - description: DAC2 channel1 DMA remap - enum: DAC2_CH1_DMA_RMP - name: DAC2_CH1_DMA_RMP - - bit_offset: 15 - bit_size: 1 - description: TIM18 and DAC2_OUT1 DMA request remapping bit - enum: TIM18_DAC2_OUT1_DMA_RMP - name: TIM18_DAC2_OUT1_DMA_RMP - - bit_offset: 16 - bit_size: 1 - description: Fast Mode Plus (FM+) driving capability activation bits. - enum: I2C_PB6_FMP - name: I2C_PB6_FMP - - bit_offset: 17 - bit_size: 1 - description: Fast Mode Plus (FM+) driving capability activation bits. - enum: I2C_PB7_FMP - name: I2C_PB7_FMP - - bit_offset: 18 - bit_size: 1 - description: Fast Mode Plus (FM+) driving capability activation bits. - enum: I2C_PB8_FMP - name: I2C_PB8_FMP - - bit_offset: 19 - bit_size: 1 - description: Fast Mode Plus (FM+) driving capability activation bits. - enum: I2C_PB9_FMP - name: I2C_PB9_FMP - - bit_offset: 20 - bit_size: 1 - description: I2C1 Fast Mode Plus - enum: I2C1_FMP - name: I2C1_FMP - - bit_offset: 21 - bit_size: 1 - description: I2C2 Fast Mode Plus - enum: I2C2_FMP - name: I2C2_FMP - - bit_offset: 22 - bit_size: 2 - description: Encoder mode - enum: ENCODER_MODE - name: ENCODER_MODE - - bit_offset: 24 - bit_size: 1 - description: I2C3 Fast Mode Plus - enum: I2C3_FMP - name: I2C3_FMP - - bit_offset: 24 - bit_size: 1 - description: VBAT monitoring enable - enum: VBAT_MON - name: VBAT_MON - - bit_offset: 26 - bit_size: 1 - description: Invalid operation interrupt enable - enum: FPU_IE0 - name: FPU_IE0 - - bit_offset: 27 - bit_size: 1 - description: Devide-by-zero interrupt enable - enum: FPU_IE1 - name: FPU_IE1 - - bit_offset: 28 - bit_size: 1 - description: Underflow interrupt enable - enum: FPU_IE2 - name: FPU_IE2 - - bit_offset: 29 - bit_size: 1 - description: Overflow interrupt enable - enum: FPU_IE3 - name: FPU_IE3 - - bit_offset: 30 - bit_size: 1 - description: Input denormal interrupt enable - enum: FPU_IE4 - name: FPU_IE4 - - bit_offset: 31 - bit_size: 1 - description: Inexact interrupt enable - enum: FPU_IE5 - name: FPU_IE5 + - name: MEM_MODE + description: Memory mapping selection bits + bit_offset: 0 + bit_size: 2 + enum: MEM_MODE + - name: USB_IT_RMP + description: USB interrupt remap + bit_offset: 5 + bit_size: 1 + enum: USB_IT_RMP + - name: TIM1_ITR3_RMP + description: Timer 1 ITR3 selection + bit_offset: 6 + bit_size: 1 + enum: TIM1_ITR3_RMP + - name: DAC1_TRIG_RMP + description: DAC trigger remap (when TSEL = 001) + bit_offset: 7 + bit_size: 1 + enum: DAC1_TRIG_RMP + - name: DAC_TRIG_RMP + description: DAC trigger remap (when TSEL = 001) + bit_offset: 7 + bit_size: 1 + enum: DAC_TRIG_RMP + - name: ADC2_DMA_RMP + description: ADC24 DMA remapping bit + bit_offset: 8 + bit_size: 1 + enum: ADC2_DMA_RMP + - name: TIM16_DMA_RMP + description: TIM16 DMA request remapping bit + bit_offset: 11 + bit_size: 1 + enum: TIM16_DMA_RMP + - name: TIM17_DMA_RMP + description: TIM17 DMA request remapping bit + bit_offset: 12 + bit_size: 1 + enum: TIM17_DMA_RMP + - name: TIM6_DAC1_CH1_DMA_RMP + description: TIM6 and DAC1 DMA request remapping bit + bit_offset: 13 + bit_size: 1 + enum: TIM6_DAC1_CH1_DMA_RMP + - name: TIM6_DAC1_DMA_RMP + description: TIM6 and DAC1 DMA request remapping bit + bit_offset: 13 + bit_size: 1 + enum: TIM6_DAC1_DMA_RMP + - name: TIM6_DAC1_OUT1_DMA_RMP + description: TIM6 and DAC1 DMA request remapping bit + bit_offset: 13 + bit_size: 1 + enum: TIM6_DAC1_OUT1_DMA_RMP + - name: TIM7_DAC1_CH2_DMA_RMP + description: TIM7 and DAC2 DMA request remapping bit + bit_offset: 14 + bit_size: 1 + enum: TIM7_DAC1_CH2_DMA_RMP + - name: TIM7_DAC1_OUT2_DMA_RMP + description: TIM7 and DAC2 DMA request remapping bit + bit_offset: 14 + bit_size: 1 + enum: TIM7_DAC1_OUT2_DMA_RMP + - name: DAC2_CH1_DMA_RMP + description: DAC2 channel1 DMA remap + bit_offset: 15 + bit_size: 1 + enum: DAC2_CH1_DMA_RMP + - name: TIM18_DAC2_OUT1_DMA_RMP + description: TIM18 and DAC2_OUT1 DMA request remapping bit + bit_offset: 15 + bit_size: 1 + enum: TIM18_DAC2_OUT1_DMA_RMP + - name: I2C_PB6_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 16 + bit_size: 1 + enum: I2C_PB6_FMP + - name: I2C_PB7_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 17 + bit_size: 1 + enum: I2C_PB7_FMP + - name: I2C_PB8_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 18 + bit_size: 1 + enum: I2C_PB8_FMP + - name: I2C_PB9_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 19 + bit_size: 1 + enum: I2C_PB9_FMP + - name: I2C1_FMP + description: I2C1 Fast Mode Plus + bit_offset: 20 + bit_size: 1 + enum: I2C1_FMP + - name: I2C2_FMP + description: I2C2 Fast Mode Plus + bit_offset: 21 + bit_size: 1 + enum: I2C2_FMP + - name: ENCODER_MODE + description: Encoder mode + bit_offset: 22 + bit_size: 2 + enum: ENCODER_MODE + - name: I2C3_FMP + description: I2C3 Fast Mode Plus + bit_offset: 24 + bit_size: 1 + enum: I2C3_FMP + - name: VBAT_MON + description: VBAT monitoring enable + bit_offset: 24 + bit_size: 1 + enum: VBAT_MON + - name: FPU_IE0 + description: Invalid operation interrupt enable + bit_offset: 26 + bit_size: 1 + enum: FPU_IE0 + - name: FPU_IE1 + description: Devide-by-zero interrupt enable + bit_offset: 27 + bit_size: 1 + enum: FPU_IE1 + - name: FPU_IE2 + description: Underflow interrupt enable + bit_offset: 28 + bit_size: 1 + enum: FPU_IE2 + - name: FPU_IE3 + description: Overflow interrupt enable + bit_offset: 29 + bit_size: 1 + enum: FPU_IE3 + - name: FPU_IE4 + description: Input denormal interrupt enable + bit_offset: 30 + bit_size: 1 + enum: FPU_IE4 + - name: FPU_IE5 + description: Inexact interrupt enable + bit_offset: 31 + bit_size: 1 + enum: FPU_IE5 fieldset/CFGR2: description: configuration register 2 fields: - - bit_offset: 0 - bit_size: 1 - description: Cortex-M0 LOCKUP bit enable bit - enum: LOCKUP_LOCK - name: LOCKUP_LOCK - - bit_offset: 1 - bit_size: 1 - description: SRAM parity lock bit - enum: SRAM_PARITY_LOCK - name: SRAM_PARITY_LOCK - - bit_offset: 2 - bit_size: 1 - description: PVD lock enable bit - enum: PVD_LOCK - name: PVD_LOCK - - bit_offset: 4 - bit_size: 1 - description: Bypass address bit 29 in parity calculation - enum: BYP_ADDR_PAR - name: BYP_ADDR_PAR - - bit_offset: 8 - bit_size: 1 - description: SRAM parity flag - enum_read: SRAM_PEFR - enum_write: SRAM_PEFW - name: SRAM_PEF + - name: LOCKUP_LOCK + description: Cortex-M0 LOCKUP bit enable bit + bit_offset: 0 + bit_size: 1 + enum: LOCKUP_LOCK + - name: SRAM_PARITY_LOCK + description: SRAM parity lock bit + bit_offset: 1 + bit_size: 1 + enum: SRAM_PARITY_LOCK + - name: PVD_LOCK + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + enum: PVD_LOCK + - name: BYP_ADDR_PAR + description: Bypass address bit 29 in parity calculation + bit_offset: 4 + bit_size: 1 + enum: BYP_ADDR_PAR + - name: SRAM_PEF + description: SRAM parity flag + bit_offset: 8 + bit_size: 1 + enum_read: SRAM_PEFR + enum_write: SRAM_PEFW fieldset/CFGR3: description: configuration register 3 fields: - - bit_offset: 0 - bit_size: 2 - description: SPI1_RX DMA remapping bit - enum: SPI1_RX_DMA_RMP - name: SPI1_RX_DMA_RMP - - bit_offset: 2 - bit_size: 2 - description: SPI1_TX DMA remapping bit - enum: SPI1_TX_DMA_RMP - name: SPI1_TX_DMA_RMP - - bit_offset: 4 - bit_size: 2 - description: I2C1_RX DMA remapping bit - enum: I2C1_RX_DMA_RMP - name: I2C1_RX_DMA_RMP - - bit_offset: 6 - bit_size: 2 - description: I2C1_TX DMA remapping bit - enum: I2C1_TX_DMA_RMP - name: I2C1_TX_DMA_RMP - - bit_offset: 8 - bit_size: 2 - description: ADC2 DMA remapping bit - enum: ADC2_DMA_RMP - name: ADC2_DMA_RMP - - bit_offset: 16 - bit_size: 1 - description: DAC1_CH1 / DAC1_CH2 Trigger remap - enum: DAC1_TRIG3_RMP - name: DAC1_TRIG3_RMP - - bit_offset: 17 - bit_size: 1 - description: DAC1_CH1 / DAC1_CH2 Trigger remap - enum: DAC1_TRIG5_RMP - name: DAC1_TRIG5_RMP + - name: SPI1_RX_DMA_RMP + description: SPI1_RX DMA remapping bit + bit_offset: 0 + bit_size: 2 + enum: SPI1_RX_DMA_RMP + - name: SPI1_TX_DMA_RMP + description: SPI1_TX DMA remapping bit + bit_offset: 2 + bit_size: 2 + enum: SPI1_TX_DMA_RMP + - name: I2C1_RX_DMA_RMP + description: I2C1_RX DMA remapping bit + bit_offset: 4 + bit_size: 2 + enum: I2C1_RX_DMA_RMP + - name: I2C1_TX_DMA_RMP + description: I2C1_TX DMA remapping bit + bit_offset: 6 + bit_size: 2 + enum: I2C1_TX_DMA_RMP + - name: ADC2_DMA_RMP + description: ADC2 DMA remapping bit + bit_offset: 8 + bit_size: 2 + enum: ADC2_DMA_RMP + - name: DAC1_TRIG3_RMP + description: DAC1_CH1 / DAC1_CH2 Trigger remap + bit_offset: 16 + bit_size: 1 + enum: DAC1_TRIG3_RMP + - name: DAC1_TRIG5_RMP + description: DAC1_CH1 / DAC1_CH2 Trigger remap + bit_offset: 17 + bit_size: 1 + enum: DAC1_TRIG5_RMP fieldset/CFGR4: description: configuration register 4 fields: - - bit_offset: 0 - bit_size: 1 - description: Controls the Input trigger of ADC12 regular channel EXT2 - enum: ADC12_EXT2_RMP - name: ADC12_EXT2_RMP - - bit_offset: 1 - bit_size: 1 - description: Controls the Input trigger of ADC12 regular channel EXT3 - enum: ADC12_EXT3_RMP - name: ADC12_EXT3_RMP - - bit_offset: 2 - bit_size: 1 - description: Controls the Input trigger of ADC12 regular channel EXT5 - enum: ADC12_EXT5_RMP - name: ADC12_EXT5_RMP - - bit_offset: 3 - bit_size: 1 - description: Controls the Input trigger of ADC12 regular channel EXT13 - enum: ADC12_EXT13_RMP - name: ADC12_EXT13_RMP - - bit_offset: 4 - bit_size: 1 - description: Controls the Input trigger of ADC12 regular channel EXT15 - enum: ADC12_EXT15_RMP - name: ADC12_EXT15_RMP - - bit_offset: 5 - bit_size: 1 - description: Controls the Input trigger of ADC12 injected channel JEXT3 - enum: ADC12_JEXT3_RMP - name: ADC12_JEXT3_RMP - - bit_offset: 6 - bit_size: 1 - description: Controls the Input trigger of ADC12 injected channel JEXT6 - enum: ADC12_JEXT6_RMP - name: ADC12_JEXT6_RMP - - bit_offset: 7 - bit_size: 1 - description: Controls the Input trigger of ADC12 injected channel JEXT13 - enum: ADC12_JEXT13_RMP - name: ADC12_JEXT13_RMP - - bit_offset: 8 - bit_size: 1 - description: Controls the Input trigger of ADC34 regular channel EXT5 - enum: ADC34_EXT5_RMP - name: ADC34_EXT5_RMP - - bit_offset: 9 - bit_size: 1 - description: Controls the Input trigger of ADC34 regular channel EXT6 - enum: ADC34_EXT6_RMP - name: ADC34_EXT6_RMP - - bit_offset: 10 - bit_size: 1 - description: Controls the Input trigger of ADC34 regular channel EXT15 - enum: ADC34_EXT15_RMP - name: ADC34_EXT15_RMP - - bit_offset: 11 - bit_size: 1 - description: Controls the Input trigger of ADC34 injected channel JEXT5 - enum: ADC34_JEXT5_RMP - name: ADC34_JEXT5_RMP - - bit_offset: 12 - bit_size: 1 - description: Controls the Input trigger of ADC34 injected channel JEXT11 - enum: ADC34_JEXT11_RMP - name: ADC34_JEXT11_RMP - - bit_offset: 13 - bit_size: 1 - description: Controls the Input trigger of ADC34 injected channel JEXT14 - enum: ADC34_JEXT14_RMP - name: ADC34_JEXT14_RMP + - name: ADC12_EXT2_RMP + description: Controls the Input trigger of ADC12 regular channel EXT2 + bit_offset: 0 + bit_size: 1 + enum: ADC12_EXT2_RMP + - name: ADC12_EXT3_RMP + description: Controls the Input trigger of ADC12 regular channel EXT3 + bit_offset: 1 + bit_size: 1 + enum: ADC12_EXT3_RMP + - name: ADC12_EXT5_RMP + description: Controls the Input trigger of ADC12 regular channel EXT5 + bit_offset: 2 + bit_size: 1 + enum: ADC12_EXT5_RMP + - name: ADC12_EXT13_RMP + description: Controls the Input trigger of ADC12 regular channel EXT13 + bit_offset: 3 + bit_size: 1 + enum: ADC12_EXT13_RMP + - name: ADC12_EXT15_RMP + description: Controls the Input trigger of ADC12 regular channel EXT15 + bit_offset: 4 + bit_size: 1 + enum: ADC12_EXT15_RMP + - name: ADC12_JEXT3_RMP + description: Controls the Input trigger of ADC12 injected channel JEXT3 + bit_offset: 5 + bit_size: 1 + enum: ADC12_JEXT3_RMP + - name: ADC12_JEXT6_RMP + description: Controls the Input trigger of ADC12 injected channel JEXT6 + bit_offset: 6 + bit_size: 1 + enum: ADC12_JEXT6_RMP + - name: ADC12_JEXT13_RMP + description: Controls the Input trigger of ADC12 injected channel JEXT13 + bit_offset: 7 + bit_size: 1 + enum: ADC12_JEXT13_RMP + - name: ADC34_EXT5_RMP + description: Controls the Input trigger of ADC34 regular channel EXT5 + bit_offset: 8 + bit_size: 1 + enum: ADC34_EXT5_RMP + - name: ADC34_EXT6_RMP + description: Controls the Input trigger of ADC34 regular channel EXT6 + bit_offset: 9 + bit_size: 1 + enum: ADC34_EXT6_RMP + - name: ADC34_EXT15_RMP + description: Controls the Input trigger of ADC34 regular channel EXT15 + bit_offset: 10 + bit_size: 1 + enum: ADC34_EXT15_RMP + - name: ADC34_JEXT5_RMP + description: Controls the Input trigger of ADC34 injected channel JEXT5 + bit_offset: 11 + bit_size: 1 + enum: ADC34_JEXT5_RMP + - name: ADC34_JEXT11_RMP + description: Controls the Input trigger of ADC34 injected channel JEXT11 + bit_offset: 12 + bit_size: 1 + enum: ADC34_JEXT11_RMP + - name: ADC34_JEXT14_RMP + description: Controls the Input trigger of ADC34 injected channel JEXT14 + bit_offset: 13 + bit_size: 1 + enum: ADC34_JEXT14_RMP fieldset/EXTICR: description: external interrupt configuration register fields: - - bit_offset: 0 - bit_size: 4 - description: EXTI x configuration - name: EXTI - array: - len: 4 - stride: 4 + - name: EXTI + description: EXTI x configuration + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 fieldset/RCR: description: CCM SRAM protection register fields: - - bit_offset: 0 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE0_WP - - bit_offset: 1 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE1_WP - - bit_offset: 2 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE2_WP - - bit_offset: 3 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE3_WP - - bit_offset: 4 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE4_WP - - bit_offset: 5 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE5_WP - - bit_offset: 6 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE6_WP - - bit_offset: 7 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE7_WP - - bit_offset: 8 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE8_WP - - bit_offset: 9 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE9_WP - - bit_offset: 10 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE10_WP - - bit_offset: 11 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE11_WP - - bit_offset: 12 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE12_WP - - bit_offset: 13 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE13_WP - - bit_offset: 14 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE14_WP - - bit_offset: 15 - bit_size: 1 - description: CCM SRAM page write protection bit - enum: PAGE0_WP - name: PAGE15_WP + - name: PAGE0_WP + description: CCM SRAM page write protection bit + bit_offset: 0 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE1_WP + description: CCM SRAM page write protection bit + bit_offset: 1 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE2_WP + description: CCM SRAM page write protection bit + bit_offset: 2 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE3_WP + description: CCM SRAM page write protection bit + bit_offset: 3 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE4_WP + description: CCM SRAM page write protection bit + bit_offset: 4 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE5_WP + description: CCM SRAM page write protection bit + bit_offset: 5 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE6_WP + description: CCM SRAM page write protection bit + bit_offset: 6 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE7_WP + description: CCM SRAM page write protection bit + bit_offset: 7 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE8_WP + description: CCM SRAM page write protection bit + bit_offset: 8 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE9_WP + description: CCM SRAM page write protection bit + bit_offset: 9 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE10_WP + description: CCM SRAM page write protection bit + bit_offset: 10 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE11_WP + description: CCM SRAM page write protection bit + bit_offset: 11 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE12_WP + description: CCM SRAM page write protection bit + bit_offset: 12 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE13_WP + description: CCM SRAM page write protection bit + bit_offset: 13 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE14_WP + description: CCM SRAM page write protection bit + bit_offset: 14 + bit_size: 1 + enum: PAGE0_WP + - name: PAGE15_WP + description: CCM SRAM page write protection bit + bit_offset: 15 + bit_size: 1 + enum: PAGE0_WP +enum/ADC12_EXT13_RMP: + bit_size: 1 + variants: + - name: Tim6 + description: Trigger source is TIM6_TRGO + value: 0 + - name: Tim20 + description: Trigger source is TIM20_CC2 + value: 1 +enum/ADC12_EXT15_RMP: + bit_size: 1 + variants: + - name: Tim3 + description: Trigger source is TIM3_CC4 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_CC3 + value: 1 +enum/ADC12_EXT2_RMP: + bit_size: 1 + variants: + - name: Tim1 + description: Trigger source is TIM3_CC3 + value: 0 + - name: Tim20 + description: rigger source is TIM20_TRGO + value: 1 +enum/ADC12_EXT3_RMP: + bit_size: 1 + variants: + - name: Tim2 + description: Trigger source is TIM2_CC2 + value: 0 + - name: Tim20 + description: rigger source is TIM20_TRGO2 + value: 1 +enum/ADC12_EXT5_RMP: + bit_size: 1 + variants: + - name: Tim4 + description: Trigger source is TIM4_CC4 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_CC1 + value: 1 +enum/ADC12_JEXT13_RMP: + bit_size: 1 + variants: + - name: Tim3 + description: Trigger source is TIM3_CC1 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_CC4 + value: 1 +enum/ADC12_JEXT3_RMP: + bit_size: 1 + variants: + - name: Tim2 + description: Trigger source is TIM2_CC1 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_TRGO + value: 1 +enum/ADC12_JEXT6_RMP: + bit_size: 1 + variants: + - name: Exti15 + description: Trigger source is EXTI line 15 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_TRGO2 + value: 1 +enum/ADC2_DMA_RMP: + bit_size: 1 + variants: + - name: MapDma2 + description: ADC2 mapped on DMA2 + value: 0 + - name: MapDma1Ch2 + description: ADC2 mapped on DMA1 channel 2 + value: 2 + - name: MapDma1Ch4 + description: ADC2 mapped on DMA1 channel 4 + value: 3 +enum/ADC34_EXT15_RMP: + bit_size: 1 + variants: + - name: Tim2 + description: Trigger source is TIM2_CC1 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_CC1 + value: 1 +enum/ADC34_EXT5_RMP: + bit_size: 1 + variants: + - name: Exti2 + description: Trigger source is EXTI line 2 when reset at 0 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_TRGO + value: 1 +enum/ADC34_EXT6_RMP: + bit_size: 1 + variants: + - name: Tim4 + description: Trigger source is TIM4_CC1 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_TRGO2 + value: 1 +enum/ADC34_JEXT11_RMP: + bit_size: 1 + variants: + - name: Tim1 + description: Trigger source is TIM1_CC3 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_TRGO2 + value: 1 +enum/ADC34_JEXT14_RMP: + bit_size: 1 + variants: + - name: Tim7 + description: Trigger source is TIM7_TRGO + value: 0 + - name: Tim20 + description: Trigger source is TIM20_CC2 + value: 1 +enum/ADC34_JEXT5_RMP: + bit_size: 1 + variants: + - name: Tim4 + description: Trigger source is TIM4_CC3 + value: 0 + - name: Tim20 + description: Trigger source is TIM20_TRGO + value: 1 +enum/BYP_ADDR_PAR: + bit_size: 1 + variants: + - name: NoBypass + description: The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated + value: 0 + - name: Bypass + description: The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated + value: 1 +enum/CFGR1_ADC2_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: ADC24 DMA requests mapped on DMA2 channels 1 and 2 + value: 0 + - name: Remapped + description: ADC24 DMA requests mapped on DMA2 channels 3 and 4 + value: 1 +enum/CFGR3_ADC2_DMA_RMP: + bit_size: 2 + variants: + - name: MapDma2 + description: ADC2 mapped on DMA2 + value: 0 + - name: MapDma1Ch2 + description: ADC2 mapped on DMA1 channel 2 + value: 2 + - name: MapDma1Ch4 + description: ADC2 mapped on DMA1 channel 4 + value: 3 +enum/DAC1_TRIG3_RMP: + bit_size: 1 + variants: + - name: Tim15 + description: DAC trigger is TIM15_TRGO + value: 0 + - name: HrTim1 + description: DAC trigger is HRTIM1_DAC1_TRIG1 + value: 1 +enum/DAC1_TRIG5_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: Not remapped + value: 0 + - name: Remapped + description: DAC trigger is HRTIM1_DAC1_TRIG2 + value: 1 +enum/DAC1_TRIG_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices + value: 0 + - name: Remapped + description: DAC trigger is TIM3_TRGO + value: 1 +enum/DAC2_CH1_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: Not remapped + value: 0 + - name: Remapped + description: DAC2_CH1 DMA requests mapped on DMA1 channel 5 + value: 1 +enum/DAC_TRIG_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: Not remapped + value: 0 + - name: Remapped + description: DAC trigger is TIM3_TRGO + value: 1 +enum/ENCODER_MODE: + bit_size: 2 + variants: + - name: NoRedirection + description: No redirection + value: 0 + - name: MapTim2Tim15 + description: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively + value: 1 + - name: MapTim3Tim15 + description: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively + value: 2 +enum/EXTI0: + bit_size: 4 + variants: + - name: PA0 + description: Select PA0 as the source input for the EXTI0 external interrupt + value: 0 + - name: PB0 + description: Select PB0 as the source input for the EXTI0 external interrupt + value: 1 + - name: PC0 + description: Select PC0 as the source input for the EXTI0 external interrupt + value: 2 + - name: PD0 + description: Select PD0 as the source input for the EXTI0 external interrupt + value: 3 + - name: PE0 + description: Select PE0 as the source input for the EXTI0 external interrupt + value: 4 + - name: PF0 + description: Select PF0 as the source input for the EXTI0 external interrupt + value: 5 +enum/EXTI1: + bit_size: 4 + variants: + - name: PA1 + description: Select PA1 as the source input for the EXTI1 external interrupt + value: 0 + - name: PB1 + description: Select PB1 as the source input for the EXTI1 external interrupt + value: 1 + - name: PC1 + description: Select PC1 as the source input for the EXTI1 external interrupt + value: 2 + - name: PD1 + description: Select PD1 as the source input for the EXTI1 external interrupt + value: 3 + - name: PE1 + description: Select PE1 as the source input for the EXTI1 external interrupt + value: 4 + - name: PF1 + description: Select PF1 as the source input for the EXTI1 external interrupt + value: 5 +enum/EXTI10: + bit_size: 4 + variants: + - name: PA10 + description: Select PA10 as the source input for the EXTI10 external interrupt + value: 0 + - name: PB10 + description: Select PB10 as the source input for the EXTI10 external interrupt + value: 1 + - name: PC10 + description: Select PC10 as the source input for the EXTI10 external interrupt + value: 2 + - name: PD10 + description: Select PD10 as the source input for the EXTI10 external interrupt + value: 3 + - name: PE10 + description: Select PE10 as the source input for the EXTI10 external interrupt + value: 4 + - name: PF10 + description: Select PF10 as the source input for the EXTI10 external interrupt + value: 5 +enum/EXTI11: + bit_size: 4 + variants: + - name: PA11 + description: Select PA11 as the source input for the EXTI11 external interrupt + value: 0 + - name: PB11 + description: Select PB11 as the source input for the EXTI11 external interrupt + value: 1 + - name: PC11 + description: Select PC11 as the source input for the EXTI11 external interrupt + value: 2 + - name: PD11 + description: Select PD11 as the source input for the EXTI11 external interrupt + value: 3 + - name: PE11 + description: Select PE11 as the source input for the EXTI11 external interrupt + value: 4 +enum/EXTI12: + bit_size: 4 + variants: + - name: PA12 + description: Select PA12 as the source input for the EXTI12 external interrupt + value: 0 + - name: PB12 + description: Select PB12 as the source input for the EXTI12 external interrupt + value: 1 + - name: PC12 + description: Select PC12 as the source input for the EXTI12 external interrupt + value: 2 + - name: PD12 + description: Select PD12 as the source input for the EXTI12 external interrupt + value: 3 + - name: PE12 + description: Select PE12 as the source input for the EXTI12 external interrupt + value: 4 +enum/EXTI13: + bit_size: 4 + variants: + - name: PA13 + description: Select PA13 as the source input for the EXTI13 external interrupt + value: 0 + - name: PB13 + description: Select PB13 as the source input for the EXTI13 external interrupt + value: 1 + - name: PC13 + description: Select PC13 as the source input for the EXTI13 external interrupt + value: 2 + - name: PD13 + description: Select PD13 as the source input for the EXTI13 external interrupt + value: 3 + - name: PE13 + description: Select PE13 as the source input for the EXTI13 external interrupt + value: 4 +enum/EXTI14: + bit_size: 4 + variants: + - name: PA14 + description: Select PA14 as the source input for the EXTI14 external interrupt + value: 0 + - name: PB14 + description: Select PB14 as the source input for the EXTI14 external interrupt + value: 1 + - name: PC14 + description: Select PC14 as the source input for the EXTI14 external interrupt + value: 2 + - name: PD14 + description: Select PD14 as the source input for the EXTI14 external interrupt + value: 3 + - name: PE14 + description: Select PE14 as the source input for the EXTI14 external interrupt + value: 4 +enum/EXTI15: + bit_size: 4 + variants: + - name: PA15 + description: Select PA15 as the source input for the EXTI15 external interrupt + value: 0 + - name: PB15 + description: Select PB15 as the source input for the EXTI15 external interrupt + value: 1 + - name: PC15 + description: Select PC15 as the source input for the EXTI15 external interrupt + value: 2 + - name: PD15 + description: Select PD15 as the source input for the EXTI15 external interrupt + value: 3 + - name: PE15 + description: Select PE15 as the source input for the EXTI15 external interrupt + value: 4 +enum/EXTI2: + bit_size: 4 + variants: + - name: PA2 + description: Select PA2 as the source input for the EXTI2 external interrupt + value: 0 + - name: PB2 + description: Select PB2 as the source input for the EXTI2 external interrupt + value: 1 + - name: PC2 + description: Select PC2 as the source input for the EXTI2 external interrupt + value: 2 + - name: PD2 + description: Select PD2 as the source input for the EXTI2 external interrupt + value: 3 + - name: PE2 + description: Select PE2 as the source input for the EXTI2 external interrupt + value: 4 + - name: PF2 + description: Select PF2 as the source input for the EXTI2 external interrupt + value: 5 +enum/EXTI3: + bit_size: 4 + variants: + - name: PA3 + description: Select PA3 as the source input for the EXTI3 external interrupt + value: 0 + - name: PB3 + description: Select PB3 as the source input for the EXTI3 external interrupt + value: 1 + - name: PC3 + description: Select PC3 as the source input for the EXTI3 external interrupt + value: 2 + - name: PD3 + description: Select PD3 as the source input for the EXTI3 external interrupt + value: 3 + - name: PE3 + description: Select PE3 as the source input for the EXTI3 external interrupt + value: 4 +enum/EXTI4: + bit_size: 4 + variants: + - name: PA4 + description: Select PA4 as the source input for the EXTI4 external interrupt + value: 0 + - name: PB4 + description: Select PB4 as the source input for the EXTI4 external interrupt + value: 1 + - name: PC4 + description: Select PC4 as the source input for the EXTI4 external interrupt + value: 2 + - name: PD4 + description: Select PD4 as the source input for the EXTI4 external interrupt + value: 3 + - name: PE4 + description: Select PE4 as the source input for the EXTI4 external interrupt + value: 4 + - name: PF4 + description: Select PF4 as the source input for the EXTI4 external interrupt + value: 5 +enum/EXTI5: + bit_size: 4 + variants: + - name: PA5 + description: Select PA5 as the source input for the EXTI5 external interrupt + value: 0 + - name: PB5 + description: Select PB5 as the source input for the EXTI5 external interrupt + value: 1 + - name: PC5 + description: Select PC5 as the source input for the EXTI5 external interrupt + value: 2 + - name: PD5 + description: Select PD5 as the source input for the EXTI5 external interrupt + value: 3 + - name: PE5 + description: Select PE5 as the source input for the EXTI5 external interrupt + value: 4 + - name: PF5 + description: Select PF5 as the source input for the EXTI5 external interrupt + value: 5 +enum/EXTI6: + bit_size: 4 + variants: + - name: PA6 + description: Select PA6 as the source input for the EXTI6 external interrupt + value: 0 + - name: PB6 + description: Select PB6 as the source input for the EXTI6 external interrupt + value: 1 + - name: PC6 + description: Select PC6 as the source input for the EXTI6 external interrupt + value: 2 + - name: PD6 + description: Select PD6 as the source input for the EXTI6 external interrupt + value: 3 + - name: PE6 + description: Select PE6 as the source input for the EXTI6 external interrupt + value: 4 + - name: PF6 + description: Select PF6 as the source input for the EXTI6 external interrupt + value: 5 +enum/EXTI7: + bit_size: 4 + variants: + - name: PA7 + description: Select PA7 as the source input for the EXTI7 external interrupt + value: 0 + - name: PB7 + description: Select PB7 as the source input for the EXTI7 external interrupt + value: 1 + - name: PC7 + description: Select PC7 as the source input for the EXTI7 external interrupt + value: 2 + - name: PD7 + description: Select PD7 as the source input for the EXTI7 external interrupt + value: 3 + - name: PE7 + description: Select PE7 as the source input for the EXTI7 external interrupt + value: 4 +enum/EXTI8: + bit_size: 4 + variants: + - name: PA8 + description: Select PA8 as the source input for the EXTI8 external interrupt + value: 0 + - name: PB8 + description: Select PB8 as the source input for the EXTI8 external interrupt + value: 1 + - name: PC8 + description: Select PC8 as the source input for the EXTI8 external interrupt + value: 2 + - name: PD8 + description: Select PD8 as the source input for the EXTI8 external interrupt + value: 3 + - name: PE8 + description: Select PE8 as the source input for the EXTI8 external interrupt + value: 4 +enum/EXTI9: + bit_size: 4 + variants: + - name: PA9 + description: Select PA9 as the source input for the EXTI9 external interrupt + value: 0 + - name: PB9 + description: Select PB9 as the source input for the EXTI9 external interrupt + value: 1 + - name: PC9 + description: Select PC9 as the source input for the EXTI9 external interrupt + value: 2 + - name: PD9 + description: Select PD9 as the source input for the EXTI9 external interrupt + value: 3 + - name: PE9 + description: Select PE9 as the source input for the EXTI9 external interrupt + value: 4 + - name: PF9 + description: Select PF9 as the source input for the EXTI9 external interrupt + value: 5 +enum/FPU_IE0: + bit_size: 1 + variants: + - name: Disabled + description: Invalid operation interrupt disable + value: 0 + - name: Enabled + description: Invalid operation interrupt enable + value: 1 +enum/FPU_IE1: + bit_size: 1 + variants: + - name: Disabled + description: Devide-by-zero interrupt disable + value: 0 + - name: Enabled + description: Devide-by-zero interrupt enable + value: 1 +enum/FPU_IE2: + bit_size: 1 + variants: + - name: Disabled + description: Underflow interrupt disable + value: 0 + - name: Enabled + description: Underflow interrupt enable + value: 1 +enum/FPU_IE3: + bit_size: 1 + variants: + - name: Disabled + description: Overflow interrupt disable + value: 0 + - name: Enabled + description: Overflow interrupt enable + value: 1 +enum/FPU_IE4: + bit_size: 1 + variants: + - name: Disabled + description: Input denormal interrupt disable + value: 0 + - name: Enabled + description: Input denormal interrupt enable + value: 1 +enum/FPU_IE5: + bit_size: 1 + variants: + - name: Disabled + description: Inexact interrupt disable + value: 0 + - name: Enabled + description: Inexact interrupt enable + value: 1 +enum/I2C1_FMP: + bit_size: 1 + variants: + - name: Standard + description: FM+ mode is controlled by I2C_Pxx_FMP bits only + value: 0 + - name: FMP + description: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits + value: 1 +enum/I2C1_RX_DMA_RMP: + bit_size: 2 + variants: + - name: MapDma1Ch7 + description: I2C1_RX mapped on DMA1 CH7 + value: 0 + - name: MapDma1Ch3 + description: I2C1_RX mapped on DMA1 CH3 + value: 1 + - name: MapDma1Ch5 + description: I2C1_RX mapped on DMA1 CH5 + value: 2 +enum/I2C1_TX_DMA_RMP: + bit_size: 2 + variants: + - name: MapDma1Ch6 + description: I2C1_TX mapped on DMA1 CH6 + value: 0 + - name: MapDma1Ch2 + description: I2C1_TX mapped on DMA1 CH2 + value: 1 + - name: MapDma1Ch4 + description: I2C1_TX mapped on DMA1 CH4 + value: 2 +enum/I2C2_FMP: + bit_size: 1 + variants: + - name: Standard + description: FM+ mode is controlled by I2C_Pxx_FMP bits only + value: 0 + - name: FMP + description: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits + value: 1 +enum/I2C3_FMP: + bit_size: 1 + variants: + - name: Standard + description: FM+ mode is controlled by I2C_Pxx_FMP bits only + value: 0 + - name: FMP + description: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits + value: 1 +enum/I2C_PB6_FMP: + bit_size: 1 + variants: + - name: Standard + description: PB6 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed + value: 1 +enum/I2C_PB7_FMP: + bit_size: 1 + variants: + - name: Standard + description: PB7 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed + value: 1 +enum/I2C_PB8_FMP: + bit_size: 1 + variants: + - name: Standard + description: PB8 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed + value: 1 +enum/I2C_PB9_FMP: + bit_size: 1 + variants: + - name: Standard + description: PB9 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed + value: 1 +enum/LOCKUP_LOCK: + bit_size: 1 + variants: + - name: Disconnected + description: Cortex-M4 LOCKUP output disconnected from TIM1/15/16/17 Break inputs and HRTIM1 SYSFLT. + value: 0 + - name: Connected + description: Cortex-M4 LOCKUP output connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs + value: 1 +enum/MEM_MODE: + bit_size: 2 + variants: + - name: MainFlash + description: Main Flash memory mapped at 0x0000_0000 + value: 0 + - name: SystemFlash + description: System Flash memory mapped at 0x0000_0000 + value: 1 + - name: MainFlash2 + description: Main Flash memory mapped at 0x0000_0000 + value: 2 + - name: SRAM + description: Embedded SRAM mapped at 0x0000_0000 + value: 3 +enum/PAGE0_WP: + bit_size: 1 + variants: + - name: Disabled + description: Write protection of pagex is disabled + value: 0 + - name: Enabled + description: Write protection of pagex is enabled + value: 1 +enum/PVD_LOCK: + bit_size: 1 + variants: + - name: Disconnected + description: PVD interrupt disconnected from TIM15/16/17 Break input + value: 0 + - name: Connected + description: PVD interrupt connected to TIM15/16/17 Break input + value: 1 +enum/SPI1_RX_DMA_RMP: + bit_size: 2 + variants: + - name: MapDma1Ch3 + description: SPI1_RX mapped on DMA1 CH2 + value: 0 + - name: MapDma1Ch5 + description: SPI1_RX mapped on DMA1 CH4 + value: 1 + - name: MapDma1Ch7 + description: SPI1_RX mapped on DMA1 CH6 + value: 2 +enum/SPI1_TX_DMA_RMP: + bit_size: 2 + variants: + - name: MapDma1Ch3 + description: SPI1_TX mapped on DMA1 CH3 + value: 0 + - name: MapDma1Ch5 + description: SPI1_TX mapped on DMA1 CH5 + value: 1 + - name: MapDma1Ch7 + description: SPI1_TX mapped on DMA1 CH7 + value: 2 +enum/SRAM_PARITY_LOCK: + bit_size: 1 + variants: + - name: Disconnected + description: SRAM parity error signal disconnected from TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs + value: 0 + - name: Connected + description: SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs + value: 1 +enum/SRAM_PEFR: + bit_size: 1 + variants: + - name: NoParityError + description: No SRAM parity error detected + value: 0 + - name: ParityErrorDetected + description: SRAM parity error detected + value: 1 +enum/SRAM_PEFW: + bit_size: 1 + variants: + - name: Clear + description: Clear SRAM parity error flag + value: 1 +enum/TIM16_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 + value: 0 + - name: Remapped + description: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 + value: 1 +enum/TIM17_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 + value: 0 + - name: Remapped + description: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 + value: 1 +enum/TIM18_DAC2_OUT1_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5 + value: 0 + - name: Remapped + description: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5 + value: 1 +enum/TIM1_ITR3_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: Not remapped + value: 0 + - name: Remapped + description: TIM1_ITR3 = TIM17_OC + value: 1 +enum/TIM6_DAC1_CH1_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 + value: 0 + - name: Remapped + description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 + value: 1 +enum/TIM6_DAC1_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 + value: 0 + - name: Remapped + description: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 + value: 1 +enum/TIM6_DAC1_OUT1_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3 + value: 0 + - name: Remapped + description: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3 + value: 1 +enum/TIM7_DAC1_CH2_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: Not remapped + value: 0 + - name: Remapped + description: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4 + value: 1 +enum/TIM7_DAC1_OUT2_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4 + value: 0 + - name: Remapped + description: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4 + value: 1 +enum/USB_IT_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively" + value: 0 + - name: Remapped + description: "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively" + value: 1 +enum/VBAT_MON: + bit_size: 1 + variants: + - name: Disable + description: Disable the power switch to not deliver VBAT voltage on ADC channel 18 input + value: 0 + - name: Enable + description: Enable the power switch to deliver VBAT voltage on ADC channel 18 input + value: 1 diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index 851964a..7df0f79 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -3,18 +3,6 @@ block/TIM_ADV: extends: TIM_GP16 description: Advanced-timers items: - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR - - name: BDTR - description: break and dead-time register - byte_offset: 68 - fieldset: BDTR - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_ADV - name: CR2 description: control register 2 byte_offset: 4 @@ -32,6 +20,18 @@ block/TIM_ADV: byte_offset: 20 access: Write fieldset: EGR_ADV + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_ADV + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR block/TIM_BASIC: description: Basic timer items: @@ -119,6 +119,13 @@ block/TIM_GP16: description: prescaler byte_offset: 40 fieldset: PSC + - name: CCR + description: capture/compare register + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_16 - name: DCR description: DMA control register byte_offset: 72 @@ -127,13 +134,6 @@ block/TIM_GP16: description: DMA address for full transfer byte_offset: 76 fieldset: DMAR - - name: CCR - description: capture/compare register - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_16 block/TIM_GP32: extends: TIM_GP16 description: General purpose 32-bit timer diff --git a/data/registers/usart_v2.yaml b/data/registers/usart_v2.yaml index b3d9d92..7f8a06b 100644 --- a/data/registers/usart_v2.yaml +++ b/data/registers/usart_v2.yaml @@ -116,6 +116,11 @@ fieldset/CR1: bit_offset: 12 bit_size: 1 enum: M0 + - name: M1 + description: Word length + bit_offset: 12 + bit_size: 1 + enum: M1 - name: MME description: Mute mode enable bit_offset: 13 @@ -148,11 +153,6 @@ fieldset/CR1: description: End of Block interrupt enable bit_offset: 27 bit_size: 1 - - name: M1 - description: Word length - bit_offset: 12 - bit_size: 1 - enum: M1 fieldset/CR2: description: Control register 2 fields: