15 Commits

Author SHA1 Message Date
Dario Nieuwenhuis
ee64389697 Rename HSI16 -> HSI 2023-10-22 22:32:08 +02:00
xoviat
8bd7ff51b0 rcc: expand checker to all chips 2023-10-18 21:01:57 -05:00
xoviat
8b8686a852 rcc: more mux and enum cleanup 2023-10-15 10:37:36 -05:00
Dario Nieuwenhuis
71f81b44e3 Rename HSE32 -> HSE. 2023-10-11 00:29:01 +02:00
Dario Nieuwenhuis
ff45aa382e rcc: add more missing enums. 2023-10-11 00:07:28 +02:00
Dario Nieuwenhuis
11256dc370 chiptool fmt. 2023-10-07 00:09:14 +02:00
Matt Ickstadt
2ceed56e94 RCC: add LSEDRV enums for WB and WL series
These are in the RMs but previously missing.
2023-10-05 11:18:49 -05:00
shakencodes
0adf2a75d1 Add enums MCOPRE & MCOSEL to wl5 & wle targets 2023-09-26 10:55:19 -07:00
Dario Nieuwenhuis
2f97514774 pwr: add all VOS enums. 2023-09-18 02:57:23 +02:00
xoviat
a70aa2f06a rcc: use same name for bus psc 2023-09-16 15:43:03 -05:00
Dario Nieuwenhuis
8fec79a722 rcc consistency fixes. 2023-09-16 02:34:03 +02:00
Dario Nieuwenhuis
86fb0cfc2f chiptool fmt. 2023-09-16 02:34:03 +02:00
Olle Sandberg
9c71725bf2 Support STM32WL5x ADC peripheral 2023-09-05 12:22:56 +02:00
Dario Nieuwenhuis
3b6363dffb wl rcc: rename SPI2S2 -> SPI2 2021-08-19 22:37:07 +02:00
Dario Nieuwenhuis
6af9f2c0d1 Add RCC for F3, F7, G4, H7AB, L1, L5, WB*, WL5, WLE 2021-08-19 19:13:30 +02:00