1425 lines
40 KiB
YAML
1425 lines
40 KiB
YAML
---
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block/RCC:
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description: Reset and clock control
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items:
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- name: CR
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description: Clock control register
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byte_offset: 0
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fieldset: CR
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- name: ICSCR
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description: Internal clock sources calibration register
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byte_offset: 4
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fieldset: ICSCR
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- name: CFGR
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description: Clock configuration register
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byte_offset: 8
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fieldset: CFGR
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- name: PLLCFGR
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description: PLL configuration register
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byte_offset: 12
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fieldset: PLLCFGR
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- name: CIER
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description: Clock interrupt enable register
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byte_offset: 24
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fieldset: CIER
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- name: CIFR
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description: Clock interrupt flag register
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byte_offset: 28
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access: Read
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fieldset: CIFR
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- name: CICR
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description: Clock interrupt clear register
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byte_offset: 32
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access: Write
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fieldset: CICR
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- name: AHB1RSTR
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description: AHB1 peripheral reset register
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byte_offset: 40
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fieldset: AHB1RSTR
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- name: AHB2RSTR
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description: AHB2 peripheral reset register
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byte_offset: 44
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fieldset: AHB2RSTR
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- name: AHB3RSTR
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description: AHB3 peripheral reset register
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byte_offset: 48
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fieldset: AHB3RSTR
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- name: APB1RSTR1
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description: APB1 peripheral reset register 1
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byte_offset: 56
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fieldset: APB1RSTR1
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- name: APB1RSTR2
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description: APB1 peripheral reset register 2
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byte_offset: 60
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fieldset: APB1RSTR2
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- name: APB2RSTR
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description: APB2 peripheral reset register
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byte_offset: 64
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fieldset: APB2RSTR
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- name: APB3RSTR
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description: APB3 peripheral reset register
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byte_offset: 68
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fieldset: APB3RSTR
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- name: AHB1ENR
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description: AHB1 peripheral clock enable register
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byte_offset: 72
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fieldset: AHB1ENR
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- name: AHB2ENR
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description: AHB2 peripheral clock enable register
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byte_offset: 76
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fieldset: AHB2ENR
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- name: AHB3ENR
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description: AHB3 peripheral clock enable register
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byte_offset: 80
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fieldset: AHB3ENR
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- name: APB1ENR1
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description: APB1 peripheral clock enable register 1
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byte_offset: 88
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fieldset: APB1ENR1
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- name: APB1ENR2
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description: APB1 peripheral clock enable register 2
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byte_offset: 92
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fieldset: APB1ENR2
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- name: APB2ENR
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description: APB2 peripheral clock enable register
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byte_offset: 96
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fieldset: APB2ENR
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- name: APB3ENR
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description: APB3 peripheral clock enable register
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byte_offset: 100
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fieldset: APB3ENR
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- name: AHB1SMENR
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description: AHB1 peripheral clocks enable in Sleep modes register
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byte_offset: 104
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fieldset: AHB1SMENR
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- name: AHB2SMENR
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description: AHB2 peripheral clocks enable in Sleep modes register
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byte_offset: 108
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fieldset: AHB2SMENR
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- name: AHB3SMENR
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description: AHB3 peripheral clocks enable in Sleep and Stop modes register
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byte_offset: 112
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fieldset: AHB3SMENR
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- name: APB1SMENR1
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description: APB1 peripheral clocks enable in Sleep mode register 1
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byte_offset: 120
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fieldset: APB1SMENR1
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- name: APB1SMENR2
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description: APB1 peripheral clocks enable in Sleep mode register 2
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byte_offset: 124
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fieldset: APB1SMENR2
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- name: APB2SMENR
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description: APB2 peripheral clocks enable in Sleep mode register
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byte_offset: 128
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fieldset: APB2SMENR
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- name: APB3SMENR
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description: APB3 peripheral clock enable in Sleep mode register
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byte_offset: 132
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fieldset: APB3SMENR
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- name: CCIPR
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description: Peripherals independent clock configuration register
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byte_offset: 136
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fieldset: CCIPR
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- name: BDCR
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description: Backup domain control register
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byte_offset: 144
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fieldset: BDCR
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- name: CSR
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description: Control/status register
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byte_offset: 148
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fieldset: CSR
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- name: EXTCFGR
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description: Extended clock recovery register
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byte_offset: 264
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fieldset: EXTCFGR
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- name: C2AHB1ENR
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description: CPU2 AHB1 peripheral clock enable register
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byte_offset: 328
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fieldset: C2AHB1ENR
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- name: C2AHB2ENR
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description: CPU2 AHB2 peripheral clock enable register
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byte_offset: 332
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fieldset: C2AHB2ENR
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- name: C2AHB3ENR
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description: "CPU2 AHB3 peripheral clock enable register [dual core device only]"
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byte_offset: 336
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fieldset: C2AHB3ENR
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- name: C2APB1ENR1
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description: "CPU2 APB1 peripheral clock enable register 1 [dual core device only]"
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byte_offset: 344
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fieldset: C2APB1ENR1
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- name: C2APB1ENR2
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description: "CPU2 APB1 peripheral clock enable register 2 [dual core device only]"
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byte_offset: 348
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fieldset: C2APB1ENR2
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- name: C2APB2ENR
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description: "CPU2 APB2 peripheral clock enable register [dual core device only]"
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byte_offset: 352
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fieldset: C2APB2ENR
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- name: C2APB3ENR
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description: "CPU2 APB3 peripheral clock enable register [dual core device only]"
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byte_offset: 356
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fieldset: C2APB3ENR
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- name: C2AHB1SMENR
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description: "CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]"
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byte_offset: 360
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fieldset: C2AHB1SMENR
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- name: C2AHB2SMENR
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description: "CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]"
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byte_offset: 364
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fieldset: C2AHB2SMENR
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- name: C2AHB3SMENR
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description: "CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]"
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byte_offset: 368
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fieldset: C2AHB3SMENR
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- name: C2APB1SMENR1
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description: "CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only]"
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byte_offset: 376
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fieldset: C2APB1SMENR1
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- name: C2APB1SMENR2
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description: "CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]"
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byte_offset: 380
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fieldset: C2APB1SMENR2
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- name: C2APB2SMENR
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description: "CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only]"
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byte_offset: 384
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fieldset: C2APB2SMENR
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- name: C2APB3SMENR
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description: "CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only]"
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byte_offset: 388
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fieldset: C2APB3SMENR
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fieldset/AHB1ENR:
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description: AHB1 peripheral clock enable register
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fields:
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- name: DMA1EN
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description: CPU1 DMA1 clock enable
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bit_offset: 0
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bit_size: 1
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- name: DMA2EN
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description: CPU1 DMA2 clock enable
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bit_offset: 1
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bit_size: 1
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- name: DMAMUX1EN
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description: CPU1 DMAMUX1 clock enable
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bit_offset: 2
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bit_size: 1
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- name: CRCEN
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description: CPU1 CRC clock enable
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bit_offset: 12
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bit_size: 1
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fieldset/AHB1RSTR:
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description: AHB1 peripheral reset register
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fields:
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- name: DMA1RST
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description: DMA1 reset
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bit_offset: 0
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bit_size: 1
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- name: DMA2RST
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description: DMA2 reset
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bit_offset: 1
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bit_size: 1
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- name: DMAMUX1RST
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description: DMAMUX1 reset
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bit_offset: 2
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bit_size: 1
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- name: CRCRST
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description: CRC reset
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bit_offset: 12
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bit_size: 1
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fieldset/AHB1SMENR:
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description: AHB1 peripheral clocks enable in Sleep modes register
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fields:
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- name: DMA1SMEN
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description: DMA1 clock enable during CPU1 CSleep mode.
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bit_offset: 0
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bit_size: 1
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- name: DMA2SMEN
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description: DMA2 clock enable during CPU1 CSleep mode
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bit_offset: 1
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bit_size: 1
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- name: DMAMUX1SMEN
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description: DMAMUX1 clock enable during CPU1 CSleep mode.
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bit_offset: 2
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bit_size: 1
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- name: CRCSMEN
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description: CRC clock enable during CPU1 CSleep mode.
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bit_offset: 12
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bit_size: 1
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fieldset/AHB2ENR:
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description: AHB2 peripheral clock enable register
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fields:
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- name: GPIOAEN
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description: CPU1 IO port A clock enable
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bit_offset: 0
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bit_size: 1
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- name: GPIOBEN
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description: CPU1 IO port B clock enable
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bit_offset: 1
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bit_size: 1
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- name: GPIOCEN
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description: CPU1 IO port C clock enable
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bit_offset: 2
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bit_size: 1
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- name: GPIOHEN
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description: CPU1 IO port H clock enable
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bit_offset: 7
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bit_size: 1
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fieldset/AHB2RSTR:
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description: AHB2 peripheral reset register
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fields:
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- name: GPIOARST
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description: IO port A reset
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bit_offset: 0
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bit_size: 1
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- name: GPIOBRST
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description: IO port B reset
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bit_offset: 1
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bit_size: 1
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- name: GPIOCRST
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description: IO port C reset
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bit_offset: 2
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bit_size: 1
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- name: GPIOHRST
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description: IO port H reset
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bit_offset: 7
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bit_size: 1
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fieldset/AHB2SMENR:
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description: AHB2 peripheral clocks enable in Sleep modes register
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fields:
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- name: GPIOASMEN
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description: IO port A clock enable during CPU1 CSleep mode.
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bit_offset: 0
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bit_size: 1
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- name: GPIOBSMEN
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description: IO port B clock enable during CPU1 CSleep mode.
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bit_offset: 1
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bit_size: 1
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- name: GPIOCSMEN
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description: IO port C clock enable during CPU1 CSleep mode.
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bit_offset: 2
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bit_size: 1
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- name: GPIOHSMEN
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description: IO port H clock enable during CPU1 CSleep mode.
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bit_offset: 7
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bit_size: 1
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fieldset/AHB3ENR:
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description: AHB3 peripheral clock enable register
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fields:
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- name: PKAEN
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description: PKAEN
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bit_offset: 16
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bit_size: 1
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- name: AESEN
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description: AESEN
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bit_offset: 17
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bit_size: 1
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- name: RNGEN
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description: RNGEN
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bit_offset: 18
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bit_size: 1
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- name: HSEMEN
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description: HSEMEN
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bit_offset: 19
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bit_size: 1
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- name: IPCCEN
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description: IPCCEN
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bit_offset: 20
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bit_size: 1
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- name: FLASHEN
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description: CPU1 Flash interface clock enable
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bit_offset: 25
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bit_size: 1
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fieldset/AHB3RSTR:
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description: AHB3 peripheral reset register
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fields:
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- name: PKARST
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description: PKARST
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bit_offset: 16
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bit_size: 1
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- name: AESRST
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description: AESRST
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bit_offset: 17
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bit_size: 1
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- name: RNGRST
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description: RNGRST
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bit_offset: 18
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bit_size: 1
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- name: HSEMRST
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description: HSEMRST
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bit_offset: 19
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bit_size: 1
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- name: IPCCRST
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description: IPCCRST
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bit_offset: 20
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bit_size: 1
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- name: FLASHRST
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description: Flash interface reset
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bit_offset: 25
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bit_size: 1
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fieldset/AHB3SMENR:
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description: AHB3 peripheral clocks enable in Sleep and Stop modes register
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fields:
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- name: PKASMEN
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description: PKA accelerator clock enable during CPU1 CSleep mode.
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bit_offset: 16
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bit_size: 1
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- name: AESSMEN
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description: AES accelerator clock enable during CPU1 CSleep mode.
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bit_offset: 17
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bit_size: 1
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- name: RNGSMEN
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description: True RNG clocks enable during CPU1 Csleep and CStop modes
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bit_offset: 18
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bit_size: 1
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- name: SRAM1SMEN
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description: SRAM1 interface clock enable during CPU1 CSleep mode.
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bit_offset: 23
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bit_size: 1
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- name: SRAM2SMEN
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description: SRAM2 memory interface clock enable during CPU1 CSleep mode
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bit_offset: 24
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bit_size: 1
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- name: FLASHSMEN
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description: Flash interface clock enable during CPU1 CSleep mode.
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bit_offset: 25
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bit_size: 1
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fieldset/APB1ENR1:
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description: APB1 peripheral clock enable register 1
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fields:
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- name: TIM2EN
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description: CPU1 TIM2 timer clock enable
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bit_offset: 0
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bit_size: 1
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- name: RTCAPBEN
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description: CPU1 RTC APB clock enable
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bit_offset: 10
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bit_size: 1
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- name: WWDGEN
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description: CPU1 Window watchdog clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI2EN
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description: CPU1 SPI2 clock enable
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bit_offset: 14
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bit_size: 1
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- name: USART2EN
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description: CPU1 USART2 clock enable
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bit_offset: 17
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bit_size: 1
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- name: I2C1EN
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description: CPU1 I2C1 clocks enable
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bit_offset: 21
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bit_size: 1
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- name: I2C2EN
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description: CPU1 I2C2 clocks enable
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bit_offset: 22
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bit_size: 1
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- name: I2C3EN
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description: CPU1 I2C3 clocks enable
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bit_offset: 23
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bit_size: 1
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- name: DAC1EN
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description: CPU1 DAC1 clock enable
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bit_offset: 29
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bit_size: 1
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- name: LPTIM1EN
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description: CPU1 Low power timer 1 clocks enable
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bit_offset: 31
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bit_size: 1
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fieldset/APB1ENR2:
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description: APB1 peripheral clock enable register 2
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fields:
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- name: LPUART1EN
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description: CPU1 Low power UART 1 clocks enable
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bit_offset: 0
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bit_size: 1
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- name: LPTIM2EN
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description: CPU1 Low power timer 2 clocks enable
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bit_offset: 5
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bit_size: 1
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- name: LPTIM3EN
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description: CPU1 Low power timer 3 clocks enable
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bit_offset: 6
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bit_size: 1
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fieldset/APB1RSTR1:
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description: APB1 peripheral reset register 1
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fields:
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- name: TIM2RST
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description: TIM2 timer reset
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bit_offset: 0
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bit_size: 1
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- name: SPI2RST
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description: SPI2 reset
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bit_offset: 14
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bit_size: 1
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- name: USART2RST
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description: USART2 reset
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bit_offset: 17
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bit_size: 1
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- name: I2C1RST
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description: I2C1 reset
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bit_offset: 21
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bit_size: 1
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- name: I2C2RST
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description: I2C2 reset
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bit_offset: 22
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bit_size: 1
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- name: I2C3RST
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description: I2C3 reset
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bit_offset: 23
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bit_size: 1
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- name: DACRST
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description: DAC1 reset
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bit_offset: 29
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bit_size: 1
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- name: LPTIM1RST
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description: Low Power Timer 1 reset
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bit_offset: 31
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bit_size: 1
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fieldset/APB1RSTR2:
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description: APB1 peripheral reset register 2
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fields:
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- name: LPUART1RST
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description: Low-power UART 1 reset
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bit_offset: 0
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bit_size: 1
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- name: LPTIM2RST
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description: Low-power timer 2 reset
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bit_offset: 5
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bit_size: 1
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- name: LPTIM3RST
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description: Low-power timer 3 reset
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bit_offset: 6
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bit_size: 1
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fieldset/APB1SMENR1:
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description: APB1 peripheral clocks enable in Sleep mode register 1
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fields:
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- name: TIM2SMEN
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description: TIM2 timer clock enable during CPU1 CSleep mode.
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bit_offset: 0
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bit_size: 1
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- name: RTCAPBSMEN
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description: RTC bus clock enable during CPU1 CSleep mode.
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bit_offset: 10
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bit_size: 1
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- name: WWDGSMEN
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description: Window watchdog clocks enable during CPU1 CSleep mode.
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bit_offset: 11
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bit_size: 1
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- name: SPI2SMEN
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description: SPI2 clock enable during CPU1 CSleep mode.
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bit_offset: 14
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bit_size: 1
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- name: USART2SMEN
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description: USART2 clock enable during CPU1 CSleep mode.
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bit_offset: 17
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bit_size: 1
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- name: I2C1SMEN
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description: I2C1 clock enable during CPU1 Csleep and CStop modes
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bit_offset: 21
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bit_size: 1
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- name: I2C2SMEN
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description: I2C2 clock enable during CPU1 Csleep and CStop modes
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bit_offset: 22
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bit_size: 1
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- name: I2C3SMEN
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description: I2C3 clock enable during CPU1 Csleep and CStop modes
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bit_offset: 23
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bit_size: 1
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- name: DACSMEN
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description: DAC1 clock enable during CPU1 CSleep mode.
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bit_offset: 29
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bit_size: 1
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- name: LPTIM1SMEN
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description: Low power timer 1 clock enable during CPU1 Csleep and CStop mode
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB1SMENR2:
|
|
description: APB1 peripheral clocks enable in Sleep mode register 2
|
|
fields:
|
|
- name: LPUART1SMEN
|
|
description: Low power UART 1 clock enable during CPU1 Csleep and CStop modes.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPTIM2SMEN
|
|
description: Low power timer 2 clock enable during CPU1 Csleep and CStop modes
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LPTIM3SMEN
|
|
description: Low power timer 3 clock enable during CPU1 Csleep and CStop modes
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
fieldset/APB2ENR:
|
|
description: APB2 peripheral clock enable register
|
|
fields:
|
|
- name: ADCEN
|
|
description: CPU1 ADC clocks enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: TIM1EN
|
|
description: CPU1 TIM1 timer clock enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1EN
|
|
description: CPU1 SPI1 clock enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1EN
|
|
description: CPU1 USART1clocks enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16EN
|
|
description: CPU1 TIM16 timer clock enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17EN
|
|
description: CPU1 TIM17 timer clock enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
fieldset/APB2RSTR:
|
|
description: APB2 peripheral reset register
|
|
fields:
|
|
- name: ADCRST
|
|
description: ADC reset
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: TIM1RST
|
|
description: TIM1 timer reset
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1RST
|
|
description: SPI1 reset
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1RST
|
|
description: USART1 reset
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16RST
|
|
description: TIM16 timer reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17RST
|
|
description: TIM17 timer reset
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
fieldset/APB2SMENR:
|
|
description: APB2 peripheral clocks enable in Sleep mode register
|
|
fields:
|
|
- name: ADCSMEN
|
|
description: ADC clocks enable during CPU1 Csleep and CStop modes
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: TIM1SMEN
|
|
description: TIM1 timer clock enable during CPU1 CSleep mode.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1SMEN
|
|
description: SPI1 clock enable during CPU1 CSleep mode.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1SMEN
|
|
description: USART1 clock enable during CPU1 Csleep and CStop modes.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16SMEN
|
|
description: TIM16 timer clock enable during CPU1 CSleep mode.
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17SMEN
|
|
description: TIM17 timer clock enable during CPU1 CSleep mode.
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
fieldset/APB3ENR:
|
|
description: APB3 peripheral clock enable register
|
|
fields:
|
|
- name: SUBGHZSPIEN
|
|
description: sub-GHz radio SPI clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/APB3RSTR:
|
|
description: APB3 peripheral reset register
|
|
fields:
|
|
- name: SUBGHZSPIRST
|
|
description: Sub-GHz radio SPI reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/APB3SMENR:
|
|
description: APB3 peripheral clock enable in Sleep mode register
|
|
fields:
|
|
- name: SUBGHZSPISMEN
|
|
description: Sub-GHz radio SPI clock enable during Sleep and Stop modes
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/BDCR:
|
|
description: Backup domain control register
|
|
fields:
|
|
- name: LSEON
|
|
description: LSE oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDY
|
|
description: LSE oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSEBYP
|
|
description: LSE oscillator bypass
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LSEDRV
|
|
description: LSE oscillator drive capability
|
|
bit_offset: 3
|
|
bit_size: 2
|
|
- name: LSECSSON
|
|
description: CSS on LSE enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LSECSSD
|
|
description: CSS on LSE failure Detection
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: LSESYSEN
|
|
description: LSE system clock enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: RTCSEL
|
|
description: RTC clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
- name: LSESYSRDY
|
|
description: LSE system clock ready
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: RTCEN
|
|
description: RTC clock enable
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: BDRST
|
|
description: Backup domain software reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: LSCOEN
|
|
description: Low speed clock output enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: LSCOSEL
|
|
description: Low speed clock output selection
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/C2AHB1ENR:
|
|
description: CPU2 AHB1 peripheral clock enable register
|
|
fields:
|
|
- name: DMA1EN
|
|
description: CPU2 DMA1 clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: DMA2EN
|
|
description: CPU2 DMA2 clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: DMAMUX1EN
|
|
description: CPU2 DMAMUX1 clock enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: CRCEN
|
|
description: CPU2 CRC clock enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
fieldset/C2AHB1SMENR:
|
|
description: "CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]"
|
|
fields:
|
|
- name: DMA1SMEN
|
|
description: DMA1 clock enable during CPU2 CSleep mode.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: DMA2SMEN
|
|
description: DMA2 clock enable during CPU2 CSleep mode.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: DMAMUX1SMEN
|
|
description: DMAMUX1 clock enable during CPU2 CSleep mode.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: CRCSMEN
|
|
description: CRC clock enable during CPU2 CSleep mode.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
fieldset/C2AHB2ENR:
|
|
description: CPU2 AHB2 peripheral clock enable register
|
|
fields:
|
|
- name: GPIOAEN
|
|
description: CPU2 IO port A clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBEN
|
|
description: CPU2 IO port B clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCEN
|
|
description: CPU2 IO port C clock enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIOHEN
|
|
description: CPU2 IO port H clock enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
fieldset/C2AHB2SMENR:
|
|
description: "CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]"
|
|
fields:
|
|
- name: GPIOASMEN
|
|
description: IO port A clock enable during CPU2 CSleep mode.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBSMEN
|
|
description: IO port B clock enable during CPU2 CSleep mode.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCSMEN
|
|
description: IO port C clock enable during CPU2 CSleep mode.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIOHSMEN
|
|
description: IO port H clock enable during CPU2 CSleep mode.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
fieldset/C2AHB3ENR:
|
|
description: "CPU2 AHB3 peripheral clock enable register [dual core device only]"
|
|
fields:
|
|
- name: PKAEN
|
|
description: CPU2 PKA accelerator clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: AESEN
|
|
description: CPU2 AES accelerator clock enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: RNGEN
|
|
description: CPU2 True RNG clocks enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: HSEMEN
|
|
description: CPU2 HSEM clock enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: IPCCEN
|
|
description: CPU2 IPCC interface clock enable
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: FLASHEN
|
|
description: CPU2 Flash interface clock enable
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/C2AHB3SMENR:
|
|
description: "CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]"
|
|
fields:
|
|
- name: PKASMEN
|
|
description: PKA accelerator clock enable during CPU2 CSleep mode.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: AESSMEN
|
|
description: AES accelerator clock enable during CPU2 CSleep mode.
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: RNGSMEN
|
|
description: True RNG clock enable during CPU2 CSleep and CStop mode.
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SRAM1SMEN
|
|
description: SRAM1 interface clock enable during CPU2 CSleep mode.
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: SRAM2SMEN
|
|
description: SRAM2 memory interface clock enable during CPU2 CSleep mode.
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: FLASHSMEN
|
|
description: Flash interface clock enable during CPU2 CSleep mode.
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/C2APB1ENR1:
|
|
description: "CPU2 APB1 peripheral clock enable register 1 [dual core device only]"
|
|
fields:
|
|
- name: TIM2EN
|
|
description: CPU2 TIM2 timer clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: RTCAPBEN
|
|
description: CPU2 RTC APB clock enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SPI2EN
|
|
description: CPU2 SPI2 clock enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: USART2EN
|
|
description: CPU2 USART2 clock enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: I2C1EN
|
|
description: CPU2 I2C1 clocks enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C2EN
|
|
description: CPU2 I2C2 clocks enable
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: I2C3EN
|
|
description: CPU2 I2C3 clocks enable
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: DAC1EN
|
|
description: CPU2 DAC1 clock enable
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: LPTIM1EN
|
|
description: CPU2 Low power timer 1 clocks enable
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/C2APB1ENR2:
|
|
description: "CPU2 APB1 peripheral clock enable register 2 [dual core device only]"
|
|
fields:
|
|
- name: LPUART1EN
|
|
description: CPU2 Low power UART 1 clocks enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPTIM2EN
|
|
description: CPU2 Low power timer 2 clocks enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LPTIM3EN
|
|
description: CPU2 Low power timer 3 clocks enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
fieldset/C2APB1SMENR1:
|
|
description: "CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only]"
|
|
fields:
|
|
- name: TIM2SMEN
|
|
description: TIM2 timer clock enable during CPU2 CSleep mode.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: RTCAPBSMEN
|
|
description: RTC bus clock enable during CPU2 CSleep mode.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SPI2SMEN
|
|
description: SPI2 clock enable during CPU2 CSleep mode.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: USART2SMEN
|
|
description: USART2 clock enable during CPU2 CSleep mode.
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: I2C1SMEN
|
|
description: I2C1 clock enable during CPU2 CSleep and CStop modes
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C2SMEN
|
|
description: I2C2 clock enable during CPU2 CSleep and CStop modes
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: I2C3SMEN
|
|
description: I2C3 clock enable during CPU2 CSleep and CStop modes
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: DAC1SMEN
|
|
description: DAC1 clock enable during CPU2 CSleep mode.
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: LPTIM1SMEN
|
|
description: Low power timer 1 clock enable during CPU2 CSleep and CStop mode
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/C2APB1SMENR2:
|
|
description: "CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]"
|
|
fields:
|
|
- name: LPUART1SMEN
|
|
description: Low power UART 1 clock enable during CPU2 CSleep and CStop mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPTIM2SMEN
|
|
description: Low power timer 2 clocks enable during CPU2 CSleep and CStop modes.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LPTIM3SMEN
|
|
description: Low power timer 3 clocks enable during CPU2 CSleep and CStop modes.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
fieldset/C2APB2ENR:
|
|
description: "CPU2 APB2 peripheral clock enable register [dual core device only]"
|
|
fields:
|
|
- name: ADCEN
|
|
description: ADC clocks enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: TIM1EN
|
|
description: CPU2 TIM1 timer clock enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1EN
|
|
description: CPU2 SPI1 clock enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1EN
|
|
description: CPU2 USART1clocks enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16EN
|
|
description: CPU2 TIM16 timer clock enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17EN
|
|
description: CPU2 TIM17 timer clock enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
fieldset/C2APB2SMENR:
|
|
description: "CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only]"
|
|
fields:
|
|
- name: ADCSMEN
|
|
description: ADC clocks enable during CPU2 Csleep and CStop modes
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: TIM1SMEN
|
|
description: TIM1 timer clock enable during CPU2 CSleep mode
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1SMEN
|
|
description: SPI1 clock enable during CPU2 CSleep mode
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1SMEN
|
|
description: USART1clock enable during CPU2 CSleep and CStop mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16SMEN
|
|
description: TIM16 timer clock enable during CPU2 CSleep mode
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17SMEN
|
|
description: TIM17 timer clock enable during CPU2 CSleep mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
fieldset/C2APB3ENR:
|
|
description: "CPU2 APB3 peripheral clock enable register [dual core device only]"
|
|
fields:
|
|
- name: SUBGHZSPIEN
|
|
description: CPU2 sub-GHz radio SPI clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/C2APB3SMENR:
|
|
description: "CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only]"
|
|
fields:
|
|
- name: SUBGHZSPISMEN
|
|
description: sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/CCIPR:
|
|
description: Peripherals independent clock configuration register
|
|
fields:
|
|
- name: USART1SEL
|
|
description: USART1 clock source selection
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: USART2SEL
|
|
description: USART2 clock source selection
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
- name: SPI2SEL
|
|
description: SPI2 I2S clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
- name: LPUART1SEL
|
|
description: LPUART1 clock source selection
|
|
bit_offset: 10
|
|
bit_size: 2
|
|
- name: I2C1SEL
|
|
description: I2C1 clock source selection
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
- name: I2C2SEL
|
|
description: I2C2 clock source selection
|
|
bit_offset: 14
|
|
bit_size: 2
|
|
- name: I2C3SEL
|
|
description: I2C3 clock source selection
|
|
bit_offset: 16
|
|
bit_size: 2
|
|
- name: LPTIM1SEL
|
|
description: Low power timer 1 clock source selection
|
|
bit_offset: 18
|
|
bit_size: 2
|
|
- name: LPTIM2SEL
|
|
description: Low power timer 2 clock source selection
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
- name: LPTIM3SEL
|
|
description: Low power timer 3 clock source selection
|
|
bit_offset: 22
|
|
bit_size: 2
|
|
- name: ADCSEL
|
|
description: ADC clock source selection
|
|
bit_offset: 28
|
|
bit_size: 2
|
|
- name: RNGSEL
|
|
description: RNG clock source selection
|
|
bit_offset: 30
|
|
bit_size: 2
|
|
fieldset/CFGR:
|
|
description: Clock configuration register
|
|
fields:
|
|
- name: SW
|
|
description: System clock switch
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: SWS
|
|
description: System clock switch status
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
- name: HPRE
|
|
description: "HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)"
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
- name: PPRE1
|
|
description: PCLK1 low-speed prescaler (APB1)
|
|
bit_offset: 8
|
|
bit_size: 3
|
|
- name: PPRE2
|
|
description: PCLK2 high-speed prescaler (APB2)
|
|
bit_offset: 11
|
|
bit_size: 3
|
|
- name: STOPWUCK
|
|
description: Wakeup from Stop and CSS backup clock selection
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: HPREF
|
|
description: "HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1)"
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PPRE1F
|
|
description: PCLK1 prescaler flag (APB1)
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: PPRE2F
|
|
description: PCLK2 prescaler flag (APB2)
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: MCOSEL
|
|
description: Microcontroller clock output
|
|
bit_offset: 24
|
|
bit_size: 4
|
|
- name: MCOPRE
|
|
description: Microcontroller clock output prescaler
|
|
bit_offset: 28
|
|
bit_size: 3
|
|
fieldset/CICR:
|
|
description: Clock interrupt clear register
|
|
fields:
|
|
- name: LSIRDYC
|
|
description: LSI ready interrupt clear
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYC
|
|
description: LSE ready interrupt clear
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIRDYC
|
|
description: MSI ready interrupt clear
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYC
|
|
description: HSI16 ready interrupt clear
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYC
|
|
description: HSE32 ready interrupt clear
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYC
|
|
description: PLL ready interrupt clear
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CSSC
|
|
description: HSE32 Clock security system interrupt clear
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSECSSC
|
|
description: LSE Clock security system interrupt clear
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
fieldset/CIER:
|
|
description: Clock interrupt enable register
|
|
fields:
|
|
- name: LSIRDYIE
|
|
description: LSI ready interrupt enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYIE
|
|
description: LSE ready interrupt enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIRDYIE
|
|
description: MSI ready interrupt enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYIE
|
|
description: HSI16 ready interrupt enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYIE
|
|
description: HSE32 ready interrupt enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYIE
|
|
description: PLL ready interrupt enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LSECSSIE
|
|
description: LSE clock security system interrupt enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
fieldset/CIFR:
|
|
description: Clock interrupt flag register
|
|
fields:
|
|
- name: LSIRDYF
|
|
description: LSI ready interrupt flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYF
|
|
description: LSE ready interrupt flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIRDYF
|
|
description: MSI ready interrupt flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYF
|
|
description: HSI16 ready interrupt flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYF
|
|
description: HSE32 ready interrupt flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYF
|
|
description: PLL ready interrupt flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CSSF
|
|
description: HSE32 Clock security system interrupt flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSECSSF
|
|
description: LSE Clock security system interrupt flag
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: Clock control register
|
|
fields:
|
|
- name: MSION
|
|
description: MSI clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: MSIRDY
|
|
description: MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready)
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIPLLEN
|
|
description: MSI clock PLL enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: MSIRGSEL
|
|
description: MSI range control selection
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: MSIRANGE
|
|
description: MSI clock ranges
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
- name: HSION
|
|
description: HSI16 clock enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: HSIKERON
|
|
description: HSI16 always enable for peripheral kernel clocks.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSIRDY
|
|
description: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready)
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: HSIASFS
|
|
description: HSI16 automatic start from Stop
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: HSIKERDY
|
|
description: HSI16 kernel clock ready flag for peripherals requests.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: HSEON
|
|
description: HSE32 clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSERDY
|
|
description: HSE32 clock ready flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: CSSON
|
|
description: HSE32 Clock security system enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: HSEPRE
|
|
description: HSE32 sysclk prescaler
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: HSEBYPPWR
|
|
description: Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO.
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: PLLON
|
|
description: Main PLL enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLRDY
|
|
description: Main PLL clock ready flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/CSR:
|
|
description: Control/status register
|
|
fields:
|
|
- name: LSION
|
|
description: LSI oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSIRDY
|
|
description: LSI oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSIPRE
|
|
description: LSI frequency prescaler
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: MSISRANGE
|
|
description: MSI clock ranges
|
|
bit_offset: 8
|
|
bit_size: 4
|
|
- name: RFRSTF
|
|
description: Radio in reset status flag
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: RFRST
|
|
description: Radio reset
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: RMVF
|
|
description: Remove reset flag
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: RFILARSTF
|
|
description: Radio illegal access flag
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: OBLRSTF
|
|
description: Option byte loader reset flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PINRSTF
|
|
description: Pin reset flag
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: BORRSTF
|
|
description: BOR flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: SFTRSTF
|
|
description: Software reset flag
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: IWDGRSTF
|
|
description: Independent window watchdog reset flag
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: WWDGRSTF
|
|
description: Window watchdog reset flag
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPWRRSTF
|
|
description: Low-power reset flag
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/EXTCFGR:
|
|
description: Extended clock recovery register
|
|
fields:
|
|
- name: SHDHPRE
|
|
description: "HCLK3 shared prescaler (AHB3, Flash, and SRAM2)"
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: C2HPRE
|
|
description: "[dual core device only] HCLK2 prescaler (CPU2)"
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
- name: SHDHPREF
|
|
description: "HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)"
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: C2HPREF
|
|
description: CLK2 prescaler flag (CPU2)
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
fieldset/ICSCR:
|
|
description: Internal clock sources calibration register
|
|
fields:
|
|
- name: MSICAL
|
|
description: MSI clock calibration
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: MSITRIM
|
|
description: MSI clock trimming
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: HSICAL
|
|
description: HSI16 clock calibration
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
- name: HSITRIM
|
|
description: HSI16 clock trimming
|
|
bit_offset: 24
|
|
bit_size: 7
|
|
fieldset/PLLCFGR:
|
|
description: PLL configuration register
|
|
fields:
|
|
- name: PLLSRC
|
|
description: Main PLL entry clock source
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: PLLM
|
|
description: Division factor for the main PLL input clock
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
- name: PLLN
|
|
description: Main PLL multiplication factor for VCO
|
|
bit_offset: 8
|
|
bit_size: 7
|
|
- name: PLLPEN
|
|
description: Main PLL PLLPCLK output enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PLLP
|
|
description: Main PLL division factor for PLLPCLK.
|
|
bit_offset: 17
|
|
bit_size: 5
|
|
- name: PLLQEN
|
|
description: Main PLL PLLQCLK output enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLQ
|
|
description: Main PLL division factor for PLLQCLK
|
|
bit_offset: 25
|
|
bit_size: 3
|
|
- name: PLLREN
|
|
description: Main PLL PLLRCLK output enable
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: PLLR
|
|
description: Main PLL division factor for PLLRCLK
|
|
bit_offset: 29
|
|
bit_size: 3
|