Mariusz Ryndzionek
fbea23bd00
Added missing FLASH registers (generated automatically)
2021-09-23 07:09:11 +02:00
Mariusz Ryndzionek
c0938c9102
Add initial register mapping for STM32 F1 AFIO and FLASH
2021-09-22 18:22:36 +02:00
Dario Nieuwenhuis
1d62ba5e14
Merge pull request #84 from lulf/l1-regs
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L1 regs
2021-09-15 14:55:09 +02:00
Ulf Lilleengen
9f1bd7d0d0
Update chip yaml
2021-09-15 14:47:33 +02:00
Ulf Lilleengen
e2bf041808
Add register mapping for STM32 L1 SYSCFG and DBGMCU
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Add missing GPIO port mapping
2021-09-15 14:47:01 +02:00
Dario Nieuwenhuis
616a2779d0
Merge pull request #82 from bgamari/stm32g0
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Fix ADC register layout on STM32G0
2021-08-31 22:21:51 +02:00
Dario Nieuwenhuis
96c902c66c
Merge pull request #83 from lulf/stm32wl55-pwr
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Stm32wl55 pwr
2021-08-31 22:18:57 +02:00
Ulf Lilleengen
201510407c
Handle SUBGHZSPI peripheral so it is recognized as an SPI peripheral
2021-08-31 14:43:02 +02:00
Ulf Lilleengen
902b9a6986
Add PWR peripheral for STM32WL5
2021-08-31 14:34:54 +02:00
Ben Gamari
3a88360dc6
Add PWR registers for STM32G0
2021-08-31 01:46:26 -04:00
Ben Gamari
5366833cbd
Introduce ADC register set for STM32G0
2021-08-31 01:46:02 -04:00
Dario Nieuwenhuis
deb37365d7
exti: g0 and l5 are 8 bits per line...
2021-08-20 01:26:33 +02:00
Dario Nieuwenhuis
8534ae884d
rcc: make GPIO EN/RST regs naming consistent.
2021-08-19 23:50:42 +02:00
Dario Nieuwenhuis
3b6363dffb
wl rcc: rename SPI2S2 -> SPI2
2021-08-19 22:37:07 +02:00
Dario Nieuwenhuis
49e579e97f
Add F2 RCC
2021-08-19 22:12:39 +02:00
Dario Nieuwenhuis
e289dd883f
Cleanup EXTI
2021-08-19 21:54:22 +02:00
Dario Nieuwenhuis
701ab04c2a
Cleanup SYSCFG naming
2021-08-19 21:28:32 +02:00
Dario Nieuwenhuis
31997049ea
Fix wrong register offsets in WB SYSCFG
2021-08-19 19:20:13 +02:00
Dario Nieuwenhuis
6af9f2c0d1
Add RCC for F3, F7, G4, H7AB, L1, L5, WB*, WL5, WLE
2021-08-19 19:13:30 +02:00
Dario Nieuwenhuis
bd402a58f2
Merge pull request #72 from bgamari/stm32g0
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STM32G0 support
2021-08-19 16:05:29 +02:00
Ben Gamari
254c59c064
Introduce STM32G0 ADC support
2021-08-19 15:57:17 +02:00
Ben Gamari
f57a268b9f
Add STM32G0 support
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Includes manually specified register layouts for EXTI and SYSCFG.
2021-08-19 15:57:00 +02:00
Ben Gamari
075d283354
parse: Drop duplicate pin definitions
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The STM32G0 SVDs contain duplicate pin declarations.
2021-08-19 15:55:13 +02:00
Ben Gamari
9c753da57b
Add a bit of documentation for register extraction process
2021-08-19 15:54:36 +02:00
Ben Gamari
f5808de749
Add RCC support for STM32G0
2021-08-19 15:54:36 +02:00
Ben Gamari
e735ea9769
Fix hash-bangs
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/usr/bin/bash isn't portable.
2021-08-19 15:54:36 +02:00
Dario Nieuwenhuis
8bb9c26d38
Update README.md
2021-08-18 22:17:16 +02:00
Dario Nieuwenhuis
f0e85a7e0d
Merge pull request #81 from embassy-rs/add-wl55-radio-spi
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Add wl55 radio spi
2021-08-18 15:21:45 +02:00
Ulf Lilleengen
63d1af4eca
Rerun parse.py
2021-08-18 14:16:49 +02:00
Ulf Lilleengen
d9708f6bfc
Use correct peripheral name for SUBGHZ SPI
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* Add SPI2s1_v3_5 register block for SUBGHZSPI peripheral
2021-08-18 14:00:14 +02:00
Ulf Lilleengen
04ae6ce25e
Add SPI2s1_v3_5
2021-08-18 13:59:51 +02:00
Dario Nieuwenhuis
80af84607a
Merge pull request #80 from lulf/stm32wl55-regs
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Stm32wl55 exti regs
2021-08-17 15:51:18 +02:00
Ulf Lilleengen
919a61e847
Add STM32WL5x exti block
2021-08-17 13:02:49 +02:00
Dario Nieuwenhuis
32b5c5c890
Merge pull request #79 from bobmcwhirter/h7_exti
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H7 exti
2021-08-16 21:30:12 +02:00
Bob McWhirter
541091cded
Include the reg block.
2021-08-16 15:12:17 -04:00
Bob McWhirter
2c7422ab76
Special-case the H7 EXTI reg layout.
2021-08-16 14:59:16 -04:00
Ulf Lilleengen
4c801c1234
Merge pull request #78 from lulf/parse-bugfix
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Parse bugfix and expose shared usart irqs
2021-08-16 16:48:39 +02:00
Ulf Lilleengen
154d226f7a
Handle shared USART IRQs
2021-08-16 13:02:25 +02:00
Ulf Lilleengen
a84e7d8b8c
Add ability to override peripheral address if bug in header sources
2021-08-16 13:01:25 +02:00
Ulf Lilleengen
7489588564
Give different names to secure and non-secure cores
2021-08-16 12:38:33 +02:00
Dario Nieuwenhuis
a7bebbd2ef
Merge pull request #77 from timokroeger/can-interrupts
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CAN interrupts
2021-08-15 13:20:09 +02:00
Timo Kröger
c5a86b0744
CAN interrupts
2021-08-15 11:13:26 +02:00
Dario Nieuwenhuis
8c392a059b
Merge pull request #74 from timokroeger/bxcan
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bxCAN Peripheral
2021-08-15 00:10:26 +02:00
Dario Nieuwenhuis
946eb0bb59
Merge pull request #76 from FrozenDroid/main
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add UART:sci2_v2_1 to parser
2021-08-13 16:35:11 +02:00
Vincent Stakenburg
67c16f80cf
add UART:sci2_v2_1 to parser
2021-08-13 16:02:12 +02:00
Timo Kröger
198e4f3247
Add bxcan registers
2021-08-06 11:52:47 +02:00
Dario Nieuwenhuis
e7998ed4c2
Merge pull request #73 from timokroeger/fix-rcc
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Fix RCC enable bits
2021-08-03 22:05:43 +02:00
Timo Kröger
7506b50031
rcc_l4: Remove duplicate bits
2021-08-03 16:33:59 +02:00
Timo Kröger
f865878b4b
rcc_f4: Fix RCC bits
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## LPTIM1EN / LPTIMER1EN
Only stm32f413 has LPTIM1 peripheral, ref manual bit names:
LPTIMER1EN, LPTIMER1RST, LPTIMER1LPEN, LPTIMER1SEL
action: Rename to LPTIM1(EN|RST|...) for consistency (matches peripheral name)
## FMC / FSMC
not available as peripheral in the YAML anyway.. TODO: why?
EN and RST
FSMC: f405, f407, f412, f413
FSC: f427, f429, f446, f469
action: none
## CECEN / CAN3EN
mutually exclusive peripherals, alias ok?
CECEN: f446
CAN3EN: f413
action: split off f4x3 yaml, f423 exists, but not available as svd
## USART / UART
all over the place, register names in ref manual not always consistent
stm32 follows a simple rule for the actual peripherals:
USART 1-3, 6
UART 4, 5, 7-10
action: rename enable/rst bits to rules above
2021-08-03 14:55:36 +02:00
Timo Kröger
babbe782f3
rcc_l0: Remove non existing RCC bits
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## firewall
l0x0, l0x1: FWEN - Firewall clock enable bit
l0x2, l0x3: MIFIEN - MiFaRe Firewall clock enable bit
action: none
## watchdog
peripheral: WWDG
WWDGRST vs WWDRST
action: remove
## CRS vs CRC
l0x2, l0x3: CRC reset is wrong
action: remove duplicate CRC bit
## LPUART12RST vs USART2RST
action: rename, it sholud be USART2
2021-08-03 14:31:36 +02:00
