xoviat
|
8bd7ff51b0
|
rcc: expand checker to all chips
|
2023-10-18 21:01:57 -05:00 |
|
Dario Nieuwenhuis
|
5b04234fbe
|
rcc: cleanup f4, f7 plls.
|
2023-10-18 05:08:14 +02:00 |
|
xoviat
|
3d9c8b70e3
|
rcc: check l4plus and l5
|
2023-10-17 17:21:06 -05:00 |
|
xoviat
|
c61495fd4e
|
rcc: more cleanup
|
2023-10-17 16:57:33 -05:00 |
|
xoviat
|
fb84c0ac55
|
rcc: fixup clock names and expand checking
|
2023-10-16 17:53:26 -05:00 |
|
JackN
|
120168456f
|
TSC: Add transform and new peripheral
|
2023-10-16 09:54:09 -04:00 |
|
Dario Nieuwenhuis
|
5ecc410f93
|
rcc/l5: cleanup
|
2023-10-16 03:56:19 +02:00 |
|
Dario Nieuwenhuis
|
73e3f8a965
|
rcc: separate L4 and L4+
|
2023-10-16 03:11:00 +02:00 |
|
Dario Nieuwenhuis
|
f437c33b41
|
rcc/l5: unify clk48sel vs clk48msel
|
2023-10-16 01:37:21 +02:00 |
|
xoviat
|
b9a89a1851
|
rcc: cleanup variants and rename ahb -> clk
|
2023-10-15 18:01:50 -05:00 |
|
xoviat
|
8b8686a852
|
rcc: more mux and enum cleanup
|
2023-10-15 10:37:36 -05:00 |
|
xoviat
|
5d51e3b706
|
rcc: add more mux data
|
2023-10-14 17:20:25 -05:00 |
|
xoviat
|
68d77f487b
|
rcc: add more mux data
|
2023-10-14 11:41:21 -05:00 |
|
xoviat
|
b14427f2d1
|
Merge branch 'main' of https://github.com/embassy-rs/stm32-data into rcc
|
2023-10-13 22:22:05 -05:00 |
|
xoviat
|
8a09bbb62c
|
rcc: more cleanup
|
2023-10-13 22:20:18 -05:00 |
|
xoviat
|
e90a83a4f0
|
Merge pull request #281 from noppej/gfxmmu
Add GFXMMU peripheral
|
2023-10-14 02:26:15 +00:00 |
|
xoviat
|
aa5e909e11
|
rcc: more enum cleanup
|
2023-10-13 20:54:24 -05:00 |
|
JackN
|
53c636386b
|
GFXMMU: New peripheral yamls
|
2023-10-13 17:12:57 -04:00 |
|
xoviat
|
c4cd46927d
|
rcc: rename h5 clock enum variants and add check
|
2023-10-12 20:48:35 -05:00 |
|
JackN
|
019e802e27
|
OCTOSPI: Fix "MAXTRAN was in wrong yaml".
|
2023-10-12 18:52:50 -04:00 |
|
JackN
|
af1a5f5877
|
OCTOSPI: Merge peri yamls
|
2023-10-12 17:44:41 -04:00 |
|
JackN
|
4e2bf3eb20
|
PR Review corrections
|
2023-10-12 16:45:54 -04:00 |
|
JackN
|
e99c97f0f6
|
OCTOSPI: Merge peripheral yamls and consolidate enums
|
2023-10-12 15:43:04 -04:00 |
|
JackN
|
b07f5a1ba2
|
Reformat yaml's with chiptool fmt
|
2023-10-12 10:49:41 -04:00 |
|
JackN
|
c34f46566e
|
Add STM32u5xx to header_map.yaml
|
2023-10-12 10:24:00 -04:00 |
|
JackN
|
e933ee6cc4
|
New peripherals: octospim_v1+v2, and octospi_v1-v4
|
2023-10-12 10:23:59 -04:00 |
|
Dario Nieuwenhuis
|
6bfa5a0dce
|
rtc/bd fixes.
|
2023-10-11 03:41:10 +02:00 |
|
Dario Nieuwenhuis
|
9f45b0c48c
|
Rename HSI to HSI16 in L1.
|
2023-10-11 01:21:46 +02:00 |
|
Dario Nieuwenhuis
|
f40f5a40c1
|
Not all L0s have HSI48/CRS.
|
2023-10-11 01:21:26 +02:00 |
|
Dario Nieuwenhuis
|
71f81b44e3
|
Rename HSE32 -> HSE.
|
2023-10-11 00:29:01 +02:00 |
|
Dario Nieuwenhuis
|
ff45aa382e
|
rcc: add more missing enums.
|
2023-10-11 00:07:28 +02:00 |
|
Dario Nieuwenhuis
|
e89b8cfc30
|
rcc: add PLL enums.
|
2023-10-09 02:44:42 +02:00 |
|
Dario Nieuwenhuis
|
6c73ffbd0b
|
rcc: make naming consistent between "mco" and "mcosel".
|
2023-10-07 00:46:19 +02:00 |
|
Dario Nieuwenhuis
|
8d112b7a93
|
rcc: add MCO enums for WB
|
2023-10-07 00:20:42 +02:00 |
|
Dario Nieuwenhuis
|
e701705d79
|
rcc: add MCOPRE enum for h5, h7.
|
2023-10-07 00:10:08 +02:00 |
|
Dario Nieuwenhuis
|
11256dc370
|
chiptool fmt.
|
2023-10-07 00:09:14 +02:00 |
|
Matt Ickstadt
|
2ceed56e94
|
RCC: add LSEDRV enums for WB and WL series
These are in the RMs but previously missing.
|
2023-10-05 11:18:49 -05:00 |
|
Matt Ickstadt
|
60d034f9fa
|
RCC: unify LSEDRV enum variant names and descriptions
Now the only differences are the series which have swapped medium low/high bits: F0, F3v2, F3, F7, and H7_RM0433.
|
2023-10-05 10:56:02 -05:00 |
|
Matt Ickstadt
|
32b3bd75ea
|
H7: Fix LSEDRV bits of RM0433
Errata ES0392 2.2.14
|
2023-10-05 10:37:07 -05:00 |
|
Matt Ickstadt
|
568a7058a1
|
Create rcc_h7rm04ee.yaml as a copy of rcc_h7.yaml
|
2023-10-05 10:35:43 -05:00 |
|
xoviat
|
feec3c1617
|
opamp: add other pins for f3 and g4
|
2023-10-03 20:38:38 -05:00 |
|
xoviat
|
06d13dfd24
|
Merge pull request #267 from oll3/tamp_block
add TAMP register block for g0, g4, l5, u5 and wl
|
2023-10-02 21:00:10 +00:00 |
|
Olle Sandberg
|
00894c8e3d
|
clean up TAMP registers
Remove obvious 1 bit enums and make arrays of repeated fields.
|
2023-10-02 07:15:40 +02:00 |
|
xoviat
|
4a893c37da
|
add man impl. pin signals
|
2023-10-01 13:28:31 -05:00 |
|
xoviat
|
e36d73af66
|
Merge branch 'main' of https://github.com/embassy-rs/stm32-data into sbs
|
2023-09-28 18:52:19 -05:00 |
|
xoviat
|
97a4fb22b2
|
rename sbs to syscfg
|
2023-09-28 18:50:30 -05:00 |
|
xoviat
|
0041cf976c
|
opamp: add f3 and g4
|
2023-09-28 18:32:30 -05:00 |
|
xoviat
|
1b39301d8c
|
Merge branch 'master' into lptim-basic
|
2023-09-27 21:09:34 -05:00 |
|
Olle Sandberg
|
e7de675353
|
add TAMP register block for g0, g4, l5, u5 and wl
|
2023-09-27 07:35:27 +02:00 |
|
shakencodes
|
0adf2a75d1
|
Add enums MCOPRE & MCOSEL to wl5 & wle targets
|
2023-09-26 10:55:19 -07:00 |
|