chemicstry
40e1ece0d1
Fix DAC registers for F1
2022-08-04 02:07:32 +03:00
chemicstry
e11fcf4454
Add iwdg v1 definitions
2022-07-10 18:40:52 +03:00
Dario Nieuwenhuis
5b8c040fe9
ban STM32L485 "ghost" chips.
2022-06-27 02:07:28 +02:00
Sean Bolton
f4de61a1e0
Fix TIM timer types across all lines
2022-06-21 08:34:21 -07:00
Sean Bolton
6f528063d2
Clean up regex string literals
2022-06-21 08:13:21 -07:00
Dario Nieuwenhuis
147d5a0787
usb: add ep mem, fix versions.
2022-06-07 00:27:54 +02:00
Dario Nieuwenhuis
d21bbe0ad8
Sort interrupts.
2022-06-06 22:34:32 +02:00
chemicstry
02763581ab
Fix RTC peripheral version names
2022-06-05 22:53:08 +02:00
chemicstry
6811a09679
Fix names
2022-06-05 22:52:52 +02:00
chemicstry
85162f723f
Manually cleanup all RTC registers
2022-06-05 22:52:52 +02:00
chemicstry
82c3d2a485
Group rtc regs by version
2022-06-05 22:52:51 +02:00
chemicstry
5ec0ad4387
Add RTC registers for all chips
2022-06-05 22:52:14 +02:00
Dario Nieuwenhuis
1910d1886a
Merge pull request #148 from chemicstry/f1_bkp
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Add F1 BKP peripheral
2022-06-05 22:43:25 +02:00
Dario Nieuwenhuis
8cd6b1e17b
Merge pull request #145 from jensenn/lcd-peripheral
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Add LCD peripheral
2022-06-03 18:37:37 +02:00
chemicstry
137611f0f6
Merge branch 'main' into f1_bkp
2022-06-03 10:20:14 +03:00
chemicstry
582969eb56
Add F1 BKP peripheral
2022-06-03 10:18:22 +03:00
Jensenn
846847b9d5
Split LCD peripheral into v1, v2
2022-05-10 13:53:11 -06:00
Grant Miller
d7674ab524
Create rcc_f100.yaml
2022-05-01 19:27:28 -05:00
Grant Miller
9ea9bd5215
Prevent crash if xENR exists but xRSTR doesn't
2022-05-01 19:20:48 -05:00
Ulf Lilleengen
bd97be07b3
Generate more flash settings
2022-04-27 13:25:48 +02:00
Matous Hybl
0c9329fe94
Add ADC3 common for H7s
2022-04-27 00:51:20 +02:00
Matous Hybl
a87cf34197
Add ADC registers for F1 and H7
2022-04-27 00:50:46 +02:00
Dario Nieuwenhuis
eff26e3e77
Add stm32u5 GPDMA, SPI
2022-04-26 23:53:28 +02:00
Joonas Javanainen
ad291b5af3
Map spi2s1_v2_1 used on F2 devices
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This seems identical to v2_2 (as used by F429) with one naming exception
in status register SR bit 8 (TI frame format error):
v2_1 data names the bit "TIFRFE" and the enum TIFRERR
v2_2 data names the bit "FRE" and the enum FRER
The register bit layout is identical.
2022-04-26 20:24:36 +03:00
Dario Nieuwenhuis
2db5d47cc6
Merge pull request #140 from davidlenfesty/eth-v1a
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Generate support for ethernet v1a and v1b
2022-04-26 18:28:41 +02:00
Ulf Lilleengen
afcd7a7d69
Rename flash_w[bl]55 flash_w[bl]
2022-04-26 18:17:09 +02:00
David Lenfesty
121e5bc92b
Generate ethernet peripherals for f2 and f4
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These are eth v1b, according to stm32-rs it should have the same register
changes as v1c, so I just copied it over.
2022-04-26 10:09:28 -06:00
David Lenfesty
05bf8c23c1
fix RCC MCO register for f1 CL variants
2022-04-26 10:04:50 -06:00
Ulf Lilleengen
004542bf86
Add l0 flash support
2022-04-26 14:51:37 +02:00
Ulf Lilleengen
3dd39de946
Add flash for stm32wl
2022-04-26 14:51:37 +02:00
Jensenn
b7d299d2a8
Update perimap for LCD peripheral
2022-04-25 13:20:57 -06:00
David Lenfesty
a0368410a5
Add STM32F107 ethernet v1a peripheral
2022-04-21 17:05:23 -06:00
Dario Nieuwenhuis
c01cb449e9
Add L5 PWR
2022-04-10 01:46:46 +02:00
Philip A Reimer
e81eeb157e
add pwr_l4
2022-04-09 11:05:50 -06:00
Dario Nieuwenhuis
6107d5a72e
Add USB
2022-04-09 00:28:44 +02:00
Dario Nieuwenhuis
b5d84de6e6
L5: add FLASH, SYSCFG
2022-04-08 02:54:56 +02:00
Philip A Reimer
62ebc483f9
use otg v1 for v3
2022-03-28 22:37:11 -06:00
Philip A Reimer
55163d5857
Add OTG FS v3
2022-03-24 21:16:11 -06:00
Nicolas Viennot
4ed9a42360
Add OTG register definitions
2022-03-20 19:07:24 -04:00
Dario Nieuwenhuis
b5ffa60b5f
Merge pull request #133 from nviennot/fsmc
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FSMC register block
2022-03-20 21:01:20 +01:00
Dario Nieuwenhuis
6ee54e8bf1
Merge pull request #131 from chemicstry/f4_uart
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Fix F4 UART definitions
2022-03-20 21:00:04 +01:00
Dario Nieuwenhuis
d5b53707d0
Merge pull request #132 from Gekkio/improve-f2-support
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F2: Add SYSCFG/FLASH/PWR, fix DBGMCU SVD typos
2022-03-20 20:59:33 +01:00
Dario Nieuwenhuis
ca8f4b3e0d
Merge pull request #130 from chemicstry/sdio_fix2
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Unify SDMMC v1 and v2 register names
2022-03-20 20:52:20 +01:00
Dario Nieuwenhuis
5c2ec818f6
Merge pull request #129 from nviennot/timer_clock
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Timers use the clock speed apb1_tim and apb2_tim
2022-03-20 20:51:45 +01:00
Nicolas Viennot
f9301d42f0
Add the FSMC register block
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The current v1 yaml has a few extra registers defined that don't belong to
some of the chips out there (the ones at byte_offset 320 and above), but
the rest of registers are identical.
2022-03-18 23:41:56 -04:00
Joonas Javanainen
f622be8f03
Add PWR block for F2
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Verified using RM0033 (F205xx/F207xx/F215xx/F217xx) Rev 9
2022-03-17 21:44:23 +02:00
Joonas Javanainen
e36b972e3c
Add FLASH block for F2
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Verified using PM0059 Programming manual (F205/215, F207/217) Rev 5
2022-03-17 21:32:59 +02:00
Joonas Javanainen
b47951b4a2
Add SYSCFG block for F2
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Verified using RM0033 (F205xx/F207xx/F215xx/F217xx) Rev 9
2022-03-17 21:32:37 +02:00
chemicstry
0f80d10a1f
Fix F4 UART parsing
2022-03-17 16:33:34 +02:00
chemicstry
caa613eab2
Unify SDMMC register names
2022-03-16 18:40:36 +02:00
