Ben Gamari
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2f42ebcd2c
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Add support for LPTIM peripherals
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2021-10-26 17:55:48 +02:00 |
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Matous Hybl
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2e1302c4e8
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Support for STM32F767ZI and basic support for the rest of the family.
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2021-10-25 10:38:28 +02:00 |
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Tobias Pisani
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b8de47fa04
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feat: Add F1 SPI registers
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2021-10-06 20:51:27 +02:00 |
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Mariusz Ryndzionek
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9e6eff587c
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Correct AFIO support (code review request)
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2021-09-27 15:35:29 +02:00 |
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Joshua Salzedo
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fb4d8b7033
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Add CRC rules to parse.py
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2021-09-26 15:09:45 -07:00 |
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Vincent Stakenburg
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f699571831
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add l4 flash parse line
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2021-09-24 16:45:17 +02:00 |
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Dario Nieuwenhuis
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5dec590202
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Merge pull request #85 from mryndzionek/stm32f1_support
Add initial register mapping for STM32 F1 AFIO and FLASH
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2021-09-23 17:36:38 +02:00 |
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Ulf Lilleengen
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a302947e87
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Add PWR register block and fix RCC register block
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2021-09-23 14:40:59 +02:00 |
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Mariusz Ryndzionek
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c0938c9102
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Add initial register mapping for STM32 F1 AFIO and FLASH
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2021-09-22 18:22:36 +02:00 |
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Ulf Lilleengen
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e2bf041808
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Add register mapping for STM32 L1 SYSCFG and DBGMCU
Add missing GPIO port mapping
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2021-09-15 14:47:01 +02:00 |
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Dario Nieuwenhuis
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616a2779d0
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Merge pull request #82 from bgamari/stm32g0
Fix ADC register layout on STM32G0
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2021-08-31 22:21:51 +02:00 |
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Ulf Lilleengen
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201510407c
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Handle SUBGHZSPI peripheral so it is recognized as an SPI peripheral
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2021-08-31 14:43:02 +02:00 |
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Ulf Lilleengen
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902b9a6986
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Add PWR peripheral for STM32WL5
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2021-08-31 14:34:54 +02:00 |
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Ben Gamari
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3a88360dc6
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Add PWR registers for STM32G0
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2021-08-31 01:46:26 -04:00 |
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Ben Gamari
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5366833cbd
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Introduce ADC register set for STM32G0
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2021-08-31 01:46:02 -04:00 |
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Dario Nieuwenhuis
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49e579e97f
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Add F2 RCC
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2021-08-19 22:12:39 +02:00 |
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Dario Nieuwenhuis
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e289dd883f
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Cleanup EXTI
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2021-08-19 21:54:22 +02:00 |
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Dario Nieuwenhuis
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701ab04c2a
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Cleanup SYSCFG naming
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2021-08-19 21:28:32 +02:00 |
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Dario Nieuwenhuis
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6af9f2c0d1
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Add RCC for F3, F7, G4, H7AB, L1, L5, WB*, WL5, WLE
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2021-08-19 19:13:30 +02:00 |
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Ben Gamari
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254c59c064
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Introduce STM32G0 ADC support
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2021-08-19 15:57:17 +02:00 |
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Ben Gamari
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f57a268b9f
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Add STM32G0 support
Includes manually specified register layouts for EXTI and SYSCFG.
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2021-08-19 15:57:00 +02:00 |
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Ben Gamari
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075d283354
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parse: Drop duplicate pin definitions
The STM32G0 SVDs contain duplicate pin declarations.
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2021-08-19 15:55:13 +02:00 |
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Ben Gamari
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f5808de749
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Add RCC support for STM32G0
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2021-08-19 15:54:36 +02:00 |
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Ulf Lilleengen
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d9708f6bfc
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Use correct peripheral name for SUBGHZ SPI
* Add SPI2s1_v3_5 register block for SUBGHZSPI peripheral
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2021-08-18 14:00:14 +02:00 |
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Ulf Lilleengen
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04ae6ce25e
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Add SPI2s1_v3_5
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2021-08-18 13:59:51 +02:00 |
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Ulf Lilleengen
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919a61e847
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Add STM32WL5x exti block
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2021-08-17 13:02:49 +02:00 |
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Bob McWhirter
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2c7422ab76
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Special-case the H7 EXTI reg layout.
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2021-08-16 14:59:16 -04:00 |
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Ulf Lilleengen
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4c801c1234
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Merge pull request #78 from lulf/parse-bugfix
Parse bugfix and expose shared usart irqs
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2021-08-16 16:48:39 +02:00 |
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Ulf Lilleengen
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154d226f7a
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Handle shared USART IRQs
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2021-08-16 13:02:25 +02:00 |
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Ulf Lilleengen
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a84e7d8b8c
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Add ability to override peripheral address if bug in header sources
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2021-08-16 13:01:25 +02:00 |
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Ulf Lilleengen
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7489588564
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Give different names to secure and non-secure cores
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2021-08-16 12:38:33 +02:00 |
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Timo Kröger
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c5a86b0744
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CAN interrupts
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2021-08-15 11:13:26 +02:00 |
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Dario Nieuwenhuis
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8c392a059b
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Merge pull request #74 from timokroeger/bxcan
bxCAN Peripheral
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2021-08-15 00:10:26 +02:00 |
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Vincent Stakenburg
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67c16f80cf
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add UART:sci2_v2_1 to parser
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2021-08-13 16:02:12 +02:00 |
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Timo Kröger
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198e4f3247
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Add bxcan registers
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2021-08-06 11:52:47 +02:00 |
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Bob McWhirter
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4a67203c86
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Keep device-id as hex.
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2021-08-02 11:06:26 -04:00 |
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Bob McWhirter
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93490bc42f
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Ensure that any bank is not larger than the total from the SVD.
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2021-08-02 11:06:26 -04:00 |
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Bob McWhirter
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99cd26c33f
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Parse memory layouts for actual region sizes.
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2021-08-02 11:06:25 -04:00 |
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Bob McWhirter
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2e7af6b842
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Parse our memory location bases and name them well-ish.
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2021-08-02 11:06:24 -04:00 |
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Bob McWhirter
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2d38aad861
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Include base addresses for flash and ram.
Remove 'null' entries for datasheets/reference-manuals.
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2021-08-02 11:06:23 -04:00 |
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Timo Kröger
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c02e3dc9ab
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Split f410 and f4 RCC yamls
f410 has the RNGEN at a different position
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2021-07-31 17:40:30 +02:00 |
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Thales Fragoso
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02b44906c9
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Add F4 PWR
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2021-07-28 19:14:39 -03:00 |
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Bob McWhirter
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e4e17c36d0
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Handle NVICs in multi-core chips.
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2021-07-28 09:07:30 -04:00 |
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Dario Nieuwenhuis
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0bbd7c2d31
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Merge pull request #67 from embassy-rs/f4-flash
Add F4 FLASH
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2021-07-28 11:45:51 +02:00 |
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Thales Fragoso
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d53b964978
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Add F4 FLASH
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2021-07-27 21:53:08 -03:00 |
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Grant Miller
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369401ca07
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Add F1 RCC
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2021-07-27 12:11:25 -05:00 |
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Bob McWhirter
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3f583ec196
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Scrape our (B)DMA interrupts per peripheral also.
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2021-07-26 14:10:25 -04:00 |
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Bob McWhirter
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2618ec3a94
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Be fancier on parsing peripheral IRQs.
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2021-07-26 13:33:36 -04:00 |
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Bob McWhirter
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38c403f205
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Fixes #9
Adds per-peripheral interrupts.
Simple list, functionality not otherwise described.
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2021-07-23 14:48:45 -04:00 |
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Dario Nieuwenhuis
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60b4b7d155
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Add dmamux yamls, use them instead of xml/c parsing.
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2021-07-17 07:23:48 +02:00 |
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