chiptool fmt.
This commit is contained in:
Dario Nieuwenhuis
parent
9b5d631059
commit
86fb0cfc2f
@ -1,4 +1,3 @@
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---
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block/ADC:
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description: Analog-to-digital converter
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items:
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@ -1,4 +1,3 @@
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---
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block/ADC:
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description: Analog-to-Digital Converter
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items:
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@ -65,26 +64,26 @@ block/ADC:
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fieldset: JSQR
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- name: OFR
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description: offset register X
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byte_offset: 96
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fieldset: OFR
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array:
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len: 4
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stride: 4
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byte_offset: 96
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fieldset: OFR
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- name: JDR
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description: injected data register X
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array:
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len: 4
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stride: 4
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byte_offset: 128
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access: Read
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fieldset: JDR
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array:
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len: 4
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stride: 4
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- name: AWDCR
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description: "Analog Watchdog X Configuration\r Register"
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byte_offset: 160
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fieldset: AWDCR
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array:
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len: 2
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stride: 4
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byte_offset: 160
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fieldset: AWDCR
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- name: DIFSEL
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description: "Differential Mode Selection Register\r 2"
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byte_offset: 176
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@ -472,10 +471,10 @@ fieldset/SMPR1:
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description: Channel x sampling time selection
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bit_offset: 3
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bit_size: 3
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enum: SAMPLE_TIME
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array:
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len: 9
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stride: 3
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enum: SAMPLE_TIME
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fieldset/SMPR2:
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description: sample time register 2
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fields:
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@ -483,10 +482,10 @@ fieldset/SMPR2:
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description: Channel x sampling time selection
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bit_offset: 0
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bit_size: 3
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enum: SAMPLE_TIME
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array:
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len: 9
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stride: 3
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enum: SAMPLE_TIME
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fieldset/SQR1:
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description: regular sequence register 1
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fields:
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@ -727,10 +726,10 @@ enum/JQM:
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bit_size: 1
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variants:
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- name: Mode0
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description: "JSQR Mode 0: Queue maintains the last written configuration into JSQR"
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description: 'JSQR Mode 0: Queue maintains the last written configuration into JSQR'
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value: 0
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- name: Mode1
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description: "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence"
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description: 'JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence'
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value: 1
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enum/RES:
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bit_size: 2
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@ -1,4 +1,3 @@
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---
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block/ADC:
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description: Analog-to-Digital Converter
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items:
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@ -65,55 +64,28 @@ block/ADC:
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- name: JDR1
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description: injected data register 1
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byte_offset: 60
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fieldset: JDR1
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access: Read
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fieldset: JDR1
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- name: JDR2
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description: injected data register 2
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byte_offset: 64
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fieldset: JDR2
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access: Read
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fieldset: JDR2
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- name: JDR3
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description: injected data register 3
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byte_offset: 68
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fieldset: JDR3
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access: Read
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fieldset: JDR3
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- name: JDR4
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description: injected data register 4
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byte_offset: 72
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fieldset: JDR4
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access: Read
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fieldset: JDR4
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- name: DR
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description: regular data register
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byte_offset: 76
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fieldset: DR
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access: Read
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fieldset/SR:
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description: status register
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fields:
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- name: AWD
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description: analog watchdog flag
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bit_offset: 0
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bit_size: 1
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- name: EOC
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description: end of conversion
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bit_offset: 1
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bit_size: 1
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- name: JEOC
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description: injected channel end of conversion
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bit_offset: 2
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bit_size: 1
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- name: JSTRT
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description: injected channel start flag
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bit_offset: 3
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bit_size: 1
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- name: STRT
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description: regular channel start flag
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bit_offset: 4
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bit_size: 1
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- name: OVR
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description: overrun
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bit_offset: 5
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bit_size: 1
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fieldset: DR
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fieldset/CR1:
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description: control register 1
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fields:
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@ -223,6 +195,106 @@ fieldset/CR2:
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description: temperature sensor and VREFINT enable
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bit_offset: 23
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bit_size: 1
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fieldset/DR:
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description: regular data register
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fields:
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- name: DATA
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description: Regular data
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bit_offset: 0
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bit_size: 16
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fieldset/HTR:
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description: watchdog higher threshold register
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fields:
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- name: HT
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description: Analog watchdog high threshold
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bit_offset: 0
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bit_size: 12
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fieldset/JDR1:
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description: injected data register 1
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fields:
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- name: JDATA1
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description: Injected data
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bit_offset: 0
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bit_size: 16
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fieldset/JDR2:
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description: injected data register 2
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fields:
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- name: JDATA2
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description: Injected data
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bit_offset: 0
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bit_size: 16
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fieldset/JDR3:
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description: injected data register 3
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fields:
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- name: JDATA3
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description: Injected data
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bit_offset: 0
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bit_size: 16
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fieldset/JDR4:
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description: injected data register 4
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fields:
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- name: JDATA4
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description: Injected data
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bit_offset: 0
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bit_size: 16
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fieldset/JOFR1:
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description: injected channel data offset register 1
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fields:
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- name: JOFFSET1
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description: data offset for injected channel 1
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bit_offset: 0
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bit_size: 12
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fieldset/JOFR2:
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description: injected channel data offset register 2
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fields:
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- name: JOFFSET2
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description: data offset for injected channel 2
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bit_offset: 0
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bit_size: 12
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fieldset/JOFR3:
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description: injected channel data offset register 3
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fields:
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- name: JOFFSET3
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description: data offset for injected channel 3
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bit_offset: 0
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bit_size: 12
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fieldset/JOFR4:
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description: injected channel data offset register 4
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fields:
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- name: JOFFSET4
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description: data offset for injected channel 4
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bit_offset: 0
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bit_size: 12
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fieldset/JSQR:
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description: injected sequence register
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fields:
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- name: JSQ1
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description: 1st conversion in injected sequence
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bit_offset: 0
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bit_size: 5
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- name: JSQ2
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description: 2nd conversion in injected sequence
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bit_offset: 5
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bit_size: 5
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- name: JSQ3
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description: 3rd conversion in injected sequence
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bit_offset: 10
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bit_size: 5
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- name: JSQ4
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description: 4th conversion in injected sequence
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bit_offset: 15
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bit_size: 5
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- name: JL
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description: injected sequence length
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bit_offset: 20
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bit_size: 2
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fieldset/LTR:
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description: watchdog lower threshold register
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fields:
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- name: LT
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description: Analog watchdog low threshold
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bit_offset: 0
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bit_size: 12
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fieldset/SMPR1:
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description: sample time register 1
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fields:
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@ -324,48 +396,6 @@ fieldset/SMPR2:
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bit_offset: 27
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bit_size: 3
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enum: SAMPLE_TIME
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fieldset/JOFR1:
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description: injected channel data offset register 1
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fields:
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- name: JOFFSET1
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description: data offset for injected channel 1
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bit_offset: 0
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bit_size: 12
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fieldset/JOFR2:
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description: injected channel data offset register 2
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fields:
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- name: JOFFSET2
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description: data offset for injected channel 2
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bit_offset: 0
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bit_size: 12
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fieldset/JOFR3:
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description: injected channel data offset register 3
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fields:
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- name: JOFFSET3
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description: data offset for injected channel 3
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bit_offset: 0
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bit_size: 12
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fieldset/JOFR4:
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description: injected channel data offset register 4
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fields:
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- name: JOFFSET4
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description: data offset for injected channel 4
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bit_offset: 0
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bit_size: 12
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fieldset/HTR:
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description: watchdog higher threshold register
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fields:
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- name: HT
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description: Analog watchdog high threshold
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bit_offset: 0
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bit_size: 12
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fieldset/LTR:
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description: watchdog lower threshold register
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fields:
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- name: LT
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description: Analog watchdog low threshold
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bit_offset: 0
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bit_size: 12
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fieldset/SQR1:
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description: regular sequence register 1
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fields:
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@ -443,64 +473,33 @@ fieldset/SQR3:
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description: 6th conversion in regular sequence
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bit_offset: 25
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bit_size: 5
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fieldset/JSQR:
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description: injected sequence register
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fieldset/SR:
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description: status register
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fields:
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- name: JSQ1
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description: 1st conversion in injected sequence
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- name: AWD
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description: analog watchdog flag
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bit_offset: 0
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bit_size: 5
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- name: JSQ2
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description: 2nd conversion in injected sequence
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bit_size: 1
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- name: EOC
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description: end of conversion
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bit_offset: 1
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bit_size: 1
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- name: JEOC
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description: injected channel end of conversion
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bit_offset: 2
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bit_size: 1
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- name: JSTRT
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description: injected channel start flag
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bit_offset: 3
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bit_size: 1
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- name: STRT
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description: regular channel start flag
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bit_offset: 4
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bit_size: 1
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- name: OVR
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description: overrun
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bit_offset: 5
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bit_size: 5
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- name: JSQ3
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description: 3rd conversion in injected sequence
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bit_offset: 10
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bit_size: 5
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- name: JSQ4
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description: 4th conversion in injected sequence
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bit_offset: 15
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bit_size: 5
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- name: JL
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description: injected sequence length
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bit_offset: 20
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bit_size: 2
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fieldset/JDR1:
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description: injected data register 1
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fields:
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- name: JDATA1
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description: Injected data
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bit_offset: 0
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bit_size: 16
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fieldset/JDR2:
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description: injected data register 2
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fields:
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- name: JDATA2
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description: Injected data
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bit_offset: 0
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bit_size: 16
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fieldset/JDR3:
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description: injected data register 3
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fields:
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- name: JDATA3
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description: Injected data
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bit_offset: 0
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bit_size: 16
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fieldset/JDR4:
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description: injected data register 4
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fields:
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- name: JDATA4
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description: Injected data
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bit_offset: 0
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bit_size: 16
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fieldset/DR:
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description: regular data register
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fields:
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- name: DATA
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description: Regular data
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bit_offset: 0
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bit_size: 16
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bit_size: 1
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enum/DISCNUM:
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bit_size: 3
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variants:
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@ -528,33 +527,6 @@ enum/DISCNUM:
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- name: DISCNUM_8
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description: 8 conversions are discontinued and the conversions are carried out on 8 channels
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value: 7
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enum/JEXTSEL:
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bit_size: 3
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variants:
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- name: TIM19_CC1
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description: Timer 19 CC1 event
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value: 0
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- name: TIM19_CC2
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description: Timer 19 CC2 event
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value: 1
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- name: TIM2_TRGO
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description: Timer 2 TRGO event
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value: 2
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- name: TIM2_CC1
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description: Timer 2 CC1 event
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value: 3
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- name: TIM3_CC4
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description: Timer 3 CC4 event
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value: 4
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- name: TIM4_TRGO
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description: Timer 4 TRGO event
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value: 5
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- name: EXTI_LINE15
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description: External interrupt line 15
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value: 6
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- name: JSWSTART
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description: JSWSTART bit
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value: 7
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enum/EXTSEL:
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bit_size: 3
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variants:
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@ -582,6 +554,33 @@ enum/EXTSEL:
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- name: SWSTART
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description: SWSTART bit
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value: 7
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enum/JEXTSEL:
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bit_size: 3
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variants:
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- name: TIM19_CC1
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description: Timer 19 CC1 event
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value: 0
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- name: TIM19_CC2
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description: Timer 19 CC2 event
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value: 1
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- name: TIM2_TRGO
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description: Timer 2 TRGO event
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value: 2
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- name: TIM2_CC1
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description: Timer 2 CC1 event
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value: 3
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- name: TIM3_CC4
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description: Timer 3 CC4 event
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value: 4
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- name: TIM4_TRGO
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description: Timer 4 TRGO event
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value: 5
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- name: EXTI_LINE15
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description: External interrupt line 15
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value: 6
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- name: JSWSTART
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description: JSWSTART bit
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value: 7
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enum/SAMPLE_TIME:
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bit_size: 3
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variants:
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@ -609,5 +608,3 @@ enum/SAMPLE_TIME:
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- name: Cycles239_5
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description: 239.5 ADC clock cycles
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value: 7
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@ -1,4 +1,3 @@
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---
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block/ADC:
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description: Analog to Digital Converter
|
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items:
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@ -1,4 +1,3 @@
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---
|
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block/ADC:
|
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description: Analog-to-digital converter
|
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items:
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@ -1,4 +1,3 @@
|
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---
|
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block/ADC:
|
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description: Analog-to-digital converter
|
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items:
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|
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@ -1,4 +1,3 @@
|
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---
|
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block/ADC:
|
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description: Analog-to-Digital Converter
|
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items:
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|
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@ -1,4 +1,3 @@
|
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---
|
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block/ADC:
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description: Analog to Digital Converter
|
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items:
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@ -569,7 +568,7 @@ fieldset/PCSEL:
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description: channel preselection register
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fields:
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- name: PCSEL
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description: "Channel x (VINP[i]) pre selection"
|
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description: Channel x (VINP[i]) pre selection
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bit_offset: 0
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bit_size: 1
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array:
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@ -860,10 +859,10 @@ enum/JQM:
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bit_size: 1
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variants:
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- name: Mode0
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description: "JSQR Mode 0: Queue maintains the last written configuration into JSQR"
|
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description: 'JSQR Mode 0: Queue maintains the last written configuration into JSQR'
|
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value: 0
|
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- name: Mode1
|
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description: "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence"
|
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description: 'JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence'
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value: 1
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enum/OVRMOD:
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bit_size: 1
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@ -1,4 +1,3 @@
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---
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block/ADC_COMMON:
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description: ADC common registers
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items:
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@ -16,8 +15,57 @@ block/ADC_COMMON:
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byte_offset: 12
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access: Read
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fieldset: CDR
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fieldset/CCR:
|
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description: ADC common control register
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fields:
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- name: DUAL
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description: Dual ADC mode selection
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bit_offset: 0
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bit_size: 5
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enum: DUAL
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- name: DELAY
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description: Delay between 2 sampling phases
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bit_offset: 8
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bit_size: 4
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- name: DMACFG
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description: DMA configuration (for multi-ADC mode)
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bit_offset: 13
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bit_size: 1
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enum: DMACFG
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- name: MDMA
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description: Direct memory access mode for multi ADC mode
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bit_offset: 14
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bit_size: 2
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enum: MDMA
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- name: CKMODE
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description: ADC clock mode
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bit_offset: 16
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bit_size: 2
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enum: CKMODE
|
||||
- name: VREFEN
|
||||
description: VREFINT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSEN
|
||||
description: Temperature sensor enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/CDR:
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
fields:
|
||||
- name: RDATA_MST
|
||||
description: Regular data of the master ADC
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: RDATA_SLV
|
||||
description: Regular data of the master ADC
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/CSR:
|
||||
decsription: ADC common status register
|
||||
fields:
|
||||
- name: ADRDY_MST
|
||||
description: Master ADC ready
|
||||
@ -127,160 +175,110 @@ fieldset/CSR:
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
enum: JQOVF
|
||||
fieldset/CCR:
|
||||
description: ADC common control register
|
||||
fields:
|
||||
- name: DUAL
|
||||
description: Dual ADC mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
enum: DUAL
|
||||
- name: DELAY
|
||||
description: Delay between 2 sampling phases
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
- name: DMACFG
|
||||
description: DMA configuration (for multi-ADC mode)
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
enum: DMACFG
|
||||
- name: MDMA
|
||||
description: Direct memory access mode for multi ADC mode
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
enum: MDMA
|
||||
- name: CKMODE
|
||||
description: ADC clock mode
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: CKMODE
|
||||
- name: VREFEN
|
||||
description: VREFINT enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSEN
|
||||
description: Temperature sensor enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/CDR:
|
||||
description: ADC common regular data register for dual and triple modes
|
||||
fields:
|
||||
- name: RDATA_MST
|
||||
description: Regular data of the master ADC
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: RDATA_SLV
|
||||
description: Regular data of the master ADC
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
enum/ENDED:
|
||||
description: End of operation
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotEnded
|
||||
value: 0
|
||||
description: Operation is not ended
|
||||
- name: Ended
|
||||
value: 1
|
||||
description: Operation is ended
|
||||
enum/OVR:
|
||||
description: Overrun flag
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoOverrun
|
||||
value: 0
|
||||
description: No overrun occurred
|
||||
- name: Overrun
|
||||
value: 1
|
||||
description: Overrun occurred
|
||||
enum/AWD:
|
||||
description: Analog watchdog flag
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoEvent
|
||||
value: 0
|
||||
description: No analog watchdog event occurred
|
||||
value: 0
|
||||
- name: Event
|
||||
value: 1
|
||||
description: Analog watchdog event occurred
|
||||
enum/JQOVF:
|
||||
description: Injected context queue overflow flag
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoOverflow
|
||||
value: 0
|
||||
description: No injected context queue overflow
|
||||
- name: Overflow
|
||||
value: 1
|
||||
description: Injected context queue overflow
|
||||
enum/DUAL:
|
||||
description: Dual ADC mode selection
|
||||
bit_size: 5
|
||||
variants:
|
||||
- name: Independent
|
||||
value: 0
|
||||
description: Independent mode
|
||||
- name: DualRJ
|
||||
value: 1
|
||||
description: Dual, combined regular simultaneous + injected simultaneous mode
|
||||
- name: DualRA
|
||||
value: 2
|
||||
description: Dual, combined regular simultaneous + alternate trigger mode
|
||||
- name: DualIJ
|
||||
value: 3
|
||||
description: Dual, combined injected simultaneous + fast interleaved mode
|
||||
- name: DualJ
|
||||
value: 5
|
||||
description: Dual, injected simultaneous mode only
|
||||
- name: DualR
|
||||
value: 6
|
||||
description: Dual, regular simultaneous mode only
|
||||
- name: DualI
|
||||
value: 7
|
||||
description: dual, interleaved mode only
|
||||
- name: DualA
|
||||
value: 9
|
||||
description: Dual, alternate trigger mode only
|
||||
enum/DMACFG:
|
||||
description: DMA configuration (for multi-ADC mode)
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: OneShot
|
||||
value: 0
|
||||
description: DMA one shot mode selected
|
||||
- name: Circulator
|
||||
value: 1
|
||||
description: DMA circular mode selected
|
||||
enum/MDMA:
|
||||
description: Direct memory access mode for multi ADC mode
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
value: 0
|
||||
description: MDMA mode disabled
|
||||
- name: Bits12_10
|
||||
value: 2
|
||||
description: MDMA mode enabled for 12 and 10-bit resolution
|
||||
- name: Bit8_6
|
||||
value: 3
|
||||
description: MDMA mode enabled for 8 and 6-bit resolution
|
||||
enum/CKMODE:
|
||||
description: ADC clock mode
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Asynchronous
|
||||
value: 0
|
||||
description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous mode
|
||||
value: 0
|
||||
- name: SyncDiv1
|
||||
value: 1
|
||||
description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck.
|
||||
value: 1
|
||||
- name: SyncDiv2
|
||||
value: 2
|
||||
description: Use AHB clock rcc_hclk3 divided by 2.
|
||||
value: 2
|
||||
- name: SyncDiv4
|
||||
value: 3
|
||||
description: Use AHB clock rcc_hclk3 divided by 4.
|
||||
value: 3
|
||||
enum/DMACFG:
|
||||
description: DMA configuration (for multi-ADC mode)
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: OneShot
|
||||
description: DMA one shot mode selected
|
||||
value: 0
|
||||
- name: Circulator
|
||||
description: DMA circular mode selected
|
||||
value: 1
|
||||
enum/DUAL:
|
||||
description: Dual ADC mode selection
|
||||
bit_size: 5
|
||||
variants:
|
||||
- name: Independent
|
||||
description: Independent mode
|
||||
value: 0
|
||||
- name: DualRJ
|
||||
description: Dual, combined regular simultaneous + injected simultaneous mode
|
||||
value: 1
|
||||
- name: DualRA
|
||||
description: Dual, combined regular simultaneous + alternate trigger mode
|
||||
value: 2
|
||||
- name: DualIJ
|
||||
description: Dual, combined injected simultaneous + fast interleaved mode
|
||||
value: 3
|
||||
- name: DualJ
|
||||
description: Dual, injected simultaneous mode only
|
||||
value: 5
|
||||
- name: DualR
|
||||
description: Dual, regular simultaneous mode only
|
||||
value: 6
|
||||
- name: DualI
|
||||
description: dual, interleaved mode only
|
||||
value: 7
|
||||
- name: DualA
|
||||
description: Dual, alternate trigger mode only
|
||||
value: 9
|
||||
enum/ENDED:
|
||||
description: End of operation
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotEnded
|
||||
description: Operation is not ended
|
||||
value: 0
|
||||
- name: Ended
|
||||
description: Operation is ended
|
||||
value: 1
|
||||
enum/JQOVF:
|
||||
description: Injected context queue overflow flag
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoOverflow
|
||||
description: No injected context queue overflow
|
||||
value: 0
|
||||
- name: Overflow
|
||||
description: Injected context queue overflow
|
||||
value: 1
|
||||
enum/MDMA:
|
||||
description: Direct memory access mode for multi ADC mode
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: MDMA mode disabled
|
||||
value: 0
|
||||
- name: Bits12_10
|
||||
description: MDMA mode enabled for 12 and 10-bit resolution
|
||||
value: 2
|
||||
- name: Bit8_6
|
||||
description: MDMA mode enabled for 8 and 6-bit resolution
|
||||
value: 3
|
||||
enum/OVR:
|
||||
description: Overrun flag
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NoOverrun
|
||||
description: No overrun occurred
|
||||
value: 0
|
||||
- name: Overrun
|
||||
description: Overrun occurred
|
||||
value: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/ADC_COMMON:
|
||||
description: ADC common registers
|
||||
items:
|
||||
@ -143,7 +142,7 @@ enum/DDS:
|
||||
description: No new DMA request is issued after the last transfer
|
||||
value: 0
|
||||
- name: Continuous
|
||||
description: "DMA requests are issued as long as data are converted and DMA=01, 10 or 11"
|
||||
description: DMA requests are issued as long as data are converted and DMA=01, 10 or 11
|
||||
value: 1
|
||||
enum/DMA:
|
||||
bit_size: 2
|
||||
@ -191,43 +190,43 @@ enum/MULTI:
|
||||
bit_size: 5
|
||||
variants:
|
||||
- name: Independent
|
||||
description: "All the ADCs independent: independent mode"
|
||||
description: 'All the ADCs independent: independent mode'
|
||||
value: 0
|
||||
- name: DualRJ
|
||||
description: "Dual ADC1 and ADC2, combined regular and injected simultaneous mode"
|
||||
description: Dual ADC1 and ADC2, combined regular and injected simultaneous mode
|
||||
value: 1
|
||||
- name: DualRA
|
||||
description: "Dual ADC1 and ADC2, combined regular and alternate trigger mode"
|
||||
description: Dual ADC1 and ADC2, combined regular and alternate trigger mode
|
||||
value: 2
|
||||
- name: DualJ
|
||||
description: "Dual ADC1 and ADC2, injected simultaneous mode only"
|
||||
description: Dual ADC1 and ADC2, injected simultaneous mode only
|
||||
value: 5
|
||||
- name: DualR
|
||||
description: "Dual ADC1 and ADC2, regular simultaneous mode only"
|
||||
description: Dual ADC1 and ADC2, regular simultaneous mode only
|
||||
value: 6
|
||||
- name: DualI
|
||||
description: "Dual ADC1 and ADC2, interleaved mode only"
|
||||
description: Dual ADC1 and ADC2, interleaved mode only
|
||||
value: 7
|
||||
- name: DualA
|
||||
description: "Dual ADC1 and ADC2, alternate trigger mode only"
|
||||
description: Dual ADC1 and ADC2, alternate trigger mode only
|
||||
value: 9
|
||||
- name: TripleRJ
|
||||
description: "Triple ADC, regular and injected simultaneous mode"
|
||||
description: Triple ADC, regular and injected simultaneous mode
|
||||
value: 17
|
||||
- name: TripleRA
|
||||
description: "Triple ADC, regular and alternate trigger mode"
|
||||
description: Triple ADC, regular and alternate trigger mode
|
||||
value: 18
|
||||
- name: TripleJ
|
||||
description: "Triple ADC, injected simultaneous mode only"
|
||||
description: Triple ADC, injected simultaneous mode only
|
||||
value: 21
|
||||
- name: TripleR
|
||||
description: "Triple ADC, regular simultaneous mode only"
|
||||
description: Triple ADC, regular simultaneous mode only
|
||||
value: 22
|
||||
- name: TripleI
|
||||
description: "Triple ADC, interleaved mode only"
|
||||
description: Triple ADC, interleaved mode only
|
||||
value: 23
|
||||
- name: TripleA
|
||||
description: "Triple ADC, alternate trigger mode only"
|
||||
description: Triple ADC, alternate trigger mode only
|
||||
value: 24
|
||||
enum/OVR:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/ADC_COMMON:
|
||||
description: Analog-to-Digital Converter
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/ADC_COMMON:
|
||||
description: Analog-to-Digital Converter
|
||||
items:
|
||||
@ -228,7 +227,7 @@ enum/DAMDF:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: NoPack
|
||||
description: "Without data packing, CDR/CDR2 not used"
|
||||
description: Without data packing, CDR/CDR2 not used
|
||||
value: 0
|
||||
- name: Format32to10
|
||||
description: CDR formatted for 32-bit down to 10-bit resolution
|
||||
@ -243,25 +242,25 @@ enum/DUAL:
|
||||
description: Independent mode
|
||||
value: 0
|
||||
- name: DualRJ
|
||||
description: "Dual, combined regular simultaneous + injected simultaneous mode"
|
||||
description: Dual, combined regular simultaneous + injected simultaneous mode
|
||||
value: 1
|
||||
- name: DualRA
|
||||
description: "Dual, combined regular simultaneous + alternate trigger mode"
|
||||
description: Dual, combined regular simultaneous + alternate trigger mode
|
||||
value: 2
|
||||
- name: DualIJ
|
||||
description: "Dual, combined interleaved mode + injected simultaneous mode"
|
||||
description: Dual, combined interleaved mode + injected simultaneous mode
|
||||
value: 3
|
||||
- name: DualJ
|
||||
description: "Dual, injected simultaneous mode only"
|
||||
description: Dual, injected simultaneous mode only
|
||||
value: 5
|
||||
- name: DualR
|
||||
description: "Dual, regular simultaneous mode only"
|
||||
description: Dual, regular simultaneous mode only
|
||||
value: 6
|
||||
- name: DualI
|
||||
description: "Dual, interleaved mode only"
|
||||
description: Dual, interleaved mode only
|
||||
value: 7
|
||||
- name: DualA
|
||||
description: "Dual, alternate trigger mode only"
|
||||
description: Dual, alternate trigger mode only
|
||||
value: 9
|
||||
enum/EOC_MST:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/AES:
|
||||
description: Advanced encryption standard hardware accelerator
|
||||
items:
|
||||
@ -192,14 +191,14 @@ enum/MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Mode1
|
||||
description: "Encryption"
|
||||
description: Encryption
|
||||
value: 0
|
||||
- name: Mode2
|
||||
description: "Key derivation (or key preparation for ECB/CBC decryption)"
|
||||
description: Key derivation (or key preparation for ECB/CBC decryption)
|
||||
value: 1
|
||||
- name: Mode3
|
||||
description: "Decryption"
|
||||
description: Decryption
|
||||
value: 2
|
||||
- name: Mode4
|
||||
description: "Key derivation then single decryption"
|
||||
description: Key derivation then single decryption
|
||||
value: 3
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/AES:
|
||||
description: Advanced encryption standard hardware accelerator
|
||||
items:
|
||||
@ -18,18 +17,6 @@ block/AES:
|
||||
description: Data output register
|
||||
byte_offset: 12
|
||||
fieldset: DOUTR
|
||||
- name: IER
|
||||
description: interrupt enable register
|
||||
byte_offset: 768
|
||||
fieldset: IER
|
||||
- name: ISR
|
||||
description: interrupt status register
|
||||
byte_offset: 772
|
||||
fieldset: ISR
|
||||
- name: ICR
|
||||
description: interrupt clear register
|
||||
byte_offset: 776
|
||||
fieldset: ICR
|
||||
- name: KEYR
|
||||
description: Key register
|
||||
array:
|
||||
@ -58,6 +45,18 @@ block/AES:
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SUSPR
|
||||
- name: IER
|
||||
description: interrupt enable register
|
||||
byte_offset: 768
|
||||
fieldset: IER
|
||||
- name: ISR
|
||||
description: interrupt status register
|
||||
byte_offset: 772
|
||||
fieldset: ISR
|
||||
- name: ICR
|
||||
description: interrupt clear register
|
||||
byte_offset: 776
|
||||
fieldset: ICR
|
||||
fieldset/CR:
|
||||
description: Control register
|
||||
fields:
|
||||
@ -249,11 +248,11 @@ enum/MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Mode1
|
||||
description: "Encryption"
|
||||
description: Encryption
|
||||
value: 0
|
||||
- name: Mode2
|
||||
description: "Key derivation (or key preparation for ECB/CBC decryption)"
|
||||
description: Key derivation (or key preparation for ECB/CBC decryption)
|
||||
value: 1
|
||||
- name: Mode3
|
||||
description: "Decryption"
|
||||
description: Decryption
|
||||
value: 2
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/AES:
|
||||
description: Advanced encryption standard hardware accelerator
|
||||
items:
|
||||
@ -95,7 +94,7 @@ fieldset/IVR:
|
||||
description: Initialization vector register
|
||||
fields:
|
||||
- name: IVI
|
||||
description: "Initialization vector input"
|
||||
description: Initialization vector input
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/KEYR:
|
||||
@ -139,14 +138,14 @@ enum/MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Mode1
|
||||
description: "Encryption"
|
||||
description: Encryption
|
||||
value: 0
|
||||
- name: Mode2
|
||||
description: "Key derivation (or key preparation for ECB/CBC decryption)"
|
||||
description: Key derivation (or key preparation for ECB/CBC decryption)
|
||||
value: 1
|
||||
- name: Mode3
|
||||
description: "Decryption"
|
||||
description: Decryption
|
||||
value: 2
|
||||
- name: Mode4
|
||||
description: "Key derivation then single decryption"
|
||||
description: Key derivation then single decryption
|
||||
value: 3
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/AES:
|
||||
description: Advanced encryption standard hardware accelerator
|
||||
items:
|
||||
@ -196,14 +195,14 @@ enum/MODE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Mode1
|
||||
description: "Encryption"
|
||||
description: Encryption
|
||||
value: 0
|
||||
- name: Mode2
|
||||
description: "Key derivation (or key preparation for ECB/CBC decryption)"
|
||||
description: Key derivation (or key preparation for ECB/CBC decryption)
|
||||
value: 1
|
||||
- name: Mode3
|
||||
description: "Decryption"
|
||||
description: Decryption
|
||||
value: 2
|
||||
- name: Mode4
|
||||
description: "Key derivation then single decryption"
|
||||
description: Key derivation then single decryption
|
||||
value: 3
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/AFIO:
|
||||
description: Alternate function I/O
|
||||
items:
|
||||
|
||||
@ -1,6 +1,5 @@
|
||||
---
|
||||
block/CH:
|
||||
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
|
||||
description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
|
||||
items:
|
||||
- name: CR
|
||||
description: DMA channel configuration register (DMA_CCR)
|
||||
@ -30,7 +29,7 @@ block/DMA:
|
||||
access: Write
|
||||
fieldset: ISR
|
||||
- name: CH
|
||||
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
|
||||
description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
|
||||
array:
|
||||
len: 8
|
||||
stride: 20
|
||||
|
||||
@ -1,6 +1,5 @@
|
||||
---
|
||||
block/CH:
|
||||
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
|
||||
description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
|
||||
items:
|
||||
- name: CR
|
||||
description: DMA channel configuration register (DMA_CCR)
|
||||
@ -30,7 +29,7 @@ block/DMA:
|
||||
access: Write
|
||||
fieldset: ISR
|
||||
- name: CH
|
||||
description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
|
||||
description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
|
||||
array:
|
||||
len: 8
|
||||
stride: 20
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/BKP:
|
||||
description: Backup registers
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/CAN:
|
||||
description: Controller area network
|
||||
items:
|
||||
@ -643,10 +642,10 @@ enum/FMPIE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "No interrupt generated when state of FMP[1:0] bits are not 00b"
|
||||
description: No interrupt generated when state of FMP[1:0] bits are not 00b
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "Interrupt generated when state of FMP[1:0] bits are not 00b"
|
||||
description: Interrupt generated when state of FMP[1:0] bits are not 00b
|
||||
value: 1
|
||||
enum/FOVIE:
|
||||
bit_size: 1
|
||||
@ -697,10 +696,10 @@ enum/LECIE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection"
|
||||
description: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection"
|
||||
description: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection
|
||||
value: 1
|
||||
enum/RIR_IDE:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FDCAN:
|
||||
description: FDCAN
|
||||
items:
|
||||
@ -13,15 +12,15 @@ block/FDCAN:
|
||||
access: Read
|
||||
fieldset: ENDN
|
||||
- name: DBTP
|
||||
description: "This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point."
|
||||
description: This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.
|
||||
byte_offset: 12
|
||||
fieldset: DBTP
|
||||
- name: TEST
|
||||
description: "Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus."
|
||||
description: Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.
|
||||
byte_offset: 16
|
||||
fieldset: TEST
|
||||
- name: RWD
|
||||
description: "The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock."
|
||||
description: The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.
|
||||
byte_offset: 20
|
||||
fieldset: RWD
|
||||
- name: CCCR
|
||||
@ -70,7 +69,7 @@ block/FDCAN:
|
||||
byte_offset: 84
|
||||
fieldset: IE
|
||||
- name: ILS
|
||||
description: "The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]."
|
||||
description: The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1].
|
||||
byte_offset: 88
|
||||
fieldset: ILS
|
||||
- name: ILE
|
||||
@ -78,7 +77,7 @@ block/FDCAN:
|
||||
byte_offset: 92
|
||||
fieldset: ILE
|
||||
- name: RXGFC
|
||||
description: "Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path."
|
||||
description: 'Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path.'
|
||||
byte_offset: 128
|
||||
fieldset: RXGFC
|
||||
- name: XIDAM
|
||||
@ -92,21 +91,21 @@ block/FDCAN:
|
||||
fieldset: HPMS
|
||||
- name: RXFS
|
||||
description: FDCAN Rx FIFO X Status Register
|
||||
byte_offset: 144
|
||||
fieldset: RXFS
|
||||
access: Read
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 8
|
||||
byte_offset: 144
|
||||
access: Read
|
||||
fieldset: RXFS
|
||||
- name: RXFA
|
||||
description: CAN Rx FIFO 0 Acknowledge Register
|
||||
byte_offset: 148
|
||||
fieldset: RXFA
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 8
|
||||
byte_offset: 148
|
||||
fieldset: RXFA
|
||||
- name: TXBC
|
||||
description: FDCAN Tx Buffer Configuration Register
|
||||
byte_offset: 192
|
||||
@ -254,7 +253,7 @@ fieldset/CREL:
|
||||
bit_offset: 28
|
||||
bit_size: 4
|
||||
fieldset/DBTP:
|
||||
description: "This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point."
|
||||
description: This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.
|
||||
fields:
|
||||
- name: DSJW
|
||||
description: DSJW
|
||||
@ -348,7 +347,6 @@ fieldset/IE:
|
||||
offsets:
|
||||
- 0
|
||||
- 3
|
||||
|
||||
- name: HPME
|
||||
description: High-priority message enable
|
||||
bit_offset: 6
|
||||
@ -433,7 +431,7 @@ fieldset/ILE:
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/ILS:
|
||||
description: "The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]."
|
||||
description: The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1].
|
||||
fields:
|
||||
- name: RXFIFO
|
||||
description: RX FIFO bit grouping the following interruption
|
||||
@ -628,7 +626,7 @@ fieldset/PSR:
|
||||
bit_offset: 16
|
||||
bit_size: 7
|
||||
fieldset/RWD:
|
||||
description: "The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock."
|
||||
description: The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.
|
||||
fields:
|
||||
- name: WDC
|
||||
description: WDC
|
||||
@ -669,7 +667,7 @@ fieldset/RXFS:
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
fieldset/RXGFC:
|
||||
description: "Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path."
|
||||
description: 'Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path.'
|
||||
fields:
|
||||
- name: RRFE
|
||||
description: RRFE
|
||||
@ -715,7 +713,7 @@ fieldset/TDCR:
|
||||
bit_offset: 8
|
||||
bit_size: 7
|
||||
fieldset/TEST:
|
||||
description: "Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus."
|
||||
description: Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.
|
||||
fields:
|
||||
- name: LBCK
|
||||
description: LBCK
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/CRC:
|
||||
description: Cyclic Redundancy Check calculation unit
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/CRC:
|
||||
description: Cyclic Redundancy Check calculation unit
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/CRC:
|
||||
description: Cyclic Redundancy Check calculation unit
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/CRS:
|
||||
description: Clock recovery system
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
@ -330,7 +329,6 @@ enum/TSEL1:
|
||||
- name: LPTIM3_OUT
|
||||
description: Low-power timer 3 OUT event
|
||||
value: 14
|
||||
|
||||
enum/TSEL2:
|
||||
bit_size: 4
|
||||
variants:
|
||||
@ -379,7 +377,6 @@ enum/TSEL2:
|
||||
- name: LPTIM3_OUT
|
||||
description: Low-power timer 3 OUT event
|
||||
value: 14
|
||||
|
||||
enum/WAVE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: MCU debug component
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: MCU debug component
|
||||
items:
|
||||
@ -285,32 +284,32 @@ fieldset/CIDR0:
|
||||
description: Debug MCU CoreSight component identity register 0
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: "component identification bits [7:0]"
|
||||
description: component identification bits [7:0]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CIDR1:
|
||||
description: Debug MCU CoreSight component identity register 1
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: "component identification bits [11:8]"
|
||||
description: component identification bits [11:8]
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: CLASS
|
||||
description: "component identification bits [15:12] - component class"
|
||||
description: component identification bits [15:12] - component class
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/CIDR2:
|
||||
description: Debug MCU CoreSight component identity register 2
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: "component identification bits [23:16]"
|
||||
description: component identification bits [23:16]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CIDR3:
|
||||
description: Debug MCU CoreSight component identity register 3
|
||||
fields:
|
||||
- name: PREAMBLE
|
||||
description: "component identification bits [31:24]"
|
||||
description: component identification bits [31:24]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/CR:
|
||||
@ -376,25 +375,25 @@ fieldset/PIDR0:
|
||||
description: Debug MCU CoreSight peripheral identity register 0
|
||||
fields:
|
||||
- name: PARTNUM
|
||||
description: "part number bits [7:0]"
|
||||
description: part number bits [7:0]
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/PIDR1:
|
||||
description: Debug MCU CoreSight peripheral identity register 1
|
||||
fields:
|
||||
- name: PARTNUM
|
||||
description: "part number bits [11:8]"
|
||||
description: part number bits [11:8]
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: JEP106ID
|
||||
description: "JEP106 identity code bits [3:0]"
|
||||
description: JEP106 identity code bits [3:0]
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/PIDR2:
|
||||
description: Debug MCU CoreSight peripheral identity register 2
|
||||
fields:
|
||||
- name: JEP106ID
|
||||
description: "JEP106 identity code bits [6:4]"
|
||||
description: JEP106 identity code bits [6:4]
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
- name: JEDEC
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Microcontroller Debug Unit
|
||||
items:
|
||||
@ -16,7 +15,7 @@ block/DBGMCU:
|
||||
byte_offset: 60
|
||||
fieldset: APB1FZR1
|
||||
- name: C2APB1FZR1
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 1 [dual core device"
|
||||
description: CPU2 APB1 Peripheral Freeze Register 1 [dual core device
|
||||
byte_offset: 64
|
||||
fieldset: C2APB1FZR1
|
||||
- name: APB1FZR2
|
||||
@ -24,7 +23,7 @@ block/DBGMCU:
|
||||
byte_offset: 68
|
||||
fieldset: APB1FZR2
|
||||
- name: C2APB1FZR2
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 2 [dual core device"
|
||||
description: CPU2 APB1 Peripheral Freeze Register 2 [dual core device
|
||||
byte_offset: 72
|
||||
fieldset: C2APB1FZR2
|
||||
- name: APB2FZR
|
||||
@ -32,7 +31,7 @@ block/DBGMCU:
|
||||
byte_offset: 76
|
||||
fieldset: APB2FZR
|
||||
- name: C2APB2FZR
|
||||
description: "CPU2 APB2 Peripheral Freeze Register [dual core device"
|
||||
description: CPU2 APB2 Peripheral Freeze Register [dual core device
|
||||
byte_offset: 80
|
||||
fieldset: C2APB2FZR
|
||||
fieldset/APB1FZR1:
|
||||
@ -97,7 +96,7 @@ fieldset/APB2FZR:
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/C2APB1FZR1:
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 1 [dual core device"
|
||||
description: CPU2 APB1 Peripheral Freeze Register 1 [dual core device
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
@ -128,7 +127,7 @@ fieldset/C2APB1FZR1:
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/C2APB1FZR2:
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 2 [dual core device"
|
||||
description: CPU2 APB1 Peripheral Freeze Register 2 [dual core device
|
||||
fields:
|
||||
- name: LPTIM2
|
||||
description: LPTIM2
|
||||
@ -139,7 +138,7 @@ fieldset/C2APB1FZR2:
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/C2APB2FZR:
|
||||
description: "CPU2 APB2 Peripheral Freeze Register [dual core device"
|
||||
description: CPU2 APB2 Peripheral Freeze Register [dual core device
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DCMI:
|
||||
description: Digital camera interface
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DMA2D:
|
||||
description: DMA2D controller
|
||||
items:
|
||||
@ -460,10 +459,10 @@ enum/BGPFCCR_AM:
|
||||
description: No modification of alpha channel
|
||||
value: 0
|
||||
- name: Replace
|
||||
description: "Replace with value in ALPHA[7:0]"
|
||||
description: Replace with value in ALPHA[7:0]
|
||||
value: 1
|
||||
- name: Multiply
|
||||
description: "Multiply with value in ALPHA[7:0]"
|
||||
description: Multiply with value in ALPHA[7:0]
|
||||
value: 2
|
||||
enum/BGPFCCR_CCM:
|
||||
bit_size: 1
|
||||
@ -601,10 +600,10 @@ enum/FGPFCCR_AM:
|
||||
description: No modification of alpha channel
|
||||
value: 0
|
||||
- name: Replace
|
||||
description: "Replace with value in ALPHA[7:0]"
|
||||
description: Replace with value in ALPHA[7:0]
|
||||
value: 1
|
||||
- name: Multiply
|
||||
description: "Multiply with value in ALPHA[7:0]"
|
||||
description: Multiply with value in ALPHA[7:0]
|
||||
value: 2
|
||||
enum/FGPFCCR_CCM:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DMA2D:
|
||||
description: DMA2D
|
||||
items:
|
||||
@ -99,77 +98,77 @@ fieldset/BGCMAR:
|
||||
description: DMA2D background CLUT memory address register
|
||||
fields:
|
||||
- name: MA
|
||||
description: "Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned."
|
||||
description: Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned.
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/BGCOLR:
|
||||
description: DMA2D background color register
|
||||
fields:
|
||||
- name: BLUE
|
||||
description: "Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: GREEN
|
||||
description: "Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: RED
|
||||
description: "Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
fieldset/BGMAR:
|
||||
description: DMA2D background memory address register
|
||||
fields:
|
||||
- name: MA
|
||||
description: "Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned."
|
||||
description: Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned.
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/BGOR:
|
||||
description: DMA2D background offset register
|
||||
fields:
|
||||
- name: LO
|
||||
description: "Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even."
|
||||
description: Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even.
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/BGPFCCR:
|
||||
description: DMA2D background PFC control register
|
||||
fields:
|
||||
- name: CM
|
||||
description: "Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless"
|
||||
description: 'Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless'
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
enum: BGPFCCR_CM
|
||||
- name: CCM
|
||||
description: "CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only."
|
||||
description: CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only.
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: BGPFCCR_CCM
|
||||
- name: START
|
||||
description: "Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer)."
|
||||
description: 'Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer).'
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: BGPFCCR_START
|
||||
- name: CS
|
||||
description: "CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1."
|
||||
description: CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1.
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: AM
|
||||
description: "Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless"
|
||||
description: 'Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless'
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: BGPFCCR_AM
|
||||
- name: AI
|
||||
description: "Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only."
|
||||
description: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
enum: BGPFCCR_AI
|
||||
- name: RBS
|
||||
description: "Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only."
|
||||
description: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only.
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
enum: BGPFCCR_RBS
|
||||
- name: ALPHA
|
||||
description: "Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: 'Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.'
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/CR:
|
||||
@ -229,81 +228,81 @@ fieldset/FGCMAR:
|
||||
description: DMA2D foreground CLUT memory address register
|
||||
fields:
|
||||
- name: MA
|
||||
description: "Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned."
|
||||
description: Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned.
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/FGCOLR:
|
||||
description: DMA2D foreground color register
|
||||
fields:
|
||||
- name: BLUE
|
||||
description: "Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only."
|
||||
description: Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: GREEN
|
||||
description: "Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only."
|
||||
description: Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only.
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: RED
|
||||
description: "Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
fieldset/FGMAR:
|
||||
description: DMA2D foreground memory address register
|
||||
fields:
|
||||
- name: MA
|
||||
description: "Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned."
|
||||
description: Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned.
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/FGOR:
|
||||
description: DMA2D foreground offset register
|
||||
fields:
|
||||
- name: LO
|
||||
description: "Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even."
|
||||
description: Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even.
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/FGPFCCR:
|
||||
description: DMA2D foreground PFC control register
|
||||
fields:
|
||||
- name: CM
|
||||
description: "Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless"
|
||||
description: 'Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless'
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
enum: FGPFCCR_CM
|
||||
- name: CCM
|
||||
description: "CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only."
|
||||
description: CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only.
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: FGPFCCR_CCM
|
||||
- name: START
|
||||
description: "Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer)."
|
||||
description: 'Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer).'
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: FGPFCCR_START
|
||||
- name: CS
|
||||
description: "CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1."
|
||||
description: CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1.
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: AM
|
||||
description: "Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless"
|
||||
description: Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: FGPFCCR_AM
|
||||
- name: CSS
|
||||
description: "Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless"
|
||||
description: 'Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless'
|
||||
bit_offset: 18
|
||||
bit_size: 2
|
||||
- name: AI
|
||||
description: "Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only."
|
||||
description: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
enum: FGPFCCR_AI
|
||||
- name: RBS
|
||||
description: "Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only."
|
||||
description: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only.
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
enum: FGPFCCR_RBS
|
||||
- name: ALPHA
|
||||
description: "Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only."
|
||||
description: Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only.
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/IFCR:
|
||||
@ -363,65 +362,65 @@ fieldset/ISR:
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: CEIF
|
||||
description: "Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed."
|
||||
description: Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed.
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/LWR:
|
||||
description: DMA2D line watermark register
|
||||
fields:
|
||||
- name: LW
|
||||
description: "Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/NLR:
|
||||
description: DMA2D number of line register
|
||||
fields:
|
||||
- name: NL
|
||||
description: "Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: PL
|
||||
description: "Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even."
|
||||
description: Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even.
|
||||
bit_offset: 16
|
||||
bit_size: 14
|
||||
fieldset/OCOLR:
|
||||
description: DMA2D output color register
|
||||
fields:
|
||||
- name: BLUE
|
||||
description: "Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: GREEN
|
||||
description: "Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: RED
|
||||
description: "Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
- name: ALPHA
|
||||
description: "Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 24
|
||||
bit_size: 8
|
||||
fieldset/OMAR:
|
||||
description: DMA2D output memory address register
|
||||
fields:
|
||||
- name: MA
|
||||
description: "Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned."
|
||||
description: Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned.
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/OOR:
|
||||
description: DMA2D output offset register
|
||||
fields:
|
||||
- name: LO
|
||||
description: "Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
|
||||
description: Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/OPFCCR:
|
||||
description: DMA2D output PFC control register
|
||||
fields:
|
||||
- name: CM
|
||||
description: "Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless"
|
||||
description: 'Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless'
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: OPFCCR_CM
|
||||
@ -431,12 +430,12 @@ fieldset/OPFCCR:
|
||||
bit_size: 1
|
||||
enum: SB
|
||||
- name: AI
|
||||
description: "Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only."
|
||||
description: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
enum: OPFCCR_AI
|
||||
- name: RBS
|
||||
description: "Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only."
|
||||
description: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only.
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
enum: OPFCCR_RBS
|
||||
@ -462,10 +461,10 @@ enum/BGPFCCR_AM:
|
||||
description: No modification of alpha channel
|
||||
value: 0
|
||||
- name: Replace
|
||||
description: "Replace with value in ALPHA[7:0]"
|
||||
description: Replace with value in ALPHA[7:0]
|
||||
value: 1
|
||||
- name: Multiply
|
||||
description: "Multiply with value in ALPHA[7:0]"
|
||||
description: Multiply with value in ALPHA[7:0]
|
||||
value: 2
|
||||
enum/BGPFCCR_CCM:
|
||||
bit_size: 1
|
||||
@ -621,10 +620,10 @@ enum/FGPFCCR_AM:
|
||||
description: No modification of alpha channel
|
||||
value: 0
|
||||
- name: Replace
|
||||
description: "Replace with value in ALPHA[7:0]"
|
||||
description: Replace with value in ALPHA[7:0]
|
||||
value: 1
|
||||
- name: Multiply
|
||||
description: "Multiply with value in ALPHA[7:0]"
|
||||
description: Multiply with value in ALPHA[7:0]
|
||||
value: 2
|
||||
enum/FGPFCCR_CCM:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DMA:
|
||||
description: DMA controller
|
||||
items:
|
||||
@ -19,14 +18,14 @@ block/DMA:
|
||||
access: Write
|
||||
fieldset: IXR
|
||||
- name: ST
|
||||
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
|
||||
description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
|
||||
array:
|
||||
len: 8
|
||||
stride: 24
|
||||
byte_offset: 16
|
||||
block: ST
|
||||
block/ST:
|
||||
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
|
||||
description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
|
||||
items:
|
||||
- name: CR
|
||||
description: stream x configuration register
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DMA:
|
||||
description: DMA controller
|
||||
items:
|
||||
@ -19,14 +18,14 @@ block/DMA:
|
||||
access: Write
|
||||
fieldset: IXR
|
||||
- name: ST
|
||||
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
|
||||
description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
|
||||
array:
|
||||
len: 8
|
||||
stride: 24
|
||||
byte_offset: 16
|
||||
block: ST
|
||||
block/ST:
|
||||
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
|
||||
description: 'Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers'
|
||||
items:
|
||||
- name: CR
|
||||
description: stream x configuration register
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/DMAMUX:
|
||||
description: DMAMUX
|
||||
items:
|
||||
@ -56,12 +55,12 @@ fieldset/CCR:
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: SPOL
|
||||
description: "Synchronization event type selector Defines the synchronization event on the selected synchronization input:"
|
||||
description: 'Synchronization event type selector Defines the synchronization event on the selected synchronization input:'
|
||||
bit_offset: 17
|
||||
bit_size: 2
|
||||
enum: POL
|
||||
- name: NBREQ
|
||||
description: "Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset."
|
||||
description: 'Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.'
|
||||
bit_offset: 19
|
||||
bit_size: 5
|
||||
- name: SYNC_ID
|
||||
@ -99,14 +98,14 @@ fieldset/RGCR:
|
||||
bit_size: 2
|
||||
enum: POL
|
||||
- name: GNBREQ
|
||||
description: "Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset."
|
||||
description: 'Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.'
|
||||
bit_offset: 19
|
||||
bit_size: 5
|
||||
fieldset/RGSR:
|
||||
description: DMAMux - DMA request generator status register
|
||||
fields:
|
||||
- name: OF
|
||||
description: "Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register."
|
||||
description: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
@ -116,7 +115,7 @@ enum/POL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: NoEdge
|
||||
description: "No event, i.e. no synchronization nor detection"
|
||||
description: No event, i.e. no synchronization nor detection
|
||||
value: 0
|
||||
- name: RisingEdge
|
||||
description: Rising edge
|
||||
|
||||
@ -1,21 +1,20 @@
|
||||
---
|
||||
block/ETH:
|
||||
description: Ethernet Peripheral
|
||||
items:
|
||||
- name: ETHERNET_MAC
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
byte_offset: 0
|
||||
block: ETHERNET_MAC
|
||||
- name: ETHERNET_PTP
|
||||
description: "Ethernet: Precision Time Protocol (PTP)"
|
||||
description: 'Ethernet: Precision Time Protocol (PTP)'
|
||||
byte_offset: 1792
|
||||
block: ETHERNET_PTP
|
||||
- name: ETHERNET_DMA
|
||||
description: "Ethernet: DMA mode register (DMA)"
|
||||
description: 'Ethernet: DMA mode register (DMA)'
|
||||
byte_offset: 4096
|
||||
block: ETHERNET_DMA
|
||||
block/ETHERNET_DMA:
|
||||
description: "Ethernet: DMA controller operation"
|
||||
description: 'Ethernet: DMA controller operation'
|
||||
items:
|
||||
- name: DMABMR
|
||||
description: Ethernet DMA bus mode register
|
||||
@ -74,7 +73,7 @@ block/ETHERNET_DMA:
|
||||
access: Read
|
||||
fieldset: DMACHRBAR
|
||||
block/ETHERNET_MAC:
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
items:
|
||||
- name: MACCR
|
||||
description: Ethernet MAC configuration register
|
||||
@ -212,7 +211,7 @@ block/ETHERNET_MAC:
|
||||
access: Read
|
||||
fieldset: MMCRGUFCR
|
||||
block/ETHERNET_PTP:
|
||||
description: "Ethernet: Precision time protocol"
|
||||
description: 'Ethernet: Precision time protocol'
|
||||
items:
|
||||
- name: PTPTSCR
|
||||
description: Ethernet PTP time stamp control register
|
||||
@ -618,7 +617,7 @@ fieldset/MACA0LR:
|
||||
description: Ethernet MAC address 0 low register
|
||||
fields:
|
||||
- name: MACA0L
|
||||
description: "0"
|
||||
description: '0'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACA1HR:
|
||||
@ -1332,7 +1331,7 @@ fieldset/PTPTTHR:
|
||||
description: Ethernet PTP target time high register
|
||||
fields:
|
||||
- name: TTSH
|
||||
description: "0"
|
||||
description: '0'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PTPTTLR:
|
||||
@ -1373,16 +1372,16 @@ enum/BL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: BL10
|
||||
description: "For retransmission n, wait up to 2^min(n, 10) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 10) time slots
|
||||
value: 0
|
||||
- name: BL8
|
||||
description: "For retransmission n, wait up to 2^min(n, 8) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 8) time slots
|
||||
value: 1
|
||||
- name: BL4
|
||||
description: "For retransmission n, wait up to 2^min(n, 4) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 4) time slots
|
||||
value: 2
|
||||
- name: BL1
|
||||
description: "For retransmission n, wait up to 2^min(n, 1) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 1) time slots
|
||||
value: 3
|
||||
enum/CR:
|
||||
bit_size: 3
|
||||
@ -1430,7 +1429,7 @@ enum/DA:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: RoundRobin
|
||||
description: "Round-robin with Rx:Tx priority given by PM"
|
||||
description: Round-robin with Rx:Tx priority given by PM
|
||||
value: 0
|
||||
- name: RxPriority
|
||||
description: Rx has priority over Tx
|
||||
@ -1493,10 +1492,10 @@ enum/FCB:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: DisableBackPressure
|
||||
description: "In half duplex only, deasserts back pressure"
|
||||
description: In half duplex only, deasserts back pressure
|
||||
value: 0
|
||||
- name: PauseOrBackPressure
|
||||
description: "In full duplex, initiate a Pause control frame. In half duplex, assert back pressure"
|
||||
description: In full duplex, initiate a Pause control frame. In half duplex, assert back pressure
|
||||
value: 1
|
||||
enum/FEF:
|
||||
bit_size: 1
|
||||
@ -1562,10 +1561,10 @@ enum/HPF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HashOnly
|
||||
description: "If HM or HU is set, only frames that match the Hash filter are passed"
|
||||
description: If HM or HU is set, only frames that match the Hash filter are passed
|
||||
value: 0
|
||||
- name: HashOrPerfect
|
||||
description: "If HM or HU is set, frames that match either the perfect filter or the hash filter are passed"
|
||||
description: If HM or HU is set, frames that match either the perfect filter or the hash filter are passed
|
||||
value: 1
|
||||
enum/HU:
|
||||
bit_size: 1
|
||||
@ -1616,10 +1615,10 @@ enum/JD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: "Jabber enabled, transmit frames up to 2048 bytes"
|
||||
description: Jabber enabled, transmit frames up to 2048 bytes
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: "Jabber disabled, transmit frames up to 16384 bytes"
|
||||
description: Jabber disabled, transmit frames up to 16384 bytes
|
||||
value: 1
|
||||
enum/LM:
|
||||
bit_size: 1
|
||||
@ -1769,16 +1768,16 @@ enum/PriorityRxOverTx:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: OneToOne
|
||||
description: "RxDMA priority over TxDMA is 1:1"
|
||||
description: RxDMA priority over TxDMA is 1:1
|
||||
value: 0
|
||||
- name: TwoToOne
|
||||
description: "RxDMA priority over TxDMA is 2:1"
|
||||
description: RxDMA priority over TxDMA is 2:1
|
||||
value: 1
|
||||
- name: ThreeToOne
|
||||
description: "RxDMA priority over TxDMA is 3:1"
|
||||
description: RxDMA priority over TxDMA is 3:1
|
||||
value: 2
|
||||
- name: FourToOne
|
||||
description: "RxDMA priority over TxDMA is 4:1"
|
||||
description: RxDMA priority over TxDMA is 4:1
|
||||
value: 3
|
||||
enum/RA:
|
||||
bit_size: 1
|
||||
@ -1883,25 +1882,25 @@ enum/RPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stopped
|
||||
description: "Stopped, reset or Stop Receive command issued"
|
||||
description: Stopped, reset or Stop Receive command issued
|
||||
value: 0
|
||||
- name: RunningFetching
|
||||
description: "Running, fetching receive transfer descriptor"
|
||||
description: Running, fetching receive transfer descriptor
|
||||
value: 1
|
||||
- name: RunningWaiting
|
||||
description: "Running, waiting for receive packet"
|
||||
description: Running, waiting for receive packet
|
||||
value: 3
|
||||
- name: Suspended
|
||||
description: "Suspended, receive descriptor unavailable"
|
||||
description: Suspended, receive descriptor unavailable
|
||||
value: 4
|
||||
- name: RunningWriting
|
||||
description: "Running, writing data to host memory buffer"
|
||||
description: Running, writing data to host memory buffer
|
||||
value: 7
|
||||
enum/RSF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: CutThrough
|
||||
description: "Rx FIFO operates in cut-through mode, subject to RTC bits"
|
||||
description: Rx FIFO operates in cut-through mode, subject to RTC bits
|
||||
value: 0
|
||||
- name: StoreForward
|
||||
description: Frames are read from Rx FIFO after complete frame has been written
|
||||
@ -1952,10 +1951,10 @@ enum/TFCE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "In full duplex, flow control is disabled. In half duplex, back pressure is disabled"
|
||||
description: In full duplex, flow control is disabled. In half duplex, back pressure is disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "In full duplex, flow control is enabled. In half duplex, back pressure is enabled"
|
||||
description: In full duplex, flow control is enabled. In half duplex, back pressure is enabled
|
||||
value: 1
|
||||
enum/TGFM:
|
||||
bit_size: 1
|
||||
@ -1994,22 +1993,22 @@ enum/TPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stopped
|
||||
description: "Stopped, Reset or Stop Transmit command issued"
|
||||
description: Stopped, Reset or Stop Transmit command issued
|
||||
value: 0
|
||||
- name: RunningFetching
|
||||
description: "Running, fetching transmit transfer descriptor"
|
||||
description: Running, fetching transmit transfer descriptor
|
||||
value: 1
|
||||
- name: RunningWaiting
|
||||
description: "Running, waiting for status"
|
||||
description: Running, waiting for status
|
||||
value: 2
|
||||
- name: RunningReading
|
||||
description: "Running, reading data from host memory buffer"
|
||||
description: Running, reading data from host memory buffer
|
||||
value: 3
|
||||
- name: Suspended
|
||||
description: "Suspended, transmit descriptor unavailable or transmit buffer underflow"
|
||||
description: Suspended, transmit descriptor unavailable or transmit buffer underflow
|
||||
value: 6
|
||||
- name: Running
|
||||
description: "Running, closing transmit descriptor"
|
||||
description: Running, closing transmit descriptor
|
||||
value: 7
|
||||
enum/TSF:
|
||||
bit_size: 1
|
||||
@ -2063,7 +2062,7 @@ enum/UPFD:
|
||||
description: MAC detects only a Pause frame with the multicast address specified in the 802.3x standard
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "MAC additionally detects Pause frames with the station's unicast address"
|
||||
description: MAC additionally detects Pause frames with the station's unicast address
|
||||
value: 1
|
||||
enum/USP:
|
||||
bit_size: 1
|
||||
@ -2072,7 +2071,7 @@ enum/USP:
|
||||
description: PBL value used for both Rx and Tx DMA
|
||||
value: 0
|
||||
- name: Separate
|
||||
description: "RxDMA uses RDP value, TxDMA uses PBL value"
|
||||
description: RxDMA uses RDP value, TxDMA uses PBL value
|
||||
value: 1
|
||||
enum/VLANTC:
|
||||
bit_size: 1
|
||||
@ -2087,10 +2086,10 @@ enum/WD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: "Watchdog enabled, receive frames limited to 2048 bytes"
|
||||
description: Watchdog enabled, receive frames limited to 2048 bytes
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: "Watchdog disabled, receive frames may be up to to 16384 bytes"
|
||||
description: Watchdog disabled, receive frames may be up to to 16384 bytes
|
||||
value: 1
|
||||
enum/WFE:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,21 +1,20 @@
|
||||
---
|
||||
block/ETH:
|
||||
description: Ethernet Peripheral
|
||||
items:
|
||||
- name: ETHERNET_MAC
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
byte_offset: 0
|
||||
block: ETHERNET_MAC
|
||||
- name: ETHERNET_PTP
|
||||
description: "Ethernet: Precision Time Protocol (PTP)"
|
||||
description: 'Ethernet: Precision Time Protocol (PTP)'
|
||||
byte_offset: 1792
|
||||
block: ETHERNET_PTP
|
||||
- name: ETHERNET_DMA
|
||||
description: "Ethernet: DMA mode register (DMA)"
|
||||
description: 'Ethernet: DMA mode register (DMA)'
|
||||
byte_offset: 4096
|
||||
block: ETHERNET_DMA
|
||||
block/ETHERNET_DMA:
|
||||
description: "Ethernet: DMA controller operation"
|
||||
description: 'Ethernet: DMA controller operation'
|
||||
items:
|
||||
- name: DMABMR
|
||||
description: Ethernet DMA bus mode register
|
||||
@ -78,7 +77,7 @@ block/ETHERNET_DMA:
|
||||
access: Read
|
||||
fieldset: DMACHRBAR
|
||||
block/ETHERNET_MAC:
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
items:
|
||||
- name: MACCR
|
||||
description: Ethernet MAC configuration register
|
||||
@ -216,7 +215,7 @@ block/ETHERNET_MAC:
|
||||
access: Read
|
||||
fieldset: MMCRGUFCR
|
||||
block/ETHERNET_PTP:
|
||||
description: "Ethernet: Precision time protocol"
|
||||
description: 'Ethernet: Precision time protocol'
|
||||
items:
|
||||
- name: PTPTSCR
|
||||
description: Ethernet PTP time stamp control register
|
||||
@ -639,7 +638,7 @@ fieldset/MACA0LR:
|
||||
description: Ethernet MAC address 0 low register
|
||||
fields:
|
||||
- name: MACA0L
|
||||
description: "0"
|
||||
description: '0'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACA1HR:
|
||||
@ -1368,7 +1367,7 @@ fieldset/PTPTTHR:
|
||||
description: Ethernet PTP target time high register
|
||||
fields:
|
||||
- name: TTSH
|
||||
description: "0"
|
||||
description: '0'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PTPTTLR:
|
||||
@ -1409,16 +1408,16 @@ enum/BL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: BL10
|
||||
description: "For retransmission n, wait up to 2^min(n, 10) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 10) time slots
|
||||
value: 0
|
||||
- name: BL8
|
||||
description: "For retransmission n, wait up to 2^min(n, 8) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 8) time slots
|
||||
value: 1
|
||||
- name: BL4
|
||||
description: "For retransmission n, wait up to 2^min(n, 4) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 4) time slots
|
||||
value: 2
|
||||
- name: BL1
|
||||
description: "For retransmission n, wait up to 2^min(n, 1) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 1) time slots
|
||||
value: 3
|
||||
enum/CR:
|
||||
bit_size: 3
|
||||
@ -1475,7 +1474,7 @@ enum/DA:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: RoundRobin
|
||||
description: "Round-robin with Rx:Tx priority given by PM"
|
||||
description: Round-robin with Rx:Tx priority given by PM
|
||||
value: 0
|
||||
- name: RxPriority
|
||||
description: Rx has priority over Tx
|
||||
@ -1532,7 +1531,7 @@ enum/EDFE:
|
||||
description: Normal descriptor format
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload"
|
||||
description: Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload
|
||||
value: 1
|
||||
enum/FB:
|
||||
bit_size: 1
|
||||
@ -1547,10 +1546,10 @@ enum/FCB:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: DisableBackPressure
|
||||
description: "In half duplex only, deasserts back pressure"
|
||||
description: In half duplex only, deasserts back pressure
|
||||
value: 0
|
||||
- name: PauseOrBackPressure
|
||||
description: "In full duplex, initiate a Pause control frame. In half duplex, assert back pressure"
|
||||
description: In full duplex, initiate a Pause control frame. In half duplex, assert back pressure
|
||||
value: 1
|
||||
enum/FEF:
|
||||
bit_size: 1
|
||||
@ -1616,10 +1615,10 @@ enum/HPF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HashOnly
|
||||
description: "If HM or HU is set, only frames that match the Hash filter are passed"
|
||||
description: If HM or HU is set, only frames that match the Hash filter are passed
|
||||
value: 0
|
||||
- name: HashOrPerfect
|
||||
description: "If HM or HU is set, frames that match either the perfect filter or the hash filter are passed"
|
||||
description: If HM or HU is set, frames that match either the perfect filter or the hash filter are passed
|
||||
value: 1
|
||||
enum/HU:
|
||||
bit_size: 1
|
||||
@ -1670,10 +1669,10 @@ enum/JD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: "Jabber enabled, transmit frames up to 2048 bytes"
|
||||
description: Jabber enabled, transmit frames up to 2048 bytes
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: "Jabber disabled, transmit frames up to 16384 bytes"
|
||||
description: Jabber disabled, transmit frames up to 16384 bytes
|
||||
value: 1
|
||||
enum/LM:
|
||||
bit_size: 1
|
||||
@ -1709,7 +1708,7 @@ enum/MB:
|
||||
description: Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below
|
||||
value: 0
|
||||
- name: Mixed
|
||||
description: "If FB is low, start all bursts greater than 16 with INCR (undefined burst)"
|
||||
description: If FB is low, start all bursts greater than 16 with INCR (undefined burst)
|
||||
value: 1
|
||||
enum/MB_progress:
|
||||
bit_size: 1
|
||||
@ -1730,10 +1729,10 @@ enum/MCFHP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: AlmostHalf
|
||||
description: "When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0"
|
||||
description: When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0
|
||||
value: 0
|
||||
- name: AlmostFull
|
||||
description: "When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0"
|
||||
description: When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0
|
||||
value: 1
|
||||
enum/MCP:
|
||||
bit_size: 1
|
||||
@ -1847,16 +1846,16 @@ enum/PriorityRxOverTx:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: OneToOne
|
||||
description: "RxDMA priority over TxDMA is 1:1"
|
||||
description: RxDMA priority over TxDMA is 1:1
|
||||
value: 0
|
||||
- name: TwoToOne
|
||||
description: "RxDMA priority over TxDMA is 2:1"
|
||||
description: RxDMA priority over TxDMA is 2:1
|
||||
value: 1
|
||||
- name: ThreeToOne
|
||||
description: "RxDMA priority over TxDMA is 3:1"
|
||||
description: RxDMA priority over TxDMA is 3:1
|
||||
value: 2
|
||||
- name: FourToOne
|
||||
description: "RxDMA priority over TxDMA is 4:1"
|
||||
description: RxDMA priority over TxDMA is 4:1
|
||||
value: 3
|
||||
enum/RA:
|
||||
bit_size: 1
|
||||
@ -1961,25 +1960,25 @@ enum/RPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stopped
|
||||
description: "Stopped, reset or Stop Receive command issued"
|
||||
description: Stopped, reset or Stop Receive command issued
|
||||
value: 0
|
||||
- name: RunningFetching
|
||||
description: "Running, fetching receive transfer descriptor"
|
||||
description: Running, fetching receive transfer descriptor
|
||||
value: 1
|
||||
- name: RunningWaiting
|
||||
description: "Running, waiting for receive packet"
|
||||
description: Running, waiting for receive packet
|
||||
value: 3
|
||||
- name: Suspended
|
||||
description: "Suspended, receive descriptor unavailable"
|
||||
description: Suspended, receive descriptor unavailable
|
||||
value: 4
|
||||
- name: RunningWriting
|
||||
description: "Running, writing data to host memory buffer"
|
||||
description: Running, writing data to host memory buffer
|
||||
value: 7
|
||||
enum/RSF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: CutThrough
|
||||
description: "Rx FIFO operates in cut-through mode, subject to RTC bits"
|
||||
description: Rx FIFO operates in cut-through mode, subject to RTC bits
|
||||
value: 0
|
||||
- name: StoreForward
|
||||
description: Frames are read from Rx FIFO after complete frame has been written
|
||||
@ -2030,10 +2029,10 @@ enum/TFCE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "In full duplex, flow control is disabled. In half duplex, back pressure is disabled"
|
||||
description: In full duplex, flow control is disabled. In half duplex, back pressure is disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "In full duplex, flow control is enabled. In half duplex, back pressure is enabled"
|
||||
description: In full duplex, flow control is enabled. In half duplex, back pressure is enabled
|
||||
value: 1
|
||||
enum/TGFM:
|
||||
bit_size: 1
|
||||
@ -2072,22 +2071,22 @@ enum/TPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stopped
|
||||
description: "Stopped, Reset or Stop Transmit command issued"
|
||||
description: Stopped, Reset or Stop Transmit command issued
|
||||
value: 0
|
||||
- name: RunningFetching
|
||||
description: "Running, fetching transmit transfer descriptor"
|
||||
description: Running, fetching transmit transfer descriptor
|
||||
value: 1
|
||||
- name: RunningWaiting
|
||||
description: "Running, waiting for status"
|
||||
description: Running, waiting for status
|
||||
value: 2
|
||||
- name: RunningReading
|
||||
description: "Running, reading data from host memory buffer"
|
||||
description: Running, reading data from host memory buffer
|
||||
value: 3
|
||||
- name: Suspended
|
||||
description: "Suspended, transmit descriptor unavailable or transmit buffer underflow"
|
||||
description: Suspended, transmit descriptor unavailable or transmit buffer underflow
|
||||
value: 6
|
||||
- name: Running
|
||||
description: "Running, closing transmit descriptor"
|
||||
description: Running, closing transmit descriptor
|
||||
value: 7
|
||||
enum/TSF:
|
||||
bit_size: 1
|
||||
@ -2141,7 +2140,7 @@ enum/UPFD:
|
||||
description: MAC detects only a Pause frame with the multicast address specified in the 802.3x standard
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "MAC additionally detects Pause frames with the station's unicast address"
|
||||
description: MAC additionally detects Pause frames with the station's unicast address
|
||||
value: 1
|
||||
enum/USP:
|
||||
bit_size: 1
|
||||
@ -2150,7 +2149,7 @@ enum/USP:
|
||||
description: PBL value used for both Rx and Tx DMA
|
||||
value: 0
|
||||
- name: Separate
|
||||
description: "RxDMA uses RDP value, TxDMA uses PBL value"
|
||||
description: RxDMA uses RDP value, TxDMA uses PBL value
|
||||
value: 1
|
||||
enum/VLANTC:
|
||||
bit_size: 1
|
||||
@ -2165,10 +2164,10 @@ enum/WD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: "Watchdog enabled, receive frames limited to 2048 bytes"
|
||||
description: Watchdog enabled, receive frames limited to 2048 bytes
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: "Watchdog disabled, receive frames may be up to to 16384 bytes"
|
||||
description: Watchdog disabled, receive frames may be up to to 16384 bytes
|
||||
value: 1
|
||||
enum/WFE:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,21 +1,20 @@
|
||||
---
|
||||
block/ETH:
|
||||
description: Ethernet Peripheral
|
||||
items:
|
||||
- name: ETHERNET_MAC
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
byte_offset: 0
|
||||
block: ETHERNET_MAC
|
||||
- name: ETHERNET_PTP
|
||||
description: "Ethernet: Precision Time Protocol (PTP)"
|
||||
description: 'Ethernet: Precision Time Protocol (PTP)'
|
||||
byte_offset: 1792
|
||||
block: ETHERNET_PTP
|
||||
- name: ETHERNET_DMA
|
||||
description: "Ethernet: DMA mode register (DMA)"
|
||||
description: 'Ethernet: DMA mode register (DMA)'
|
||||
byte_offset: 4096
|
||||
block: ETHERNET_DMA
|
||||
block/ETHERNET_DMA:
|
||||
description: "Ethernet: DMA controller operation"
|
||||
description: 'Ethernet: DMA controller operation'
|
||||
items:
|
||||
- name: DMABMR
|
||||
description: Ethernet DMA bus mode register
|
||||
@ -78,7 +77,7 @@ block/ETHERNET_DMA:
|
||||
access: Read
|
||||
fieldset: DMACHRBAR
|
||||
block/ETHERNET_MAC:
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
items:
|
||||
- name: MACCR
|
||||
description: Ethernet MAC configuration register
|
||||
@ -216,7 +215,7 @@ block/ETHERNET_MAC:
|
||||
access: Read
|
||||
fieldset: MMCRGUFCR
|
||||
block/ETHERNET_PTP:
|
||||
description: "Ethernet: Precision time protocol"
|
||||
description: 'Ethernet: Precision time protocol'
|
||||
items:
|
||||
- name: PTPTSCR
|
||||
description: Ethernet PTP time stamp control register
|
||||
@ -639,7 +638,7 @@ fieldset/MACA0LR:
|
||||
description: Ethernet MAC address 0 low register
|
||||
fields:
|
||||
- name: MACA0L
|
||||
description: "0"
|
||||
description: '0'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACA1HR:
|
||||
@ -1368,7 +1367,7 @@ fieldset/PTPTTHR:
|
||||
description: Ethernet PTP target time high register
|
||||
fields:
|
||||
- name: TTSH
|
||||
description: "0"
|
||||
description: '0'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/PTPTTLR:
|
||||
@ -1409,16 +1408,16 @@ enum/BL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: BL10
|
||||
description: "For retransmission n, wait up to 2^min(n, 10) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 10) time slots
|
||||
value: 0
|
||||
- name: BL8
|
||||
description: "For retransmission n, wait up to 2^min(n, 8) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 8) time slots
|
||||
value: 1
|
||||
- name: BL4
|
||||
description: "For retransmission n, wait up to 2^min(n, 4) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 4) time slots
|
||||
value: 2
|
||||
- name: BL1
|
||||
description: "For retransmission n, wait up to 2^min(n, 1) time slots"
|
||||
description: For retransmission n, wait up to 2^min(n, 1) time slots
|
||||
value: 3
|
||||
enum/CR:
|
||||
bit_size: 3
|
||||
@ -1475,7 +1474,7 @@ enum/DA:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: RoundRobin
|
||||
description: "Round-robin with Rx:Tx priority given by PM"
|
||||
description: Round-robin with Rx:Tx priority given by PM
|
||||
value: 0
|
||||
- name: RxPriority
|
||||
description: Rx has priority over Tx
|
||||
@ -1532,7 +1531,7 @@ enum/EDFE:
|
||||
description: Normal descriptor format
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload"
|
||||
description: Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload
|
||||
value: 1
|
||||
enum/FB:
|
||||
bit_size: 1
|
||||
@ -1547,10 +1546,10 @@ enum/FCB:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: DisableBackPressure
|
||||
description: "In half duplex only, deasserts back pressure"
|
||||
description: In half duplex only, deasserts back pressure
|
||||
value: 0
|
||||
- name: PauseOrBackPressure
|
||||
description: "In full duplex, initiate a Pause control frame. In half duplex, assert back pressure"
|
||||
description: In full duplex, initiate a Pause control frame. In half duplex, assert back pressure
|
||||
value: 1
|
||||
enum/FEF:
|
||||
bit_size: 1
|
||||
@ -1616,10 +1615,10 @@ enum/HPF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HashOnly
|
||||
description: "If HM or HU is set, only frames that match the Hash filter are passed"
|
||||
description: If HM or HU is set, only frames that match the Hash filter are passed
|
||||
value: 0
|
||||
- name: HashOrPerfect
|
||||
description: "If HM or HU is set, frames that match either the perfect filter or the hash filter are passed"
|
||||
description: If HM or HU is set, frames that match either the perfect filter or the hash filter are passed
|
||||
value: 1
|
||||
enum/HU:
|
||||
bit_size: 1
|
||||
@ -1670,10 +1669,10 @@ enum/JD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: "Jabber enabled, transmit frames up to 2048 bytes"
|
||||
description: Jabber enabled, transmit frames up to 2048 bytes
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: "Jabber disabled, transmit frames up to 16384 bytes"
|
||||
description: Jabber disabled, transmit frames up to 16384 bytes
|
||||
value: 1
|
||||
enum/LM:
|
||||
bit_size: 1
|
||||
@ -1709,7 +1708,7 @@ enum/MB:
|
||||
description: Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below
|
||||
value: 0
|
||||
- name: Mixed
|
||||
description: "If FB is low, start all bursts greater than 16 with INCR (undefined burst)"
|
||||
description: If FB is low, start all bursts greater than 16 with INCR (undefined burst)
|
||||
value: 1
|
||||
enum/MB_progress:
|
||||
bit_size: 1
|
||||
@ -1730,10 +1729,10 @@ enum/MCFHP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: AlmostHalf
|
||||
description: "When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0"
|
||||
description: When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0
|
||||
value: 0
|
||||
- name: AlmostFull
|
||||
description: "When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0"
|
||||
description: When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0
|
||||
value: 1
|
||||
enum/MCP:
|
||||
bit_size: 1
|
||||
@ -1847,16 +1846,16 @@ enum/PriorityRxOverTx:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: OneToOne
|
||||
description: "RxDMA priority over TxDMA is 1:1"
|
||||
description: RxDMA priority over TxDMA is 1:1
|
||||
value: 0
|
||||
- name: TwoToOne
|
||||
description: "RxDMA priority over TxDMA is 2:1"
|
||||
description: RxDMA priority over TxDMA is 2:1
|
||||
value: 1
|
||||
- name: ThreeToOne
|
||||
description: "RxDMA priority over TxDMA is 3:1"
|
||||
description: RxDMA priority over TxDMA is 3:1
|
||||
value: 2
|
||||
- name: FourToOne
|
||||
description: "RxDMA priority over TxDMA is 4:1"
|
||||
description: RxDMA priority over TxDMA is 4:1
|
||||
value: 3
|
||||
enum/RA:
|
||||
bit_size: 1
|
||||
@ -1961,25 +1960,25 @@ enum/RPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stopped
|
||||
description: "Stopped, reset or Stop Receive command issued"
|
||||
description: Stopped, reset or Stop Receive command issued
|
||||
value: 0
|
||||
- name: RunningFetching
|
||||
description: "Running, fetching receive transfer descriptor"
|
||||
description: Running, fetching receive transfer descriptor
|
||||
value: 1
|
||||
- name: RunningWaiting
|
||||
description: "Running, waiting for receive packet"
|
||||
description: Running, waiting for receive packet
|
||||
value: 3
|
||||
- name: Suspended
|
||||
description: "Suspended, receive descriptor unavailable"
|
||||
description: Suspended, receive descriptor unavailable
|
||||
value: 4
|
||||
- name: RunningWriting
|
||||
description: "Running, writing data to host memory buffer"
|
||||
description: Running, writing data to host memory buffer
|
||||
value: 7
|
||||
enum/RSF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: CutThrough
|
||||
description: "Rx FIFO operates in cut-through mode, subject to RTC bits"
|
||||
description: Rx FIFO operates in cut-through mode, subject to RTC bits
|
||||
value: 0
|
||||
- name: StoreForward
|
||||
description: Frames are read from Rx FIFO after complete frame has been written
|
||||
@ -2030,10 +2029,10 @@ enum/TFCE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "In full duplex, flow control is disabled. In half duplex, back pressure is disabled"
|
||||
description: In full duplex, flow control is disabled. In half duplex, back pressure is disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "In full duplex, flow control is enabled. In half duplex, back pressure is enabled"
|
||||
description: In full duplex, flow control is enabled. In half duplex, back pressure is enabled
|
||||
value: 1
|
||||
enum/TGFM:
|
||||
bit_size: 1
|
||||
@ -2072,22 +2071,22 @@ enum/TPS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Stopped
|
||||
description: "Stopped, Reset or Stop Transmit command issued"
|
||||
description: Stopped, Reset or Stop Transmit command issued
|
||||
value: 0
|
||||
- name: RunningFetching
|
||||
description: "Running, fetching transmit transfer descriptor"
|
||||
description: Running, fetching transmit transfer descriptor
|
||||
value: 1
|
||||
- name: RunningWaiting
|
||||
description: "Running, waiting for status"
|
||||
description: Running, waiting for status
|
||||
value: 2
|
||||
- name: RunningReading
|
||||
description: "Running, reading data from host memory buffer"
|
||||
description: Running, reading data from host memory buffer
|
||||
value: 3
|
||||
- name: Suspended
|
||||
description: "Suspended, transmit descriptor unavailable or transmit buffer underflow"
|
||||
description: Suspended, transmit descriptor unavailable or transmit buffer underflow
|
||||
value: 6
|
||||
- name: Running
|
||||
description: "Running, closing transmit descriptor"
|
||||
description: Running, closing transmit descriptor
|
||||
value: 7
|
||||
enum/TSF:
|
||||
bit_size: 1
|
||||
@ -2141,7 +2140,7 @@ enum/UPFD:
|
||||
description: MAC detects only a Pause frame with the multicast address specified in the 802.3x standard
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "MAC additionally detects Pause frames with the station's unicast address"
|
||||
description: MAC additionally detects Pause frames with the station's unicast address
|
||||
value: 1
|
||||
enum/USP:
|
||||
bit_size: 1
|
||||
@ -2150,7 +2149,7 @@ enum/USP:
|
||||
description: PBL value used for both Rx and Tx DMA
|
||||
value: 0
|
||||
- name: Separate
|
||||
description: "RxDMA uses RDP value, TxDMA uses PBL value"
|
||||
description: RxDMA uses RDP value, TxDMA uses PBL value
|
||||
value: 1
|
||||
enum/VLANTC:
|
||||
bit_size: 1
|
||||
@ -2165,10 +2164,10 @@ enum/WD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Enabled
|
||||
description: "Watchdog enabled, receive frames limited to 2048 bytes"
|
||||
description: Watchdog enabled, receive frames limited to 2048 bytes
|
||||
value: 0
|
||||
- name: Disabled
|
||||
description: "Watchdog disabled, receive frames may be up to to 16384 bytes"
|
||||
description: Watchdog disabled, receive frames may be up to to 16384 bytes
|
||||
value: 1
|
||||
enum/WFE:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,21 +1,20 @@
|
||||
---
|
||||
block/ETH:
|
||||
description: Ethernet Peripheral
|
||||
items:
|
||||
- name: ETHERNET_MAC
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
byte_offset: 0
|
||||
block: ETHERNET_MAC
|
||||
- name: ETHERNET_MTL
|
||||
description: "Ethernet: MTL mode register (MTL)"
|
||||
description: 'Ethernet: MTL mode register (MTL)'
|
||||
byte_offset: 3072
|
||||
block: ETHERNET_MTL
|
||||
- name: ETHERNET_DMA
|
||||
description: "Ethernet: DMA mode register (DMA)"
|
||||
description: 'Ethernet: DMA mode register (DMA)'
|
||||
byte_offset: 4096
|
||||
block: ETHERNET_DMA
|
||||
block/ETHERNET_DMA:
|
||||
description: "Ethernet: DMA mode register (DMA)"
|
||||
description: 'Ethernet: DMA mode register (DMA)'
|
||||
items:
|
||||
- name: DMAMR
|
||||
description: DMA mode register
|
||||
@ -109,7 +108,7 @@ block/ETHERNET_DMA:
|
||||
access: Read
|
||||
fieldset: DMACMFCR
|
||||
block/ETHERNET_MAC:
|
||||
description: "Ethernet: media access control (MAC)"
|
||||
description: 'Ethernet: media access control (MAC)'
|
||||
items:
|
||||
- name: MACCR
|
||||
description: Operating mode configuration register
|
||||
@ -497,7 +496,7 @@ block/ETHERNET_MAC:
|
||||
byte_offset: 3024
|
||||
fieldset: MACLMIR
|
||||
block/ETHERNET_MTL:
|
||||
description: "Ethernet: MTL mode register (MTL)"
|
||||
description: 'Ethernet: MTL mode register (MTL)'
|
||||
items:
|
||||
- name: MTLOMR
|
||||
description: Operating mode Register
|
||||
@ -882,7 +881,7 @@ fieldset/MACA0HR:
|
||||
description: Address 0 high register
|
||||
fields:
|
||||
- name: ADDRHI
|
||||
description: "MAC Address0[47:32]"
|
||||
description: MAC Address0[47:32]
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: AE
|
||||
@ -893,14 +892,14 @@ fieldset/MACA0LR:
|
||||
description: Address 0 low register
|
||||
fields:
|
||||
- name: ADDRLO
|
||||
description: "MAC Address 0 [31:0]"
|
||||
description: MAC Address 0 [31:0]
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACA1HR:
|
||||
description: Address 1 high register
|
||||
fields:
|
||||
- name: ADDRHI
|
||||
description: "MAC Address1 [47:32]"
|
||||
description: MAC Address1 [47:32]
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: MBC
|
||||
@ -919,14 +918,14 @@ fieldset/MACA1LR:
|
||||
description: Address 1 low register
|
||||
fields:
|
||||
- name: ADDRLO
|
||||
description: "MAC Address 1 [31:0]"
|
||||
description: MAC Address 1 [31:0]
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACA2HR:
|
||||
description: Address 2 high register
|
||||
fields:
|
||||
- name: ADDRHI
|
||||
description: "MAC Address2 [47:32]"
|
||||
description: MAC Address2 [47:32]
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: MBC
|
||||
@ -945,14 +944,14 @@ fieldset/MACA2LR:
|
||||
description: Address 2 low register
|
||||
fields:
|
||||
- name: ADDRLO
|
||||
description: "MAC Address 2 [31:0]"
|
||||
description: MAC Address 2 [31:0]
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACA3HR:
|
||||
description: Address 3 high register
|
||||
fields:
|
||||
- name: ADDRHI
|
||||
description: "MAC Address3 [47:32]"
|
||||
description: MAC Address3 [47:32]
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: MBC
|
||||
@ -971,7 +970,7 @@ fieldset/MACA3LR:
|
||||
description: Address 3 low register
|
||||
fields:
|
||||
- name: ADDRLO
|
||||
description: "MAC Address 3 [31:0]"
|
||||
description: MAC Address 3 [31:0]
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/MACACR:
|
||||
@ -1791,7 +1790,7 @@ fieldset/MACPPSCR:
|
||||
description: PPS control register
|
||||
fields:
|
||||
- name: PPSCTRL
|
||||
description: "Flexible PPS Output (ptp_pps_o[0]) Control or PPSCTRL PPS Output Frequency Control if PPSEN0 is cleared"
|
||||
description: Flexible PPS Output (ptp_pps_o[0]) Control or PPSCTRL PPS Output Frequency Control if PPSEN0 is cleared
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: PPSEN0
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -69,7 +68,7 @@ fieldset/EXTICR:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -69,7 +68,7 @@ fieldset/EXTICR:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: Extended interrupt and event controller
|
||||
items:
|
||||
@ -87,7 +86,7 @@ fieldset/EXTI:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: Extended interrupt and event controller
|
||||
items:
|
||||
@ -76,7 +75,7 @@ fieldset/EXTI:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -45,7 +44,7 @@ block/EXTI:
|
||||
byte_offset: 136
|
||||
fieldset: LINES
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -87,7 +86,7 @@ fieldset/EXTICR:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -87,7 +86,7 @@ fieldset/EXTICR:
|
||||
len: 4
|
||||
stride: 8
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -45,7 +44,7 @@ block/EXTI:
|
||||
byte_offset: 20
|
||||
fieldset: LINES
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/CPU:
|
||||
description: CPU-specific registers
|
||||
items:
|
||||
@ -55,7 +54,7 @@ block/EXTI:
|
||||
byte_offset: 128
|
||||
block: CPU
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/EXTI:
|
||||
description: External interrupt/event controller
|
||||
items:
|
||||
@ -45,7 +44,7 @@ block/EXTI:
|
||||
byte_offset: 132
|
||||
fieldset: LINES
|
||||
fieldset/LINES:
|
||||
description: "EXTI lines register, 1 bit per line"
|
||||
description: EXTI lines register, 1 bit per line
|
||||
fields:
|
||||
- name: LINE
|
||||
description: EXTI line
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
@ -270,19 +269,19 @@ enum/nBOOT0:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "When BOOT_SEL is cleared, select the device boot mode"
|
||||
description: When BOOT_SEL is cleared, select the device boot mode
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "When BOOT_SEL is cleared, select the device boot mode"
|
||||
description: When BOOT_SEL is cleared, select the device boot mode
|
||||
value: 1
|
||||
enum/nBOOT1:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: "Together with BOOT0, select the device boot mode"
|
||||
description: Together with BOOT0, select the device boot mode
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: "Together with BOOT0, select the device boot mode"
|
||||
description: Together with BOOT0, select the device boot mode
|
||||
value: 1
|
||||
enum/nRST_STDBY:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH
|
||||
items:
|
||||
@ -184,11 +183,11 @@ enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: "Zero wait state, if 0 < SYSCLK≤ 24 MHz"
|
||||
description: Zero wait state, if 0 < SYSCLK≤ 24 MHz
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: "One wait state, if 24 MHz < SYSCLK ≤ 48 MHz"
|
||||
description: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: "Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz"
|
||||
description: Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz
|
||||
value: 2
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
@ -208,13 +207,13 @@ enum/LATENCY:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: WS0
|
||||
description: "0 wait states, if 0 < HCLK <= 24 MHz"
|
||||
description: 0 wait states, if 0 < HCLK <= 24 MHz
|
||||
value: 0
|
||||
- name: WS1
|
||||
description: "1 wait state, if 24 < HCLK <= 48 MHz"
|
||||
description: 1 wait state, if 24 < HCLK <= 48 MHz
|
||||
value: 1
|
||||
- name: WS2
|
||||
description: "2 wait states, if 48 < HCLK <= 72 MHz"
|
||||
description: 2 wait states, if 48 < HCLK <= 72 MHz
|
||||
value: 2
|
||||
enum/RDPRT:
|
||||
bit_size: 2
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH address block description
|
||||
items:
|
||||
@ -281,7 +280,7 @@ fieldset/BOOTR:
|
||||
description: FLASH secure boot register
|
||||
fields:
|
||||
- name: SECBOOT_LOCK
|
||||
description: "A field locking the values of UBE, SWAP_ BANK, and SECBOOTADD setting."
|
||||
description: A field locking the values of UBE, SWAP_ BANK, and SECBOOTADD setting.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: BOOTR_SECBOOT_LOCK
|
||||
@ -421,7 +420,7 @@ fieldset/NSBOOTR:
|
||||
description: FLASH non-secure boot register
|
||||
fields:
|
||||
- name: NSBOOT_LOCK
|
||||
description: "A field locking the values of SWAP_ BANK, and NSBOOTADD settings."
|
||||
description: A field locking the values of SWAP_ BANK, and NSBOOTADD settings.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: NSBOOTR_NSBOOT_LOCK
|
||||
@ -711,7 +710,7 @@ fieldset/OPTSR:
|
||||
bit_size: 1
|
||||
enum: OPTSR_NRST_STDBY
|
||||
- name: PRODUCT_STATE
|
||||
description: "Life state code (based on Hamming 8,4). More information in Section<6F>7.6.11: Product state transitions."
|
||||
description: 'Life state code (based on Hamming 8,4). More information in Section<6F>7.6.11: Product state transitions.'
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: IO_VDD_HSLV
|
||||
@ -819,7 +818,7 @@ fieldset/SECBOOTR:
|
||||
description: FLASH secure boot register
|
||||
fields:
|
||||
- name: SECBOOT_LOCK
|
||||
description: "A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings."
|
||||
description: A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: SECBOOTR_SECBOOT_LOCK
|
||||
@ -1042,7 +1041,7 @@ enum/BOOTR_SECBOOT_LOCK:
|
||||
description: The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled).
|
||||
value: 180
|
||||
- name: B_0xC3
|
||||
description: "The BOOT_UBE, SWAP_ BANK and SECBOOTADD can still be modified following their individual rules."
|
||||
description: The BOOT_UBE, SWAP_ BANK and SECBOOTADD can still be modified following their individual rules.
|
||||
value: 195
|
||||
enum/CODE_OP:
|
||||
bit_size: 3
|
||||
@ -1129,10 +1128,10 @@ enum/OPTSR_BOR_LEV:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: B_0x1
|
||||
description: "BOR Level 2, the threshold level is medium (around 2.4 V)"
|
||||
description: BOR Level 2, the threshold level is medium (around 2.4 V)
|
||||
value: 1
|
||||
- name: B_0x2
|
||||
description: "BOR Level 3, the threshold level is high (around 2.7 V)"
|
||||
description: BOR Level 3, the threshold level is high (around 2.7 V)
|
||||
value: 2
|
||||
enum/OPTSR_IO_VDDIO_HSLV:
|
||||
bit_size: 1
|
||||
@ -1258,7 +1257,7 @@ enum/SECBOOTR_SECBOOT_LOCK:
|
||||
description: The BOOT_UBE and SECBOOTADD are frozen. SWAP_ BANK can only be modified with TZEN set to 0xC3 (disabled).
|
||||
value: 180
|
||||
- name: B_0xC3
|
||||
description: "The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules."
|
||||
description: The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules.
|
||||
value: 195
|
||||
enum/SECCR_BKSEL:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: FLASH address block description
|
||||
items:
|
||||
@ -165,7 +164,7 @@ fieldset/ECCCORR:
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: ECCCIE
|
||||
description: "ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation."
|
||||
description: ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation.
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: ECCC
|
||||
@ -239,7 +238,7 @@ fieldset/NSBOOTR:
|
||||
description: FLASH non-secure unique boot entry register
|
||||
fields:
|
||||
- name: NSBOOT_LOCK
|
||||
description: "A field locking the values of SWAP_BANK, and NSBOOTADD settings."
|
||||
description: A field locking the values of SWAP_BANK, and NSBOOTADD settings.
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
enum: NSBOOTR_NSBOOT_LOCK
|
||||
@ -469,7 +468,7 @@ fieldset/OPTSR:
|
||||
bit_size: 1
|
||||
enum: OPTSR_NRST_STDBY
|
||||
- name: PRODUCT_STATE
|
||||
description: "Life state code (based on Hamming 8,4). More information in ."
|
||||
description: Life state code (based on Hamming 8,4). More information in .
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: IO_VDD_HSLV
|
||||
@ -658,16 +657,16 @@ enum/OPTSR_BOR_LEV:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "BOR OFF, POR/PDR reset threshold level is applied"
|
||||
description: BOR OFF, POR/PDR reset threshold level is applied
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "BOR Level 1, the threshold level is low (around 2.1 V)"
|
||||
description: BOR Level 1, the threshold level is low (around 2.1 V)
|
||||
value: 1
|
||||
- name: B_0x2
|
||||
description: "BOR Level 2, the threshold level is medium (around 2.4 V)"
|
||||
description: BOR Level 2, the threshold level is medium (around 2.4 V)
|
||||
value: 2
|
||||
- name: B_0x3
|
||||
description: "BOR Level 3, the threshold level is high (around 2.7 V)"
|
||||
description: BOR Level 3, the threshold level is high (around 2.7 V)
|
||||
value: 3
|
||||
enum/OPTSR_IO_VDDIO_HSLV:
|
||||
bit_size: 1
|
||||
|
||||
@ -1,6 +1,5 @@
|
||||
---
|
||||
block/BANK:
|
||||
description: "Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R"
|
||||
description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R
|
||||
items:
|
||||
- name: KEYR
|
||||
description: FLASH key register for bank 1
|
||||
@ -70,7 +69,7 @@ block/FLASH:
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: BANK
|
||||
description: "Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R"
|
||||
description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R
|
||||
array:
|
||||
len: 2
|
||||
stride: 256
|
||||
|
||||
@ -1,6 +1,5 @@
|
||||
---
|
||||
block/BANK:
|
||||
description: "Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R"
|
||||
description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R
|
||||
items:
|
||||
- name: KEYR
|
||||
description: FLASH key register for bank 1
|
||||
@ -70,7 +69,7 @@ block/FLASH:
|
||||
byte_offset: 0
|
||||
fieldset: ACR
|
||||
- name: BANK
|
||||
description: "Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R"
|
||||
description: Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R
|
||||
array:
|
||||
len: 2
|
||||
stride: 256
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
@ -129,7 +128,7 @@ fieldset/PECR:
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: FIX
|
||||
description: "Fixed time data write for Byte, Half Word and Word programming"
|
||||
description: Fixed time data write for Byte, Half Word and Word programming
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ERASE
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
@ -139,7 +138,7 @@ fieldset/PECR:
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: FTDW
|
||||
description: "Fixed time data write for Byte, Half Word and Word programming"
|
||||
description: Fixed time data write for Byte, Half Word and Word programming
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: ERASE
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
@ -476,7 +475,7 @@ fieldset/OPTR:
|
||||
bit_size: 1
|
||||
enum: nRST_SHDW
|
||||
- name: SRAM1345_RST
|
||||
description: "SRAM1, SRAM3 and SRAM4 erase upon system reset"
|
||||
description: SRAM1, SRAM3 and SRAM4 erase upon system reset
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: IWDG_SW
|
||||
@ -3143,7 +3142,7 @@ enum/RDP:
|
||||
bit_size: 8
|
||||
variants:
|
||||
- name: B_0x55
|
||||
description: "Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1)"
|
||||
description: Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1)
|
||||
value: 85
|
||||
- name: B_0xAA
|
||||
description: Level 0 (readout protection not active)
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FLASH:
|
||||
description: Flash
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FMAC:
|
||||
description: Filter math accelerator
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FMC:
|
||||
description: Flexible memory controller
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FMC:
|
||||
description: Flexible memory controller
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FMC:
|
||||
description: Flexible memory controller
|
||||
items:
|
||||
@ -212,7 +211,7 @@ fieldset/BCR1:
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: BMAP
|
||||
description: "FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register."
|
||||
description: 'FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register.'
|
||||
bit_offset: 24
|
||||
bit_size: 2
|
||||
- name: FMCEN
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FSMC:
|
||||
description: Flexible static memory controller
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FSMC:
|
||||
description: Flexible static memory controller
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FSMC:
|
||||
description: Flexible static memory controller
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FSMC:
|
||||
description: Flexible static memory controller
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FSMC:
|
||||
description: Flexible static memory controller
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/FSMC:
|
||||
description: Flexible static memory controller
|
||||
items:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/Channel:
|
||||
items:
|
||||
- name: LBAR
|
||||
@ -80,11 +79,11 @@ fieldset/CH_BR1:
|
||||
description: GPDMA channel 15 alternate block register 1
|
||||
fields:
|
||||
- name: BNDT
|
||||
description: "block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued."
|
||||
description: 'block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued.'
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: BRC
|
||||
description: "Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer."
|
||||
description: 'Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer.'
|
||||
bit_offset: 16
|
||||
bit_size: 11
|
||||
- name: SDEC
|
||||
@ -98,12 +97,12 @@ fieldset/CH_BR1:
|
||||
bit_size: 1
|
||||
enum: CH_BR1_DEC
|
||||
- name: BRSDEC
|
||||
description: "Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer."
|
||||
description: 'Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer.'
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
enum: CH_BR1_DEC
|
||||
- name: BRDDEC
|
||||
description: "Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer."
|
||||
description: 'Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer.'
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
enum: CH_BR1_DEC
|
||||
@ -111,26 +110,26 @@ fieldset/CH_BR2:
|
||||
description: GPDMA channel 12 block register 2
|
||||
fields:
|
||||
- name: BRSAO
|
||||
description: "Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued."
|
||||
description: 'Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued.'
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: BRDAO
|
||||
description: "Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued."
|
||||
description: 'Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued.'
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/CH_CR:
|
||||
description: GPDMA channel 11 control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: "enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored."
|
||||
description: 'enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.'
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RESET
|
||||
description: "reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in )."
|
||||
description: 'reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in ).'
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: SUSP
|
||||
description: "suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in ."
|
||||
description: 'suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in .'
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TCIE
|
||||
@ -162,17 +161,17 @@ fieldset/CH_CR:
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: LSM
|
||||
description: "Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1."
|
||||
description: 'Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.'
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum: CH_CR_LSM
|
||||
- name: LAP
|
||||
description: "linked-list allocated port. This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1."
|
||||
description: 'linked-list allocated port. This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1.'
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
enum: CH_CR_LAP
|
||||
- name: PRIO
|
||||
description: "priority level of the channel x GPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1."
|
||||
description: 'priority level of the channel x GPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.'
|
||||
bit_offset: 22
|
||||
bit_size: 2
|
||||
enum: CH_CR_PRIO
|
||||
@ -218,54 +217,54 @@ fieldset/CH_LLR:
|
||||
description: GPDMA channel 15 alternate linked-list address register
|
||||
fields:
|
||||
- name: LA
|
||||
description: "pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored."
|
||||
description: 'pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.'
|
||||
bit_offset: 2
|
||||
bit_size: 14
|
||||
- name: ULL
|
||||
description: "Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer."
|
||||
description: Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer.
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: UB2
|
||||
description: "Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer."
|
||||
description: Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer.
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: UT3
|
||||
description: "Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer."
|
||||
description: Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer.
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: UDA
|
||||
description: "Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer."
|
||||
description: Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer.
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: USA
|
||||
description: "update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer."
|
||||
description: update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer.
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: UB1
|
||||
description: "Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer."
|
||||
description: Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer.
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: UT2
|
||||
description: "Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer."
|
||||
description: Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer.
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: UT1
|
||||
description: "Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer."
|
||||
description: Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer.
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/CH_SR:
|
||||
description: GPDMA channel 15 status register
|
||||
fields:
|
||||
- name: IDLEF
|
||||
description: "idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state)."
|
||||
description: idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TCF
|
||||
description: "transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0])."
|
||||
description: transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]).
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: HTF
|
||||
description: "half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination."
|
||||
description: half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination.
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: DTEF
|
||||
@ -289,111 +288,111 @@ fieldset/CH_SR:
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: FIFOL
|
||||
description: "monitored FIFO level. Number of available write beats in the FIFO, in units of the programmed destination data width (see CH[x].TR1.DDW[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to CH[x].BR1.BDNT[15:0] and CH[x].BR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (CH[x].SR.SUSPF = 1)."
|
||||
description: 'monitored FIFO level. Number of available write beats in the FIFO, in units of the programmed destination data width (see CH[x].TR1.DDW[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to CH[x].BR1.BDNT[15:0] and CH[x].BR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (CH[x].SR.SUSPF = 1).'
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
fieldset/CH_TR1:
|
||||
description: GPDMA channel 8 transfer register 1
|
||||
fields:
|
||||
- name: SDW
|
||||
description: "binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued."
|
||||
description: 'binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.'
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
enum: CH_TR1_DW
|
||||
- name: SINC
|
||||
description: "source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer."
|
||||
description: source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: SBL_1
|
||||
description: "source burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed."
|
||||
description: 'source burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed.'
|
||||
bit_offset: 4
|
||||
bit_size: 6
|
||||
- name: PAM
|
||||
description: "padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note:"
|
||||
description: 'padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note:'
|
||||
bit_offset: 11
|
||||
bit_size: 2
|
||||
enum: CH_TR1_PAM
|
||||
- name: SBX
|
||||
description: "source byte exchange within the unaligned half-word of each source word. If set, the two consecutive bytes within the unaligned half-word of each source word are exchanged. If the source data width is shorter than a word, this bit is ignored."
|
||||
description: source byte exchange within the unaligned half-word of each source word. If set, the two consecutive bytes within the unaligned half-word of each source word are exchanged. If the source data width is shorter than a word, this bit is ignored.
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: SAP
|
||||
description: "source allocated port. This bit is used to allocate the master port for the source transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1."
|
||||
description: 'source allocated port. This bit is used to allocate the master port for the source transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.'
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: CH_TR1_AP
|
||||
- name: SSEC
|
||||
description: "security attribute of the GPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure."
|
||||
description: 'security attribute of the GPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure.'
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: DDW
|
||||
description: "binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued."
|
||||
description: 'binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued.'
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: CH_TR1_DW
|
||||
- name: DINC
|
||||
description: "destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer."
|
||||
description: destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: DBL_1
|
||||
description: "destination burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed."
|
||||
description: 'destination burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed.'
|
||||
bit_offset: 20
|
||||
bit_size: 6
|
||||
- name: DBX
|
||||
description: "destination byte exchange. IF set, the two consecutive (post PAM) bytes are exchanged in each destination half-word. If the destination data size is a byte, this bit is ignored."
|
||||
description: destination byte exchange. IF set, the two consecutive (post PAM) bytes are exchanged in each destination half-word. If the destination data size is a byte, this bit is ignored.
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: DHX
|
||||
description: "destination half-word exchange. If set, e two consecutive (post PAM) half-words are exchanged in each destination word. If the destination data size is shorter than a word, this bit is ignored."
|
||||
description: destination half-word exchange. If set, e two consecutive (post PAM) half-words are exchanged in each destination word. If the destination data size is shorter than a word, this bit is ignored.
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: DAP
|
||||
description: "destination allocated port. This bit is used to allocate the master port for the destination transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1."
|
||||
description: 'destination allocated port. This bit is used to allocate the master port for the destination transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.'
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
enum: CH_TR1_AP
|
||||
- name: DSEC
|
||||
description: "security attribute of the GPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure."
|
||||
description: 'security attribute of the GPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure.'
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/CH_TR2:
|
||||
description: GPDMA channel 10 transfer register 2
|
||||
fields:
|
||||
- name: REQSEL
|
||||
description: "GPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting."
|
||||
description: GPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.
|
||||
bit_offset: 0
|
||||
bit_size: 7
|
||||
- name: SWREQ
|
||||
description: "software request. This bit is internally taken into account when CH[x].CR.EN is asserted."
|
||||
description: software request. This bit is internally taken into account when CH[x].CR.EN is asserted.
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: CH_TR2_SWREQ
|
||||
- name: DREQ
|
||||
description: "destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note:"
|
||||
description: 'destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note:'
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: CH_TR2_DREQ
|
||||
- name: BREQ
|
||||
description: "Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:"
|
||||
description: 'Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:'
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: CH_TR2_BREQ
|
||||
- name: TRIGM
|
||||
description: "trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger."
|
||||
description: 'trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger.'
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
enum: CH_TR2_TRIGM
|
||||
- name: TRIGSEL
|
||||
description: "trigger event input selection. These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00."
|
||||
description: trigger event input selection. These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00.
|
||||
bit_offset: 16
|
||||
bit_size: 6
|
||||
- name: TRIGPOL
|
||||
description: "trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]."
|
||||
description: trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
|
||||
bit_offset: 24
|
||||
bit_size: 2
|
||||
enum: CH_TR2_TRIGPOL
|
||||
- name: TCEM
|
||||
description: "transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1."
|
||||
description: 'transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.'
|
||||
bit_offset: 30
|
||||
bit_size: 2
|
||||
enum: CH_TR2_TCEM
|
||||
@ -401,11 +400,11 @@ fieldset/CH_TR3:
|
||||
description: GPDMA channel 14 transfer register 3
|
||||
fields:
|
||||
- name: SAO
|
||||
description: "source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied."
|
||||
description: 'source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied.'
|
||||
bit_offset: 0
|
||||
bit_size: 13
|
||||
- name: DAO
|
||||
description: "destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued."
|
||||
description: 'destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued.'
|
||||
bit_offset: 16
|
||||
bit_size: 13
|
||||
fieldset/MISR:
|
||||
@ -470,7 +469,7 @@ enum/CH_CR_LSM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: RunToCompletion
|
||||
description: "channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present."
|
||||
description: channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present.
|
||||
value: 0
|
||||
- name: LinkStep
|
||||
description: channel executed once for the current LLI
|
||||
@ -479,13 +478,13 @@ enum/CH_CR_PRIO:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: LowWithLowhWeight
|
||||
description: "low priority, low weight"
|
||||
description: low priority, low weight
|
||||
value: 0
|
||||
- name: LowWithMidWeight
|
||||
description: "low priority, mid weight"
|
||||
description: low priority, mid weight
|
||||
value: 1
|
||||
- name: LowWithHighWeight
|
||||
description: "low priority, high weight"
|
||||
description: low priority, high weight
|
||||
value: 2
|
||||
- name: High
|
||||
description: high priority
|
||||
@ -515,13 +514,17 @@ enum/CH_TR1_PAM:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: ZeroExtendOrLeftTruncate
|
||||
description: "If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width\nIf source is wider: source data is transferred as right aligned, left-truncated down to the destination data width"
|
||||
description: |-
|
||||
If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width
|
||||
If source is wider: source data is transferred as right aligned, left-truncated down to the destination data width
|
||||
value: 0
|
||||
- name: SignExtendOrRightTruncate
|
||||
description: "If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width\nIf source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width"
|
||||
description: |-
|
||||
If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width
|
||||
If source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width
|
||||
value: 1
|
||||
- name: Pack
|
||||
description: "source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination"
|
||||
description: source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination
|
||||
value: 2
|
||||
enum/CH_TR2_BREQ:
|
||||
bit_size: 1
|
||||
@ -545,40 +548,40 @@ enum/CH_TR2_SWREQ:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Hardware
|
||||
description: "no software request. The selected hardware request REQSEL[6:0] is taken into account."
|
||||
description: no software request. The selected hardware request REQSEL[6:0] is taken into account.
|
||||
value: 0
|
||||
- name: Software
|
||||
description: "software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored."
|
||||
description: software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.
|
||||
value: 1
|
||||
enum/CH_TR2_TCEM:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: EachBlock
|
||||
description: "at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block."
|
||||
description: 'at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.'
|
||||
value: 0
|
||||
- name: Each2DBlock
|
||||
description: "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block."
|
||||
description: channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block.
|
||||
value: 1
|
||||
- name: EachLinkedListItem
|
||||
description: "at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer."
|
||||
description: 'at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer.'
|
||||
value: 2
|
||||
- name: LastLinkedListItem
|
||||
description: "at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated."
|
||||
description: 'at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated.'
|
||||
value: 3
|
||||
enum/CH_TR2_TRIGM:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Block
|
||||
description: "at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0)."
|
||||
description: 'at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0).'
|
||||
value: 0
|
||||
- name: 2DBlock
|
||||
description: "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the"
|
||||
description: channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the
|
||||
value: 1
|
||||
- name: LinkedListItem
|
||||
description: "at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned."
|
||||
description: 'at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.'
|
||||
value: 2
|
||||
- name: Burst
|
||||
description: "at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger."
|
||||
description: 'at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger.'
|
||||
value: 3
|
||||
enum/CH_TR2_TRIGPOL:
|
||||
bit_size: 2
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/GPIO:
|
||||
description: General purpose I/O
|
||||
items:
|
||||
@ -71,7 +70,7 @@ fieldset/CR:
|
||||
stride: 4
|
||||
enum: MODE
|
||||
- name: CNF_IN
|
||||
description: "Port n configuration bits, for input mode"
|
||||
description: Port n configuration bits, for input mode
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
array:
|
||||
@ -79,7 +78,7 @@ fieldset/CR:
|
||||
stride: 4
|
||||
enum: CNF_IN
|
||||
- name: CNF_OUT
|
||||
description: "Port n configuration bits, for output mode"
|
||||
description: Port n configuration bits, for output mode
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
array:
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
---
|
||||
block/GPIO:
|
||||
description: General-purpose I/Os
|
||||
items:
|
||||
@ -37,14 +36,14 @@ block/GPIO:
|
||||
byte_offset: 28
|
||||
fieldset: LCKR
|
||||
- name: AFR
|
||||
description: "GPIO alternate function registers. The register described in the datasheet as AFRL is index 0 in this array, and AFRH is index 1. Note that when operating on AFRH, you need to subtract 8 from any operations on the field array it contains -- the alternate function for pin 9 is at index 1, for instance."
|
||||
description: GPIO alternate function registers. The register described in the datasheet as AFRL is index 0 in this array, and AFRH is index 1. Note that when operating on AFRH, you need to subtract 8 from any operations on the field array it contains -- the alternate function for pin 9 is at index 1, for instance.
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 32
|
||||
fieldset: AFR
|
||||
fieldset/AFR:
|
||||
description: "GPIO alternate function register. This contains an array of 8 fields, which correspond to pins 0-7 of the port (for AFRL) or pins 8-15 of the port (for AFRH)."
|
||||
description: GPIO alternate function register. This contains an array of 8 fields, which correspond to pins 0-7 of the port (for AFRL) or pins 8-15 of the port (for AFRH).
|
||||
fields:
|
||||
- name: AFR
|
||||
description: Alternate function selection for one of the pins controlled by this register (0-7).
|
||||
@ -231,7 +230,7 @@ enum/PUPDR:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Floating
|
||||
description: "No pull-up, pull-down"
|
||||
description: No pull-up, pull-down
|
||||
value: 0
|
||||
- name: PullUp
|
||||
description: Pull-up
|
||||
|
||||
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Load Diff
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user