make compile pass

data/registers/adc_f3_v1_1.yaml

@@ -232,10 +232,12 @@ fieldset/CR2:
       description: External event select for injected group
       bit_offset: 16
       bit_size: 4
+      enum: JEXTSEL
     - name: JEXTEN
       description: External trigger enable for injected channels
       bit_offset: 20
       bit_size: 2
+      enum: EXTEN
     - name: JSWSTART
       description: Start conversion of injected channels
       bit_offset: 22
@@ -244,10 +246,12 @@ fieldset/CR2:
       description: External event select for regular group
       bit_offset: 24
       bit_size: 4
+      enum: EXTSEL
     - name: EXTEN
       description: External trigger enable for regular channels
       bit_offset: 28
       bit_size: 2
+      enum: EXTEN
     - name: SWSTART
       description: Start conversion of regular channels
       bit_offset: 30
@@ -584,7 +588,7 @@ enum/DELS:
       description:  Delay 255 APB clock cycles after the conversion
       value: 7
 enum/EXTEN:
-  bit_size: 3
+  bit_size: 2
   variants:
     - name: DISABLED
       description: Trigger detection disabled
@@ -599,7 +603,7 @@ enum/EXTEN:
       description: Trigger detection on both edges
       value: 3
 enum/EXTSEL:
-  bit_size: 3
+  bit_size: 4
   variants:
     - name: TIM9_CC2
       description: Timer 9 CC2 event
@@ -638,7 +642,7 @@ enum/EXTSEL:
       description: External interrupt line 11
       value: 15
 enum/JEXTSEL:
-  bit_size: 3
+  bit_size: 4
   variants:
     - name: TIM9_CC1
       description: Timer 9 CC1 event

data/registers/adc_v4.yaml

@@ -740,7 +740,7 @@ enum/OVRMOD:
     description: Overwrite DR register when an overrun is detected
     value: 1
 enum/PCSEL:
-  bit_size: 20
+  bit_size: 1
   variants:
   - name: NotPreselected
     description: Input channel x is not pre-selected

data/registers/adf_v1.yaml

@@ -581,7 +581,7 @@ enum/SADST:
     value: 2
 enum/SCKSRC:
   description: Serial clock source. This bitfield is set and cleared by software. It is used to select the clock source of the serial interface.
-  bit_size: 1
+  bit_size: 2
   variants:
   - name: CCK0
     description: Serial clock source is CCK0.
@@ -589,6 +589,12 @@ enum/SCKSRC:
   - name: CCK1
     description: Serial clock source is CCK1.
     value: 1
+  - name: CKI0
+    description: Serial clock source is CCI0.
+    value: 2
+  - name: CKI1
+    description: Serial clock source is CCI1.
+    value: 3
 enum/SITFMOD:
   description: Serial interface mode. This bitfield is set and cleared by software. It is used to select the serial interface mode.
   bit_size: 2
@@ -607,14 +613,104 @@ enum/SITFMOD:
     value: 3
 enum/BSSEL:
   description: Bitstream selection. This bitfield is set and cleared by software. It is used to select the bitstream to be used by the DFLT0.
-  bit_size: 1
+  bit_size: 5
   variants:
-  - name: BSR
+  - name: BS0_R
-    description: bs0_r provided to DFLT0.
+    description: bsx_r provided to DFLTy (and SCDy).
     value: 0
-  - name: BSF
+  - name: BS0_F
-    description: bs0_f provided to DFLT0.
+    description: bsx_f provided to DFLTy (and SCDy).
     value: 1
+  - name: BS1_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 2
+  - name: BS1_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 3
+  - name: BS2_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 4
+  - name: BS2_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 5
+  - name: BS3_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 6
+  - name: BS3_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 7
+  - name: BS4_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 8
+  - name: BS4_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 9
+  - name: BS5_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 10
+  - name: BS5_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 11
+  - name: BS6_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 12
+  - name: BS6_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 13
+  - name: BS7_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 14
+  - name: BS7_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 15
+  - name: BS8_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 16
+  - name: BS8_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 17
+  - name: BS9_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 18
+  - name: BS9_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 19
+  - name: BS10_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 20
+  - name: BS10_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 21
+  - name: BS11_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 22
+  - name: BS11_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 23
+  - name: BS12_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 24
+  - name: BS12_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 25
+  - name: BS13_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 26
+  - name: BS13_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 27
+  - name: BS14_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 28
+  - name: BS14_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 29
+  - name: BS15_R
+    description: bsx_r provided to DFLTy (and SCDy).
+    value: 30
+  - name: BS15_F
+    description: bsx_f provided to DFLTy (and SCDy).
+    value: 31
 enum/DATSRC:
   description: Source data for the digital filter.
   bit_size: 2
@@ -774,5 +870,3 @@ enum/SNTHR:
   - name: NOISE PLUS 30_1
     description: Threshold is 30.1 dB higher than ANLVL
     value: 9
-
-

data/registers/flash_f4.yaml

@@ -31,7 +31,7 @@ fieldset/ACR:
   - name: LATENCY
     description: Latency
     bit_offset: 0
-    bit_size: 3
+    bit_size: 4
     enum: LATENCY
   - name: PRFTEN
     description: Prefetch enable
@@ -168,7 +168,7 @@ fieldset/SR:
     bit_offset: 16
     bit_size: 1
 enum/LATENCY:
-  bit_size: 3
+  bit_size: 4
   variants:
   - name: WS0
     description: 0 wait states

data/registers/flash_g4.yaml

@@ -359,7 +359,7 @@ fieldset/WRP1BR:
     bit_offset: 16
     bit_size: 7
 enum/LATENCY:
-  bit_size: 3
+  bit_size: 4
   variants:
   - name: WS0
     description: Zero wait states

data/registers/icache_v1.yaml

@@ -29,10 +29,12 @@ fieldset/CRRX:
     description: AHB cache master selection for region.
     bit_offset: 28
     bit_size: 1
+    enum: MSTSEL
   - name: HBURST
     description: output burst type for region.
     bit_offset: 31
     bit_size: 1
+    enum: HBURST
 block/ICACHE:
   description: Instruction Cache Control Registers.
   items:

data/registers/ipcc_v1.yaml

@@ -14,126 +14,71 @@ block/IPCC_CPU:
   - name: CR
     description: Control register CPUx
     byte_offset: 0
-    fieldset: C1CR
+    fieldset: CxCR
   - name: MR
     description: Mask register CPUx
     byte_offset: 4
-    fieldset: C1MR
+    fieldset: CxMR
   - name: SCR
-    description: Status Set or Clear register CPU1
+    description: Status Set or Clear register CPUx
     byte_offset: 8
     access: Write
-    fieldset: C1SCR
+    fieldset: CxSCR
   - name: SR
-    description: CPU1 to CPU2 status register
+    description: CPUx to CPUy status register
     byte_offset: 12
     access: Read
-    fieldset: C1TO2SR
+    fieldset: CxTOySR
-fieldset/C1CR:
+fieldset/CxCR:
-  description: Control register CPU1
+  description: Control register CPUx
   fields:
   - name: RXOIE
-    description: processor 1 Receive channel occupied interrupt enable
+    description: processor x Receive channel occupied interrupt enable
     bit_offset: 0
     bit_size: 1
   - name: TXFIE
-    description: processor 1 Transmit channel free interrupt enable
+    description: processor x Transmit channel free interrupt enable
     bit_offset: 16
     bit_size: 1
-fieldset/C1MR:
+fieldset/CxMR:
-  description: Mask register CPU1
+  description: Mask register CPUx
   fields:
   - name: CHOM
-    description: processor 1 Receive channel x occupied interrupt enable
+    description: processor x Receive channel y occupied interrupt enable
     bit_offset: 0
     bit_size: 1
     array:
       len: 6
       stride: 1
   - name: CHFM
-    description: processor 1 Transmit channel x free interrupt mask
+    description: processor x Transmit channel y free interrupt mask
     bit_offset: 16
     bit_size: 1
     array:
       len: 6
       stride: 1
-fieldset/C1SCR:
+fieldset/CxSCR:
-  description: Status Set or Clear register CPU1
+  description: Status Set or Clear register CPUx
   fields:
   - name: CHC
-    description: processor 1 Receive channel x status clear
+    description: processor x Receive channel y status clear
     bit_offset: 0
     bit_size: 1
     array:
       len: 6
       stride: 1
   - name: CHS
-    description: processor 1 Transmit channel x status set
+    description: processor x Transmit channel y status set
     bit_offset: 16
     bit_size: 1
     array:
       len: 6
       stride: 1
-fieldset/C1TO2SR:
+fieldset/CxTOySR:
-  description: CPU1 to CPU2 status register
+  description: CPUx to CPUy status register
   fields:
   - name: CHF
-    description: processor 1 transmit to process 2 Receive channel x status flag
+    description: processor x transmit to process y Receive channel z status flag
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 6
-      stride: 1
-fieldset/C2CR:
-  description: Control register CPU2
-  fields:
-  - name: RXOIE
-    description: processor 2 Receive channel occupied interrupt enable
-    bit_offset: 0
-    bit_size: 1
-  - name: TXFIE
-    description: processor 2 Transmit channel free interrupt enable
-    bit_offset: 16
-    bit_size: 1
-fieldset/C2MR:
-  description: Mask register CPU2
-  fields:
-  - name: CHOM
-    description: processor 2 Receive channel x occupied interrupt enable
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 6
-      stride: 1
-  - name: CHFM
-    description: processor 2 Transmit channel 1 free interrupt mask
-    bit_offset: 16
-    bit_size: 1
-    array:
-      len: 6
-      stride: 1
-fieldset/C2SCR:
-  description: Status Set or Clear register CPU2
-  fields:
-  - name: CHC
-    description: processor 2 Receive channel x status clear
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 6
-      stride: 1
-  - name: CHS
-    description: processor 2 Transmit channel 1 status set
-    bit_offset: 16
-    bit_size: 1
-    array:
-      len: 6
-      stride: 1
-fieldset/C2TOC1SR:
-  description: CPU2 to CPU1 status register
-  fields:
-  - name: CHF
-    description: processor 2 transmit to process 1 Receive channel x status flag
     bit_offset: 0
     bit_size: 1
     array:

data/registers/octospi_v1.yaml

@@ -214,6 +214,7 @@ fieldset/CR:
     description: Flash select. This bit selects the Flash memory to be addressed in Single-, Dual-, Quad-SPI mode in single-memory configuration (when DMM = 0). This bit is ignored when DMM = 1 or when Octal-SPI mode is selected.
     bit_offset: 7
     bit_size: 1
+    enum: FlashSelect
   - name: FTHRES
     description: 'FIFO threshold level. This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[4:0] value.'
     bit_offset: 8
@@ -247,6 +248,7 @@ fieldset/CR:
     description: Polling match mode. This bit indicates which method must be used to determine a match during the Automatic status-polling mode.
     bit_offset: 23
     bit_size: 1
+    enum: MatchMode
   - name: FMODE
     description: Functional mode. This field defines the OCTOSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state.
     bit_offset: 28
@@ -349,6 +351,7 @@ fieldset/HLCR:
     description: Latency mode. This bit selects the Latency mode.
     bit_offset: 0
     bit_size: 1
+    enum: LatencyMode
   - name: WZL
     description: Write zero latency. This bit enables zero latency on write operations.
     bit_offset: 1
@@ -595,7 +598,7 @@ fieldset/WPTCR:
     bit_offset: 0
     bit_size: 5
   - name: DHQC
-    description: Delay hold quarter cycle Add a quarter cycle delay on the outputs in DTR communication to match hold requirement.
+    description: Delay hold quarter cycle. Add a quarter cycle delay on the outputs in DTR communication to match hold requirement.
     bit_offset: 28
     bit_size: 1
   - name: SSHIFT
@@ -610,15 +613,6 @@ fieldset/WTCR:
     description: Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated.
     bit_offset: 0
     bit_size: 5
-enum/CycleDelay:
-  bit_size: 1
-  variants:
-  - name: None
-    description: No delay hold
-    value: 0
-  - name: QuarterCycle
-    description: 1/4 cycle hold
-    value: 1
 enum/FlashSelect:
   bit_size: 1
   variants:
@@ -643,7 +637,7 @@ enum/FunctionalMode:
   - name: MemoryMapped
     description: Memory-mapped mode
     value: 3
-enum/Latency:
+enum/LatencyMode:
   bit_size: 1
   variants:
   - name: Variable
@@ -682,18 +676,6 @@ enum/MemType:
   - name: HyperBusRegister
     description: HyperBus register mode, addressing register space. The memory-mapped accesses in. this mode must be non-cacheable, or Indirect read/write modes must be used.
     value: 5
-enum/NcsCycleHold:
-  bit_size: 6
-  variants:
-  - name: OneCycle
-    description: NCS stays high for at least 1 cycle between external device commands.
-    value: 0
-  - name: TwoCycles
-    description: NCS stays high for at least 2 cycles between external device commands.
-    value: 1
-  - name: SixtyFourCycles
-    description: NCS stays high for at least 64 cycles between external device commands.
-    value: 63
 enum/PhaseMode:
   bit_size: 3
   variants:

data/registers/octospi_v2.yaml

@@ -214,6 +214,7 @@ fieldset/CR:
     description: Flash select. This bit selects the Flash memory to be addressed in Single-, Dual-, Quad-SPI mode in single-memory configuration (when DMM = 0). This bit is ignored when DMM = 1 or when Octal-SPI mode is selected.
     bit_offset: 7
     bit_size: 1
+    enum: FlashSelect
   - name: FTHRES
     description: 'FIFO threshold level. This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[4:0] value.'
     bit_offset: 8
@@ -247,6 +248,7 @@ fieldset/CR:
     description: Polling match mode. This bit indicates which method must be used to determine a match during the Automatic status-polling mode.
     bit_offset: 23
     bit_size: 1
+    enum: MatchMode
   - name: FMODE
     description: Functional mode. This field defines the OCTOSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state.
     bit_offset: 28
@@ -345,6 +347,7 @@ fieldset/HLCR:
     description: Latency mode. This bit selects the Latency mode.
     bit_offset: 0
     bit_size: 1
+    enum: LatencyMode
   - name: WZL
     description: Write zero latency. This bit enables zero latency on write operations.
     bit_offset: 1
@@ -591,7 +594,7 @@ fieldset/WPTCR:
     bit_offset: 0
     bit_size: 5
   - name: DHQC
-    description: Delay hold quarter cycle Add a quarter cycle delay on the outputs in DTR communication to match hold requirement.
+    description: Delay hold quarter cycle. Add a quarter cycle delay on the outputs in DTR communication to match hold requirement.
     bit_offset: 28
     bit_size: 1
   - name: SSHIFT
@@ -606,15 +609,6 @@ fieldset/WTCR:
     description: Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated.
     bit_offset: 0
     bit_size: 5
-enum/CycleDelay:
-  bit_size: 1
-  variants:
-  - name: None
-    description: No delay hold
-    value: 0
-  - name: QuarterCycle
-    description: 1/4 cycle hold
-    value: 1
 enum/FlashSelect:
   bit_size: 1
   variants:
@@ -639,7 +633,7 @@ enum/FunctionalMode:
   - name: MemoryMapped
     description: Memory-mapped mode
     value: 3
-enum/Latency:
+enum/LatencyMode:
   bit_size: 1
   variants:
   - name: Variable
@@ -678,18 +672,6 @@ enum/MemType:
   - name: HyperBusRegister
     description: HyperBus register mode, addressing register space. The memory-mapped accesses in. this mode must be non-cacheable, or Indirect read/write modes must be used.
     value: 5
-enum/NcsCycleHold:
-  bit_size: 6
-  variants:
-  - name: OneCycle
-    description: NCS stays high for at least 1 cycle between external device commands.
-    value: 0
-  - name: TwoCycles
-    description: NCS stays high for at least 2 cycles between external device commands.
-    value: 1
-  - name: SixtyFourCycles
-    description: NCS stays high for at least 64 cycles between external device commands.
-    value: 63
 enum/PhaseMode:
   bit_size: 3
   variants:

data/registers/opamp_f3.yaml

@@ -13,17 +13,20 @@ fieldset/OPAMP_CSR:
     bit_offset: 0
     bit_size: 1
   - name: FORCE_VP
-    description: FORCE_VP
+    description: Forces a calibration reference voltage on non-inverting input and disables external connections.
     bit_offset: 1
     bit_size: 1
+    enum: FORCE_VP
   - name: VP_SEL
     description: OPAMP Non inverting input selection
     bit_offset: 2
     bit_size: 2
+    enum: VP_SEL
   - name: VM_SEL
     description: OPAMP inverting input selection
     bit_offset: 5
     bit_size: 2
+    enum: VM_SEL
   - name: TCM_EN
     description: Timer controlled Mux mode enable
     bit_offset: 7
@@ -32,10 +35,12 @@ fieldset/OPAMP_CSR:
     description: OPAMP inverting input secondary selection
     bit_offset: 8
     bit_size: 1
+    enum: VMS_SEL
   - name: VPS_SEL
     description: OPAMP Non inverting input secondary selection
     bit_offset: 9
     bit_size: 2
+    enum: VPS_SEL
   - name: CALON
     description: Calibration mode enable
     bit_offset: 11
@@ -44,10 +49,12 @@ fieldset/OPAMP_CSR:
     description: Calibration selection
     bit_offset: 12
     bit_size: 2
+    enum: CALSEL
   - name: PGA_GAIN
     description: Gain in PGA mode
     bit_offset: 14
     bit_size: 4
+    enum: PGA_GAIN
   - name: USER_TRIM
     description: User trimming enable
     bit_offset: 18
@@ -61,13 +68,14 @@ fieldset/OPAMP_CSR:
     bit_offset: 24
     bit_size: 5
   - name: TSTREF
-    description: TSTREF
+    description: Output the internal reference voltage
     bit_offset: 29
     bit_size: 1
   - name: OUTCAL
     description: OPAMP ouput status flag
     bit_offset: 30
     bit_size: 1
+    enum: OUTCAL
   - name: LOCK
     description: OPAMP lock
     bit_offset: 31
@@ -144,15 +152,6 @@ enum/PGA_GAIN:
   - name: Gain16_VM1
     description: Gain 16, feedback connected to VM1
     value: 15
-enum/TSTREF:
-  bit_size: 1
-  variants:
-  - name: Output
-    description: VREFOPAMP2 is output
-    value: 0
-  - name: NotOutput
-    description: VREFOPAMP2 is not output
-    value: 1
 enum/VMS_SEL:
   bit_size: 1
   variants:

data/registers/otg_v1.yaml

@@ -1076,21 +1076,6 @@ fieldset/GLPMCFG:
     description: Enable best effort service latency
     bit_offset: 28
     bit_size: 1
-fieldset/GNPTXSTS:
-  description: Non-periodic transmit FIFO/queue status register
-  fields:
-  - name: NPTXFSAV
-    description: Non-periodic TxFIFO space available
-    bit_offset: 0
-    bit_size: 16
-  - name: NPTQXSAV
-    description: Non-periodic transmit request queue space available
-    bit_offset: 16
-    bit_size: 8
-  - name: NPTXQTOP
-    description: Top of the non-periodic transmit request queue
-    bit_offset: 24
-    bit_size: 7
 fieldset/GOTGCTL:
   description: Control and status register
   fields:

data/registers/rcc_f0.yaml

@@ -477,7 +477,7 @@ fieldset/CFGR:
   - name: MCOSEL
     description: Microcontroller clock output
     bit_offset: 24
-    bit_size: 3
+    bit_size: 4
     enum: MCOSEL
   - name: MCOPRE
     description: Microcontroller Clock Output Prescaler
@@ -845,7 +845,7 @@ enum/MCOPRE:
     description: MCO is divided by 128
     value: 7
 enum/MCOSEL:
-  bit_size: 3
+  bit_size: 4
   variants:
   - name: NoMCO
     description: MCO output disabled, no clock on MCO

data/registers/rcc_f4.yaml

@@ -1260,7 +1260,7 @@ fieldset/CFGR:
     description: I2S clock selection
     bit_offset: 23
     bit_size: 1
-    enum: ISSRC
+    enum: I2SSRC_CFGR
   - name: MCO1PRE
     description: MCO1 prescaler
     bit_offset: 24
@@ -1539,7 +1539,7 @@ fieldset/DCKCFGR:
   - name: CKDFSDM1ASEL
     description: DFSDM1 audio clock selection
     bit_offset: 15
-    bit_size: 5
+    bit_size: 1
     enum: CKDFSDMASEL
   - name: PLLSAIDIVR
     description: division factor for LCD_CLK
@@ -1580,7 +1580,7 @@ fieldset/DCKCFGR:
     description: I2SSRC
     bit_offset: 25
     bit_size: 2
-    enum: ISSRC
+    enum: I2SSRC_DCKCFGR
   - name: CLK48SEL
     description: 48 MHz clock source selection
     bit_offset: 27
@@ -1865,7 +1865,7 @@ enum/I2S1SRC:
   - name: HSI_HSE
     description: I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])
     value: 3
-enum/ISSRC:
+enum/I2SSRC_CFGR:
   bit_size: 1
   variants:
   - name: PLLI2S
@@ -1874,6 +1874,21 @@ enum/ISSRC:
   - name: CKIN
     description: External clock mapped on the I2S_CKIN pin used as I2S clock source
     value: 1
+enum/I2SSRC_DCKCFGR:
+  bit_size: 2
+  variants:
+  - name: PLLI2S_R
+    description: clock frequency = f(PLLI2S_R)
+    value: 0
+  - name: I2S_CKIN
+    description: clock frequency = I2S_CKIN Alternate function input frequency
+    value: 1
+  - name: PLL_R
+    description: clock frequency = f(PLL_R)
+    value: 2
+  - name: HSI_HSE
+    description: clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])
+    value: 3
 enum/LPTIMSEL:
   bit_size: 2
   variants:
@@ -2243,21 +2258,6 @@ enum/PLLI2SDIVR:
   - name: Div32
     description: PLLI2SDIVQ = /32
     value: 31
-enum/PLLI2SP:
-  bit_size: 2
-  variants:
-  - name: Div2
-    description: PLL*P=2
-    value: 0
-  - name: Div4
-    description: PLL*P=4
-    value: 1
-  - name: Div6
-    description: PLL*P=6
-    value: 2
-  - name: Div8
-    description: PLL*P=8
-    value: 3
 enum/PLLI2SSRC:
   bit_size: 1
   variants:
@@ -3338,21 +3338,6 @@ enum/PLLSAIDIVR:
   - name: Div16
     description: PLLSAIDIVR = /16
     value: 3
-enum/PLLSAIP:
-  bit_size: 2
-  variants:
-  - name: Div2
-    description: PLL*P=2
-    value: 0
-  - name: Div4
-    description: PLL*P=4
-    value: 1
-  - name: Div6
-    description: PLL*P=6
-    value: 2
-  - name: Div8
-    description: PLL*P=8
-    value: 3
 enum/PLLSRC:
   bit_size: 1
   variants:

data/registers/rcc_f7.yaml

@@ -1965,21 +1965,6 @@ enum/PLLI2SDIVQ:
   - name: Div32
     description: PLLI2SDIVQ = /32
     value: 31
-enum/PLLI2SP:
-  bit_size: 2
-  variants:
-  - name: Div2
-    description: PLL*P=2
-    value: 0
-  - name: Div4
-    description: PLL*P=4
-    value: 1
-  - name: Div6
-    description: PLL*P=6
-    value: 2
-  - name: Div8
-    description: PLL*P=8
-    value: 3
 enum/PLLM:
   bit_size: 6
   variants:
@@ -3051,21 +3036,6 @@ enum/PLLSAIDIVR:
   - name: Div16
     description: PLLSAIDIVR = /16
     value: 3
-enum/PLLSAIP:
-  bit_size: 2
-  variants:
-  - name: Div2
-    description: PLL*P=2
-    value: 0
-  - name: Div4
-    description: PLL*P=4
-    value: 1
-  - name: Div6
-    description: PLL*P=6
-    value: 2
-  - name: Div8
-    description: PLL*P=8
-    value: 3
 enum/PLLSRC:
   bit_size: 1
   variants:

data/registers/rcc_g0.yaml

@@ -849,12 +849,12 @@ fieldset/CFGR:
   - name: MCO1SEL
     description: Microcontroller clock output
     bit_offset: 24
-    bit_size: 3
+    bit_size: 4
     enum: MCOSEL
   - name: MCO1PRE
     description: Microcontroller clock output prescaler
     bit_offset: 28
-    bit_size: 3
+    bit_size: 4
     enum: MCOPRE
 fieldset/CICR:
   description: Clock interrupt clear register
@@ -1765,7 +1765,7 @@ enum/PLLSRC:
     description: HSE selected as PLL entry clock source
     value: 3
 enum/PPRE:
-  bit_size: 4
+  bit_size: 3
   variants:
   - name: Div1
     description: HCLK not divided

data/registers/rcc_g4.yaml

@@ -1743,7 +1743,7 @@ enum/PLLN:
   - name: Mul127
     value: 127
 enum/PLLP:
-  bit_size: 7
+  bit_size: 5
   variants:
   - name: Div2
     value: 2
@@ -1847,7 +1847,7 @@ enum/PLLSRC:
     description: HSE selected as PLL entry clock source
     value: 3
 enum/PPRE:
-  bit_size: 4
+  bit_size: 3
   variants:
   - name: Div1
     description: HCLK not divided

data/registers/rcc_h7.yaml

@@ -5,6 +5,10 @@ block/RCC:
     description: clock control register
     byte_offset: 0
     fieldset: CR
+  - name: ICSCR
+    description: RCC Internal Clock Source Calibration Register
+    byte_offset: 4
+    fieldset: ICSCR
   - name: HSICFGR
     description: RCC HSI configuration register
     byte_offset: 4

data/registers/rcc_h7rm0433.yaml

@@ -5,6 +5,10 @@ block/RCC:
     description: clock control register
     byte_offset: 0
     fieldset: CR
+  - name: ICSCR
+    description: RCC Internal Clock Source Calibration Register
+    byte_offset: 4
+    fieldset: ICSCR
   - name: HSICFGR
     description: RCC HSI configuration register
     byte_offset: 4

data/registers/rcc_l1.yaml

@@ -881,7 +881,7 @@ enum/MCOPRE:
     description: Division by 16
     value: 4
 enum/MCOSEL:
-  bit_size: 4
+  bit_size: 3
   variants:
   - name: DISABLE
     description: No clock

data/registers/rcc_l5.yaml

@@ -2394,7 +2394,7 @@ enum/PLLN:
   - name: Mul127
     value: 127
 enum/PLLP:
-  bit_size: 7
+  bit_size: 5
   variants:
   - name: Div2
     value: 2

data/registers/rtc_v3l5.yaml

@@ -854,18 +854,6 @@ enum/RECALPF:
   - name: Pending
     description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0
     value: 1
-enum/SSRUF:
-  bit_size: 1
-  variants:
-  - name: Underflow
-    description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1
-    value: 1
-enum/SSRUMF:
-  bit_size: 1
-  variants:
-  - name: Underflow
-    description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1
-    value: 1
 enum/TAMPALRM_TYPE:
   bit_size: 1
   variants:

data/registers/sdmmc_v1.yaml

@@ -29,7 +29,7 @@ block/SDMMC:
       stride: 4
     byte_offset: 20
     access: Read
-    fieldset: RESP1R
+    fieldset: RESPxR
   - name: DTIMER
     description: data timer register
     byte_offset: 36
@@ -361,28 +361,7 @@ fieldset/POWER:
     description: PWRCTRL
     bit_offset: 0
     bit_size: 2
-fieldset/RESP1R:
+fieldset/RESPxR:
-  description: response 1..4 register
-  fields:
-  - name: CARDSTATUS
-    description: see Table 132
-    bit_offset: 0
-    bit_size: 32
-fieldset/RESP2R:
-  description: response 1..4 register
-  fields:
-  - name: CARDSTATUS
-    description: see Table 132
-    bit_offset: 0
-    bit_size: 32
-fieldset/RESP3R:
-  description: response 1..4 register
-  fields:
-  - name: CARDSTATUS
-    description: see Table 132
-    bit_offset: 0
-    bit_size: 32
-fieldset/RESP4R:
   description: response 1..4 register
   fields:
   - name: CARDSTATUS

data/registers/sdmmc_v2.yaml

@@ -29,7 +29,7 @@ block/SDMMC:
       stride: 4
     byte_offset: 20
     access: Read
-    fieldset: RESP1R
+    fieldset: RESPxR
   - name: DTIMER
     description: The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.
     byte_offset: 36
@@ -501,34 +501,13 @@ fieldset/POWER:
     description: Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00).
     bit_offset: 4
     bit_size: 1
-fieldset/RESP1R:
+fieldset/RESPxR:
   description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
   fields:
   - name: CARDSTATUS
     description: see Table 432
     bit_offset: 0
     bit_size: 32
-fieldset/RESP2R:
-  description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
-  fields:
-  - name: CARDSTATUS
-    description: see Table404.
-    bit_offset: 0
-    bit_size: 32
-fieldset/RESP3R:
-  description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
-  fields:
-  - name: CARDSTATUS
-    description: see Table404.
-    bit_offset: 0
-    bit_size: 32
-fieldset/RESP4R:
-  description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
-  fields:
-  - name: CARDSTATUS
-    description: see Table404.
-    bit_offset: 0
-    bit_size: 32
 fieldset/RESPCMDR:
   description: SDMMC command response register
   fields:

data/registers/syscfg_c0.yaml

@@ -417,105 +417,69 @@ enum/MEM_MODE:
 enum/PINMUX0:
   bit_size: 2
   variants:
-  - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1
+  - name: PB7
     description: PB7
     value: 0
-  - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2
+  - name: PC14
-    description: PA1
-    value: 0
-  - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1
     description: PC14
     value: 1
-  - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2
-    description: PA2
-    value: 1
 enum/PINMUX1:
   bit_size: 2
   variants:
-  - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
+  - name: PF2
     description: PF2
     value: 0
-  - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3
+  - name: PA0
-    description: PF2
-    value: 0
-  - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
     description: PA0
     value: 1
-  - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3
+  - name: PA1
-    description: PA0
-    value: 1
-  - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
     description: PA1
     value: 2
-  - name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
+  - name: PA2
     description: PA2
     value: 3
 enum/PINMUX2:
   bit_size: 2
   variants:
-  - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5
+  - name: PA8
     description: PA8
     value: 0
-  - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1
+  - name: PA11
-    description: PA8
-    value: 0
-  - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5
-    description: PA11
-    value: 1
-  - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1
     description: PA11
     value: 1
 enum/PINMUX3:
   bit_size: 2
   variants:
-  - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8
+  - name: PA14
     description: PA14
     value: 0
-  - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2
+  - name: PB6
-    description: PA5
-    value: 0
-  - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8
     description: PB6
     value: 1
-  - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2
+  - name: PC15
-    description: PA6
-    value: 1
-  - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8
     description: PC15
     value: 2
 enum/PINMUX4:
   bit_size: 2
   variants:
-  - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2
+  - name: PA7
     description: PA7
     value: 0
-  - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1
+  - name: PA12
-    description: PA7
-    value: 0
-  - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2
-    description: PA12
-    value: 1
-  - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1
     description: PA12
     value: 1
 enum/PINMUX5:
   bit_size: 2
   variants:
-  - name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
+  - name: PA3
     description: PA3
     value: 0
-  - name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3
+  - name: PA4
-    description: PA3
-    value: 0
-  - name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
     description: PA4
     value: 1
-  - name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3
+  - name: PA5
-    description: PA4
-    value: 1
-  - name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
     description: PA5
     value: 2
-  - name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
+  - name: PA6
     description: PA6
     value: 3

data/registers/syscfg_f3.yaml

@@ -398,10 +398,10 @@ enum/ADC2_DMA_RMP_CFGR1:
   variants:
   - name: NotRemapped
     description: ADC24 DMA requests mapped on DMA2 channels 1 and 2
-    value: 2
+    value: 0
   - name: Remapped
     description: ADC24 DMA requests mapped on DMA2 channels 3 and 4
-    value: 3
+    value: 1
 enum/ADC2_DMA_RMP_CFGR3:
   bit_size: 2
   variants:

data/registers/usart_v1.yaml

@@ -267,10 +267,6 @@ fieldset/SR:
     description: LIN break detection flag
     bit_offset: 8
     bit_size: 1
-fieldset/SR_USART:
-  extends: SR
-  description: Status register
-  fields:
   - name: CTS
     description: CTS flag
     bit_offset: 9

data/registers/usart_v2.yaml

@@ -276,10 +276,6 @@ fieldset/SR:
     description: LIN break detection flag
     bit_offset: 8
     bit_size: 1
-fieldset/SR_USART:
-  extends: SR
-  description: Status register
-  fields:
   - name: CTS
     description: CTS flag
     bit_offset: 9