1048 lines
24 KiB
YAML
1048 lines
24 KiB
YAML
block/RCC:
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description: Reset and clock control
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items:
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- name: CR
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description: Clock control register
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byte_offset: 0
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fieldset: CR
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- name: ICSCR
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description: Internal clock sources calibration register
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byte_offset: 4
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fieldset: ICSCR
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- name: CFGR
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description: Clock configuration register
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byte_offset: 8
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fieldset: CFGR
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- name: CIR
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description: Clock interrupt register
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byte_offset: 12
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fieldset: CIR
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- name: AHBRSTR
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description: AHB peripheral reset register
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byte_offset: 16
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fieldset: AHBRSTR
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- name: APB2RSTR
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description: APB2 peripheral reset register
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byte_offset: 20
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fieldset: APB2RSTR
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- name: APB1RSTR
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description: APB1 peripheral reset register
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byte_offset: 24
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fieldset: APB1RSTR
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- name: AHBENR
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description: AHB peripheral clock enable register
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byte_offset: 28
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fieldset: AHBENR
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- name: APB2ENR
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description: APB2 peripheral clock enable register
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byte_offset: 32
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fieldset: APB2ENR
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- name: APB1ENR
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description: APB1 peripheral clock enable register
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byte_offset: 36
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fieldset: APB1ENR
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- name: AHBLPENR
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description: AHB peripheral clock enable in low power mode register
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byte_offset: 40
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fieldset: AHBLPENR
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- name: APB2LPENR
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description: APB2 peripheral clock enable in low power mode register
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byte_offset: 44
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fieldset: APB2LPENR
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- name: APB1LPENR
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description: APB1 peripheral clock enable in low power mode register
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byte_offset: 48
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fieldset: APB1LPENR
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- name: CSR
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description: Control/status register
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byte_offset: 52
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fieldset: CSR
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fieldset/AHBENR:
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description: AHB peripheral clock enable register
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fields:
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- name: GPIOAEN
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description: IO port A clock enable
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bit_offset: 0
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bit_size: 1
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- name: GPIOBEN
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description: IO port B clock enable
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bit_offset: 1
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bit_size: 1
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- name: GPIOCEN
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description: IO port C clock enable
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bit_offset: 2
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bit_size: 1
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- name: GPIODEN
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description: IO port D clock enable
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bit_offset: 3
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bit_size: 1
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- name: GPIOEEN
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description: IO port E clock enable
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bit_offset: 4
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bit_size: 1
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- name: GPIOHEN
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description: IO port H clock enable
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bit_offset: 5
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bit_size: 1
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- name: GPIOFEN
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description: IO port F clock enable
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bit_offset: 6
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bit_size: 1
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- name: GPIOGEN
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description: IO port G clock enable
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bit_offset: 7
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bit_size: 1
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- name: CRCEN
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description: CRC clock enable
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bit_offset: 12
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bit_size: 1
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- name: FLASHEN
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description: FLASH clock enable
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bit_offset: 15
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bit_size: 1
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- name: DMA1EN
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description: DMA1 clock enable
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bit_offset: 24
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bit_size: 1
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- name: DMA2EN
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description: DMA2 clock enable
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bit_offset: 25
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bit_size: 1
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- name: FSMCEN
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description: FSMCEN
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bit_offset: 30
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bit_size: 1
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fieldset/AHBLPENR:
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description: AHB peripheral clock enable in low power mode register
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fields:
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- name: GPIOALPEN
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description: IO port A clock enable during Sleep mode
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bit_offset: 0
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bit_size: 1
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- name: GPIOBLPEN
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description: IO port B clock enable during Sleep mode
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bit_offset: 1
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bit_size: 1
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- name: GPIOCLPEN
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description: IO port C clock enable during Sleep mode
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bit_offset: 2
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bit_size: 1
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- name: GPIODLPEN
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description: IO port D clock enable during Sleep mode
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bit_offset: 3
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bit_size: 1
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- name: GPIOELPEN
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description: IO port E clock enable during Sleep mode
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bit_offset: 4
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bit_size: 1
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- name: GPIOHLPEN
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description: IO port H clock enable during Sleep mode
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bit_offset: 5
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bit_size: 1
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- name: GPIOFLPEN
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description: IO port F clock enable during Sleep mode
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bit_offset: 6
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bit_size: 1
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- name: GPIOGLPEN
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description: IO port G clock enable during Sleep mode
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bit_offset: 7
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bit_size: 1
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- name: CRCLPEN
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description: CRC clock enable during Sleep mode
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bit_offset: 12
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bit_size: 1
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- name: FLASHLPEN
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description: FLASH clock enable during Sleep mode
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bit_offset: 15
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bit_size: 1
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- name: SRAMLPEN
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description: SRAM clock enable during Sleep mode
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bit_offset: 16
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bit_size: 1
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- name: DMA1LPEN
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description: DMA1 clock enable during Sleep mode
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bit_offset: 24
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bit_size: 1
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- name: DMA2LPEN
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description: DMA2 clock enable during Sleep mode
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bit_offset: 25
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bit_size: 1
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fieldset/AHBRSTR:
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description: AHB peripheral reset register
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fields:
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- name: GPIOARST
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description: IO port A reset
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bit_offset: 0
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bit_size: 1
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- name: GPIOBRST
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description: IO port B reset
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bit_offset: 1
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bit_size: 1
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- name: GPIOCRST
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description: IO port C reset
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bit_offset: 2
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bit_size: 1
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- name: GPIODRST
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description: IO port D reset
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bit_offset: 3
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bit_size: 1
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- name: GPIOERST
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description: IO port E reset
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bit_offset: 4
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bit_size: 1
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- name: GPIOHRST
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description: IO port H reset
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bit_offset: 5
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bit_size: 1
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- name: GPIOFRST
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description: IO port F reset
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bit_offset: 6
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bit_size: 1
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- name: GPIOGRST
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description: IO port G reset
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bit_offset: 7
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bit_size: 1
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- name: CRCRST
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description: CRC reset
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bit_offset: 12
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bit_size: 1
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- name: FLASHRST
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description: FLASH reset
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bit_offset: 15
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bit_size: 1
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- name: DMA1RST
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description: DMA1 reset
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bit_offset: 24
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bit_size: 1
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- name: DMA2RST
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description: DMA2 reset
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bit_offset: 25
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bit_size: 1
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- name: FSMCRST
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description: FSMC reset
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bit_offset: 30
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bit_size: 1
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fieldset/APB1ENR:
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description: APB1 peripheral clock enable register
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fields:
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- name: TIM2EN
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description: Timer 2 clock enable
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bit_offset: 0
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bit_size: 1
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- name: TIM3EN
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description: Timer 3 clock enable
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bit_offset: 1
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bit_size: 1
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- name: TIM4EN
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description: Timer 4 clock enable
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bit_offset: 2
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bit_size: 1
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- name: TIM5EN
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description: Timer 5 clock enable
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bit_offset: 3
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bit_size: 1
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- name: TIM6EN
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description: Timer 6 clock enable
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bit_offset: 4
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bit_size: 1
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- name: TIM7EN
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description: Timer 7 clock enable
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bit_offset: 5
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bit_size: 1
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- name: LCDEN
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description: LCD clock enable
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bit_offset: 9
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bit_size: 1
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- name: WWDGEN
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description: Window watchdog clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI2EN
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description: SPI 2 clock enable
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bit_offset: 14
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bit_size: 1
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- name: SPI3EN
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description: SPI 3 clock enable
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bit_offset: 15
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bit_size: 1
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- name: USART2EN
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description: USART 2 clock enable
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bit_offset: 17
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bit_size: 1
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- name: USART3EN
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description: USART 3 clock enable
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bit_offset: 18
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bit_size: 1
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- name: USART4EN
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description: UART 4 clock enable
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bit_offset: 19
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bit_size: 1
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- name: USART5EN
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description: UART 5 clock enable
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bit_offset: 20
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bit_size: 1
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- name: I2C1EN
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description: I2C 1 clock enable
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bit_offset: 21
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bit_size: 1
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- name: I2C2EN
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description: I2C 2 clock enable
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bit_offset: 22
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bit_size: 1
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- name: USBEN
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description: USB clock enable
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bit_offset: 23
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bit_size: 1
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- name: PWREN
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description: Power interface clock enable
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bit_offset: 28
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bit_size: 1
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- name: DACEN
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description: DAC interface clock enable
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bit_offset: 29
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bit_size: 1
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- name: COMPEN
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description: COMP interface clock enable
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bit_offset: 31
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bit_size: 1
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fieldset/APB1LPENR:
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description: APB1 peripheral clock enable in low power mode register
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fields:
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- name: TIM2LPEN
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description: Timer 2 clock enable during Sleep mode
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bit_offset: 0
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bit_size: 1
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- name: TIM3LPEN
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description: Timer 3 clock enable during Sleep mode
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bit_offset: 1
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bit_size: 1
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- name: TIM4LPEN
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description: Timer 4 clock enable during Sleep mode
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bit_offset: 2
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bit_size: 1
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- name: TIM6LPEN
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description: Timer 6 clock enable during Sleep mode
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bit_offset: 4
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bit_size: 1
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- name: TIM7LPEN
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description: Timer 7 clock enable during Sleep mode
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bit_offset: 5
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bit_size: 1
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- name: LCDLPEN
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description: LCD clock enable during Sleep mode
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bit_offset: 9
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bit_size: 1
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- name: WWDGLPEN
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description: Window watchdog clock enable during Sleep mode
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bit_offset: 11
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bit_size: 1
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- name: SPI2LPEN
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description: SPI 2 clock enable during Sleep mode
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bit_offset: 14
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bit_size: 1
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- name: USART2LPEN
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description: USART 2 clock enable during Sleep mode
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bit_offset: 17
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bit_size: 1
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- name: USART3LPEN
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description: USART 3 clock enable during Sleep mode
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bit_offset: 18
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bit_size: 1
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- name: I2C1LPEN
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description: I2C 1 clock enable during Sleep mode
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bit_offset: 21
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bit_size: 1
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- name: I2C2LPEN
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description: I2C 2 clock enable during Sleep mode
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bit_offset: 22
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bit_size: 1
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- name: USBLPEN
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description: USB clock enable during Sleep mode
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bit_offset: 23
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bit_size: 1
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- name: PWRLPEN
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description: Power interface clock enable during Sleep mode
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bit_offset: 28
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bit_size: 1
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- name: DACLPEN
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description: DAC interface clock enable during Sleep mode
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bit_offset: 29
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bit_size: 1
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- name: COMPLPEN
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description: COMP interface clock enable during Sleep mode
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bit_offset: 31
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bit_size: 1
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fieldset/APB1RSTR:
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description: APB1 peripheral reset register
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fields:
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- name: TIM2RST
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description: Timer 2 reset
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bit_offset: 0
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bit_size: 1
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- name: TIM3RST
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description: Timer 3 reset
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bit_offset: 1
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bit_size: 1
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- name: TIM4RST
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description: Timer 4 reset
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bit_offset: 2
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bit_size: 1
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- name: TIM5RST
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description: Timer 5 reset
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bit_offset: 3
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bit_size: 1
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- name: TIM6RST
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description: Timer 6reset
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bit_offset: 4
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bit_size: 1
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- name: TIM7RST
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description: Timer 7 reset
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bit_offset: 5
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bit_size: 1
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- name: LCDRST
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description: LCD reset
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bit_offset: 9
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bit_size: 1
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- name: WWDRST
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description: Window watchdog reset
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bit_offset: 11
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bit_size: 1
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- name: SPI2RST
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description: SPI 2 reset
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bit_offset: 14
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bit_size: 1
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- name: SPI3RST
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description: SPI 3 reset
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bit_offset: 15
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bit_size: 1
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- name: USART2RST
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description: USART 2 reset
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bit_offset: 17
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bit_size: 1
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- name: USART3RST
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description: USART 3 reset
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bit_offset: 18
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bit_size: 1
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- name: UART4RST
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description: UART 4 reset
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bit_offset: 19
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bit_size: 1
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- name: UART5RST
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description: UART 5 reset
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bit_offset: 20
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bit_size: 1
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- name: I2C1RST
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description: I2C 1 reset
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bit_offset: 21
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bit_size: 1
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- name: I2C2RST
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description: I2C 2 reset
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bit_offset: 22
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bit_size: 1
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- name: USBRST
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description: USB reset
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bit_offset: 23
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bit_size: 1
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- name: PWRRST
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description: Power interface reset
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bit_offset: 28
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bit_size: 1
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- name: DACRST
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description: DAC interface reset
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bit_offset: 29
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bit_size: 1
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- name: COMPRST
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description: COMP interface reset
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bit_offset: 31
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bit_size: 1
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fieldset/APB2ENR:
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description: APB2 peripheral clock enable register
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fields:
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- name: SYSCFGEN
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description: System configuration controller clock enable
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bit_offset: 0
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bit_size: 1
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- name: TIM9EN
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description: TIM9 timer clock enable
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bit_offset: 2
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bit_size: 1
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- name: TIM10EN
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description: TIM10 timer clock enable
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bit_offset: 3
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bit_size: 1
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- name: TIM11EN
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description: TIM11 timer clock enable
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bit_offset: 4
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bit_size: 1
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- name: ADC1EN
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description: ADC1 interface clock enable
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bit_offset: 9
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bit_size: 1
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- name: SDIOEN
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description: SDIO clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI1EN
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description: SPI 1 clock enable
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bit_offset: 12
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bit_size: 1
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- name: USART1EN
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description: USART1 clock enable
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bit_offset: 14
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bit_size: 1
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fieldset/APB2LPENR:
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description: APB2 peripheral clock enable in low power mode register
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fields:
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- name: SYSCFGLPEN
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description: System configuration controller clock enable during Sleep mode
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bit_offset: 0
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bit_size: 1
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- name: TIM9LPEN
|
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description: TIM9 timer clock enable during Sleep mode
|
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bit_offset: 2
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bit_size: 1
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- name: TIM10LPEN
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description: TIM10 timer clock enable during Sleep mode
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bit_offset: 3
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bit_size: 1
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- name: TIM11LPEN
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description: TIM11 timer clock enable during Sleep mode
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bit_offset: 4
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bit_size: 1
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- name: ADC1LPEN
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description: ADC1 interface clock enable during Sleep mode
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bit_offset: 9
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bit_size: 1
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- name: SDIOLPEN
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description: SDIO clock enable during Sleep mode
|
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bit_offset: 11
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bit_size: 1
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- name: SPI1LPEN
|
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description: SPI 1 clock enable during Sleep mode
|
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bit_offset: 12
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bit_size: 1
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- name: USART1LPEN
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description: USART1 clock enable during Sleep mode
|
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bit_offset: 14
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bit_size: 1
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|
fieldset/APB2RSTR:
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description: APB2 peripheral reset register
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fields:
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- name: SYSCFGRST
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description: SYSCFGRST
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bit_offset: 0
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bit_size: 1
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- name: TIM9RST
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description: TIM9RST
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bit_offset: 2
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bit_size: 1
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- name: TM10RST
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description: TM10RST
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bit_offset: 3
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bit_size: 1
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- name: TM11RST
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description: TM11RST
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bit_offset: 4
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bit_size: 1
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- name: ADC1RST
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description: ADC1RST
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bit_offset: 9
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bit_size: 1
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- name: SDIORST
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description: SDIORST
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bit_offset: 11
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bit_size: 1
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- name: SPI1RST
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description: SPI1RST
|
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bit_offset: 12
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bit_size: 1
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- name: USART1RST
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description: USART1RST
|
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bit_offset: 14
|
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bit_size: 1
|
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fieldset/CFGR:
|
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description: Clock configuration register
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fields:
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- name: SW
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description: System clock switch
|
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bit_offset: 0
|
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bit_size: 2
|
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enum: SW
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- name: SWS
|
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description: System clock switch status
|
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bit_offset: 2
|
|
bit_size: 2
|
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enum: SW
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- name: HPRE
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|
description: AHB prescaler
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
enum: HPRE
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|
- name: PPRE1
|
|
description: APB low-speed prescaler (APB1)
|
|
bit_offset: 8
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: PPRE2
|
|
description: APB high-speed prescaler (APB2)
|
|
bit_offset: 11
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: PLLSRC
|
|
description: PLL entry clock source
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: PLLSRC
|
|
- name: PLLMUL
|
|
description: PLL multiplication factor
|
|
bit_offset: 18
|
|
bit_size: 4
|
|
enum: PLLMUL
|
|
- name: PLLDIV
|
|
description: PLL output division
|
|
bit_offset: 22
|
|
bit_size: 2
|
|
enum: PLLDIV
|
|
- name: MCOSEL
|
|
description: Microcontroller clock output selection
|
|
bit_offset: 24
|
|
bit_size: 3
|
|
enum: MCOSEL
|
|
- name: MCOPRE
|
|
description: Microcontroller clock output prescaler
|
|
bit_offset: 28
|
|
bit_size: 3
|
|
enum: MCOPRE
|
|
fieldset/CIR:
|
|
description: Clock interrupt register
|
|
fields:
|
|
- name: LSIRDYF
|
|
description: LSI ready interrupt flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYF
|
|
description: LSE ready interrupt flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDYF
|
|
description: HSI ready interrupt flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSERDYF
|
|
description: HSE ready interrupt flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: PLLRDYF
|
|
description: PLL ready interrupt flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: MSIRDYF
|
|
description: MSI ready interrupt flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CSSF
|
|
description: Clock security system interrupt flag
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: LSIRDYIE
|
|
description: LSI ready interrupt enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSERDYIE
|
|
description: LSE ready interrupt enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSIRDYIE
|
|
description: HSI ready interrupt enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: HSERDYIE
|
|
description: HSE ready interrupt enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: PLLRDYIE
|
|
description: PLL ready interrupt enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: MSIRDYIE
|
|
description: MSI ready interrupt enable
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: LSIRDYC
|
|
description: LSI ready interrupt clear
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: LSERDYC
|
|
description: LSE ready interrupt clear
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSIRDYC
|
|
description: HSI ready interrupt clear
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: HSERDYC
|
|
description: HSE ready interrupt clear
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: PLLRDYC
|
|
description: PLL ready interrupt clear
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: MSIRDYC
|
|
description: MSI ready interrupt clear
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: CSSC
|
|
description: Clock security system interrupt clear
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: Clock control register
|
|
fields:
|
|
- name: HSION
|
|
description: Internal high-speed clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSIRDY
|
|
description: Internal high-speed clock ready flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSION
|
|
description: MSI clock enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: MSIRDY
|
|
description: MSI clock ready flag
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSEON
|
|
description: HSE clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSERDY
|
|
description: HSE clock ready flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSEBYP
|
|
description: HSE clock bypass
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: PLLON
|
|
description: PLL enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLRDY
|
|
description: PLL clock ready flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: CSSON
|
|
description: Clock security system enable
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: RTCPRE
|
|
description: RTC/LCD prescaler
|
|
bit_offset: 29
|
|
bit_size: 2
|
|
enum: RTCPRE
|
|
fieldset/CSR:
|
|
description: Control and status register
|
|
fields:
|
|
- name: LSION
|
|
description: Internal low-speed oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSIRDY
|
|
description: Internal low-speed oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSEON
|
|
description: External low-speed oscillator enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSERDY
|
|
description: External low-speed oscillator ready
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: LSEBYP
|
|
description: External low-speed oscillator bypass
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: RTCSEL
|
|
description: RTC and LCD clock source selection
|
|
bit_offset: 16
|
|
bit_size: 2
|
|
enum: RTCSEL
|
|
- name: RTCEN
|
|
description: RTC clock enable
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: RTCRST
|
|
description: RTC software reset
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: RMVF
|
|
description: Remove reset flag
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PINRSTF
|
|
description: PIN reset flag
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PORRSTF
|
|
description: POR/PDR reset flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: SFTRSTF
|
|
description: Software reset flag
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: IWDGRSTF
|
|
description: Independent watchdog reset flag
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: WWDGRSTF
|
|
description: Window watchdog reset flag
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPWRRSTF
|
|
description: Low-power reset flag
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/ICSCR:
|
|
description: Internal clock sources calibration register
|
|
fields:
|
|
- name: HSICAL
|
|
description: nternal high speed clock calibration
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: HSITRIM
|
|
description: High speed internal clock trimming
|
|
bit_offset: 8
|
|
bit_size: 5
|
|
- name: MSIRANGE
|
|
description: MSI clock ranges
|
|
bit_offset: 13
|
|
bit_size: 3
|
|
enum: MSIRANGE
|
|
- name: MSICAL
|
|
description: MSI clock calibration
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
- name: MSITRIM
|
|
description: MSI clock trimming
|
|
bit_offset: 24
|
|
bit_size: 8
|
|
enum/HPRE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: system clock not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: system clock divided by 2
|
|
value: 8
|
|
- name: Div4
|
|
description: system clock divided by 4
|
|
value: 9
|
|
- name: Div8
|
|
description: system clock divided by 8
|
|
value: 10
|
|
- name: Div16
|
|
description: system clock divided by 16
|
|
value: 11
|
|
- name: Div64
|
|
description: system clock divided by 64
|
|
value: 12
|
|
- name: Div128
|
|
description: system clock divided by 128
|
|
value: 13
|
|
- name: Div256
|
|
description: system clock divided by 256
|
|
value: 14
|
|
- name: Div512
|
|
description: system clock divided by 512
|
|
value: 15
|
|
enum/MCOPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: No division
|
|
value: 0
|
|
- name: Div2
|
|
description: Division by 2
|
|
value: 1
|
|
- name: Div4
|
|
description: Division by 4
|
|
value: 2
|
|
- name: Div8
|
|
description: Division by 8
|
|
value: 3
|
|
- name: Div16
|
|
description: Division by 16
|
|
value: 4
|
|
enum/MCOSEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: DISABLE
|
|
description: No clock
|
|
value: 0
|
|
- name: SYS
|
|
description: SYSCLK clock selected
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI oscillator clock selected
|
|
value: 2
|
|
- name: MSI
|
|
description: MSI oscillator clock selected
|
|
value: 3
|
|
- name: HSE
|
|
description: HSE oscillator clock selected
|
|
value: 4
|
|
- name: PLL
|
|
description: PLL clock selected
|
|
value: 5
|
|
- name: LSI
|
|
description: LSI oscillator clock selected
|
|
value: 6
|
|
- name: LSE
|
|
description: LSE oscillator clock selected
|
|
value: 7
|
|
enum/MSIRANGE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Range66K
|
|
description: range 0 around 65.536 kHz
|
|
value: 0
|
|
- name: Range131K
|
|
description: range 1 around 131.072 kHz
|
|
value: 1
|
|
- name: Range262K
|
|
description: range 2 around 262.144 kHz
|
|
value: 2
|
|
- name: Range524K
|
|
description: range 3 around 524.288 kHz
|
|
value: 3
|
|
- name: Range1M
|
|
description: range 4 around 1.048 MHz
|
|
value: 4
|
|
- name: Range2M
|
|
description: range 5 around 2.097 MHz (reset value)
|
|
value: 5
|
|
- name: Range4M
|
|
description: range 6 around 4.194 MHz
|
|
value: 6
|
|
enum/PLLDIV:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Div2
|
|
description: PLLVCO / 2
|
|
value: 1
|
|
- name: Div3
|
|
description: PLLVCO / 3
|
|
value: 2
|
|
- name: Div4
|
|
description: PLLVCO / 4
|
|
value: 3
|
|
enum/PLLMUL:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Mul3
|
|
description: PLL clock entry x 3
|
|
value: 0
|
|
- name: Mul4
|
|
description: PLL clock entry x 4
|
|
value: 1
|
|
- name: Mul6
|
|
description: PLL clock entry x 6
|
|
value: 2
|
|
- name: Mul8
|
|
description: PLL clock entry x 8
|
|
value: 3
|
|
- name: Mul12
|
|
description: PLL clock entry x 12
|
|
value: 4
|
|
- name: Mul16
|
|
description: PLL clock entry x 16
|
|
value: 5
|
|
- name: Mul24
|
|
description: PLL clock entry x 24
|
|
value: 6
|
|
- name: Mul32
|
|
description: PLL clock entry x 32
|
|
value: 7
|
|
- name: Mul48
|
|
description: PLL clock entry x 48
|
|
value: 8
|
|
enum/PLLSRC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: HSI
|
|
description: HSI selected as PLL input clock
|
|
value: 0
|
|
- name: HSE
|
|
description: HSE selected as PLL input clock
|
|
value: 1
|
|
enum/PPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: HCLK not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: HCLK divided by 2
|
|
value: 4
|
|
- name: Div4
|
|
description: HCLK divided by 4
|
|
value: 5
|
|
- name: Div8
|
|
description: HCLK divided by 8
|
|
value: 6
|
|
- name: Div16
|
|
description: HCLK divided by 16
|
|
value: 7
|
|
enum/RTCPRE:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Div2
|
|
description: HSE divided by 2
|
|
value: 0
|
|
- name: Div4
|
|
description: HSE divided by 4
|
|
value: 1
|
|
- name: Div8
|
|
description: HSE divided by 8
|
|
value: 2
|
|
- name: Div16
|
|
description: HSE divided by 16
|
|
value: 3
|
|
enum/RTCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: DISABLE
|
|
description: No clock
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE oscillator clock used as RTC clock
|
|
value: 1
|
|
- name: LSI
|
|
description: LSI oscillator clock used as RTC clock
|
|
value: 2
|
|
- name: HSE
|
|
description: HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock
|
|
value: 3
|
|
enum/SW:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MSI
|
|
description: MSI oscillator used as system clock
|
|
value: 0
|
|
- name: HSI
|
|
description: HSI oscillator used as system clock
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE oscillator used as system clock
|
|
value: 2
|
|
- name: PLL1_R
|
|
description: PLL used as system clock
|
|
value: 3
|