87 lines
1.9 KiB
YAML
87 lines
1.9 KiB
YAML
block/IPCC:
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description: IPCC
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items:
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- name: CPU
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description: CPU specific registers
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array:
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len: 2
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stride: 16
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byte_offset: 0
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block: IPCC_CPU
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block/IPCC_CPU:
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description: IPCC
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items:
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- name: CR
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description: Control register CPUx
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byte_offset: 0
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fieldset: CxCR
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- name: MR
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description: Mask register CPUx
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byte_offset: 4
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fieldset: CxMR
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- name: SCR
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description: Status Set or Clear register CPUx
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byte_offset: 8
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access: Write
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fieldset: CxSCR
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- name: SR
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description: CPUx to CPUy status register
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byte_offset: 12
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access: Read
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fieldset: CxTOySR
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fieldset/CxCR:
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description: Control register CPUx
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fields:
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- name: RXOIE
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description: processor x Receive channel occupied interrupt enable
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bit_offset: 0
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bit_size: 1
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- name: TXFIE
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description: processor x Transmit channel free interrupt enable
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bit_offset: 16
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bit_size: 1
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fieldset/CxMR:
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description: Mask register CPUx
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fields:
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- name: CHOM
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description: processor x Receive channel y occupied interrupt enable
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bit_offset: 0
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bit_size: 1
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array:
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len: 6
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stride: 1
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- name: CHFM
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description: processor x Transmit channel y free interrupt mask
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bit_offset: 16
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bit_size: 1
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array:
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len: 6
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stride: 1
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fieldset/CxSCR:
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description: Status Set or Clear register CPUx
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fields:
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- name: CHC
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description: processor x Receive channel y status clear
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bit_offset: 0
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bit_size: 1
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array:
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len: 6
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stride: 1
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- name: CHS
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description: processor x Transmit channel y status set
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bit_offset: 16
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bit_size: 1
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array:
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len: 6
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stride: 1
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fieldset/CxTOySR:
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description: CPUx to CPUy status register
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fields:
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- name: CHF
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description: processor x transmit to process y Receive channel z status flag
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bit_offset: 0
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bit_size: 1
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array:
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len: 6
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stride: 1
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